1 /* Definitions to make GDB run on a mips box under 4.3bsd.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 Free Software Foundation, Inc.
5 Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
6 and by Alessandro Forin (af@cs.cmu.edu) at CMU..
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
28 #define GDB_MULTI_ARCH 1
38 #include "coff/sym.h" /* Needed for PDR below. */
39 #include "coff/symconst.h"
41 /* PC should be masked to remove possible MIPS16 flag */
42 #if !defined (GDB_TARGET_MASK_DISAS_PC)
43 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
45 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
46 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
49 /* The name of the usual type of MIPS processor that is in the target
52 #define DEFAULT_MIPS_TYPE "generic"
54 /* Return non-zero if PC points to an instruction which will cause a step
55 to execute both the instruction at PC and an instruction at PC+4. */
56 extern int mips_step_skips_delay (CORE_ADDR);
57 #define STEP_SKIPS_DELAY_P (1)
58 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
60 /* Say how long (ordinary) registers are. This is a piece of bogosity
61 used in push_word and a few other places; REGISTER_RAW_SIZE is the
62 real way to know how big a register is. */
64 #define REGISTER_SIZE 4
66 /* The size of a register. This is predefined in tm-mips64.h. We
67 can't use REGISTER_SIZE because that is used for various other
71 #define MIPS_REGSIZE 4
74 /* Number of machine registers */
80 /* Initializer for an array of names of registers.
81 There should be NUM_REGS strings in this initializer. */
83 #ifndef MIPS_REGISTER_NAMES
84 #define MIPS_REGISTER_NAMES \
85 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
86 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
87 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
88 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
89 "sr", "lo", "hi", "bad", "cause","pc", \
90 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
91 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
92 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
93 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
94 "fsr", "fir", "fp", "", \
95 "", "", "", "", "", "", "", "", \
96 "", "", "", "", "", "", "", "", \
100 /* Register numbers of various important registers.
101 Note that some of these values are "real" register numbers,
102 and correspond to the general registers of the machine,
103 and some are "phony" register numbers which are too large
104 to be actual register numbers as far as the user is concerned
105 but do serve to get the desired values when passed to read_register. */
107 #define ZERO_REGNUM 0 /* read-only register, always 0 */
108 #define V0_REGNUM 2 /* Function integer return value */
109 #define A0_REGNUM 4 /* Loc of first arg during a subr call */
110 #define T9_REGNUM 25 /* Contains address of callee in PIC */
111 #define SP_REGNUM 29 /* Contains address of top of stack */
112 #define RA_REGNUM 31 /* Contains return address value */
113 #define PS_REGNUM 32 /* Contains processor status */
114 #define HI_REGNUM 34 /* Multiple/divide temp */
115 #define LO_REGNUM 33 /* ... */
116 #define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
117 #define CAUSE_REGNUM 36 /* describes last exception */
118 #define PC_REGNUM 37 /* Contains program counter */
119 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
120 #define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */
121 #define FCRCS_REGNUM 70 /* FP control/status */
122 #define FCRIR_REGNUM 71 /* FP implementation/revision */
123 #define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
124 #define UNUSED_REGNUM 73 /* Never used, FIXME */
125 #define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */
126 #define PRID_REGNUM 89 /* Processor ID */
127 #define LAST_EMBED_REGNUM 89 /* Last one */
129 /* Total amount of space needed to store our copies of the machine's
130 register state, the array `registers'. */
132 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
134 /* Index within `registers' of the first byte of the space for
137 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
139 /* Return the GDB type object for the "standard" data type of data in
142 #ifndef REGISTER_VIRTUAL_TYPE
143 #define REGISTER_VIRTUAL_TYPE(N) \
144 (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
145 : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
146 : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
150 /* All mips targets store doubles in a register pair with the least
151 significant register in the lower numbered register.
152 If the target is big endian, double register values need conversion
153 between memory and register formats. */
155 extern void mips_register_convert_to_type (int regnum,
158 extern void mips_register_convert_from_type (int regnum,
162 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
163 mips_register_convert_to_type ((n), (type), (buffer))
165 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
166 mips_register_convert_from_type ((n), (type), (buffer))
169 /* Special symbol found in blocks associated with routines. We can hang
170 mips_extra_func_info_t's off of this. */
172 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
173 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
175 /* Specific information about a procedure.
176 This overlays the MIPS's PDR records,
177 mipsread.c (ab)uses this to save memory */
179 typedef struct mips_extra_func_info
181 long numargs; /* number of args to procedure (was iopt) */
182 bfd_vma high_addr; /* upper address bound */
183 long frame_adjust; /* offset of FP from SP (used on MIPS16) */
184 PDR pdr; /* Procedure descriptor record */
186 *mips_extra_func_info_t;
188 extern void mips_print_extra_frame_info (struct frame_info *frame);
189 #define PRINT_EXTRA_FRAME_INFO(fi) \
190 mips_print_extra_frame_info (fi)
192 /* It takes two values to specify a frame on the MIPS.
194 In fact, the *PC* is the primary value that sets up a frame. The
195 PC is looked up to see what function it's in; symbol information
196 from that function tells us which register is the frame pointer
197 base, and what offset from there is the "virtual frame pointer".
198 (This is usually an offset from SP.) On most non-MIPS machines,
199 the primary value is the SP, and the PC, if needed, disambiguates
200 multiple functions with the same SP. But on the MIPS we can't do
201 that since the PC is not stored in the same part of the frame every
202 time. This does not seem to be a very clever way to set up frames,
203 but there is nothing we can do about that. */
205 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
206 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
208 /* Select the default mips disassembler */
210 #define TM_PRINT_INSN_MACH 0
213 /* These are defined in mdebugread.c and are used in mips-tdep.c */
214 extern CORE_ADDR sigtramp_address, sigtramp_end;
215 extern void fixup_sigtramp (void);
217 /* Defined in mips-tdep.c and used in remote-mips.c */
218 extern char *mips_read_processor_type (void);
220 /* Functions for dealing with MIPS16 call and return stubs. */
221 #define IGNORE_HELPER_CALL(pc) mips_ignore_helper (pc)
222 extern int mips_ignore_helper (CORE_ADDR pc);
228 /* Definitions and declarations used by mips-tdep.c and remote-mips.c */
229 #define MIPS_INSTLEN 4 /* Length of an instruction */
230 #define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16 */
231 #define MIPS_NUMREGS 32 /* Number of integer or float registers */
232 typedef unsigned long t_inst; /* Integer big enough to hold an instruction */
234 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
235 macros to test, set, or clear bit 0 of addresses. */
236 #define IS_MIPS16_ADDR(addr) ((addr) & 1)
237 #define MAKE_MIPS16_ADDR(addr) ((addr) | 1)
238 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
240 #endif /* TM_MIPS_H */
242 /* Macros for setting and testing a bit in a minimal symbol that
243 marks it as 16-bit function. The MSB of the minimal symbol's
244 "info" field is used for this purpose. This field is already
245 being used to store the symbol size, so the assumption is
246 that the symbol size cannot exceed 2^31.
248 ELF_MAKE_MSYMBOL_SPECIAL
249 tests whether an ELF symbol is "special", i.e. refers
250 to a 16-bit function, and sets a "special" bit in a
251 minimal symbol to mark it as a 16-bit function
252 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
253 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
254 the "info" field with the "special" bit masked out
257 #define MSYMBOL_IS_SPECIAL(msym) \
258 mips_msymbol_is_special (msym)
259 #define MSYMBOL_SIZE(msym) \
260 mips_msymbol_size (msym)
261 struct minimal_symbol;
262 extern int mips_msymbol_is_special (struct minimal_symbol *msym);
263 extern long mips_msymbol_size (struct minimal_symbol *msym);
266 /* Command to set the processor type. */
267 extern void mips_set_processor_type_command (char *, int);
270 /* Single step based on where the current instruction will take us. */
271 extern void mips_software_single_step (enum target_signal, int);