1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002, 2003, 2007, 2008, 2009 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Forward declarations. */
26 /* Register numbers of various important registers. */
29 ARM_A1_REGNUM = 0, /* first integer-like argument */
30 ARM_A4_REGNUM = 3, /* last integer-like argument */
33 ARM_SP_REGNUM = 13, /* Contains address of top of stack */
34 ARM_LR_REGNUM = 14, /* address to return to from a function call */
35 ARM_PC_REGNUM = 15, /* Contains program counter */
36 ARM_F0_REGNUM = 16, /* first floating point register */
37 ARM_F3_REGNUM = 19, /* last floating point argument register */
38 ARM_F7_REGNUM = 23, /* last floating point register */
39 ARM_FPS_REGNUM = 24, /* floating point status register */
40 ARM_PS_REGNUM = 25, /* Contains processor status */
41 ARM_WR0_REGNUM, /* WMMX data registers. */
42 ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
43 ARM_WC0_REGNUM, /* WMMX control registers. */
44 ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
45 ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
46 ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
47 ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
48 ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
49 ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
50 ARM_D0_REGNUM, /* VFP double-precision registers. */
51 ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
55 /* Other useful registers. */
56 ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
57 THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
59 ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
60 ARM_NUM_FP_ARG_REGS = 4,
61 ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
64 /* Size of integer registers. */
65 #define INT_REGISTER_SIZE 4
67 /* Say how long FP registers are. Used for documentation purposes and
68 code readability in this header. IEEE extended doubles are 80
69 bits. DWORD aligned they use 96 bits. */
70 #define FP_REGISTER_SIZE 12
72 /* Number of machine registers. The only define actually required
73 is gdbarch_num_regs. The other definitions are used for documentation
74 purposes and code readability. */
75 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
76 (and called PS for processor status) so the status bits can be cleared
77 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
79 #define NUM_FREGS 8 /* Number of floating point registers. */
80 #define NUM_SREGS 2 /* Number of status registers. */
81 #define NUM_GREGS 16 /* Number of general purpose registers. */
84 /* Instruction condition field values. */
102 #define FLAG_N 0x80000000
103 #define FLAG_Z 0x40000000
104 #define FLAG_C 0x20000000
105 #define FLAG_V 0x10000000
109 /* Type of floating-point code in use by inferior. There are really 3 models
110 that are traditionally supported (plus the endianness issue), but gcc can
111 only generate 2 of those. The third is APCS_FLOAT, where arguments to
112 functions are passed in floating-point registers.
114 In addition to the traditional models, VFP adds two more.
116 If you update this enum, don't forget to update fp_model_strings in
121 ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
122 ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
123 ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
124 ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
125 ARM_FLOAT_VFP, /* Full VFP calling convention. */
126 ARM_FLOAT_LAST /* Keep at end. */
129 /* ABI used by the inferior. */
138 /* Convention for returning structures. */
142 pcc_struct_return, /* Return "short" structures in memory. */
143 reg_struct_return /* Return "short" structures in registers. */
146 /* Target-dependent structure in gdbarch. */
149 /* The ABI for this architecture. It should never be set to
151 enum arm_abi_kind arm_abi;
153 enum arm_float_model fp_model; /* Floating point calling conventions. */
155 int have_fpa_registers; /* Does the target report the FPA registers? */
156 int have_vfp_registers; /* Does the target report the VFP registers? */
157 int have_vfp_pseudos; /* Are we synthesizing the single precision
159 int have_neon_pseudos; /* Are we synthesizing the quad precision
160 NEON registers? Requires
162 int have_neon; /* Do we have a NEON unit? */
164 CORE_ADDR lowest_pc; /* Lowest address at which instructions
167 const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
168 int arm_breakpoint_size; /* And its size. */
169 const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */
170 int thumb_breakpoint_size; /* And its size. */
172 int jb_pc; /* Offset to PC value in jump buffer.
173 If this is negative, longjmp support
175 size_t jb_elt_size; /* And the size of each entry in the buf. */
177 /* Convention for returning structures. */
178 enum struct_return struct_return;
180 /* Cached core file helpers. */
181 struct regset *gregset, *fpregset;
183 /* ISA-specific data types. */
184 struct type *arm_ext_type;
185 struct type *neon_double_type;
186 struct type *neon_quad_type;
189 /* Structures used for displaced stepping. */
191 /* The maximum number of temporaries available for displaced instructions. */
192 #define DISPLACED_TEMPS 16
193 /* The maximum number of modified instructions generated for one single-stepped
194 instruction, including the breakpoint (usually at the end of the instruction
195 sequence) and any scratch words, etc. */
196 #define DISPLACED_MODIFIED_INSNS 8
198 struct displaced_step_closure
200 ULONGEST tmp[DISPLACED_TEMPS];
208 int rn; /* Writeback register. */
209 unsigned int immed : 1; /* Offset is immediate. */
210 unsigned int writeback : 1; /* Perform base-register writeback. */
211 unsigned int restore_r4 : 1; /* Used r4 as scratch. */
217 unsigned int link : 1;
218 unsigned int exchange : 1;
219 unsigned int cond : 4;
224 unsigned int regmask;
227 unsigned int load : 1;
228 unsigned int user : 1;
229 unsigned int increment : 1;
230 unsigned int before : 1;
231 unsigned int writeback : 1;
232 unsigned int cond : 4;
237 unsigned int immed : 1;
242 /* If non-NULL, override generic SVC handling (e.g. for a particular
244 int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
245 struct regcache *regs,
246 struct displaced_step_closure *dsc);
249 unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
252 CORE_ADDR scratch_base;
253 void (*cleanup) (struct gdbarch *, struct regcache *,
254 struct displaced_step_closure *);
257 /* Values for the WRITE_PC argument to displaced_write_reg. If the register
258 write may write to the PC, specifies the way the CPSR T bit, etc. is
259 modified by the instruction. */
271 arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
272 CORE_ADDR from, CORE_ADDR to,
273 struct regcache *regs,
274 struct displaced_step_closure *dsc);
276 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
277 CORE_ADDR to, struct displaced_step_closure *dsc);
279 displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
281 displaced_write_reg (struct regcache *regs,
282 struct displaced_step_closure *dsc, int regno,
283 ULONGEST val, enum pc_write_style write_pc);
285 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
286 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
287 int arm_software_single_step (struct frame_info *);
289 extern struct displaced_step_closure *
290 arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
292 extern void arm_displaced_step_fixup (struct gdbarch *,
293 struct displaced_step_closure *,
294 CORE_ADDR, CORE_ADDR, struct regcache *);
296 /* Functions exported from armbsd-tdep.h. */
298 /* Return the appropriate register set for the core section identified
299 by SECT_NAME and SECT_SIZE. */
301 extern const struct regset *
302 armbsd_regset_from_core_section (struct gdbarch *gdbarch,
303 const char *sect_name, size_t sect_size);
305 #endif /* arm-tdep.h */