1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002, 2003, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Forward declarations. */
26 /* Register numbers of various important registers. */
29 ARM_A1_REGNUM = 0, /* first integer-like argument */
30 ARM_A4_REGNUM = 3, /* last integer-like argument */
33 ARM_SP_REGNUM = 13, /* Contains address of top of stack */
34 ARM_LR_REGNUM = 14, /* address to return to from a function call */
35 ARM_PC_REGNUM = 15, /* Contains program counter */
36 ARM_F0_REGNUM = 16, /* first floating point register */
37 ARM_F3_REGNUM = 19, /* last floating point argument register */
38 ARM_F7_REGNUM = 23, /* last floating point register */
39 ARM_FPS_REGNUM = 24, /* floating point status register */
40 ARM_PS_REGNUM = 25, /* Contains processor status */
41 ARM_CPSR_REGNUM = ARM_PS_REGNUM,
42 ARM_WR0_REGNUM, /* WMMX data registers. */
43 ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
44 ARM_WC0_REGNUM, /* WMMX control registers. */
45 ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
46 ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
47 ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
48 ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
49 ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
50 ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
54 /* Other useful registers. */
55 ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
56 THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
58 ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
59 ARM_NUM_FP_ARG_REGS = 4,
60 ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
63 /* Size of integer registers. */
64 #define INT_REGISTER_SIZE 4
66 /* Say how long FP registers are. Used for documentation purposes and
67 code readability in this header. IEEE extended doubles are 80
68 bits. DWORD aligned they use 96 bits. */
69 #define FP_REGISTER_SIZE 12
71 /* Status registers are the same size as general purpose registers.
72 Used for documentation purposes and code readability in this
74 #define STATUS_REGISTER_SIZE 4
76 /* Number of machine registers. The only define actually required
77 is gdbarch_num_regs. The other definitions are used for documentation
78 purposes and code readability. */
79 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
80 (and called PS for processor status) so the status bits can be cleared
81 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
83 #define NUM_FREGS 8 /* Number of floating point registers. */
84 #define NUM_SREGS 2 /* Number of status registers. */
85 #define NUM_GREGS 16 /* Number of general purpose registers. */
88 /* Instruction condition field values. */
106 #define FLAG_N 0x80000000
107 #define FLAG_Z 0x40000000
108 #define FLAG_C 0x20000000
109 #define FLAG_V 0x10000000
113 /* Type of floating-point code in use by inferior. There are really 3 models
114 that are traditionally supported (plus the endianness issue), but gcc can
115 only generate 2 of those. The third is APCS_FLOAT, where arguments to
116 functions are passed in floating-point registers.
118 In addition to the traditional models, VFP adds two more.
120 If you update this enum, don't forget to update fp_model_strings in
125 ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
126 ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
127 ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
128 ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
129 ARM_FLOAT_VFP, /* Full VFP calling convention. */
130 ARM_FLOAT_LAST /* Keep at end. */
133 /* ABI used by the inferior. */
142 /* Convention for returning structures. */
146 pcc_struct_return, /* Return "short" structures in memory. */
147 reg_struct_return /* Return "short" structures in registers. */
150 /* Target-dependent structure in gdbarch. */
153 /* The ABI for this architecture. It should never be set to
155 enum arm_abi_kind arm_abi;
157 enum arm_float_model fp_model; /* Floating point calling conventions. */
159 int have_fpa_registers; /* Does the target report the FPA registers? */
161 CORE_ADDR lowest_pc; /* Lowest address at which instructions
164 const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
165 int arm_breakpoint_size; /* And its size. */
166 const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */
167 int thumb_breakpoint_size; /* And its size. */
169 int jb_pc; /* Offset to PC value in jump buffer.
170 If this is negative, longjmp support
172 size_t jb_elt_size; /* And the size of each entry in the buf. */
174 /* Convention for returning structures. */
175 enum struct_return struct_return;
177 /* Cached core file helpers. */
178 struct regset *gregset, *fpregset;
182 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
183 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
184 int arm_software_single_step (struct frame_info *);
186 /* Functions exported from armbsd-tdep.h. */
188 /* Return the appropriate register set for the core section identified
189 by SECT_NAME and SECT_SIZE. */
191 extern const struct regset *
192 armbsd_regset_from_core_section (struct gdbarch *gdbarch,
193 const char *sect_name, size_t sect_size);
195 #endif /* arm-tdep.h */