1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002-2019 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Forward declarations. */
26 struct arm_get_next_pcs;
27 struct gdb_get_next_pcs;
35 /* Number of machine registers. The only define actually required
36 is gdbarch_num_regs. The other definitions are used for documentation
37 purposes and code readability. */
38 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
39 (and called PS for processor status) so the status bits can be cleared
40 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
42 #define NUM_FREGS 8 /* Number of floating point registers. */
43 #define NUM_SREGS 2 /* Number of status registers. */
44 #define NUM_GREGS 16 /* Number of general purpose registers. */
48 /* Type of floating-point code in use by inferior. There are really 3 models
49 that are traditionally supported (plus the endianness issue), but gcc can
50 only generate 2 of those. The third is APCS_FLOAT, where arguments to
51 functions are passed in floating-point registers.
53 In addition to the traditional models, VFP adds two more.
55 If you update this enum, don't forget to update fp_model_strings in
60 ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
61 ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
62 ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
63 ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
64 ARM_FLOAT_VFP, /* Full VFP calling convention. */
65 ARM_FLOAT_LAST /* Keep at end. */
68 /* ABI used by the inferior. */
77 /* Convention for returning structures. */
81 pcc_struct_return, /* Return "short" structures in memory. */
82 reg_struct_return /* Return "short" structures in registers. */
85 /* Target-dependent structure in gdbarch. */
88 /* The ABI for this architecture. It should never be set to
90 enum arm_abi_kind arm_abi;
92 enum arm_float_model fp_model; /* Floating point calling conventions. */
94 int have_fpa_registers; /* Does the target report the FPA registers? */
95 int have_wmmx_registers; /* Does the target report the WMMX registers? */
96 /* The number of VFP registers reported by the target. It is zero
97 if VFP registers are not supported. */
98 int vfp_register_count;
99 int have_vfp_pseudos; /* Are we synthesizing the single precision
101 int have_neon_pseudos; /* Are we synthesizing the quad precision
102 NEON registers? Requires
104 int have_neon; /* Do we have a NEON unit? */
106 int is_m; /* Does the target follow the "M" profile. */
107 CORE_ADDR lowest_pc; /* Lowest address at which instructions
110 const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
111 int arm_breakpoint_size; /* And its size. */
112 const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */
113 int thumb_breakpoint_size; /* And its size. */
115 /* If the Thumb breakpoint is an undefined instruction (which is
116 affected by IT blocks) rather than a BKPT instruction (which is
117 not), then we need a 32-bit Thumb breakpoint to preserve the
118 instruction count in IT blocks. */
119 const gdb_byte *thumb2_breakpoint;
120 int thumb2_breakpoint_size;
122 int jb_pc; /* Offset to PC value in jump buffer.
123 If this is negative, longjmp support
125 size_t jb_elt_size; /* And the size of each entry in the buf. */
127 /* Convention for returning structures. */
128 enum struct_return struct_return;
130 /* ISA-specific data types. */
131 struct type *arm_ext_type;
132 struct type *neon_double_type;
133 struct type *neon_quad_type;
135 /* syscall record. */
136 int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
139 /* Structures used for displaced stepping. */
141 /* The maximum number of temporaries available for displaced instructions. */
142 #define DISPLACED_TEMPS 16
143 /* The maximum number of modified instructions generated for one single-stepped
144 instruction, including the breakpoint (usually at the end of the instruction
145 sequence) and any scratch words, etc. */
146 #define ARM_DISPLACED_MODIFIED_INSNS 8
148 struct arm_displaced_step_closure : public displaced_step_closure
150 ULONGEST tmp[DISPLACED_TEMPS];
158 int rn; /* Writeback register. */
159 unsigned int immed : 1; /* Offset is immediate. */
160 unsigned int writeback : 1; /* Perform base-register writeback. */
161 unsigned int restore_r4 : 1; /* Used r4 as scratch. */
167 unsigned int link : 1;
168 unsigned int exchange : 1;
169 unsigned int cond : 4;
174 unsigned int regmask;
177 unsigned int load : 1;
178 unsigned int user : 1;
179 unsigned int increment : 1;
180 unsigned int before : 1;
181 unsigned int writeback : 1;
182 unsigned int cond : 4;
187 unsigned int immed : 1;
192 /* If non-NULL, override generic SVC handling (e.g. for a particular
194 int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
195 arm_displaced_step_closure *dsc);
199 /* The size of original instruction, 2 or 4. */
200 unsigned int insn_size;
201 /* True if the original insn (and thus all replacement insns) are Thumb
203 unsigned int is_thumb;
205 /* The slots in the array is used in this way below,
206 - ARM instruction occupies one slot,
207 - Thumb 16 bit instruction occupies one slot,
208 - Thumb 32-bit instruction occupies *two* slots, one part for each. */
209 unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
212 CORE_ADDR scratch_base;
213 void (*cleanup) (struct gdbarch *, struct regcache *,
214 arm_displaced_step_closure *);
217 /* Values for the WRITE_PC argument to displaced_write_reg. If the register
218 write may write to the PC, specifies the way the CPSR T bit, etc. is
219 modified by the instruction. */
231 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
232 CORE_ADDR to, struct regcache *regs,
233 arm_displaced_step_closure *dsc);
235 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
236 CORE_ADDR to, arm_displaced_step_closure *dsc);
238 displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
241 displaced_write_reg (struct regcache *regs,
242 arm_displaced_step_closure *dsc, int regno,
243 ULONGEST val, enum pc_write_style write_pc);
245 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
247 ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
251 CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
254 int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
256 std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
257 int arm_is_thumb (struct regcache *regcache);
258 int arm_frame_is_thumb (struct frame_info *frame);
260 extern void arm_displaced_step_fixup (struct gdbarch *,
261 struct displaced_step_closure *,
262 CORE_ADDR, CORE_ADDR, struct regcache *);
264 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
265 extern int arm_psr_thumb_bit (struct gdbarch *);
267 /* Is the instruction at the given memory address a Thumb or ARM
269 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
271 extern int arm_process_record (struct gdbarch *gdbarch,
272 struct regcache *regcache, CORE_ADDR addr);
273 /* Functions exported from arm-bsd-tdep.h. */
275 /* Return the appropriate register set for the core section identified
276 by SECT_NAME and SECT_SIZE. */
279 armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
280 iterate_over_regset_sections_cb *cb,
282 const struct regcache *regcache);
284 /* Get the correct Arm target description with given FP hardware type. */
285 const target_desc *arm_read_description (arm_fp_type fp_type);
287 /* Get the correct Arm M-Profile target description with given hardware
289 const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);
291 #endif /* arm-tdep.h */