1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
48 #include "gdb/sim-arm.h"
51 #include "coff/internal.h"
54 #include "gdb_assert.h"
57 #include "features/arm-with-m.c"
61 /* Macros for setting and testing a bit in a minimal symbol that marks
62 it as Thumb function. The MSB of the minimal symbol's "info" field
63 is used for this purpose.
65 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
66 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
68 #define MSYMBOL_SET_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym) = 1
71 #define MSYMBOL_IS_SPECIAL(msym) \
72 MSYMBOL_TARGET_FLAG_1 (msym)
74 /* Per-objfile data used for mapping symbols. */
75 static const struct objfile_data *arm_objfile_data_key;
77 struct arm_mapping_symbol
82 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
83 DEF_VEC_O(arm_mapping_symbol_s);
85 struct arm_per_objfile
87 VEC(arm_mapping_symbol_s) **section_maps;
90 /* The list of available "set arm ..." and "show arm ..." commands. */
91 static struct cmd_list_element *setarmcmdlist = NULL;
92 static struct cmd_list_element *showarmcmdlist = NULL;
94 /* The type of floating-point to use. Keep this in sync with enum
95 arm_float_model, and the help string in _initialize_arm_tdep. */
96 static const char *fp_model_strings[] =
106 /* A variable that can be configured by the user. */
107 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
108 static const char *current_fp_model = "auto";
110 /* The ABI to use. Keep this in sync with arm_abi_kind. */
111 static const char *arm_abi_strings[] =
119 /* A variable that can be configured by the user. */
120 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
121 static const char *arm_abi_string = "auto";
123 /* The execution mode to assume. */
124 static const char *arm_mode_strings[] =
132 static const char *arm_fallback_mode_string = "auto";
133 static const char *arm_force_mode_string = "auto";
135 /* Number of different reg name sets (options). */
136 static int num_disassembly_options;
138 /* The standard register names, and all the valid aliases for them. Note
139 that `fp', `sp' and `pc' are not added in this alias list, because they
140 have been added as builtin user registers in
141 std-regs.c:_initialize_frame_reg. */
146 } arm_register_aliases[] = {
147 /* Basic register numbers. */
164 /* Synonyms (argument and variable registers). */
177 /* Other platform-specific names for r9. */
183 /* Names used by GCC (not listed in the ARM EABI). */
185 /* A special name from the older ATPCS. */
189 static const char *const arm_register_names[] =
190 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
191 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
192 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
193 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
194 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
195 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
196 "fps", "cpsr" }; /* 24 25 */
198 /* Valid register name styles. */
199 static const char **valid_disassembly_styles;
201 /* Disassembly style to use. Default to "std" register names. */
202 static const char *disassembly_style;
204 /* This is used to keep the bfd arch_info in sync with the disassembly
206 static void set_disassembly_style_sfunc(char *, int,
207 struct cmd_list_element *);
208 static void set_disassembly_style (void);
210 static void convert_from_extended (const struct floatformat *, const void *,
212 static void convert_to_extended (const struct floatformat *, void *,
215 static void arm_neon_quad_read (struct gdbarch *gdbarch,
216 struct regcache *regcache,
217 int regnum, gdb_byte *buf);
218 static void arm_neon_quad_write (struct gdbarch *gdbarch,
219 struct regcache *regcache,
220 int regnum, const gdb_byte *buf);
222 struct arm_prologue_cache
224 /* The stack pointer at the time this frame was created; i.e. the
225 caller's stack pointer when this function was called. It is used
226 to identify this frame. */
229 /* The frame base for this frame is just prev_sp - frame size.
230 FRAMESIZE is the distance from the frame pointer to the
231 initial stack pointer. */
235 /* The register used to hold the frame pointer for this frame. */
238 /* Saved register offsets. */
239 struct trad_frame_saved_reg *saved_regs;
242 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
243 CORE_ADDR prologue_start,
244 CORE_ADDR prologue_end,
245 struct arm_prologue_cache *cache);
247 /* Architecture version for displaced stepping. This effects the behaviour of
248 certain instructions, and really should not be hard-wired. */
250 #define DISPLACED_STEPPING_ARCH_VERSION 5
252 /* Addresses for calling Thumb functions have the bit 0 set.
253 Here are some macros to test, set, or clear bit 0 of addresses. */
254 #define IS_THUMB_ADDR(addr) ((addr) & 1)
255 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
256 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
258 /* Set to true if the 32-bit mode is in use. */
262 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
265 arm_psr_thumb_bit (struct gdbarch *gdbarch)
267 if (gdbarch_tdep (gdbarch)->is_m)
273 /* Determine if FRAME is executing in Thumb mode. */
276 arm_frame_is_thumb (struct frame_info *frame)
279 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
281 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
282 directly (from a signal frame or dummy frame) or by interpreting
283 the saved LR (from a prologue or DWARF frame). So consult it and
284 trust the unwinders. */
285 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
287 return (cpsr & t_bit) != 0;
290 /* Callback for VEC_lower_bound. */
293 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
294 const struct arm_mapping_symbol *rhs)
296 return lhs->value < rhs->value;
299 /* Search for the mapping symbol covering MEMADDR. If one is found,
300 return its type. Otherwise, return 0. If START is non-NULL,
301 set *START to the location of the mapping symbol. */
304 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
306 struct obj_section *sec;
308 /* If there are mapping symbols, consult them. */
309 sec = find_pc_section (memaddr);
312 struct arm_per_objfile *data;
313 VEC(arm_mapping_symbol_s) *map;
314 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
318 data = objfile_data (sec->objfile, arm_objfile_data_key);
321 map = data->section_maps[sec->the_bfd_section->index];
322 if (!VEC_empty (arm_mapping_symbol_s, map))
324 struct arm_mapping_symbol *map_sym;
326 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
327 arm_compare_mapping_symbols);
329 /* VEC_lower_bound finds the earliest ordered insertion
330 point. If the following symbol starts at this exact
331 address, we use that; otherwise, the preceding
332 mapping symbol covers this address. */
333 if (idx < VEC_length (arm_mapping_symbol_s, map))
335 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
336 if (map_sym->value == map_key.value)
339 *start = map_sym->value + obj_section_addr (sec);
340 return map_sym->type;
346 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
348 *start = map_sym->value + obj_section_addr (sec);
349 return map_sym->type;
358 static CORE_ADDR arm_get_next_pc_raw (struct frame_info *frame,
359 CORE_ADDR pc, int insert_bkpt);
361 /* Determine if the program counter specified in MEMADDR is in a Thumb
362 function. This function should be called for addresses unrelated to
363 any executing frame; otherwise, prefer arm_frame_is_thumb. */
366 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
368 struct obj_section *sec;
369 struct minimal_symbol *sym;
372 /* If bit 0 of the address is set, assume this is a Thumb address. */
373 if (IS_THUMB_ADDR (memaddr))
376 /* If the user wants to override the symbol table, let him. */
377 if (strcmp (arm_force_mode_string, "arm") == 0)
379 if (strcmp (arm_force_mode_string, "thumb") == 0)
382 /* ARM v6-M and v7-M are always in Thumb mode. */
383 if (gdbarch_tdep (gdbarch)->is_m)
386 /* If there are mapping symbols, consult them. */
387 type = arm_find_mapping_symbol (memaddr, NULL);
391 /* Thumb functions have a "special" bit set in minimal symbols. */
392 sym = lookup_minimal_symbol_by_pc (memaddr);
394 return (MSYMBOL_IS_SPECIAL (sym));
396 /* If the user wants to override the fallback mode, let them. */
397 if (strcmp (arm_fallback_mode_string, "arm") == 0)
399 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
402 /* If we couldn't find any symbol, but we're talking to a running
403 target, then trust the current value of $cpsr. This lets
404 "display/i $pc" always show the correct mode (though if there is
405 a symbol table we will not reach here, so it still may not be
406 displayed in the mode it will be executed).
408 As a further heuristic if we detect that we are doing a single-step we
409 see what state executing the current instruction ends up with us being
411 if (target_has_registers)
413 struct frame_info *current_frame = get_current_frame ();
414 CORE_ADDR current_pc = get_frame_pc (current_frame);
415 int is_thumb = arm_frame_is_thumb (current_frame);
417 if (memaddr == current_pc)
421 struct gdbarch *gdbarch = get_frame_arch (current_frame);
422 next_pc = arm_get_next_pc_raw (current_frame, current_pc, FALSE);
423 if (memaddr == gdbarch_addr_bits_remove (gdbarch, next_pc))
424 return IS_THUMB_ADDR (next_pc);
430 /* Otherwise we're out of luck; we assume ARM. */
434 /* Remove useless bits from addresses in a running program. */
436 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
439 return UNMAKE_THUMB_ADDR (val);
441 return (val & 0x03fffffc);
444 /* When reading symbols, we need to zap the low bit of the address,
445 which may be set to 1 for Thumb functions. */
447 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
452 /* Return 1 if PC is the start of a compiler helper function which
453 can be safely ignored during prologue skipping. */
455 skip_prologue_function (CORE_ADDR pc)
457 struct minimal_symbol *msym;
460 msym = lookup_minimal_symbol_by_pc (pc);
461 if (msym == NULL || SYMBOL_VALUE_ADDRESS (msym) != pc)
464 name = SYMBOL_LINKAGE_NAME (msym);
468 /* The GNU linker's Thumb call stub to foo is named
470 if (strstr (name, "_from_thumb") != NULL)
473 /* On soft-float targets, __truncdfsf2 is called to convert promoted
474 arguments to their argument types in non-prototyped
476 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
478 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
481 /* Internal functions related to thread-local storage. */
482 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
484 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
490 /* Support routines for instruction parsing. */
491 #define submask(x) ((1L << ((x) + 1)) - 1)
492 #define bit(obj,st) (((obj) >> (st)) & 1)
493 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
494 #define sbits(obj,st,fn) \
495 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
496 #define BranchDest(addr,instr) \
497 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
499 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
500 the first 16-bit of instruction, and INSN2 is the second 16-bit of
502 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
503 ((bits ((insn1), 0, 3) << 12) \
504 | (bits ((insn1), 10, 10) << 11) \
505 | (bits ((insn2), 12, 14) << 8) \
506 | bits ((insn2), 0, 7))
508 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
509 the 32-bit instruction. */
510 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
511 ((bits ((insn), 16, 19) << 12) \
512 | bits ((insn), 0, 11))
514 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
517 thumb_expand_immediate (unsigned int imm)
519 unsigned int count = imm >> 7;
527 return (imm & 0xff) | ((imm & 0xff) << 16);
529 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
531 return (imm & 0xff) | ((imm & 0xff) << 8)
532 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
535 return (0x80 | (imm & 0x7f)) << (32 - count);
538 /* Return 1 if the 16-bit Thumb instruction INST might change
539 control flow, 0 otherwise. */
542 thumb_instruction_changes_pc (unsigned short inst)
544 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
547 if ((inst & 0xf000) == 0xd000) /* conditional branch */
550 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
553 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
556 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
559 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
565 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
566 might change control flow, 0 otherwise. */
569 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
571 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
573 /* Branches and miscellaneous control instructions. */
575 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
580 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
582 /* SUBS PC, LR, #imm8. */
585 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
587 /* Conditional branch. */
594 if ((inst1 & 0xfe50) == 0xe810)
596 /* Load multiple or RFE. */
598 if (bit (inst1, 7) && !bit (inst1, 8))
604 else if (!bit (inst1, 7) && bit (inst1, 8))
610 else if (bit (inst1, 7) && bit (inst1, 8))
615 else if (!bit (inst1, 7) && !bit (inst1, 8))
624 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
626 /* MOV PC or MOVS PC. */
630 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
633 if (bits (inst1, 0, 3) == 15)
639 if ((inst2 & 0x0fc0) == 0x0000)
645 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
651 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
660 /* Analyze a Thumb prologue, looking for a recognizable stack frame
661 and frame pointer. Scan until we encounter a store that could
662 clobber the stack frame unexpectedly, or an unknown instruction.
663 Return the last address which is definitely safe to skip for an
664 initial breakpoint. */
667 thumb_analyze_prologue (struct gdbarch *gdbarch,
668 CORE_ADDR start, CORE_ADDR limit,
669 struct arm_prologue_cache *cache)
671 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
672 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
675 struct pv_area *stack;
676 struct cleanup *back_to;
678 CORE_ADDR unrecognized_pc = 0;
680 for (i = 0; i < 16; i++)
681 regs[i] = pv_register (i, 0);
682 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
683 back_to = make_cleanup_free_pv_area (stack);
685 while (start < limit)
689 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
691 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
696 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
699 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
700 whether to save LR (R14). */
701 mask = (insn & 0xff) | ((insn & 0x100) << 6);
703 /* Calculate offsets of saved R0-R7 and LR. */
704 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
705 if (mask & (1 << regno))
707 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
709 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
712 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
715 offset = (insn & 0x7f) << 2; /* get scaled offset */
716 if (insn & 0x80) /* Check for SUB. */
717 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
720 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
723 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
724 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
726 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
727 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
728 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
730 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
731 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
732 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
734 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
735 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
736 && pv_is_constant (regs[bits (insn, 3, 5)]))
737 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
738 regs[bits (insn, 6, 8)]);
739 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
740 && pv_is_constant (regs[bits (insn, 3, 6)]))
742 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
743 int rm = bits (insn, 3, 6);
744 regs[rd] = pv_add (regs[rd], regs[rm]);
746 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
748 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
749 int src_reg = (insn & 0x78) >> 3;
750 regs[dst_reg] = regs[src_reg];
752 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
754 /* Handle stores to the stack. Normally pushes are used,
755 but with GCC -mtpcs-frame, there may be other stores
756 in the prologue to create the frame. */
757 int regno = (insn >> 8) & 0x7;
760 offset = (insn & 0xff) << 2;
761 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
763 if (pv_area_store_would_trash (stack, addr))
766 pv_area_store (stack, addr, 4, regs[regno]);
768 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
770 int rd = bits (insn, 0, 2);
771 int rn = bits (insn, 3, 5);
774 offset = bits (insn, 6, 10) << 2;
775 addr = pv_add_constant (regs[rn], offset);
777 if (pv_area_store_would_trash (stack, addr))
780 pv_area_store (stack, addr, 4, regs[rd]);
782 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
783 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
784 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
785 /* Ignore stores of argument registers to the stack. */
787 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
788 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
789 /* Ignore block loads from the stack, potentially copying
790 parameters from memory. */
792 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
793 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
794 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
795 /* Similarly ignore single loads from the stack. */
797 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
798 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
799 /* Skip register copies, i.e. saves to another register
800 instead of the stack. */
802 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
803 /* Recognize constant loads; even with small stacks these are necessary
805 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
806 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
808 /* Constant pool loads, for the same reason. */
809 unsigned int constant;
812 loc = start + 4 + bits (insn, 0, 7) * 4;
813 constant = read_memory_unsigned_integer (loc, 4, byte_order);
814 regs[bits (insn, 8, 10)] = pv_constant (constant);
816 else if ((insn & 0xe000) == 0xe000)
818 unsigned short inst2;
820 inst2 = read_memory_unsigned_integer (start + 2, 2,
821 byte_order_for_code);
823 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
825 /* BL, BLX. Allow some special function calls when
826 skipping the prologue; GCC generates these before
827 storing arguments to the stack. */
829 int j1, j2, imm1, imm2;
831 imm1 = sbits (insn, 0, 10);
832 imm2 = bits (inst2, 0, 10);
833 j1 = bit (inst2, 13);
834 j2 = bit (inst2, 11);
836 offset = ((imm1 << 12) + (imm2 << 1));
837 offset ^= ((!j2) << 22) | ((!j1) << 23);
839 nextpc = start + 4 + offset;
840 /* For BLX make sure to clear the low bits. */
841 if (bit (inst2, 12) == 0)
842 nextpc = nextpc & 0xfffffffc;
844 if (!skip_prologue_function (nextpc))
848 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, { registers } */
849 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
851 pv_t addr = regs[bits (insn, 0, 3)];
854 if (pv_area_store_would_trash (stack, addr))
857 /* Calculate offsets of saved registers. */
858 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
859 if (inst2 & (1 << regno))
861 addr = pv_add_constant (addr, -4);
862 pv_area_store (stack, addr, 4, regs[regno]);
866 regs[bits (insn, 0, 3)] = addr;
869 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, [Rn, #+/-imm]{!} */
870 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
872 int regno1 = bits (inst2, 12, 15);
873 int regno2 = bits (inst2, 8, 11);
874 pv_t addr = regs[bits (insn, 0, 3)];
876 offset = inst2 & 0xff;
878 addr = pv_add_constant (addr, offset);
880 addr = pv_add_constant (addr, -offset);
882 if (pv_area_store_would_trash (stack, addr))
885 pv_area_store (stack, addr, 4, regs[regno1]);
886 pv_area_store (stack, pv_add_constant (addr, 4),
890 regs[bits (insn, 0, 3)] = addr;
893 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
894 && (inst2 & 0x0c00) == 0x0c00
895 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
897 int regno = bits (inst2, 12, 15);
898 pv_t addr = regs[bits (insn, 0, 3)];
900 offset = inst2 & 0xff;
902 addr = pv_add_constant (addr, offset);
904 addr = pv_add_constant (addr, -offset);
906 if (pv_area_store_would_trash (stack, addr))
909 pv_area_store (stack, addr, 4, regs[regno]);
912 regs[bits (insn, 0, 3)] = addr;
915 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
916 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
918 int regno = bits (inst2, 12, 15);
921 offset = inst2 & 0xfff;
922 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
924 if (pv_area_store_would_trash (stack, addr))
927 pv_area_store (stack, addr, 4, regs[regno]);
930 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
931 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
932 /* Ignore stores of argument registers to the stack. */
935 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
936 && (inst2 & 0x0d00) == 0x0c00
937 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
938 /* Ignore stores of argument registers to the stack. */
941 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
942 && (inst2 & 0x8000) == 0x0000
943 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
944 /* Ignore block loads from the stack, potentially copying
945 parameters from memory. */
948 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, [Rn, #+/-imm] */
949 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
950 /* Similarly ignore dual loads from the stack. */
953 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
954 && (inst2 & 0x0d00) == 0x0c00
955 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
956 /* Similarly ignore single loads from the stack. */
959 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
960 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
961 /* Similarly ignore single loads from the stack. */
964 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
965 && (inst2 & 0x8000) == 0x0000)
967 unsigned int imm = ((bits (insn, 10, 10) << 11)
968 | (bits (inst2, 12, 14) << 8)
969 | bits (inst2, 0, 7));
971 regs[bits (inst2, 8, 11)]
972 = pv_add_constant (regs[bits (insn, 0, 3)],
973 thumb_expand_immediate (imm));
976 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
977 && (inst2 & 0x8000) == 0x0000)
979 unsigned int imm = ((bits (insn, 10, 10) << 11)
980 | (bits (inst2, 12, 14) << 8)
981 | bits (inst2, 0, 7));
983 regs[bits (inst2, 8, 11)]
984 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
987 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
988 && (inst2 & 0x8000) == 0x0000)
990 unsigned int imm = ((bits (insn, 10, 10) << 11)
991 | (bits (inst2, 12, 14) << 8)
992 | bits (inst2, 0, 7));
994 regs[bits (inst2, 8, 11)]
995 = pv_add_constant (regs[bits (insn, 0, 3)],
996 - (CORE_ADDR) thumb_expand_immediate (imm));
999 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1000 && (inst2 & 0x8000) == 0x0000)
1002 unsigned int imm = ((bits (insn, 10, 10) << 11)
1003 | (bits (inst2, 12, 14) << 8)
1004 | bits (inst2, 0, 7));
1006 regs[bits (inst2, 8, 11)]
1007 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1010 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1012 unsigned int imm = ((bits (insn, 10, 10) << 11)
1013 | (bits (inst2, 12, 14) << 8)
1014 | bits (inst2, 0, 7));
1016 regs[bits (inst2, 8, 11)]
1017 = pv_constant (thumb_expand_immediate (imm));
1020 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1023 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1025 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1028 else if (insn == 0xea5f /* mov.w Rd,Rm */
1029 && (inst2 & 0xf0f0) == 0)
1031 int dst_reg = (inst2 & 0x0f00) >> 8;
1032 int src_reg = inst2 & 0xf;
1033 regs[dst_reg] = regs[src_reg];
1036 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1038 /* Constant pool loads. */
1039 unsigned int constant;
1042 offset = bits (insn, 0, 11);
1044 loc = start + 4 + offset;
1046 loc = start + 4 - offset;
1048 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1049 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1052 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1054 /* Constant pool loads. */
1055 unsigned int constant;
1058 offset = bits (insn, 0, 7) << 2;
1060 loc = start + 4 + offset;
1062 loc = start + 4 - offset;
1064 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1065 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1067 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1068 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1071 else if (thumb2_instruction_changes_pc (insn, inst2))
1073 /* Don't scan past anything that might change control flow. */
1078 /* The optimizer might shove anything into the prologue,
1079 so we just skip what we don't recognize. */
1080 unrecognized_pc = start;
1085 else if (thumb_instruction_changes_pc (insn))
1087 /* Don't scan past anything that might change control flow. */
1092 /* The optimizer might shove anything into the prologue,
1093 so we just skip what we don't recognize. */
1094 unrecognized_pc = start;
1101 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1102 paddress (gdbarch, start));
1104 if (unrecognized_pc == 0)
1105 unrecognized_pc = start;
1109 do_cleanups (back_to);
1110 return unrecognized_pc;
1113 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1115 /* Frame pointer is fp. Frame size is constant. */
1116 cache->framereg = ARM_FP_REGNUM;
1117 cache->framesize = -regs[ARM_FP_REGNUM].k;
1119 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1121 /* Frame pointer is r7. Frame size is constant. */
1122 cache->framereg = THUMB_FP_REGNUM;
1123 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1125 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1127 /* Try the stack pointer... this is a bit desperate. */
1128 cache->framereg = ARM_SP_REGNUM;
1129 cache->framesize = -regs[ARM_SP_REGNUM].k;
1133 /* We're just out of luck. We don't know where the frame is. */
1134 cache->framereg = -1;
1135 cache->framesize = 0;
1138 for (i = 0; i < 16; i++)
1139 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1140 cache->saved_regs[i].addr = offset;
1142 do_cleanups (back_to);
1143 return unrecognized_pc;
1147 /* Try to analyze the instructions starting from PC, which load symbol
1148 __stack_chk_guard. Return the address of instruction after loading this
1149 symbol, set the dest register number to *BASEREG, and set the size of
1150 instructions for loading symbol in OFFSET. Return 0 if instructions are
1154 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1155 unsigned int *destreg, int *offset)
1157 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1158 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1159 unsigned int low, high, address;
1164 unsigned short insn1
1165 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1167 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1169 *destreg = bits (insn1, 8, 10);
1171 address = bits (insn1, 0, 7);
1173 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1175 unsigned short insn2
1176 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1178 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1181 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1183 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1185 /* movt Rd, #const */
1186 if ((insn1 & 0xfbc0) == 0xf2c0)
1188 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1189 *destreg = bits (insn2, 8, 11);
1191 address = (high << 16 | low);
1198 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1200 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1202 address = bits (insn, 0, 11);
1203 *destreg = bits (insn, 12, 15);
1206 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1208 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1211 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1213 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1214 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1216 address = (high << 16 | low);
1217 *destreg = bits (insn, 12, 15);
1225 /* Try to skip a sequence of instructions used for stack protector. If PC
1226 points to the first instruction of this sequence, return the address of first
1227 instruction after this sequence, otherwise, return original PC.
1229 On arm, this sequence of instructions is composed of mainly three steps,
1230 Step 1: load symbol __stack_chk_guard,
1231 Step 2: load from address of __stack_chk_guard,
1232 Step 3: store it to somewhere else.
1234 Usually, instructions on step 2 and step 3 are the same on various ARM
1235 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1236 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1237 instructions in step 1 vary from different ARM architectures. On ARMv7,
1240 movw Rn, #:lower16:__stack_chk_guard
1241 movt Rn, #:upper16:__stack_chk_guard
1248 .word __stack_chk_guard
1250 Since ldr/str is a very popular instruction, we can't use them as
1251 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1252 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1253 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1256 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1258 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1259 unsigned int address, basereg;
1260 struct minimal_symbol *stack_chk_guard;
1262 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1265 /* Try to parse the instructions in Step 1. */
1266 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1271 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1272 /* If name of symbol doesn't start with '__stack_chk_guard', this
1273 instruction sequence is not for stack protector. If symbol is
1274 removed, we conservatively think this sequence is for stack protector. */
1276 && strcmp (SYMBOL_LINKAGE_NAME(stack_chk_guard), "__stack_chk_guard"))
1281 unsigned int destreg;
1283 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1285 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1286 if ((insn & 0xf800) != 0x6800)
1288 if (bits (insn, 3, 5) != basereg)
1290 destreg = bits (insn, 0, 2);
1292 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1293 byte_order_for_code);
1294 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1295 if ((insn & 0xf800) != 0x6000)
1297 if (destreg != bits (insn, 0, 2))
1302 unsigned int destreg;
1304 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1306 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1307 if ((insn & 0x0e500000) != 0x04100000)
1309 if (bits (insn, 16, 19) != basereg)
1311 destreg = bits (insn, 12, 15);
1312 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1313 insn = read_memory_unsigned_integer (pc + offset + 4,
1314 4, byte_order_for_code);
1315 if ((insn & 0x0e500000) != 0x04000000)
1317 if (bits (insn, 12, 15) != destreg)
1320 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1323 return pc + offset + 4;
1325 return pc + offset + 8;
1328 /* Advance the PC across any function entry prologue instructions to
1329 reach some "real" code.
1331 The APCS (ARM Procedure Call Standard) defines the following
1335 [stmfd sp!, {a1,a2,a3,a4}]
1336 stmfd sp!, {...,fp,ip,lr,pc}
1337 [stfe f7, [sp, #-12]!]
1338 [stfe f6, [sp, #-12]!]
1339 [stfe f5, [sp, #-12]!]
1340 [stfe f4, [sp, #-12]!]
1341 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
1344 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1346 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1349 CORE_ADDR func_addr, limit_pc;
1350 struct symtab_and_line sal;
1352 /* See if we can determine the end of the prologue via the symbol table.
1353 If so, then return either PC, or the PC after the prologue, whichever
1355 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1357 CORE_ADDR post_prologue_pc
1358 = skip_prologue_using_sal (gdbarch, func_addr);
1359 struct symtab *s = find_pc_symtab (func_addr);
1361 if (post_prologue_pc)
1363 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1366 /* GCC always emits a line note before the prologue and another
1367 one after, even if the two are at the same address or on the
1368 same line. Take advantage of this so that we do not need to
1369 know every instruction that might appear in the prologue. We
1370 will have producer information for most binaries; if it is
1371 missing (e.g. for -gstabs), assuming the GNU tools. */
1372 if (post_prologue_pc
1374 || s->producer == NULL
1375 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0))
1376 return post_prologue_pc;
1378 if (post_prologue_pc != 0)
1380 CORE_ADDR analyzed_limit;
1382 /* For non-GCC compilers, make sure the entire line is an
1383 acceptable prologue; GDB will round this function's
1384 return value up to the end of the following line so we
1385 can not skip just part of a line (and we do not want to).
1387 RealView does not treat the prologue specially, but does
1388 associate prologue code with the opening brace; so this
1389 lets us skip the first line if we think it is the opening
1391 if (arm_pc_is_thumb (gdbarch, func_addr))
1392 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1393 post_prologue_pc, NULL);
1395 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1396 post_prologue_pc, NULL);
1398 if (analyzed_limit != post_prologue_pc)
1401 return post_prologue_pc;
1405 /* Can't determine prologue from the symbol table, need to examine
1408 /* Find an upper limit on the function prologue using the debug
1409 information. If the debug information could not be used to provide
1410 that bound, then use an arbitrary large number as the upper bound. */
1411 /* Like arm_scan_prologue, stop no later than pc + 64. */
1412 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1414 limit_pc = pc + 64; /* Magic. */
1417 /* Check if this is Thumb code. */
1418 if (arm_pc_is_thumb (gdbarch, pc))
1419 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1421 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1423 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1425 /* "mov ip, sp" is no longer a required part of the prologue. */
1426 if (inst == 0xe1a0c00d) /* mov ip, sp */
1429 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1432 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1435 /* Some prologues begin with "str lr, [sp, #-4]!". */
1436 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1439 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1442 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1445 /* Any insns after this point may float into the code, if it makes
1446 for better instruction scheduling, so we skip them only if we
1447 find them, but still consider the function to be frame-ful. */
1449 /* We may have either one sfmfd instruction here, or several stfe
1450 insns, depending on the version of floating point code we
1452 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1455 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1458 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1461 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1464 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1465 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1466 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1469 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1470 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1471 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1474 /* Un-recognized instruction; stop scanning. */
1478 return skip_pc; /* End of prologue */
1482 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1483 This function decodes a Thumb function prologue to determine:
1484 1) the size of the stack frame
1485 2) which registers are saved on it
1486 3) the offsets of saved regs
1487 4) the offset from the stack pointer to the frame pointer
1489 A typical Thumb function prologue would create this stack frame
1490 (offsets relative to FP)
1491 old SP -> 24 stack parameters
1494 R7 -> 0 local variables (16 bytes)
1495 SP -> -12 additional stack space (12 bytes)
1496 The frame size would thus be 36 bytes, and the frame offset would be
1497 12 bytes. The frame register is R7.
1499 The comments for thumb_skip_prolog() describe the algorithm we use
1500 to detect the end of the prolog. */
1504 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1505 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1507 CORE_ADDR prologue_start;
1508 CORE_ADDR prologue_end;
1509 CORE_ADDR current_pc;
1511 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1514 /* See comment in arm_scan_prologue for an explanation of
1516 if (prologue_end > prologue_start + 64)
1518 prologue_end = prologue_start + 64;
1522 /* We're in the boondocks: we have no idea where the start of the
1526 prologue_end = min (prologue_end, prev_pc);
1528 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1531 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1534 arm_instruction_changes_pc (uint32_t this_instr)
1536 if (bits (this_instr, 28, 31) == INST_NV)
1537 /* Unconditional instructions. */
1538 switch (bits (this_instr, 24, 27))
1542 /* Branch with Link and change to Thumb. */
1547 /* Coprocessor register transfer. */
1548 if (bits (this_instr, 12, 15) == 15)
1549 error (_("Invalid update to pc in instruction"));
1555 switch (bits (this_instr, 25, 27))
1558 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1560 /* Multiplies and extra load/stores. */
1561 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1562 /* Neither multiplies nor extension load/stores are allowed
1566 /* Otherwise, miscellaneous instructions. */
1568 /* BX <reg>, BXJ <reg>, BLX <reg> */
1569 if (bits (this_instr, 4, 27) == 0x12fff1
1570 || bits (this_instr, 4, 27) == 0x12fff2
1571 || bits (this_instr, 4, 27) == 0x12fff3)
1574 /* Other miscellaneous instructions are unpredictable if they
1578 /* Data processing instruction. Fall through. */
1581 if (bits (this_instr, 12, 15) == 15)
1588 /* Media instructions and architecturally undefined instructions. */
1589 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1593 if (bit (this_instr, 20) == 0)
1597 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1603 /* Load/store multiple. */
1604 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1610 /* Branch and branch with link. */
1615 /* Coprocessor transfers or SWIs can not affect PC. */
1619 internal_error (__FILE__, __LINE__, "bad value in switch");
1623 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1624 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1625 fill it in. Return the first address not recognized as a prologue
1628 We recognize all the instructions typically found in ARM prologues,
1629 plus harmless instructions which can be skipped (either for analysis
1630 purposes, or a more restrictive set that can be skipped when finding
1631 the end of the prologue). */
1634 arm_analyze_prologue (struct gdbarch *gdbarch,
1635 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1636 struct arm_prologue_cache *cache)
1638 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1639 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1641 CORE_ADDR offset, current_pc;
1642 pv_t regs[ARM_FPS_REGNUM];
1643 struct pv_area *stack;
1644 struct cleanup *back_to;
1645 int framereg, framesize;
1646 CORE_ADDR unrecognized_pc = 0;
1648 /* Search the prologue looking for instructions that set up the
1649 frame pointer, adjust the stack pointer, and save registers.
1651 Be careful, however, and if it doesn't look like a prologue,
1652 don't try to scan it. If, for instance, a frameless function
1653 begins with stmfd sp!, then we will tell ourselves there is
1654 a frame, which will confuse stack traceback, as well as "finish"
1655 and other operations that rely on a knowledge of the stack
1658 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1659 regs[regno] = pv_register (regno, 0);
1660 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1661 back_to = make_cleanup_free_pv_area (stack);
1663 for (current_pc = prologue_start;
1664 current_pc < prologue_end;
1668 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1670 if (insn == 0xe1a0c00d) /* mov ip, sp */
1672 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1675 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1676 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1678 unsigned imm = insn & 0xff; /* immediate value */
1679 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1680 int rd = bits (insn, 12, 15);
1681 imm = (imm >> rot) | (imm << (32 - rot));
1682 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1685 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1686 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1688 unsigned imm = insn & 0xff; /* immediate value */
1689 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1690 int rd = bits (insn, 12, 15);
1691 imm = (imm >> rot) | (imm << (32 - rot));
1692 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1695 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */
1697 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1699 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1700 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1701 regs[bits (insn, 12, 15)]);
1704 else if ((insn & 0xffff0000) == 0xe92d0000)
1705 /* stmfd sp!, {..., fp, ip, lr, pc}
1707 stmfd sp!, {a1, a2, a3, a4} */
1709 int mask = insn & 0xffff;
1711 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1714 /* Calculate offsets of saved registers. */
1715 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1716 if (mask & (1 << regno))
1718 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1719 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1722 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1723 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1724 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1726 /* No need to add this to saved_regs -- it's just an arg reg. */
1729 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1730 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1731 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1733 /* No need to add this to saved_regs -- it's just an arg reg. */
1736 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */
1737 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1739 /* No need to add this to saved_regs -- it's just arg regs. */
1742 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1744 unsigned imm = insn & 0xff; /* immediate value */
1745 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1746 imm = (imm >> rot) | (imm << (32 - rot));
1747 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1749 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1751 unsigned imm = insn & 0xff; /* immediate value */
1752 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1753 imm = (imm >> rot) | (imm << (32 - rot));
1754 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1756 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
1757 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1759 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1762 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1763 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1764 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1766 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
1767 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1769 int n_saved_fp_regs;
1770 unsigned int fp_start_reg, fp_bound_reg;
1772 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1775 if ((insn & 0x800) == 0x800) /* N0 is set */
1777 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1778 n_saved_fp_regs = 3;
1780 n_saved_fp_regs = 1;
1784 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1785 n_saved_fp_regs = 2;
1787 n_saved_fp_regs = 4;
1790 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1791 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1792 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1794 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1795 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1796 regs[fp_start_reg++]);
1799 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1801 /* Allow some special function calls when skipping the
1802 prologue; GCC generates these before storing arguments to
1804 CORE_ADDR dest = BranchDest (current_pc, insn);
1806 if (skip_prologue_function (dest))
1811 else if ((insn & 0xf0000000) != 0xe0000000)
1812 break; /* Condition not true, exit early */
1813 else if (arm_instruction_changes_pc (insn))
1814 /* Don't scan past anything that might change control flow. */
1816 else if ((insn & 0xfe500000) == 0xe8100000) /* ldm */
1818 /* Ignore block loads from the stack, potentially copying
1819 parameters from memory. */
1820 if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1825 else if ((insn & 0xfc500000) == 0xe4100000)
1827 /* Similarly ignore single loads from the stack. */
1828 if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1833 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1834 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1835 register instead of the stack. */
1839 /* The optimizer might shove anything into the prologue,
1840 so we just skip what we don't recognize. */
1841 unrecognized_pc = current_pc;
1846 if (unrecognized_pc == 0)
1847 unrecognized_pc = current_pc;
1849 /* The frame size is just the distance from the frame register
1850 to the original stack pointer. */
1851 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1853 /* Frame pointer is fp. */
1854 framereg = ARM_FP_REGNUM;
1855 framesize = -regs[ARM_FP_REGNUM].k;
1857 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1859 /* Try the stack pointer... this is a bit desperate. */
1860 framereg = ARM_SP_REGNUM;
1861 framesize = -regs[ARM_SP_REGNUM].k;
1865 /* We're just out of luck. We don't know where the frame is. */
1872 cache->framereg = framereg;
1873 cache->framesize = framesize;
1875 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1876 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1877 cache->saved_regs[regno].addr = offset;
1881 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1882 paddress (gdbarch, unrecognized_pc));
1884 do_cleanups (back_to);
1885 return unrecognized_pc;
1889 arm_scan_prologue (struct frame_info *this_frame,
1890 struct arm_prologue_cache *cache)
1892 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1893 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1895 CORE_ADDR prologue_start, prologue_end, current_pc;
1896 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1897 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1898 pv_t regs[ARM_FPS_REGNUM];
1899 struct pv_area *stack;
1900 struct cleanup *back_to;
1903 /* Assume there is no frame until proven otherwise. */
1904 cache->framereg = ARM_SP_REGNUM;
1905 cache->framesize = 0;
1907 /* Check for Thumb prologue. */
1908 if (arm_frame_is_thumb (this_frame))
1910 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1914 /* Find the function prologue. If we can't find the function in
1915 the symbol table, peek in the stack frame to find the PC. */
1916 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1919 /* One way to find the end of the prologue (which works well
1920 for unoptimized code) is to do the following:
1922 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1925 prologue_end = prev_pc;
1926 else if (sal.end < prologue_end)
1927 prologue_end = sal.end;
1929 This mechanism is very accurate so long as the optimizer
1930 doesn't move any instructions from the function body into the
1931 prologue. If this happens, sal.end will be the last
1932 instruction in the first hunk of prologue code just before
1933 the first instruction that the scheduler has moved from
1934 the body to the prologue.
1936 In order to make sure that we scan all of the prologue
1937 instructions, we use a slightly less accurate mechanism which
1938 may scan more than necessary. To help compensate for this
1939 lack of accuracy, the prologue scanning loop below contains
1940 several clauses which'll cause the loop to terminate early if
1941 an implausible prologue instruction is encountered.
1947 is a suitable endpoint since it accounts for the largest
1948 possible prologue plus up to five instructions inserted by
1951 if (prologue_end > prologue_start + 64)
1953 prologue_end = prologue_start + 64; /* See above. */
1958 /* We have no symbol information. Our only option is to assume this
1959 function has a standard stack frame and the normal frame register.
1960 Then, we can find the value of our frame pointer on entrance to
1961 the callee (or at the present moment if this is the innermost frame).
1962 The value stored there should be the address of the stmfd + 8. */
1963 CORE_ADDR frame_loc;
1964 LONGEST return_value;
1966 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1967 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1971 prologue_start = gdbarch_addr_bits_remove
1972 (gdbarch, return_value) - 8;
1973 prologue_end = prologue_start + 64; /* See above. */
1977 if (prev_pc < prologue_end)
1978 prologue_end = prev_pc;
1980 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1983 static struct arm_prologue_cache *
1984 arm_make_prologue_cache (struct frame_info *this_frame)
1987 struct arm_prologue_cache *cache;
1988 CORE_ADDR unwound_fp;
1990 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1991 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1993 arm_scan_prologue (this_frame, cache);
1995 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1996 if (unwound_fp == 0)
1999 cache->prev_sp = unwound_fp + cache->framesize;
2001 /* Calculate actual addresses of saved registers using offsets
2002 determined by arm_scan_prologue. */
2003 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2004 if (trad_frame_addr_p (cache->saved_regs, reg))
2005 cache->saved_regs[reg].addr += cache->prev_sp;
2010 /* Our frame ID for a normal frame is the current function's starting PC
2011 and the caller's SP when we were called. */
2014 arm_prologue_this_id (struct frame_info *this_frame,
2016 struct frame_id *this_id)
2018 struct arm_prologue_cache *cache;
2022 if (*this_cache == NULL)
2023 *this_cache = arm_make_prologue_cache (this_frame);
2024 cache = *this_cache;
2026 /* This is meant to halt the backtrace at "_start". */
2027 pc = get_frame_pc (this_frame);
2028 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2031 /* If we've hit a wall, stop. */
2032 if (cache->prev_sp == 0)
2035 func = get_frame_func (this_frame);
2036 id = frame_id_build (cache->prev_sp, func);
2040 static struct value *
2041 arm_prologue_prev_register (struct frame_info *this_frame,
2045 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2046 struct arm_prologue_cache *cache;
2048 if (*this_cache == NULL)
2049 *this_cache = arm_make_prologue_cache (this_frame);
2050 cache = *this_cache;
2052 /* If we are asked to unwind the PC, then we need to return the LR
2053 instead. The prologue may save PC, but it will point into this
2054 frame's prologue, not the next frame's resume location. Also
2055 strip the saved T bit. A valid LR may have the low bit set, but
2056 a valid PC never does. */
2057 if (prev_regnum == ARM_PC_REGNUM)
2061 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2062 return frame_unwind_got_constant (this_frame, prev_regnum,
2063 arm_addr_bits_remove (gdbarch, lr));
2066 /* SP is generally not saved to the stack, but this frame is
2067 identified by the next frame's stack pointer at the time of the call.
2068 The value was already reconstructed into PREV_SP. */
2069 if (prev_regnum == ARM_SP_REGNUM)
2070 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2072 /* The CPSR may have been changed by the call instruction and by the
2073 called function. The only bit we can reconstruct is the T bit,
2074 by checking the low bit of LR as of the call. This is a reliable
2075 indicator of Thumb-ness except for some ARM v4T pre-interworking
2076 Thumb code, which could get away with a clear low bit as long as
2077 the called function did not use bx. Guess that all other
2078 bits are unchanged; the condition flags are presumably lost,
2079 but the processor status is likely valid. */
2080 if (prev_regnum == ARM_PS_REGNUM)
2083 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2085 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2086 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2087 if (IS_THUMB_ADDR (lr))
2091 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2094 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2098 struct frame_unwind arm_prologue_unwind = {
2100 arm_prologue_this_id,
2101 arm_prologue_prev_register,
2103 default_frame_sniffer
2106 static struct arm_prologue_cache *
2107 arm_make_stub_cache (struct frame_info *this_frame)
2109 struct arm_prologue_cache *cache;
2111 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2112 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2114 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2119 /* Our frame ID for a stub frame is the current SP and LR. */
2122 arm_stub_this_id (struct frame_info *this_frame,
2124 struct frame_id *this_id)
2126 struct arm_prologue_cache *cache;
2128 if (*this_cache == NULL)
2129 *this_cache = arm_make_stub_cache (this_frame);
2130 cache = *this_cache;
2132 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2136 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2137 struct frame_info *this_frame,
2138 void **this_prologue_cache)
2140 CORE_ADDR addr_in_block;
2143 addr_in_block = get_frame_address_in_block (this_frame);
2144 if (in_plt_section (addr_in_block, NULL)
2145 /* We also use the stub winder if the target memory is unreadable
2146 to avoid having the prologue unwinder trying to read it. */
2147 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2153 struct frame_unwind arm_stub_unwind = {
2156 arm_prologue_prev_register,
2158 arm_stub_unwind_sniffer
2162 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
2164 struct arm_prologue_cache *cache;
2166 if (*this_cache == NULL)
2167 *this_cache = arm_make_prologue_cache (this_frame);
2168 cache = *this_cache;
2170 return cache->prev_sp - cache->framesize;
2173 struct frame_base arm_normal_base = {
2174 &arm_prologue_unwind,
2175 arm_normal_frame_base,
2176 arm_normal_frame_base,
2177 arm_normal_frame_base
2180 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2181 dummy frame. The frame ID's base needs to match the TOS value
2182 saved by save_dummy_frame_tos() and returned from
2183 arm_push_dummy_call, and the PC needs to match the dummy frame's
2186 static struct frame_id
2187 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2189 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
2190 get_frame_pc (this_frame));
2193 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2194 be used to construct the previous frame's ID, after looking up the
2195 containing function). */
2198 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
2201 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
2202 return arm_addr_bits_remove (gdbarch, pc);
2206 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
2208 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
2211 static struct value *
2212 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
2215 struct gdbarch * gdbarch = get_frame_arch (this_frame);
2217 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2222 /* The PC is normally copied from the return column, which
2223 describes saves of LR. However, that version may have an
2224 extra bit set to indicate Thumb state. The bit is not
2226 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2227 return frame_unwind_got_constant (this_frame, regnum,
2228 arm_addr_bits_remove (gdbarch, lr));
2231 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
2232 cpsr = get_frame_register_unsigned (this_frame, regnum);
2233 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2234 if (IS_THUMB_ADDR (lr))
2238 return frame_unwind_got_constant (this_frame, regnum, cpsr);
2241 internal_error (__FILE__, __LINE__,
2242 _("Unexpected register %d"), regnum);
2247 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2248 struct dwarf2_frame_state_reg *reg,
2249 struct frame_info *this_frame)
2255 reg->how = DWARF2_FRAME_REG_FN;
2256 reg->loc.fn = arm_dwarf2_prev_register;
2259 reg->how = DWARF2_FRAME_REG_CFA;
2264 /* Return true if we are in the function's epilogue, i.e. after the
2265 instruction that destroyed the function's stack frame. */
2268 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2270 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2271 unsigned int insn, insn2;
2272 int found_return = 0, found_stack_adjust = 0;
2273 CORE_ADDR func_start, func_end;
2277 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
2280 /* The epilogue is a sequence of instructions along the following lines:
2282 - add stack frame size to SP or FP
2283 - [if frame pointer used] restore SP from FP
2284 - restore registers from SP [may include PC]
2285 - a return-type instruction [if PC wasn't already restored]
2287 In a first pass, we scan forward from the current PC and verify the
2288 instructions we find as compatible with this sequence, ending in a
2291 However, this is not sufficient to distinguish indirect function calls
2292 within a function from indirect tail calls in the epilogue in some cases.
2293 Therefore, if we didn't already find any SP-changing instruction during
2294 forward scan, we add a backward scanning heuristic to ensure we actually
2295 are in the epilogue. */
2298 while (scan_pc < func_end && !found_return)
2300 if (target_read_memory (scan_pc, buf, 2))
2304 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
2306 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2308 else if (insn == 0x46f7) /* mov pc, lr */
2310 else if (insn == 0x46bd) /* mov sp, r7 */
2311 found_stack_adjust = 1;
2312 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
2313 found_stack_adjust = 1;
2314 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
2316 found_stack_adjust = 1;
2317 if (insn & 0x0100) /* <registers> include PC. */
2320 else if ((insn & 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */
2322 if (target_read_memory (scan_pc, buf, 2))
2326 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2328 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
2330 found_stack_adjust = 1;
2331 if (insn2 & 0x8000) /* <registers> include PC. */
2334 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
2335 && (insn2 & 0x0fff) == 0x0b04)
2337 found_stack_adjust = 1;
2338 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
2341 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
2342 && (insn2 & 0x0e00) == 0x0a00)
2343 found_stack_adjust = 1;
2354 /* Since any instruction in the epilogue sequence, with the possible
2355 exception of return itself, updates the stack pointer, we need to
2356 scan backwards for at most one instruction. Try either a 16-bit or
2357 a 32-bit instruction. This is just a heuristic, so we do not worry
2358 too much about false positives.*/
2360 if (!found_stack_adjust)
2362 if (pc - 4 < func_start)
2364 if (target_read_memory (pc - 4, buf, 4))
2367 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
2368 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
2370 if (insn2 == 0x46bd) /* mov sp, r7 */
2371 found_stack_adjust = 1;
2372 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
2373 found_stack_adjust = 1;
2374 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
2375 found_stack_adjust = 1;
2376 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
2377 found_stack_adjust = 1;
2378 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
2379 && (insn2 & 0x0fff) == 0x0b04)
2380 found_stack_adjust = 1;
2381 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
2382 && (insn2 & 0x0e00) == 0x0a00)
2383 found_stack_adjust = 1;
2386 return found_stack_adjust;
2389 /* Return true if we are in the function's epilogue, i.e. after the
2390 instruction that destroyed the function's stack frame. */
2393 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2395 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2397 int found_return, found_stack_adjust;
2398 CORE_ADDR func_start, func_end;
2400 if (arm_pc_is_thumb (gdbarch, pc))
2401 return thumb_in_function_epilogue_p (gdbarch, pc);
2403 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
2406 /* We are in the epilogue if the previous instruction was a stack
2407 adjustment and the next instruction is a possible return (bx, mov
2408 pc, or pop). We could have to scan backwards to find the stack
2409 adjustment, or forwards to find the return, but this is a decent
2410 approximation. First scan forwards. */
2413 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
2414 if (bits (insn, 28, 31) != INST_NV)
2416 if ((insn & 0x0ffffff0) == 0x012fff10)
2419 else if ((insn & 0x0ffffff0) == 0x01a0f000)
2422 else if ((insn & 0x0fff0000) == 0x08bd0000
2423 && (insn & 0x0000c000) != 0)
2424 /* POP (LDMIA), including PC or LR. */
2431 /* Scan backwards. This is just a heuristic, so do not worry about
2432 false positives from mode changes. */
2434 if (pc < func_start + 4)
2437 found_stack_adjust = 0;
2438 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
2439 if (bits (insn, 28, 31) != INST_NV)
2441 if ((insn & 0x0df0f000) == 0x0080d000)
2442 /* ADD SP (register or immediate). */
2443 found_stack_adjust = 1;
2444 else if ((insn & 0x0df0f000) == 0x0040d000)
2445 /* SUB SP (register or immediate). */
2446 found_stack_adjust = 1;
2447 else if ((insn & 0x0ffffff0) == 0x01a0d000)
2449 found_stack_adjust = 1;
2450 else if ((insn & 0x0fff0000) == 0x08bd0000)
2452 found_stack_adjust = 1;
2455 if (found_stack_adjust)
2462 /* When arguments must be pushed onto the stack, they go on in reverse
2463 order. The code below implements a FILO (stack) to do this. */
2468 struct stack_item *prev;
2472 static struct stack_item *
2473 push_stack_item (struct stack_item *prev, const void *contents, int len)
2475 struct stack_item *si;
2476 si = xmalloc (sizeof (struct stack_item));
2477 si->data = xmalloc (len);
2480 memcpy (si->data, contents, len);
2484 static struct stack_item *
2485 pop_stack_item (struct stack_item *si)
2487 struct stack_item *dead = si;
2495 /* Return the alignment (in bytes) of the given type. */
2498 arm_type_align (struct type *t)
2504 t = check_typedef (t);
2505 switch (TYPE_CODE (t))
2508 /* Should never happen. */
2509 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
2513 case TYPE_CODE_ENUM:
2517 case TYPE_CODE_RANGE:
2518 case TYPE_CODE_BITSTRING:
2520 case TYPE_CODE_CHAR:
2521 case TYPE_CODE_BOOL:
2522 return TYPE_LENGTH (t);
2524 case TYPE_CODE_ARRAY:
2525 case TYPE_CODE_COMPLEX:
2526 /* TODO: What about vector types? */
2527 return arm_type_align (TYPE_TARGET_TYPE (t));
2529 case TYPE_CODE_STRUCT:
2530 case TYPE_CODE_UNION:
2532 for (n = 0; n < TYPE_NFIELDS (t); n++)
2534 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
2542 /* Possible base types for a candidate for passing and returning in
2545 enum arm_vfp_cprc_base_type
2554 /* The length of one element of base type B. */
2557 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
2561 case VFP_CPRC_SINGLE:
2563 case VFP_CPRC_DOUBLE:
2565 case VFP_CPRC_VEC64:
2567 case VFP_CPRC_VEC128:
2570 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
2575 /* The character ('s', 'd' or 'q') for the type of VFP register used
2576 for passing base type B. */
2579 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
2583 case VFP_CPRC_SINGLE:
2585 case VFP_CPRC_DOUBLE:
2587 case VFP_CPRC_VEC64:
2589 case VFP_CPRC_VEC128:
2592 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
2597 /* Determine whether T may be part of a candidate for passing and
2598 returning in VFP registers, ignoring the limit on the total number
2599 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
2600 classification of the first valid component found; if it is not
2601 VFP_CPRC_UNKNOWN, all components must have the same classification
2602 as *BASE_TYPE. If it is found that T contains a type not permitted
2603 for passing and returning in VFP registers, a type differently
2604 classified from *BASE_TYPE, or two types differently classified
2605 from each other, return -1, otherwise return the total number of
2606 base-type elements found (possibly 0 in an empty structure or
2607 array). Vectors and complex types are not currently supported,
2608 matching the generic AAPCS support. */
2611 arm_vfp_cprc_sub_candidate (struct type *t,
2612 enum arm_vfp_cprc_base_type *base_type)
2614 t = check_typedef (t);
2615 switch (TYPE_CODE (t))
2618 switch (TYPE_LENGTH (t))
2621 if (*base_type == VFP_CPRC_UNKNOWN)
2622 *base_type = VFP_CPRC_SINGLE;
2623 else if (*base_type != VFP_CPRC_SINGLE)
2628 if (*base_type == VFP_CPRC_UNKNOWN)
2629 *base_type = VFP_CPRC_DOUBLE;
2630 else if (*base_type != VFP_CPRC_DOUBLE)
2639 case TYPE_CODE_ARRAY:
2643 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
2646 if (TYPE_LENGTH (t) == 0)
2648 gdb_assert (count == 0);
2651 else if (count == 0)
2653 unitlen = arm_vfp_cprc_unit_length (*base_type);
2654 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
2655 return TYPE_LENGTH (t) / unitlen;
2659 case TYPE_CODE_STRUCT:
2664 for (i = 0; i < TYPE_NFIELDS (t); i++)
2666 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
2668 if (sub_count == -1)
2672 if (TYPE_LENGTH (t) == 0)
2674 gdb_assert (count == 0);
2677 else if (count == 0)
2679 unitlen = arm_vfp_cprc_unit_length (*base_type);
2680 if (TYPE_LENGTH (t) != unitlen * count)
2685 case TYPE_CODE_UNION:
2690 for (i = 0; i < TYPE_NFIELDS (t); i++)
2692 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
2694 if (sub_count == -1)
2696 count = (count > sub_count ? count : sub_count);
2698 if (TYPE_LENGTH (t) == 0)
2700 gdb_assert (count == 0);
2703 else if (count == 0)
2705 unitlen = arm_vfp_cprc_unit_length (*base_type);
2706 if (TYPE_LENGTH (t) != unitlen * count)
2718 /* Determine whether T is a VFP co-processor register candidate (CPRC)
2719 if passed to or returned from a non-variadic function with the VFP
2720 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
2721 *BASE_TYPE to the base type for T and *COUNT to the number of
2722 elements of that base type before returning. */
2725 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
2728 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
2729 int c = arm_vfp_cprc_sub_candidate (t, &b);
2730 if (c <= 0 || c > 4)
2737 /* Return 1 if the VFP ABI should be used for passing arguments to and
2738 returning values from a function of type FUNC_TYPE, 0
2742 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
2744 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2745 /* Variadic functions always use the base ABI. Assume that functions
2746 without debug info are not variadic. */
2747 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
2749 /* The VFP ABI is only supported as a variant of AAPCS. */
2750 if (tdep->arm_abi != ARM_ABI_AAPCS)
2752 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
2755 /* We currently only support passing parameters in integer registers, which
2756 conforms with GCC's default model, and VFP argument passing following
2757 the VFP variant of AAPCS. Several other variants exist and
2758 we should probably support some of them based on the selected ABI. */
2761 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2762 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2763 struct value **args, CORE_ADDR sp, int struct_return,
2764 CORE_ADDR struct_addr)
2766 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2770 struct stack_item *si = NULL;
2773 unsigned vfp_regs_free = (1 << 16) - 1;
2775 /* Determine the type of this function and whether the VFP ABI
2777 ftype = check_typedef (value_type (function));
2778 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
2779 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
2780 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
2782 /* Set the return address. For the ARM, the return breakpoint is
2783 always at BP_ADDR. */
2784 if (arm_pc_is_thumb (gdbarch, bp_addr))
2786 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
2788 /* Walk through the list of args and determine how large a temporary
2789 stack is required. Need to take care here as structs may be
2790 passed on the stack, and we have to to push them. */
2793 argreg = ARM_A1_REGNUM;
2796 /* The struct_return pointer occupies the first parameter
2797 passing register. */
2801 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
2802 gdbarch_register_name (gdbarch, argreg),
2803 paddress (gdbarch, struct_addr));
2804 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
2808 for (argnum = 0; argnum < nargs; argnum++)
2811 struct type *arg_type;
2812 struct type *target_type;
2813 enum type_code typecode;
2814 const bfd_byte *val;
2816 enum arm_vfp_cprc_base_type vfp_base_type;
2818 int may_use_core_reg = 1;
2820 arg_type = check_typedef (value_type (args[argnum]));
2821 len = TYPE_LENGTH (arg_type);
2822 target_type = TYPE_TARGET_TYPE (arg_type);
2823 typecode = TYPE_CODE (arg_type);
2824 val = value_contents (args[argnum]);
2826 align = arm_type_align (arg_type);
2827 /* Round alignment up to a whole number of words. */
2828 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
2829 /* Different ABIs have different maximum alignments. */
2830 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
2832 /* The APCS ABI only requires word alignment. */
2833 align = INT_REGISTER_SIZE;
2837 /* The AAPCS requires at most doubleword alignment. */
2838 if (align > INT_REGISTER_SIZE * 2)
2839 align = INT_REGISTER_SIZE * 2;
2843 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
2851 /* Because this is a CPRC it cannot go in a core register or
2852 cause a core register to be skipped for alignment.
2853 Either it goes in VFP registers and the rest of this loop
2854 iteration is skipped for this argument, or it goes on the
2855 stack (and the stack alignment code is correct for this
2857 may_use_core_reg = 0;
2859 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
2860 shift = unit_length / 4;
2861 mask = (1 << (shift * vfp_base_count)) - 1;
2862 for (regno = 0; regno < 16; regno += shift)
2863 if (((vfp_regs_free >> regno) & mask) == mask)
2872 vfp_regs_free &= ~(mask << regno);
2873 reg_scaled = regno / shift;
2874 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
2875 for (i = 0; i < vfp_base_count; i++)
2879 if (reg_char == 'q')
2880 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
2881 val + i * unit_length);
2884 sprintf (name_buf, "%c%d", reg_char, reg_scaled + i);
2885 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
2887 regcache_cooked_write (regcache, regnum,
2888 val + i * unit_length);
2895 /* This CPRC could not go in VFP registers, so all VFP
2896 registers are now marked as used. */
2901 /* Push stack padding for dowubleword alignment. */
2902 if (nstack & (align - 1))
2904 si = push_stack_item (si, val, INT_REGISTER_SIZE);
2905 nstack += INT_REGISTER_SIZE;
2908 /* Doubleword aligned quantities must go in even register pairs. */
2909 if (may_use_core_reg
2910 && argreg <= ARM_LAST_ARG_REGNUM
2911 && align > INT_REGISTER_SIZE
2915 /* If the argument is a pointer to a function, and it is a
2916 Thumb function, create a LOCAL copy of the value and set
2917 the THUMB bit in it. */
2918 if (TYPE_CODE_PTR == typecode
2919 && target_type != NULL
2920 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
2922 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
2923 if (arm_pc_is_thumb (gdbarch, regval))
2925 bfd_byte *copy = alloca (len);
2926 store_unsigned_integer (copy, len, byte_order,
2927 MAKE_THUMB_ADDR (regval));
2932 /* Copy the argument to general registers or the stack in
2933 register-sized pieces. Large arguments are split between
2934 registers and stack. */
2937 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
2939 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
2941 /* The argument is being passed in a general purpose
2944 = extract_unsigned_integer (val, partial_len, byte_order);
2945 if (byte_order == BFD_ENDIAN_BIG)
2946 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
2948 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
2950 gdbarch_register_name
2952 phex (regval, INT_REGISTER_SIZE));
2953 regcache_cooked_write_unsigned (regcache, argreg, regval);
2958 /* Push the arguments onto the stack. */
2960 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
2962 si = push_stack_item (si, val, INT_REGISTER_SIZE);
2963 nstack += INT_REGISTER_SIZE;
2970 /* If we have an odd number of words to push, then decrement the stack
2971 by one word now, so first stack argument will be dword aligned. */
2978 write_memory (sp, si->data, si->len);
2979 si = pop_stack_item (si);
2982 /* Finally, update teh SP register. */
2983 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
2989 /* Always align the frame to an 8-byte boundary. This is required on
2990 some platforms and harmless on the rest. */
2993 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2995 /* Align the stack to eight bytes. */
2996 return sp & ~ (CORE_ADDR) 7;
3000 print_fpu_flags (int flags)
3002 if (flags & (1 << 0))
3003 fputs ("IVO ", stdout);
3004 if (flags & (1 << 1))
3005 fputs ("DVZ ", stdout);
3006 if (flags & (1 << 2))
3007 fputs ("OFL ", stdout);
3008 if (flags & (1 << 3))
3009 fputs ("UFL ", stdout);
3010 if (flags & (1 << 4))
3011 fputs ("INX ", stdout);
3015 /* Print interesting information about the floating point processor
3016 (if present) or emulator. */
3018 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3019 struct frame_info *frame, const char *args)
3021 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3024 type = (status >> 24) & 127;
3025 if (status & (1 << 31))
3026 printf (_("Hardware FPU type %d\n"), type);
3028 printf (_("Software FPU type %d\n"), type);
3029 /* i18n: [floating point unit] mask */
3030 fputs (_("mask: "), stdout);
3031 print_fpu_flags (status >> 16);
3032 /* i18n: [floating point unit] flags */
3033 fputs (_("flags: "), stdout);
3034 print_fpu_flags (status);
3037 /* Construct the ARM extended floating point type. */
3038 static struct type *
3039 arm_ext_type (struct gdbarch *gdbarch)
3041 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3043 if (!tdep->arm_ext_type)
3045 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3046 floatformats_arm_ext);
3048 return tdep->arm_ext_type;
3051 static struct type *
3052 arm_neon_double_type (struct gdbarch *gdbarch)
3054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3056 if (tdep->neon_double_type == NULL)
3058 struct type *t, *elem;
3060 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3062 elem = builtin_type (gdbarch)->builtin_uint8;
3063 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3064 elem = builtin_type (gdbarch)->builtin_uint16;
3065 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3066 elem = builtin_type (gdbarch)->builtin_uint32;
3067 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3068 elem = builtin_type (gdbarch)->builtin_uint64;
3069 append_composite_type_field (t, "u64", elem);
3070 elem = builtin_type (gdbarch)->builtin_float;
3071 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3072 elem = builtin_type (gdbarch)->builtin_double;
3073 append_composite_type_field (t, "f64", elem);
3075 TYPE_VECTOR (t) = 1;
3076 TYPE_NAME (t) = "neon_d";
3077 tdep->neon_double_type = t;
3080 return tdep->neon_double_type;
3083 /* FIXME: The vector types are not correctly ordered on big-endian
3084 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3085 bits of d0 - regardless of what unit size is being held in d0. So
3086 the offset of the first uint8 in d0 is 7, but the offset of the
3087 first float is 4. This code works as-is for little-endian
3090 static struct type *
3091 arm_neon_quad_type (struct gdbarch *gdbarch)
3093 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3095 if (tdep->neon_quad_type == NULL)
3097 struct type *t, *elem;
3099 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3101 elem = builtin_type (gdbarch)->builtin_uint8;
3102 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3103 elem = builtin_type (gdbarch)->builtin_uint16;
3104 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3105 elem = builtin_type (gdbarch)->builtin_uint32;
3106 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3107 elem = builtin_type (gdbarch)->builtin_uint64;
3108 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
3109 elem = builtin_type (gdbarch)->builtin_float;
3110 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
3111 elem = builtin_type (gdbarch)->builtin_double;
3112 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
3114 TYPE_VECTOR (t) = 1;
3115 TYPE_NAME (t) = "neon_q";
3116 tdep->neon_quad_type = t;
3119 return tdep->neon_quad_type;
3122 /* Return the GDB type object for the "standard" data type of data in
3125 static struct type *
3126 arm_register_type (struct gdbarch *gdbarch, int regnum)
3128 int num_regs = gdbarch_num_regs (gdbarch);
3130 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
3131 && regnum >= num_regs && regnum < num_regs + 32)
3132 return builtin_type (gdbarch)->builtin_float;
3134 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
3135 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
3136 return arm_neon_quad_type (gdbarch);
3138 /* If the target description has register information, we are only
3139 in this function so that we can override the types of
3140 double-precision registers for NEON. */
3141 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
3143 struct type *t = tdesc_register_type (gdbarch, regnum);
3145 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
3146 && TYPE_CODE (t) == TYPE_CODE_FLT
3147 && gdbarch_tdep (gdbarch)->have_neon)
3148 return arm_neon_double_type (gdbarch);
3153 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
3155 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
3156 return builtin_type (gdbarch)->builtin_void;
3158 return arm_ext_type (gdbarch);
3160 else if (regnum == ARM_SP_REGNUM)
3161 return builtin_type (gdbarch)->builtin_data_ptr;
3162 else if (regnum == ARM_PC_REGNUM)
3163 return builtin_type (gdbarch)->builtin_func_ptr;
3164 else if (regnum >= ARRAY_SIZE (arm_register_names))
3165 /* These registers are only supported on targets which supply
3166 an XML description. */
3167 return builtin_type (gdbarch)->builtin_int0;
3169 return builtin_type (gdbarch)->builtin_uint32;
3172 /* Map a DWARF register REGNUM onto the appropriate GDB register
3176 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3178 /* Core integer regs. */
3179 if (reg >= 0 && reg <= 15)
3182 /* Legacy FPA encoding. These were once used in a way which
3183 overlapped with VFP register numbering, so their use is
3184 discouraged, but GDB doesn't support the ARM toolchain
3185 which used them for VFP. */
3186 if (reg >= 16 && reg <= 23)
3187 return ARM_F0_REGNUM + reg - 16;
3189 /* New assignments for the FPA registers. */
3190 if (reg >= 96 && reg <= 103)
3191 return ARM_F0_REGNUM + reg - 96;
3193 /* WMMX register assignments. */
3194 if (reg >= 104 && reg <= 111)
3195 return ARM_WCGR0_REGNUM + reg - 104;
3197 if (reg >= 112 && reg <= 127)
3198 return ARM_WR0_REGNUM + reg - 112;
3200 if (reg >= 192 && reg <= 199)
3201 return ARM_WC0_REGNUM + reg - 192;
3203 /* VFP v2 registers. A double precision value is actually
3204 in d1 rather than s2, but the ABI only defines numbering
3205 for the single precision registers. This will "just work"
3206 in GDB for little endian targets (we'll read eight bytes,
3207 starting in s0 and then progressing to s1), but will be
3208 reversed on big endian targets with VFP. This won't
3209 be a problem for the new Neon quad registers; you're supposed
3210 to use DW_OP_piece for those. */
3211 if (reg >= 64 && reg <= 95)
3215 sprintf (name_buf, "s%d", reg - 64);
3216 return user_reg_map_name_to_regnum (gdbarch, name_buf,
3220 /* VFP v3 / Neon registers. This range is also used for VFP v2
3221 registers, except that it now describes d0 instead of s0. */
3222 if (reg >= 256 && reg <= 287)
3226 sprintf (name_buf, "d%d", reg - 256);
3227 return user_reg_map_name_to_regnum (gdbarch, name_buf,
3234 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
3236 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
3239 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
3241 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
3242 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
3244 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
3245 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
3247 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
3248 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
3250 if (reg < NUM_GREGS)
3251 return SIM_ARM_R0_REGNUM + reg;
3254 if (reg < NUM_FREGS)
3255 return SIM_ARM_FP0_REGNUM + reg;
3258 if (reg < NUM_SREGS)
3259 return SIM_ARM_FPS_REGNUM + reg;
3262 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
3265 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
3266 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
3267 It is thought that this is is the floating-point register format on
3268 little-endian systems. */
3271 convert_from_extended (const struct floatformat *fmt, const void *ptr,
3272 void *dbl, int endianess)
3276 if (endianess == BFD_ENDIAN_BIG)
3277 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
3279 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
3281 floatformat_from_doublest (fmt, &d, dbl);
3285 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
3290 floatformat_to_doublest (fmt, ptr, &d);
3291 if (endianess == BFD_ENDIAN_BIG)
3292 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
3294 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
3299 condition_true (unsigned long cond, unsigned long status_reg)
3301 if (cond == INST_AL || cond == INST_NV)
3307 return ((status_reg & FLAG_Z) != 0);
3309 return ((status_reg & FLAG_Z) == 0);
3311 return ((status_reg & FLAG_C) != 0);
3313 return ((status_reg & FLAG_C) == 0);
3315 return ((status_reg & FLAG_N) != 0);
3317 return ((status_reg & FLAG_N) == 0);
3319 return ((status_reg & FLAG_V) != 0);
3321 return ((status_reg & FLAG_V) == 0);
3323 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
3325 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
3327 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
3329 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
3331 return (((status_reg & FLAG_Z) == 0)
3332 && (((status_reg & FLAG_N) == 0)
3333 == ((status_reg & FLAG_V) == 0)));
3335 return (((status_reg & FLAG_Z) != 0)
3336 || (((status_reg & FLAG_N) == 0)
3337 != ((status_reg & FLAG_V) == 0)));
3342 static unsigned long
3343 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
3344 unsigned long pc_val, unsigned long status_reg)
3346 unsigned long res, shift;
3347 int rm = bits (inst, 0, 3);
3348 unsigned long shifttype = bits (inst, 5, 6);
3352 int rs = bits (inst, 8, 11);
3353 shift = (rs == 15 ? pc_val + 8
3354 : get_frame_register_unsigned (frame, rs)) & 0xFF;
3357 shift = bits (inst, 7, 11);
3360 ? (pc_val + (bit (inst, 4) ? 12 : 8))
3361 : get_frame_register_unsigned (frame, rm));
3366 res = shift >= 32 ? 0 : res << shift;
3370 res = shift >= 32 ? 0 : res >> shift;
3376 res = ((res & 0x80000000L)
3377 ? ~((~res) >> shift) : res >> shift);
3380 case 3: /* ROR/RRX */
3383 res = (res >> 1) | (carry ? 0x80000000L : 0);
3385 res = (res >> shift) | (res << (32 - shift));
3389 return res & 0xffffffff;
3392 /* Return number of 1-bits in VAL. */
3395 bitcount (unsigned long val)
3398 for (nbits = 0; val != 0; nbits++)
3399 val &= val - 1; /* delete rightmost 1-bit in val */
3403 /* Return the size in bytes of the complete Thumb instruction whose
3404 first halfword is INST1. */
3407 thumb_insn_size (unsigned short inst1)
3409 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
3416 thumb_advance_itstate (unsigned int itstate)
3418 /* Preserve IT[7:5], the first three bits of the condition. Shift
3419 the upcoming condition flags left by one bit. */
3420 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
3422 /* If we have finished the IT block, clear the state. */
3423 if ((itstate & 0x0f) == 0)
3429 /* Find the next PC after the current instruction executes. In some
3430 cases we can not statically determine the answer (see the IT state
3431 handling in this function); in that case, a breakpoint may be
3432 inserted in addition to the returned PC, which will be used to set
3433 another breakpoint by our caller. */
3436 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
3438 struct gdbarch *gdbarch = get_frame_arch (frame);
3439 struct address_space *aspace = get_frame_address_space (frame);
3440 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3441 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3442 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
3443 unsigned short inst1;
3444 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
3445 unsigned long offset;
3446 ULONGEST status, itstate;
3448 nextpc = MAKE_THUMB_ADDR (nextpc);
3449 pc_val = MAKE_THUMB_ADDR (pc_val);
3451 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
3453 /* Thumb-2 conditional execution support. There are eight bits in
3454 the CPSR which describe conditional execution state. Once
3455 reconstructed (they're in a funny order), the low five bits
3456 describe the low bit of the condition for each instruction and
3457 how many instructions remain. The high three bits describe the
3458 base condition. One of the low four bits will be set if an IT
3459 block is active. These bits read as zero on earlier
3461 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
3462 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
3464 /* If-Then handling. On GNU/Linux, where this routine is used, we
3465 use an undefined instruction as a breakpoint. Unlike BKPT, IT
3466 can disable execution of the undefined instruction. So we might
3467 miss the breakpoint if we set it on a skipped conditional
3468 instruction. Because conditional instructions can change the
3469 flags, affecting the execution of further instructions, we may
3470 need to set two breakpoints. */
3472 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
3474 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
3476 /* An IT instruction. Because this instruction does not
3477 modify the flags, we can accurately predict the next
3478 executed instruction. */
3479 itstate = inst1 & 0x00ff;
3480 pc += thumb_insn_size (inst1);
3482 while (itstate != 0 && ! condition_true (itstate >> 4, status))
3484 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
3485 pc += thumb_insn_size (inst1);
3486 itstate = thumb_advance_itstate (itstate);
3489 return MAKE_THUMB_ADDR (pc);
3491 else if (itstate != 0)
3493 /* We are in a conditional block. Check the condition. */
3494 if (! condition_true (itstate >> 4, status))
3496 /* Advance to the next executed instruction. */
3497 pc += thumb_insn_size (inst1);
3498 itstate = thumb_advance_itstate (itstate);
3500 while (itstate != 0 && ! condition_true (itstate >> 4, status))
3502 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
3503 pc += thumb_insn_size (inst1);
3504 itstate = thumb_advance_itstate (itstate);
3507 return MAKE_THUMB_ADDR (pc);
3509 else if ((itstate & 0x0f) == 0x08)
3511 /* This is the last instruction of the conditional
3512 block, and it is executed. We can handle it normally
3513 because the following instruction is not conditional,
3514 and we must handle it normally because it is
3515 permitted to branch. Fall through. */
3521 /* There are conditional instructions after this one.
3522 If this instruction modifies the flags, then we can
3523 not predict what the next executed instruction will
3524 be. Fortunately, this instruction is architecturally
3525 forbidden to branch; we know it will fall through.
3526 Start by skipping past it. */
3527 pc += thumb_insn_size (inst1);
3528 itstate = thumb_advance_itstate (itstate);
3530 /* Set a breakpoint on the following instruction. */
3531 gdb_assert ((itstate & 0x0f) != 0);
3533 insert_single_step_breakpoint (gdbarch, aspace, pc);
3534 cond_negated = (itstate >> 4) & 1;
3536 /* Skip all following instructions with the same
3537 condition. If there is a later instruction in the IT
3538 block with the opposite condition, set the other
3539 breakpoint there. If not, then set a breakpoint on
3540 the instruction after the IT block. */
3543 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
3544 pc += thumb_insn_size (inst1);
3545 itstate = thumb_advance_itstate (itstate);
3547 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
3549 return MAKE_THUMB_ADDR (pc);
3553 else if (itstate & 0x0f)
3555 /* We are in a conditional block. Check the condition. */
3556 int cond = itstate >> 4;
3558 if (! condition_true (cond, status))
3560 /* Advance to the next instruction. All the 32-bit
3561 instructions share a common prefix. */
3562 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
3563 return MAKE_THUMB_ADDR (pc + 4);
3565 return MAKE_THUMB_ADDR (pc + 2);
3568 /* Otherwise, handle the instruction normally. */
3571 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
3575 /* Fetch the saved PC from the stack. It's stored above
3576 all of the other registers. */
3577 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
3578 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
3579 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
3581 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
3583 unsigned long cond = bits (inst1, 8, 11);
3584 if (cond == 0x0f) /* 0x0f = SWI */
3586 struct gdbarch_tdep *tdep;
3587 tdep = gdbarch_tdep (gdbarch);
3589 if (tdep->syscall_next_pc != NULL)
3590 nextpc = tdep->syscall_next_pc (frame);
3593 else if (cond != 0x0f && condition_true (cond, status))
3594 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
3596 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
3598 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
3600 else if ((inst1 & 0xe000) == 0xe000) /* 32-bit instruction */
3602 unsigned short inst2;
3603 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
3605 /* Default to the next instruction. */
3607 nextpc = MAKE_THUMB_ADDR (nextpc);
3609 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
3611 /* Branches and miscellaneous control instructions. */
3613 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
3616 int j1, j2, imm1, imm2;
3618 imm1 = sbits (inst1, 0, 10);
3619 imm2 = bits (inst2, 0, 10);
3620 j1 = bit (inst2, 13);
3621 j2 = bit (inst2, 11);
3623 offset = ((imm1 << 12) + (imm2 << 1));
3624 offset ^= ((!j2) << 22) | ((!j1) << 23);
3626 nextpc = pc_val + offset;
3627 /* For BLX make sure to clear the low bits. */
3628 if (bit (inst2, 12) == 0)
3629 nextpc = nextpc & 0xfffffffc;
3631 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
3633 /* SUBS PC, LR, #imm8. */
3634 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
3635 nextpc -= inst2 & 0x00ff;
3637 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
3639 /* Conditional branch. */
3640 if (condition_true (bits (inst1, 6, 9), status))
3642 int sign, j1, j2, imm1, imm2;
3644 sign = sbits (inst1, 10, 10);
3645 imm1 = bits (inst1, 0, 5);
3646 imm2 = bits (inst2, 0, 10);
3647 j1 = bit (inst2, 13);
3648 j2 = bit (inst2, 11);
3650 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
3651 offset += (imm1 << 12) + (imm2 << 1);
3653 nextpc = pc_val + offset;
3657 else if ((inst1 & 0xfe50) == 0xe810)
3659 /* Load multiple or RFE. */
3660 int rn, offset, load_pc = 1;
3662 rn = bits (inst1, 0, 3);
3663 if (bit (inst1, 7) && !bit (inst1, 8))
3666 if (!bit (inst2, 15))
3668 offset = bitcount (inst2) * 4 - 4;
3670 else if (!bit (inst1, 7) && bit (inst1, 8))
3673 if (!bit (inst2, 15))
3677 else if (bit (inst1, 7) && bit (inst1, 8))
3682 else if (!bit (inst1, 7) && !bit (inst1, 8))
3692 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
3693 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
3696 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
3698 /* MOV PC or MOVS PC. */
3699 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
3700 nextpc = MAKE_THUMB_ADDR (nextpc);
3702 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
3706 int rn, load_pc = 1;
3708 rn = bits (inst1, 0, 3);
3709 base = get_frame_register_unsigned (frame, rn);
3712 base = (base + 4) & ~(CORE_ADDR) 0x3;
3714 base += bits (inst2, 0, 11);
3716 base -= bits (inst2, 0, 11);
3718 else if (bit (inst1, 7))
3719 base += bits (inst2, 0, 11);
3720 else if (bit (inst2, 11))
3722 if (bit (inst2, 10))
3725 base += bits (inst2, 0, 7);
3727 base -= bits (inst2, 0, 7);
3730 else if ((inst2 & 0x0fc0) == 0x0000)
3732 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
3733 base += get_frame_register_unsigned (frame, rm) << shift;
3740 nextpc = get_frame_memory_unsigned (frame, base, 4);
3742 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
3745 CORE_ADDR tbl_reg, table, offset, length;
3747 tbl_reg = bits (inst1, 0, 3);
3748 if (tbl_reg == 0x0f)
3749 table = pc + 4; /* Regcache copy of PC isn't right yet. */
3751 table = get_frame_register_unsigned (frame, tbl_reg);
3753 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
3754 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
3755 nextpc = pc_val + length;
3757 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
3760 CORE_ADDR tbl_reg, table, offset, length;
3762 tbl_reg = bits (inst1, 0, 3);
3763 if (tbl_reg == 0x0f)
3764 table = pc + 4; /* Regcache copy of PC isn't right yet. */
3766 table = get_frame_register_unsigned (frame, tbl_reg);
3768 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
3769 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
3770 nextpc = pc_val + length;
3773 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
3775 if (bits (inst1, 3, 6) == 0x0f)
3778 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
3780 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
3782 if (bits (inst1, 3, 6) == 0x0f)
3785 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
3787 nextpc = MAKE_THUMB_ADDR (nextpc);
3789 else if ((inst1 & 0xf500) == 0xb100)
3792 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
3793 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
3795 if (bit (inst1, 11) && reg != 0)
3796 nextpc = pc_val + imm;
3797 else if (!bit (inst1, 11) && reg == 0)
3798 nextpc = pc_val + imm;
3803 /* Get the raw next address. PC is the current program counter, in
3804 FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on
3805 the alternative next instruction if there are two options.
3807 The value returned has the execution state of the next instruction
3808 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
3809 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
3813 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
3815 struct gdbarch *gdbarch = get_frame_arch (frame);
3816 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3817 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3818 unsigned long pc_val;
3819 unsigned long this_instr;
3820 unsigned long status;
3823 if (arm_frame_is_thumb (frame))
3824 return thumb_get_next_pc_raw (frame, pc, insert_bkpt);
3826 pc_val = (unsigned long) pc;
3827 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3829 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
3830 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
3832 if (bits (this_instr, 28, 31) == INST_NV)
3833 switch (bits (this_instr, 24, 27))
3838 /* Branch with Link and change to Thumb. */
3839 nextpc = BranchDest (pc, this_instr);
3840 nextpc |= bit (this_instr, 24) << 1;
3841 nextpc = MAKE_THUMB_ADDR (nextpc);
3847 /* Coprocessor register transfer. */
3848 if (bits (this_instr, 12, 15) == 15)
3849 error (_("Invalid update to pc in instruction"));
3852 else if (condition_true (bits (this_instr, 28, 31), status))
3854 switch (bits (this_instr, 24, 27))
3857 case 0x1: /* data processing */
3861 unsigned long operand1, operand2, result = 0;
3865 if (bits (this_instr, 12, 15) != 15)
3868 if (bits (this_instr, 22, 25) == 0
3869 && bits (this_instr, 4, 7) == 9) /* multiply */
3870 error (_("Invalid update to pc in instruction"));
3872 /* BX <reg>, BLX <reg> */
3873 if (bits (this_instr, 4, 27) == 0x12fff1
3874 || bits (this_instr, 4, 27) == 0x12fff3)
3876 rn = bits (this_instr, 0, 3);
3877 nextpc = (rn == 15) ? pc_val + 8
3878 : get_frame_register_unsigned (frame, rn);
3882 /* Multiply into PC */
3883 c = (status & FLAG_C) ? 1 : 0;
3884 rn = bits (this_instr, 16, 19);
3885 operand1 = (rn == 15) ? pc_val + 8
3886 : get_frame_register_unsigned (frame, rn);
3888 if (bit (this_instr, 25))
3890 unsigned long immval = bits (this_instr, 0, 7);
3891 unsigned long rotate = 2 * bits (this_instr, 8, 11);
3892 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
3895 else /* operand 2 is a shifted register */
3896 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
3898 switch (bits (this_instr, 21, 24))
3901 result = operand1 & operand2;
3905 result = operand1 ^ operand2;
3909 result = operand1 - operand2;
3913 result = operand2 - operand1;
3917 result = operand1 + operand2;
3921 result = operand1 + operand2 + c;
3925 result = operand1 - operand2 + c;
3929 result = operand2 - operand1 + c;
3935 case 0xb: /* tst, teq, cmp, cmn */
3936 result = (unsigned long) nextpc;
3940 result = operand1 | operand2;
3944 /* Always step into a function. */
3949 result = operand1 & ~operand2;
3957 /* In 26-bit APCS the bottom two bits of the result are
3958 ignored, and we always end up in ARM state. */
3960 nextpc = arm_addr_bits_remove (gdbarch, result);
3968 case 0x5: /* data transfer */
3971 if (bit (this_instr, 20))
3974 if (bits (this_instr, 12, 15) == 15)
3980 if (bit (this_instr, 22))
3981 error (_("Invalid update to pc in instruction"));
3983 /* byte write to PC */
3984 rn = bits (this_instr, 16, 19);
3985 base = (rn == 15) ? pc_val + 8
3986 : get_frame_register_unsigned (frame, rn);
3987 if (bit (this_instr, 24))
3990 int c = (status & FLAG_C) ? 1 : 0;
3991 unsigned long offset =
3992 (bit (this_instr, 25)
3993 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
3994 : bits (this_instr, 0, 11));
3996 if (bit (this_instr, 23))
4001 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
4008 case 0x9: /* block transfer */
4009 if (bit (this_instr, 20))
4012 if (bit (this_instr, 15))
4017 if (bit (this_instr, 23))
4020 unsigned long reglist = bits (this_instr, 0, 14);
4021 offset = bitcount (reglist) * 4;
4022 if (bit (this_instr, 24)) /* pre */
4025 else if (bit (this_instr, 24))
4029 unsigned long rn_val =
4030 get_frame_register_unsigned (frame,
4031 bits (this_instr, 16, 19));
4033 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
4041 case 0xb: /* branch & link */
4042 case 0xa: /* branch */
4044 nextpc = BranchDest (pc, this_instr);
4050 case 0xe: /* coproc ops */
4054 struct gdbarch_tdep *tdep;
4055 tdep = gdbarch_tdep (gdbarch);
4057 if (tdep->syscall_next_pc != NULL)
4058 nextpc = tdep->syscall_next_pc (frame);
4064 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4073 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4075 struct gdbarch *gdbarch = get_frame_arch (frame);
4077 gdbarch_addr_bits_remove (gdbarch,
4078 arm_get_next_pc_raw (frame, pc, TRUE));
4080 error (_("Infinite loop detected"));
4084 /* single_step() is called just before we want to resume the inferior,
4085 if we want to single-step it but there is no hardware or kernel
4086 single-step support. We find the target of the coming instruction
4087 and breakpoint it. */
4090 arm_software_single_step (struct frame_info *frame)
4092 struct gdbarch *gdbarch = get_frame_arch (frame);
4093 struct address_space *aspace = get_frame_address_space (frame);
4095 /* NOTE: This may insert the wrong breakpoint instruction when
4096 single-stepping over a mode-changing instruction, if the
4097 CPSR heuristics are used. */
4099 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
4100 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
4105 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4106 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4107 NULL if an error occurs. BUF is freed. */
4110 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4111 int old_len, int new_len)
4113 gdb_byte *new_buf, *middle;
4114 int bytes_to_read = new_len - old_len;
4116 new_buf = xmalloc (new_len);
4117 memcpy (new_buf + bytes_to_read, buf, old_len);
4119 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4127 /* An IT block is at most the 2-byte IT instruction followed by
4128 four 4-byte instructions. The furthest back we must search to
4129 find an IT block that affects the current instruction is thus
4130 2 + 3 * 4 == 14 bytes. */
4131 #define MAX_IT_BLOCK_PREFIX 14
4133 /* Use a quick scan if there are more than this many bytes of
4135 #define IT_SCAN_THRESHOLD 32
4137 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4138 A breakpoint in an IT block may not be hit, depending on the
4141 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4145 CORE_ADDR boundary, func_start;
4146 int buf_len, buf2_len;
4147 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4148 int i, any, last_it, last_it_count;
4150 /* If we are using BKPT breakpoints, none of this is necessary. */
4151 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4154 /* ARM mode does not have this problem. */
4155 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4158 /* We are setting a breakpoint in Thumb code that could potentially
4159 contain an IT block. The first step is to find how much Thumb
4160 code there is; we do not need to read outside of known Thumb
4162 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4164 /* Thumb-2 code must have mapping symbols to have a chance. */
4167 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4169 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4170 && func_start > boundary)
4171 boundary = func_start;
4173 /* Search for a candidate IT instruction. We have to do some fancy
4174 footwork to distinguish a real IT instruction from the second
4175 half of a 32-bit instruction, but there is no need for that if
4176 there's no candidate. */
4177 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
4179 /* No room for an IT instruction. */
4182 buf = xmalloc (buf_len);
4183 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4186 for (i = 0; i < buf_len; i += 2)
4188 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4189 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4201 /* OK, the code bytes before this instruction contain at least one
4202 halfword which resembles an IT instruction. We know that it's
4203 Thumb code, but there are still two possibilities. Either the
4204 halfword really is an IT instruction, or it is the second half of
4205 a 32-bit Thumb instruction. The only way we can tell is to
4206 scan forwards from a known instruction boundary. */
4207 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
4211 /* There's a lot of code before this instruction. Start with an
4212 optimistic search; it's easy to recognize halfwords that can
4213 not be the start of a 32-bit instruction, and use that to
4214 lock on to the instruction boundaries. */
4215 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
4218 buf_len = IT_SCAN_THRESHOLD;
4221 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
4223 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4224 if (thumb_insn_size (inst1) == 2)
4231 /* At this point, if DEFINITE, BUF[I] is the first place we
4232 are sure that we know the instruction boundaries, and it is far
4233 enough from BPADDR that we could not miss an IT instruction
4234 affecting BPADDR. If ! DEFINITE, give up - start from a
4238 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4241 buf_len = bpaddr - boundary;
4247 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4250 buf_len = bpaddr - boundary;
4254 /* Scan forwards. Find the last IT instruction before BPADDR. */
4259 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4261 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4266 else if (inst1 & 0x0002)
4268 else if (inst1 & 0x0004)
4273 i += thumb_insn_size (inst1);
4279 /* There wasn't really an IT instruction after all. */
4282 if (last_it_count < 1)
4283 /* It was too far away. */
4286 /* This really is a trouble spot. Move the breakpoint to the IT
4288 return bpaddr - buf_len + last_it;
4291 /* ARM displaced stepping support.
4293 Generally ARM displaced stepping works as follows:
4295 1. When an instruction is to be single-stepped, it is first decoded by
4296 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
4297 Depending on the type of instruction, it is then copied to a scratch
4298 location, possibly in a modified form. The copy_* set of functions
4299 performs such modification, as necessary. A breakpoint is placed after
4300 the modified instruction in the scratch space to return control to GDB.
4301 Note in particular that instructions which modify the PC will no longer
4302 do so after modification.
4304 2. The instruction is single-stepped, by setting the PC to the scratch
4305 location address, and resuming. Control returns to GDB when the
4308 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4309 function used for the current instruction. This function's job is to
4310 put the CPU/memory state back to what it would have been if the
4311 instruction had been executed unmodified in its original location. */
4313 /* NOP instruction (mov r0, r0). */
4314 #define ARM_NOP 0xe1a00000
4316 /* Helper for register reads for displaced stepping. In particular, this
4317 returns the PC as it would be seen by the instruction at its original
4321 displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno)
4327 if (debug_displaced)
4328 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
4329 (unsigned long) from + 8);
4330 return (ULONGEST) from + 8; /* Pipeline offset. */
4334 regcache_cooked_read_unsigned (regs, regno, &ret);
4335 if (debug_displaced)
4336 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
4337 regno, (unsigned long) ret);
4343 displaced_in_arm_mode (struct regcache *regs)
4346 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4348 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4350 return (ps & t_bit) == 0;
4353 /* Write to the PC as from a branch instruction. */
4356 branch_write_pc (struct regcache *regs, ULONGEST val)
4358 if (displaced_in_arm_mode (regs))
4359 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4360 architecture versions < 6. */
4361 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3);
4363 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1);
4366 /* Write to the PC as from a branch-exchange instruction. */
4369 bx_write_pc (struct regcache *regs, ULONGEST val)
4372 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4374 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4378 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
4379 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
4381 else if ((val & 2) == 0)
4383 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4384 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
4388 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4389 mode, align dest to 4 bytes). */
4390 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4391 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4392 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
4396 /* Write to the PC as if from a load instruction. */
4399 load_write_pc (struct regcache *regs, ULONGEST val)
4401 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
4402 bx_write_pc (regs, val);
4404 branch_write_pc (regs, val);
4407 /* Write to the PC as if from an ALU instruction. */
4410 alu_write_pc (struct regcache *regs, ULONGEST val)
4412 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && displaced_in_arm_mode (regs))
4413 bx_write_pc (regs, val);
4415 branch_write_pc (regs, val);
4418 /* Helper for writing to registers for displaced stepping. Writing to the PC
4419 has a varying effects depending on the instruction which does the write:
4420 this is controlled by the WRITE_PC argument. */
4423 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4424 int regno, ULONGEST val, enum pc_write_style write_pc)
4428 if (debug_displaced)
4429 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
4430 (unsigned long) val);
4433 case BRANCH_WRITE_PC:
4434 branch_write_pc (regs, val);
4438 bx_write_pc (regs, val);
4442 load_write_pc (regs, val);
4446 alu_write_pc (regs, val);
4449 case CANNOT_WRITE_PC:
4450 warning (_("Instruction wrote to PC in an unexpected way when "
4451 "single-stepping"));
4455 internal_error (__FILE__, __LINE__,
4456 _("Invalid argument to displaced_write_reg"));
4459 dsc->wrote_to_pc = 1;
4463 if (debug_displaced)
4464 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
4465 regno, (unsigned long) val);
4466 regcache_cooked_write_unsigned (regs, regno, val);
4470 /* This function is used to concisely determine if an instruction INSN
4471 references PC. Register fields of interest in INSN should have the
4472 corresponding fields of BITMASK set to 0b1111. The function returns return 1
4473 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
4477 insn_references_pc (uint32_t insn, uint32_t bitmask)
4479 uint32_t lowbit = 1;
4481 while (bitmask != 0)
4485 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
4491 mask = lowbit * 0xf;
4493 if ((insn & mask) == mask)
4502 /* The simplest copy function. Many instructions have the same effect no
4503 matter what address they are executed at: in those cases, use this. */
4506 copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
4507 const char *iname, struct displaced_step_closure *dsc)
4509 if (debug_displaced)
4510 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
4511 "opcode/class '%s' unmodified\n", (unsigned long) insn,
4514 dsc->modinsn[0] = insn;
4519 /* Preload instructions with immediate offset. */
4522 cleanup_preload (struct gdbarch *gdbarch,
4523 struct regcache *regs, struct displaced_step_closure *dsc)
4525 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4526 if (!dsc->u.preload.immed)
4527 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4531 copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4532 struct displaced_step_closure *dsc)
4534 unsigned int rn = bits (insn, 16, 19);
4536 CORE_ADDR from = dsc->insn_addr;
4538 if (!insn_references_pc (insn, 0x000f0000ul))
4539 return copy_unmodified (gdbarch, insn, "preload", dsc);
4541 if (debug_displaced)
4542 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4543 (unsigned long) insn);
4545 /* Preload instructions:
4547 {pli/pld} [rn, #+/-imm]
4549 {pli/pld} [r0, #+/-imm]. */
4551 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
4552 rn_val = displaced_read_reg (regs, from, rn);
4553 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4555 dsc->u.preload.immed = 1;
4557 dsc->modinsn[0] = insn & 0xfff0ffff;
4559 dsc->cleanup = &cleanup_preload;
4564 /* Preload instructions with register offset. */
4567 copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4568 struct displaced_step_closure *dsc)
4570 unsigned int rn = bits (insn, 16, 19);
4571 unsigned int rm = bits (insn, 0, 3);
4572 ULONGEST rn_val, rm_val;
4573 CORE_ADDR from = dsc->insn_addr;
4575 if (!insn_references_pc (insn, 0x000f000ful))
4576 return copy_unmodified (gdbarch, insn, "preload reg", dsc);
4578 if (debug_displaced)
4579 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4580 (unsigned long) insn);
4582 /* Preload register-offset instructions:
4584 {pli/pld} [rn, rm {, shift}]
4586 {pli/pld} [r0, r1 {, shift}]. */
4588 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
4589 dsc->tmp[1] = displaced_read_reg (regs, from, 1);
4590 rn_val = displaced_read_reg (regs, from, rn);
4591 rm_val = displaced_read_reg (regs, from, rm);
4592 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4593 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
4595 dsc->u.preload.immed = 0;
4597 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
4599 dsc->cleanup = &cleanup_preload;
4604 /* Copy/cleanup coprocessor load and store instructions. */
4607 cleanup_copro_load_store (struct gdbarch *gdbarch,
4608 struct regcache *regs,
4609 struct displaced_step_closure *dsc)
4611 ULONGEST rn_val = displaced_read_reg (regs, dsc->insn_addr, 0);
4613 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4615 if (dsc->u.ldst.writeback)
4616 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
4620 copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
4621 struct regcache *regs,
4622 struct displaced_step_closure *dsc)
4624 unsigned int rn = bits (insn, 16, 19);
4626 CORE_ADDR from = dsc->insn_addr;
4628 if (!insn_references_pc (insn, 0x000f0000ul))
4629 return copy_unmodified (gdbarch, insn, "copro load/store", dsc);
4631 if (debug_displaced)
4632 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4633 "load/store insn %.8lx\n", (unsigned long) insn);
4635 /* Coprocessor load/store instructions:
4637 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4639 {stc/stc2} [r0, #+/-imm].
4641 ldc/ldc2 are handled identically. */
4643 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
4644 rn_val = displaced_read_reg (regs, from, rn);
4645 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4647 dsc->u.ldst.writeback = bit (insn, 25);
4648 dsc->u.ldst.rn = rn;
4650 dsc->modinsn[0] = insn & 0xfff0ffff;
4652 dsc->cleanup = &cleanup_copro_load_store;
4657 /* Clean up branch instructions (actually perform the branch, by setting
4661 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
4662 struct displaced_step_closure *dsc)
4664 ULONGEST from = dsc->insn_addr;
4665 uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM);
4666 int branch_taken = condition_true (dsc->u.branch.cond, status);
4667 enum pc_write_style write_pc = dsc->u.branch.exchange
4668 ? BX_WRITE_PC : BRANCH_WRITE_PC;
4673 if (dsc->u.branch.link)
4675 ULONGEST pc = displaced_read_reg (regs, from, 15);
4676 displaced_write_reg (regs, dsc, 14, pc - 4, CANNOT_WRITE_PC);
4679 displaced_write_reg (regs, dsc, 15, dsc->u.branch.dest, write_pc);
4682 /* Copy B/BL/BLX instructions with immediate destinations. */
4685 copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
4686 struct regcache *regs, struct displaced_step_closure *dsc)
4688 unsigned int cond = bits (insn, 28, 31);
4689 int exchange = (cond == 0xf);
4690 int link = exchange || bit (insn, 24);
4691 CORE_ADDR from = dsc->insn_addr;
4694 if (debug_displaced)
4695 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
4696 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
4697 (unsigned long) insn);
4699 /* Implement "BL<cond> <label>" as:
4701 Preparation: cond <- instruction condition
4702 Insn: mov r0, r0 (nop)
4703 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4705 B<cond> similar, but don't set r14 in cleanup. */
4708 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4709 then arrange the switch into Thumb mode. */
4710 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
4712 offset = bits (insn, 0, 23) << 2;
4714 if (bit (offset, 25))
4715 offset = offset | ~0x3ffffff;
4717 dsc->u.branch.cond = cond;
4718 dsc->u.branch.link = link;
4719 dsc->u.branch.exchange = exchange;
4720 dsc->u.branch.dest = from + 8 + offset;
4722 dsc->modinsn[0] = ARM_NOP;
4724 dsc->cleanup = &cleanup_branch;
4729 /* Copy BX/BLX with register-specified destinations. */
4732 copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
4733 struct regcache *regs, struct displaced_step_closure *dsc)
4735 unsigned int cond = bits (insn, 28, 31);
4738 int link = bit (insn, 5);
4739 unsigned int rm = bits (insn, 0, 3);
4740 CORE_ADDR from = dsc->insn_addr;
4742 if (debug_displaced)
4743 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s register insn "
4744 "%.8lx\n", (link) ? "blx" : "bx", (unsigned long) insn);
4746 /* Implement {BX,BLX}<cond> <reg>" as:
4748 Preparation: cond <- instruction condition
4749 Insn: mov r0, r0 (nop)
4750 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
4752 Don't set r14 in cleanup for BX. */
4754 dsc->u.branch.dest = displaced_read_reg (regs, from, rm);
4756 dsc->u.branch.cond = cond;
4757 dsc->u.branch.link = link;
4758 dsc->u.branch.exchange = 1;
4760 dsc->modinsn[0] = ARM_NOP;
4762 dsc->cleanup = &cleanup_branch;
4767 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
4770 cleanup_alu_imm (struct gdbarch *gdbarch,
4771 struct regcache *regs, struct displaced_step_closure *dsc)
4773 ULONGEST rd_val = displaced_read_reg (regs, dsc->insn_addr, 0);
4774 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4775 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4776 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
4780 copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4781 struct displaced_step_closure *dsc)
4783 unsigned int rn = bits (insn, 16, 19);
4784 unsigned int rd = bits (insn, 12, 15);
4785 unsigned int op = bits (insn, 21, 24);
4786 int is_mov = (op == 0xd);
4787 ULONGEST rd_val, rn_val;
4788 CORE_ADDR from = dsc->insn_addr;
4790 if (!insn_references_pc (insn, 0x000ff000ul))
4791 return copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
4793 if (debug_displaced)
4794 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
4795 "%.8lx\n", is_mov ? "move" : "ALU",
4796 (unsigned long) insn);
4798 /* Instruction is of form:
4800 <op><cond> rd, [rn,] #imm
4804 Preparation: tmp1, tmp2 <- r0, r1;
4806 Insn: <op><cond> r0, r1, #imm
4807 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
4810 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
4811 dsc->tmp[1] = displaced_read_reg (regs, from, 1);
4812 rn_val = displaced_read_reg (regs, from, rn);
4813 rd_val = displaced_read_reg (regs, from, rd);
4814 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
4815 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
4819 dsc->modinsn[0] = insn & 0xfff00fff;
4821 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
4823 dsc->cleanup = &cleanup_alu_imm;
4828 /* Copy/cleanup arithmetic/logic insns with register RHS. */
4831 cleanup_alu_reg (struct gdbarch *gdbarch,
4832 struct regcache *regs, struct displaced_step_closure *dsc)
4837 rd_val = displaced_read_reg (regs, dsc->insn_addr, 0);
4839 for (i = 0; i < 3; i++)
4840 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
4842 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
4846 copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4847 struct displaced_step_closure *dsc)
4849 unsigned int rn = bits (insn, 16, 19);
4850 unsigned int rm = bits (insn, 0, 3);
4851 unsigned int rd = bits (insn, 12, 15);
4852 unsigned int op = bits (insn, 21, 24);
4853 int is_mov = (op == 0xd);
4854 ULONGEST rd_val, rn_val, rm_val;
4855 CORE_ADDR from = dsc->insn_addr;
4857 if (!insn_references_pc (insn, 0x000ff00ful))
4858 return copy_unmodified (gdbarch, insn, "ALU reg", dsc);
4860 if (debug_displaced)
4861 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
4862 is_mov ? "move" : "ALU", (unsigned long) insn);
4864 /* Instruction is of form:
4866 <op><cond> rd, [rn,] rm [, <shift>]
4870 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
4871 r0, r1, r2 <- rd, rn, rm
4872 Insn: <op><cond> r0, r1, r2 [, <shift>]
4873 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
4876 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
4877 dsc->tmp[1] = displaced_read_reg (regs, from, 1);
4878 dsc->tmp[2] = displaced_read_reg (regs, from, 2);
4879 rd_val = displaced_read_reg (regs, from, rd);
4880 rn_val = displaced_read_reg (regs, from, rn);
4881 rm_val = displaced_read_reg (regs, from, rm);
4882 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
4883 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
4884 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
4888 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
4890 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
4892 dsc->cleanup = &cleanup_alu_reg;
4897 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
4900 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
4901 struct regcache *regs,
4902 struct displaced_step_closure *dsc)
4904 ULONGEST rd_val = displaced_read_reg (regs, dsc->insn_addr, 0);
4907 for (i = 0; i < 4; i++)
4908 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
4910 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
4914 copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
4915 struct regcache *regs, struct displaced_step_closure *dsc)
4917 unsigned int rn = bits (insn, 16, 19);
4918 unsigned int rm = bits (insn, 0, 3);
4919 unsigned int rd = bits (insn, 12, 15);
4920 unsigned int rs = bits (insn, 8, 11);
4921 unsigned int op = bits (insn, 21, 24);
4922 int is_mov = (op == 0xd), i;
4923 ULONGEST rd_val, rn_val, rm_val, rs_val;
4924 CORE_ADDR from = dsc->insn_addr;
4926 if (!insn_references_pc (insn, 0x000fff0ful))
4927 return copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
4929 if (debug_displaced)
4930 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
4931 "%.8lx\n", is_mov ? "move" : "ALU",
4932 (unsigned long) insn);
4934 /* Instruction is of form:
4936 <op><cond> rd, [rn,] rm, <shift> rs
4940 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
4941 r0, r1, r2, r3 <- rd, rn, rm, rs
4942 Insn: <op><cond> r0, r1, r2, <shift> r3
4944 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
4948 for (i = 0; i < 4; i++)
4949 dsc->tmp[i] = displaced_read_reg (regs, from, i);
4951 rd_val = displaced_read_reg (regs, from, rd);
4952 rn_val = displaced_read_reg (regs, from, rn);
4953 rm_val = displaced_read_reg (regs, from, rm);
4954 rs_val = displaced_read_reg (regs, from, rs);
4955 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
4956 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
4957 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
4958 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
4962 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
4964 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
4966 dsc->cleanup = &cleanup_alu_shifted_reg;
4971 /* Clean up load instructions. */
4974 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
4975 struct displaced_step_closure *dsc)
4977 ULONGEST rt_val, rt_val2 = 0, rn_val;
4978 CORE_ADDR from = dsc->insn_addr;
4980 rt_val = displaced_read_reg (regs, from, 0);
4981 if (dsc->u.ldst.xfersize == 8)
4982 rt_val2 = displaced_read_reg (regs, from, 1);
4983 rn_val = displaced_read_reg (regs, from, 2);
4985 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4986 if (dsc->u.ldst.xfersize > 4)
4987 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4988 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
4989 if (!dsc->u.ldst.immed)
4990 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
4992 /* Handle register writeback. */
4993 if (dsc->u.ldst.writeback)
4994 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
4995 /* Put result in right place. */
4996 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
4997 if (dsc->u.ldst.xfersize == 8)
4998 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5001 /* Clean up store instructions. */
5004 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5005 struct displaced_step_closure *dsc)
5007 CORE_ADDR from = dsc->insn_addr;
5008 ULONGEST rn_val = displaced_read_reg (regs, from, 2);
5010 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5011 if (dsc->u.ldst.xfersize > 4)
5012 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5013 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5014 if (!dsc->u.ldst.immed)
5015 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5016 if (!dsc->u.ldst.restore_r4)
5017 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5020 if (dsc->u.ldst.writeback)
5021 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5024 /* Copy "extra" load/store instructions. These are halfword/doubleword
5025 transfers, which have a different encoding to byte/word transfers. */
5028 copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
5029 struct regcache *regs, struct displaced_step_closure *dsc)
5031 unsigned int op1 = bits (insn, 20, 24);
5032 unsigned int op2 = bits (insn, 5, 6);
5033 unsigned int rt = bits (insn, 12, 15);
5034 unsigned int rn = bits (insn, 16, 19);
5035 unsigned int rm = bits (insn, 0, 3);
5036 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5037 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5038 int immed = (op1 & 0x4) != 0;
5040 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5041 CORE_ADDR from = dsc->insn_addr;
5043 if (!insn_references_pc (insn, 0x000ff00ful))
5044 return copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5046 if (debug_displaced)
5047 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5048 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
5049 (unsigned long) insn);
5051 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5054 internal_error (__FILE__, __LINE__,
5055 _("copy_extra_ld_st: instruction decode error"));
5057 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
5058 dsc->tmp[1] = displaced_read_reg (regs, from, 1);
5059 dsc->tmp[2] = displaced_read_reg (regs, from, 2);
5061 dsc->tmp[3] = displaced_read_reg (regs, from, 3);
5063 rt_val = displaced_read_reg (regs, from, rt);
5064 if (bytesize[opcode] == 8)
5065 rt_val2 = displaced_read_reg (regs, from, rt + 1);
5066 rn_val = displaced_read_reg (regs, from, rn);
5068 rm_val = displaced_read_reg (regs, from, rm);
5070 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5071 if (bytesize[opcode] == 8)
5072 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5073 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5075 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5078 dsc->u.ldst.xfersize = bytesize[opcode];
5079 dsc->u.ldst.rn = rn;
5080 dsc->u.ldst.immed = immed;
5081 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5082 dsc->u.ldst.restore_r4 = 0;
5085 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5087 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5088 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5090 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5092 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5093 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5095 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5100 /* Copy byte/word loads and stores. */
5103 copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
5104 struct regcache *regs,
5105 struct displaced_step_closure *dsc, int load, int byte,
5108 int immed = !bit (insn, 25);
5109 unsigned int rt = bits (insn, 12, 15);
5110 unsigned int rn = bits (insn, 16, 19);
5111 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
5112 ULONGEST rt_val, rn_val, rm_val = 0;
5113 CORE_ADDR from = dsc->insn_addr;
5115 if (!insn_references_pc (insn, 0x000ff00ful))
5116 return copy_unmodified (gdbarch, insn, "load/store", dsc);
5118 if (debug_displaced)
5119 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s%s insn %.8lx\n",
5120 load ? (byte ? "ldrb" : "ldr")
5121 : (byte ? "strb" : "str"), usermode ? "t" : "",
5122 (unsigned long) insn);
5124 dsc->tmp[0] = displaced_read_reg (regs, from, 0);
5125 dsc->tmp[2] = displaced_read_reg (regs, from, 2);
5127 dsc->tmp[3] = displaced_read_reg (regs, from, 3);
5129 dsc->tmp[4] = displaced_read_reg (regs, from, 4);
5131 rt_val = displaced_read_reg (regs, from, rt);
5132 rn_val = displaced_read_reg (regs, from, rn);
5134 rm_val = displaced_read_reg (regs, from, rm);
5136 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5137 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5139 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5142 dsc->u.ldst.xfersize = byte ? 1 : 4;
5143 dsc->u.ldst.rn = rn;
5144 dsc->u.ldst.immed = immed;
5145 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5147 /* To write PC we can do:
5149 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
5150 scratch+4: ldr r4, temp
5151 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
5152 scratch+12: add r4, r4, #8 (r4 = offset)
5153 scratch+16: add r0, r0, r4
5154 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
5157 Otherwise we don't know what value to write for PC, since the offset is
5158 architecture-dependent (sometimes PC+8, sometimes PC+12). */
5160 if (load || rt != 15)
5162 dsc->u.ldst.restore_r4 = 0;
5165 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5167 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5168 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5170 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5172 {ldr,str}[b]<cond> r0, [r2, r3]. */
5173 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5177 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5178 dsc->u.ldst.restore_r4 = 1;
5180 dsc->modinsn[0] = 0xe58ff014; /* str pc, [pc, #20]. */
5181 dsc->modinsn[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
5182 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
5183 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
5184 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
5188 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
5190 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
5192 dsc->modinsn[6] = 0x0; /* breakpoint location. */
5193 dsc->modinsn[7] = 0x0; /* scratch space. */
5198 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5203 /* Cleanup LDM instructions with fully-populated register list. This is an
5204 unfortunate corner case: it's impossible to implement correctly by modifying
5205 the instruction. The issue is as follows: we have an instruction,
5209 which we must rewrite to avoid loading PC. A possible solution would be to
5210 do the load in two halves, something like (with suitable cleanup
5214 ldm[id][ab] r8!, {r0-r7}
5216 ldm[id][ab] r8, {r7-r14}
5219 but at present there's no suitable place for <temp>, since the scratch space
5220 is overwritten before the cleanup routine is called. For now, we simply
5221 emulate the instruction. */
5224 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
5225 struct displaced_step_closure *dsc)
5227 ULONGEST from = dsc->insn_addr;
5228 int inc = dsc->u.block.increment;
5229 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
5230 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
5231 uint32_t regmask = dsc->u.block.regmask;
5232 int regno = inc ? 0 : 15;
5233 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
5234 int exception_return = dsc->u.block.load && dsc->u.block.user
5235 && (regmask & 0x8000) != 0;
5236 uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM);
5237 int do_transfer = condition_true (dsc->u.block.cond, status);
5238 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5243 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5244 sensible we can do here. Complain loudly. */
5245 if (exception_return)
5246 error (_("Cannot single-step exception return"));
5248 /* We don't handle any stores here for now. */
5249 gdb_assert (dsc->u.block.load != 0);
5251 if (debug_displaced)
5252 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
5253 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
5254 dsc->u.block.increment ? "inc" : "dec",
5255 dsc->u.block.before ? "before" : "after");
5262 while (regno <= 15 && (regmask & (1 << regno)) == 0)
5265 while (regno >= 0 && (regmask & (1 << regno)) == 0)
5268 xfer_addr += bump_before;
5270 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
5271 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
5273 xfer_addr += bump_after;
5275 regmask &= ~(1 << regno);
5278 if (dsc->u.block.writeback)
5279 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
5283 /* Clean up an STM which included the PC in the register list. */
5286 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
5287 struct displaced_step_closure *dsc)
5289 ULONGEST from = dsc->insn_addr;
5290 uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM);
5291 int store_executed = condition_true (dsc->u.block.cond, status);
5292 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
5293 CORE_ADDR stm_insn_addr;
5296 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5298 /* If condition code fails, there's nothing else to do. */
5299 if (!store_executed)
5302 if (dsc->u.block.increment)
5304 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
5306 if (dsc->u.block.before)
5311 pc_stored_at = dsc->u.block.xfer_addr;
5313 if (dsc->u.block.before)
5317 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
5318 stm_insn_addr = dsc->scratch_base;
5319 offset = pc_val - stm_insn_addr;
5321 if (debug_displaced)
5322 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
5323 "STM instruction\n", offset);
5325 /* Rewrite the stored PC to the proper value for the non-displaced original
5327 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
5328 dsc->insn_addr + offset);
5331 /* Clean up an LDM which includes the PC in the register list. We clumped all
5332 the registers in the transferred list into a contiguous range r0...rX (to
5333 avoid loading PC directly and losing control of the debugged program), so we
5334 must undo that here. */
5337 cleanup_block_load_pc (struct gdbarch *gdbarch,
5338 struct regcache *regs,
5339 struct displaced_step_closure *dsc)
5341 ULONGEST from = dsc->insn_addr;
5342 uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM);
5343 int load_executed = condition_true (dsc->u.block.cond, status), i;
5344 unsigned int mask = dsc->u.block.regmask, write_reg = 15;
5345 unsigned int regs_loaded = bitcount (mask);
5346 unsigned int num_to_shuffle = regs_loaded, clobbered;
5348 /* The method employed here will fail if the register list is fully populated
5349 (we need to avoid loading PC directly). */
5350 gdb_assert (num_to_shuffle < 16);
5355 clobbered = (1 << num_to_shuffle) - 1;
5357 while (num_to_shuffle > 0)
5359 if ((mask & (1 << write_reg)) != 0)
5361 unsigned int read_reg = num_to_shuffle - 1;
5363 if (read_reg != write_reg)
5365 ULONGEST rval = displaced_read_reg (regs, from, read_reg);
5366 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
5367 if (debug_displaced)
5368 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
5369 "loaded register r%d to r%d\n"), read_reg,
5372 else if (debug_displaced)
5373 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
5374 "r%d already in the right place\n"),
5377 clobbered &= ~(1 << write_reg);
5385 /* Restore any registers we scribbled over. */
5386 for (write_reg = 0; clobbered != 0; write_reg++)
5388 if ((clobbered & (1 << write_reg)) != 0)
5390 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
5392 if (debug_displaced)
5393 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
5394 "clobbered register r%d\n"), write_reg);
5395 clobbered &= ~(1 << write_reg);
5399 /* Perform register writeback manually. */
5400 if (dsc->u.block.writeback)
5402 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
5404 if (dsc->u.block.increment)
5405 new_rn_val += regs_loaded * 4;
5407 new_rn_val -= regs_loaded * 4;
5409 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
5414 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
5415 in user-level code (in particular exception return, ldm rn, {...pc}^). */
5418 copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5419 struct displaced_step_closure *dsc)
5421 int load = bit (insn, 20);
5422 int user = bit (insn, 22);
5423 int increment = bit (insn, 23);
5424 int before = bit (insn, 24);
5425 int writeback = bit (insn, 21);
5426 int rn = bits (insn, 16, 19);
5427 CORE_ADDR from = dsc->insn_addr;
5429 /* Block transfers which don't mention PC can be run directly out-of-line. */
5430 if (rn != 15 && (insn & 0x8000) == 0)
5431 return copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
5435 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
5436 return copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
5439 if (debug_displaced)
5440 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
5441 "%.8lx\n", (unsigned long) insn);
5443 dsc->u.block.xfer_addr = displaced_read_reg (regs, from, rn);
5444 dsc->u.block.rn = rn;
5446 dsc->u.block.load = load;
5447 dsc->u.block.user = user;
5448 dsc->u.block.increment = increment;
5449 dsc->u.block.before = before;
5450 dsc->u.block.writeback = writeback;
5451 dsc->u.block.cond = bits (insn, 28, 31);
5453 dsc->u.block.regmask = insn & 0xffff;
5457 if ((insn & 0xffff) == 0xffff)
5459 /* LDM with a fully-populated register list. This case is
5460 particularly tricky. Implement for now by fully emulating the
5461 instruction (which might not behave perfectly in all cases, but
5462 these instructions should be rare enough for that not to matter
5464 dsc->modinsn[0] = ARM_NOP;
5466 dsc->cleanup = &cleanup_block_load_all;
5470 /* LDM of a list of registers which includes PC. Implement by
5471 rewriting the list of registers to be transferred into a
5472 contiguous chunk r0...rX before doing the transfer, then shuffling
5473 registers into the correct places in the cleanup routine. */
5474 unsigned int regmask = insn & 0xffff;
5475 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
5476 unsigned int to = 0, from = 0, i, new_rn;
5478 for (i = 0; i < num_in_list; i++)
5479 dsc->tmp[i] = displaced_read_reg (regs, from, i);
5481 /* Writeback makes things complicated. We need to avoid clobbering
5482 the base register with one of the registers in our modified
5483 register list, but just using a different register can't work in
5486 ldm r14!, {r0-r13,pc}
5488 which would need to be rewritten as:
5492 but that can't work, because there's no free register for N.
5494 Solve this by turning off the writeback bit, and emulating
5495 writeback manually in the cleanup routine. */
5500 new_regmask = (1 << num_in_list) - 1;
5502 if (debug_displaced)
5503 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
5504 "{..., pc}: original reg list %.4x, modified "
5505 "list %.4x\n"), rn, writeback ? "!" : "",
5506 (int) insn & 0xffff, new_regmask);
5508 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
5510 dsc->cleanup = &cleanup_block_load_pc;
5515 /* STM of a list of registers which includes PC. Run the instruction
5516 as-is, but out of line: this will store the wrong value for the PC,
5517 so we must manually fix up the memory in the cleanup routine.
5518 Doing things this way has the advantage that we can auto-detect
5519 the offset of the PC write (which is architecture-dependent) in
5520 the cleanup routine. */
5521 dsc->modinsn[0] = insn;
5523 dsc->cleanup = &cleanup_block_store_pc;
5529 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
5530 for Linux, where some SVC instructions must be treated specially. */
5533 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
5534 struct displaced_step_closure *dsc)
5536 CORE_ADDR from = dsc->insn_addr;
5537 CORE_ADDR resume_addr = from + 4;
5539 if (debug_displaced)
5540 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
5541 "%.8lx\n", (unsigned long) resume_addr);
5543 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
5547 copy_svc (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
5548 struct regcache *regs, struct displaced_step_closure *dsc)
5550 CORE_ADDR from = dsc->insn_addr;
5552 /* Allow OS-specific code to override SVC handling. */
5553 if (dsc->u.svc.copy_svc_os)
5554 return dsc->u.svc.copy_svc_os (gdbarch, insn, to, regs, dsc);
5556 if (debug_displaced)
5557 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
5558 (unsigned long) insn);
5560 /* Preparation: none.
5561 Insn: unmodified svc.
5562 Cleanup: pc <- insn_addr + 4. */
5564 dsc->modinsn[0] = insn;
5566 dsc->cleanup = &cleanup_svc;
5567 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
5569 dsc->wrote_to_pc = 1;
5574 /* Copy undefined instructions. */
5577 copy_undef (struct gdbarch *gdbarch, uint32_t insn,
5578 struct displaced_step_closure *dsc)
5580 if (debug_displaced)
5581 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn %.8lx\n",
5582 (unsigned long) insn);
5584 dsc->modinsn[0] = insn;
5589 /* Copy unpredictable instructions. */
5592 copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
5593 struct displaced_step_closure *dsc)
5595 if (debug_displaced)
5596 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
5597 "%.8lx\n", (unsigned long) insn);
5599 dsc->modinsn[0] = insn;
5604 /* The decode_* functions are instruction decoding helpers. They mostly follow
5605 the presentation in the ARM ARM. */
5608 decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
5609 struct regcache *regs,
5610 struct displaced_step_closure *dsc)
5612 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
5613 unsigned int rn = bits (insn, 16, 19);
5615 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
5616 return copy_unmodified (gdbarch, insn, "cps", dsc);
5617 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
5618 return copy_unmodified (gdbarch, insn, "setend", dsc);
5619 else if ((op1 & 0x60) == 0x20)
5620 return copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
5621 else if ((op1 & 0x71) == 0x40)
5622 return copy_unmodified (gdbarch, insn, "neon elt/struct load/store", dsc);
5623 else if ((op1 & 0x77) == 0x41)
5624 return copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
5625 else if ((op1 & 0x77) == 0x45)
5626 return copy_preload (gdbarch, insn, regs, dsc); /* pli. */
5627 else if ((op1 & 0x77) == 0x51)
5630 return copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
5632 return copy_unpred (gdbarch, insn, dsc);
5634 else if ((op1 & 0x77) == 0x55)
5635 return copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
5636 else if (op1 == 0x57)
5639 case 0x1: return copy_unmodified (gdbarch, insn, "clrex", dsc);
5640 case 0x4: return copy_unmodified (gdbarch, insn, "dsb", dsc);
5641 case 0x5: return copy_unmodified (gdbarch, insn, "dmb", dsc);
5642 case 0x6: return copy_unmodified (gdbarch, insn, "isb", dsc);
5643 default: return copy_unpred (gdbarch, insn, dsc);
5645 else if ((op1 & 0x63) == 0x43)
5646 return copy_unpred (gdbarch, insn, dsc);
5647 else if ((op2 & 0x1) == 0x0)
5648 switch (op1 & ~0x80)
5651 return copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
5653 return copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
5654 case 0x71: case 0x75:
5656 return copy_preload_reg (gdbarch, insn, regs, dsc);
5657 case 0x63: case 0x67: case 0x73: case 0x77:
5658 return copy_unpred (gdbarch, insn, dsc);
5660 return copy_undef (gdbarch, insn, dsc);
5663 return copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
5667 decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
5668 struct regcache *regs, struct displaced_step_closure *dsc)
5670 if (bit (insn, 27) == 0)
5671 return decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
5672 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
5673 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
5676 return copy_unmodified (gdbarch, insn, "srs", dsc);
5679 return copy_unmodified (gdbarch, insn, "rfe", dsc);
5681 case 0x4: case 0x5: case 0x6: case 0x7:
5682 return copy_b_bl_blx (gdbarch, insn, regs, dsc);
5685 switch ((insn & 0xe00000) >> 21)
5687 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
5689 return copy_copro_load_store (gdbarch, insn, regs, dsc);
5692 return copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
5695 return copy_undef (gdbarch, insn, dsc);
5700 int rn_f = (bits (insn, 16, 19) == 0xf);
5701 switch ((insn & 0xe00000) >> 21)
5704 /* ldc/ldc2 imm (undefined for rn == pc). */
5705 return rn_f ? copy_undef (gdbarch, insn, dsc)
5706 : copy_copro_load_store (gdbarch, insn, regs, dsc);
5709 return copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
5711 case 0x4: case 0x5: case 0x6: case 0x7:
5712 /* ldc/ldc2 lit (undefined for rn != pc). */
5713 return rn_f ? copy_copro_load_store (gdbarch, insn, regs, dsc)
5714 : copy_undef (gdbarch, insn, dsc);
5717 return copy_undef (gdbarch, insn, dsc);
5722 return copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
5725 if (bits (insn, 16, 19) == 0xf)
5727 return copy_copro_load_store (gdbarch, insn, regs, dsc);
5729 return copy_undef (gdbarch, insn, dsc);
5733 return copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
5735 return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
5739 return copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
5741 return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
5744 return copy_undef (gdbarch, insn, dsc);
5748 /* Decode miscellaneous instructions in dp/misc encoding space. */
5751 decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
5752 struct regcache *regs, struct displaced_step_closure *dsc)
5754 unsigned int op2 = bits (insn, 4, 6);
5755 unsigned int op = bits (insn, 21, 22);
5756 unsigned int op1 = bits (insn, 16, 19);
5761 return copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
5764 if (op == 0x1) /* bx. */
5765 return copy_bx_blx_reg (gdbarch, insn, regs, dsc);
5767 return copy_unmodified (gdbarch, insn, "clz", dsc);
5769 return copy_undef (gdbarch, insn, dsc);
5773 /* Not really supported. */
5774 return copy_unmodified (gdbarch, insn, "bxj", dsc);
5776 return copy_undef (gdbarch, insn, dsc);
5780 return copy_bx_blx_reg (gdbarch, insn, regs, dsc); /* blx register. */
5782 return copy_undef (gdbarch, insn, dsc);
5785 return copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
5789 return copy_unmodified (gdbarch, insn, "bkpt", dsc);
5791 /* Not really supported. */
5792 return copy_unmodified (gdbarch, insn, "smc", dsc);
5795 return copy_undef (gdbarch, insn, dsc);
5800 decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5801 struct displaced_step_closure *dsc)
5804 switch (bits (insn, 20, 24))
5807 return copy_unmodified (gdbarch, insn, "movw", dsc);
5810 return copy_unmodified (gdbarch, insn, "movt", dsc);
5812 case 0x12: case 0x16:
5813 return copy_unmodified (gdbarch, insn, "msr imm", dsc);
5816 return copy_alu_imm (gdbarch, insn, regs, dsc);
5820 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
5822 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
5823 return copy_alu_reg (gdbarch, insn, regs, dsc);
5824 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
5825 return copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
5826 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
5827 return decode_miscellaneous (gdbarch, insn, regs, dsc);
5828 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
5829 return copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
5830 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
5831 return copy_unmodified (gdbarch, insn, "mul/mla", dsc);
5832 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
5833 return copy_unmodified (gdbarch, insn, "synch", dsc);
5834 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
5835 /* 2nd arg means "unpriveleged". */
5836 return copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
5840 /* Should be unreachable. */
5845 decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
5846 struct regcache *regs,
5847 struct displaced_step_closure *dsc)
5849 int a = bit (insn, 25), b = bit (insn, 4);
5850 uint32_t op1 = bits (insn, 20, 24);
5851 int rn_f = bits (insn, 16, 19) == 0xf;
5853 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
5854 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
5855 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 0);
5856 else if ((!a && (op1 & 0x17) == 0x02)
5857 || (a && (op1 & 0x17) == 0x02 && !b))
5858 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 1);
5859 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
5860 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
5861 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 0);
5862 else if ((!a && (op1 & 0x17) == 0x03)
5863 || (a && (op1 & 0x17) == 0x03 && !b))
5864 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 1);
5865 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
5866 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
5867 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
5868 else if ((!a && (op1 & 0x17) == 0x06)
5869 || (a && (op1 & 0x17) == 0x06 && !b))
5870 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
5871 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
5872 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
5873 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
5874 else if ((!a && (op1 & 0x17) == 0x07)
5875 || (a && (op1 & 0x17) == 0x07 && !b))
5876 return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
5878 /* Should be unreachable. */
5883 decode_media (struct gdbarch *gdbarch, uint32_t insn,
5884 struct displaced_step_closure *dsc)
5886 switch (bits (insn, 20, 24))
5888 case 0x00: case 0x01: case 0x02: case 0x03:
5889 return copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
5891 case 0x04: case 0x05: case 0x06: case 0x07:
5892 return copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
5894 case 0x08: case 0x09: case 0x0a: case 0x0b:
5895 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5896 return copy_unmodified (gdbarch, insn,
5897 "decode/pack/unpack/saturate/reverse", dsc);
5900 if (bits (insn, 5, 7) == 0) /* op2. */
5902 if (bits (insn, 12, 15) == 0xf)
5903 return copy_unmodified (gdbarch, insn, "usad8", dsc);
5905 return copy_unmodified (gdbarch, insn, "usada8", dsc);
5908 return copy_undef (gdbarch, insn, dsc);
5910 case 0x1a: case 0x1b:
5911 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
5912 return copy_unmodified (gdbarch, insn, "sbfx", dsc);
5914 return copy_undef (gdbarch, insn, dsc);
5916 case 0x1c: case 0x1d:
5917 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
5919 if (bits (insn, 0, 3) == 0xf)
5920 return copy_unmodified (gdbarch, insn, "bfc", dsc);
5922 return copy_unmodified (gdbarch, insn, "bfi", dsc);
5925 return copy_undef (gdbarch, insn, dsc);
5927 case 0x1e: case 0x1f:
5928 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
5929 return copy_unmodified (gdbarch, insn, "ubfx", dsc);
5931 return copy_undef (gdbarch, insn, dsc);
5934 /* Should be unreachable. */
5939 decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
5940 struct regcache *regs, struct displaced_step_closure *dsc)
5943 return copy_b_bl_blx (gdbarch, insn, regs, dsc);
5945 return copy_block_xfer (gdbarch, insn, regs, dsc);
5949 decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
5950 struct regcache *regs, struct displaced_step_closure *dsc)
5952 unsigned int opcode = bits (insn, 20, 24);
5956 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
5957 return copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
5959 case 0x08: case 0x0a: case 0x0c: case 0x0e:
5960 case 0x12: case 0x16:
5961 return copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
5963 case 0x09: case 0x0b: case 0x0d: case 0x0f:
5964 case 0x13: case 0x17:
5965 return copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
5967 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
5968 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
5969 /* Note: no writeback for these instructions. Bit 25 will always be
5970 zero though (via caller), so the following works OK. */
5971 return copy_copro_load_store (gdbarch, insn, regs, dsc);
5974 /* Should be unreachable. */
5979 decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
5980 struct regcache *regs, struct displaced_step_closure *dsc)
5982 unsigned int op1 = bits (insn, 20, 25);
5983 int op = bit (insn, 4);
5984 unsigned int coproc = bits (insn, 8, 11);
5985 unsigned int rn = bits (insn, 16, 19);
5987 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
5988 return decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
5989 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
5990 && (coproc & 0xe) != 0xa)
5992 return copy_copro_load_store (gdbarch, insn, regs, dsc);
5993 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
5994 && (coproc & 0xe) != 0xa)
5995 /* ldc/ldc2 imm/lit. */
5996 return copy_copro_load_store (gdbarch, insn, regs, dsc);
5997 else if ((op1 & 0x3e) == 0x00)
5998 return copy_undef (gdbarch, insn, dsc);
5999 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6000 return copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6001 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6002 return copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6003 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6004 return copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6005 else if ((op1 & 0x30) == 0x20 && !op)
6007 if ((coproc & 0xe) == 0xa)
6008 return copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6010 return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6012 else if ((op1 & 0x30) == 0x20 && op)
6013 return copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6014 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6015 return copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6016 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6017 return copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6018 else if ((op1 & 0x30) == 0x30)
6019 return copy_svc (gdbarch, insn, to, regs, dsc);
6021 return copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6025 arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
6026 CORE_ADDR from, CORE_ADDR to, struct regcache *regs,
6027 struct displaced_step_closure *dsc)
6031 if (!displaced_in_arm_mode (regs))
6032 error (_("Displaced stepping is only supported in ARM mode"));
6034 /* Most displaced instructions use a 1-instruction scratch space, so set this
6035 here and override below if/when necessary. */
6037 dsc->insn_addr = from;
6038 dsc->scratch_base = to;
6039 dsc->cleanup = NULL;
6040 dsc->wrote_to_pc = 0;
6042 if ((insn & 0xf0000000) == 0xf0000000)
6043 err = decode_unconditional (gdbarch, insn, regs, dsc);
6044 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
6046 case 0x0: case 0x1: case 0x2: case 0x3:
6047 err = decode_dp_misc (gdbarch, insn, regs, dsc);
6050 case 0x4: case 0x5: case 0x6:
6051 err = decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
6055 err = decode_media (gdbarch, insn, dsc);
6058 case 0x8: case 0x9: case 0xa: case 0xb:
6059 err = decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
6062 case 0xc: case 0xd: case 0xe: case 0xf:
6063 err = decode_svc_copro (gdbarch, insn, to, regs, dsc);
6068 internal_error (__FILE__, __LINE__,
6069 _("arm_process_displaced_insn: Instruction decode error"));
6072 /* Actually set up the scratch space for a displaced instruction. */
6075 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
6076 CORE_ADDR to, struct displaced_step_closure *dsc)
6078 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6080 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
6082 /* Poke modified instruction(s). */
6083 for (i = 0; i < dsc->numinsns; i++)
6085 if (debug_displaced)
6086 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn %.8lx at "
6087 "%.8lx\n", (unsigned long) dsc->modinsn[i],
6088 (unsigned long) to + i * 4);
6089 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
6093 /* Put breakpoint afterwards. */
6094 write_memory (to + dsc->numinsns * 4, tdep->arm_breakpoint,
6095 tdep->arm_breakpoint_size);
6097 if (debug_displaced)
6098 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
6099 paddress (gdbarch, from), paddress (gdbarch, to));
6102 /* Entry point for copying an instruction into scratch space for displaced
6105 struct displaced_step_closure *
6106 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
6107 CORE_ADDR from, CORE_ADDR to,
6108 struct regcache *regs)
6110 struct displaced_step_closure *dsc
6111 = xmalloc (sizeof (struct displaced_step_closure));
6112 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
6113 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
6115 if (debug_displaced)
6116 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
6117 "at %.8lx\n", (unsigned long) insn,
6118 (unsigned long) from);
6120 arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc);
6121 arm_displaced_init_closure (gdbarch, from, to, dsc);
6126 /* Entry point for cleaning things up after a displaced instruction has been
6130 arm_displaced_step_fixup (struct gdbarch *gdbarch,
6131 struct displaced_step_closure *dsc,
6132 CORE_ADDR from, CORE_ADDR to,
6133 struct regcache *regs)
6136 dsc->cleanup (gdbarch, regs, dsc);
6138 if (!dsc->wrote_to_pc)
6139 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, dsc->insn_addr + 4);
6142 #include "bfd-in2.h"
6143 #include "libcoff.h"
6146 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
6148 struct gdbarch *gdbarch = info->application_data;
6150 if (arm_pc_is_thumb (gdbarch, memaddr))
6152 static asymbol *asym;
6153 static combined_entry_type ce;
6154 static struct coff_symbol_struct csym;
6155 static struct bfd fake_bfd;
6156 static bfd_target fake_target;
6158 if (csym.native == NULL)
6160 /* Create a fake symbol vector containing a Thumb symbol.
6161 This is solely so that the code in print_insn_little_arm()
6162 and print_insn_big_arm() in opcodes/arm-dis.c will detect
6163 the presence of a Thumb symbol and switch to decoding
6164 Thumb instructions. */
6166 fake_target.flavour = bfd_target_coff_flavour;
6167 fake_bfd.xvec = &fake_target;
6168 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
6170 csym.symbol.the_bfd = &fake_bfd;
6171 csym.symbol.name = "fake";
6172 asym = (asymbol *) & csym;
6175 memaddr = UNMAKE_THUMB_ADDR (memaddr);
6176 info->symbols = &asym;
6179 info->symbols = NULL;
6181 if (info->endian == BFD_ENDIAN_BIG)
6182 return print_insn_big_arm (memaddr, info);
6184 return print_insn_little_arm (memaddr, info);
6187 /* The following define instruction sequences that will cause ARM
6188 cpu's to take an undefined instruction trap. These are used to
6189 signal a breakpoint to GDB.
6191 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
6192 modes. A different instruction is required for each mode. The ARM
6193 cpu's can also be big or little endian. Thus four different
6194 instructions are needed to support all cases.
6196 Note: ARMv4 defines several new instructions that will take the
6197 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
6198 not in fact add the new instructions. The new undefined
6199 instructions in ARMv4 are all instructions that had no defined
6200 behaviour in earlier chips. There is no guarantee that they will
6201 raise an exception, but may be treated as NOP's. In practice, it
6202 may only safe to rely on instructions matching:
6204 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
6205 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
6206 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
6208 Even this may only true if the condition predicate is true. The
6209 following use a condition predicate of ALWAYS so it is always TRUE.
6211 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
6212 and NetBSD all use a software interrupt rather than an undefined
6213 instruction to force a trap. This can be handled by by the
6214 abi-specific code during establishment of the gdbarch vector. */
6216 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
6217 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
6218 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
6219 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
6221 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
6222 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
6223 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
6224 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
6226 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
6227 the program counter value to determine whether a 16-bit or 32-bit
6228 breakpoint should be used. It returns a pointer to a string of
6229 bytes that encode a breakpoint instruction, stores the length of
6230 the string to *lenptr, and adjusts the program counter (if
6231 necessary) to point to the actual memory location where the
6232 breakpoint should be inserted. */
6234 static const unsigned char *
6235 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
6237 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6238 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
6240 if (arm_pc_is_thumb (gdbarch, *pcptr))
6242 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
6244 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
6245 check whether we are replacing a 32-bit instruction. */
6246 if (tdep->thumb2_breakpoint != NULL)
6249 if (target_read_memory (*pcptr, buf, 2) == 0)
6251 unsigned short inst1;
6252 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
6253 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
6255 *lenptr = tdep->thumb2_breakpoint_size;
6256 return tdep->thumb2_breakpoint;
6261 *lenptr = tdep->thumb_breakpoint_size;
6262 return tdep->thumb_breakpoint;
6266 *lenptr = tdep->arm_breakpoint_size;
6267 return tdep->arm_breakpoint;
6272 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
6275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6277 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
6279 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
6280 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
6281 that this is not confused with a 32-bit ARM breakpoint. */
6285 /* Extract from an array REGBUF containing the (raw) register state a
6286 function return value of type TYPE, and copy that, in virtual
6287 format, into VALBUF. */
6290 arm_extract_return_value (struct type *type, struct regcache *regs,
6293 struct gdbarch *gdbarch = get_regcache_arch (regs);
6294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6296 if (TYPE_CODE_FLT == TYPE_CODE (type))
6298 switch (gdbarch_tdep (gdbarch)->fp_model)
6302 /* The value is in register F0 in internal format. We need to
6303 extract the raw value and then convert it to the desired
6305 bfd_byte tmpbuf[FP_REGISTER_SIZE];
6307 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
6308 convert_from_extended (floatformat_from_type (type), tmpbuf,
6309 valbuf, gdbarch_byte_order (gdbarch));
6313 case ARM_FLOAT_SOFT_FPA:
6314 case ARM_FLOAT_SOFT_VFP:
6315 /* ARM_FLOAT_VFP can arise if this is a variadic function so
6316 not using the VFP ABI code. */
6318 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
6319 if (TYPE_LENGTH (type) > 4)
6320 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
6321 valbuf + INT_REGISTER_SIZE);
6326 (__FILE__, __LINE__,
6327 _("arm_extract_return_value: Floating point model not supported"));
6331 else if (TYPE_CODE (type) == TYPE_CODE_INT
6332 || TYPE_CODE (type) == TYPE_CODE_CHAR
6333 || TYPE_CODE (type) == TYPE_CODE_BOOL
6334 || TYPE_CODE (type) == TYPE_CODE_PTR
6335 || TYPE_CODE (type) == TYPE_CODE_REF
6336 || TYPE_CODE (type) == TYPE_CODE_ENUM)
6338 /* If the the type is a plain integer, then the access is
6339 straight-forward. Otherwise we have to play around a bit more. */
6340 int len = TYPE_LENGTH (type);
6341 int regno = ARM_A1_REGNUM;
6346 /* By using store_unsigned_integer we avoid having to do
6347 anything special for small big-endian values. */
6348 regcache_cooked_read_unsigned (regs, regno++, &tmp);
6349 store_unsigned_integer (valbuf,
6350 (len > INT_REGISTER_SIZE
6351 ? INT_REGISTER_SIZE : len),
6353 len -= INT_REGISTER_SIZE;
6354 valbuf += INT_REGISTER_SIZE;
6359 /* For a structure or union the behaviour is as if the value had
6360 been stored to word-aligned memory and then loaded into
6361 registers with 32-bit load instruction(s). */
6362 int len = TYPE_LENGTH (type);
6363 int regno = ARM_A1_REGNUM;
6364 bfd_byte tmpbuf[INT_REGISTER_SIZE];
6368 regcache_cooked_read (regs, regno++, tmpbuf);
6369 memcpy (valbuf, tmpbuf,
6370 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
6371 len -= INT_REGISTER_SIZE;
6372 valbuf += INT_REGISTER_SIZE;
6378 /* Will a function return an aggregate type in memory or in a
6379 register? Return 0 if an aggregate type can be returned in a
6380 register, 1 if it must be returned in memory. */
6383 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
6386 enum type_code code;
6388 CHECK_TYPEDEF (type);
6390 /* In the ARM ABI, "integer" like aggregate types are returned in
6391 registers. For an aggregate type to be integer like, its size
6392 must be less than or equal to INT_REGISTER_SIZE and the
6393 offset of each addressable subfield must be zero. Note that bit
6394 fields are not addressable, and all addressable subfields of
6395 unions always start at offset zero.
6397 This function is based on the behaviour of GCC 2.95.1.
6398 See: gcc/arm.c: arm_return_in_memory() for details.
6400 Note: All versions of GCC before GCC 2.95.2 do not set up the
6401 parameters correctly for a function returning the following
6402 structure: struct { float f;}; This should be returned in memory,
6403 not a register. Richard Earnshaw sent me a patch, but I do not
6404 know of any way to detect if a function like the above has been
6405 compiled with the correct calling convention. */
6407 /* All aggregate types that won't fit in a register must be returned
6409 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
6414 /* The AAPCS says all aggregates not larger than a word are returned
6416 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
6419 /* The only aggregate types that can be returned in a register are
6420 structs and unions. Arrays must be returned in memory. */
6421 code = TYPE_CODE (type);
6422 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
6427 /* Assume all other aggregate types can be returned in a register.
6428 Run a check for structures, unions and arrays. */
6431 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
6434 /* Need to check if this struct/union is "integer" like. For
6435 this to be true, its size must be less than or equal to
6436 INT_REGISTER_SIZE and the offset of each addressable
6437 subfield must be zero. Note that bit fields are not
6438 addressable, and unions always start at offset zero. If any
6439 of the subfields is a floating point type, the struct/union
6440 cannot be an integer type. */
6442 /* For each field in the object, check:
6443 1) Is it FP? --> yes, nRc = 1;
6444 2) Is it addressable (bitpos != 0) and
6445 not packed (bitsize == 0)?
6449 for (i = 0; i < TYPE_NFIELDS (type); i++)
6451 enum type_code field_type_code;
6452 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
6454 /* Is it a floating point type field? */
6455 if (field_type_code == TYPE_CODE_FLT)
6461 /* If bitpos != 0, then we have to care about it. */
6462 if (TYPE_FIELD_BITPOS (type, i) != 0)
6464 /* Bitfields are not addressable. If the field bitsize is
6465 zero, then the field is not packed. Hence it cannot be
6466 a bitfield or any other packed type. */
6467 if (TYPE_FIELD_BITSIZE (type, i) == 0)
6479 /* Write into appropriate registers a function return value of type
6480 TYPE, given in virtual format. */
6483 arm_store_return_value (struct type *type, struct regcache *regs,
6484 const gdb_byte *valbuf)
6486 struct gdbarch *gdbarch = get_regcache_arch (regs);
6487 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6489 if (TYPE_CODE (type) == TYPE_CODE_FLT)
6491 char buf[MAX_REGISTER_SIZE];
6493 switch (gdbarch_tdep (gdbarch)->fp_model)
6497 convert_to_extended (floatformat_from_type (type), buf, valbuf,
6498 gdbarch_byte_order (gdbarch));
6499 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
6502 case ARM_FLOAT_SOFT_FPA:
6503 case ARM_FLOAT_SOFT_VFP:
6504 /* ARM_FLOAT_VFP can arise if this is a variadic function so
6505 not using the VFP ABI code. */
6507 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
6508 if (TYPE_LENGTH (type) > 4)
6509 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
6510 valbuf + INT_REGISTER_SIZE);
6515 (__FILE__, __LINE__,
6516 _("arm_store_return_value: Floating point model not supported"));
6520 else if (TYPE_CODE (type) == TYPE_CODE_INT
6521 || TYPE_CODE (type) == TYPE_CODE_CHAR
6522 || TYPE_CODE (type) == TYPE_CODE_BOOL
6523 || TYPE_CODE (type) == TYPE_CODE_PTR
6524 || TYPE_CODE (type) == TYPE_CODE_REF
6525 || TYPE_CODE (type) == TYPE_CODE_ENUM)
6527 if (TYPE_LENGTH (type) <= 4)
6529 /* Values of one word or less are zero/sign-extended and
6531 bfd_byte tmpbuf[INT_REGISTER_SIZE];
6532 LONGEST val = unpack_long (type, valbuf);
6534 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
6535 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
6539 /* Integral values greater than one word are stored in consecutive
6540 registers starting with r0. This will always be a multiple of
6541 the regiser size. */
6542 int len = TYPE_LENGTH (type);
6543 int regno = ARM_A1_REGNUM;
6547 regcache_cooked_write (regs, regno++, valbuf);
6548 len -= INT_REGISTER_SIZE;
6549 valbuf += INT_REGISTER_SIZE;
6555 /* For a structure or union the behaviour is as if the value had
6556 been stored to word-aligned memory and then loaded into
6557 registers with 32-bit load instruction(s). */
6558 int len = TYPE_LENGTH (type);
6559 int regno = ARM_A1_REGNUM;
6560 bfd_byte tmpbuf[INT_REGISTER_SIZE];
6564 memcpy (tmpbuf, valbuf,
6565 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
6566 regcache_cooked_write (regs, regno++, tmpbuf);
6567 len -= INT_REGISTER_SIZE;
6568 valbuf += INT_REGISTER_SIZE;
6574 /* Handle function return values. */
6576 static enum return_value_convention
6577 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
6578 struct type *valtype, struct regcache *regcache,
6579 gdb_byte *readbuf, const gdb_byte *writebuf)
6581 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6582 enum arm_vfp_cprc_base_type vfp_base_type;
6585 if (arm_vfp_abi_for_function (gdbarch, func_type)
6586 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
6588 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
6589 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
6591 for (i = 0; i < vfp_base_count; i++)
6593 if (reg_char == 'q')
6596 arm_neon_quad_write (gdbarch, regcache, i,
6597 writebuf + i * unit_length);
6600 arm_neon_quad_read (gdbarch, regcache, i,
6601 readbuf + i * unit_length);
6608 sprintf (name_buf, "%c%d", reg_char, i);
6609 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
6612 regcache_cooked_write (regcache, regnum,
6613 writebuf + i * unit_length);
6615 regcache_cooked_read (regcache, regnum,
6616 readbuf + i * unit_length);
6619 return RETURN_VALUE_REGISTER_CONVENTION;
6622 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
6623 || TYPE_CODE (valtype) == TYPE_CODE_UNION
6624 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
6626 if (tdep->struct_return == pcc_struct_return
6627 || arm_return_in_memory (gdbarch, valtype))
6628 return RETURN_VALUE_STRUCT_CONVENTION;
6632 arm_store_return_value (valtype, regcache, writebuf);
6635 arm_extract_return_value (valtype, regcache, readbuf);
6637 return RETURN_VALUE_REGISTER_CONVENTION;
6642 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
6644 struct gdbarch *gdbarch = get_frame_arch (frame);
6645 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6646 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6648 char buf[INT_REGISTER_SIZE];
6650 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
6652 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
6656 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
6660 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
6661 return the target PC. Otherwise return 0. */
6664 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
6668 CORE_ADDR start_addr;
6670 /* Find the starting address and name of the function containing the PC. */
6671 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
6674 /* If PC is in a Thumb call or return stub, return the address of the
6675 target PC, which is in a register. The thunk functions are called
6676 _call_via_xx, where x is the register name. The possible names
6677 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
6678 functions, named __ARM_call_via_r[0-7]. */
6679 if (strncmp (name, "_call_via_", 10) == 0
6680 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
6682 /* Use the name suffix to determine which register contains the
6684 static char *table[15] =
6685 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6686 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
6689 int offset = strlen (name) - 2;
6691 for (regno = 0; regno <= 14; regno++)
6692 if (strcmp (&name[offset], table[regno]) == 0)
6693 return get_frame_register_unsigned (frame, regno);
6696 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
6697 non-interworking calls to foo. We could decode the stubs
6698 to find the target but it's easier to use the symbol table. */
6699 namelen = strlen (name);
6700 if (name[0] == '_' && name[1] == '_'
6701 && ((namelen > 2 + strlen ("_from_thumb")
6702 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
6703 strlen ("_from_thumb")) == 0)
6704 || (namelen > 2 + strlen ("_from_arm")
6705 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
6706 strlen ("_from_arm")) == 0)))
6709 int target_len = namelen - 2;
6710 struct minimal_symbol *minsym;
6711 struct objfile *objfile;
6712 struct obj_section *sec;
6714 if (name[namelen - 1] == 'b')
6715 target_len -= strlen ("_from_thumb");
6717 target_len -= strlen ("_from_arm");
6719 target_name = alloca (target_len + 1);
6720 memcpy (target_name, name + 2, target_len);
6721 target_name[target_len] = '\0';
6723 sec = find_pc_section (pc);
6724 objfile = (sec == NULL) ? NULL : sec->objfile;
6725 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
6727 return SYMBOL_VALUE_ADDRESS (minsym);
6732 return 0; /* not a stub */
6736 set_arm_command (char *args, int from_tty)
6738 printf_unfiltered (_("\
6739 \"set arm\" must be followed by an apporpriate subcommand.\n"));
6740 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
6744 show_arm_command (char *args, int from_tty)
6746 cmd_show_list (showarmcmdlist, from_tty, "");
6750 arm_update_current_architecture (void)
6752 struct gdbarch_info info;
6754 /* If the current architecture is not ARM, we have nothing to do. */
6755 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
6758 /* Update the architecture. */
6759 gdbarch_info_init (&info);
6761 if (!gdbarch_update_p (info))
6762 internal_error (__FILE__, __LINE__, "could not update architecture");
6766 set_fp_model_sfunc (char *args, int from_tty,
6767 struct cmd_list_element *c)
6769 enum arm_float_model fp_model;
6771 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
6772 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
6774 arm_fp_model = fp_model;
6778 if (fp_model == ARM_FLOAT_LAST)
6779 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
6782 arm_update_current_architecture ();
6786 show_fp_model (struct ui_file *file, int from_tty,
6787 struct cmd_list_element *c, const char *value)
6789 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
6791 if (arm_fp_model == ARM_FLOAT_AUTO
6792 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
6793 fprintf_filtered (file, _("\
6794 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
6795 fp_model_strings[tdep->fp_model]);
6797 fprintf_filtered (file, _("\
6798 The current ARM floating point model is \"%s\".\n"),
6799 fp_model_strings[arm_fp_model]);
6803 arm_set_abi (char *args, int from_tty,
6804 struct cmd_list_element *c)
6806 enum arm_abi_kind arm_abi;
6808 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
6809 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
6811 arm_abi_global = arm_abi;
6815 if (arm_abi == ARM_ABI_LAST)
6816 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
6819 arm_update_current_architecture ();
6823 arm_show_abi (struct ui_file *file, int from_tty,
6824 struct cmd_list_element *c, const char *value)
6826 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
6828 if (arm_abi_global == ARM_ABI_AUTO
6829 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
6830 fprintf_filtered (file, _("\
6831 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
6832 arm_abi_strings[tdep->arm_abi]);
6834 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
6839 arm_show_fallback_mode (struct ui_file *file, int from_tty,
6840 struct cmd_list_element *c, const char *value)
6842 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
6844 fprintf_filtered (file, _("\
6845 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
6846 arm_fallback_mode_string);
6850 arm_show_force_mode (struct ui_file *file, int from_tty,
6851 struct cmd_list_element *c, const char *value)
6853 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
6855 fprintf_filtered (file, _("\
6856 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
6857 arm_force_mode_string);
6860 /* If the user changes the register disassembly style used for info
6861 register and other commands, we have to also switch the style used
6862 in opcodes for disassembly output. This function is run in the "set
6863 arm disassembly" command, and does that. */
6866 set_disassembly_style_sfunc (char *args, int from_tty,
6867 struct cmd_list_element *c)
6869 set_disassembly_style ();
6872 /* Return the ARM register name corresponding to register I. */
6874 arm_register_name (struct gdbarch *gdbarch, int i)
6876 const int num_regs = gdbarch_num_regs (gdbarch);
6878 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
6879 && i >= num_regs && i < num_regs + 32)
6881 static const char *const vfp_pseudo_names[] = {
6882 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
6883 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
6884 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
6885 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6888 return vfp_pseudo_names[i - num_regs];
6891 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
6892 && i >= num_regs + 32 && i < num_regs + 32 + 16)
6894 static const char *const neon_pseudo_names[] = {
6895 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
6896 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
6899 return neon_pseudo_names[i - num_regs - 32];
6902 if (i >= ARRAY_SIZE (arm_register_names))
6903 /* These registers are only supported on targets which supply
6904 an XML description. */
6907 return arm_register_names[i];
6911 set_disassembly_style (void)
6915 /* Find the style that the user wants. */
6916 for (current = 0; current < num_disassembly_options; current++)
6917 if (disassembly_style == valid_disassembly_styles[current])
6919 gdb_assert (current < num_disassembly_options);
6921 /* Synchronize the disassembler. */
6922 set_arm_regname_option (current);
6925 /* Test whether the coff symbol specific value corresponds to a Thumb
6929 coff_sym_is_thumb (int val)
6931 return (val == C_THUMBEXT
6932 || val == C_THUMBSTAT
6933 || val == C_THUMBEXTFUNC
6934 || val == C_THUMBSTATFUNC
6935 || val == C_THUMBLABEL);
6938 /* arm_coff_make_msymbol_special()
6939 arm_elf_make_msymbol_special()
6941 These functions test whether the COFF or ELF symbol corresponds to
6942 an address in thumb code, and set a "special" bit in a minimal
6943 symbol to indicate that it does. */
6946 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
6948 /* Thumb symbols are of type STT_LOPROC, (synonymous with
6950 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
6952 MSYMBOL_SET_SPECIAL (msym);
6956 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
6958 if (coff_sym_is_thumb (val))
6959 MSYMBOL_SET_SPECIAL (msym);
6963 arm_objfile_data_free (struct objfile *objfile, void *arg)
6965 struct arm_per_objfile *data = arg;
6968 for (i = 0; i < objfile->obfd->section_count; i++)
6969 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
6973 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
6976 const char *name = bfd_asymbol_name (sym);
6977 struct arm_per_objfile *data;
6978 VEC(arm_mapping_symbol_s) **map_p;
6979 struct arm_mapping_symbol new_map_sym;
6981 gdb_assert (name[0] == '$');
6982 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
6985 data = objfile_data (objfile, arm_objfile_data_key);
6988 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
6989 struct arm_per_objfile);
6990 set_objfile_data (objfile, arm_objfile_data_key, data);
6991 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
6992 objfile->obfd->section_count,
6993 VEC(arm_mapping_symbol_s) *);
6995 map_p = &data->section_maps[bfd_get_section (sym)->index];
6997 new_map_sym.value = sym->value;
6998 new_map_sym.type = name[1];
7000 /* Assume that most mapping symbols appear in order of increasing
7001 value. If they were randomly distributed, it would be faster to
7002 always push here and then sort at first use. */
7003 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
7005 struct arm_mapping_symbol *prev_map_sym;
7007 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
7008 if (prev_map_sym->value >= sym->value)
7011 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
7012 arm_compare_mapping_symbols);
7013 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
7018 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
7022 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
7024 struct gdbarch *gdbarch = get_regcache_arch (regcache);
7025 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
7027 /* If necessary, set the T bit. */
7030 ULONGEST val, t_bit;
7031 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
7032 t_bit = arm_psr_thumb_bit (gdbarch);
7033 if (arm_pc_is_thumb (gdbarch, pc))
7034 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
7037 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
7042 /* Read the contents of a NEON quad register, by reading from two
7043 double registers. This is used to implement the quad pseudo
7044 registers, and for argument passing in case the quad registers are
7045 missing; vectors are passed in quad registers when using the VFP
7046 ABI, even if a NEON unit is not present. REGNUM is the index of
7047 the quad register, in [0, 15]. */
7050 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
7051 int regnum, gdb_byte *buf)
7054 gdb_byte reg_buf[8];
7055 int offset, double_regnum;
7057 sprintf (name_buf, "d%d", regnum << 1);
7058 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
7061 /* d0 is always the least significant half of q0. */
7062 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
7067 regcache_raw_read (regcache, double_regnum, reg_buf);
7068 memcpy (buf + offset, reg_buf, 8);
7070 offset = 8 - offset;
7071 regcache_raw_read (regcache, double_regnum + 1, reg_buf);
7072 memcpy (buf + offset, reg_buf, 8);
7076 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
7077 int regnum, gdb_byte *buf)
7079 const int num_regs = gdbarch_num_regs (gdbarch);
7081 gdb_byte reg_buf[8];
7082 int offset, double_regnum;
7084 gdb_assert (regnum >= num_regs);
7087 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
7088 /* Quad-precision register. */
7089 arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
7092 /* Single-precision register. */
7093 gdb_assert (regnum < 32);
7095 /* s0 is always the least significant half of d0. */
7096 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
7097 offset = (regnum & 1) ? 0 : 4;
7099 offset = (regnum & 1) ? 4 : 0;
7101 sprintf (name_buf, "d%d", regnum >> 1);
7102 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
7105 regcache_raw_read (regcache, double_regnum, reg_buf);
7106 memcpy (buf, reg_buf + offset, 4);
7110 /* Store the contents of BUF to a NEON quad register, by writing to
7111 two double registers. This is used to implement the quad pseudo
7112 registers, and for argument passing in case the quad registers are
7113 missing; vectors are passed in quad registers when using the VFP
7114 ABI, even if a NEON unit is not present. REGNUM is the index
7115 of the quad register, in [0, 15]. */
7118 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
7119 int regnum, const gdb_byte *buf)
7122 gdb_byte reg_buf[8];
7123 int offset, double_regnum;
7125 sprintf (name_buf, "d%d", regnum << 1);
7126 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
7129 /* d0 is always the least significant half of q0. */
7130 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
7135 regcache_raw_write (regcache, double_regnum, buf + offset);
7136 offset = 8 - offset;
7137 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
7141 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
7142 int regnum, const gdb_byte *buf)
7144 const int num_regs = gdbarch_num_regs (gdbarch);
7146 gdb_byte reg_buf[8];
7147 int offset, double_regnum;
7149 gdb_assert (regnum >= num_regs);
7152 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
7153 /* Quad-precision register. */
7154 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
7157 /* Single-precision register. */
7158 gdb_assert (regnum < 32);
7160 /* s0 is always the least significant half of d0. */
7161 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
7162 offset = (regnum & 1) ? 0 : 4;
7164 offset = (regnum & 1) ? 4 : 0;
7166 sprintf (name_buf, "d%d", regnum >> 1);
7167 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
7170 regcache_raw_read (regcache, double_regnum, reg_buf);
7171 memcpy (reg_buf + offset, buf, 4);
7172 regcache_raw_write (regcache, double_regnum, reg_buf);
7176 static struct value *
7177 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
7179 const int *reg_p = baton;
7180 return value_of_register (*reg_p, frame);
7183 static enum gdb_osabi
7184 arm_elf_osabi_sniffer (bfd *abfd)
7186 unsigned int elfosabi;
7187 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
7189 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
7191 if (elfosabi == ELFOSABI_ARM)
7192 /* GNU tools use this value. Check note sections in this case,
7194 bfd_map_over_sections (abfd,
7195 generic_elf_osabi_sniff_abi_tag_sections,
7198 /* Anything else will be handled by the generic ELF sniffer. */
7203 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
7204 struct reggroup *group)
7206 /* FPS register's type is INT, but belongs to float_group. */
7207 if (regnum == ARM_FPS_REGNUM)
7208 return (group == float_reggroup);
7210 return default_register_reggroup_p (gdbarch, regnum, group);
7214 /* Initialize the current architecture based on INFO. If possible,
7215 re-use an architecture from ARCHES, which is a list of
7216 architectures already created during this debugging session.
7218 Called e.g. at program startup, when reading a core file, and when
7219 reading a binary file. */
7221 static struct gdbarch *
7222 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7224 struct gdbarch_tdep *tdep;
7225 struct gdbarch *gdbarch;
7226 struct gdbarch_list *best_arch;
7227 enum arm_abi_kind arm_abi = arm_abi_global;
7228 enum arm_float_model fp_model = arm_fp_model;
7229 struct tdesc_arch_data *tdesc_data = NULL;
7231 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
7233 int have_fpa_registers = 1;
7234 const struct target_desc *tdesc = info.target_desc;
7236 /* If we have an object to base this architecture on, try to determine
7239 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
7241 int ei_osabi, e_flags;
7243 switch (bfd_get_flavour (info.abfd))
7245 case bfd_target_aout_flavour:
7246 /* Assume it's an old APCS-style ABI. */
7247 arm_abi = ARM_ABI_APCS;
7250 case bfd_target_coff_flavour:
7251 /* Assume it's an old APCS-style ABI. */
7253 arm_abi = ARM_ABI_APCS;
7256 case bfd_target_elf_flavour:
7257 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
7258 e_flags = elf_elfheader (info.abfd)->e_flags;
7260 if (ei_osabi == ELFOSABI_ARM)
7262 /* GNU tools used to use this value, but do not for EABI
7263 objects. There's nowhere to tag an EABI version
7264 anyway, so assume APCS. */
7265 arm_abi = ARM_ABI_APCS;
7267 else if (ei_osabi == ELFOSABI_NONE)
7269 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
7270 int attr_arch, attr_profile;
7274 case EF_ARM_EABI_UNKNOWN:
7275 /* Assume GNU tools. */
7276 arm_abi = ARM_ABI_APCS;
7279 case EF_ARM_EABI_VER4:
7280 case EF_ARM_EABI_VER5:
7281 arm_abi = ARM_ABI_AAPCS;
7282 /* EABI binaries default to VFP float ordering.
7283 They may also contain build attributes that can
7284 be used to identify if the VFP argument-passing
7286 if (fp_model == ARM_FLOAT_AUTO)
7289 switch (bfd_elf_get_obj_attr_int (info.abfd,
7294 /* "The user intended FP parameter/result
7295 passing to conform to AAPCS, base
7297 fp_model = ARM_FLOAT_SOFT_VFP;
7300 /* "The user intended FP parameter/result
7301 passing to conform to AAPCS, VFP
7303 fp_model = ARM_FLOAT_VFP;
7306 /* "The user intended FP parameter/result
7307 passing to conform to tool chain-specific
7308 conventions" - we don't know any such
7309 conventions, so leave it as "auto". */
7312 /* Attribute value not mentioned in the
7313 October 2008 ABI, so leave it as
7318 fp_model = ARM_FLOAT_SOFT_VFP;
7324 /* Leave it as "auto". */
7325 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
7330 /* Detect M-profile programs. This only works if the
7331 executable file includes build attributes; GCC does
7332 copy them to the executable, but e.g. RealView does
7334 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
7336 attr_profile = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
7337 Tag_CPU_arch_profile);
7338 /* GCC specifies the profile for v6-M; RealView only
7339 specifies the profile for architectures starting with
7340 V7 (as opposed to architectures with a tag
7341 numerically greater than TAG_CPU_ARCH_V7). */
7342 if (!tdesc_has_registers (tdesc)
7343 && (attr_arch == TAG_CPU_ARCH_V6_M
7344 || attr_arch == TAG_CPU_ARCH_V6S_M
7345 || attr_profile == 'M'))
7346 tdesc = tdesc_arm_with_m;
7350 if (fp_model == ARM_FLOAT_AUTO)
7352 int e_flags = elf_elfheader (info.abfd)->e_flags;
7354 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
7357 /* Leave it as "auto". Strictly speaking this case
7358 means FPA, but almost nobody uses that now, and
7359 many toolchains fail to set the appropriate bits
7360 for the floating-point model they use. */
7362 case EF_ARM_SOFT_FLOAT:
7363 fp_model = ARM_FLOAT_SOFT_FPA;
7365 case EF_ARM_VFP_FLOAT:
7366 fp_model = ARM_FLOAT_VFP;
7368 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
7369 fp_model = ARM_FLOAT_SOFT_VFP;
7374 if (e_flags & EF_ARM_BE8)
7375 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
7380 /* Leave it as "auto". */
7385 /* Check any target description for validity. */
7386 if (tdesc_has_registers (tdesc))
7388 /* For most registers we require GDB's default names; but also allow
7389 the numeric names for sp / lr / pc, as a convenience. */
7390 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
7391 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
7392 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
7394 const struct tdesc_feature *feature;
7397 feature = tdesc_find_feature (tdesc,
7398 "org.gnu.gdb.arm.core");
7399 if (feature == NULL)
7401 feature = tdesc_find_feature (tdesc,
7402 "org.gnu.gdb.arm.m-profile");
7403 if (feature == NULL)
7409 tdesc_data = tdesc_data_alloc ();
7412 for (i = 0; i < ARM_SP_REGNUM; i++)
7413 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
7414 arm_register_names[i]);
7415 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
7418 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
7421 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
7425 valid_p &= tdesc_numbered_register (feature, tdesc_data,
7426 ARM_PS_REGNUM, "xpsr");
7428 valid_p &= tdesc_numbered_register (feature, tdesc_data,
7429 ARM_PS_REGNUM, "cpsr");
7433 tdesc_data_cleanup (tdesc_data);
7437 feature = tdesc_find_feature (tdesc,
7438 "org.gnu.gdb.arm.fpa");
7439 if (feature != NULL)
7442 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
7443 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
7444 arm_register_names[i]);
7447 tdesc_data_cleanup (tdesc_data);
7452 have_fpa_registers = 0;
7454 feature = tdesc_find_feature (tdesc,
7455 "org.gnu.gdb.xscale.iwmmxt");
7456 if (feature != NULL)
7458 static const char *const iwmmxt_names[] = {
7459 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
7460 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
7461 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
7462 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
7466 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
7468 &= tdesc_numbered_register (feature, tdesc_data, i,
7469 iwmmxt_names[i - ARM_WR0_REGNUM]);
7471 /* Check for the control registers, but do not fail if they
7473 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
7474 tdesc_numbered_register (feature, tdesc_data, i,
7475 iwmmxt_names[i - ARM_WR0_REGNUM]);
7477 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
7479 &= tdesc_numbered_register (feature, tdesc_data, i,
7480 iwmmxt_names[i - ARM_WR0_REGNUM]);
7484 tdesc_data_cleanup (tdesc_data);
7489 /* If we have a VFP unit, check whether the single precision registers
7490 are present. If not, then we will synthesize them as pseudo
7492 feature = tdesc_find_feature (tdesc,
7493 "org.gnu.gdb.arm.vfp");
7494 if (feature != NULL)
7496 static const char *const vfp_double_names[] = {
7497 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7498 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
7499 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
7500 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
7503 /* Require the double precision registers. There must be either
7506 for (i = 0; i < 32; i++)
7508 valid_p &= tdesc_numbered_register (feature, tdesc_data,
7510 vfp_double_names[i]);
7515 if (!valid_p && i != 16)
7517 tdesc_data_cleanup (tdesc_data);
7521 if (tdesc_unnumbered_register (feature, "s0") == 0)
7522 have_vfp_pseudos = 1;
7524 have_vfp_registers = 1;
7526 /* If we have VFP, also check for NEON. The architecture allows
7527 NEON without VFP (integer vector operations only), but GDB
7528 does not support that. */
7529 feature = tdesc_find_feature (tdesc,
7530 "org.gnu.gdb.arm.neon");
7531 if (feature != NULL)
7533 /* NEON requires 32 double-precision registers. */
7536 tdesc_data_cleanup (tdesc_data);
7540 /* If there are quad registers defined by the stub, use
7541 their type; otherwise (normally) provide them with
7542 the default type. */
7543 if (tdesc_unnumbered_register (feature, "q0") == 0)
7544 have_neon_pseudos = 1;
7551 /* If there is already a candidate, use it. */
7552 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
7554 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
7556 if (arm_abi != ARM_ABI_AUTO
7557 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
7560 if (fp_model != ARM_FLOAT_AUTO
7561 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
7564 /* There are various other properties in tdep that we do not
7565 need to check here: those derived from a target description,
7566 since gdbarches with a different target description are
7567 automatically disqualified. */
7569 /* Do check is_m, though, since it might come from the binary. */
7570 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
7573 /* Found a match. */
7577 if (best_arch != NULL)
7579 if (tdesc_data != NULL)
7580 tdesc_data_cleanup (tdesc_data);
7581 return best_arch->gdbarch;
7584 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
7585 gdbarch = gdbarch_alloc (&info, tdep);
7587 /* Record additional information about the architecture we are defining.
7588 These are gdbarch discriminators, like the OSABI. */
7589 tdep->arm_abi = arm_abi;
7590 tdep->fp_model = fp_model;
7592 tdep->have_fpa_registers = have_fpa_registers;
7593 tdep->have_vfp_registers = have_vfp_registers;
7594 tdep->have_vfp_pseudos = have_vfp_pseudos;
7595 tdep->have_neon_pseudos = have_neon_pseudos;
7596 tdep->have_neon = have_neon;
7599 switch (info.byte_order_for_code)
7601 case BFD_ENDIAN_BIG:
7602 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
7603 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
7604 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
7605 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
7609 case BFD_ENDIAN_LITTLE:
7610 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
7611 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
7612 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
7613 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
7618 internal_error (__FILE__, __LINE__,
7619 _("arm_gdbarch_init: bad byte order for float format"));
7622 /* On ARM targets char defaults to unsigned. */
7623 set_gdbarch_char_signed (gdbarch, 0);
7625 /* Note: for displaced stepping, this includes the breakpoint, and one word
7626 of additional scratch space. This setting isn't used for anything beside
7627 displaced stepping at present. */
7628 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
7630 /* This should be low enough for everything. */
7631 tdep->lowest_pc = 0x20;
7632 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
7634 /* The default, for both APCS and AAPCS, is to return small
7635 structures in registers. */
7636 tdep->struct_return = reg_struct_return;
7638 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
7639 set_gdbarch_frame_align (gdbarch, arm_frame_align);
7641 set_gdbarch_write_pc (gdbarch, arm_write_pc);
7643 /* Frame handling. */
7644 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
7645 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
7646 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
7648 frame_base_set_default (gdbarch, &arm_normal_base);
7650 /* Address manipulation. */
7651 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
7652 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
7654 /* Advance PC across function entry code. */
7655 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
7657 /* Detect whether PC is in function epilogue. */
7658 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
7660 /* Skip trampolines. */
7661 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
7663 /* The stack grows downward. */
7664 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7666 /* Breakpoint manipulation. */
7667 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
7668 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
7669 arm_remote_breakpoint_from_pc);
7671 /* Information about registers, etc. */
7672 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
7673 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
7674 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
7675 set_gdbarch_register_type (gdbarch, arm_register_type);
7676 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
7678 /* This "info float" is FPA-specific. Use the generic version if we
7680 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
7681 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
7683 /* Internal <-> external register number maps. */
7684 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
7685 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
7687 set_gdbarch_register_name (gdbarch, arm_register_name);
7689 /* Returning results. */
7690 set_gdbarch_return_value (gdbarch, arm_return_value);
7693 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
7695 /* Minsymbol frobbing. */
7696 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
7697 set_gdbarch_coff_make_msymbol_special (gdbarch,
7698 arm_coff_make_msymbol_special);
7699 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
7701 /* Thumb-2 IT block support. */
7702 set_gdbarch_adjust_breakpoint_address (gdbarch,
7703 arm_adjust_breakpoint_address);
7705 /* Virtual tables. */
7706 set_gdbarch_vbit_in_delta (gdbarch, 1);
7708 /* Hook in the ABI-specific overrides, if they have been registered. */
7709 gdbarch_init_osabi (info, gdbarch);
7711 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
7713 /* Add some default predicates. */
7714 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
7715 dwarf2_append_unwinders (gdbarch);
7716 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
7718 /* Now we have tuned the configuration, set a few final things,
7719 based on what the OS ABI has told us. */
7721 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
7722 binaries are always marked. */
7723 if (tdep->arm_abi == ARM_ABI_AUTO)
7724 tdep->arm_abi = ARM_ABI_APCS;
7726 /* We used to default to FPA for generic ARM, but almost nobody
7727 uses that now, and we now provide a way for the user to force
7728 the model. So default to the most useful variant. */
7729 if (tdep->fp_model == ARM_FLOAT_AUTO)
7730 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
7732 if (tdep->jb_pc >= 0)
7733 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
7735 /* Floating point sizes and format. */
7736 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
7737 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
7739 set_gdbarch_double_format
7740 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
7741 set_gdbarch_long_double_format
7742 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
7746 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
7747 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
7750 if (have_vfp_pseudos)
7752 /* NOTE: These are the only pseudo registers used by
7753 the ARM target at the moment. If more are added, a
7754 little more care in numbering will be needed. */
7756 int num_pseudos = 32;
7757 if (have_neon_pseudos)
7759 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
7760 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
7761 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
7766 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
7768 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7770 /* Override tdesc_register_type to adjust the types of VFP
7771 registers for NEON. */
7772 set_gdbarch_register_type (gdbarch, arm_register_type);
7775 /* Add standard register aliases. We add aliases even for those
7776 nanes which are used by the current architecture - it's simpler,
7777 and does no harm, since nothing ever lists user registers. */
7778 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
7779 user_reg_add (gdbarch, arm_register_aliases[i].name,
7780 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
7786 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7788 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7793 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
7794 (unsigned long) tdep->lowest_pc);
7797 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
7800 _initialize_arm_tdep (void)
7802 struct ui_file *stb;
7804 struct cmd_list_element *new_set, *new_show;
7805 const char *setname;
7806 const char *setdesc;
7807 const char *const *regnames;
7809 static char *helptext;
7810 char regdesc[1024], *rdptr = regdesc;
7811 size_t rest = sizeof (regdesc);
7813 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
7815 arm_objfile_data_key
7816 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
7818 /* Register an ELF OS ABI sniffer for ARM binaries. */
7819 gdbarch_register_osabi_sniffer (bfd_arch_arm,
7820 bfd_target_elf_flavour,
7821 arm_elf_osabi_sniffer);
7823 /* Initialize the standard target descriptions. */
7824 initialize_tdesc_arm_with_m ();
7826 /* Get the number of possible sets of register names defined in opcodes. */
7827 num_disassembly_options = get_arm_regname_num_options ();
7829 /* Add root prefix command for all "set arm"/"show arm" commands. */
7830 add_prefix_cmd ("arm", no_class, set_arm_command,
7831 _("Various ARM-specific commands."),
7832 &setarmcmdlist, "set arm ", 0, &setlist);
7834 add_prefix_cmd ("arm", no_class, show_arm_command,
7835 _("Various ARM-specific commands."),
7836 &showarmcmdlist, "show arm ", 0, &showlist);
7838 /* Sync the opcode insn printer with our register viewer. */
7839 parse_arm_disassembler_option ("reg-names-std");
7841 /* Initialize the array that will be passed to
7842 add_setshow_enum_cmd(). */
7843 valid_disassembly_styles
7844 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
7845 for (i = 0; i < num_disassembly_options; i++)
7847 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
7848 valid_disassembly_styles[i] = setname;
7849 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
7852 /* When we find the default names, tell the disassembler to use
7854 if (!strcmp (setname, "std"))
7856 disassembly_style = setname;
7857 set_arm_regname_option (i);
7860 /* Mark the end of valid options. */
7861 valid_disassembly_styles[num_disassembly_options] = NULL;
7863 /* Create the help text. */
7864 stb = mem_fileopen ();
7865 fprintf_unfiltered (stb, "%s%s%s",
7866 _("The valid values are:\n"),
7868 _("The default is \"std\"."));
7869 helptext = ui_file_xstrdup (stb, NULL);
7870 ui_file_delete (stb);
7872 add_setshow_enum_cmd("disassembler", no_class,
7873 valid_disassembly_styles, &disassembly_style,
7874 _("Set the disassembly style."),
7875 _("Show the disassembly style."),
7877 set_disassembly_style_sfunc,
7878 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
7879 &setarmcmdlist, &showarmcmdlist);
7881 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
7882 _("Set usage of ARM 32-bit mode."),
7883 _("Show usage of ARM 32-bit mode."),
7884 _("When off, a 26-bit PC will be used."),
7886 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
7887 &setarmcmdlist, &showarmcmdlist);
7889 /* Add a command to allow the user to force the FPU model. */
7890 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
7891 _("Set the floating point type."),
7892 _("Show the floating point type."),
7893 _("auto - Determine the FP typefrom the OS-ABI.\n\
7894 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
7895 fpa - FPA co-processor (GCC compiled).\n\
7896 softvfp - Software FP with pure-endian doubles.\n\
7897 vfp - VFP co-processor."),
7898 set_fp_model_sfunc, show_fp_model,
7899 &setarmcmdlist, &showarmcmdlist);
7901 /* Add a command to allow the user to force the ABI. */
7902 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
7905 NULL, arm_set_abi, arm_show_abi,
7906 &setarmcmdlist, &showarmcmdlist);
7908 /* Add two commands to allow the user to force the assumed
7910 add_setshow_enum_cmd ("fallback-mode", class_support,
7911 arm_mode_strings, &arm_fallback_mode_string,
7912 _("Set the mode assumed when symbols are unavailable."),
7913 _("Show the mode assumed when symbols are unavailable."),
7914 NULL, NULL, arm_show_fallback_mode,
7915 &setarmcmdlist, &showarmcmdlist);
7916 add_setshow_enum_cmd ("force-mode", class_support,
7917 arm_mode_strings, &arm_force_mode_string,
7918 _("Set the mode assumed even when symbols are available."),
7919 _("Show the mode assumed even when symbols are available."),
7920 NULL, NULL, arm_show_force_mode,
7921 &setarmcmdlist, &showarmcmdlist);
7923 /* Debugging flag. */
7924 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
7925 _("Set ARM debugging."),
7926 _("Show ARM debugging."),
7927 _("When on, arm-specific debugging is enabled."),
7929 NULL, /* FIXME: i18n: "ARM debugging is %s. */
7930 &setdebuglist, &showdebuglist);