1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "gdb/sim-arm.h"
53 #include "coff/internal.h"
59 #include "record-full.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data *arm_objfile_data_key;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
93 DEF_VEC_O(arm_mapping_symbol_s);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s) **section_maps;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element *setarmcmdlist = NULL;
102 static struct cmd_list_element *showarmcmdlist = NULL;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
118 static const char *current_fp_model = "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
131 static const char *arm_abi_string = "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings[] =
142 static const char *arm_fallback_mode_string = "auto";
143 static const char *arm_force_mode_string = "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode = -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element *);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat *, const void *,
229 static void convert_to_extended (const struct floatformat *, void *,
232 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
233 struct regcache *regcache,
234 int regnum, gdb_byte *buf);
235 static void arm_neon_quad_write (struct gdbarch *gdbarch,
236 struct regcache *regcache,
237 int regnum, const gdb_byte *buf);
239 static int thumb_insn_size (unsigned short inst1);
241 struct arm_prologue_cache
243 /* The stack pointer at the time this frame was created; i.e. the
244 caller's stack pointer when this function was called. It is used
245 to identify this frame. */
248 /* The frame base for this frame is just prev_sp - frame size.
249 FRAMESIZE is the distance from the frame pointer to the
250 initial stack pointer. */
254 /* The register used to hold the frame pointer for this frame. */
257 /* Saved register offsets. */
258 struct trad_frame_saved_reg *saved_regs;
261 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
262 CORE_ADDR prologue_start,
263 CORE_ADDR prologue_end,
264 struct arm_prologue_cache *cache);
266 /* Architecture version for displaced stepping. This effects the behaviour of
267 certain instructions, and really should not be hard-wired. */
269 #define DISPLACED_STEPPING_ARCH_VERSION 5
271 /* Addresses for calling Thumb functions have the bit 0 set.
272 Here are some macros to test, set, or clear bit 0 of addresses. */
273 #define IS_THUMB_ADDR(addr) ((addr) & 1)
274 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
275 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch *gdbarch)
286 if (gdbarch_tdep (gdbarch)->is_m)
292 /* Determine if FRAME is executing in Thumb mode. */
295 arm_frame_is_thumb (struct frame_info *frame)
298 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
300 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
301 directly (from a signal frame or dummy frame) or by interpreting
302 the saved LR (from a prologue or DWARF frame). So consult it and
303 trust the unwinders. */
304 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
306 return (cpsr & t_bit) != 0;
309 /* Callback for VEC_lower_bound. */
312 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
313 const struct arm_mapping_symbol *rhs)
315 return lhs->value < rhs->value;
318 /* Search for the mapping symbol covering MEMADDR. If one is found,
319 return its type. Otherwise, return 0. If START is non-NULL,
320 set *START to the location of the mapping symbol. */
323 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
325 struct obj_section *sec;
327 /* If there are mapping symbols, consult them. */
328 sec = find_pc_section (memaddr);
331 struct arm_per_objfile *data;
332 VEC(arm_mapping_symbol_s) *map;
333 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
337 data = objfile_data (sec->objfile, arm_objfile_data_key);
340 map = data->section_maps[sec->the_bfd_section->index];
341 if (!VEC_empty (arm_mapping_symbol_s, map))
343 struct arm_mapping_symbol *map_sym;
345 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
346 arm_compare_mapping_symbols);
348 /* VEC_lower_bound finds the earliest ordered insertion
349 point. If the following symbol starts at this exact
350 address, we use that; otherwise, the preceding
351 mapping symbol covers this address. */
352 if (idx < VEC_length (arm_mapping_symbol_s, map))
354 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
355 if (map_sym->value == map_key.value)
358 *start = map_sym->value + obj_section_addr (sec);
359 return map_sym->type;
365 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
367 *start = map_sym->value + obj_section_addr (sec);
368 return map_sym->type;
377 /* Determine if the program counter specified in MEMADDR is in a Thumb
378 function. This function should be called for addresses unrelated to
379 any executing frame; otherwise, prefer arm_frame_is_thumb. */
382 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
384 struct bound_minimal_symbol sym;
386 struct displaced_step_closure* dsc
387 = get_displaced_step_closure_by_addr(memaddr);
389 /* If checking the mode of displaced instruction in copy area, the mode
390 should be determined by instruction on the original address. */
394 fprintf_unfiltered (gdb_stdlog,
395 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (unsigned long) dsc->insn_addr,
397 (unsigned long) memaddr);
398 memaddr = dsc->insn_addr;
401 /* If bit 0 of the address is set, assume this is a Thumb address. */
402 if (IS_THUMB_ADDR (memaddr))
405 /* Respect internal mode override if active. */
406 if (arm_override_mode != -1)
407 return arm_override_mode;
409 /* If the user wants to override the symbol table, let him. */
410 if (strcmp (arm_force_mode_string, "arm") == 0)
412 if (strcmp (arm_force_mode_string, "thumb") == 0)
415 /* ARM v6-M and v7-M are always in Thumb mode. */
416 if (gdbarch_tdep (gdbarch)->is_m)
419 /* If there are mapping symbols, consult them. */
420 type = arm_find_mapping_symbol (memaddr, NULL);
424 /* Thumb functions have a "special" bit set in minimal symbols. */
425 sym = lookup_minimal_symbol_by_pc (memaddr);
427 return (MSYMBOL_IS_SPECIAL (sym.minsym));
429 /* If the user wants to override the fallback mode, let them. */
430 if (strcmp (arm_fallback_mode_string, "arm") == 0)
432 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
435 /* If we couldn't find any symbol, but we're talking to a running
436 target, then trust the current value of $cpsr. This lets
437 "display/i $pc" always show the correct mode (though if there is
438 a symbol table we will not reach here, so it still may not be
439 displayed in the mode it will be executed). */
440 if (target_has_registers)
441 return arm_frame_is_thumb (get_current_frame ());
443 /* Otherwise we're out of luck; we assume ARM. */
447 /* Remove useless bits from addresses in a running program. */
449 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
451 /* On M-profile devices, do not strip the low bit from EXC_RETURN
452 (the magic exception return address). */
453 if (gdbarch_tdep (gdbarch)->is_m
454 && (val & 0xfffffff0) == 0xfffffff0)
458 return UNMAKE_THUMB_ADDR (val);
460 return (val & 0x03fffffc);
463 /* Return 1 if PC is the start of a compiler helper function which
464 can be safely ignored during prologue skipping. IS_THUMB is true
465 if the function is known to be a Thumb function due to the way it
468 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
470 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
471 struct bound_minimal_symbol msym;
473 msym = lookup_minimal_symbol_by_pc (pc);
474 if (msym.minsym != NULL
475 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
476 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
478 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
480 /* The GNU linker's Thumb call stub to foo is named
482 if (strstr (name, "_from_thumb") != NULL)
485 /* On soft-float targets, __truncdfsf2 is called to convert promoted
486 arguments to their argument types in non-prototyped
488 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
490 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
493 /* Internal functions related to thread-local storage. */
494 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
496 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
501 /* If we run against a stripped glibc, we may be unable to identify
502 special functions by name. Check for one important case,
503 __aeabi_read_tp, by comparing the *code* against the default
504 implementation (this is hand-written ARM assembler in glibc). */
507 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
508 == 0xe3e00a0f /* mov r0, #0xffff0fff */
509 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
510 == 0xe240f01f) /* sub pc, r0, #31 */
517 /* Support routines for instruction parsing. */
518 #define submask(x) ((1L << ((x) + 1)) - 1)
519 #define bit(obj,st) (((obj) >> (st)) & 1)
520 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
521 #define sbits(obj,st,fn) \
522 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
523 #define BranchDest(addr,instr) \
524 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
526 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
527 the first 16-bit of instruction, and INSN2 is the second 16-bit of
529 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
530 ((bits ((insn1), 0, 3) << 12) \
531 | (bits ((insn1), 10, 10) << 11) \
532 | (bits ((insn2), 12, 14) << 8) \
533 | bits ((insn2), 0, 7))
535 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
536 the 32-bit instruction. */
537 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
538 ((bits ((insn), 16, 19) << 12) \
539 | bits ((insn), 0, 11))
541 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
544 thumb_expand_immediate (unsigned int imm)
546 unsigned int count = imm >> 7;
554 return (imm & 0xff) | ((imm & 0xff) << 16);
556 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
558 return (imm & 0xff) | ((imm & 0xff) << 8)
559 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
562 return (0x80 | (imm & 0x7f)) << (32 - count);
565 /* Return 1 if the 16-bit Thumb instruction INST might change
566 control flow, 0 otherwise. */
569 thumb_instruction_changes_pc (unsigned short inst)
571 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
574 if ((inst & 0xf000) == 0xd000) /* conditional branch */
577 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
580 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
583 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
586 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
592 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
593 might change control flow, 0 otherwise. */
596 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
598 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
600 /* Branches and miscellaneous control instructions. */
602 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
607 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
609 /* SUBS PC, LR, #imm8. */
612 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
614 /* Conditional branch. */
621 if ((inst1 & 0xfe50) == 0xe810)
623 /* Load multiple or RFE. */
625 if (bit (inst1, 7) && !bit (inst1, 8))
631 else if (!bit (inst1, 7) && bit (inst1, 8))
637 else if (bit (inst1, 7) && bit (inst1, 8))
642 else if (!bit (inst1, 7) && !bit (inst1, 8))
651 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
653 /* MOV PC or MOVS PC. */
657 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
660 if (bits (inst1, 0, 3) == 15)
666 if ((inst2 & 0x0fc0) == 0x0000)
672 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
678 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
687 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
688 epilogue, 0 otherwise. */
691 thumb_instruction_restores_sp (unsigned short insn)
693 return (insn == 0x46bd /* mov sp, r7 */
694 || (insn & 0xff80) == 0xb000 /* add sp, imm */
695 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
698 /* Analyze a Thumb prologue, looking for a recognizable stack frame
699 and frame pointer. Scan until we encounter a store that could
700 clobber the stack frame unexpectedly, or an unknown instruction.
701 Return the last address which is definitely safe to skip for an
702 initial breakpoint. */
705 thumb_analyze_prologue (struct gdbarch *gdbarch,
706 CORE_ADDR start, CORE_ADDR limit,
707 struct arm_prologue_cache *cache)
709 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
710 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
713 struct pv_area *stack;
714 struct cleanup *back_to;
716 CORE_ADDR unrecognized_pc = 0;
718 for (i = 0; i < 16; i++)
719 regs[i] = pv_register (i, 0);
720 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
721 back_to = make_cleanup_free_pv_area (stack);
723 while (start < limit)
727 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
729 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
734 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
737 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
738 whether to save LR (R14). */
739 mask = (insn & 0xff) | ((insn & 0x100) << 6);
741 /* Calculate offsets of saved R0-R7 and LR. */
742 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
743 if (mask & (1 << regno))
745 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
747 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
750 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
752 offset = (insn & 0x7f) << 2; /* get scaled offset */
753 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
756 else if (thumb_instruction_restores_sp (insn))
758 /* Don't scan past the epilogue. */
761 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
762 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
764 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
765 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
766 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
768 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
769 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
770 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
772 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
773 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
774 && pv_is_constant (regs[bits (insn, 3, 5)]))
775 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
776 regs[bits (insn, 6, 8)]);
777 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
778 && pv_is_constant (regs[bits (insn, 3, 6)]))
780 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
781 int rm = bits (insn, 3, 6);
782 regs[rd] = pv_add (regs[rd], regs[rm]);
784 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
786 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
787 int src_reg = (insn & 0x78) >> 3;
788 regs[dst_reg] = regs[src_reg];
790 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
792 /* Handle stores to the stack. Normally pushes are used,
793 but with GCC -mtpcs-frame, there may be other stores
794 in the prologue to create the frame. */
795 int regno = (insn >> 8) & 0x7;
798 offset = (insn & 0xff) << 2;
799 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
801 if (pv_area_store_would_trash (stack, addr))
804 pv_area_store (stack, addr, 4, regs[regno]);
806 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
808 int rd = bits (insn, 0, 2);
809 int rn = bits (insn, 3, 5);
812 offset = bits (insn, 6, 10) << 2;
813 addr = pv_add_constant (regs[rn], offset);
815 if (pv_area_store_would_trash (stack, addr))
818 pv_area_store (stack, addr, 4, regs[rd]);
820 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
821 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
822 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
823 /* Ignore stores of argument registers to the stack. */
825 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
826 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
827 /* Ignore block loads from the stack, potentially copying
828 parameters from memory. */
830 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
831 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
832 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
833 /* Similarly ignore single loads from the stack. */
835 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
836 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
837 /* Skip register copies, i.e. saves to another register
838 instead of the stack. */
840 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
841 /* Recognize constant loads; even with small stacks these are necessary
843 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
844 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
846 /* Constant pool loads, for the same reason. */
847 unsigned int constant;
850 loc = start + 4 + bits (insn, 0, 7) * 4;
851 constant = read_memory_unsigned_integer (loc, 4, byte_order);
852 regs[bits (insn, 8, 10)] = pv_constant (constant);
854 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
856 unsigned short inst2;
858 inst2 = read_memory_unsigned_integer (start + 2, 2,
859 byte_order_for_code);
861 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
863 /* BL, BLX. Allow some special function calls when
864 skipping the prologue; GCC generates these before
865 storing arguments to the stack. */
867 int j1, j2, imm1, imm2;
869 imm1 = sbits (insn, 0, 10);
870 imm2 = bits (inst2, 0, 10);
871 j1 = bit (inst2, 13);
872 j2 = bit (inst2, 11);
874 offset = ((imm1 << 12) + (imm2 << 1));
875 offset ^= ((!j2) << 22) | ((!j1) << 23);
877 nextpc = start + 4 + offset;
878 /* For BLX make sure to clear the low bits. */
879 if (bit (inst2, 12) == 0)
880 nextpc = nextpc & 0xfffffffc;
882 if (!skip_prologue_function (gdbarch, nextpc,
883 bit (inst2, 12) != 0))
887 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
889 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
891 pv_t addr = regs[bits (insn, 0, 3)];
894 if (pv_area_store_would_trash (stack, addr))
897 /* Calculate offsets of saved registers. */
898 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
899 if (inst2 & (1 << regno))
901 addr = pv_add_constant (addr, -4);
902 pv_area_store (stack, addr, 4, regs[regno]);
906 regs[bits (insn, 0, 3)] = addr;
909 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
911 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
913 int regno1 = bits (inst2, 12, 15);
914 int regno2 = bits (inst2, 8, 11);
915 pv_t addr = regs[bits (insn, 0, 3)];
917 offset = inst2 & 0xff;
919 addr = pv_add_constant (addr, offset);
921 addr = pv_add_constant (addr, -offset);
923 if (pv_area_store_would_trash (stack, addr))
926 pv_area_store (stack, addr, 4, regs[regno1]);
927 pv_area_store (stack, pv_add_constant (addr, 4),
931 regs[bits (insn, 0, 3)] = addr;
934 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
935 && (inst2 & 0x0c00) == 0x0c00
936 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
938 int regno = bits (inst2, 12, 15);
939 pv_t addr = regs[bits (insn, 0, 3)];
941 offset = inst2 & 0xff;
943 addr = pv_add_constant (addr, offset);
945 addr = pv_add_constant (addr, -offset);
947 if (pv_area_store_would_trash (stack, addr))
950 pv_area_store (stack, addr, 4, regs[regno]);
953 regs[bits (insn, 0, 3)] = addr;
956 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
957 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
959 int regno = bits (inst2, 12, 15);
962 offset = inst2 & 0xfff;
963 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
965 if (pv_area_store_would_trash (stack, addr))
968 pv_area_store (stack, addr, 4, regs[regno]);
971 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
972 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
973 /* Ignore stores of argument registers to the stack. */
976 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
977 && (inst2 & 0x0d00) == 0x0c00
978 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
979 /* Ignore stores of argument registers to the stack. */
982 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
984 && (inst2 & 0x8000) == 0x0000
985 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
986 /* Ignore block loads from the stack, potentially copying
987 parameters from memory. */
990 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
992 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
993 /* Similarly ignore dual loads from the stack. */
996 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
997 && (inst2 & 0x0d00) == 0x0c00
998 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
999 /* Similarly ignore single loads from the stack. */
1002 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1003 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
1004 /* Similarly ignore single loads from the stack. */
1007 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1008 && (inst2 & 0x8000) == 0x0000)
1010 unsigned int imm = ((bits (insn, 10, 10) << 11)
1011 | (bits (inst2, 12, 14) << 8)
1012 | bits (inst2, 0, 7));
1014 regs[bits (inst2, 8, 11)]
1015 = pv_add_constant (regs[bits (insn, 0, 3)],
1016 thumb_expand_immediate (imm));
1019 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1020 && (inst2 & 0x8000) == 0x0000)
1022 unsigned int imm = ((bits (insn, 10, 10) << 11)
1023 | (bits (inst2, 12, 14) << 8)
1024 | bits (inst2, 0, 7));
1026 regs[bits (inst2, 8, 11)]
1027 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1030 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1031 && (inst2 & 0x8000) == 0x0000)
1033 unsigned int imm = ((bits (insn, 10, 10) << 11)
1034 | (bits (inst2, 12, 14) << 8)
1035 | bits (inst2, 0, 7));
1037 regs[bits (inst2, 8, 11)]
1038 = pv_add_constant (regs[bits (insn, 0, 3)],
1039 - (CORE_ADDR) thumb_expand_immediate (imm));
1042 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1043 && (inst2 & 0x8000) == 0x0000)
1045 unsigned int imm = ((bits (insn, 10, 10) << 11)
1046 | (bits (inst2, 12, 14) << 8)
1047 | bits (inst2, 0, 7));
1049 regs[bits (inst2, 8, 11)]
1050 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1053 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1055 unsigned int imm = ((bits (insn, 10, 10) << 11)
1056 | (bits (inst2, 12, 14) << 8)
1057 | bits (inst2, 0, 7));
1059 regs[bits (inst2, 8, 11)]
1060 = pv_constant (thumb_expand_immediate (imm));
1063 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1066 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1068 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1071 else if (insn == 0xea5f /* mov.w Rd,Rm */
1072 && (inst2 & 0xf0f0) == 0)
1074 int dst_reg = (inst2 & 0x0f00) >> 8;
1075 int src_reg = inst2 & 0xf;
1076 regs[dst_reg] = regs[src_reg];
1079 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1081 /* Constant pool loads. */
1082 unsigned int constant;
1085 offset = bits (inst2, 0, 11);
1087 loc = start + 4 + offset;
1089 loc = start + 4 - offset;
1091 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1092 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1095 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1097 /* Constant pool loads. */
1098 unsigned int constant;
1101 offset = bits (inst2, 0, 7) << 2;
1103 loc = start + 4 + offset;
1105 loc = start + 4 - offset;
1107 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1108 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1110 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1111 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1114 else if (thumb2_instruction_changes_pc (insn, inst2))
1116 /* Don't scan past anything that might change control flow. */
1121 /* The optimizer might shove anything into the prologue,
1122 so we just skip what we don't recognize. */
1123 unrecognized_pc = start;
1128 else if (thumb_instruction_changes_pc (insn))
1130 /* Don't scan past anything that might change control flow. */
1135 /* The optimizer might shove anything into the prologue,
1136 so we just skip what we don't recognize. */
1137 unrecognized_pc = start;
1144 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1145 paddress (gdbarch, start));
1147 if (unrecognized_pc == 0)
1148 unrecognized_pc = start;
1152 do_cleanups (back_to);
1153 return unrecognized_pc;
1156 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1158 /* Frame pointer is fp. Frame size is constant. */
1159 cache->framereg = ARM_FP_REGNUM;
1160 cache->framesize = -regs[ARM_FP_REGNUM].k;
1162 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1164 /* Frame pointer is r7. Frame size is constant. */
1165 cache->framereg = THUMB_FP_REGNUM;
1166 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1170 /* Try the stack pointer... this is a bit desperate. */
1171 cache->framereg = ARM_SP_REGNUM;
1172 cache->framesize = -regs[ARM_SP_REGNUM].k;
1175 for (i = 0; i < 16; i++)
1176 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1177 cache->saved_regs[i].addr = offset;
1179 do_cleanups (back_to);
1180 return unrecognized_pc;
1184 /* Try to analyze the instructions starting from PC, which load symbol
1185 __stack_chk_guard. Return the address of instruction after loading this
1186 symbol, set the dest register number to *BASEREG, and set the size of
1187 instructions for loading symbol in OFFSET. Return 0 if instructions are
1191 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1192 unsigned int *destreg, int *offset)
1194 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1195 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1196 unsigned int low, high, address;
1201 unsigned short insn1
1202 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1204 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1206 *destreg = bits (insn1, 8, 10);
1208 address = bits (insn1, 0, 7);
1210 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1212 unsigned short insn2
1213 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1215 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1218 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1220 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1222 /* movt Rd, #const */
1223 if ((insn1 & 0xfbc0) == 0xf2c0)
1225 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1226 *destreg = bits (insn2, 8, 11);
1228 address = (high << 16 | low);
1235 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1237 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1239 address = bits (insn, 0, 11);
1240 *destreg = bits (insn, 12, 15);
1243 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1245 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1248 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1250 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1252 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1253 *destreg = bits (insn, 12, 15);
1255 address = (high << 16 | low);
1263 /* Try to skip a sequence of instructions used for stack protector. If PC
1264 points to the first instruction of this sequence, return the address of
1265 first instruction after this sequence, otherwise, return original PC.
1267 On arm, this sequence of instructions is composed of mainly three steps,
1268 Step 1: load symbol __stack_chk_guard,
1269 Step 2: load from address of __stack_chk_guard,
1270 Step 3: store it to somewhere else.
1272 Usually, instructions on step 2 and step 3 are the same on various ARM
1273 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1274 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1275 instructions in step 1 vary from different ARM architectures. On ARMv7,
1278 movw Rn, #:lower16:__stack_chk_guard
1279 movt Rn, #:upper16:__stack_chk_guard
1286 .word __stack_chk_guard
1288 Since ldr/str is a very popular instruction, we can't use them as
1289 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1290 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1291 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1294 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1296 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1297 unsigned int basereg;
1298 struct bound_minimal_symbol stack_chk_guard;
1300 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1303 /* Try to parse the instructions in Step 1. */
1304 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1309 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1310 /* If name of symbol doesn't start with '__stack_chk_guard', this
1311 instruction sequence is not for stack protector. If symbol is
1312 removed, we conservatively think this sequence is for stack protector. */
1313 if (stack_chk_guard.minsym
1314 && strncmp (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym),
1315 "__stack_chk_guard",
1316 strlen ("__stack_chk_guard")) != 0)
1321 unsigned int destreg;
1323 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1325 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1326 if ((insn & 0xf800) != 0x6800)
1328 if (bits (insn, 3, 5) != basereg)
1330 destreg = bits (insn, 0, 2);
1332 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1333 byte_order_for_code);
1334 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1335 if ((insn & 0xf800) != 0x6000)
1337 if (destreg != bits (insn, 0, 2))
1342 unsigned int destreg;
1344 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1346 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1347 if ((insn & 0x0e500000) != 0x04100000)
1349 if (bits (insn, 16, 19) != basereg)
1351 destreg = bits (insn, 12, 15);
1352 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1353 insn = read_memory_unsigned_integer (pc + offset + 4,
1354 4, byte_order_for_code);
1355 if ((insn & 0x0e500000) != 0x04000000)
1357 if (bits (insn, 12, 15) != destreg)
1360 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1363 return pc + offset + 4;
1365 return pc + offset + 8;
1368 /* Advance the PC across any function entry prologue instructions to
1369 reach some "real" code.
1371 The APCS (ARM Procedure Call Standard) defines the following
1375 [stmfd sp!, {a1,a2,a3,a4}]
1376 stmfd sp!, {...,fp,ip,lr,pc}
1377 [stfe f7, [sp, #-12]!]
1378 [stfe f6, [sp, #-12]!]
1379 [stfe f5, [sp, #-12]!]
1380 [stfe f4, [sp, #-12]!]
1381 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1384 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1386 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1389 CORE_ADDR func_addr, limit_pc;
1391 /* See if we can determine the end of the prologue via the symbol table.
1392 If so, then return either PC, or the PC after the prologue, whichever
1394 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1396 CORE_ADDR post_prologue_pc
1397 = skip_prologue_using_sal (gdbarch, func_addr);
1398 struct symtab *s = find_pc_symtab (func_addr);
1400 if (post_prologue_pc)
1402 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1405 /* GCC always emits a line note before the prologue and another
1406 one after, even if the two are at the same address or on the
1407 same line. Take advantage of this so that we do not need to
1408 know every instruction that might appear in the prologue. We
1409 will have producer information for most binaries; if it is
1410 missing (e.g. for -gstabs), assuming the GNU tools. */
1411 if (post_prologue_pc
1413 || s->producer == NULL
1414 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0
1415 || strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
1416 return post_prologue_pc;
1418 if (post_prologue_pc != 0)
1420 CORE_ADDR analyzed_limit;
1422 /* For non-GCC compilers, make sure the entire line is an
1423 acceptable prologue; GDB will round this function's
1424 return value up to the end of the following line so we
1425 can not skip just part of a line (and we do not want to).
1427 RealView does not treat the prologue specially, but does
1428 associate prologue code with the opening brace; so this
1429 lets us skip the first line if we think it is the opening
1431 if (arm_pc_is_thumb (gdbarch, func_addr))
1432 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1433 post_prologue_pc, NULL);
1435 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1436 post_prologue_pc, NULL);
1438 if (analyzed_limit != post_prologue_pc)
1441 return post_prologue_pc;
1445 /* Can't determine prologue from the symbol table, need to examine
1448 /* Find an upper limit on the function prologue using the debug
1449 information. If the debug information could not be used to provide
1450 that bound, then use an arbitrary large number as the upper bound. */
1451 /* Like arm_scan_prologue, stop no later than pc + 64. */
1452 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1454 limit_pc = pc + 64; /* Magic. */
1457 /* Check if this is Thumb code. */
1458 if (arm_pc_is_thumb (gdbarch, pc))
1459 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1461 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1463 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1465 /* "mov ip, sp" is no longer a required part of the prologue. */
1466 if (inst == 0xe1a0c00d) /* mov ip, sp */
1469 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1472 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1475 /* Some prologues begin with "str lr, [sp, #-4]!". */
1476 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1479 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1482 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1485 /* Any insns after this point may float into the code, if it makes
1486 for better instruction scheduling, so we skip them only if we
1487 find them, but still consider the function to be frame-ful. */
1489 /* We may have either one sfmfd instruction here, or several stfe
1490 insns, depending on the version of floating point code we
1492 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1495 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1498 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1501 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1504 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1505 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1506 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1509 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1510 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1511 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1514 /* Un-recognized instruction; stop scanning. */
1518 return skip_pc; /* End of prologue. */
1522 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1523 This function decodes a Thumb function prologue to determine:
1524 1) the size of the stack frame
1525 2) which registers are saved on it
1526 3) the offsets of saved regs
1527 4) the offset from the stack pointer to the frame pointer
1529 A typical Thumb function prologue would create this stack frame
1530 (offsets relative to FP)
1531 old SP -> 24 stack parameters
1534 R7 -> 0 local variables (16 bytes)
1535 SP -> -12 additional stack space (12 bytes)
1536 The frame size would thus be 36 bytes, and the frame offset would be
1537 12 bytes. The frame register is R7.
1539 The comments for thumb_skip_prolog() describe the algorithm we use
1540 to detect the end of the prolog. */
1544 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1545 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1547 CORE_ADDR prologue_start;
1548 CORE_ADDR prologue_end;
1550 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1553 /* See comment in arm_scan_prologue for an explanation of
1555 if (prologue_end > prologue_start + 64)
1557 prologue_end = prologue_start + 64;
1561 /* We're in the boondocks: we have no idea where the start of the
1565 prologue_end = min (prologue_end, prev_pc);
1567 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1570 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1573 arm_instruction_changes_pc (uint32_t this_instr)
1575 if (bits (this_instr, 28, 31) == INST_NV)
1576 /* Unconditional instructions. */
1577 switch (bits (this_instr, 24, 27))
1581 /* Branch with Link and change to Thumb. */
1586 /* Coprocessor register transfer. */
1587 if (bits (this_instr, 12, 15) == 15)
1588 error (_("Invalid update to pc in instruction"));
1594 switch (bits (this_instr, 25, 27))
1597 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1599 /* Multiplies and extra load/stores. */
1600 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1601 /* Neither multiplies nor extension load/stores are allowed
1605 /* Otherwise, miscellaneous instructions. */
1607 /* BX <reg>, BXJ <reg>, BLX <reg> */
1608 if (bits (this_instr, 4, 27) == 0x12fff1
1609 || bits (this_instr, 4, 27) == 0x12fff2
1610 || bits (this_instr, 4, 27) == 0x12fff3)
1613 /* Other miscellaneous instructions are unpredictable if they
1617 /* Data processing instruction. Fall through. */
1620 if (bits (this_instr, 12, 15) == 15)
1627 /* Media instructions and architecturally undefined instructions. */
1628 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1632 if (bit (this_instr, 20) == 0)
1636 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1642 /* Load/store multiple. */
1643 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1649 /* Branch and branch with link. */
1654 /* Coprocessor transfers or SWIs can not affect PC. */
1658 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1662 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1663 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1664 fill it in. Return the first address not recognized as a prologue
1667 We recognize all the instructions typically found in ARM prologues,
1668 plus harmless instructions which can be skipped (either for analysis
1669 purposes, or a more restrictive set that can be skipped when finding
1670 the end of the prologue). */
1673 arm_analyze_prologue (struct gdbarch *gdbarch,
1674 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1675 struct arm_prologue_cache *cache)
1677 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1678 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1680 CORE_ADDR offset, current_pc;
1681 pv_t regs[ARM_FPS_REGNUM];
1682 struct pv_area *stack;
1683 struct cleanup *back_to;
1684 int framereg, framesize;
1685 CORE_ADDR unrecognized_pc = 0;
1687 /* Search the prologue looking for instructions that set up the
1688 frame pointer, adjust the stack pointer, and save registers.
1690 Be careful, however, and if it doesn't look like a prologue,
1691 don't try to scan it. If, for instance, a frameless function
1692 begins with stmfd sp!, then we will tell ourselves there is
1693 a frame, which will confuse stack traceback, as well as "finish"
1694 and other operations that rely on a knowledge of the stack
1697 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1698 regs[regno] = pv_register (regno, 0);
1699 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1700 back_to = make_cleanup_free_pv_area (stack);
1702 for (current_pc = prologue_start;
1703 current_pc < prologue_end;
1707 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1709 if (insn == 0xe1a0c00d) /* mov ip, sp */
1711 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1714 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1715 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1717 unsigned imm = insn & 0xff; /* immediate value */
1718 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1719 int rd = bits (insn, 12, 15);
1720 imm = (imm >> rot) | (imm << (32 - rot));
1721 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1724 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1725 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1727 unsigned imm = insn & 0xff; /* immediate value */
1728 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1729 int rd = bits (insn, 12, 15);
1730 imm = (imm >> rot) | (imm << (32 - rot));
1731 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1734 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1737 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1739 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1740 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1741 regs[bits (insn, 12, 15)]);
1744 else if ((insn & 0xffff0000) == 0xe92d0000)
1745 /* stmfd sp!, {..., fp, ip, lr, pc}
1747 stmfd sp!, {a1, a2, a3, a4} */
1749 int mask = insn & 0xffff;
1751 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1754 /* Calculate offsets of saved registers. */
1755 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1756 if (mask & (1 << regno))
1759 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1760 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1763 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1764 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1765 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1767 /* No need to add this to saved_regs -- it's just an arg reg. */
1770 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1771 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1772 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1774 /* No need to add this to saved_regs -- it's just an arg reg. */
1777 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1779 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1781 /* No need to add this to saved_regs -- it's just arg regs. */
1784 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1786 unsigned imm = insn & 0xff; /* immediate value */
1787 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1788 imm = (imm >> rot) | (imm << (32 - rot));
1789 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1791 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1793 unsigned imm = insn & 0xff; /* immediate value */
1794 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1795 imm = (imm >> rot) | (imm << (32 - rot));
1796 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1798 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1800 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1802 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1805 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1806 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1807 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1809 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1811 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1813 int n_saved_fp_regs;
1814 unsigned int fp_start_reg, fp_bound_reg;
1816 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1819 if ((insn & 0x800) == 0x800) /* N0 is set */
1821 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1822 n_saved_fp_regs = 3;
1824 n_saved_fp_regs = 1;
1828 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1829 n_saved_fp_regs = 2;
1831 n_saved_fp_regs = 4;
1834 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1835 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1836 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1838 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1839 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1840 regs[fp_start_reg++]);
1843 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1845 /* Allow some special function calls when skipping the
1846 prologue; GCC generates these before storing arguments to
1848 CORE_ADDR dest = BranchDest (current_pc, insn);
1850 if (skip_prologue_function (gdbarch, dest, 0))
1855 else if ((insn & 0xf0000000) != 0xe0000000)
1856 break; /* Condition not true, exit early. */
1857 else if (arm_instruction_changes_pc (insn))
1858 /* Don't scan past anything that might change control flow. */
1860 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1861 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1862 /* Ignore block loads from the stack, potentially copying
1863 parameters from memory. */
1865 else if ((insn & 0xfc500000) == 0xe4100000
1866 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1867 /* Similarly ignore single loads from the stack. */
1869 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1870 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1871 register instead of the stack. */
1875 /* The optimizer might shove anything into the prologue,
1876 so we just skip what we don't recognize. */
1877 unrecognized_pc = current_pc;
1882 if (unrecognized_pc == 0)
1883 unrecognized_pc = current_pc;
1885 /* The frame size is just the distance from the frame register
1886 to the original stack pointer. */
1887 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1889 /* Frame pointer is fp. */
1890 framereg = ARM_FP_REGNUM;
1891 framesize = -regs[ARM_FP_REGNUM].k;
1895 /* Try the stack pointer... this is a bit desperate. */
1896 framereg = ARM_SP_REGNUM;
1897 framesize = -regs[ARM_SP_REGNUM].k;
1902 cache->framereg = framereg;
1903 cache->framesize = framesize;
1905 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1906 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1907 cache->saved_regs[regno].addr = offset;
1911 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1912 paddress (gdbarch, unrecognized_pc));
1914 do_cleanups (back_to);
1915 return unrecognized_pc;
1919 arm_scan_prologue (struct frame_info *this_frame,
1920 struct arm_prologue_cache *cache)
1922 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1923 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1925 CORE_ADDR prologue_start, prologue_end, current_pc;
1926 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1927 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1928 pv_t regs[ARM_FPS_REGNUM];
1929 struct pv_area *stack;
1930 struct cleanup *back_to;
1933 /* Assume there is no frame until proven otherwise. */
1934 cache->framereg = ARM_SP_REGNUM;
1935 cache->framesize = 0;
1937 /* Check for Thumb prologue. */
1938 if (arm_frame_is_thumb (this_frame))
1940 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1944 /* Find the function prologue. If we can't find the function in
1945 the symbol table, peek in the stack frame to find the PC. */
1946 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1949 /* One way to find the end of the prologue (which works well
1950 for unoptimized code) is to do the following:
1952 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1955 prologue_end = prev_pc;
1956 else if (sal.end < prologue_end)
1957 prologue_end = sal.end;
1959 This mechanism is very accurate so long as the optimizer
1960 doesn't move any instructions from the function body into the
1961 prologue. If this happens, sal.end will be the last
1962 instruction in the first hunk of prologue code just before
1963 the first instruction that the scheduler has moved from
1964 the body to the prologue.
1966 In order to make sure that we scan all of the prologue
1967 instructions, we use a slightly less accurate mechanism which
1968 may scan more than necessary. To help compensate for this
1969 lack of accuracy, the prologue scanning loop below contains
1970 several clauses which'll cause the loop to terminate early if
1971 an implausible prologue instruction is encountered.
1977 is a suitable endpoint since it accounts for the largest
1978 possible prologue plus up to five instructions inserted by
1981 if (prologue_end > prologue_start + 64)
1983 prologue_end = prologue_start + 64; /* See above. */
1988 /* We have no symbol information. Our only option is to assume this
1989 function has a standard stack frame and the normal frame register.
1990 Then, we can find the value of our frame pointer on entrance to
1991 the callee (or at the present moment if this is the innermost frame).
1992 The value stored there should be the address of the stmfd + 8. */
1993 CORE_ADDR frame_loc;
1994 LONGEST return_value;
1996 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1997 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
2001 prologue_start = gdbarch_addr_bits_remove
2002 (gdbarch, return_value) - 8;
2003 prologue_end = prologue_start + 64; /* See above. */
2007 if (prev_pc < prologue_end)
2008 prologue_end = prev_pc;
2010 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2013 static struct arm_prologue_cache *
2014 arm_make_prologue_cache (struct frame_info *this_frame)
2017 struct arm_prologue_cache *cache;
2018 CORE_ADDR unwound_fp;
2020 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2021 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2023 arm_scan_prologue (this_frame, cache);
2025 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2026 if (unwound_fp == 0)
2029 cache->prev_sp = unwound_fp + cache->framesize;
2031 /* Calculate actual addresses of saved registers using offsets
2032 determined by arm_scan_prologue. */
2033 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2034 if (trad_frame_addr_p (cache->saved_regs, reg))
2035 cache->saved_regs[reg].addr += cache->prev_sp;
2040 /* Our frame ID for a normal frame is the current function's starting PC
2041 and the caller's SP when we were called. */
2044 arm_prologue_this_id (struct frame_info *this_frame,
2046 struct frame_id *this_id)
2048 struct arm_prologue_cache *cache;
2052 if (*this_cache == NULL)
2053 *this_cache = arm_make_prologue_cache (this_frame);
2054 cache = *this_cache;
2056 /* This is meant to halt the backtrace at "_start". */
2057 pc = get_frame_pc (this_frame);
2058 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2061 /* If we've hit a wall, stop. */
2062 if (cache->prev_sp == 0)
2065 /* Use function start address as part of the frame ID. If we cannot
2066 identify the start address (due to missing symbol information),
2067 fall back to just using the current PC. */
2068 func = get_frame_func (this_frame);
2072 id = frame_id_build (cache->prev_sp, func);
2076 static struct value *
2077 arm_prologue_prev_register (struct frame_info *this_frame,
2081 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2082 struct arm_prologue_cache *cache;
2084 if (*this_cache == NULL)
2085 *this_cache = arm_make_prologue_cache (this_frame);
2086 cache = *this_cache;
2088 /* If we are asked to unwind the PC, then we need to return the LR
2089 instead. The prologue may save PC, but it will point into this
2090 frame's prologue, not the next frame's resume location. Also
2091 strip the saved T bit. A valid LR may have the low bit set, but
2092 a valid PC never does. */
2093 if (prev_regnum == ARM_PC_REGNUM)
2097 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2098 return frame_unwind_got_constant (this_frame, prev_regnum,
2099 arm_addr_bits_remove (gdbarch, lr));
2102 /* SP is generally not saved to the stack, but this frame is
2103 identified by the next frame's stack pointer at the time of the call.
2104 The value was already reconstructed into PREV_SP. */
2105 if (prev_regnum == ARM_SP_REGNUM)
2106 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2108 /* The CPSR may have been changed by the call instruction and by the
2109 called function. The only bit we can reconstruct is the T bit,
2110 by checking the low bit of LR as of the call. This is a reliable
2111 indicator of Thumb-ness except for some ARM v4T pre-interworking
2112 Thumb code, which could get away with a clear low bit as long as
2113 the called function did not use bx. Guess that all other
2114 bits are unchanged; the condition flags are presumably lost,
2115 but the processor status is likely valid. */
2116 if (prev_regnum == ARM_PS_REGNUM)
2119 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2121 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2122 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2123 if (IS_THUMB_ADDR (lr))
2127 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2130 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2134 struct frame_unwind arm_prologue_unwind = {
2136 default_frame_unwind_stop_reason,
2137 arm_prologue_this_id,
2138 arm_prologue_prev_register,
2140 default_frame_sniffer
2143 /* Maintain a list of ARM exception table entries per objfile, similar to the
2144 list of mapping symbols. We only cache entries for standard ARM-defined
2145 personality routines; the cache will contain only the frame unwinding
2146 instructions associated with the entry (not the descriptors). */
2148 static const struct objfile_data *arm_exidx_data_key;
2150 struct arm_exidx_entry
2155 typedef struct arm_exidx_entry arm_exidx_entry_s;
2156 DEF_VEC_O(arm_exidx_entry_s);
2158 struct arm_exidx_data
2160 VEC(arm_exidx_entry_s) **section_maps;
2164 arm_exidx_data_free (struct objfile *objfile, void *arg)
2166 struct arm_exidx_data *data = arg;
2169 for (i = 0; i < objfile->obfd->section_count; i++)
2170 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2174 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2175 const struct arm_exidx_entry *rhs)
2177 return lhs->addr < rhs->addr;
2180 static struct obj_section *
2181 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2183 struct obj_section *osect;
2185 ALL_OBJFILE_OSECTIONS (objfile, osect)
2186 if (bfd_get_section_flags (objfile->obfd,
2187 osect->the_bfd_section) & SEC_ALLOC)
2189 bfd_vma start, size;
2190 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2191 size = bfd_get_section_size (osect->the_bfd_section);
2193 if (start <= vma && vma < start + size)
2200 /* Parse contents of exception table and exception index sections
2201 of OBJFILE, and fill in the exception table entry cache.
2203 For each entry that refers to a standard ARM-defined personality
2204 routine, extract the frame unwinding instructions (from either
2205 the index or the table section). The unwinding instructions
2207 - extracting them from the rest of the table data
2208 - converting to host endianness
2209 - appending the implicit 0xb0 ("Finish") code
2211 The extracted and normalized instructions are stored for later
2212 retrieval by the arm_find_exidx_entry routine. */
2215 arm_exidx_new_objfile (struct objfile *objfile)
2217 struct cleanup *cleanups;
2218 struct arm_exidx_data *data;
2219 asection *exidx, *extab;
2220 bfd_vma exidx_vma = 0, extab_vma = 0;
2221 bfd_size_type exidx_size = 0, extab_size = 0;
2222 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2225 /* If we've already touched this file, do nothing. */
2226 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2228 cleanups = make_cleanup (null_cleanup, NULL);
2230 /* Read contents of exception table and index. */
2231 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2234 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2235 exidx_size = bfd_get_section_size (exidx);
2236 exidx_data = xmalloc (exidx_size);
2237 make_cleanup (xfree, exidx_data);
2239 if (!bfd_get_section_contents (objfile->obfd, exidx,
2240 exidx_data, 0, exidx_size))
2242 do_cleanups (cleanups);
2247 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2250 extab_vma = bfd_section_vma (objfile->obfd, extab);
2251 extab_size = bfd_get_section_size (extab);
2252 extab_data = xmalloc (extab_size);
2253 make_cleanup (xfree, extab_data);
2255 if (!bfd_get_section_contents (objfile->obfd, extab,
2256 extab_data, 0, extab_size))
2258 do_cleanups (cleanups);
2263 /* Allocate exception table data structure. */
2264 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2265 set_objfile_data (objfile, arm_exidx_data_key, data);
2266 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2267 objfile->obfd->section_count,
2268 VEC(arm_exidx_entry_s) *);
2270 /* Fill in exception table. */
2271 for (i = 0; i < exidx_size / 8; i++)
2273 struct arm_exidx_entry new_exidx_entry;
2274 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2275 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2276 bfd_vma addr = 0, word = 0;
2277 int n_bytes = 0, n_words = 0;
2278 struct obj_section *sec;
2279 gdb_byte *entry = NULL;
2281 /* Extract address of start of function. */
2282 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2283 idx += exidx_vma + i * 8;
2285 /* Find section containing function and compute section offset. */
2286 sec = arm_obj_section_from_vma (objfile, idx);
2289 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2291 /* Determine address of exception table entry. */
2294 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2296 else if ((val & 0xff000000) == 0x80000000)
2298 /* Exception table entry embedded in .ARM.exidx
2299 -- must be short form. */
2303 else if (!(val & 0x80000000))
2305 /* Exception table entry in .ARM.extab. */
2306 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2307 addr += exidx_vma + i * 8 + 4;
2309 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2311 word = bfd_h_get_32 (objfile->obfd,
2312 extab_data + addr - extab_vma);
2315 if ((word & 0xff000000) == 0x80000000)
2320 else if ((word & 0xff000000) == 0x81000000
2321 || (word & 0xff000000) == 0x82000000)
2325 n_words = ((word >> 16) & 0xff);
2327 else if (!(word & 0x80000000))
2330 struct obj_section *pers_sec;
2331 int gnu_personality = 0;
2333 /* Custom personality routine. */
2334 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2335 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2337 /* Check whether we've got one of the variants of the
2338 GNU personality routines. */
2339 pers_sec = arm_obj_section_from_vma (objfile, pers);
2342 static const char *personality[] =
2344 "__gcc_personality_v0",
2345 "__gxx_personality_v0",
2346 "__gcj_personality_v0",
2347 "__gnu_objc_personality_v0",
2351 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2354 for (k = 0; personality[k]; k++)
2355 if (lookup_minimal_symbol_by_pc_name
2356 (pc, personality[k], objfile))
2358 gnu_personality = 1;
2363 /* If so, the next word contains a word count in the high
2364 byte, followed by the same unwind instructions as the
2365 pre-defined forms. */
2367 && addr + 4 <= extab_vma + extab_size)
2369 word = bfd_h_get_32 (objfile->obfd,
2370 extab_data + addr - extab_vma);
2373 n_words = ((word >> 24) & 0xff);
2379 /* Sanity check address. */
2381 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2382 n_words = n_bytes = 0;
2384 /* The unwind instructions reside in WORD (only the N_BYTES least
2385 significant bytes are valid), followed by N_WORDS words in the
2386 extab section starting at ADDR. */
2387 if (n_bytes || n_words)
2389 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2390 n_bytes + n_words * 4 + 1);
2393 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2397 word = bfd_h_get_32 (objfile->obfd,
2398 extab_data + addr - extab_vma);
2401 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2402 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2403 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2404 *p++ = (gdb_byte) (word & 0xff);
2407 /* Implied "Finish" to terminate the list. */
2411 /* Push entry onto vector. They are guaranteed to always
2412 appear in order of increasing addresses. */
2413 new_exidx_entry.addr = idx;
2414 new_exidx_entry.entry = entry;
2415 VEC_safe_push (arm_exidx_entry_s,
2416 data->section_maps[sec->the_bfd_section->index],
2420 do_cleanups (cleanups);
2423 /* Search for the exception table entry covering MEMADDR. If one is found,
2424 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2425 set *START to the start of the region covered by this entry. */
2428 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2430 struct obj_section *sec;
2432 sec = find_pc_section (memaddr);
2435 struct arm_exidx_data *data;
2436 VEC(arm_exidx_entry_s) *map;
2437 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2440 data = objfile_data (sec->objfile, arm_exidx_data_key);
2443 map = data->section_maps[sec->the_bfd_section->index];
2444 if (!VEC_empty (arm_exidx_entry_s, map))
2446 struct arm_exidx_entry *map_sym;
2448 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2449 arm_compare_exidx_entries);
2451 /* VEC_lower_bound finds the earliest ordered insertion
2452 point. If the following symbol starts at this exact
2453 address, we use that; otherwise, the preceding
2454 exception table entry covers this address. */
2455 if (idx < VEC_length (arm_exidx_entry_s, map))
2457 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2458 if (map_sym->addr == map_key.addr)
2461 *start = map_sym->addr + obj_section_addr (sec);
2462 return map_sym->entry;
2468 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2470 *start = map_sym->addr + obj_section_addr (sec);
2471 return map_sym->entry;
2480 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2481 instruction list from the ARM exception table entry ENTRY, allocate and
2482 return a prologue cache structure describing how to unwind this frame.
2484 Return NULL if the unwinding instruction list contains a "spare",
2485 "reserved" or "refuse to unwind" instruction as defined in section
2486 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2487 for the ARM Architecture" document. */
2489 static struct arm_prologue_cache *
2490 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2495 struct arm_prologue_cache *cache;
2496 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2497 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2503 /* Whenever we reload SP, we actually have to retrieve its
2504 actual value in the current frame. */
2507 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2509 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2510 vsp = get_frame_register_unsigned (this_frame, reg);
2514 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2515 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2521 /* Decode next unwind instruction. */
2524 if ((insn & 0xc0) == 0)
2526 int offset = insn & 0x3f;
2527 vsp += (offset << 2) + 4;
2529 else if ((insn & 0xc0) == 0x40)
2531 int offset = insn & 0x3f;
2532 vsp -= (offset << 2) + 4;
2534 else if ((insn & 0xf0) == 0x80)
2536 int mask = ((insn & 0xf) << 8) | *entry++;
2539 /* The special case of an all-zero mask identifies
2540 "Refuse to unwind". We return NULL to fall back
2541 to the prologue analyzer. */
2545 /* Pop registers r4..r15 under mask. */
2546 for (i = 0; i < 12; i++)
2547 if (mask & (1 << i))
2549 cache->saved_regs[4 + i].addr = vsp;
2553 /* Special-case popping SP -- we need to reload vsp. */
2554 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2557 else if ((insn & 0xf0) == 0x90)
2559 int reg = insn & 0xf;
2561 /* Reserved cases. */
2562 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2565 /* Set SP from another register and mark VSP for reload. */
2566 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2569 else if ((insn & 0xf0) == 0xa0)
2571 int count = insn & 0x7;
2572 int pop_lr = (insn & 0x8) != 0;
2575 /* Pop r4..r[4+count]. */
2576 for (i = 0; i <= count; i++)
2578 cache->saved_regs[4 + i].addr = vsp;
2582 /* If indicated by flag, pop LR as well. */
2585 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2589 else if (insn == 0xb0)
2591 /* We could only have updated PC by popping into it; if so, it
2592 will show up as address. Otherwise, copy LR into PC. */
2593 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2594 cache->saved_regs[ARM_PC_REGNUM]
2595 = cache->saved_regs[ARM_LR_REGNUM];
2600 else if (insn == 0xb1)
2602 int mask = *entry++;
2605 /* All-zero mask and mask >= 16 is "spare". */
2606 if (mask == 0 || mask >= 16)
2609 /* Pop r0..r3 under mask. */
2610 for (i = 0; i < 4; i++)
2611 if (mask & (1 << i))
2613 cache->saved_regs[i].addr = vsp;
2617 else if (insn == 0xb2)
2619 ULONGEST offset = 0;
2624 offset |= (*entry & 0x7f) << shift;
2627 while (*entry++ & 0x80);
2629 vsp += 0x204 + (offset << 2);
2631 else if (insn == 0xb3)
2633 int start = *entry >> 4;
2634 int count = (*entry++) & 0xf;
2637 /* Only registers D0..D15 are valid here. */
2638 if (start + count >= 16)
2641 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2642 for (i = 0; i <= count; i++)
2644 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2648 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2651 else if ((insn & 0xf8) == 0xb8)
2653 int count = insn & 0x7;
2656 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2657 for (i = 0; i <= count; i++)
2659 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2663 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2666 else if (insn == 0xc6)
2668 int start = *entry >> 4;
2669 int count = (*entry++) & 0xf;
2672 /* Only registers WR0..WR15 are valid. */
2673 if (start + count >= 16)
2676 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2677 for (i = 0; i <= count; i++)
2679 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2683 else if (insn == 0xc7)
2685 int mask = *entry++;
2688 /* All-zero mask and mask >= 16 is "spare". */
2689 if (mask == 0 || mask >= 16)
2692 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2693 for (i = 0; i < 4; i++)
2694 if (mask & (1 << i))
2696 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2700 else if ((insn & 0xf8) == 0xc0)
2702 int count = insn & 0x7;
2705 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2706 for (i = 0; i <= count; i++)
2708 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2712 else if (insn == 0xc8)
2714 int start = *entry >> 4;
2715 int count = (*entry++) & 0xf;
2718 /* Only registers D0..D31 are valid. */
2719 if (start + count >= 16)
2722 /* Pop VFP double-precision registers
2723 D[16+start]..D[16+start+count]. */
2724 for (i = 0; i <= count; i++)
2726 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2730 else if (insn == 0xc9)
2732 int start = *entry >> 4;
2733 int count = (*entry++) & 0xf;
2736 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2737 for (i = 0; i <= count; i++)
2739 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2743 else if ((insn & 0xf8) == 0xd0)
2745 int count = insn & 0x7;
2748 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2749 for (i = 0; i <= count; i++)
2751 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2757 /* Everything else is "spare". */
2762 /* If we restore SP from a register, assume this was the frame register.
2763 Otherwise just fall back to SP as frame register. */
2764 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2765 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2767 cache->framereg = ARM_SP_REGNUM;
2769 /* Determine offset to previous frame. */
2771 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2773 /* We already got the previous SP. */
2774 cache->prev_sp = vsp;
2779 /* Unwinding via ARM exception table entries. Note that the sniffer
2780 already computes a filled-in prologue cache, which is then used
2781 with the same arm_prologue_this_id and arm_prologue_prev_register
2782 routines also used for prologue-parsing based unwinding. */
2785 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2786 struct frame_info *this_frame,
2787 void **this_prologue_cache)
2789 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2790 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2791 CORE_ADDR addr_in_block, exidx_region, func_start;
2792 struct arm_prologue_cache *cache;
2795 /* See if we have an ARM exception table entry covering this address. */
2796 addr_in_block = get_frame_address_in_block (this_frame);
2797 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2801 /* The ARM exception table does not describe unwind information
2802 for arbitrary PC values, but is guaranteed to be correct only
2803 at call sites. We have to decide here whether we want to use
2804 ARM exception table information for this frame, or fall back
2805 to using prologue parsing. (Note that if we have DWARF CFI,
2806 this sniffer isn't even called -- CFI is always preferred.)
2808 Before we make this decision, however, we check whether we
2809 actually have *symbol* information for the current frame.
2810 If not, prologue parsing would not work anyway, so we might
2811 as well use the exception table and hope for the best. */
2812 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2816 /* If the next frame is "normal", we are at a call site in this
2817 frame, so exception information is guaranteed to be valid. */
2818 if (get_next_frame (this_frame)
2819 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2822 /* We also assume exception information is valid if we're currently
2823 blocked in a system call. The system library is supposed to
2824 ensure this, so that e.g. pthread cancellation works. */
2825 if (arm_frame_is_thumb (this_frame))
2829 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2830 byte_order_for_code, &insn)
2831 && (insn & 0xff00) == 0xdf00 /* svc */)
2838 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2839 byte_order_for_code, &insn)
2840 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2844 /* Bail out if we don't know that exception information is valid. */
2848 /* The ARM exception index does not mark the *end* of the region
2849 covered by the entry, and some functions will not have any entry.
2850 To correctly recognize the end of the covered region, the linker
2851 should have inserted dummy records with a CANTUNWIND marker.
2853 Unfortunately, current versions of GNU ld do not reliably do
2854 this, and thus we may have found an incorrect entry above.
2855 As a (temporary) sanity check, we only use the entry if it
2856 lies *within* the bounds of the function. Note that this check
2857 might reject perfectly valid entries that just happen to cover
2858 multiple functions; therefore this check ought to be removed
2859 once the linker is fixed. */
2860 if (func_start > exidx_region)
2864 /* Decode the list of unwinding instructions into a prologue cache.
2865 Note that this may fail due to e.g. a "refuse to unwind" code. */
2866 cache = arm_exidx_fill_cache (this_frame, entry);
2870 *this_prologue_cache = cache;
2874 struct frame_unwind arm_exidx_unwind = {
2876 default_frame_unwind_stop_reason,
2877 arm_prologue_this_id,
2878 arm_prologue_prev_register,
2880 arm_exidx_unwind_sniffer
2883 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2884 trampoline, return the target PC. Otherwise return 0.
2886 void call0a (char c, short s, int i, long l) {}
2890 (*pointer_to_call0a) (c, s, i, l);
2893 Instead of calling a stub library function _call_via_xx (xx is
2894 the register name), GCC may inline the trampoline in the object
2895 file as below (register r2 has the address of call0a).
2898 .type main, %function
2907 The trampoline 'bx r2' doesn't belong to main. */
2910 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2912 /* The heuristics of recognizing such trampoline is that FRAME is
2913 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2914 if (arm_frame_is_thumb (frame))
2918 if (target_read_memory (pc, buf, 2) == 0)
2920 struct gdbarch *gdbarch = get_frame_arch (frame);
2921 enum bfd_endian byte_order_for_code
2922 = gdbarch_byte_order_for_code (gdbarch);
2924 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2926 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2929 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2931 /* Clear the LSB so that gdb core sets step-resume
2932 breakpoint at the right address. */
2933 return UNMAKE_THUMB_ADDR (dest);
2941 static struct arm_prologue_cache *
2942 arm_make_stub_cache (struct frame_info *this_frame)
2944 struct arm_prologue_cache *cache;
2946 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2947 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2949 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2954 /* Our frame ID for a stub frame is the current SP and LR. */
2957 arm_stub_this_id (struct frame_info *this_frame,
2959 struct frame_id *this_id)
2961 struct arm_prologue_cache *cache;
2963 if (*this_cache == NULL)
2964 *this_cache = arm_make_stub_cache (this_frame);
2965 cache = *this_cache;
2967 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2971 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2972 struct frame_info *this_frame,
2973 void **this_prologue_cache)
2975 CORE_ADDR addr_in_block;
2977 CORE_ADDR pc, start_addr;
2980 addr_in_block = get_frame_address_in_block (this_frame);
2981 pc = get_frame_pc (this_frame);
2982 if (in_plt_section (addr_in_block)
2983 /* We also use the stub winder if the target memory is unreadable
2984 to avoid having the prologue unwinder trying to read it. */
2985 || target_read_memory (pc, dummy, 4) != 0)
2988 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2989 && arm_skip_bx_reg (this_frame, pc) != 0)
2995 struct frame_unwind arm_stub_unwind = {
2997 default_frame_unwind_stop_reason,
2999 arm_prologue_prev_register,
3001 arm_stub_unwind_sniffer
3004 /* Put here the code to store, into CACHE->saved_regs, the addresses
3005 of the saved registers of frame described by THIS_FRAME. CACHE is
3008 static struct arm_prologue_cache *
3009 arm_m_exception_cache (struct frame_info *this_frame)
3011 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3012 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3013 struct arm_prologue_cache *cache;
3014 CORE_ADDR unwound_sp;
3017 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
3018 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3020 unwound_sp = get_frame_register_unsigned (this_frame,
3023 /* The hardware saves eight 32-bit words, comprising xPSR,
3024 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3025 "B1.5.6 Exception entry behavior" in
3026 "ARMv7-M Architecture Reference Manual". */
3027 cache->saved_regs[0].addr = unwound_sp;
3028 cache->saved_regs[1].addr = unwound_sp + 4;
3029 cache->saved_regs[2].addr = unwound_sp + 8;
3030 cache->saved_regs[3].addr = unwound_sp + 12;
3031 cache->saved_regs[12].addr = unwound_sp + 16;
3032 cache->saved_regs[14].addr = unwound_sp + 20;
3033 cache->saved_regs[15].addr = unwound_sp + 24;
3034 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
3036 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3037 aligner between the top of the 32-byte stack frame and the
3038 previous context's stack pointer. */
3039 cache->prev_sp = unwound_sp + 32;
3040 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
3041 && (xpsr & (1 << 9)) != 0)
3042 cache->prev_sp += 4;
3047 /* Implementation of function hook 'this_id' in
3048 'struct frame_uwnind'. */
3051 arm_m_exception_this_id (struct frame_info *this_frame,
3053 struct frame_id *this_id)
3055 struct arm_prologue_cache *cache;
3057 if (*this_cache == NULL)
3058 *this_cache = arm_m_exception_cache (this_frame);
3059 cache = *this_cache;
3061 /* Our frame ID for a stub frame is the current SP and LR. */
3062 *this_id = frame_id_build (cache->prev_sp,
3063 get_frame_pc (this_frame));
3066 /* Implementation of function hook 'prev_register' in
3067 'struct frame_uwnind'. */
3069 static struct value *
3070 arm_m_exception_prev_register (struct frame_info *this_frame,
3074 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3075 struct arm_prologue_cache *cache;
3077 if (*this_cache == NULL)
3078 *this_cache = arm_m_exception_cache (this_frame);
3079 cache = *this_cache;
3081 /* The value was already reconstructed into PREV_SP. */
3082 if (prev_regnum == ARM_SP_REGNUM)
3083 return frame_unwind_got_constant (this_frame, prev_regnum,
3086 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3090 /* Implementation of function hook 'sniffer' in
3091 'struct frame_uwnind'. */
3094 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3095 struct frame_info *this_frame,
3096 void **this_prologue_cache)
3098 CORE_ADDR this_pc = get_frame_pc (this_frame);
3100 /* No need to check is_m; this sniffer is only registered for
3101 M-profile architectures. */
3103 /* Exception frames return to one of these magic PCs. Other values
3104 are not defined as of v7-M. See details in "B1.5.8 Exception
3105 return behavior" in "ARMv7-M Architecture Reference Manual". */
3106 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3107 || this_pc == 0xfffffffd)
3113 /* Frame unwinder for M-profile exceptions. */
3115 struct frame_unwind arm_m_exception_unwind =
3118 default_frame_unwind_stop_reason,
3119 arm_m_exception_this_id,
3120 arm_m_exception_prev_register,
3122 arm_m_exception_unwind_sniffer
3126 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3128 struct arm_prologue_cache *cache;
3130 if (*this_cache == NULL)
3131 *this_cache = arm_make_prologue_cache (this_frame);
3132 cache = *this_cache;
3134 return cache->prev_sp - cache->framesize;
3137 struct frame_base arm_normal_base = {
3138 &arm_prologue_unwind,
3139 arm_normal_frame_base,
3140 arm_normal_frame_base,
3141 arm_normal_frame_base
3144 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3145 dummy frame. The frame ID's base needs to match the TOS value
3146 saved by save_dummy_frame_tos() and returned from
3147 arm_push_dummy_call, and the PC needs to match the dummy frame's
3150 static struct frame_id
3151 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3153 return frame_id_build (get_frame_register_unsigned (this_frame,
3155 get_frame_pc (this_frame));
3158 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3159 be used to construct the previous frame's ID, after looking up the
3160 containing function). */
3163 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3166 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3167 return arm_addr_bits_remove (gdbarch, pc);
3171 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3173 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3176 static struct value *
3177 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3180 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3182 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3187 /* The PC is normally copied from the return column, which
3188 describes saves of LR. However, that version may have an
3189 extra bit set to indicate Thumb state. The bit is not
3191 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3192 return frame_unwind_got_constant (this_frame, regnum,
3193 arm_addr_bits_remove (gdbarch, lr));
3196 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3197 cpsr = get_frame_register_unsigned (this_frame, regnum);
3198 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3199 if (IS_THUMB_ADDR (lr))
3203 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3206 internal_error (__FILE__, __LINE__,
3207 _("Unexpected register %d"), regnum);
3212 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3213 struct dwarf2_frame_state_reg *reg,
3214 struct frame_info *this_frame)
3220 reg->how = DWARF2_FRAME_REG_FN;
3221 reg->loc.fn = arm_dwarf2_prev_register;
3224 reg->how = DWARF2_FRAME_REG_CFA;
3229 /* Return true if we are in the function's epilogue, i.e. after the
3230 instruction that destroyed the function's stack frame. */
3233 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3235 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3236 unsigned int insn, insn2;
3237 int found_return = 0, found_stack_adjust = 0;
3238 CORE_ADDR func_start, func_end;
3242 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3245 /* The epilogue is a sequence of instructions along the following lines:
3247 - add stack frame size to SP or FP
3248 - [if frame pointer used] restore SP from FP
3249 - restore registers from SP [may include PC]
3250 - a return-type instruction [if PC wasn't already restored]
3252 In a first pass, we scan forward from the current PC and verify the
3253 instructions we find as compatible with this sequence, ending in a
3256 However, this is not sufficient to distinguish indirect function calls
3257 within a function from indirect tail calls in the epilogue in some cases.
3258 Therefore, if we didn't already find any SP-changing instruction during
3259 forward scan, we add a backward scanning heuristic to ensure we actually
3260 are in the epilogue. */
3263 while (scan_pc < func_end && !found_return)
3265 if (target_read_memory (scan_pc, buf, 2))
3269 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3271 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3273 else if (insn == 0x46f7) /* mov pc, lr */
3275 else if (thumb_instruction_restores_sp (insn))
3277 found_stack_adjust = 1;
3278 if ((insn & 0xfe00) == 0xbd00) /* pop <registers, PC> */
3281 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3283 if (target_read_memory (scan_pc, buf, 2))
3287 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3289 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3291 found_stack_adjust = 1;
3292 if (insn2 & 0x8000) /* <registers> include PC. */
3295 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3296 && (insn2 & 0x0fff) == 0x0b04)
3298 found_stack_adjust = 1;
3299 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3302 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3303 && (insn2 & 0x0e00) == 0x0a00)
3304 found_stack_adjust = 1;
3315 /* Since any instruction in the epilogue sequence, with the possible
3316 exception of return itself, updates the stack pointer, we need to
3317 scan backwards for at most one instruction. Try either a 16-bit or
3318 a 32-bit instruction. This is just a heuristic, so we do not worry
3319 too much about false positives. */
3321 if (!found_stack_adjust)
3323 if (pc - 4 < func_start)
3325 if (target_read_memory (pc - 4, buf, 4))
3328 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3329 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3331 if (thumb_instruction_restores_sp (insn2))
3332 found_stack_adjust = 1;
3333 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3334 found_stack_adjust = 1;
3335 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3336 && (insn2 & 0x0fff) == 0x0b04)
3337 found_stack_adjust = 1;
3338 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3339 && (insn2 & 0x0e00) == 0x0a00)
3340 found_stack_adjust = 1;
3343 return found_stack_adjust;
3346 /* Return true if we are in the function's epilogue, i.e. after the
3347 instruction that destroyed the function's stack frame. */
3350 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3352 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3354 int found_return, found_stack_adjust;
3355 CORE_ADDR func_start, func_end;
3357 if (arm_pc_is_thumb (gdbarch, pc))
3358 return thumb_in_function_epilogue_p (gdbarch, pc);
3360 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3363 /* We are in the epilogue if the previous instruction was a stack
3364 adjustment and the next instruction is a possible return (bx, mov
3365 pc, or pop). We could have to scan backwards to find the stack
3366 adjustment, or forwards to find the return, but this is a decent
3367 approximation. First scan forwards. */
3370 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3371 if (bits (insn, 28, 31) != INST_NV)
3373 if ((insn & 0x0ffffff0) == 0x012fff10)
3376 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3379 else if ((insn & 0x0fff0000) == 0x08bd0000
3380 && (insn & 0x0000c000) != 0)
3381 /* POP (LDMIA), including PC or LR. */
3388 /* Scan backwards. This is just a heuristic, so do not worry about
3389 false positives from mode changes. */
3391 if (pc < func_start + 4)
3394 found_stack_adjust = 0;
3395 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3396 if (bits (insn, 28, 31) != INST_NV)
3398 if ((insn & 0x0df0f000) == 0x0080d000)
3399 /* ADD SP (register or immediate). */
3400 found_stack_adjust = 1;
3401 else if ((insn & 0x0df0f000) == 0x0040d000)
3402 /* SUB SP (register or immediate). */
3403 found_stack_adjust = 1;
3404 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3406 found_stack_adjust = 1;
3407 else if ((insn & 0x0fff0000) == 0x08bd0000)
3409 found_stack_adjust = 1;
3410 else if ((insn & 0x0fff0000) == 0x049d0000)
3411 /* POP of a single register. */
3412 found_stack_adjust = 1;
3415 if (found_stack_adjust)
3422 /* When arguments must be pushed onto the stack, they go on in reverse
3423 order. The code below implements a FILO (stack) to do this. */
3428 struct stack_item *prev;
3432 static struct stack_item *
3433 push_stack_item (struct stack_item *prev, const void *contents, int len)
3435 struct stack_item *si;
3436 si = xmalloc (sizeof (struct stack_item));
3437 si->data = xmalloc (len);
3440 memcpy (si->data, contents, len);
3444 static struct stack_item *
3445 pop_stack_item (struct stack_item *si)
3447 struct stack_item *dead = si;
3455 /* Return the alignment (in bytes) of the given type. */
3458 arm_type_align (struct type *t)
3464 t = check_typedef (t);
3465 switch (TYPE_CODE (t))
3468 /* Should never happen. */
3469 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3473 case TYPE_CODE_ENUM:
3477 case TYPE_CODE_RANGE:
3479 case TYPE_CODE_CHAR:
3480 case TYPE_CODE_BOOL:
3481 return TYPE_LENGTH (t);
3483 case TYPE_CODE_ARRAY:
3484 case TYPE_CODE_COMPLEX:
3485 /* TODO: What about vector types? */
3486 return arm_type_align (TYPE_TARGET_TYPE (t));
3488 case TYPE_CODE_STRUCT:
3489 case TYPE_CODE_UNION:
3491 for (n = 0; n < TYPE_NFIELDS (t); n++)
3493 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3501 /* Possible base types for a candidate for passing and returning in
3504 enum arm_vfp_cprc_base_type
3513 /* The length of one element of base type B. */
3516 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3520 case VFP_CPRC_SINGLE:
3522 case VFP_CPRC_DOUBLE:
3524 case VFP_CPRC_VEC64:
3526 case VFP_CPRC_VEC128:
3529 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3534 /* The character ('s', 'd' or 'q') for the type of VFP register used
3535 for passing base type B. */
3538 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3542 case VFP_CPRC_SINGLE:
3544 case VFP_CPRC_DOUBLE:
3546 case VFP_CPRC_VEC64:
3548 case VFP_CPRC_VEC128:
3551 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3556 /* Determine whether T may be part of a candidate for passing and
3557 returning in VFP registers, ignoring the limit on the total number
3558 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3559 classification of the first valid component found; if it is not
3560 VFP_CPRC_UNKNOWN, all components must have the same classification
3561 as *BASE_TYPE. If it is found that T contains a type not permitted
3562 for passing and returning in VFP registers, a type differently
3563 classified from *BASE_TYPE, or two types differently classified
3564 from each other, return -1, otherwise return the total number of
3565 base-type elements found (possibly 0 in an empty structure or
3566 array). Vectors and complex types are not currently supported,
3567 matching the generic AAPCS support. */
3570 arm_vfp_cprc_sub_candidate (struct type *t,
3571 enum arm_vfp_cprc_base_type *base_type)
3573 t = check_typedef (t);
3574 switch (TYPE_CODE (t))
3577 switch (TYPE_LENGTH (t))
3580 if (*base_type == VFP_CPRC_UNKNOWN)
3581 *base_type = VFP_CPRC_SINGLE;
3582 else if (*base_type != VFP_CPRC_SINGLE)
3587 if (*base_type == VFP_CPRC_UNKNOWN)
3588 *base_type = VFP_CPRC_DOUBLE;
3589 else if (*base_type != VFP_CPRC_DOUBLE)
3598 case TYPE_CODE_ARRAY:
3602 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3605 if (TYPE_LENGTH (t) == 0)
3607 gdb_assert (count == 0);
3610 else if (count == 0)
3612 unitlen = arm_vfp_cprc_unit_length (*base_type);
3613 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3614 return TYPE_LENGTH (t) / unitlen;
3618 case TYPE_CODE_STRUCT:
3623 for (i = 0; i < TYPE_NFIELDS (t); i++)
3625 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3627 if (sub_count == -1)
3631 if (TYPE_LENGTH (t) == 0)
3633 gdb_assert (count == 0);
3636 else if (count == 0)
3638 unitlen = arm_vfp_cprc_unit_length (*base_type);
3639 if (TYPE_LENGTH (t) != unitlen * count)
3644 case TYPE_CODE_UNION:
3649 for (i = 0; i < TYPE_NFIELDS (t); i++)
3651 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3653 if (sub_count == -1)
3655 count = (count > sub_count ? count : sub_count);
3657 if (TYPE_LENGTH (t) == 0)
3659 gdb_assert (count == 0);
3662 else if (count == 0)
3664 unitlen = arm_vfp_cprc_unit_length (*base_type);
3665 if (TYPE_LENGTH (t) != unitlen * count)
3677 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3678 if passed to or returned from a non-variadic function with the VFP
3679 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3680 *BASE_TYPE to the base type for T and *COUNT to the number of
3681 elements of that base type before returning. */
3684 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3687 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3688 int c = arm_vfp_cprc_sub_candidate (t, &b);
3689 if (c <= 0 || c > 4)
3696 /* Return 1 if the VFP ABI should be used for passing arguments to and
3697 returning values from a function of type FUNC_TYPE, 0
3701 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3703 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3704 /* Variadic functions always use the base ABI. Assume that functions
3705 without debug info are not variadic. */
3706 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3708 /* The VFP ABI is only supported as a variant of AAPCS. */
3709 if (tdep->arm_abi != ARM_ABI_AAPCS)
3711 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3714 /* We currently only support passing parameters in integer registers, which
3715 conforms with GCC's default model, and VFP argument passing following
3716 the VFP variant of AAPCS. Several other variants exist and
3717 we should probably support some of them based on the selected ABI. */
3720 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3721 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3722 struct value **args, CORE_ADDR sp, int struct_return,
3723 CORE_ADDR struct_addr)
3725 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3729 struct stack_item *si = NULL;
3732 unsigned vfp_regs_free = (1 << 16) - 1;
3734 /* Determine the type of this function and whether the VFP ABI
3736 ftype = check_typedef (value_type (function));
3737 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3738 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3739 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3741 /* Set the return address. For the ARM, the return breakpoint is
3742 always at BP_ADDR. */
3743 if (arm_pc_is_thumb (gdbarch, bp_addr))
3745 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3747 /* Walk through the list of args and determine how large a temporary
3748 stack is required. Need to take care here as structs may be
3749 passed on the stack, and we have to push them. */
3752 argreg = ARM_A1_REGNUM;
3755 /* The struct_return pointer occupies the first parameter
3756 passing register. */
3760 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3761 gdbarch_register_name (gdbarch, argreg),
3762 paddress (gdbarch, struct_addr));
3763 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3767 for (argnum = 0; argnum < nargs; argnum++)
3770 struct type *arg_type;
3771 struct type *target_type;
3772 enum type_code typecode;
3773 const bfd_byte *val;
3775 enum arm_vfp_cprc_base_type vfp_base_type;
3777 int may_use_core_reg = 1;
3779 arg_type = check_typedef (value_type (args[argnum]));
3780 len = TYPE_LENGTH (arg_type);
3781 target_type = TYPE_TARGET_TYPE (arg_type);
3782 typecode = TYPE_CODE (arg_type);
3783 val = value_contents (args[argnum]);
3785 align = arm_type_align (arg_type);
3786 /* Round alignment up to a whole number of words. */
3787 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3788 /* Different ABIs have different maximum alignments. */
3789 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3791 /* The APCS ABI only requires word alignment. */
3792 align = INT_REGISTER_SIZE;
3796 /* The AAPCS requires at most doubleword alignment. */
3797 if (align > INT_REGISTER_SIZE * 2)
3798 align = INT_REGISTER_SIZE * 2;
3802 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3810 /* Because this is a CPRC it cannot go in a core register or
3811 cause a core register to be skipped for alignment.
3812 Either it goes in VFP registers and the rest of this loop
3813 iteration is skipped for this argument, or it goes on the
3814 stack (and the stack alignment code is correct for this
3816 may_use_core_reg = 0;
3818 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3819 shift = unit_length / 4;
3820 mask = (1 << (shift * vfp_base_count)) - 1;
3821 for (regno = 0; regno < 16; regno += shift)
3822 if (((vfp_regs_free >> regno) & mask) == mask)
3831 vfp_regs_free &= ~(mask << regno);
3832 reg_scaled = regno / shift;
3833 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3834 for (i = 0; i < vfp_base_count; i++)
3838 if (reg_char == 'q')
3839 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3840 val + i * unit_length);
3843 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3844 reg_char, reg_scaled + i);
3845 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3847 regcache_cooked_write (regcache, regnum,
3848 val + i * unit_length);
3855 /* This CPRC could not go in VFP registers, so all VFP
3856 registers are now marked as used. */
3861 /* Push stack padding for dowubleword alignment. */
3862 if (nstack & (align - 1))
3864 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3865 nstack += INT_REGISTER_SIZE;
3868 /* Doubleword aligned quantities must go in even register pairs. */
3869 if (may_use_core_reg
3870 && argreg <= ARM_LAST_ARG_REGNUM
3871 && align > INT_REGISTER_SIZE
3875 /* If the argument is a pointer to a function, and it is a
3876 Thumb function, create a LOCAL copy of the value and set
3877 the THUMB bit in it. */
3878 if (TYPE_CODE_PTR == typecode
3879 && target_type != NULL
3880 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3882 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3883 if (arm_pc_is_thumb (gdbarch, regval))
3885 bfd_byte *copy = alloca (len);
3886 store_unsigned_integer (copy, len, byte_order,
3887 MAKE_THUMB_ADDR (regval));
3892 /* Copy the argument to general registers or the stack in
3893 register-sized pieces. Large arguments are split between
3894 registers and stack. */
3897 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3899 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3901 /* The argument is being passed in a general purpose
3904 = extract_unsigned_integer (val, partial_len, byte_order);
3905 if (byte_order == BFD_ENDIAN_BIG)
3906 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3908 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3910 gdbarch_register_name
3912 phex (regval, INT_REGISTER_SIZE));
3913 regcache_cooked_write_unsigned (regcache, argreg, regval);
3918 /* Push the arguments onto the stack. */
3920 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3922 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3923 nstack += INT_REGISTER_SIZE;
3930 /* If we have an odd number of words to push, then decrement the stack
3931 by one word now, so first stack argument will be dword aligned. */
3938 write_memory (sp, si->data, si->len);
3939 si = pop_stack_item (si);
3942 /* Finally, update teh SP register. */
3943 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3949 /* Always align the frame to an 8-byte boundary. This is required on
3950 some platforms and harmless on the rest. */
3953 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3955 /* Align the stack to eight bytes. */
3956 return sp & ~ (CORE_ADDR) 7;
3960 print_fpu_flags (struct ui_file *file, int flags)
3962 if (flags & (1 << 0))
3963 fputs_filtered ("IVO ", file);
3964 if (flags & (1 << 1))
3965 fputs_filtered ("DVZ ", file);
3966 if (flags & (1 << 2))
3967 fputs_filtered ("OFL ", file);
3968 if (flags & (1 << 3))
3969 fputs_filtered ("UFL ", file);
3970 if (flags & (1 << 4))
3971 fputs_filtered ("INX ", file);
3972 fputc_filtered ('\n', file);
3975 /* Print interesting information about the floating point processor
3976 (if present) or emulator. */
3978 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3979 struct frame_info *frame, const char *args)
3981 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3984 type = (status >> 24) & 127;
3985 if (status & (1 << 31))
3986 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3988 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3989 /* i18n: [floating point unit] mask */
3990 fputs_filtered (_("mask: "), file);
3991 print_fpu_flags (file, status >> 16);
3992 /* i18n: [floating point unit] flags */
3993 fputs_filtered (_("flags: "), file);
3994 print_fpu_flags (file, status);
3997 /* Construct the ARM extended floating point type. */
3998 static struct type *
3999 arm_ext_type (struct gdbarch *gdbarch)
4001 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4003 if (!tdep->arm_ext_type)
4005 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
4006 floatformats_arm_ext);
4008 return tdep->arm_ext_type;
4011 static struct type *
4012 arm_neon_double_type (struct gdbarch *gdbarch)
4014 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4016 if (tdep->neon_double_type == NULL)
4018 struct type *t, *elem;
4020 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
4022 elem = builtin_type (gdbarch)->builtin_uint8;
4023 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
4024 elem = builtin_type (gdbarch)->builtin_uint16;
4025 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
4026 elem = builtin_type (gdbarch)->builtin_uint32;
4027 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
4028 elem = builtin_type (gdbarch)->builtin_uint64;
4029 append_composite_type_field (t, "u64", elem);
4030 elem = builtin_type (gdbarch)->builtin_float;
4031 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
4032 elem = builtin_type (gdbarch)->builtin_double;
4033 append_composite_type_field (t, "f64", elem);
4035 TYPE_VECTOR (t) = 1;
4036 TYPE_NAME (t) = "neon_d";
4037 tdep->neon_double_type = t;
4040 return tdep->neon_double_type;
4043 /* FIXME: The vector types are not correctly ordered on big-endian
4044 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4045 bits of d0 - regardless of what unit size is being held in d0. So
4046 the offset of the first uint8 in d0 is 7, but the offset of the
4047 first float is 4. This code works as-is for little-endian
4050 static struct type *
4051 arm_neon_quad_type (struct gdbarch *gdbarch)
4053 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4055 if (tdep->neon_quad_type == NULL)
4057 struct type *t, *elem;
4059 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4061 elem = builtin_type (gdbarch)->builtin_uint8;
4062 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4063 elem = builtin_type (gdbarch)->builtin_uint16;
4064 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4065 elem = builtin_type (gdbarch)->builtin_uint32;
4066 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4067 elem = builtin_type (gdbarch)->builtin_uint64;
4068 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4069 elem = builtin_type (gdbarch)->builtin_float;
4070 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4071 elem = builtin_type (gdbarch)->builtin_double;
4072 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4074 TYPE_VECTOR (t) = 1;
4075 TYPE_NAME (t) = "neon_q";
4076 tdep->neon_quad_type = t;
4079 return tdep->neon_quad_type;
4082 /* Return the GDB type object for the "standard" data type of data in
4085 static struct type *
4086 arm_register_type (struct gdbarch *gdbarch, int regnum)
4088 int num_regs = gdbarch_num_regs (gdbarch);
4090 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4091 && regnum >= num_regs && regnum < num_regs + 32)
4092 return builtin_type (gdbarch)->builtin_float;
4094 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4095 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4096 return arm_neon_quad_type (gdbarch);
4098 /* If the target description has register information, we are only
4099 in this function so that we can override the types of
4100 double-precision registers for NEON. */
4101 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4103 struct type *t = tdesc_register_type (gdbarch, regnum);
4105 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4106 && TYPE_CODE (t) == TYPE_CODE_FLT
4107 && gdbarch_tdep (gdbarch)->have_neon)
4108 return arm_neon_double_type (gdbarch);
4113 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4115 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4116 return builtin_type (gdbarch)->builtin_void;
4118 return arm_ext_type (gdbarch);
4120 else if (regnum == ARM_SP_REGNUM)
4121 return builtin_type (gdbarch)->builtin_data_ptr;
4122 else if (regnum == ARM_PC_REGNUM)
4123 return builtin_type (gdbarch)->builtin_func_ptr;
4124 else if (regnum >= ARRAY_SIZE (arm_register_names))
4125 /* These registers are only supported on targets which supply
4126 an XML description. */
4127 return builtin_type (gdbarch)->builtin_int0;
4129 return builtin_type (gdbarch)->builtin_uint32;
4132 /* Map a DWARF register REGNUM onto the appropriate GDB register
4136 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4138 /* Core integer regs. */
4139 if (reg >= 0 && reg <= 15)
4142 /* Legacy FPA encoding. These were once used in a way which
4143 overlapped with VFP register numbering, so their use is
4144 discouraged, but GDB doesn't support the ARM toolchain
4145 which used them for VFP. */
4146 if (reg >= 16 && reg <= 23)
4147 return ARM_F0_REGNUM + reg - 16;
4149 /* New assignments for the FPA registers. */
4150 if (reg >= 96 && reg <= 103)
4151 return ARM_F0_REGNUM + reg - 96;
4153 /* WMMX register assignments. */
4154 if (reg >= 104 && reg <= 111)
4155 return ARM_WCGR0_REGNUM + reg - 104;
4157 if (reg >= 112 && reg <= 127)
4158 return ARM_WR0_REGNUM + reg - 112;
4160 if (reg >= 192 && reg <= 199)
4161 return ARM_WC0_REGNUM + reg - 192;
4163 /* VFP v2 registers. A double precision value is actually
4164 in d1 rather than s2, but the ABI only defines numbering
4165 for the single precision registers. This will "just work"
4166 in GDB for little endian targets (we'll read eight bytes,
4167 starting in s0 and then progressing to s1), but will be
4168 reversed on big endian targets with VFP. This won't
4169 be a problem for the new Neon quad registers; you're supposed
4170 to use DW_OP_piece for those. */
4171 if (reg >= 64 && reg <= 95)
4175 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4176 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4180 /* VFP v3 / Neon registers. This range is also used for VFP v2
4181 registers, except that it now describes d0 instead of s0. */
4182 if (reg >= 256 && reg <= 287)
4186 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4187 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4194 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4196 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4199 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4201 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4202 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4204 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4205 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4207 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4208 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4210 if (reg < NUM_GREGS)
4211 return SIM_ARM_R0_REGNUM + reg;
4214 if (reg < NUM_FREGS)
4215 return SIM_ARM_FP0_REGNUM + reg;
4218 if (reg < NUM_SREGS)
4219 return SIM_ARM_FPS_REGNUM + reg;
4222 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4225 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4226 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4227 It is thought that this is is the floating-point register format on
4228 little-endian systems. */
4231 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4232 void *dbl, int endianess)
4236 if (endianess == BFD_ENDIAN_BIG)
4237 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4239 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4241 floatformat_from_doublest (fmt, &d, dbl);
4245 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4250 floatformat_to_doublest (fmt, ptr, &d);
4251 if (endianess == BFD_ENDIAN_BIG)
4252 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4254 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4259 condition_true (unsigned long cond, unsigned long status_reg)
4261 if (cond == INST_AL || cond == INST_NV)
4267 return ((status_reg & FLAG_Z) != 0);
4269 return ((status_reg & FLAG_Z) == 0);
4271 return ((status_reg & FLAG_C) != 0);
4273 return ((status_reg & FLAG_C) == 0);
4275 return ((status_reg & FLAG_N) != 0);
4277 return ((status_reg & FLAG_N) == 0);
4279 return ((status_reg & FLAG_V) != 0);
4281 return ((status_reg & FLAG_V) == 0);
4283 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4285 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4287 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4289 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4291 return (((status_reg & FLAG_Z) == 0)
4292 && (((status_reg & FLAG_N) == 0)
4293 == ((status_reg & FLAG_V) == 0)));
4295 return (((status_reg & FLAG_Z) != 0)
4296 || (((status_reg & FLAG_N) == 0)
4297 != ((status_reg & FLAG_V) == 0)));
4302 static unsigned long
4303 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4304 unsigned long pc_val, unsigned long status_reg)
4306 unsigned long res, shift;
4307 int rm = bits (inst, 0, 3);
4308 unsigned long shifttype = bits (inst, 5, 6);
4312 int rs = bits (inst, 8, 11);
4313 shift = (rs == 15 ? pc_val + 8
4314 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4317 shift = bits (inst, 7, 11);
4319 res = (rm == ARM_PC_REGNUM
4320 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4321 : get_frame_register_unsigned (frame, rm));
4326 res = shift >= 32 ? 0 : res << shift;
4330 res = shift >= 32 ? 0 : res >> shift;
4336 res = ((res & 0x80000000L)
4337 ? ~((~res) >> shift) : res >> shift);
4340 case 3: /* ROR/RRX */
4343 res = (res >> 1) | (carry ? 0x80000000L : 0);
4345 res = (res >> shift) | (res << (32 - shift));
4349 return res & 0xffffffff;
4352 /* Return number of 1-bits in VAL. */
4355 bitcount (unsigned long val)
4358 for (nbits = 0; val != 0; nbits++)
4359 val &= val - 1; /* Delete rightmost 1-bit in val. */
4363 /* Return the size in bytes of the complete Thumb instruction whose
4364 first halfword is INST1. */
4367 thumb_insn_size (unsigned short inst1)
4369 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4376 thumb_advance_itstate (unsigned int itstate)
4378 /* Preserve IT[7:5], the first three bits of the condition. Shift
4379 the upcoming condition flags left by one bit. */
4380 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4382 /* If we have finished the IT block, clear the state. */
4383 if ((itstate & 0x0f) == 0)
4389 /* Find the next PC after the current instruction executes. In some
4390 cases we can not statically determine the answer (see the IT state
4391 handling in this function); in that case, a breakpoint may be
4392 inserted in addition to the returned PC, which will be used to set
4393 another breakpoint by our caller. */
4396 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4398 struct gdbarch *gdbarch = get_frame_arch (frame);
4399 struct address_space *aspace = get_frame_address_space (frame);
4400 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4401 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4402 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4403 unsigned short inst1;
4404 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4405 unsigned long offset;
4406 ULONGEST status, itstate;
4408 nextpc = MAKE_THUMB_ADDR (nextpc);
4409 pc_val = MAKE_THUMB_ADDR (pc_val);
4411 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4413 /* Thumb-2 conditional execution support. There are eight bits in
4414 the CPSR which describe conditional execution state. Once
4415 reconstructed (they're in a funny order), the low five bits
4416 describe the low bit of the condition for each instruction and
4417 how many instructions remain. The high three bits describe the
4418 base condition. One of the low four bits will be set if an IT
4419 block is active. These bits read as zero on earlier
4421 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4422 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4424 /* If-Then handling. On GNU/Linux, where this routine is used, we
4425 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4426 can disable execution of the undefined instruction. So we might
4427 miss the breakpoint if we set it on a skipped conditional
4428 instruction. Because conditional instructions can change the
4429 flags, affecting the execution of further instructions, we may
4430 need to set two breakpoints. */
4432 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4434 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4436 /* An IT instruction. Because this instruction does not
4437 modify the flags, we can accurately predict the next
4438 executed instruction. */
4439 itstate = inst1 & 0x00ff;
4440 pc += thumb_insn_size (inst1);
4442 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4444 inst1 = read_memory_unsigned_integer (pc, 2,
4445 byte_order_for_code);
4446 pc += thumb_insn_size (inst1);
4447 itstate = thumb_advance_itstate (itstate);
4450 return MAKE_THUMB_ADDR (pc);
4452 else if (itstate != 0)
4454 /* We are in a conditional block. Check the condition. */
4455 if (! condition_true (itstate >> 4, status))
4457 /* Advance to the next executed instruction. */
4458 pc += thumb_insn_size (inst1);
4459 itstate = thumb_advance_itstate (itstate);
4461 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4463 inst1 = read_memory_unsigned_integer (pc, 2,
4464 byte_order_for_code);
4465 pc += thumb_insn_size (inst1);
4466 itstate = thumb_advance_itstate (itstate);
4469 return MAKE_THUMB_ADDR (pc);
4471 else if ((itstate & 0x0f) == 0x08)
4473 /* This is the last instruction of the conditional
4474 block, and it is executed. We can handle it normally
4475 because the following instruction is not conditional,
4476 and we must handle it normally because it is
4477 permitted to branch. Fall through. */
4483 /* There are conditional instructions after this one.
4484 If this instruction modifies the flags, then we can
4485 not predict what the next executed instruction will
4486 be. Fortunately, this instruction is architecturally
4487 forbidden to branch; we know it will fall through.
4488 Start by skipping past it. */
4489 pc += thumb_insn_size (inst1);
4490 itstate = thumb_advance_itstate (itstate);
4492 /* Set a breakpoint on the following instruction. */
4493 gdb_assert ((itstate & 0x0f) != 0);
4494 arm_insert_single_step_breakpoint (gdbarch, aspace,
4495 MAKE_THUMB_ADDR (pc));
4496 cond_negated = (itstate >> 4) & 1;
4498 /* Skip all following instructions with the same
4499 condition. If there is a later instruction in the IT
4500 block with the opposite condition, set the other
4501 breakpoint there. If not, then set a breakpoint on
4502 the instruction after the IT block. */
4505 inst1 = read_memory_unsigned_integer (pc, 2,
4506 byte_order_for_code);
4507 pc += thumb_insn_size (inst1);
4508 itstate = thumb_advance_itstate (itstate);
4510 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4512 return MAKE_THUMB_ADDR (pc);
4516 else if (itstate & 0x0f)
4518 /* We are in a conditional block. Check the condition. */
4519 int cond = itstate >> 4;
4521 if (! condition_true (cond, status))
4522 /* Advance to the next instruction. All the 32-bit
4523 instructions share a common prefix. */
4524 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4526 /* Otherwise, handle the instruction normally. */
4529 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4533 /* Fetch the saved PC from the stack. It's stored above
4534 all of the other registers. */
4535 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4536 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4537 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4539 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4541 unsigned long cond = bits (inst1, 8, 11);
4542 if (cond == 0x0f) /* 0x0f = SWI */
4544 struct gdbarch_tdep *tdep;
4545 tdep = gdbarch_tdep (gdbarch);
4547 if (tdep->syscall_next_pc != NULL)
4548 nextpc = tdep->syscall_next_pc (frame);
4551 else if (cond != 0x0f && condition_true (cond, status))
4552 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4554 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4556 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4558 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4560 unsigned short inst2;
4561 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4563 /* Default to the next instruction. */
4565 nextpc = MAKE_THUMB_ADDR (nextpc);
4567 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4569 /* Branches and miscellaneous control instructions. */
4571 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4574 int j1, j2, imm1, imm2;
4576 imm1 = sbits (inst1, 0, 10);
4577 imm2 = bits (inst2, 0, 10);
4578 j1 = bit (inst2, 13);
4579 j2 = bit (inst2, 11);
4581 offset = ((imm1 << 12) + (imm2 << 1));
4582 offset ^= ((!j2) << 22) | ((!j1) << 23);
4584 nextpc = pc_val + offset;
4585 /* For BLX make sure to clear the low bits. */
4586 if (bit (inst2, 12) == 0)
4587 nextpc = nextpc & 0xfffffffc;
4589 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4591 /* SUBS PC, LR, #imm8. */
4592 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4593 nextpc -= inst2 & 0x00ff;
4595 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4597 /* Conditional branch. */
4598 if (condition_true (bits (inst1, 6, 9), status))
4600 int sign, j1, j2, imm1, imm2;
4602 sign = sbits (inst1, 10, 10);
4603 imm1 = bits (inst1, 0, 5);
4604 imm2 = bits (inst2, 0, 10);
4605 j1 = bit (inst2, 13);
4606 j2 = bit (inst2, 11);
4608 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4609 offset += (imm1 << 12) + (imm2 << 1);
4611 nextpc = pc_val + offset;
4615 else if ((inst1 & 0xfe50) == 0xe810)
4617 /* Load multiple or RFE. */
4618 int rn, offset, load_pc = 1;
4620 rn = bits (inst1, 0, 3);
4621 if (bit (inst1, 7) && !bit (inst1, 8))
4624 if (!bit (inst2, 15))
4626 offset = bitcount (inst2) * 4 - 4;
4628 else if (!bit (inst1, 7) && bit (inst1, 8))
4631 if (!bit (inst2, 15))
4635 else if (bit (inst1, 7) && bit (inst1, 8))
4640 else if (!bit (inst1, 7) && !bit (inst1, 8))
4650 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4651 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4654 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4656 /* MOV PC or MOVS PC. */
4657 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4658 nextpc = MAKE_THUMB_ADDR (nextpc);
4660 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4664 int rn, load_pc = 1;
4666 rn = bits (inst1, 0, 3);
4667 base = get_frame_register_unsigned (frame, rn);
4668 if (rn == ARM_PC_REGNUM)
4670 base = (base + 4) & ~(CORE_ADDR) 0x3;
4672 base += bits (inst2, 0, 11);
4674 base -= bits (inst2, 0, 11);
4676 else if (bit (inst1, 7))
4677 base += bits (inst2, 0, 11);
4678 else if (bit (inst2, 11))
4680 if (bit (inst2, 10))
4683 base += bits (inst2, 0, 7);
4685 base -= bits (inst2, 0, 7);
4688 else if ((inst2 & 0x0fc0) == 0x0000)
4690 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4691 base += get_frame_register_unsigned (frame, rm) << shift;
4698 nextpc = get_frame_memory_unsigned (frame, base, 4);
4700 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4703 CORE_ADDR tbl_reg, table, offset, length;
4705 tbl_reg = bits (inst1, 0, 3);
4706 if (tbl_reg == 0x0f)
4707 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4709 table = get_frame_register_unsigned (frame, tbl_reg);
4711 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4712 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4713 nextpc = pc_val + length;
4715 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4718 CORE_ADDR tbl_reg, table, offset, length;
4720 tbl_reg = bits (inst1, 0, 3);
4721 if (tbl_reg == 0x0f)
4722 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4724 table = get_frame_register_unsigned (frame, tbl_reg);
4726 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4727 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4728 nextpc = pc_val + length;
4731 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4733 if (bits (inst1, 3, 6) == 0x0f)
4734 nextpc = UNMAKE_THUMB_ADDR (pc_val);
4736 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4738 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4740 if (bits (inst1, 3, 6) == 0x0f)
4743 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4745 nextpc = MAKE_THUMB_ADDR (nextpc);
4747 else if ((inst1 & 0xf500) == 0xb100)
4750 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4751 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4753 if (bit (inst1, 11) && reg != 0)
4754 nextpc = pc_val + imm;
4755 else if (!bit (inst1, 11) && reg == 0)
4756 nextpc = pc_val + imm;
4761 /* Get the raw next address. PC is the current program counter, in
4762 FRAME, which is assumed to be executing in ARM mode.
4764 The value returned has the execution state of the next instruction
4765 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4766 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4770 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4772 struct gdbarch *gdbarch = get_frame_arch (frame);
4773 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4774 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4775 unsigned long pc_val;
4776 unsigned long this_instr;
4777 unsigned long status;
4780 pc_val = (unsigned long) pc;
4781 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4783 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4784 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4786 if (bits (this_instr, 28, 31) == INST_NV)
4787 switch (bits (this_instr, 24, 27))
4792 /* Branch with Link and change to Thumb. */
4793 nextpc = BranchDest (pc, this_instr);
4794 nextpc |= bit (this_instr, 24) << 1;
4795 nextpc = MAKE_THUMB_ADDR (nextpc);
4801 /* Coprocessor register transfer. */
4802 if (bits (this_instr, 12, 15) == 15)
4803 error (_("Invalid update to pc in instruction"));
4806 else if (condition_true (bits (this_instr, 28, 31), status))
4808 switch (bits (this_instr, 24, 27))
4811 case 0x1: /* data processing */
4815 unsigned long operand1, operand2, result = 0;
4819 if (bits (this_instr, 12, 15) != 15)
4822 if (bits (this_instr, 22, 25) == 0
4823 && bits (this_instr, 4, 7) == 9) /* multiply */
4824 error (_("Invalid update to pc in instruction"));
4826 /* BX <reg>, BLX <reg> */
4827 if (bits (this_instr, 4, 27) == 0x12fff1
4828 || bits (this_instr, 4, 27) == 0x12fff3)
4830 rn = bits (this_instr, 0, 3);
4831 nextpc = ((rn == ARM_PC_REGNUM)
4833 : get_frame_register_unsigned (frame, rn));
4838 /* Multiply into PC. */
4839 c = (status & FLAG_C) ? 1 : 0;
4840 rn = bits (this_instr, 16, 19);
4841 operand1 = ((rn == ARM_PC_REGNUM)
4843 : get_frame_register_unsigned (frame, rn));
4845 if (bit (this_instr, 25))
4847 unsigned long immval = bits (this_instr, 0, 7);
4848 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4849 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4852 else /* operand 2 is a shifted register. */
4853 operand2 = shifted_reg_val (frame, this_instr, c,
4856 switch (bits (this_instr, 21, 24))
4859 result = operand1 & operand2;
4863 result = operand1 ^ operand2;
4867 result = operand1 - operand2;
4871 result = operand2 - operand1;
4875 result = operand1 + operand2;
4879 result = operand1 + operand2 + c;
4883 result = operand1 - operand2 + c;
4887 result = operand2 - operand1 + c;
4893 case 0xb: /* tst, teq, cmp, cmn */
4894 result = (unsigned long) nextpc;
4898 result = operand1 | operand2;
4902 /* Always step into a function. */
4907 result = operand1 & ~operand2;
4915 /* In 26-bit APCS the bottom two bits of the result are
4916 ignored, and we always end up in ARM state. */
4918 nextpc = arm_addr_bits_remove (gdbarch, result);
4926 case 0x5: /* data transfer */
4929 if (bit (this_instr, 20))
4932 if (bits (this_instr, 12, 15) == 15)
4938 if (bit (this_instr, 22))
4939 error (_("Invalid update to pc in instruction"));
4941 /* byte write to PC */
4942 rn = bits (this_instr, 16, 19);
4943 base = ((rn == ARM_PC_REGNUM)
4945 : get_frame_register_unsigned (frame, rn));
4947 if (bit (this_instr, 24))
4950 int c = (status & FLAG_C) ? 1 : 0;
4951 unsigned long offset =
4952 (bit (this_instr, 25)
4953 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4954 : bits (this_instr, 0, 11));
4956 if (bit (this_instr, 23))
4962 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4969 case 0x9: /* block transfer */
4970 if (bit (this_instr, 20))
4973 if (bit (this_instr, 15))
4977 unsigned long rn_val
4978 = get_frame_register_unsigned (frame,
4979 bits (this_instr, 16, 19));
4981 if (bit (this_instr, 23))
4984 unsigned long reglist = bits (this_instr, 0, 14);
4985 offset = bitcount (reglist) * 4;
4986 if (bit (this_instr, 24)) /* pre */
4989 else if (bit (this_instr, 24))
4993 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
5000 case 0xb: /* branch & link */
5001 case 0xa: /* branch */
5003 nextpc = BranchDest (pc, this_instr);
5009 case 0xe: /* coproc ops */
5013 struct gdbarch_tdep *tdep;
5014 tdep = gdbarch_tdep (gdbarch);
5016 if (tdep->syscall_next_pc != NULL)
5017 nextpc = tdep->syscall_next_pc (frame);
5023 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
5031 /* Determine next PC after current instruction executes. Will call either
5032 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5033 loop is detected. */
5036 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
5040 if (arm_frame_is_thumb (frame))
5041 nextpc = thumb_get_next_pc_raw (frame, pc);
5043 nextpc = arm_get_next_pc_raw (frame, pc);
5048 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5049 of the appropriate mode (as encoded in the PC value), even if this
5050 differs from what would be expected according to the symbol tables. */
5053 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
5054 struct address_space *aspace,
5057 struct cleanup *old_chain
5058 = make_cleanup_restore_integer (&arm_override_mode);
5060 arm_override_mode = IS_THUMB_ADDR (pc);
5061 pc = gdbarch_addr_bits_remove (gdbarch, pc);
5063 insert_single_step_breakpoint (gdbarch, aspace, pc);
5065 do_cleanups (old_chain);
5068 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5069 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5070 is found, attempt to step through it. A breakpoint is placed at the end of
5074 thumb_deal_with_atomic_sequence_raw (struct frame_info *frame)
5076 struct gdbarch *gdbarch = get_frame_arch (frame);
5077 struct address_space *aspace = get_frame_address_space (frame);
5078 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5079 CORE_ADDR pc = get_frame_pc (frame);
5080 CORE_ADDR breaks[2] = {-1, -1};
5082 unsigned short insn1, insn2;
5085 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5086 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5087 ULONGEST status, itstate;
5089 /* We currently do not support atomic sequences within an IT block. */
5090 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
5091 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5095 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5096 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5098 if (thumb_insn_size (insn1) != 4)
5101 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5103 if (!((insn1 & 0xfff0) == 0xe850
5104 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5107 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5109 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5111 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5114 if (thumb_insn_size (insn1) != 4)
5116 /* Assume that there is at most one conditional branch in the
5117 atomic sequence. If a conditional branch is found, put a
5118 breakpoint in its destination address. */
5119 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
5121 if (last_breakpoint > 0)
5122 return 0; /* More than one conditional branch found,
5123 fallback to the standard code. */
5125 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
5129 /* We do not support atomic sequences that use any *other*
5130 instructions but conditional branches to change the PC.
5131 Fall back to standard code to avoid losing control of
5133 else if (thumb_instruction_changes_pc (insn1))
5138 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5141 /* Assume that there is at most one conditional branch in the
5142 atomic sequence. If a conditional branch is found, put a
5143 breakpoint in its destination address. */
5144 if ((insn1 & 0xf800) == 0xf000
5145 && (insn2 & 0xd000) == 0x8000
5146 && (insn1 & 0x0380) != 0x0380)
5148 int sign, j1, j2, imm1, imm2;
5149 unsigned int offset;
5151 sign = sbits (insn1, 10, 10);
5152 imm1 = bits (insn1, 0, 5);
5153 imm2 = bits (insn2, 0, 10);
5154 j1 = bit (insn2, 13);
5155 j2 = bit (insn2, 11);
5157 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5158 offset += (imm1 << 12) + (imm2 << 1);
5160 if (last_breakpoint > 0)
5161 return 0; /* More than one conditional branch found,
5162 fallback to the standard code. */
5164 breaks[1] = loc + offset;
5168 /* We do not support atomic sequences that use any *other*
5169 instructions but conditional branches to change the PC.
5170 Fall back to standard code to avoid losing control of
5172 else if (thumb2_instruction_changes_pc (insn1, insn2))
5175 /* If we find a strex{,b,h,d}, we're done. */
5176 if ((insn1 & 0xfff0) == 0xe840
5177 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5182 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5183 if (insn_count == atomic_sequence_length)
5186 /* Insert a breakpoint right after the end of the atomic sequence. */
5189 /* Check for duplicated breakpoints. Check also for a breakpoint
5190 placed (branch instruction's destination) anywhere in sequence. */
5192 && (breaks[1] == breaks[0]
5193 || (breaks[1] >= pc && breaks[1] < loc)))
5194 last_breakpoint = 0;
5196 /* Effectively inserts the breakpoints. */
5197 for (index = 0; index <= last_breakpoint; index++)
5198 arm_insert_single_step_breakpoint (gdbarch, aspace,
5199 MAKE_THUMB_ADDR (breaks[index]));
5205 arm_deal_with_atomic_sequence_raw (struct frame_info *frame)
5207 struct gdbarch *gdbarch = get_frame_arch (frame);
5208 struct address_space *aspace = get_frame_address_space (frame);
5209 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5210 CORE_ADDR pc = get_frame_pc (frame);
5211 CORE_ADDR breaks[2] = {-1, -1};
5216 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5217 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5219 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5220 Note that we do not currently support conditionally executed atomic
5222 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5224 if ((insn & 0xff9000f0) != 0xe1900090)
5227 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5229 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5231 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5234 /* Assume that there is at most one conditional branch in the atomic
5235 sequence. If a conditional branch is found, put a breakpoint in
5236 its destination address. */
5237 if (bits (insn, 24, 27) == 0xa)
5239 if (last_breakpoint > 0)
5240 return 0; /* More than one conditional branch found, fallback
5241 to the standard single-step code. */
5243 breaks[1] = BranchDest (loc - 4, insn);
5247 /* We do not support atomic sequences that use any *other* instructions
5248 but conditional branches to change the PC. Fall back to standard
5249 code to avoid losing control of execution. */
5250 else if (arm_instruction_changes_pc (insn))
5253 /* If we find a strex{,b,h,d}, we're done. */
5254 if ((insn & 0xff9000f0) == 0xe1800090)
5258 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5259 if (insn_count == atomic_sequence_length)
5262 /* Insert a breakpoint right after the end of the atomic sequence. */
5265 /* Check for duplicated breakpoints. Check also for a breakpoint
5266 placed (branch instruction's destination) anywhere in sequence. */
5268 && (breaks[1] == breaks[0]
5269 || (breaks[1] >= pc && breaks[1] < loc)))
5270 last_breakpoint = 0;
5272 /* Effectively inserts the breakpoints. */
5273 for (index = 0; index <= last_breakpoint; index++)
5274 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5280 arm_deal_with_atomic_sequence (struct frame_info *frame)
5282 if (arm_frame_is_thumb (frame))
5283 return thumb_deal_with_atomic_sequence_raw (frame);
5285 return arm_deal_with_atomic_sequence_raw (frame);
5288 /* single_step() is called just before we want to resume the inferior,
5289 if we want to single-step it but there is no hardware or kernel
5290 single-step support. We find the target of the coming instruction
5291 and breakpoint it. */
5294 arm_software_single_step (struct frame_info *frame)
5296 struct gdbarch *gdbarch = get_frame_arch (frame);
5297 struct address_space *aspace = get_frame_address_space (frame);
5300 if (arm_deal_with_atomic_sequence (frame))
5303 next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
5304 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5309 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5310 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5311 NULL if an error occurs. BUF is freed. */
5314 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5315 int old_len, int new_len)
5318 int bytes_to_read = new_len - old_len;
5320 new_buf = xmalloc (new_len);
5321 memcpy (new_buf + bytes_to_read, buf, old_len);
5323 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5331 /* An IT block is at most the 2-byte IT instruction followed by
5332 four 4-byte instructions. The furthest back we must search to
5333 find an IT block that affects the current instruction is thus
5334 2 + 3 * 4 == 14 bytes. */
5335 #define MAX_IT_BLOCK_PREFIX 14
5337 /* Use a quick scan if there are more than this many bytes of
5339 #define IT_SCAN_THRESHOLD 32
5341 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5342 A breakpoint in an IT block may not be hit, depending on the
5345 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5349 CORE_ADDR boundary, func_start;
5351 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5352 int i, any, last_it, last_it_count;
5354 /* If we are using BKPT breakpoints, none of this is necessary. */
5355 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5358 /* ARM mode does not have this problem. */
5359 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5362 /* We are setting a breakpoint in Thumb code that could potentially
5363 contain an IT block. The first step is to find how much Thumb
5364 code there is; we do not need to read outside of known Thumb
5366 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5368 /* Thumb-2 code must have mapping symbols to have a chance. */
5371 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5373 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5374 && func_start > boundary)
5375 boundary = func_start;
5377 /* Search for a candidate IT instruction. We have to do some fancy
5378 footwork to distinguish a real IT instruction from the second
5379 half of a 32-bit instruction, but there is no need for that if
5380 there's no candidate. */
5381 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5383 /* No room for an IT instruction. */
5386 buf = xmalloc (buf_len);
5387 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5390 for (i = 0; i < buf_len; i += 2)
5392 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5393 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5405 /* OK, the code bytes before this instruction contain at least one
5406 halfword which resembles an IT instruction. We know that it's
5407 Thumb code, but there are still two possibilities. Either the
5408 halfword really is an IT instruction, or it is the second half of
5409 a 32-bit Thumb instruction. The only way we can tell is to
5410 scan forwards from a known instruction boundary. */
5411 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5415 /* There's a lot of code before this instruction. Start with an
5416 optimistic search; it's easy to recognize halfwords that can
5417 not be the start of a 32-bit instruction, and use that to
5418 lock on to the instruction boundaries. */
5419 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5422 buf_len = IT_SCAN_THRESHOLD;
5425 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5427 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5428 if (thumb_insn_size (inst1) == 2)
5435 /* At this point, if DEFINITE, BUF[I] is the first place we
5436 are sure that we know the instruction boundaries, and it is far
5437 enough from BPADDR that we could not miss an IT instruction
5438 affecting BPADDR. If ! DEFINITE, give up - start from a
5442 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5446 buf_len = bpaddr - boundary;
5452 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5455 buf_len = bpaddr - boundary;
5459 /* Scan forwards. Find the last IT instruction before BPADDR. */
5464 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5466 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5471 else if (inst1 & 0x0002)
5473 else if (inst1 & 0x0004)
5478 i += thumb_insn_size (inst1);
5484 /* There wasn't really an IT instruction after all. */
5487 if (last_it_count < 1)
5488 /* It was too far away. */
5491 /* This really is a trouble spot. Move the breakpoint to the IT
5493 return bpaddr - buf_len + last_it;
5496 /* ARM displaced stepping support.
5498 Generally ARM displaced stepping works as follows:
5500 1. When an instruction is to be single-stepped, it is first decoded by
5501 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5502 Depending on the type of instruction, it is then copied to a scratch
5503 location, possibly in a modified form. The copy_* set of functions
5504 performs such modification, as necessary. A breakpoint is placed after
5505 the modified instruction in the scratch space to return control to GDB.
5506 Note in particular that instructions which modify the PC will no longer
5507 do so after modification.
5509 2. The instruction is single-stepped, by setting the PC to the scratch
5510 location address, and resuming. Control returns to GDB when the
5513 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5514 function used for the current instruction. This function's job is to
5515 put the CPU/memory state back to what it would have been if the
5516 instruction had been executed unmodified in its original location. */
5518 /* NOP instruction (mov r0, r0). */
5519 #define ARM_NOP 0xe1a00000
5520 #define THUMB_NOP 0x4600
5522 /* Helper for register reads for displaced stepping. In particular, this
5523 returns the PC as it would be seen by the instruction at its original
5527 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5531 CORE_ADDR from = dsc->insn_addr;
5533 if (regno == ARM_PC_REGNUM)
5535 /* Compute pipeline offset:
5536 - When executing an ARM instruction, PC reads as the address of the
5537 current instruction plus 8.
5538 - When executing a Thumb instruction, PC reads as the address of the
5539 current instruction plus 4. */
5546 if (debug_displaced)
5547 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5548 (unsigned long) from);
5549 return (ULONGEST) from;
5553 regcache_cooked_read_unsigned (regs, regno, &ret);
5554 if (debug_displaced)
5555 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5556 regno, (unsigned long) ret);
5562 displaced_in_arm_mode (struct regcache *regs)
5565 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5567 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5569 return (ps & t_bit) == 0;
5572 /* Write to the PC as from a branch instruction. */
5575 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5579 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5580 architecture versions < 6. */
5581 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5582 val & ~(ULONGEST) 0x3);
5584 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5585 val & ~(ULONGEST) 0x1);
5588 /* Write to the PC as from a branch-exchange instruction. */
5591 bx_write_pc (struct regcache *regs, ULONGEST val)
5594 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5596 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5600 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5601 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5603 else if ((val & 2) == 0)
5605 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5606 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5610 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5611 mode, align dest to 4 bytes). */
5612 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5613 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5614 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5618 /* Write to the PC as if from a load instruction. */
5621 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5624 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5625 bx_write_pc (regs, val);
5627 branch_write_pc (regs, dsc, val);
5630 /* Write to the PC as if from an ALU instruction. */
5633 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5636 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5637 bx_write_pc (regs, val);
5639 branch_write_pc (regs, dsc, val);
5642 /* Helper for writing to registers for displaced stepping. Writing to the PC
5643 has a varying effects depending on the instruction which does the write:
5644 this is controlled by the WRITE_PC argument. */
5647 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5648 int regno, ULONGEST val, enum pc_write_style write_pc)
5650 if (regno == ARM_PC_REGNUM)
5652 if (debug_displaced)
5653 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5654 (unsigned long) val);
5657 case BRANCH_WRITE_PC:
5658 branch_write_pc (regs, dsc, val);
5662 bx_write_pc (regs, val);
5666 load_write_pc (regs, dsc, val);
5670 alu_write_pc (regs, dsc, val);
5673 case CANNOT_WRITE_PC:
5674 warning (_("Instruction wrote to PC in an unexpected way when "
5675 "single-stepping"));
5679 internal_error (__FILE__, __LINE__,
5680 _("Invalid argument to displaced_write_reg"));
5683 dsc->wrote_to_pc = 1;
5687 if (debug_displaced)
5688 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5689 regno, (unsigned long) val);
5690 regcache_cooked_write_unsigned (regs, regno, val);
5694 /* This function is used to concisely determine if an instruction INSN
5695 references PC. Register fields of interest in INSN should have the
5696 corresponding fields of BITMASK set to 0b1111. The function
5697 returns return 1 if any of these fields in INSN reference the PC
5698 (also 0b1111, r15), else it returns 0. */
5701 insn_references_pc (uint32_t insn, uint32_t bitmask)
5703 uint32_t lowbit = 1;
5705 while (bitmask != 0)
5709 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5715 mask = lowbit * 0xf;
5717 if ((insn & mask) == mask)
5726 /* The simplest copy function. Many instructions have the same effect no
5727 matter what address they are executed at: in those cases, use this. */
5730 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5731 const char *iname, struct displaced_step_closure *dsc)
5733 if (debug_displaced)
5734 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5735 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5738 dsc->modinsn[0] = insn;
5744 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5745 uint16_t insn2, const char *iname,
5746 struct displaced_step_closure *dsc)
5748 if (debug_displaced)
5749 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5750 "opcode/class '%s' unmodified\n", insn1, insn2,
5753 dsc->modinsn[0] = insn1;
5754 dsc->modinsn[1] = insn2;
5760 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5763 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5765 struct displaced_step_closure *dsc)
5767 if (debug_displaced)
5768 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5769 "opcode/class '%s' unmodified\n", insn,
5772 dsc->modinsn[0] = insn;
5777 /* Preload instructions with immediate offset. */
5780 cleanup_preload (struct gdbarch *gdbarch,
5781 struct regcache *regs, struct displaced_step_closure *dsc)
5783 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5784 if (!dsc->u.preload.immed)
5785 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5789 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5790 struct displaced_step_closure *dsc, unsigned int rn)
5793 /* Preload instructions:
5795 {pli/pld} [rn, #+/-imm]
5797 {pli/pld} [r0, #+/-imm]. */
5799 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5800 rn_val = displaced_read_reg (regs, dsc, rn);
5801 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5802 dsc->u.preload.immed = 1;
5804 dsc->cleanup = &cleanup_preload;
5808 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5809 struct displaced_step_closure *dsc)
5811 unsigned int rn = bits (insn, 16, 19);
5813 if (!insn_references_pc (insn, 0x000f0000ul))
5814 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5816 if (debug_displaced)
5817 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5818 (unsigned long) insn);
5820 dsc->modinsn[0] = insn & 0xfff0ffff;
5822 install_preload (gdbarch, regs, dsc, rn);
5828 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5829 struct regcache *regs, struct displaced_step_closure *dsc)
5831 unsigned int rn = bits (insn1, 0, 3);
5832 unsigned int u_bit = bit (insn1, 7);
5833 int imm12 = bits (insn2, 0, 11);
5836 if (rn != ARM_PC_REGNUM)
5837 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5839 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5840 PLD (literal) Encoding T1. */
5841 if (debug_displaced)
5842 fprintf_unfiltered (gdb_stdlog,
5843 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5844 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5850 /* Rewrite instruction {pli/pld} PC imm12 into:
5851 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5855 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5857 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5858 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5860 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5862 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5863 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5864 dsc->u.preload.immed = 0;
5866 /* {pli/pld} [r0, r1] */
5867 dsc->modinsn[0] = insn1 & 0xfff0;
5868 dsc->modinsn[1] = 0xf001;
5871 dsc->cleanup = &cleanup_preload;
5875 /* Preload instructions with register offset. */
5878 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5879 struct displaced_step_closure *dsc, unsigned int rn,
5882 ULONGEST rn_val, rm_val;
5884 /* Preload register-offset instructions:
5886 {pli/pld} [rn, rm {, shift}]
5888 {pli/pld} [r0, r1 {, shift}]. */
5890 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5891 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5892 rn_val = displaced_read_reg (regs, dsc, rn);
5893 rm_val = displaced_read_reg (regs, dsc, rm);
5894 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5895 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5896 dsc->u.preload.immed = 0;
5898 dsc->cleanup = &cleanup_preload;
5902 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5903 struct regcache *regs,
5904 struct displaced_step_closure *dsc)
5906 unsigned int rn = bits (insn, 16, 19);
5907 unsigned int rm = bits (insn, 0, 3);
5910 if (!insn_references_pc (insn, 0x000f000ful))
5911 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5913 if (debug_displaced)
5914 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5915 (unsigned long) insn);
5917 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5919 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5923 /* Copy/cleanup coprocessor load and store instructions. */
5926 cleanup_copro_load_store (struct gdbarch *gdbarch,
5927 struct regcache *regs,
5928 struct displaced_step_closure *dsc)
5930 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5932 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5934 if (dsc->u.ldst.writeback)
5935 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5939 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5940 struct displaced_step_closure *dsc,
5941 int writeback, unsigned int rn)
5945 /* Coprocessor load/store instructions:
5947 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5949 {stc/stc2} [r0, #+/-imm].
5951 ldc/ldc2 are handled identically. */
5953 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5954 rn_val = displaced_read_reg (regs, dsc, rn);
5955 /* PC should be 4-byte aligned. */
5956 rn_val = rn_val & 0xfffffffc;
5957 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5959 dsc->u.ldst.writeback = writeback;
5960 dsc->u.ldst.rn = rn;
5962 dsc->cleanup = &cleanup_copro_load_store;
5966 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5967 struct regcache *regs,
5968 struct displaced_step_closure *dsc)
5970 unsigned int rn = bits (insn, 16, 19);
5972 if (!insn_references_pc (insn, 0x000f0000ul))
5973 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5975 if (debug_displaced)
5976 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5977 "load/store insn %.8lx\n", (unsigned long) insn);
5979 dsc->modinsn[0] = insn & 0xfff0ffff;
5981 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5987 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5988 uint16_t insn2, struct regcache *regs,
5989 struct displaced_step_closure *dsc)
5991 unsigned int rn = bits (insn1, 0, 3);
5993 if (rn != ARM_PC_REGNUM)
5994 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5995 "copro load/store", dsc);
5997 if (debug_displaced)
5998 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5999 "load/store insn %.4x%.4x\n", insn1, insn2);
6001 dsc->modinsn[0] = insn1 & 0xfff0;
6002 dsc->modinsn[1] = insn2;
6005 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6006 doesn't support writeback, so pass 0. */
6007 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
6012 /* Clean up branch instructions (actually perform the branch, by setting
6016 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
6017 struct displaced_step_closure *dsc)
6019 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6020 int branch_taken = condition_true (dsc->u.branch.cond, status);
6021 enum pc_write_style write_pc = dsc->u.branch.exchange
6022 ? BX_WRITE_PC : BRANCH_WRITE_PC;
6027 if (dsc->u.branch.link)
6029 /* The value of LR should be the next insn of current one. In order
6030 not to confuse logic hanlding later insn `bx lr', if current insn mode
6031 is Thumb, the bit 0 of LR value should be set to 1. */
6032 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
6035 next_insn_addr |= 0x1;
6037 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
6041 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
6044 /* Copy B/BL/BLX instructions with immediate destinations. */
6047 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
6048 struct displaced_step_closure *dsc,
6049 unsigned int cond, int exchange, int link, long offset)
6051 /* Implement "BL<cond> <label>" as:
6053 Preparation: cond <- instruction condition
6054 Insn: mov r0, r0 (nop)
6055 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6057 B<cond> similar, but don't set r14 in cleanup. */
6059 dsc->u.branch.cond = cond;
6060 dsc->u.branch.link = link;
6061 dsc->u.branch.exchange = exchange;
6063 dsc->u.branch.dest = dsc->insn_addr;
6064 if (link && exchange)
6065 /* For BLX, offset is computed from the Align (PC, 4). */
6066 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6069 dsc->u.branch.dest += 4 + offset;
6071 dsc->u.branch.dest += 8 + offset;
6073 dsc->cleanup = &cleanup_branch;
6076 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
6077 struct regcache *regs, struct displaced_step_closure *dsc)
6079 unsigned int cond = bits (insn, 28, 31);
6080 int exchange = (cond == 0xf);
6081 int link = exchange || bit (insn, 24);
6084 if (debug_displaced)
6085 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
6086 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
6087 (unsigned long) insn);
6089 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6090 then arrange the switch into Thumb mode. */
6091 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
6093 offset = bits (insn, 0, 23) << 2;
6095 if (bit (offset, 25))
6096 offset = offset | ~0x3ffffff;
6098 dsc->modinsn[0] = ARM_NOP;
6100 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6105 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
6106 uint16_t insn2, struct regcache *regs,
6107 struct displaced_step_closure *dsc)
6109 int link = bit (insn2, 14);
6110 int exchange = link && !bit (insn2, 12);
6113 int j1 = bit (insn2, 13);
6114 int j2 = bit (insn2, 11);
6115 int s = sbits (insn1, 10, 10);
6116 int i1 = !(j1 ^ bit (insn1, 10));
6117 int i2 = !(j2 ^ bit (insn1, 10));
6119 if (!link && !exchange) /* B */
6121 offset = (bits (insn2, 0, 10) << 1);
6122 if (bit (insn2, 12)) /* Encoding T4 */
6124 offset |= (bits (insn1, 0, 9) << 12)
6130 else /* Encoding T3 */
6132 offset |= (bits (insn1, 0, 5) << 12)
6136 cond = bits (insn1, 6, 9);
6141 offset = (bits (insn1, 0, 9) << 12);
6142 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6143 offset |= exchange ?
6144 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
6147 if (debug_displaced)
6148 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
6149 "%.4x %.4x with offset %.8lx\n",
6150 link ? (exchange) ? "blx" : "bl" : "b",
6151 insn1, insn2, offset);
6153 dsc->modinsn[0] = THUMB_NOP;
6155 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6159 /* Copy B Thumb instructions. */
6161 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
6162 struct displaced_step_closure *dsc)
6164 unsigned int cond = 0;
6166 unsigned short bit_12_15 = bits (insn, 12, 15);
6167 CORE_ADDR from = dsc->insn_addr;
6169 if (bit_12_15 == 0xd)
6171 /* offset = SignExtend (imm8:0, 32) */
6172 offset = sbits ((insn << 1), 0, 8);
6173 cond = bits (insn, 8, 11);
6175 else if (bit_12_15 == 0xe) /* Encoding T2 */
6177 offset = sbits ((insn << 1), 0, 11);
6181 if (debug_displaced)
6182 fprintf_unfiltered (gdb_stdlog,
6183 "displaced: copying b immediate insn %.4x "
6184 "with offset %d\n", insn, offset);
6186 dsc->u.branch.cond = cond;
6187 dsc->u.branch.link = 0;
6188 dsc->u.branch.exchange = 0;
6189 dsc->u.branch.dest = from + 4 + offset;
6191 dsc->modinsn[0] = THUMB_NOP;
6193 dsc->cleanup = &cleanup_branch;
6198 /* Copy BX/BLX with register-specified destinations. */
6201 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6202 struct displaced_step_closure *dsc, int link,
6203 unsigned int cond, unsigned int rm)
6205 /* Implement {BX,BLX}<cond> <reg>" as:
6207 Preparation: cond <- instruction condition
6208 Insn: mov r0, r0 (nop)
6209 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6211 Don't set r14 in cleanup for BX. */
6213 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6215 dsc->u.branch.cond = cond;
6216 dsc->u.branch.link = link;
6218 dsc->u.branch.exchange = 1;
6220 dsc->cleanup = &cleanup_branch;
6224 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6225 struct regcache *regs, struct displaced_step_closure *dsc)
6227 unsigned int cond = bits (insn, 28, 31);
6230 int link = bit (insn, 5);
6231 unsigned int rm = bits (insn, 0, 3);
6233 if (debug_displaced)
6234 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6235 (unsigned long) insn);
6237 dsc->modinsn[0] = ARM_NOP;
6239 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6244 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6245 struct regcache *regs,
6246 struct displaced_step_closure *dsc)
6248 int link = bit (insn, 7);
6249 unsigned int rm = bits (insn, 3, 6);
6251 if (debug_displaced)
6252 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6253 (unsigned short) insn);
6255 dsc->modinsn[0] = THUMB_NOP;
6257 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6263 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6266 cleanup_alu_imm (struct gdbarch *gdbarch,
6267 struct regcache *regs, struct displaced_step_closure *dsc)
6269 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6270 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6271 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6272 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6276 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6277 struct displaced_step_closure *dsc)
6279 unsigned int rn = bits (insn, 16, 19);
6280 unsigned int rd = bits (insn, 12, 15);
6281 unsigned int op = bits (insn, 21, 24);
6282 int is_mov = (op == 0xd);
6283 ULONGEST rd_val, rn_val;
6285 if (!insn_references_pc (insn, 0x000ff000ul))
6286 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6288 if (debug_displaced)
6289 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6290 "%.8lx\n", is_mov ? "move" : "ALU",
6291 (unsigned long) insn);
6293 /* Instruction is of form:
6295 <op><cond> rd, [rn,] #imm
6299 Preparation: tmp1, tmp2 <- r0, r1;
6301 Insn: <op><cond> r0, r1, #imm
6302 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6305 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6306 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6307 rn_val = displaced_read_reg (regs, dsc, rn);
6308 rd_val = displaced_read_reg (regs, dsc, rd);
6309 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6310 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6314 dsc->modinsn[0] = insn & 0xfff00fff;
6316 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6318 dsc->cleanup = &cleanup_alu_imm;
6324 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6325 uint16_t insn2, struct regcache *regs,
6326 struct displaced_step_closure *dsc)
6328 unsigned int op = bits (insn1, 5, 8);
6329 unsigned int rn, rm, rd;
6330 ULONGEST rd_val, rn_val;
6332 rn = bits (insn1, 0, 3); /* Rn */
6333 rm = bits (insn2, 0, 3); /* Rm */
6334 rd = bits (insn2, 8, 11); /* Rd */
6336 /* This routine is only called for instruction MOV. */
6337 gdb_assert (op == 0x2 && rn == 0xf);
6339 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6340 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6342 if (debug_displaced)
6343 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6344 "ALU", insn1, insn2);
6346 /* Instruction is of form:
6348 <op><cond> rd, [rn,] #imm
6352 Preparation: tmp1, tmp2 <- r0, r1;
6354 Insn: <op><cond> r0, r1, #imm
6355 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6358 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6359 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6360 rn_val = displaced_read_reg (regs, dsc, rn);
6361 rd_val = displaced_read_reg (regs, dsc, rd);
6362 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6363 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6366 dsc->modinsn[0] = insn1;
6367 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6370 dsc->cleanup = &cleanup_alu_imm;
6375 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6378 cleanup_alu_reg (struct gdbarch *gdbarch,
6379 struct regcache *regs, struct displaced_step_closure *dsc)
6384 rd_val = displaced_read_reg (regs, dsc, 0);
6386 for (i = 0; i < 3; i++)
6387 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6389 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6393 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6394 struct displaced_step_closure *dsc,
6395 unsigned int rd, unsigned int rn, unsigned int rm)
6397 ULONGEST rd_val, rn_val, rm_val;
6399 /* Instruction is of form:
6401 <op><cond> rd, [rn,] rm [, <shift>]
6405 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6406 r0, r1, r2 <- rd, rn, rm
6407 Insn: <op><cond> r0, r1, r2 [, <shift>]
6408 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6411 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6412 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6413 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6414 rd_val = displaced_read_reg (regs, dsc, rd);
6415 rn_val = displaced_read_reg (regs, dsc, rn);
6416 rm_val = displaced_read_reg (regs, dsc, rm);
6417 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6418 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6419 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6422 dsc->cleanup = &cleanup_alu_reg;
6426 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6427 struct displaced_step_closure *dsc)
6429 unsigned int op = bits (insn, 21, 24);
6430 int is_mov = (op == 0xd);
6432 if (!insn_references_pc (insn, 0x000ff00ful))
6433 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6435 if (debug_displaced)
6436 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6437 is_mov ? "move" : "ALU", (unsigned long) insn);
6440 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6442 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6444 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6450 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6451 struct regcache *regs,
6452 struct displaced_step_closure *dsc)
6454 unsigned rn, rm, rd;
6456 rd = bits (insn, 3, 6);
6457 rn = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6460 if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6461 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6463 if (debug_displaced)
6464 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n",
6465 "ALU", (unsigned short) insn);
6467 dsc->modinsn[0] = ((insn & 0xff00) | 0x08);
6469 install_alu_reg (gdbarch, regs, dsc, rd, rn, rm);
6474 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6477 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6478 struct regcache *regs,
6479 struct displaced_step_closure *dsc)
6481 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6484 for (i = 0; i < 4; i++)
6485 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6487 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6491 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6492 struct displaced_step_closure *dsc,
6493 unsigned int rd, unsigned int rn, unsigned int rm,
6497 ULONGEST rd_val, rn_val, rm_val, rs_val;
6499 /* Instruction is of form:
6501 <op><cond> rd, [rn,] rm, <shift> rs
6505 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6506 r0, r1, r2, r3 <- rd, rn, rm, rs
6507 Insn: <op><cond> r0, r1, r2, <shift> r3
6509 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6513 for (i = 0; i < 4; i++)
6514 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6516 rd_val = displaced_read_reg (regs, dsc, rd);
6517 rn_val = displaced_read_reg (regs, dsc, rn);
6518 rm_val = displaced_read_reg (regs, dsc, rm);
6519 rs_val = displaced_read_reg (regs, dsc, rs);
6520 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6521 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6522 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6523 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6525 dsc->cleanup = &cleanup_alu_shifted_reg;
6529 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6530 struct regcache *regs,
6531 struct displaced_step_closure *dsc)
6533 unsigned int op = bits (insn, 21, 24);
6534 int is_mov = (op == 0xd);
6535 unsigned int rd, rn, rm, rs;
6537 if (!insn_references_pc (insn, 0x000fff0ful))
6538 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6540 if (debug_displaced)
6541 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6542 "%.8lx\n", is_mov ? "move" : "ALU",
6543 (unsigned long) insn);
6545 rn = bits (insn, 16, 19);
6546 rm = bits (insn, 0, 3);
6547 rs = bits (insn, 8, 11);
6548 rd = bits (insn, 12, 15);
6551 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6553 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6555 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6560 /* Clean up load instructions. */
6563 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6564 struct displaced_step_closure *dsc)
6566 ULONGEST rt_val, rt_val2 = 0, rn_val;
6568 rt_val = displaced_read_reg (regs, dsc, 0);
6569 if (dsc->u.ldst.xfersize == 8)
6570 rt_val2 = displaced_read_reg (regs, dsc, 1);
6571 rn_val = displaced_read_reg (regs, dsc, 2);
6573 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6574 if (dsc->u.ldst.xfersize > 4)
6575 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6576 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6577 if (!dsc->u.ldst.immed)
6578 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6580 /* Handle register writeback. */
6581 if (dsc->u.ldst.writeback)
6582 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6583 /* Put result in right place. */
6584 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6585 if (dsc->u.ldst.xfersize == 8)
6586 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6589 /* Clean up store instructions. */
6592 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6593 struct displaced_step_closure *dsc)
6595 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6597 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6598 if (dsc->u.ldst.xfersize > 4)
6599 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6600 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6601 if (!dsc->u.ldst.immed)
6602 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6603 if (!dsc->u.ldst.restore_r4)
6604 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6607 if (dsc->u.ldst.writeback)
6608 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6611 /* Copy "extra" load/store instructions. These are halfword/doubleword
6612 transfers, which have a different encoding to byte/word transfers. */
6615 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6616 struct regcache *regs, struct displaced_step_closure *dsc)
6618 unsigned int op1 = bits (insn, 20, 24);
6619 unsigned int op2 = bits (insn, 5, 6);
6620 unsigned int rt = bits (insn, 12, 15);
6621 unsigned int rn = bits (insn, 16, 19);
6622 unsigned int rm = bits (insn, 0, 3);
6623 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6624 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6625 int immed = (op1 & 0x4) != 0;
6627 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6629 if (!insn_references_pc (insn, 0x000ff00ful))
6630 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6632 if (debug_displaced)
6633 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6634 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6635 (unsigned long) insn);
6637 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6640 internal_error (__FILE__, __LINE__,
6641 _("copy_extra_ld_st: instruction decode error"));
6643 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6644 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6645 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6647 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6649 rt_val = displaced_read_reg (regs, dsc, rt);
6650 if (bytesize[opcode] == 8)
6651 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6652 rn_val = displaced_read_reg (regs, dsc, rn);
6654 rm_val = displaced_read_reg (regs, dsc, rm);
6656 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6657 if (bytesize[opcode] == 8)
6658 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6659 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6661 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6664 dsc->u.ldst.xfersize = bytesize[opcode];
6665 dsc->u.ldst.rn = rn;
6666 dsc->u.ldst.immed = immed;
6667 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6668 dsc->u.ldst.restore_r4 = 0;
6671 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6673 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6674 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6676 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6678 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6679 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6681 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6686 /* Copy byte/half word/word loads and stores. */
6689 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6690 struct displaced_step_closure *dsc, int load,
6691 int immed, int writeback, int size, int usermode,
6692 int rt, int rm, int rn)
6694 ULONGEST rt_val, rn_val, rm_val = 0;
6696 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6697 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6699 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6701 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6703 rt_val = displaced_read_reg (regs, dsc, rt);
6704 rn_val = displaced_read_reg (regs, dsc, rn);
6706 rm_val = displaced_read_reg (regs, dsc, rm);
6708 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6709 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6711 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6713 dsc->u.ldst.xfersize = size;
6714 dsc->u.ldst.rn = rn;
6715 dsc->u.ldst.immed = immed;
6716 dsc->u.ldst.writeback = writeback;
6718 /* To write PC we can do:
6720 Before this sequence of instructions:
6721 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6722 r2 is the Rn value got from dispalced_read_reg.
6724 Insn1: push {pc} Write address of STR instruction + offset on stack
6725 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6726 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6727 = addr(Insn1) + offset - addr(Insn3) - 8
6729 Insn4: add r4, r4, #8 r4 = offset - 8
6730 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6732 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6734 Otherwise we don't know what value to write for PC, since the offset is
6735 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6736 of this can be found in Section "Saving from r15" in
6737 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6739 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6744 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6745 uint16_t insn2, struct regcache *regs,
6746 struct displaced_step_closure *dsc, int size)
6748 unsigned int u_bit = bit (insn1, 7);
6749 unsigned int rt = bits (insn2, 12, 15);
6750 int imm12 = bits (insn2, 0, 11);
6753 if (debug_displaced)
6754 fprintf_unfiltered (gdb_stdlog,
6755 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6756 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6762 /* Rewrite instruction LDR Rt imm12 into:
6764 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6768 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6771 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6772 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6773 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6775 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6777 pc_val = pc_val & 0xfffffffc;
6779 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6780 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6784 dsc->u.ldst.xfersize = size;
6785 dsc->u.ldst.immed = 0;
6786 dsc->u.ldst.writeback = 0;
6787 dsc->u.ldst.restore_r4 = 0;
6789 /* LDR R0, R2, R3 */
6790 dsc->modinsn[0] = 0xf852;
6791 dsc->modinsn[1] = 0x3;
6794 dsc->cleanup = &cleanup_load;
6800 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6801 uint16_t insn2, struct regcache *regs,
6802 struct displaced_step_closure *dsc,
6803 int writeback, int immed)
6805 unsigned int rt = bits (insn2, 12, 15);
6806 unsigned int rn = bits (insn1, 0, 3);
6807 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6808 /* In LDR (register), there is also a register Rm, which is not allowed to
6809 be PC, so we don't have to check it. */
6811 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6812 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6815 if (debug_displaced)
6816 fprintf_unfiltered (gdb_stdlog,
6817 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6818 rt, rn, insn1, insn2);
6820 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6823 dsc->u.ldst.restore_r4 = 0;
6826 /* ldr[b]<cond> rt, [rn, #imm], etc.
6828 ldr[b]<cond> r0, [r2, #imm]. */
6830 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6831 dsc->modinsn[1] = insn2 & 0x0fff;
6834 /* ldr[b]<cond> rt, [rn, rm], etc.
6836 ldr[b]<cond> r0, [r2, r3]. */
6838 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6839 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6849 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6850 struct regcache *regs,
6851 struct displaced_step_closure *dsc,
6852 int load, int size, int usermode)
6854 int immed = !bit (insn, 25);
6855 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6856 unsigned int rt = bits (insn, 12, 15);
6857 unsigned int rn = bits (insn, 16, 19);
6858 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6860 if (!insn_references_pc (insn, 0x000ff00ful))
6861 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6863 if (debug_displaced)
6864 fprintf_unfiltered (gdb_stdlog,
6865 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6866 load ? (size == 1 ? "ldrb" : "ldr")
6867 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6869 (unsigned long) insn);
6871 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6872 usermode, rt, rm, rn);
6874 if (load || rt != ARM_PC_REGNUM)
6876 dsc->u.ldst.restore_r4 = 0;
6879 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6881 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6882 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6884 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6886 {ldr,str}[b]<cond> r0, [r2, r3]. */
6887 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6891 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6892 dsc->u.ldst.restore_r4 = 1;
6893 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6894 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6895 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6896 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6897 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6901 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6903 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6908 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6913 /* Cleanup LDM instructions with fully-populated register list. This is an
6914 unfortunate corner case: it's impossible to implement correctly by modifying
6915 the instruction. The issue is as follows: we have an instruction,
6919 which we must rewrite to avoid loading PC. A possible solution would be to
6920 do the load in two halves, something like (with suitable cleanup
6924 ldm[id][ab] r8!, {r0-r7}
6926 ldm[id][ab] r8, {r7-r14}
6929 but at present there's no suitable place for <temp>, since the scratch space
6930 is overwritten before the cleanup routine is called. For now, we simply
6931 emulate the instruction. */
6934 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6935 struct displaced_step_closure *dsc)
6937 int inc = dsc->u.block.increment;
6938 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6939 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6940 uint32_t regmask = dsc->u.block.regmask;
6941 int regno = inc ? 0 : 15;
6942 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6943 int exception_return = dsc->u.block.load && dsc->u.block.user
6944 && (regmask & 0x8000) != 0;
6945 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6946 int do_transfer = condition_true (dsc->u.block.cond, status);
6947 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6952 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6953 sensible we can do here. Complain loudly. */
6954 if (exception_return)
6955 error (_("Cannot single-step exception return"));
6957 /* We don't handle any stores here for now. */
6958 gdb_assert (dsc->u.block.load != 0);
6960 if (debug_displaced)
6961 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6962 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6963 dsc->u.block.increment ? "inc" : "dec",
6964 dsc->u.block.before ? "before" : "after");
6971 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6974 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6977 xfer_addr += bump_before;
6979 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6980 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6982 xfer_addr += bump_after;
6984 regmask &= ~(1 << regno);
6987 if (dsc->u.block.writeback)
6988 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6992 /* Clean up an STM which included the PC in the register list. */
6995 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6996 struct displaced_step_closure *dsc)
6998 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6999 int store_executed = condition_true (dsc->u.block.cond, status);
7000 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
7001 CORE_ADDR stm_insn_addr;
7004 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7006 /* If condition code fails, there's nothing else to do. */
7007 if (!store_executed)
7010 if (dsc->u.block.increment)
7012 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
7014 if (dsc->u.block.before)
7019 pc_stored_at = dsc->u.block.xfer_addr;
7021 if (dsc->u.block.before)
7025 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
7026 stm_insn_addr = dsc->scratch_base;
7027 offset = pc_val - stm_insn_addr;
7029 if (debug_displaced)
7030 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
7031 "STM instruction\n", offset);
7033 /* Rewrite the stored PC to the proper value for the non-displaced original
7035 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
7036 dsc->insn_addr + offset);
7039 /* Clean up an LDM which includes the PC in the register list. We clumped all
7040 the registers in the transferred list into a contiguous range r0...rX (to
7041 avoid loading PC directly and losing control of the debugged program), so we
7042 must undo that here. */
7045 cleanup_block_load_pc (struct gdbarch *gdbarch,
7046 struct regcache *regs,
7047 struct displaced_step_closure *dsc)
7049 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
7050 int load_executed = condition_true (dsc->u.block.cond, status);
7051 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
7052 unsigned int regs_loaded = bitcount (mask);
7053 unsigned int num_to_shuffle = regs_loaded, clobbered;
7055 /* The method employed here will fail if the register list is fully populated
7056 (we need to avoid loading PC directly). */
7057 gdb_assert (num_to_shuffle < 16);
7062 clobbered = (1 << num_to_shuffle) - 1;
7064 while (num_to_shuffle > 0)
7066 if ((mask & (1 << write_reg)) != 0)
7068 unsigned int read_reg = num_to_shuffle - 1;
7070 if (read_reg != write_reg)
7072 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
7073 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7074 if (debug_displaced)
7075 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
7076 "loaded register r%d to r%d\n"), read_reg,
7079 else if (debug_displaced)
7080 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
7081 "r%d already in the right place\n"),
7084 clobbered &= ~(1 << write_reg);
7092 /* Restore any registers we scribbled over. */
7093 for (write_reg = 0; clobbered != 0; write_reg++)
7095 if ((clobbered & (1 << write_reg)) != 0)
7097 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7099 if (debug_displaced)
7100 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
7101 "clobbered register r%d\n"), write_reg);
7102 clobbered &= ~(1 << write_reg);
7106 /* Perform register writeback manually. */
7107 if (dsc->u.block.writeback)
7109 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7111 if (dsc->u.block.increment)
7112 new_rn_val += regs_loaded * 4;
7114 new_rn_val -= regs_loaded * 4;
7116 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7121 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7122 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7125 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
7126 struct regcache *regs,
7127 struct displaced_step_closure *dsc)
7129 int load = bit (insn, 20);
7130 int user = bit (insn, 22);
7131 int increment = bit (insn, 23);
7132 int before = bit (insn, 24);
7133 int writeback = bit (insn, 21);
7134 int rn = bits (insn, 16, 19);
7136 /* Block transfers which don't mention PC can be run directly
7138 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
7139 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7141 if (rn == ARM_PC_REGNUM)
7143 warning (_("displaced: Unpredictable LDM or STM with "
7144 "base register r15"));
7145 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7148 if (debug_displaced)
7149 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7150 "%.8lx\n", (unsigned long) insn);
7152 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7153 dsc->u.block.rn = rn;
7155 dsc->u.block.load = load;
7156 dsc->u.block.user = user;
7157 dsc->u.block.increment = increment;
7158 dsc->u.block.before = before;
7159 dsc->u.block.writeback = writeback;
7160 dsc->u.block.cond = bits (insn, 28, 31);
7162 dsc->u.block.regmask = insn & 0xffff;
7166 if ((insn & 0xffff) == 0xffff)
7168 /* LDM with a fully-populated register list. This case is
7169 particularly tricky. Implement for now by fully emulating the
7170 instruction (which might not behave perfectly in all cases, but
7171 these instructions should be rare enough for that not to matter
7173 dsc->modinsn[0] = ARM_NOP;
7175 dsc->cleanup = &cleanup_block_load_all;
7179 /* LDM of a list of registers which includes PC. Implement by
7180 rewriting the list of registers to be transferred into a
7181 contiguous chunk r0...rX before doing the transfer, then shuffling
7182 registers into the correct places in the cleanup routine. */
7183 unsigned int regmask = insn & 0xffff;
7184 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7185 unsigned int to = 0, from = 0, i, new_rn;
7187 for (i = 0; i < num_in_list; i++)
7188 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7190 /* Writeback makes things complicated. We need to avoid clobbering
7191 the base register with one of the registers in our modified
7192 register list, but just using a different register can't work in
7195 ldm r14!, {r0-r13,pc}
7197 which would need to be rewritten as:
7201 but that can't work, because there's no free register for N.
7203 Solve this by turning off the writeback bit, and emulating
7204 writeback manually in the cleanup routine. */
7209 new_regmask = (1 << num_in_list) - 1;
7211 if (debug_displaced)
7212 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7213 "{..., pc}: original reg list %.4x, modified "
7214 "list %.4x\n"), rn, writeback ? "!" : "",
7215 (int) insn & 0xffff, new_regmask);
7217 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7219 dsc->cleanup = &cleanup_block_load_pc;
7224 /* STM of a list of registers which includes PC. Run the instruction
7225 as-is, but out of line: this will store the wrong value for the PC,
7226 so we must manually fix up the memory in the cleanup routine.
7227 Doing things this way has the advantage that we can auto-detect
7228 the offset of the PC write (which is architecture-dependent) in
7229 the cleanup routine. */
7230 dsc->modinsn[0] = insn;
7232 dsc->cleanup = &cleanup_block_store_pc;
7239 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7240 struct regcache *regs,
7241 struct displaced_step_closure *dsc)
7243 int rn = bits (insn1, 0, 3);
7244 int load = bit (insn1, 4);
7245 int writeback = bit (insn1, 5);
7247 /* Block transfers which don't mention PC can be run directly
7249 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7250 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7252 if (rn == ARM_PC_REGNUM)
7254 warning (_("displaced: Unpredictable LDM or STM with "
7255 "base register r15"));
7256 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7257 "unpredictable ldm/stm", dsc);
7260 if (debug_displaced)
7261 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7262 "%.4x%.4x\n", insn1, insn2);
7264 /* Clear bit 13, since it should be always zero. */
7265 dsc->u.block.regmask = (insn2 & 0xdfff);
7266 dsc->u.block.rn = rn;
7268 dsc->u.block.load = load;
7269 dsc->u.block.user = 0;
7270 dsc->u.block.increment = bit (insn1, 7);
7271 dsc->u.block.before = bit (insn1, 8);
7272 dsc->u.block.writeback = writeback;
7273 dsc->u.block.cond = INST_AL;
7274 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7278 if (dsc->u.block.regmask == 0xffff)
7280 /* This branch is impossible to happen. */
7285 unsigned int regmask = dsc->u.block.regmask;
7286 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7287 unsigned int to = 0, from = 0, i, new_rn;
7289 for (i = 0; i < num_in_list; i++)
7290 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7295 new_regmask = (1 << num_in_list) - 1;
7297 if (debug_displaced)
7298 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7299 "{..., pc}: original reg list %.4x, modified "
7300 "list %.4x\n"), rn, writeback ? "!" : "",
7301 (int) dsc->u.block.regmask, new_regmask);
7303 dsc->modinsn[0] = insn1;
7304 dsc->modinsn[1] = (new_regmask & 0xffff);
7307 dsc->cleanup = &cleanup_block_load_pc;
7312 dsc->modinsn[0] = insn1;
7313 dsc->modinsn[1] = insn2;
7315 dsc->cleanup = &cleanup_block_store_pc;
7320 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7321 for Linux, where some SVC instructions must be treated specially. */
7324 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7325 struct displaced_step_closure *dsc)
7327 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7329 if (debug_displaced)
7330 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7331 "%.8lx\n", (unsigned long) resume_addr);
7333 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7337 /* Common copy routine for svc instruciton. */
7340 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7341 struct displaced_step_closure *dsc)
7343 /* Preparation: none.
7344 Insn: unmodified svc.
7345 Cleanup: pc <- insn_addr + insn_size. */
7347 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7349 dsc->wrote_to_pc = 1;
7351 /* Allow OS-specific code to override SVC handling. */
7352 if (dsc->u.svc.copy_svc_os)
7353 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7356 dsc->cleanup = &cleanup_svc;
7362 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7363 struct regcache *regs, struct displaced_step_closure *dsc)
7366 if (debug_displaced)
7367 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7368 (unsigned long) insn);
7370 dsc->modinsn[0] = insn;
7372 return install_svc (gdbarch, regs, dsc);
7376 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7377 struct regcache *regs, struct displaced_step_closure *dsc)
7380 if (debug_displaced)
7381 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7384 dsc->modinsn[0] = insn;
7386 return install_svc (gdbarch, regs, dsc);
7389 /* Copy undefined instructions. */
7392 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7393 struct displaced_step_closure *dsc)
7395 if (debug_displaced)
7396 fprintf_unfiltered (gdb_stdlog,
7397 "displaced: copying undefined insn %.8lx\n",
7398 (unsigned long) insn);
7400 dsc->modinsn[0] = insn;
7406 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7407 struct displaced_step_closure *dsc)
7410 if (debug_displaced)
7411 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7412 "%.4x %.4x\n", (unsigned short) insn1,
7413 (unsigned short) insn2);
7415 dsc->modinsn[0] = insn1;
7416 dsc->modinsn[1] = insn2;
7422 /* Copy unpredictable instructions. */
7425 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7426 struct displaced_step_closure *dsc)
7428 if (debug_displaced)
7429 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7430 "%.8lx\n", (unsigned long) insn);
7432 dsc->modinsn[0] = insn;
7437 /* The decode_* functions are instruction decoding helpers. They mostly follow
7438 the presentation in the ARM ARM. */
7441 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7442 struct regcache *regs,
7443 struct displaced_step_closure *dsc)
7445 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7446 unsigned int rn = bits (insn, 16, 19);
7448 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7449 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7450 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7451 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7452 else if ((op1 & 0x60) == 0x20)
7453 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7454 else if ((op1 & 0x71) == 0x40)
7455 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7457 else if ((op1 & 0x77) == 0x41)
7458 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7459 else if ((op1 & 0x77) == 0x45)
7460 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7461 else if ((op1 & 0x77) == 0x51)
7464 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7466 return arm_copy_unpred (gdbarch, insn, dsc);
7468 else if ((op1 & 0x77) == 0x55)
7469 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7470 else if (op1 == 0x57)
7473 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7474 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7475 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7476 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7477 default: return arm_copy_unpred (gdbarch, insn, dsc);
7479 else if ((op1 & 0x63) == 0x43)
7480 return arm_copy_unpred (gdbarch, insn, dsc);
7481 else if ((op2 & 0x1) == 0x0)
7482 switch (op1 & ~0x80)
7485 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7487 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7488 case 0x71: case 0x75:
7490 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7491 case 0x63: case 0x67: case 0x73: case 0x77:
7492 return arm_copy_unpred (gdbarch, insn, dsc);
7494 return arm_copy_undef (gdbarch, insn, dsc);
7497 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7501 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7502 struct regcache *regs,
7503 struct displaced_step_closure *dsc)
7505 if (bit (insn, 27) == 0)
7506 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7507 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7508 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7511 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7514 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7516 case 0x4: case 0x5: case 0x6: case 0x7:
7517 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7520 switch ((insn & 0xe00000) >> 21)
7522 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7524 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7527 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7530 return arm_copy_undef (gdbarch, insn, dsc);
7535 int rn_f = (bits (insn, 16, 19) == 0xf);
7536 switch ((insn & 0xe00000) >> 21)
7539 /* ldc/ldc2 imm (undefined for rn == pc). */
7540 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7541 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7544 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7546 case 0x4: case 0x5: case 0x6: case 0x7:
7547 /* ldc/ldc2 lit (undefined for rn != pc). */
7548 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7549 : arm_copy_undef (gdbarch, insn, dsc);
7552 return arm_copy_undef (gdbarch, insn, dsc);
7557 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7560 if (bits (insn, 16, 19) == 0xf)
7562 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7564 return arm_copy_undef (gdbarch, insn, dsc);
7568 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7570 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7574 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7576 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7579 return arm_copy_undef (gdbarch, insn, dsc);
7583 /* Decode miscellaneous instructions in dp/misc encoding space. */
7586 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7587 struct regcache *regs,
7588 struct displaced_step_closure *dsc)
7590 unsigned int op2 = bits (insn, 4, 6);
7591 unsigned int op = bits (insn, 21, 22);
7592 unsigned int op1 = bits (insn, 16, 19);
7597 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7600 if (op == 0x1) /* bx. */
7601 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7603 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7605 return arm_copy_undef (gdbarch, insn, dsc);
7609 /* Not really supported. */
7610 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7612 return arm_copy_undef (gdbarch, insn, dsc);
7616 return arm_copy_bx_blx_reg (gdbarch, insn,
7617 regs, dsc); /* blx register. */
7619 return arm_copy_undef (gdbarch, insn, dsc);
7622 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7626 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7628 /* Not really supported. */
7629 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7632 return arm_copy_undef (gdbarch, insn, dsc);
7637 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7638 struct regcache *regs,
7639 struct displaced_step_closure *dsc)
7642 switch (bits (insn, 20, 24))
7645 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7648 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7650 case 0x12: case 0x16:
7651 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7654 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7658 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7660 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7661 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7662 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7663 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7664 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7665 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7666 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7667 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7668 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7669 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7670 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7671 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7672 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7673 /* 2nd arg means "unpriveleged". */
7674 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7678 /* Should be unreachable. */
7683 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7684 struct regcache *regs,
7685 struct displaced_step_closure *dsc)
7687 int a = bit (insn, 25), b = bit (insn, 4);
7688 uint32_t op1 = bits (insn, 20, 24);
7689 int rn_f = bits (insn, 16, 19) == 0xf;
7691 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7692 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7693 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7694 else if ((!a && (op1 & 0x17) == 0x02)
7695 || (a && (op1 & 0x17) == 0x02 && !b))
7696 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7697 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7698 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7699 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7700 else if ((!a && (op1 & 0x17) == 0x03)
7701 || (a && (op1 & 0x17) == 0x03 && !b))
7702 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7703 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7704 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7705 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7706 else if ((!a && (op1 & 0x17) == 0x06)
7707 || (a && (op1 & 0x17) == 0x06 && !b))
7708 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7709 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7710 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7711 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7712 else if ((!a && (op1 & 0x17) == 0x07)
7713 || (a && (op1 & 0x17) == 0x07 && !b))
7714 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7716 /* Should be unreachable. */
7721 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7722 struct displaced_step_closure *dsc)
7724 switch (bits (insn, 20, 24))
7726 case 0x00: case 0x01: case 0x02: case 0x03:
7727 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7729 case 0x04: case 0x05: case 0x06: case 0x07:
7730 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7732 case 0x08: case 0x09: case 0x0a: case 0x0b:
7733 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7734 return arm_copy_unmodified (gdbarch, insn,
7735 "decode/pack/unpack/saturate/reverse", dsc);
7738 if (bits (insn, 5, 7) == 0) /* op2. */
7740 if (bits (insn, 12, 15) == 0xf)
7741 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7743 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7746 return arm_copy_undef (gdbarch, insn, dsc);
7748 case 0x1a: case 0x1b:
7749 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7750 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7752 return arm_copy_undef (gdbarch, insn, dsc);
7754 case 0x1c: case 0x1d:
7755 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7757 if (bits (insn, 0, 3) == 0xf)
7758 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7760 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7763 return arm_copy_undef (gdbarch, insn, dsc);
7765 case 0x1e: case 0x1f:
7766 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7767 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7769 return arm_copy_undef (gdbarch, insn, dsc);
7772 /* Should be unreachable. */
7777 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7778 struct regcache *regs,
7779 struct displaced_step_closure *dsc)
7782 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7784 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7788 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7789 struct regcache *regs,
7790 struct displaced_step_closure *dsc)
7792 unsigned int opcode = bits (insn, 20, 24);
7796 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7797 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7799 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7800 case 0x12: case 0x16:
7801 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7803 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7804 case 0x13: case 0x17:
7805 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7807 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7808 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7809 /* Note: no writeback for these instructions. Bit 25 will always be
7810 zero though (via caller), so the following works OK. */
7811 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7814 /* Should be unreachable. */
7818 /* Decode shifted register instructions. */
7821 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7822 uint16_t insn2, struct regcache *regs,
7823 struct displaced_step_closure *dsc)
7825 /* PC is only allowed to be used in instruction MOV. */
7827 unsigned int op = bits (insn1, 5, 8);
7828 unsigned int rn = bits (insn1, 0, 3);
7830 if (op == 0x2 && rn == 0xf) /* MOV */
7831 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7833 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7834 "dp (shift reg)", dsc);
7838 /* Decode extension register load/store. Exactly the same as
7839 arm_decode_ext_reg_ld_st. */
7842 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7843 uint16_t insn2, struct regcache *regs,
7844 struct displaced_step_closure *dsc)
7846 unsigned int opcode = bits (insn1, 4, 8);
7850 case 0x04: case 0x05:
7851 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7852 "vfp/neon vmov", dsc);
7854 case 0x08: case 0x0c: /* 01x00 */
7855 case 0x0a: case 0x0e: /* 01x10 */
7856 case 0x12: case 0x16: /* 10x10 */
7857 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7858 "vfp/neon vstm/vpush", dsc);
7860 case 0x09: case 0x0d: /* 01x01 */
7861 case 0x0b: case 0x0f: /* 01x11 */
7862 case 0x13: case 0x17: /* 10x11 */
7863 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7864 "vfp/neon vldm/vpop", dsc);
7866 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7867 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7869 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7870 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7873 /* Should be unreachable. */
7878 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7879 struct regcache *regs, struct displaced_step_closure *dsc)
7881 unsigned int op1 = bits (insn, 20, 25);
7882 int op = bit (insn, 4);
7883 unsigned int coproc = bits (insn, 8, 11);
7884 unsigned int rn = bits (insn, 16, 19);
7886 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7887 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7888 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7889 && (coproc & 0xe) != 0xa)
7891 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7892 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7893 && (coproc & 0xe) != 0xa)
7894 /* ldc/ldc2 imm/lit. */
7895 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7896 else if ((op1 & 0x3e) == 0x00)
7897 return arm_copy_undef (gdbarch, insn, dsc);
7898 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7899 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7900 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7901 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7902 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7903 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7904 else if ((op1 & 0x30) == 0x20 && !op)
7906 if ((coproc & 0xe) == 0xa)
7907 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7909 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7911 else if ((op1 & 0x30) == 0x20 && op)
7912 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7913 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7914 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7915 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7916 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7917 else if ((op1 & 0x30) == 0x30)
7918 return arm_copy_svc (gdbarch, insn, regs, dsc);
7920 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7924 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7925 uint16_t insn2, struct regcache *regs,
7926 struct displaced_step_closure *dsc)
7928 unsigned int coproc = bits (insn2, 8, 11);
7929 unsigned int op1 = bits (insn1, 4, 9);
7930 unsigned int bit_5_8 = bits (insn1, 5, 8);
7931 unsigned int bit_9 = bit (insn1, 9);
7932 unsigned int bit_4 = bit (insn1, 4);
7933 unsigned int rn = bits (insn1, 0, 3);
7938 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7939 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7941 else if (bit_5_8 == 0) /* UNDEFINED. */
7942 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7945 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7946 if ((coproc & 0xe) == 0xa)
7947 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7949 else /* coproc is not 101x. */
7951 if (bit_4 == 0) /* STC/STC2. */
7952 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7954 else /* LDC/LDC2 {literal, immeidate}. */
7955 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7961 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7967 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7968 struct displaced_step_closure *dsc, int rd)
7974 Preparation: Rd <- PC
7980 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7981 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7985 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7986 struct displaced_step_closure *dsc,
7987 int rd, unsigned int imm)
7990 /* Encoding T2: ADDS Rd, #imm */
7991 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7993 install_pc_relative (gdbarch, regs, dsc, rd);
7999 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
8000 struct regcache *regs,
8001 struct displaced_step_closure *dsc)
8003 unsigned int rd = bits (insn, 8, 10);
8004 unsigned int imm8 = bits (insn, 0, 7);
8006 if (debug_displaced)
8007 fprintf_unfiltered (gdb_stdlog,
8008 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8011 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
8015 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
8016 uint16_t insn2, struct regcache *regs,
8017 struct displaced_step_closure *dsc)
8019 unsigned int rd = bits (insn2, 8, 11);
8020 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8021 extract raw immediate encoding rather than computing immediate. When
8022 generating ADD or SUB instruction, we can simply perform OR operation to
8023 set immediate into ADD. */
8024 unsigned int imm_3_8 = insn2 & 0x70ff;
8025 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
8027 if (debug_displaced)
8028 fprintf_unfiltered (gdb_stdlog,
8029 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8030 rd, imm_i, imm_3_8, insn1, insn2);
8032 if (bit (insn1, 7)) /* Encoding T2 */
8034 /* Encoding T3: SUB Rd, Rd, #imm */
8035 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
8036 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8038 else /* Encoding T3 */
8040 /* Encoding T3: ADD Rd, Rd, #imm */
8041 dsc->modinsn[0] = (0xf100 | rd | imm_i);
8042 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8046 install_pc_relative (gdbarch, regs, dsc, rd);
8052 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
8053 struct regcache *regs,
8054 struct displaced_step_closure *dsc)
8056 unsigned int rt = bits (insn1, 8, 10);
8058 int imm8 = (bits (insn1, 0, 7) << 2);
8059 CORE_ADDR from = dsc->insn_addr;
8065 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8067 Insn: LDR R0, [R2, R3];
8068 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8070 if (debug_displaced)
8071 fprintf_unfiltered (gdb_stdlog,
8072 "displaced: copying thumb ldr r%d [pc #%d]\n"
8075 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8076 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8077 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8078 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8079 /* The assembler calculates the required value of the offset from the
8080 Align(PC,4) value of this instruction to the label. */
8081 pc = pc & 0xfffffffc;
8083 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8084 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8087 dsc->u.ldst.xfersize = 4;
8089 dsc->u.ldst.immed = 0;
8090 dsc->u.ldst.writeback = 0;
8091 dsc->u.ldst.restore_r4 = 0;
8093 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8095 dsc->cleanup = &cleanup_load;
8100 /* Copy Thumb cbnz/cbz insruction. */
8103 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
8104 struct regcache *regs,
8105 struct displaced_step_closure *dsc)
8107 int non_zero = bit (insn1, 11);
8108 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
8109 CORE_ADDR from = dsc->insn_addr;
8110 int rn = bits (insn1, 0, 2);
8111 int rn_val = displaced_read_reg (regs, dsc, rn);
8113 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8114 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8115 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8116 condition is false, let it be, cleanup_branch will do nothing. */
8117 if (dsc->u.branch.cond)
8119 dsc->u.branch.cond = INST_AL;
8120 dsc->u.branch.dest = from + 4 + imm5;
8123 dsc->u.branch.dest = from + 2;
8125 dsc->u.branch.link = 0;
8126 dsc->u.branch.exchange = 0;
8128 if (debug_displaced)
8129 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
8130 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
8131 rn, rn_val, insn1, dsc->u.branch.dest);
8133 dsc->modinsn[0] = THUMB_NOP;
8135 dsc->cleanup = &cleanup_branch;
8139 /* Copy Table Branch Byte/Halfword */
8141 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
8142 uint16_t insn2, struct regcache *regs,
8143 struct displaced_step_closure *dsc)
8145 ULONGEST rn_val, rm_val;
8146 int is_tbh = bit (insn2, 4);
8147 CORE_ADDR halfwords = 0;
8148 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8150 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8151 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8157 target_read_memory (rn_val + 2 * rm_val, buf, 2);
8158 halfwords = extract_unsigned_integer (buf, 2, byte_order);
8164 target_read_memory (rn_val + rm_val, buf, 1);
8165 halfwords = extract_unsigned_integer (buf, 1, byte_order);
8168 if (debug_displaced)
8169 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
8170 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
8171 (unsigned int) rn_val, (unsigned int) rm_val,
8172 (unsigned int) halfwords);
8174 dsc->u.branch.cond = INST_AL;
8175 dsc->u.branch.link = 0;
8176 dsc->u.branch.exchange = 0;
8177 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8179 dsc->cleanup = &cleanup_branch;
8185 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8186 struct displaced_step_closure *dsc)
8189 int val = displaced_read_reg (regs, dsc, 7);
8190 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8193 val = displaced_read_reg (regs, dsc, 8);
8194 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8197 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8202 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8203 struct regcache *regs,
8204 struct displaced_step_closure *dsc)
8206 dsc->u.block.regmask = insn1 & 0x00ff;
8208 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8211 (1) register list is full, that is, r0-r7 are used.
8212 Prepare: tmp[0] <- r8
8214 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8215 MOV r8, r7; Move value of r7 to r8;
8216 POP {r7}; Store PC value into r7.
8218 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8220 (2) register list is not full, supposing there are N registers in
8221 register list (except PC, 0 <= N <= 7).
8222 Prepare: for each i, 0 - N, tmp[i] <- ri.
8224 POP {r0, r1, ...., rN};
8226 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8227 from tmp[] properly.
8229 if (debug_displaced)
8230 fprintf_unfiltered (gdb_stdlog,
8231 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8232 dsc->u.block.regmask, insn1);
8234 if (dsc->u.block.regmask == 0xff)
8236 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8238 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8239 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8240 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8243 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8247 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8248 unsigned int new_regmask, bit = 1;
8249 unsigned int to = 0, from = 0, i, new_rn;
8251 for (i = 0; i < num_in_list + 1; i++)
8252 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8254 new_regmask = (1 << (num_in_list + 1)) - 1;
8256 if (debug_displaced)
8257 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8258 "{..., pc}: original reg list %.4x,"
8259 " modified list %.4x\n"),
8260 (int) dsc->u.block.regmask, new_regmask);
8262 dsc->u.block.regmask |= 0x8000;
8263 dsc->u.block.writeback = 0;
8264 dsc->u.block.cond = INST_AL;
8266 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8268 dsc->cleanup = &cleanup_block_load_pc;
8275 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8276 struct regcache *regs,
8277 struct displaced_step_closure *dsc)
8279 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8280 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8283 /* 16-bit thumb instructions. */
8284 switch (op_bit_12_15)
8286 /* Shift (imme), add, subtract, move and compare. */
8287 case 0: case 1: case 2: case 3:
8288 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8289 "shift/add/sub/mov/cmp",
8293 switch (op_bit_10_11)
8295 case 0: /* Data-processing */
8296 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8300 case 1: /* Special data instructions and branch and exchange. */
8302 unsigned short op = bits (insn1, 7, 9);
8303 if (op == 6 || op == 7) /* BX or BLX */
8304 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8305 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8306 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8308 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8312 default: /* LDR (literal) */
8313 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8316 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8317 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8320 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8321 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8322 else /* Generate SP-relative address */
8323 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8325 case 11: /* Misc 16-bit instructions */
8327 switch (bits (insn1, 8, 11))
8329 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8330 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8332 case 12: case 13: /* POP */
8333 if (bit (insn1, 8)) /* PC is in register list. */
8334 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8336 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8338 case 15: /* If-Then, and hints */
8339 if (bits (insn1, 0, 3))
8340 /* If-Then makes up to four following instructions conditional.
8341 IT instruction itself is not conditional, so handle it as a
8342 common unmodified instruction. */
8343 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8346 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8349 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8354 if (op_bit_10_11 < 2) /* Store multiple registers */
8355 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8356 else /* Load multiple registers */
8357 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8359 case 13: /* Conditional branch and supervisor call */
8360 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8361 err = thumb_copy_b (gdbarch, insn1, dsc);
8363 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8365 case 14: /* Unconditional branch */
8366 err = thumb_copy_b (gdbarch, insn1, dsc);
8373 internal_error (__FILE__, __LINE__,
8374 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8378 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8379 uint16_t insn1, uint16_t insn2,
8380 struct regcache *regs,
8381 struct displaced_step_closure *dsc)
8383 int rt = bits (insn2, 12, 15);
8384 int rn = bits (insn1, 0, 3);
8385 int op1 = bits (insn1, 7, 8);
8388 switch (bits (insn1, 5, 6))
8390 case 0: /* Load byte and memory hints */
8391 if (rt == 0xf) /* PLD/PLI */
8394 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8395 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8397 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8402 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8403 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8406 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8407 "ldrb{reg, immediate}/ldrbt",
8412 case 1: /* Load halfword and memory hints. */
8413 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8414 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8415 "pld/unalloc memhint", dsc);
8419 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8422 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8426 case 2: /* Load word */
8428 int insn2_bit_8_11 = bits (insn2, 8, 11);
8431 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8432 else if (op1 == 0x1) /* Encoding T3 */
8433 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8435 else /* op1 == 0x0 */
8437 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8438 /* LDR (immediate) */
8439 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8440 dsc, bit (insn2, 8), 1);
8441 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8442 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8445 /* LDR (register) */
8446 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8452 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8459 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8460 uint16_t insn2, struct regcache *regs,
8461 struct displaced_step_closure *dsc)
8464 unsigned short op = bit (insn2, 15);
8465 unsigned int op1 = bits (insn1, 11, 12);
8471 switch (bits (insn1, 9, 10))
8476 /* Load/store {dual, execlusive}, table branch. */
8477 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8478 && bits (insn2, 5, 7) == 0)
8479 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8482 /* PC is not allowed to use in load/store {dual, exclusive}
8484 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8485 "load/store dual/ex", dsc);
8487 else /* load/store multiple */
8489 switch (bits (insn1, 7, 8))
8491 case 0: case 3: /* SRS, RFE */
8492 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8495 case 1: case 2: /* LDM/STM/PUSH/POP */
8496 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8503 /* Data-processing (shift register). */
8504 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8507 default: /* Coprocessor instructions. */
8508 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8513 case 2: /* op1 = 2 */
8514 if (op) /* Branch and misc control. */
8516 if (bit (insn2, 14) /* BLX/BL */
8517 || bit (insn2, 12) /* Unconditional branch */
8518 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8519 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8521 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8526 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8528 int op = bits (insn1, 4, 8);
8529 int rn = bits (insn1, 0, 3);
8530 if ((op == 0 || op == 0xa) && rn == 0xf)
8531 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8534 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8537 else /* Data processing (modified immeidate) */
8538 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8542 case 3: /* op1 = 3 */
8543 switch (bits (insn1, 9, 10))
8547 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8549 else /* NEON Load/Store and Store single data item */
8550 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8551 "neon elt/struct load/store",
8554 case 1: /* op1 = 3, bits (9, 10) == 1 */
8555 switch (bits (insn1, 7, 8))
8557 case 0: case 1: /* Data processing (register) */
8558 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8561 case 2: /* Multiply and absolute difference */
8562 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8563 "mul/mua/diff", dsc);
8565 case 3: /* Long multiply and divide */
8566 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8571 default: /* Coprocessor instructions */
8572 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8581 internal_error (__FILE__, __LINE__,
8582 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8587 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8588 CORE_ADDR to, struct regcache *regs,
8589 struct displaced_step_closure *dsc)
8591 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8593 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8595 if (debug_displaced)
8596 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8597 "at %.8lx\n", insn1, (unsigned long) from);
8600 dsc->insn_size = thumb_insn_size (insn1);
8601 if (thumb_insn_size (insn1) == 4)
8604 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8605 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8608 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8612 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8613 CORE_ADDR to, struct regcache *regs,
8614 struct displaced_step_closure *dsc)
8617 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8620 /* Most displaced instructions use a 1-instruction scratch space, so set this
8621 here and override below if/when necessary. */
8623 dsc->insn_addr = from;
8624 dsc->scratch_base = to;
8625 dsc->cleanup = NULL;
8626 dsc->wrote_to_pc = 0;
8628 if (!displaced_in_arm_mode (regs))
8629 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8633 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8634 if (debug_displaced)
8635 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8636 "at %.8lx\n", (unsigned long) insn,
8637 (unsigned long) from);
8639 if ((insn & 0xf0000000) == 0xf0000000)
8640 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8641 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8643 case 0x0: case 0x1: case 0x2: case 0x3:
8644 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8647 case 0x4: case 0x5: case 0x6:
8648 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8652 err = arm_decode_media (gdbarch, insn, dsc);
8655 case 0x8: case 0x9: case 0xa: case 0xb:
8656 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8659 case 0xc: case 0xd: case 0xe: case 0xf:
8660 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8665 internal_error (__FILE__, __LINE__,
8666 _("arm_process_displaced_insn: Instruction decode error"));
8669 /* Actually set up the scratch space for a displaced instruction. */
8672 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8673 CORE_ADDR to, struct displaced_step_closure *dsc)
8675 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8676 unsigned int i, len, offset;
8677 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8678 int size = dsc->is_thumb? 2 : 4;
8679 const gdb_byte *bkp_insn;
8682 /* Poke modified instruction(s). */
8683 for (i = 0; i < dsc->numinsns; i++)
8685 if (debug_displaced)
8687 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8689 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8692 fprintf_unfiltered (gdb_stdlog, "%.4x",
8693 (unsigned short)dsc->modinsn[i]);
8695 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8696 (unsigned long) to + offset);
8699 write_memory_unsigned_integer (to + offset, size,
8700 byte_order_for_code,
8705 /* Choose the correct breakpoint instruction. */
8708 bkp_insn = tdep->thumb_breakpoint;
8709 len = tdep->thumb_breakpoint_size;
8713 bkp_insn = tdep->arm_breakpoint;
8714 len = tdep->arm_breakpoint_size;
8717 /* Put breakpoint afterwards. */
8718 write_memory (to + offset, bkp_insn, len);
8720 if (debug_displaced)
8721 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8722 paddress (gdbarch, from), paddress (gdbarch, to));
8725 /* Entry point for copying an instruction into scratch space for displaced
8728 struct displaced_step_closure *
8729 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8730 CORE_ADDR from, CORE_ADDR to,
8731 struct regcache *regs)
8733 struct displaced_step_closure *dsc
8734 = xmalloc (sizeof (struct displaced_step_closure));
8735 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8736 arm_displaced_init_closure (gdbarch, from, to, dsc);
8741 /* Entry point for cleaning things up after a displaced instruction has been
8745 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8746 struct displaced_step_closure *dsc,
8747 CORE_ADDR from, CORE_ADDR to,
8748 struct regcache *regs)
8751 dsc->cleanup (gdbarch, regs, dsc);
8753 if (!dsc->wrote_to_pc)
8754 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8755 dsc->insn_addr + dsc->insn_size);
8759 #include "bfd-in2.h"
8760 #include "libcoff.h"
8763 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8765 struct gdbarch *gdbarch = info->application_data;
8767 if (arm_pc_is_thumb (gdbarch, memaddr))
8769 static asymbol *asym;
8770 static combined_entry_type ce;
8771 static struct coff_symbol_struct csym;
8772 static struct bfd fake_bfd;
8773 static bfd_target fake_target;
8775 if (csym.native == NULL)
8777 /* Create a fake symbol vector containing a Thumb symbol.
8778 This is solely so that the code in print_insn_little_arm()
8779 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8780 the presence of a Thumb symbol and switch to decoding
8781 Thumb instructions. */
8783 fake_target.flavour = bfd_target_coff_flavour;
8784 fake_bfd.xvec = &fake_target;
8785 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8787 csym.symbol.the_bfd = &fake_bfd;
8788 csym.symbol.name = "fake";
8789 asym = (asymbol *) & csym;
8792 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8793 info->symbols = &asym;
8796 info->symbols = NULL;
8798 if (info->endian == BFD_ENDIAN_BIG)
8799 return print_insn_big_arm (memaddr, info);
8801 return print_insn_little_arm (memaddr, info);
8804 /* The following define instruction sequences that will cause ARM
8805 cpu's to take an undefined instruction trap. These are used to
8806 signal a breakpoint to GDB.
8808 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8809 modes. A different instruction is required for each mode. The ARM
8810 cpu's can also be big or little endian. Thus four different
8811 instructions are needed to support all cases.
8813 Note: ARMv4 defines several new instructions that will take the
8814 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8815 not in fact add the new instructions. The new undefined
8816 instructions in ARMv4 are all instructions that had no defined
8817 behaviour in earlier chips. There is no guarantee that they will
8818 raise an exception, but may be treated as NOP's. In practice, it
8819 may only safe to rely on instructions matching:
8821 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8822 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8823 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8825 Even this may only true if the condition predicate is true. The
8826 following use a condition predicate of ALWAYS so it is always TRUE.
8828 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8829 and NetBSD all use a software interrupt rather than an undefined
8830 instruction to force a trap. This can be handled by by the
8831 abi-specific code during establishment of the gdbarch vector. */
8833 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8834 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8835 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8836 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8838 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8839 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8840 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8841 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8843 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8844 the program counter value to determine whether a 16-bit or 32-bit
8845 breakpoint should be used. It returns a pointer to a string of
8846 bytes that encode a breakpoint instruction, stores the length of
8847 the string to *lenptr, and adjusts the program counter (if
8848 necessary) to point to the actual memory location where the
8849 breakpoint should be inserted. */
8851 static const unsigned char *
8852 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8854 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8855 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8857 if (arm_pc_is_thumb (gdbarch, *pcptr))
8859 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8861 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8862 check whether we are replacing a 32-bit instruction. */
8863 if (tdep->thumb2_breakpoint != NULL)
8866 if (target_read_memory (*pcptr, buf, 2) == 0)
8868 unsigned short inst1;
8869 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8870 if (thumb_insn_size (inst1) == 4)
8872 *lenptr = tdep->thumb2_breakpoint_size;
8873 return tdep->thumb2_breakpoint;
8878 *lenptr = tdep->thumb_breakpoint_size;
8879 return tdep->thumb_breakpoint;
8883 *lenptr = tdep->arm_breakpoint_size;
8884 return tdep->arm_breakpoint;
8889 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8892 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8894 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8895 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8896 that this is not confused with a 32-bit ARM breakpoint. */
8900 /* Extract from an array REGBUF containing the (raw) register state a
8901 function return value of type TYPE, and copy that, in virtual
8902 format, into VALBUF. */
8905 arm_extract_return_value (struct type *type, struct regcache *regs,
8908 struct gdbarch *gdbarch = get_regcache_arch (regs);
8909 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8911 if (TYPE_CODE_FLT == TYPE_CODE (type))
8913 switch (gdbarch_tdep (gdbarch)->fp_model)
8917 /* The value is in register F0 in internal format. We need to
8918 extract the raw value and then convert it to the desired
8920 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8922 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8923 convert_from_extended (floatformat_from_type (type), tmpbuf,
8924 valbuf, gdbarch_byte_order (gdbarch));
8928 case ARM_FLOAT_SOFT_FPA:
8929 case ARM_FLOAT_SOFT_VFP:
8930 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8931 not using the VFP ABI code. */
8933 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8934 if (TYPE_LENGTH (type) > 4)
8935 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8936 valbuf + INT_REGISTER_SIZE);
8940 internal_error (__FILE__, __LINE__,
8941 _("arm_extract_return_value: "
8942 "Floating point model not supported"));
8946 else if (TYPE_CODE (type) == TYPE_CODE_INT
8947 || TYPE_CODE (type) == TYPE_CODE_CHAR
8948 || TYPE_CODE (type) == TYPE_CODE_BOOL
8949 || TYPE_CODE (type) == TYPE_CODE_PTR
8950 || TYPE_CODE (type) == TYPE_CODE_REF
8951 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8953 /* If the type is a plain integer, then the access is
8954 straight-forward. Otherwise we have to play around a bit
8956 int len = TYPE_LENGTH (type);
8957 int regno = ARM_A1_REGNUM;
8962 /* By using store_unsigned_integer we avoid having to do
8963 anything special for small big-endian values. */
8964 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8965 store_unsigned_integer (valbuf,
8966 (len > INT_REGISTER_SIZE
8967 ? INT_REGISTER_SIZE : len),
8969 len -= INT_REGISTER_SIZE;
8970 valbuf += INT_REGISTER_SIZE;
8975 /* For a structure or union the behaviour is as if the value had
8976 been stored to word-aligned memory and then loaded into
8977 registers with 32-bit load instruction(s). */
8978 int len = TYPE_LENGTH (type);
8979 int regno = ARM_A1_REGNUM;
8980 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8984 regcache_cooked_read (regs, regno++, tmpbuf);
8985 memcpy (valbuf, tmpbuf,
8986 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8987 len -= INT_REGISTER_SIZE;
8988 valbuf += INT_REGISTER_SIZE;
8994 /* Will a function return an aggregate type in memory or in a
8995 register? Return 0 if an aggregate type can be returned in a
8996 register, 1 if it must be returned in memory. */
8999 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
9002 enum type_code code;
9004 CHECK_TYPEDEF (type);
9006 /* In the ARM ABI, "integer" like aggregate types are returned in
9007 registers. For an aggregate type to be integer like, its size
9008 must be less than or equal to INT_REGISTER_SIZE and the
9009 offset of each addressable subfield must be zero. Note that bit
9010 fields are not addressable, and all addressable subfields of
9011 unions always start at offset zero.
9013 This function is based on the behaviour of GCC 2.95.1.
9014 See: gcc/arm.c: arm_return_in_memory() for details.
9016 Note: All versions of GCC before GCC 2.95.2 do not set up the
9017 parameters correctly for a function returning the following
9018 structure: struct { float f;}; This should be returned in memory,
9019 not a register. Richard Earnshaw sent me a patch, but I do not
9020 know of any way to detect if a function like the above has been
9021 compiled with the correct calling convention. */
9023 /* All aggregate types that won't fit in a register must be returned
9025 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
9030 /* The AAPCS says all aggregates not larger than a word are returned
9032 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
9035 /* The only aggregate types that can be returned in a register are
9036 structs and unions. Arrays must be returned in memory. */
9037 code = TYPE_CODE (type);
9038 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
9043 /* Assume all other aggregate types can be returned in a register.
9044 Run a check for structures, unions and arrays. */
9047 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
9050 /* Need to check if this struct/union is "integer" like. For
9051 this to be true, its size must be less than or equal to
9052 INT_REGISTER_SIZE and the offset of each addressable
9053 subfield must be zero. Note that bit fields are not
9054 addressable, and unions always start at offset zero. If any
9055 of the subfields is a floating point type, the struct/union
9056 cannot be an integer type. */
9058 /* For each field in the object, check:
9059 1) Is it FP? --> yes, nRc = 1;
9060 2) Is it addressable (bitpos != 0) and
9061 not packed (bitsize == 0)?
9065 for (i = 0; i < TYPE_NFIELDS (type); i++)
9067 enum type_code field_type_code;
9068 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
9071 /* Is it a floating point type field? */
9072 if (field_type_code == TYPE_CODE_FLT)
9078 /* If bitpos != 0, then we have to care about it. */
9079 if (TYPE_FIELD_BITPOS (type, i) != 0)
9081 /* Bitfields are not addressable. If the field bitsize is
9082 zero, then the field is not packed. Hence it cannot be
9083 a bitfield or any other packed type. */
9084 if (TYPE_FIELD_BITSIZE (type, i) == 0)
9096 /* Write into appropriate registers a function return value of type
9097 TYPE, given in virtual format. */
9100 arm_store_return_value (struct type *type, struct regcache *regs,
9101 const gdb_byte *valbuf)
9103 struct gdbarch *gdbarch = get_regcache_arch (regs);
9104 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9106 if (TYPE_CODE (type) == TYPE_CODE_FLT)
9108 gdb_byte buf[MAX_REGISTER_SIZE];
9110 switch (gdbarch_tdep (gdbarch)->fp_model)
9114 convert_to_extended (floatformat_from_type (type), buf, valbuf,
9115 gdbarch_byte_order (gdbarch));
9116 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
9119 case ARM_FLOAT_SOFT_FPA:
9120 case ARM_FLOAT_SOFT_VFP:
9121 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9122 not using the VFP ABI code. */
9124 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
9125 if (TYPE_LENGTH (type) > 4)
9126 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
9127 valbuf + INT_REGISTER_SIZE);
9131 internal_error (__FILE__, __LINE__,
9132 _("arm_store_return_value: Floating "
9133 "point model not supported"));
9137 else if (TYPE_CODE (type) == TYPE_CODE_INT
9138 || TYPE_CODE (type) == TYPE_CODE_CHAR
9139 || TYPE_CODE (type) == TYPE_CODE_BOOL
9140 || TYPE_CODE (type) == TYPE_CODE_PTR
9141 || TYPE_CODE (type) == TYPE_CODE_REF
9142 || TYPE_CODE (type) == TYPE_CODE_ENUM)
9144 if (TYPE_LENGTH (type) <= 4)
9146 /* Values of one word or less are zero/sign-extended and
9148 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9149 LONGEST val = unpack_long (type, valbuf);
9151 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
9152 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
9156 /* Integral values greater than one word are stored in consecutive
9157 registers starting with r0. This will always be a multiple of
9158 the regiser size. */
9159 int len = TYPE_LENGTH (type);
9160 int regno = ARM_A1_REGNUM;
9164 regcache_cooked_write (regs, regno++, valbuf);
9165 len -= INT_REGISTER_SIZE;
9166 valbuf += INT_REGISTER_SIZE;
9172 /* For a structure or union the behaviour is as if the value had
9173 been stored to word-aligned memory and then loaded into
9174 registers with 32-bit load instruction(s). */
9175 int len = TYPE_LENGTH (type);
9176 int regno = ARM_A1_REGNUM;
9177 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9181 memcpy (tmpbuf, valbuf,
9182 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9183 regcache_cooked_write (regs, regno++, tmpbuf);
9184 len -= INT_REGISTER_SIZE;
9185 valbuf += INT_REGISTER_SIZE;
9191 /* Handle function return values. */
9193 static enum return_value_convention
9194 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9195 struct type *valtype, struct regcache *regcache,
9196 gdb_byte *readbuf, const gdb_byte *writebuf)
9198 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9199 struct type *func_type = function ? value_type (function) : NULL;
9200 enum arm_vfp_cprc_base_type vfp_base_type;
9203 if (arm_vfp_abi_for_function (gdbarch, func_type)
9204 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9206 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9207 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9209 for (i = 0; i < vfp_base_count; i++)
9211 if (reg_char == 'q')
9214 arm_neon_quad_write (gdbarch, regcache, i,
9215 writebuf + i * unit_length);
9218 arm_neon_quad_read (gdbarch, regcache, i,
9219 readbuf + i * unit_length);
9226 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
9227 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9230 regcache_cooked_write (regcache, regnum,
9231 writebuf + i * unit_length);
9233 regcache_cooked_read (regcache, regnum,
9234 readbuf + i * unit_length);
9237 return RETURN_VALUE_REGISTER_CONVENTION;
9240 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9241 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9242 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9244 if (tdep->struct_return == pcc_struct_return
9245 || arm_return_in_memory (gdbarch, valtype))
9246 return RETURN_VALUE_STRUCT_CONVENTION;
9249 /* AAPCS returns complex types longer than a register in memory. */
9250 if (tdep->arm_abi != ARM_ABI_APCS
9251 && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
9252 && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE)
9253 return RETURN_VALUE_STRUCT_CONVENTION;
9256 arm_store_return_value (valtype, regcache, writebuf);
9259 arm_extract_return_value (valtype, regcache, readbuf);
9261 return RETURN_VALUE_REGISTER_CONVENTION;
9266 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9268 struct gdbarch *gdbarch = get_frame_arch (frame);
9269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9270 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9272 gdb_byte buf[INT_REGISTER_SIZE];
9274 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9276 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9280 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9284 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9285 return the target PC. Otherwise return 0. */
9288 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9292 CORE_ADDR start_addr;
9294 /* Find the starting address and name of the function containing the PC. */
9295 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9297 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9299 start_addr = arm_skip_bx_reg (frame, pc);
9300 if (start_addr != 0)
9306 /* If PC is in a Thumb call or return stub, return the address of the
9307 target PC, which is in a register. The thunk functions are called
9308 _call_via_xx, where x is the register name. The possible names
9309 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9310 functions, named __ARM_call_via_r[0-7]. */
9311 if (strncmp (name, "_call_via_", 10) == 0
9312 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9314 /* Use the name suffix to determine which register contains the
9316 static char *table[15] =
9317 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9318 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9321 int offset = strlen (name) - 2;
9323 for (regno = 0; regno <= 14; regno++)
9324 if (strcmp (&name[offset], table[regno]) == 0)
9325 return get_frame_register_unsigned (frame, regno);
9328 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9329 non-interworking calls to foo. We could decode the stubs
9330 to find the target but it's easier to use the symbol table. */
9331 namelen = strlen (name);
9332 if (name[0] == '_' && name[1] == '_'
9333 && ((namelen > 2 + strlen ("_from_thumb")
9334 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
9335 strlen ("_from_thumb")) == 0)
9336 || (namelen > 2 + strlen ("_from_arm")
9337 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
9338 strlen ("_from_arm")) == 0)))
9341 int target_len = namelen - 2;
9342 struct bound_minimal_symbol minsym;
9343 struct objfile *objfile;
9344 struct obj_section *sec;
9346 if (name[namelen - 1] == 'b')
9347 target_len -= strlen ("_from_thumb");
9349 target_len -= strlen ("_from_arm");
9351 target_name = alloca (target_len + 1);
9352 memcpy (target_name, name + 2, target_len);
9353 target_name[target_len] = '\0';
9355 sec = find_pc_section (pc);
9356 objfile = (sec == NULL) ? NULL : sec->objfile;
9357 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9358 if (minsym.minsym != NULL)
9359 return BMSYMBOL_VALUE_ADDRESS (minsym);
9364 return 0; /* not a stub */
9368 set_arm_command (char *args, int from_tty)
9370 printf_unfiltered (_("\
9371 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9372 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9376 show_arm_command (char *args, int from_tty)
9378 cmd_show_list (showarmcmdlist, from_tty, "");
9382 arm_update_current_architecture (void)
9384 struct gdbarch_info info;
9386 /* If the current architecture is not ARM, we have nothing to do. */
9387 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
9390 /* Update the architecture. */
9391 gdbarch_info_init (&info);
9393 if (!gdbarch_update_p (info))
9394 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9398 set_fp_model_sfunc (char *args, int from_tty,
9399 struct cmd_list_element *c)
9401 enum arm_float_model fp_model;
9403 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9404 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9406 arm_fp_model = fp_model;
9410 if (fp_model == ARM_FLOAT_LAST)
9411 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9414 arm_update_current_architecture ();
9418 show_fp_model (struct ui_file *file, int from_tty,
9419 struct cmd_list_element *c, const char *value)
9421 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9423 if (arm_fp_model == ARM_FLOAT_AUTO
9424 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9425 fprintf_filtered (file, _("\
9426 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9427 fp_model_strings[tdep->fp_model]);
9429 fprintf_filtered (file, _("\
9430 The current ARM floating point model is \"%s\".\n"),
9431 fp_model_strings[arm_fp_model]);
9435 arm_set_abi (char *args, int from_tty,
9436 struct cmd_list_element *c)
9438 enum arm_abi_kind arm_abi;
9440 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9441 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9443 arm_abi_global = arm_abi;
9447 if (arm_abi == ARM_ABI_LAST)
9448 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9451 arm_update_current_architecture ();
9455 arm_show_abi (struct ui_file *file, int from_tty,
9456 struct cmd_list_element *c, const char *value)
9458 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9460 if (arm_abi_global == ARM_ABI_AUTO
9461 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9462 fprintf_filtered (file, _("\
9463 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9464 arm_abi_strings[tdep->arm_abi]);
9466 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9471 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9472 struct cmd_list_element *c, const char *value)
9474 fprintf_filtered (file,
9475 _("The current execution mode assumed "
9476 "(when symbols are unavailable) is \"%s\".\n"),
9477 arm_fallback_mode_string);
9481 arm_show_force_mode (struct ui_file *file, int from_tty,
9482 struct cmd_list_element *c, const char *value)
9484 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9486 fprintf_filtered (file,
9487 _("The current execution mode assumed "
9488 "(even when symbols are available) is \"%s\".\n"),
9489 arm_force_mode_string);
9492 /* If the user changes the register disassembly style used for info
9493 register and other commands, we have to also switch the style used
9494 in opcodes for disassembly output. This function is run in the "set
9495 arm disassembly" command, and does that. */
9498 set_disassembly_style_sfunc (char *args, int from_tty,
9499 struct cmd_list_element *c)
9501 set_disassembly_style ();
9504 /* Return the ARM register name corresponding to register I. */
9506 arm_register_name (struct gdbarch *gdbarch, int i)
9508 const int num_regs = gdbarch_num_regs (gdbarch);
9510 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9511 && i >= num_regs && i < num_regs + 32)
9513 static const char *const vfp_pseudo_names[] = {
9514 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9515 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9516 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9517 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9520 return vfp_pseudo_names[i - num_regs];
9523 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9524 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9526 static const char *const neon_pseudo_names[] = {
9527 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9528 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9531 return neon_pseudo_names[i - num_regs - 32];
9534 if (i >= ARRAY_SIZE (arm_register_names))
9535 /* These registers are only supported on targets which supply
9536 an XML description. */
9539 return arm_register_names[i];
9543 set_disassembly_style (void)
9547 /* Find the style that the user wants. */
9548 for (current = 0; current < num_disassembly_options; current++)
9549 if (disassembly_style == valid_disassembly_styles[current])
9551 gdb_assert (current < num_disassembly_options);
9553 /* Synchronize the disassembler. */
9554 set_arm_regname_option (current);
9557 /* Test whether the coff symbol specific value corresponds to a Thumb
9561 coff_sym_is_thumb (int val)
9563 return (val == C_THUMBEXT
9564 || val == C_THUMBSTAT
9565 || val == C_THUMBEXTFUNC
9566 || val == C_THUMBSTATFUNC
9567 || val == C_THUMBLABEL);
9570 /* arm_coff_make_msymbol_special()
9571 arm_elf_make_msymbol_special()
9573 These functions test whether the COFF or ELF symbol corresponds to
9574 an address in thumb code, and set a "special" bit in a minimal
9575 symbol to indicate that it does. */
9578 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9580 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9581 == ST_BRANCH_TO_THUMB)
9582 MSYMBOL_SET_SPECIAL (msym);
9586 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9588 if (coff_sym_is_thumb (val))
9589 MSYMBOL_SET_SPECIAL (msym);
9593 arm_objfile_data_free (struct objfile *objfile, void *arg)
9595 struct arm_per_objfile *data = arg;
9598 for (i = 0; i < objfile->obfd->section_count; i++)
9599 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9603 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9606 const char *name = bfd_asymbol_name (sym);
9607 struct arm_per_objfile *data;
9608 VEC(arm_mapping_symbol_s) **map_p;
9609 struct arm_mapping_symbol new_map_sym;
9611 gdb_assert (name[0] == '$');
9612 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9615 data = objfile_data (objfile, arm_objfile_data_key);
9618 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9619 struct arm_per_objfile);
9620 set_objfile_data (objfile, arm_objfile_data_key, data);
9621 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9622 objfile->obfd->section_count,
9623 VEC(arm_mapping_symbol_s) *);
9625 map_p = &data->section_maps[bfd_get_section (sym)->index];
9627 new_map_sym.value = sym->value;
9628 new_map_sym.type = name[1];
9630 /* Assume that most mapping symbols appear in order of increasing
9631 value. If they were randomly distributed, it would be faster to
9632 always push here and then sort at first use. */
9633 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9635 struct arm_mapping_symbol *prev_map_sym;
9637 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9638 if (prev_map_sym->value >= sym->value)
9641 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9642 arm_compare_mapping_symbols);
9643 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9648 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9652 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9654 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9655 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9657 /* If necessary, set the T bit. */
9660 ULONGEST val, t_bit;
9661 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9662 t_bit = arm_psr_thumb_bit (gdbarch);
9663 if (arm_pc_is_thumb (gdbarch, pc))
9664 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9667 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9672 /* Read the contents of a NEON quad register, by reading from two
9673 double registers. This is used to implement the quad pseudo
9674 registers, and for argument passing in case the quad registers are
9675 missing; vectors are passed in quad registers when using the VFP
9676 ABI, even if a NEON unit is not present. REGNUM is the index of
9677 the quad register, in [0, 15]. */
9679 static enum register_status
9680 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9681 int regnum, gdb_byte *buf)
9684 gdb_byte reg_buf[8];
9685 int offset, double_regnum;
9686 enum register_status status;
9688 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9689 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9692 /* d0 is always the least significant half of q0. */
9693 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9698 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9699 if (status != REG_VALID)
9701 memcpy (buf + offset, reg_buf, 8);
9703 offset = 8 - offset;
9704 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9705 if (status != REG_VALID)
9707 memcpy (buf + offset, reg_buf, 8);
9712 static enum register_status
9713 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9714 int regnum, gdb_byte *buf)
9716 const int num_regs = gdbarch_num_regs (gdbarch);
9718 gdb_byte reg_buf[8];
9719 int offset, double_regnum;
9721 gdb_assert (regnum >= num_regs);
9724 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9725 /* Quad-precision register. */
9726 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9729 enum register_status status;
9731 /* Single-precision register. */
9732 gdb_assert (regnum < 32);
9734 /* s0 is always the least significant half of d0. */
9735 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9736 offset = (regnum & 1) ? 0 : 4;
9738 offset = (regnum & 1) ? 4 : 0;
9740 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9741 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9744 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9745 if (status == REG_VALID)
9746 memcpy (buf, reg_buf + offset, 4);
9751 /* Store the contents of BUF to a NEON quad register, by writing to
9752 two double registers. This is used to implement the quad pseudo
9753 registers, and for argument passing in case the quad registers are
9754 missing; vectors are passed in quad registers when using the VFP
9755 ABI, even if a NEON unit is not present. REGNUM is the index
9756 of the quad register, in [0, 15]. */
9759 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9760 int regnum, const gdb_byte *buf)
9763 int offset, double_regnum;
9765 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9766 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9769 /* d0 is always the least significant half of q0. */
9770 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9775 regcache_raw_write (regcache, double_regnum, buf + offset);
9776 offset = 8 - offset;
9777 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9781 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9782 int regnum, const gdb_byte *buf)
9784 const int num_regs = gdbarch_num_regs (gdbarch);
9786 gdb_byte reg_buf[8];
9787 int offset, double_regnum;
9789 gdb_assert (regnum >= num_regs);
9792 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9793 /* Quad-precision register. */
9794 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9797 /* Single-precision register. */
9798 gdb_assert (regnum < 32);
9800 /* s0 is always the least significant half of d0. */
9801 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9802 offset = (regnum & 1) ? 0 : 4;
9804 offset = (regnum & 1) ? 4 : 0;
9806 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9807 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9810 regcache_raw_read (regcache, double_regnum, reg_buf);
9811 memcpy (reg_buf + offset, buf, 4);
9812 regcache_raw_write (regcache, double_regnum, reg_buf);
9816 static struct value *
9817 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9819 const int *reg_p = baton;
9820 return value_of_register (*reg_p, frame);
9823 static enum gdb_osabi
9824 arm_elf_osabi_sniffer (bfd *abfd)
9826 unsigned int elfosabi;
9827 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9829 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9831 if (elfosabi == ELFOSABI_ARM)
9832 /* GNU tools use this value. Check note sections in this case,
9834 bfd_map_over_sections (abfd,
9835 generic_elf_osabi_sniff_abi_tag_sections,
9838 /* Anything else will be handled by the generic ELF sniffer. */
9843 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9844 struct reggroup *group)
9846 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9847 this, FPS register belongs to save_regroup, restore_reggroup, and
9848 all_reggroup, of course. */
9849 if (regnum == ARM_FPS_REGNUM)
9850 return (group == float_reggroup
9851 || group == save_reggroup
9852 || group == restore_reggroup
9853 || group == all_reggroup);
9855 return default_register_reggroup_p (gdbarch, regnum, group);
9859 /* For backward-compatibility we allow two 'g' packet lengths with
9860 the remote protocol depending on whether FPA registers are
9861 supplied. M-profile targets do not have FPA registers, but some
9862 stubs already exist in the wild which use a 'g' packet which
9863 supplies them albeit with dummy values. The packet format which
9864 includes FPA registers should be considered deprecated for
9865 M-profile targets. */
9868 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9870 if (gdbarch_tdep (gdbarch)->is_m)
9872 /* If we know from the executable this is an M-profile target,
9873 cater for remote targets whose register set layout is the
9874 same as the FPA layout. */
9875 register_remote_g_packet_guess (gdbarch,
9876 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9877 (16 * INT_REGISTER_SIZE)
9878 + (8 * FP_REGISTER_SIZE)
9879 + (2 * INT_REGISTER_SIZE),
9880 tdesc_arm_with_m_fpa_layout);
9882 /* The regular M-profile layout. */
9883 register_remote_g_packet_guess (gdbarch,
9884 /* r0-r12,sp,lr,pc; xpsr */
9885 (16 * INT_REGISTER_SIZE)
9886 + INT_REGISTER_SIZE,
9889 /* M-profile plus M4F VFP. */
9890 register_remote_g_packet_guess (gdbarch,
9891 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9892 (16 * INT_REGISTER_SIZE)
9893 + (16 * VFP_REGISTER_SIZE)
9894 + (2 * INT_REGISTER_SIZE),
9895 tdesc_arm_with_m_vfp_d16);
9898 /* Otherwise we don't have a useful guess. */
9902 /* Initialize the current architecture based on INFO. If possible,
9903 re-use an architecture from ARCHES, which is a list of
9904 architectures already created during this debugging session.
9906 Called e.g. at program startup, when reading a core file, and when
9907 reading a binary file. */
9909 static struct gdbarch *
9910 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9912 struct gdbarch_tdep *tdep;
9913 struct gdbarch *gdbarch;
9914 struct gdbarch_list *best_arch;
9915 enum arm_abi_kind arm_abi = arm_abi_global;
9916 enum arm_float_model fp_model = arm_fp_model;
9917 struct tdesc_arch_data *tdesc_data = NULL;
9919 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9921 int have_fpa_registers = 1;
9922 const struct target_desc *tdesc = info.target_desc;
9924 /* If we have an object to base this architecture on, try to determine
9927 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9929 int ei_osabi, e_flags;
9931 switch (bfd_get_flavour (info.abfd))
9933 case bfd_target_aout_flavour:
9934 /* Assume it's an old APCS-style ABI. */
9935 arm_abi = ARM_ABI_APCS;
9938 case bfd_target_coff_flavour:
9939 /* Assume it's an old APCS-style ABI. */
9941 arm_abi = ARM_ABI_APCS;
9944 case bfd_target_elf_flavour:
9945 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9946 e_flags = elf_elfheader (info.abfd)->e_flags;
9948 if (ei_osabi == ELFOSABI_ARM)
9950 /* GNU tools used to use this value, but do not for EABI
9951 objects. There's nowhere to tag an EABI version
9952 anyway, so assume APCS. */
9953 arm_abi = ARM_ABI_APCS;
9955 else if (ei_osabi == ELFOSABI_NONE)
9957 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9958 int attr_arch, attr_profile;
9962 case EF_ARM_EABI_UNKNOWN:
9963 /* Assume GNU tools. */
9964 arm_abi = ARM_ABI_APCS;
9967 case EF_ARM_EABI_VER4:
9968 case EF_ARM_EABI_VER5:
9969 arm_abi = ARM_ABI_AAPCS;
9970 /* EABI binaries default to VFP float ordering.
9971 They may also contain build attributes that can
9972 be used to identify if the VFP argument-passing
9974 if (fp_model == ARM_FLOAT_AUTO)
9977 switch (bfd_elf_get_obj_attr_int (info.abfd,
9982 /* "The user intended FP parameter/result
9983 passing to conform to AAPCS, base
9985 fp_model = ARM_FLOAT_SOFT_VFP;
9988 /* "The user intended FP parameter/result
9989 passing to conform to AAPCS, VFP
9991 fp_model = ARM_FLOAT_VFP;
9994 /* "The user intended FP parameter/result
9995 passing to conform to tool chain-specific
9996 conventions" - we don't know any such
9997 conventions, so leave it as "auto". */
10000 /* Attribute value not mentioned in the
10001 October 2008 ABI, so leave it as
10006 fp_model = ARM_FLOAT_SOFT_VFP;
10012 /* Leave it as "auto". */
10013 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
10018 /* Detect M-profile programs. This only works if the
10019 executable file includes build attributes; GCC does
10020 copy them to the executable, but e.g. RealView does
10022 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10024 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
10026 Tag_CPU_arch_profile);
10027 /* GCC specifies the profile for v6-M; RealView only
10028 specifies the profile for architectures starting with
10029 V7 (as opposed to architectures with a tag
10030 numerically greater than TAG_CPU_ARCH_V7). */
10031 if (!tdesc_has_registers (tdesc)
10032 && (attr_arch == TAG_CPU_ARCH_V6_M
10033 || attr_arch == TAG_CPU_ARCH_V6S_M
10034 || attr_profile == 'M'))
10039 if (fp_model == ARM_FLOAT_AUTO)
10041 int e_flags = elf_elfheader (info.abfd)->e_flags;
10043 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
10046 /* Leave it as "auto". Strictly speaking this case
10047 means FPA, but almost nobody uses that now, and
10048 many toolchains fail to set the appropriate bits
10049 for the floating-point model they use. */
10051 case EF_ARM_SOFT_FLOAT:
10052 fp_model = ARM_FLOAT_SOFT_FPA;
10054 case EF_ARM_VFP_FLOAT:
10055 fp_model = ARM_FLOAT_VFP;
10057 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
10058 fp_model = ARM_FLOAT_SOFT_VFP;
10063 if (e_flags & EF_ARM_BE8)
10064 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10069 /* Leave it as "auto". */
10074 /* Check any target description for validity. */
10075 if (tdesc_has_registers (tdesc))
10077 /* For most registers we require GDB's default names; but also allow
10078 the numeric names for sp / lr / pc, as a convenience. */
10079 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
10080 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
10081 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
10083 const struct tdesc_feature *feature;
10086 feature = tdesc_find_feature (tdesc,
10087 "org.gnu.gdb.arm.core");
10088 if (feature == NULL)
10090 feature = tdesc_find_feature (tdesc,
10091 "org.gnu.gdb.arm.m-profile");
10092 if (feature == NULL)
10098 tdesc_data = tdesc_data_alloc ();
10101 for (i = 0; i < ARM_SP_REGNUM; i++)
10102 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10103 arm_register_names[i]);
10104 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10107 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10110 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10114 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10115 ARM_PS_REGNUM, "xpsr");
10117 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10118 ARM_PS_REGNUM, "cpsr");
10122 tdesc_data_cleanup (tdesc_data);
10126 feature = tdesc_find_feature (tdesc,
10127 "org.gnu.gdb.arm.fpa");
10128 if (feature != NULL)
10131 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
10132 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10133 arm_register_names[i]);
10136 tdesc_data_cleanup (tdesc_data);
10141 have_fpa_registers = 0;
10143 feature = tdesc_find_feature (tdesc,
10144 "org.gnu.gdb.xscale.iwmmxt");
10145 if (feature != NULL)
10147 static const char *const iwmmxt_names[] = {
10148 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10149 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10150 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10151 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10155 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
10157 &= tdesc_numbered_register (feature, tdesc_data, i,
10158 iwmmxt_names[i - ARM_WR0_REGNUM]);
10160 /* Check for the control registers, but do not fail if they
10162 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
10163 tdesc_numbered_register (feature, tdesc_data, i,
10164 iwmmxt_names[i - ARM_WR0_REGNUM]);
10166 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
10168 &= tdesc_numbered_register (feature, tdesc_data, i,
10169 iwmmxt_names[i - ARM_WR0_REGNUM]);
10173 tdesc_data_cleanup (tdesc_data);
10178 /* If we have a VFP unit, check whether the single precision registers
10179 are present. If not, then we will synthesize them as pseudo
10181 feature = tdesc_find_feature (tdesc,
10182 "org.gnu.gdb.arm.vfp");
10183 if (feature != NULL)
10185 static const char *const vfp_double_names[] = {
10186 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10187 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10188 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10189 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10192 /* Require the double precision registers. There must be either
10195 for (i = 0; i < 32; i++)
10197 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10199 vfp_double_names[i]);
10203 if (!valid_p && i == 16)
10206 /* Also require FPSCR. */
10207 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10208 ARM_FPSCR_REGNUM, "fpscr");
10211 tdesc_data_cleanup (tdesc_data);
10215 if (tdesc_unnumbered_register (feature, "s0") == 0)
10216 have_vfp_pseudos = 1;
10218 have_vfp_registers = 1;
10220 /* If we have VFP, also check for NEON. The architecture allows
10221 NEON without VFP (integer vector operations only), but GDB
10222 does not support that. */
10223 feature = tdesc_find_feature (tdesc,
10224 "org.gnu.gdb.arm.neon");
10225 if (feature != NULL)
10227 /* NEON requires 32 double-precision registers. */
10230 tdesc_data_cleanup (tdesc_data);
10234 /* If there are quad registers defined by the stub, use
10235 their type; otherwise (normally) provide them with
10236 the default type. */
10237 if (tdesc_unnumbered_register (feature, "q0") == 0)
10238 have_neon_pseudos = 1;
10245 /* If there is already a candidate, use it. */
10246 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10248 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10250 if (arm_abi != ARM_ABI_AUTO
10251 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10254 if (fp_model != ARM_FLOAT_AUTO
10255 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10258 /* There are various other properties in tdep that we do not
10259 need to check here: those derived from a target description,
10260 since gdbarches with a different target description are
10261 automatically disqualified. */
10263 /* Do check is_m, though, since it might come from the binary. */
10264 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10267 /* Found a match. */
10271 if (best_arch != NULL)
10273 if (tdesc_data != NULL)
10274 tdesc_data_cleanup (tdesc_data);
10275 return best_arch->gdbarch;
10278 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
10279 gdbarch = gdbarch_alloc (&info, tdep);
10281 /* Record additional information about the architecture we are defining.
10282 These are gdbarch discriminators, like the OSABI. */
10283 tdep->arm_abi = arm_abi;
10284 tdep->fp_model = fp_model;
10286 tdep->have_fpa_registers = have_fpa_registers;
10287 tdep->have_vfp_registers = have_vfp_registers;
10288 tdep->have_vfp_pseudos = have_vfp_pseudos;
10289 tdep->have_neon_pseudos = have_neon_pseudos;
10290 tdep->have_neon = have_neon;
10292 arm_register_g_packet_guesses (gdbarch);
10295 switch (info.byte_order_for_code)
10297 case BFD_ENDIAN_BIG:
10298 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10299 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10300 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10301 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10305 case BFD_ENDIAN_LITTLE:
10306 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10307 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10308 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10309 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10314 internal_error (__FILE__, __LINE__,
10315 _("arm_gdbarch_init: bad byte order for float format"));
10318 /* On ARM targets char defaults to unsigned. */
10319 set_gdbarch_char_signed (gdbarch, 0);
10321 /* Note: for displaced stepping, this includes the breakpoint, and one word
10322 of additional scratch space. This setting isn't used for anything beside
10323 displaced stepping at present. */
10324 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10326 /* This should be low enough for everything. */
10327 tdep->lowest_pc = 0x20;
10328 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10330 /* The default, for both APCS and AAPCS, is to return small
10331 structures in registers. */
10332 tdep->struct_return = reg_struct_return;
10334 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10335 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10337 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10339 /* Frame handling. */
10340 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10341 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10342 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10344 frame_base_set_default (gdbarch, &arm_normal_base);
10346 /* Address manipulation. */
10347 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10349 /* Advance PC across function entry code. */
10350 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10352 /* Detect whether PC is in function epilogue. */
10353 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
10355 /* Skip trampolines. */
10356 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10358 /* The stack grows downward. */
10359 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10361 /* Breakpoint manipulation. */
10362 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10363 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10364 arm_remote_breakpoint_from_pc);
10366 /* Information about registers, etc. */
10367 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10368 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10369 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10370 set_gdbarch_register_type (gdbarch, arm_register_type);
10371 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10373 /* This "info float" is FPA-specific. Use the generic version if we
10374 do not have FPA. */
10375 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10376 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10378 /* Internal <-> external register number maps. */
10379 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10380 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10382 set_gdbarch_register_name (gdbarch, arm_register_name);
10384 /* Returning results. */
10385 set_gdbarch_return_value (gdbarch, arm_return_value);
10388 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10390 /* Minsymbol frobbing. */
10391 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10392 set_gdbarch_coff_make_msymbol_special (gdbarch,
10393 arm_coff_make_msymbol_special);
10394 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10396 /* Thumb-2 IT block support. */
10397 set_gdbarch_adjust_breakpoint_address (gdbarch,
10398 arm_adjust_breakpoint_address);
10400 /* Virtual tables. */
10401 set_gdbarch_vbit_in_delta (gdbarch, 1);
10403 /* Hook in the ABI-specific overrides, if they have been registered. */
10404 gdbarch_init_osabi (info, gdbarch);
10406 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10408 /* Add some default predicates. */
10410 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
10411 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10412 dwarf2_append_unwinders (gdbarch);
10413 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10414 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10416 /* Now we have tuned the configuration, set a few final things,
10417 based on what the OS ABI has told us. */
10419 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10420 binaries are always marked. */
10421 if (tdep->arm_abi == ARM_ABI_AUTO)
10422 tdep->arm_abi = ARM_ABI_APCS;
10424 /* Watchpoints are not steppable. */
10425 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10427 /* We used to default to FPA for generic ARM, but almost nobody
10428 uses that now, and we now provide a way for the user to force
10429 the model. So default to the most useful variant. */
10430 if (tdep->fp_model == ARM_FLOAT_AUTO)
10431 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10433 if (tdep->jb_pc >= 0)
10434 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10436 /* Floating point sizes and format. */
10437 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10438 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10440 set_gdbarch_double_format
10441 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10442 set_gdbarch_long_double_format
10443 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10447 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10448 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10451 if (have_vfp_pseudos)
10453 /* NOTE: These are the only pseudo registers used by
10454 the ARM target at the moment. If more are added, a
10455 little more care in numbering will be needed. */
10457 int num_pseudos = 32;
10458 if (have_neon_pseudos)
10460 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10461 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10462 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10467 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10469 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10471 /* Override tdesc_register_type to adjust the types of VFP
10472 registers for NEON. */
10473 set_gdbarch_register_type (gdbarch, arm_register_type);
10476 /* Add standard register aliases. We add aliases even for those
10477 nanes which are used by the current architecture - it's simpler,
10478 and does no harm, since nothing ever lists user registers. */
10479 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10480 user_reg_add (gdbarch, arm_register_aliases[i].name,
10481 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10487 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10489 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10494 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10495 (unsigned long) tdep->lowest_pc);
10498 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10501 _initialize_arm_tdep (void)
10503 struct ui_file *stb;
10505 struct cmd_list_element *new_set, *new_show;
10506 const char *setname;
10507 const char *setdesc;
10508 const char *const *regnames;
10510 static char *helptext;
10511 char regdesc[1024], *rdptr = regdesc;
10512 size_t rest = sizeof (regdesc);
10514 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10516 arm_objfile_data_key
10517 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10519 /* Add ourselves to objfile event chain. */
10520 observer_attach_new_objfile (arm_exidx_new_objfile);
10522 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10524 /* Register an ELF OS ABI sniffer for ARM binaries. */
10525 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10526 bfd_target_elf_flavour,
10527 arm_elf_osabi_sniffer);
10529 /* Initialize the standard target descriptions. */
10530 initialize_tdesc_arm_with_m ();
10531 initialize_tdesc_arm_with_m_fpa_layout ();
10532 initialize_tdesc_arm_with_m_vfp_d16 ();
10533 initialize_tdesc_arm_with_iwmmxt ();
10534 initialize_tdesc_arm_with_vfpv2 ();
10535 initialize_tdesc_arm_with_vfpv3 ();
10536 initialize_tdesc_arm_with_neon ();
10538 /* Get the number of possible sets of register names defined in opcodes. */
10539 num_disassembly_options = get_arm_regname_num_options ();
10541 /* Add root prefix command for all "set arm"/"show arm" commands. */
10542 add_prefix_cmd ("arm", no_class, set_arm_command,
10543 _("Various ARM-specific commands."),
10544 &setarmcmdlist, "set arm ", 0, &setlist);
10546 add_prefix_cmd ("arm", no_class, show_arm_command,
10547 _("Various ARM-specific commands."),
10548 &showarmcmdlist, "show arm ", 0, &showlist);
10550 /* Sync the opcode insn printer with our register viewer. */
10551 parse_arm_disassembler_option ("reg-names-std");
10553 /* Initialize the array that will be passed to
10554 add_setshow_enum_cmd(). */
10555 valid_disassembly_styles
10556 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10557 for (i = 0; i < num_disassembly_options; i++)
10559 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10560 valid_disassembly_styles[i] = setname;
10561 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10564 /* When we find the default names, tell the disassembler to use
10566 if (!strcmp (setname, "std"))
10568 disassembly_style = setname;
10569 set_arm_regname_option (i);
10572 /* Mark the end of valid options. */
10573 valid_disassembly_styles[num_disassembly_options] = NULL;
10575 /* Create the help text. */
10576 stb = mem_fileopen ();
10577 fprintf_unfiltered (stb, "%s%s%s",
10578 _("The valid values are:\n"),
10580 _("The default is \"std\"."));
10581 helptext = ui_file_xstrdup (stb, NULL);
10582 ui_file_delete (stb);
10584 add_setshow_enum_cmd("disassembler", no_class,
10585 valid_disassembly_styles, &disassembly_style,
10586 _("Set the disassembly style."),
10587 _("Show the disassembly style."),
10589 set_disassembly_style_sfunc,
10590 NULL, /* FIXME: i18n: The disassembly style is
10592 &setarmcmdlist, &showarmcmdlist);
10594 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10595 _("Set usage of ARM 32-bit mode."),
10596 _("Show usage of ARM 32-bit mode."),
10597 _("When off, a 26-bit PC will be used."),
10599 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10601 &setarmcmdlist, &showarmcmdlist);
10603 /* Add a command to allow the user to force the FPU model. */
10604 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10605 _("Set the floating point type."),
10606 _("Show the floating point type."),
10607 _("auto - Determine the FP typefrom the OS-ABI.\n\
10608 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10609 fpa - FPA co-processor (GCC compiled).\n\
10610 softvfp - Software FP with pure-endian doubles.\n\
10611 vfp - VFP co-processor."),
10612 set_fp_model_sfunc, show_fp_model,
10613 &setarmcmdlist, &showarmcmdlist);
10615 /* Add a command to allow the user to force the ABI. */
10616 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10618 _("Show the ABI."),
10619 NULL, arm_set_abi, arm_show_abi,
10620 &setarmcmdlist, &showarmcmdlist);
10622 /* Add two commands to allow the user to force the assumed
10624 add_setshow_enum_cmd ("fallback-mode", class_support,
10625 arm_mode_strings, &arm_fallback_mode_string,
10626 _("Set the mode assumed when symbols are unavailable."),
10627 _("Show the mode assumed when symbols are unavailable."),
10628 NULL, NULL, arm_show_fallback_mode,
10629 &setarmcmdlist, &showarmcmdlist);
10630 add_setshow_enum_cmd ("force-mode", class_support,
10631 arm_mode_strings, &arm_force_mode_string,
10632 _("Set the mode assumed even when symbols are available."),
10633 _("Show the mode assumed even when symbols are available."),
10634 NULL, NULL, arm_show_force_mode,
10635 &setarmcmdlist, &showarmcmdlist);
10637 /* Debugging flag. */
10638 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10639 _("Set ARM debugging."),
10640 _("Show ARM debugging."),
10641 _("When on, arm-specific debugging is enabled."),
10643 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10644 &setdebuglist, &showdebuglist);
10647 /* ARM-reversible process record data structures. */
10649 #define ARM_INSN_SIZE_BYTES 4
10650 #define THUMB_INSN_SIZE_BYTES 2
10651 #define THUMB2_INSN_SIZE_BYTES 4
10654 #define INSN_S_L_BIT_NUM 20
10656 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10659 unsigned int reg_len = LENGTH; \
10662 REGS = XNEWVEC (uint32_t, reg_len); \
10663 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10668 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10671 unsigned int mem_len = LENGTH; \
10674 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10675 memcpy(&MEMS->len, &RECORD_BUF[0], \
10676 sizeof(struct arm_mem_r) * LENGTH); \
10681 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10682 #define INSN_RECORDED(ARM_RECORD) \
10683 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10685 /* ARM memory record structure. */
10688 uint32_t len; /* Record length. */
10689 uint32_t addr; /* Memory address. */
10692 /* ARM instruction record contains opcode of current insn
10693 and execution state (before entry to decode_insn()),
10694 contains list of to-be-modified registers and
10695 memory blocks (on return from decode_insn()). */
10697 typedef struct insn_decode_record_t
10699 struct gdbarch *gdbarch;
10700 struct regcache *regcache;
10701 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10702 uint32_t arm_insn; /* Should accommodate thumb. */
10703 uint32_t cond; /* Condition code. */
10704 uint32_t opcode; /* Insn opcode. */
10705 uint32_t decode; /* Insn decode bits. */
10706 uint32_t mem_rec_count; /* No of mem records. */
10707 uint32_t reg_rec_count; /* No of reg records. */
10708 uint32_t *arm_regs; /* Registers to be saved for this record. */
10709 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10710 } insn_decode_record;
10713 /* Checks ARM SBZ and SBO mandatory fields. */
10716 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10718 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10737 enum arm_record_result
10739 ARM_RECORD_SUCCESS = 0,
10740 ARM_RECORD_FAILURE = 1
10747 } arm_record_strx_t;
10758 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10759 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10762 struct regcache *reg_cache = arm_insn_r->regcache;
10763 ULONGEST u_regval[2]= {0};
10765 uint32_t reg_src1 = 0, reg_src2 = 0;
10766 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10767 uint32_t opcode1 = 0;
10769 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10770 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10771 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10774 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10776 /* 1) Handle misc store, immediate offset. */
10777 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10778 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10779 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10780 regcache_raw_read_unsigned (reg_cache, reg_src1,
10782 if (ARM_PC_REGNUM == reg_src1)
10784 /* If R15 was used as Rn, hence current PC+8. */
10785 u_regval[0] = u_regval[0] + 8;
10787 offset_8 = (immed_high << 4) | immed_low;
10788 /* Calculate target store address. */
10789 if (14 == arm_insn_r->opcode)
10791 tgt_mem_addr = u_regval[0] + offset_8;
10795 tgt_mem_addr = u_regval[0] - offset_8;
10797 if (ARM_RECORD_STRH == str_type)
10799 record_buf_mem[0] = 2;
10800 record_buf_mem[1] = tgt_mem_addr;
10801 arm_insn_r->mem_rec_count = 1;
10803 else if (ARM_RECORD_STRD == str_type)
10805 record_buf_mem[0] = 4;
10806 record_buf_mem[1] = tgt_mem_addr;
10807 record_buf_mem[2] = 4;
10808 record_buf_mem[3] = tgt_mem_addr + 4;
10809 arm_insn_r->mem_rec_count = 2;
10812 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10814 /* 2) Store, register offset. */
10816 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10818 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10819 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10820 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10821 if (15 == reg_src2)
10823 /* If R15 was used as Rn, hence current PC+8. */
10824 u_regval[0] = u_regval[0] + 8;
10826 /* Calculate target store address, Rn +/- Rm, register offset. */
10827 if (12 == arm_insn_r->opcode)
10829 tgt_mem_addr = u_regval[0] + u_regval[1];
10833 tgt_mem_addr = u_regval[1] - u_regval[0];
10835 if (ARM_RECORD_STRH == str_type)
10837 record_buf_mem[0] = 2;
10838 record_buf_mem[1] = tgt_mem_addr;
10839 arm_insn_r->mem_rec_count = 1;
10841 else if (ARM_RECORD_STRD == str_type)
10843 record_buf_mem[0] = 4;
10844 record_buf_mem[1] = tgt_mem_addr;
10845 record_buf_mem[2] = 4;
10846 record_buf_mem[3] = tgt_mem_addr + 4;
10847 arm_insn_r->mem_rec_count = 2;
10850 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10851 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10853 /* 3) Store, immediate pre-indexed. */
10854 /* 5) Store, immediate post-indexed. */
10855 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10856 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10857 offset_8 = (immed_high << 4) | immed_low;
10858 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10859 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10860 /* Calculate target store address, Rn +/- Rm, register offset. */
10861 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10863 tgt_mem_addr = u_regval[0] + offset_8;
10867 tgt_mem_addr = u_regval[0] - offset_8;
10869 if (ARM_RECORD_STRH == str_type)
10871 record_buf_mem[0] = 2;
10872 record_buf_mem[1] = tgt_mem_addr;
10873 arm_insn_r->mem_rec_count = 1;
10875 else if (ARM_RECORD_STRD == str_type)
10877 record_buf_mem[0] = 4;
10878 record_buf_mem[1] = tgt_mem_addr;
10879 record_buf_mem[2] = 4;
10880 record_buf_mem[3] = tgt_mem_addr + 4;
10881 arm_insn_r->mem_rec_count = 2;
10883 /* Record Rn also as it changes. */
10884 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10885 arm_insn_r->reg_rec_count = 1;
10887 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10888 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10890 /* 4) Store, register pre-indexed. */
10891 /* 6) Store, register post -indexed. */
10892 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10893 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10894 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10895 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10896 /* Calculate target store address, Rn +/- Rm, register offset. */
10897 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10899 tgt_mem_addr = u_regval[0] + u_regval[1];
10903 tgt_mem_addr = u_regval[1] - u_regval[0];
10905 if (ARM_RECORD_STRH == str_type)
10907 record_buf_mem[0] = 2;
10908 record_buf_mem[1] = tgt_mem_addr;
10909 arm_insn_r->mem_rec_count = 1;
10911 else if (ARM_RECORD_STRD == str_type)
10913 record_buf_mem[0] = 4;
10914 record_buf_mem[1] = tgt_mem_addr;
10915 record_buf_mem[2] = 4;
10916 record_buf_mem[3] = tgt_mem_addr + 4;
10917 arm_insn_r->mem_rec_count = 2;
10919 /* Record Rn also as it changes. */
10920 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10921 arm_insn_r->reg_rec_count = 1;
10926 /* Handling ARM extension space insns. */
10929 arm_record_extension_space (insn_decode_record *arm_insn_r)
10931 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10932 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10933 uint32_t record_buf[8], record_buf_mem[8];
10934 uint32_t reg_src1 = 0;
10935 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10936 struct regcache *reg_cache = arm_insn_r->regcache;
10937 ULONGEST u_regval = 0;
10939 gdb_assert (!INSN_RECORDED(arm_insn_r));
10940 /* Handle unconditional insn extension space. */
10942 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10943 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10944 if (arm_insn_r->cond)
10946 /* PLD has no affect on architectural state, it just affects
10948 if (5 == ((opcode1 & 0xE0) >> 5))
10951 record_buf[0] = ARM_PS_REGNUM;
10952 record_buf[1] = ARM_LR_REGNUM;
10953 arm_insn_r->reg_rec_count = 2;
10955 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10959 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10960 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10963 /* Undefined instruction on ARM V5; need to handle if later
10964 versions define it. */
10967 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10968 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10969 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10971 /* Handle arithmetic insn extension space. */
10972 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10973 && !INSN_RECORDED(arm_insn_r))
10975 /* Handle MLA(S) and MUL(S). */
10976 if (0 <= insn_op1 && 3 >= insn_op1)
10978 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10979 record_buf[1] = ARM_PS_REGNUM;
10980 arm_insn_r->reg_rec_count = 2;
10982 else if (4 <= insn_op1 && 15 >= insn_op1)
10984 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10985 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10986 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10987 record_buf[2] = ARM_PS_REGNUM;
10988 arm_insn_r->reg_rec_count = 3;
10992 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10993 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10994 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10996 /* Handle control insn extension space. */
10998 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10999 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
11001 if (!bit (arm_insn_r->arm_insn,25))
11003 if (!bits (arm_insn_r->arm_insn, 4, 7))
11005 if ((0 == insn_op1) || (2 == insn_op1))
11008 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11009 arm_insn_r->reg_rec_count = 1;
11011 else if (1 == insn_op1)
11013 /* CSPR is going to be changed. */
11014 record_buf[0] = ARM_PS_REGNUM;
11015 arm_insn_r->reg_rec_count = 1;
11017 else if (3 == insn_op1)
11019 /* SPSR is going to be changed. */
11020 /* We need to get SPSR value, which is yet to be done. */
11021 printf_unfiltered (_("Process record does not support "
11022 "instruction 0x%0x at address %s.\n"),
11023 arm_insn_r->arm_insn,
11024 paddress (arm_insn_r->gdbarch,
11025 arm_insn_r->this_addr));
11029 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
11034 record_buf[0] = ARM_PS_REGNUM;
11035 arm_insn_r->reg_rec_count = 1;
11037 else if (3 == insn_op1)
11040 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11041 arm_insn_r->reg_rec_count = 1;
11044 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
11047 record_buf[0] = ARM_PS_REGNUM;
11048 record_buf[1] = ARM_LR_REGNUM;
11049 arm_insn_r->reg_rec_count = 2;
11051 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
11053 /* QADD, QSUB, QDADD, QDSUB */
11054 record_buf[0] = ARM_PS_REGNUM;
11055 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11056 arm_insn_r->reg_rec_count = 2;
11058 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
11061 record_buf[0] = ARM_PS_REGNUM;
11062 record_buf[1] = ARM_LR_REGNUM;
11063 arm_insn_r->reg_rec_count = 2;
11065 /* Save SPSR also;how? */
11066 printf_unfiltered (_("Process record does not support "
11067 "instruction 0x%0x at address %s.\n"),
11068 arm_insn_r->arm_insn,
11069 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11072 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
11073 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
11074 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
11075 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
11078 if (0 == insn_op1 || 1 == insn_op1)
11080 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11081 /* We dont do optimization for SMULW<y> where we
11083 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11084 record_buf[1] = ARM_PS_REGNUM;
11085 arm_insn_r->reg_rec_count = 2;
11087 else if (2 == insn_op1)
11090 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11091 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11092 arm_insn_r->reg_rec_count = 2;
11094 else if (3 == insn_op1)
11097 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11098 arm_insn_r->reg_rec_count = 1;
11104 /* MSR : immediate form. */
11107 /* CSPR is going to be changed. */
11108 record_buf[0] = ARM_PS_REGNUM;
11109 arm_insn_r->reg_rec_count = 1;
11111 else if (3 == insn_op1)
11113 /* SPSR is going to be changed. */
11114 /* we need to get SPSR value, which is yet to be done */
11115 printf_unfiltered (_("Process record does not support "
11116 "instruction 0x%0x at address %s.\n"),
11117 arm_insn_r->arm_insn,
11118 paddress (arm_insn_r->gdbarch,
11119 arm_insn_r->this_addr));
11125 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
11126 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
11127 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
11129 /* Handle load/store insn extension space. */
11131 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
11132 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
11133 && !INSN_RECORDED(arm_insn_r))
11138 /* These insn, changes register and memory as well. */
11139 /* SWP or SWPB insn. */
11140 /* Get memory address given by Rn. */
11141 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11142 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11143 /* SWP insn ?, swaps word. */
11144 if (8 == arm_insn_r->opcode)
11146 record_buf_mem[0] = 4;
11150 /* SWPB insn, swaps only byte. */
11151 record_buf_mem[0] = 1;
11153 record_buf_mem[1] = u_regval;
11154 arm_insn_r->mem_rec_count = 1;
11155 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11156 arm_insn_r->reg_rec_count = 1;
11158 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11161 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11164 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11167 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11168 record_buf[1] = record_buf[0] + 1;
11169 arm_insn_r->reg_rec_count = 2;
11171 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11174 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11177 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
11179 /* LDRH, LDRSB, LDRSH. */
11180 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11181 arm_insn_r->reg_rec_count = 1;
11186 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
11187 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
11188 && !INSN_RECORDED(arm_insn_r))
11191 /* Handle coprocessor insn extension space. */
11194 /* To be done for ARMv5 and later; as of now we return -1. */
11196 printf_unfiltered (_("Process record does not support instruction x%0x "
11197 "at address %s.\n"),arm_insn_r->arm_insn,
11198 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11201 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11202 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11207 /* Handling opcode 000 insns. */
11210 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11212 struct regcache *reg_cache = arm_insn_r->regcache;
11213 uint32_t record_buf[8], record_buf_mem[8];
11214 ULONGEST u_regval[2] = {0};
11216 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11217 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11218 uint32_t opcode1 = 0;
11220 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11221 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11222 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11224 /* Data processing insn /multiply insn. */
11225 if (9 == arm_insn_r->decode
11226 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11227 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11229 /* Handle multiply instructions. */
11230 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11231 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11233 /* Handle MLA and MUL. */
11234 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11235 record_buf[1] = ARM_PS_REGNUM;
11236 arm_insn_r->reg_rec_count = 2;
11238 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11240 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11241 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11242 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11243 record_buf[2] = ARM_PS_REGNUM;
11244 arm_insn_r->reg_rec_count = 3;
11247 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11248 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11250 /* Handle misc load insns, as 20th bit (L = 1). */
11251 /* LDR insn has a capability to do branching, if
11252 MOV LR, PC is precceded by LDR insn having Rn as R15
11253 in that case, it emulates branch and link insn, and hence we
11254 need to save CSPR and PC as well. I am not sure this is right
11255 place; as opcode = 010 LDR insn make this happen, if R15 was
11257 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11258 if (15 != reg_dest)
11260 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11261 arm_insn_r->reg_rec_count = 1;
11265 record_buf[0] = reg_dest;
11266 record_buf[1] = ARM_PS_REGNUM;
11267 arm_insn_r->reg_rec_count = 2;
11270 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11271 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11272 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11273 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11275 /* Handle MSR insn. */
11276 if (9 == arm_insn_r->opcode)
11278 /* CSPR is going to be changed. */
11279 record_buf[0] = ARM_PS_REGNUM;
11280 arm_insn_r->reg_rec_count = 1;
11284 /* SPSR is going to be changed. */
11285 /* How to read SPSR value? */
11286 printf_unfiltered (_("Process record does not support instruction "
11287 "0x%0x at address %s.\n"),
11288 arm_insn_r->arm_insn,
11289 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11293 else if (9 == arm_insn_r->decode
11294 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11295 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11297 /* Handling SWP, SWPB. */
11298 /* These insn, changes register and memory as well. */
11299 /* SWP or SWPB insn. */
11301 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11302 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11303 /* SWP insn ?, swaps word. */
11304 if (8 == arm_insn_r->opcode)
11306 record_buf_mem[0] = 4;
11310 /* SWPB insn, swaps only byte. */
11311 record_buf_mem[0] = 1;
11313 record_buf_mem[1] = u_regval[0];
11314 arm_insn_r->mem_rec_count = 1;
11315 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11316 arm_insn_r->reg_rec_count = 1;
11318 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11319 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11321 /* Handle BLX, branch and link/exchange. */
11322 if (9 == arm_insn_r->opcode)
11324 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11325 and R14 stores the return address. */
11326 record_buf[0] = ARM_PS_REGNUM;
11327 record_buf[1] = ARM_LR_REGNUM;
11328 arm_insn_r->reg_rec_count = 2;
11331 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11333 /* Handle enhanced software breakpoint insn, BKPT. */
11334 /* CPSR is changed to be executed in ARM state, disabling normal
11335 interrupts, entering abort mode. */
11336 /* According to high vector configuration PC is set. */
11337 /* user hit breakpoint and type reverse, in
11338 that case, we need to go back with previous CPSR and
11339 Program Counter. */
11340 record_buf[0] = ARM_PS_REGNUM;
11341 record_buf[1] = ARM_LR_REGNUM;
11342 arm_insn_r->reg_rec_count = 2;
11344 /* Save SPSR also; how? */
11345 printf_unfiltered (_("Process record does not support instruction "
11346 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11347 paddress (arm_insn_r->gdbarch,
11348 arm_insn_r->this_addr));
11351 else if (11 == arm_insn_r->decode
11352 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11354 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11356 /* Handle str(x) insn */
11357 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11360 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11361 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11363 /* Handle BX, branch and link/exchange. */
11364 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11365 record_buf[0] = ARM_PS_REGNUM;
11366 arm_insn_r->reg_rec_count = 1;
11368 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11369 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11370 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11372 /* Count leading zeros: CLZ. */
11373 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11374 arm_insn_r->reg_rec_count = 1;
11376 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11377 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11378 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11379 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11382 /* Handle MRS insn. */
11383 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11384 arm_insn_r->reg_rec_count = 1;
11386 else if (arm_insn_r->opcode <= 15)
11388 /* Normal data processing insns. */
11389 /* Out of 11 shifter operands mode, all the insn modifies destination
11390 register, which is specified by 13-16 decode. */
11391 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11392 record_buf[1] = ARM_PS_REGNUM;
11393 arm_insn_r->reg_rec_count = 2;
11400 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11401 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11405 /* Handling opcode 001 insns. */
11408 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11410 uint32_t record_buf[8], record_buf_mem[8];
11412 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11413 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11415 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11416 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11417 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11420 /* Handle MSR insn. */
11421 if (9 == arm_insn_r->opcode)
11423 /* CSPR is going to be changed. */
11424 record_buf[0] = ARM_PS_REGNUM;
11425 arm_insn_r->reg_rec_count = 1;
11429 /* SPSR is going to be changed. */
11432 else if (arm_insn_r->opcode <= 15)
11434 /* Normal data processing insns. */
11435 /* Out of 11 shifter operands mode, all the insn modifies destination
11436 register, which is specified by 13-16 decode. */
11437 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11438 record_buf[1] = ARM_PS_REGNUM;
11439 arm_insn_r->reg_rec_count = 2;
11446 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11447 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11451 /* Handling opcode 010 insns. */
11454 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11456 struct regcache *reg_cache = arm_insn_r->regcache;
11458 uint32_t reg_src1 = 0 , reg_dest = 0;
11459 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11460 uint32_t record_buf[8], record_buf_mem[8];
11462 ULONGEST u_regval = 0;
11464 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11465 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11467 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11469 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11470 /* LDR insn has a capability to do branching, if
11471 MOV LR, PC is precedded by LDR insn having Rn as R15
11472 in that case, it emulates branch and link insn, and hence we
11473 need to save CSPR and PC as well. */
11474 if (ARM_PC_REGNUM != reg_dest)
11476 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11477 arm_insn_r->reg_rec_count = 1;
11481 record_buf[0] = reg_dest;
11482 record_buf[1] = ARM_PS_REGNUM;
11483 arm_insn_r->reg_rec_count = 2;
11488 /* Store, immediate offset, immediate pre-indexed,
11489 immediate post-indexed. */
11490 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11491 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11492 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11494 if (bit (arm_insn_r->arm_insn, 23))
11496 tgt_mem_addr = u_regval + offset_12;
11500 tgt_mem_addr = u_regval - offset_12;
11503 switch (arm_insn_r->opcode)
11517 record_buf_mem[0] = 4;
11532 record_buf_mem[0] = 1;
11536 gdb_assert_not_reached ("no decoding pattern found");
11539 record_buf_mem[1] = tgt_mem_addr;
11540 arm_insn_r->mem_rec_count = 1;
11542 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11543 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11544 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11545 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11546 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11547 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11550 /* We are handling pre-indexed mode; post-indexed mode;
11551 where Rn is going to be changed. */
11552 record_buf[0] = reg_src1;
11553 arm_insn_r->reg_rec_count = 1;
11557 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11558 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11562 /* Handling opcode 011 insns. */
11565 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11567 struct regcache *reg_cache = arm_insn_r->regcache;
11569 uint32_t shift_imm = 0;
11570 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11571 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11572 uint32_t record_buf[8], record_buf_mem[8];
11575 ULONGEST u_regval[2];
11577 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11578 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11580 /* Handle enhanced store insns and LDRD DSP insn,
11581 order begins according to addressing modes for store insns
11585 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11587 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11588 /* LDR insn has a capability to do branching, if
11589 MOV LR, PC is precedded by LDR insn having Rn as R15
11590 in that case, it emulates branch and link insn, and hence we
11591 need to save CSPR and PC as well. */
11592 if (15 != reg_dest)
11594 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11595 arm_insn_r->reg_rec_count = 1;
11599 record_buf[0] = reg_dest;
11600 record_buf[1] = ARM_PS_REGNUM;
11601 arm_insn_r->reg_rec_count = 2;
11606 if (! bits (arm_insn_r->arm_insn, 4, 11))
11608 /* Store insn, register offset and register pre-indexed,
11609 register post-indexed. */
11611 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11613 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11614 regcache_raw_read_unsigned (reg_cache, reg_src1
11616 regcache_raw_read_unsigned (reg_cache, reg_src2
11618 if (15 == reg_src2)
11620 /* If R15 was used as Rn, hence current PC+8. */
11621 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11622 u_regval[0] = u_regval[0] + 8;
11624 /* Calculate target store address, Rn +/- Rm, register offset. */
11626 if (bit (arm_insn_r->arm_insn, 23))
11628 tgt_mem_addr = u_regval[0] + u_regval[1];
11632 tgt_mem_addr = u_regval[1] - u_regval[0];
11635 switch (arm_insn_r->opcode)
11649 record_buf_mem[0] = 4;
11664 record_buf_mem[0] = 1;
11668 gdb_assert_not_reached ("no decoding pattern found");
11671 record_buf_mem[1] = tgt_mem_addr;
11672 arm_insn_r->mem_rec_count = 1;
11674 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11675 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11676 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11677 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11678 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11679 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11682 /* Rn is going to be changed in pre-indexed mode and
11683 post-indexed mode as well. */
11684 record_buf[0] = reg_src2;
11685 arm_insn_r->reg_rec_count = 1;
11690 /* Store insn, scaled register offset; scaled pre-indexed. */
11691 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11693 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11695 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11696 /* Get shift_imm. */
11697 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11698 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11699 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11700 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11701 /* Offset_12 used as shift. */
11705 /* Offset_12 used as index. */
11706 offset_12 = u_regval[0] << shift_imm;
11710 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11716 if (bit (u_regval[0], 31))
11718 offset_12 = 0xFFFFFFFF;
11727 /* This is arithmetic shift. */
11728 offset_12 = s_word >> shift_imm;
11735 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11737 /* Get C flag value and shift it by 31. */
11738 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11739 | (u_regval[0]) >> 1);
11743 offset_12 = (u_regval[0] >> shift_imm) \
11745 (sizeof(uint32_t) - shift_imm));
11750 gdb_assert_not_reached ("no decoding pattern found");
11754 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11756 if (bit (arm_insn_r->arm_insn, 23))
11758 tgt_mem_addr = u_regval[1] + offset_12;
11762 tgt_mem_addr = u_regval[1] - offset_12;
11765 switch (arm_insn_r->opcode)
11779 record_buf_mem[0] = 4;
11794 record_buf_mem[0] = 1;
11798 gdb_assert_not_reached ("no decoding pattern found");
11801 record_buf_mem[1] = tgt_mem_addr;
11802 arm_insn_r->mem_rec_count = 1;
11804 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11805 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11806 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11807 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11808 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11809 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11812 /* Rn is going to be changed in register scaled pre-indexed
11813 mode,and scaled post indexed mode. */
11814 record_buf[0] = reg_src2;
11815 arm_insn_r->reg_rec_count = 1;
11820 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11821 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11825 /* Handling opcode 100 insns. */
11828 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11830 struct regcache *reg_cache = arm_insn_r->regcache;
11832 uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0;
11833 uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0;
11834 uint32_t start_address = 0, index = 0;
11835 uint32_t record_buf[24], record_buf_mem[48];
11837 ULONGEST u_regval[2] = {0};
11839 /* This mode is exclusively for load and store multiple. */
11840 /* Handle incremenrt after/before and decrment after.before mode;
11841 Rn is changing depending on W bit, but as of now we store Rn too
11842 without optimization. */
11844 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11846 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11848 if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22))
11850 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11855 register_bits = bits (arm_insn_r->arm_insn, 0, 14);
11859 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11860 while (register_bits)
11862 if (register_bits & 0x00000001)
11863 record_buf[index++] = register_count;
11864 register_bits = register_bits >> 1;
11868 /* Extra space for Base Register and CPSR; wihtout optimization. */
11869 record_buf[index++] = reg_src1;
11870 record_buf[index++] = ARM_PS_REGNUM;
11871 arm_insn_r->reg_rec_count = index;
11875 /* It handles both STM(1) and STM(2). */
11876 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11878 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11880 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11881 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11882 while (register_bits)
11884 if (register_bits & 0x00000001)
11886 register_bits = register_bits >> 1;
11891 /* Decrement after. */
11893 start_address = (u_regval[0]) - (register_count * 4) + 4;
11894 arm_insn_r->mem_rec_count = register_count;
11895 while (register_count)
11897 record_buf_mem[(register_count * 2) - 1] = start_address;
11898 record_buf_mem[(register_count * 2) - 2] = 4;
11899 start_address = start_address + 4;
11904 /* Increment after. */
11906 start_address = u_regval[0];
11907 arm_insn_r->mem_rec_count = register_count;
11908 while (register_count)
11910 record_buf_mem[(register_count * 2) - 1] = start_address;
11911 record_buf_mem[(register_count * 2) - 2] = 4;
11912 start_address = start_address + 4;
11917 /* Decrement before. */
11920 start_address = (u_regval[0]) - (register_count * 4);
11921 arm_insn_r->mem_rec_count = register_count;
11922 while (register_count)
11924 record_buf_mem[(register_count * 2) - 1] = start_address;
11925 record_buf_mem[(register_count * 2) - 2] = 4;
11926 start_address = start_address + 4;
11931 /* Increment before. */
11933 start_address = u_regval[0] + 4;
11934 arm_insn_r->mem_rec_count = register_count;
11935 while (register_count)
11937 record_buf_mem[(register_count * 2) - 1] = start_address;
11938 record_buf_mem[(register_count * 2) - 2] = 4;
11939 start_address = start_address + 4;
11945 gdb_assert_not_reached ("no decoding pattern found");
11949 /* Base register also changes; based on condition and W bit. */
11950 /* We save it anyway without optimization. */
11951 record_buf[0] = reg_src1;
11952 arm_insn_r->reg_rec_count = 1;
11955 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11956 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11960 /* Handling opcode 101 insns. */
11963 arm_record_b_bl (insn_decode_record *arm_insn_r)
11965 uint32_t record_buf[8];
11967 /* Handle B, BL, BLX(1) insns. */
11968 /* B simply branches so we do nothing here. */
11969 /* Note: BLX(1) doesnt fall here but instead it falls into
11970 extension space. */
11971 if (bit (arm_insn_r->arm_insn, 24))
11973 record_buf[0] = ARM_LR_REGNUM;
11974 arm_insn_r->reg_rec_count = 1;
11977 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11982 /* Handling opcode 110 insns. */
11985 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
11987 printf_unfiltered (_("Process record does not support instruction "
11988 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11989 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11994 /* Handling opcode 111 insns. */
11997 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11999 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
12000 struct regcache *reg_cache = arm_insn_r->regcache;
12001 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12002 ULONGEST u_regval = 0;
12004 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
12006 /* Handle arm SWI/SVC system call instructions. */
12007 if (15 == arm_insn_r->opcode)
12009 if (tdep->arm_syscall_record != NULL)
12011 ULONGEST svc_operand, svc_number;
12013 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
12015 if (svc_operand) /* OABI. */
12016 svc_number = svc_operand - 0x900000;
12018 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
12020 ret = tdep->arm_syscall_record (reg_cache, svc_number);
12024 printf_unfiltered (_("no syscall record support\n"));
12030 arm_record_unsupported_insn (arm_insn_r);
12037 /* Handling opcode 000 insns. */
12040 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
12042 uint32_t record_buf[8];
12043 uint32_t reg_src1 = 0;
12045 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12047 record_buf[0] = ARM_PS_REGNUM;
12048 record_buf[1] = reg_src1;
12049 thumb_insn_r->reg_rec_count = 2;
12051 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12057 /* Handling opcode 001 insns. */
12060 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
12062 uint32_t record_buf[8];
12063 uint32_t reg_src1 = 0;
12065 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12067 record_buf[0] = ARM_PS_REGNUM;
12068 record_buf[1] = reg_src1;
12069 thumb_insn_r->reg_rec_count = 2;
12071 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12076 /* Handling opcode 010 insns. */
12079 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
12081 struct regcache *reg_cache = thumb_insn_r->regcache;
12082 uint32_t record_buf[8], record_buf_mem[8];
12084 uint32_t reg_src1 = 0, reg_src2 = 0;
12085 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12087 ULONGEST u_regval[2] = {0};
12089 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
12091 if (bit (thumb_insn_r->arm_insn, 12))
12093 /* Handle load/store register offset. */
12094 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
12095 if (opcode2 >= 12 && opcode2 <= 15)
12097 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12098 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
12099 record_buf[0] = reg_src1;
12100 thumb_insn_r->reg_rec_count = 1;
12102 else if (opcode2 >= 8 && opcode2 <= 10)
12104 /* STR(2), STRB(2), STRH(2) . */
12105 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12106 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
12107 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
12108 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
12110 record_buf_mem[0] = 4; /* STR (2). */
12111 else if (10 == opcode2)
12112 record_buf_mem[0] = 1; /* STRB (2). */
12113 else if (9 == opcode2)
12114 record_buf_mem[0] = 2; /* STRH (2). */
12115 record_buf_mem[1] = u_regval[0] + u_regval[1];
12116 thumb_insn_r->mem_rec_count = 1;
12119 else if (bit (thumb_insn_r->arm_insn, 11))
12121 /* Handle load from literal pool. */
12123 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12124 record_buf[0] = reg_src1;
12125 thumb_insn_r->reg_rec_count = 1;
12129 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
12130 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
12131 if ((3 == opcode2) && (!opcode3))
12133 /* Branch with exchange. */
12134 record_buf[0] = ARM_PS_REGNUM;
12135 thumb_insn_r->reg_rec_count = 1;
12139 /* Format 8; special data processing insns. */
12140 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12141 record_buf[0] = ARM_PS_REGNUM;
12142 record_buf[1] = reg_src1;
12143 thumb_insn_r->reg_rec_count = 2;
12148 /* Format 5; data processing insns. */
12149 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12150 if (bit (thumb_insn_r->arm_insn, 7))
12152 reg_src1 = reg_src1 + 8;
12154 record_buf[0] = ARM_PS_REGNUM;
12155 record_buf[1] = reg_src1;
12156 thumb_insn_r->reg_rec_count = 2;
12159 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12160 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12166 /* Handling opcode 001 insns. */
12169 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
12171 struct regcache *reg_cache = thumb_insn_r->regcache;
12172 uint32_t record_buf[8], record_buf_mem[8];
12174 uint32_t reg_src1 = 0;
12175 uint32_t opcode = 0, immed_5 = 0;
12177 ULONGEST u_regval = 0;
12179 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12184 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12185 record_buf[0] = reg_src1;
12186 thumb_insn_r->reg_rec_count = 1;
12191 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12192 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12193 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12194 record_buf_mem[0] = 4;
12195 record_buf_mem[1] = u_regval + (immed_5 * 4);
12196 thumb_insn_r->mem_rec_count = 1;
12199 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12200 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12206 /* Handling opcode 100 insns. */
12209 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12211 struct regcache *reg_cache = thumb_insn_r->regcache;
12212 uint32_t record_buf[8], record_buf_mem[8];
12214 uint32_t reg_src1 = 0;
12215 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12217 ULONGEST u_regval = 0;
12219 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12224 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12225 record_buf[0] = reg_src1;
12226 thumb_insn_r->reg_rec_count = 1;
12228 else if (1 == opcode)
12231 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12232 record_buf[0] = reg_src1;
12233 thumb_insn_r->reg_rec_count = 1;
12235 else if (2 == opcode)
12238 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12239 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12240 record_buf_mem[0] = 4;
12241 record_buf_mem[1] = u_regval + (immed_8 * 4);
12242 thumb_insn_r->mem_rec_count = 1;
12244 else if (0 == opcode)
12247 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12248 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12249 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12250 record_buf_mem[0] = 2;
12251 record_buf_mem[1] = u_regval + (immed_5 * 2);
12252 thumb_insn_r->mem_rec_count = 1;
12255 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12256 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12262 /* Handling opcode 101 insns. */
12265 thumb_record_misc (insn_decode_record *thumb_insn_r)
12267 struct regcache *reg_cache = thumb_insn_r->regcache;
12269 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12270 uint32_t register_bits = 0, register_count = 0;
12271 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12272 uint32_t record_buf[24], record_buf_mem[48];
12275 ULONGEST u_regval = 0;
12277 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12278 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12279 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12284 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12285 while (register_bits)
12287 if (register_bits & 0x00000001)
12288 record_buf[index++] = register_count;
12289 register_bits = register_bits >> 1;
12292 record_buf[index++] = ARM_PS_REGNUM;
12293 record_buf[index++] = ARM_SP_REGNUM;
12294 thumb_insn_r->reg_rec_count = index;
12296 else if (10 == opcode2)
12299 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12300 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12301 while (register_bits)
12303 if (register_bits & 0x00000001)
12305 register_bits = register_bits >> 1;
12307 start_address = u_regval - \
12308 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12309 thumb_insn_r->mem_rec_count = register_count;
12310 while (register_count)
12312 record_buf_mem[(register_count * 2) - 1] = start_address;
12313 record_buf_mem[(register_count * 2) - 2] = 4;
12314 start_address = start_address + 4;
12317 record_buf[0] = ARM_SP_REGNUM;
12318 thumb_insn_r->reg_rec_count = 1;
12320 else if (0x1E == opcode1)
12323 /* Handle enhanced software breakpoint insn, BKPT. */
12324 /* CPSR is changed to be executed in ARM state, disabling normal
12325 interrupts, entering abort mode. */
12326 /* According to high vector configuration PC is set. */
12327 /* User hits breakpoint and type reverse, in that case, we need to go back with
12328 previous CPSR and Program Counter. */
12329 record_buf[0] = ARM_PS_REGNUM;
12330 record_buf[1] = ARM_LR_REGNUM;
12331 thumb_insn_r->reg_rec_count = 2;
12332 /* We need to save SPSR value, which is not yet done. */
12333 printf_unfiltered (_("Process record does not support instruction "
12334 "0x%0x at address %s.\n"),
12335 thumb_insn_r->arm_insn,
12336 paddress (thumb_insn_r->gdbarch,
12337 thumb_insn_r->this_addr));
12340 else if ((0 == opcode) || (1 == opcode))
12342 /* ADD(5), ADD(6). */
12343 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12344 record_buf[0] = reg_src1;
12345 thumb_insn_r->reg_rec_count = 1;
12347 else if (2 == opcode)
12349 /* ADD(7), SUB(4). */
12350 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12351 record_buf[0] = ARM_SP_REGNUM;
12352 thumb_insn_r->reg_rec_count = 1;
12355 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12356 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12362 /* Handling opcode 110 insns. */
12365 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12367 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12368 struct regcache *reg_cache = thumb_insn_r->regcache;
12370 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12371 uint32_t reg_src1 = 0;
12372 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12373 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12374 uint32_t record_buf[24], record_buf_mem[48];
12376 ULONGEST u_regval = 0;
12378 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12379 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12385 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12387 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12388 while (register_bits)
12390 if (register_bits & 0x00000001)
12391 record_buf[index++] = register_count;
12392 register_bits = register_bits >> 1;
12395 record_buf[index++] = reg_src1;
12396 thumb_insn_r->reg_rec_count = index;
12398 else if (0 == opcode2)
12400 /* It handles both STMIA. */
12401 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12403 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12404 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12405 while (register_bits)
12407 if (register_bits & 0x00000001)
12409 register_bits = register_bits >> 1;
12411 start_address = u_regval;
12412 thumb_insn_r->mem_rec_count = register_count;
12413 while (register_count)
12415 record_buf_mem[(register_count * 2) - 1] = start_address;
12416 record_buf_mem[(register_count * 2) - 2] = 4;
12417 start_address = start_address + 4;
12421 else if (0x1F == opcode1)
12423 /* Handle arm syscall insn. */
12424 if (tdep->arm_syscall_record != NULL)
12426 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
12427 ret = tdep->arm_syscall_record (reg_cache, u_regval);
12431 printf_unfiltered (_("no syscall record support\n"));
12436 /* B (1), conditional branch is automatically taken care in process_record,
12437 as PC is saved there. */
12439 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12440 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12446 /* Handling opcode 111 insns. */
12449 thumb_record_branch (insn_decode_record *thumb_insn_r)
12451 uint32_t record_buf[8];
12452 uint32_t bits_h = 0;
12454 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12456 if (2 == bits_h || 3 == bits_h)
12459 record_buf[0] = ARM_LR_REGNUM;
12460 thumb_insn_r->reg_rec_count = 1;
12462 else if (1 == bits_h)
12465 record_buf[0] = ARM_PS_REGNUM;
12466 record_buf[1] = ARM_LR_REGNUM;
12467 thumb_insn_r->reg_rec_count = 2;
12470 /* B(2) is automatically taken care in process_record, as PC is
12473 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12478 /* Handler for thumb2 load/store multiple instructions. */
12481 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
12483 struct regcache *reg_cache = thumb2_insn_r->regcache;
12485 uint32_t reg_rn, op;
12486 uint32_t register_bits = 0, register_count = 0;
12487 uint32_t index = 0, start_address = 0;
12488 uint32_t record_buf[24], record_buf_mem[48];
12490 ULONGEST u_regval = 0;
12492 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12493 op = bits (thumb2_insn_r->arm_insn, 23, 24);
12495 if (0 == op || 3 == op)
12497 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12499 /* Handle RFE instruction. */
12500 record_buf[0] = ARM_PS_REGNUM;
12501 thumb2_insn_r->reg_rec_count = 1;
12505 /* Handle SRS instruction after reading banked SP. */
12506 return arm_record_unsupported_insn (thumb2_insn_r);
12509 else if (1 == op || 2 == op)
12511 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12513 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12514 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12515 while (register_bits)
12517 if (register_bits & 0x00000001)
12518 record_buf[index++] = register_count;
12521 register_bits = register_bits >> 1;
12523 record_buf[index++] = reg_rn;
12524 record_buf[index++] = ARM_PS_REGNUM;
12525 thumb2_insn_r->reg_rec_count = index;
12529 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12530 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12531 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12532 while (register_bits)
12534 if (register_bits & 0x00000001)
12537 register_bits = register_bits >> 1;
12542 /* Start address calculation for LDMDB/LDMEA. */
12543 start_address = u_regval;
12547 /* Start address calculation for LDMDB/LDMEA. */
12548 start_address = u_regval - register_count * 4;
12551 thumb2_insn_r->mem_rec_count = register_count;
12552 while (register_count)
12554 record_buf_mem[register_count * 2 - 1] = start_address;
12555 record_buf_mem[register_count * 2 - 2] = 4;
12556 start_address = start_address + 4;
12559 record_buf[0] = reg_rn;
12560 record_buf[1] = ARM_PS_REGNUM;
12561 thumb2_insn_r->reg_rec_count = 2;
12565 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12567 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12569 return ARM_RECORD_SUCCESS;
12572 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12576 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
12578 struct regcache *reg_cache = thumb2_insn_r->regcache;
12580 uint32_t reg_rd, reg_rn, offset_imm;
12581 uint32_t reg_dest1, reg_dest2;
12582 uint32_t address, offset_addr;
12583 uint32_t record_buf[8], record_buf_mem[8];
12584 uint32_t op1, op2, op3;
12587 ULONGEST u_regval[2];
12589 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
12590 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
12591 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
12593 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12595 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
12597 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
12598 record_buf[0] = reg_dest1;
12599 record_buf[1] = ARM_PS_REGNUM;
12600 thumb2_insn_r->reg_rec_count = 2;
12603 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
12605 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12606 record_buf[2] = reg_dest2;
12607 thumb2_insn_r->reg_rec_count = 3;
12612 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12613 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12615 if (0 == op1 && 0 == op2)
12617 /* Handle STREX. */
12618 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12619 address = u_regval[0] + (offset_imm * 4);
12620 record_buf_mem[0] = 4;
12621 record_buf_mem[1] = address;
12622 thumb2_insn_r->mem_rec_count = 1;
12623 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12624 record_buf[0] = reg_rd;
12625 thumb2_insn_r->reg_rec_count = 1;
12627 else if (1 == op1 && 0 == op2)
12629 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12630 record_buf[0] = reg_rd;
12631 thumb2_insn_r->reg_rec_count = 1;
12632 address = u_regval[0];
12633 record_buf_mem[1] = address;
12637 /* Handle STREXB. */
12638 record_buf_mem[0] = 1;
12639 thumb2_insn_r->mem_rec_count = 1;
12643 /* Handle STREXH. */
12644 record_buf_mem[0] = 2 ;
12645 thumb2_insn_r->mem_rec_count = 1;
12649 /* Handle STREXD. */
12650 address = u_regval[0];
12651 record_buf_mem[0] = 4;
12652 record_buf_mem[2] = 4;
12653 record_buf_mem[3] = address + 4;
12654 thumb2_insn_r->mem_rec_count = 2;
12659 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12661 if (bit (thumb2_insn_r->arm_insn, 24))
12663 if (bit (thumb2_insn_r->arm_insn, 23))
12664 offset_addr = u_regval[0] + (offset_imm * 4);
12666 offset_addr = u_regval[0] - (offset_imm * 4);
12668 address = offset_addr;
12671 address = u_regval[0];
12673 record_buf_mem[0] = 4;
12674 record_buf_mem[1] = address;
12675 record_buf_mem[2] = 4;
12676 record_buf_mem[3] = address + 4;
12677 thumb2_insn_r->mem_rec_count = 2;
12678 record_buf[0] = reg_rn;
12679 thumb2_insn_r->reg_rec_count = 1;
12683 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12685 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12687 return ARM_RECORD_SUCCESS;
12690 /* Handler for thumb2 data processing (shift register and modified immediate)
12694 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
12696 uint32_t reg_rd, op;
12697 uint32_t record_buf[8];
12699 op = bits (thumb2_insn_r->arm_insn, 21, 24);
12700 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12702 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
12704 record_buf[0] = ARM_PS_REGNUM;
12705 thumb2_insn_r->reg_rec_count = 1;
12709 record_buf[0] = reg_rd;
12710 record_buf[1] = ARM_PS_REGNUM;
12711 thumb2_insn_r->reg_rec_count = 2;
12714 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12716 return ARM_RECORD_SUCCESS;
12719 /* Generic handler for thumb2 instructions which effect destination and PS
12723 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
12726 uint32_t record_buf[8];
12728 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12730 record_buf[0] = reg_rd;
12731 record_buf[1] = ARM_PS_REGNUM;
12732 thumb2_insn_r->reg_rec_count = 2;
12734 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12736 return ARM_RECORD_SUCCESS;
12739 /* Handler for thumb2 branch and miscellaneous control instructions. */
12742 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
12744 uint32_t op, op1, op2;
12745 uint32_t record_buf[8];
12747 op = bits (thumb2_insn_r->arm_insn, 20, 26);
12748 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
12749 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12751 /* Handle MSR insn. */
12752 if (!(op1 & 0x2) && 0x38 == op)
12756 /* CPSR is going to be changed. */
12757 record_buf[0] = ARM_PS_REGNUM;
12758 thumb2_insn_r->reg_rec_count = 1;
12762 arm_record_unsupported_insn(thumb2_insn_r);
12766 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
12769 record_buf[0] = ARM_PS_REGNUM;
12770 record_buf[1] = ARM_LR_REGNUM;
12771 thumb2_insn_r->reg_rec_count = 2;
12774 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12776 return ARM_RECORD_SUCCESS;
12779 /* Handler for thumb2 store single data item instructions. */
12782 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
12784 struct regcache *reg_cache = thumb2_insn_r->regcache;
12786 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
12787 uint32_t address, offset_addr;
12788 uint32_t record_buf[8], record_buf_mem[8];
12791 ULONGEST u_regval[2];
12793 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
12794 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
12795 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12796 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12798 if (bit (thumb2_insn_r->arm_insn, 23))
12801 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
12802 offset_addr = u_regval[0] + offset_imm;
12803 address = offset_addr;
12808 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
12810 /* Handle STRB (register). */
12811 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
12812 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
12813 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
12814 offset_addr = u_regval[1] << shift_imm;
12815 address = u_regval[0] + offset_addr;
12819 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12820 if (bit (thumb2_insn_r->arm_insn, 10))
12822 if (bit (thumb2_insn_r->arm_insn, 9))
12823 offset_addr = u_regval[0] + offset_imm;
12825 offset_addr = u_regval[0] - offset_imm;
12827 address = offset_addr;
12830 address = u_regval[0];
12836 /* Store byte instructions. */
12839 record_buf_mem[0] = 1;
12841 /* Store half word instructions. */
12844 record_buf_mem[0] = 2;
12846 /* Store word instructions. */
12849 record_buf_mem[0] = 4;
12853 gdb_assert_not_reached ("no decoding pattern found");
12857 record_buf_mem[1] = address;
12858 thumb2_insn_r->mem_rec_count = 1;
12859 record_buf[0] = reg_rn;
12860 thumb2_insn_r->reg_rec_count = 1;
12862 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12864 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12866 return ARM_RECORD_SUCCESS;
12869 /* Handler for thumb2 load memory hints instructions. */
12872 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
12874 uint32_t record_buf[8];
12875 uint32_t reg_rt, reg_rn;
12877 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
12878 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12880 if (ARM_PC_REGNUM != reg_rt)
12882 record_buf[0] = reg_rt;
12883 record_buf[1] = reg_rn;
12884 record_buf[2] = ARM_PS_REGNUM;
12885 thumb2_insn_r->reg_rec_count = 3;
12887 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12889 return ARM_RECORD_SUCCESS;
12892 return ARM_RECORD_FAILURE;
12895 /* Handler for thumb2 load word instructions. */
12898 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
12900 uint32_t opcode1 = 0, opcode2 = 0;
12901 uint32_t record_buf[8];
12903 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
12904 record_buf[1] = ARM_PS_REGNUM;
12905 thumb2_insn_r->reg_rec_count = 2;
12907 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12909 return ARM_RECORD_SUCCESS;
12912 /* Handler for thumb2 long multiply, long multiply accumulate, and
12913 divide instructions. */
12916 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
12918 uint32_t opcode1 = 0, opcode2 = 0;
12919 uint32_t record_buf[8];
12920 uint32_t reg_src1 = 0;
12922 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
12923 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
12925 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
12927 /* Handle SMULL, UMULL, SMULAL. */
12928 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12929 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12930 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12931 record_buf[2] = ARM_PS_REGNUM;
12932 thumb2_insn_r->reg_rec_count = 3;
12934 else if (1 == opcode1 || 3 == opcode2)
12936 /* Handle SDIV and UDIV. */
12937 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12938 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12939 record_buf[2] = ARM_PS_REGNUM;
12940 thumb2_insn_r->reg_rec_count = 3;
12943 return ARM_RECORD_FAILURE;
12945 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12947 return ARM_RECORD_SUCCESS;
12950 /* Decodes thumb2 instruction type and invokes its record handler. */
12952 static unsigned int
12953 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
12955 uint32_t op, op1, op2;
12957 op = bit (thumb2_insn_r->arm_insn, 15);
12958 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
12959 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
12963 if (!(op2 & 0x64 ))
12965 /* Load/store multiple instruction. */
12966 return thumb2_record_ld_st_multiple (thumb2_insn_r);
12968 else if (!((op2 & 0x64) ^ 0x04))
12970 /* Load/store (dual/exclusive) and table branch instruction. */
12971 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
12973 else if (!((op2 & 0x20) ^ 0x20))
12975 /* Data-processing (shifted register). */
12976 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12978 else if (op2 & 0x40)
12980 /* Co-processor instructions. */
12981 arm_record_unsupported_insn (thumb2_insn_r);
12984 else if (op1 == 0x02)
12988 /* Branches and miscellaneous control instructions. */
12989 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
12991 else if (op2 & 0x20)
12993 /* Data-processing (plain binary immediate) instruction. */
12994 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12998 /* Data-processing (modified immediate). */
12999 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
13002 else if (op1 == 0x03)
13004 if (!(op2 & 0x71 ))
13006 /* Store single data item. */
13007 return thumb2_record_str_single_data (thumb2_insn_r);
13009 else if (!((op2 & 0x71) ^ 0x10))
13011 /* Advanced SIMD or structure load/store instructions. */
13012 return arm_record_unsupported_insn (thumb2_insn_r);
13014 else if (!((op2 & 0x67) ^ 0x01))
13016 /* Load byte, memory hints instruction. */
13017 return thumb2_record_ld_mem_hints (thumb2_insn_r);
13019 else if (!((op2 & 0x67) ^ 0x03))
13021 /* Load halfword, memory hints instruction. */
13022 return thumb2_record_ld_mem_hints (thumb2_insn_r);
13024 else if (!((op2 & 0x67) ^ 0x05))
13026 /* Load word instruction. */
13027 return thumb2_record_ld_word (thumb2_insn_r);
13029 else if (!((op2 & 0x70) ^ 0x20))
13031 /* Data-processing (register) instruction. */
13032 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13034 else if (!((op2 & 0x78) ^ 0x30))
13036 /* Multiply, multiply accumulate, abs diff instruction. */
13037 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13039 else if (!((op2 & 0x78) ^ 0x38))
13041 /* Long multiply, long multiply accumulate, and divide. */
13042 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
13044 else if (op2 & 0x40)
13046 /* Co-processor instructions. */
13047 return arm_record_unsupported_insn (thumb2_insn_r);
13054 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13055 and positive val on fauilure. */
13058 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
13060 gdb_byte buf[insn_size];
13062 memset (&buf[0], 0, insn_size);
13064 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
13066 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
13068 gdbarch_byte_order (insn_record->gdbarch));
13072 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
13074 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13078 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
13079 uint32_t insn_size)
13082 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13083 static const sti_arm_hdl_fp_t const arm_handle_insn[8] =
13085 arm_record_data_proc_misc_ld_str, /* 000. */
13086 arm_record_data_proc_imm, /* 001. */
13087 arm_record_ld_st_imm_offset, /* 010. */
13088 arm_record_ld_st_reg_offset, /* 011. */
13089 arm_record_ld_st_multiple, /* 100. */
13090 arm_record_b_bl, /* 101. */
13091 arm_record_unsupported_insn, /* 110. */
13092 arm_record_coproc_data_proc /* 111. */
13095 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13096 static const sti_arm_hdl_fp_t const thumb_handle_insn[8] =
13098 thumb_record_shift_add_sub, /* 000. */
13099 thumb_record_add_sub_cmp_mov, /* 001. */
13100 thumb_record_ld_st_reg_offset, /* 010. */
13101 thumb_record_ld_st_imm_offset, /* 011. */
13102 thumb_record_ld_st_stack, /* 100. */
13103 thumb_record_misc, /* 101. */
13104 thumb_record_ldm_stm_swi, /* 110. */
13105 thumb_record_branch /* 111. */
13108 uint32_t ret = 0; /* return value: negative:failure 0:success. */
13109 uint32_t insn_id = 0;
13111 if (extract_arm_insn (arm_record, insn_size))
13115 printf_unfiltered (_("Process record: error reading memory at "
13116 "addr %s len = %d.\n"),
13117 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
13121 else if (ARM_RECORD == record_type)
13123 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
13124 insn_id = bits (arm_record->arm_insn, 25, 27);
13125 ret = arm_record_extension_space (arm_record);
13126 /* If this insn has fallen into extension space
13127 then we need not decode it anymore. */
13128 if (ret != -1 && !INSN_RECORDED(arm_record))
13130 ret = arm_handle_insn[insn_id] (arm_record);
13133 else if (THUMB_RECORD == record_type)
13135 /* As thumb does not have condition codes, we set negative. */
13136 arm_record->cond = -1;
13137 insn_id = bits (arm_record->arm_insn, 13, 15);
13138 ret = thumb_handle_insn[insn_id] (arm_record);
13140 else if (THUMB2_RECORD == record_type)
13142 /* As thumb does not have condition codes, we set negative. */
13143 arm_record->cond = -1;
13145 /* Swap first half of 32bit thumb instruction with second half. */
13146 arm_record->arm_insn
13147 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
13149 insn_id = thumb2_record_decode_insn_handler (arm_record);
13151 if (insn_id != ARM_RECORD_SUCCESS)
13153 arm_record_unsupported_insn (arm_record);
13159 /* Throw assertion. */
13160 gdb_assert_not_reached ("not a valid instruction, could not decode");
13167 /* Cleans up local record registers and memory allocations. */
13170 deallocate_reg_mem (insn_decode_record *record)
13172 xfree (record->arm_regs);
13173 xfree (record->arm_mems);
13177 /* Parse the current instruction and record the values of the registers and
13178 memory that will be changed in current instruction to record_arch_list".
13179 Return -1 if something is wrong. */
13182 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
13183 CORE_ADDR insn_addr)
13186 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
13187 uint32_t no_of_rec = 0;
13188 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
13189 ULONGEST t_bit = 0, insn_id = 0;
13191 ULONGEST u_regval = 0;
13193 insn_decode_record arm_record;
13195 memset (&arm_record, 0, sizeof (insn_decode_record));
13196 arm_record.regcache = regcache;
13197 arm_record.this_addr = insn_addr;
13198 arm_record.gdbarch = gdbarch;
13201 if (record_debug > 1)
13203 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
13205 paddress (gdbarch, arm_record.this_addr));
13208 if (extract_arm_insn (&arm_record, 2))
13212 printf_unfiltered (_("Process record: error reading memory at "
13213 "addr %s len = %d.\n"),
13214 paddress (arm_record.gdbarch,
13215 arm_record.this_addr), 2);
13220 /* Check the insn, whether it is thumb or arm one. */
13222 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
13223 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
13226 if (!(u_regval & t_bit))
13228 /* We are decoding arm insn. */
13229 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
13233 insn_id = bits (arm_record.arm_insn, 11, 15);
13234 /* is it thumb2 insn? */
13235 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13237 ret = decode_insn (&arm_record, THUMB2_RECORD,
13238 THUMB2_INSN_SIZE_BYTES);
13242 /* We are decoding thumb insn. */
13243 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
13249 /* Record registers. */
13250 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
13251 if (arm_record.arm_regs)
13253 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
13255 if (record_full_arch_list_add_reg
13256 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
13260 /* Record memories. */
13261 if (arm_record.arm_mems)
13263 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
13265 if (record_full_arch_list_add_mem
13266 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
13267 arm_record.arm_mems[no_of_rec].len))
13272 if (record_full_arch_list_add_end ())
13277 deallocate_reg_mem (&arm_record);