1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
58 #include "record-full.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data *arm_objfile_data_key;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
92 DEF_VEC_O(arm_mapping_symbol_s);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s) **section_maps;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element *setarmcmdlist = NULL;
101 static struct cmd_list_element *showarmcmdlist = NULL;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
117 static const char *current_fp_model = "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
130 static const char *arm_abi_string = "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings[] =
141 static const char *arm_fallback_mode_string = "auto";
142 static const char *arm_force_mode_string = "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode = -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element *);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat *, const void *,
228 static void convert_to_extended (const struct floatformat *, void *,
231 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
232 struct regcache *regcache,
233 int regnum, gdb_byte *buf);
234 static void arm_neon_quad_write (struct gdbarch *gdbarch,
235 struct regcache *regcache,
236 int regnum, const gdb_byte *buf);
238 static int thumb_insn_size (unsigned short inst1);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg *saved_regs;
260 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
261 CORE_ADDR prologue_start,
262 CORE_ADDR prologue_end,
263 struct arm_prologue_cache *cache);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch *gdbarch)
285 if (gdbarch_tdep (gdbarch)->is_m)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info *frame)
297 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
305 return (cpsr & t_bit) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
312 const struct arm_mapping_symbol *rhs)
314 return lhs->value < rhs->value;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
324 struct obj_section *sec;
326 /* If there are mapping symbols, consult them. */
327 sec = find_pc_section (memaddr);
330 struct arm_per_objfile *data;
331 VEC(arm_mapping_symbol_s) *map;
332 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
336 data = objfile_data (sec->objfile, arm_objfile_data_key);
339 map = data->section_maps[sec->the_bfd_section->index];
340 if (!VEC_empty (arm_mapping_symbol_s, map))
342 struct arm_mapping_symbol *map_sym;
344 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
345 arm_compare_mapping_symbols);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx < VEC_length (arm_mapping_symbol_s, map))
353 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
354 if (map_sym->value == map_key.value)
357 *start = map_sym->value + obj_section_addr (sec);
358 return map_sym->type;
364 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
366 *start = map_sym->value + obj_section_addr (sec);
367 return map_sym->type;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
383 struct bound_minimal_symbol sym;
385 struct displaced_step_closure* dsc
386 = get_displaced_step_closure_by_addr(memaddr);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc->insn_addr,
396 (unsigned long) memaddr);
397 memaddr = dsc->insn_addr;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode != -1)
406 return arm_override_mode;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string, "arm") == 0)
411 if (strcmp (arm_force_mode_string, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch)->is_m)
418 /* If there are mapping symbols, consult them. */
419 type = arm_find_mapping_symbol (memaddr, NULL);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym = lookup_minimal_symbol_by_pc (memaddr);
426 return (MSYMBOL_IS_SPECIAL (sym.minsym));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
450 /* On M-profile devices, do not strip the low bit from EXC_RETURN
451 (the magic exception return address). */
452 if (gdbarch_tdep (gdbarch)->is_m
453 && (val & 0xfffffff0) == 0xfffffff0)
457 return UNMAKE_THUMB_ADDR (val);
459 return (val & 0x03fffffc);
462 /* Return 1 if PC is the start of a compiler helper function which
463 can be safely ignored during prologue skipping. IS_THUMB is true
464 if the function is known to be a Thumb function due to the way it
467 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
469 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
470 struct bound_minimal_symbol msym;
472 msym = lookup_minimal_symbol_by_pc (pc);
473 if (msym.minsym != NULL
474 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
475 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
477 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
479 /* The GNU linker's Thumb call stub to foo is named
481 if (strstr (name, "_from_thumb") != NULL)
484 /* On soft-float targets, __truncdfsf2 is called to convert promoted
485 arguments to their argument types in non-prototyped
487 if (startswith (name, "__truncdfsf2"))
489 if (startswith (name, "__aeabi_d2f"))
492 /* Internal functions related to thread-local storage. */
493 if (startswith (name, "__tls_get_addr"))
495 if (startswith (name, "__aeabi_read_tp"))
500 /* If we run against a stripped glibc, we may be unable to identify
501 special functions by name. Check for one important case,
502 __aeabi_read_tp, by comparing the *code* against the default
503 implementation (this is hand-written ARM assembler in glibc). */
506 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
507 == 0xe3e00a0f /* mov r0, #0xffff0fff */
508 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
509 == 0xe240f01f) /* sub pc, r0, #31 */
516 /* Support routines for instruction parsing. */
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
525 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
526 the first 16-bit of instruction, and INSN2 is the second 16-bit of
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
534 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
535 the 32-bit instruction. */
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
540 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
543 thumb_expand_immediate (unsigned int imm)
545 unsigned int count = imm >> 7;
553 return (imm & 0xff) | ((imm & 0xff) << 16);
555 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
557 return (imm & 0xff) | ((imm & 0xff) << 8)
558 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
561 return (0x80 | (imm & 0x7f)) << (32 - count);
564 /* Return 1 if the 16-bit Thumb instruction INST might change
565 control flow, 0 otherwise. */
568 thumb_instruction_changes_pc (unsigned short inst)
570 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
573 if ((inst & 0xf000) == 0xd000) /* conditional branch */
576 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
579 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
582 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
585 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
591 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
592 might change control flow, 0 otherwise. */
595 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
597 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
599 /* Branches and miscellaneous control instructions. */
601 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
606 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
608 /* SUBS PC, LR, #imm8. */
611 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
613 /* Conditional branch. */
620 if ((inst1 & 0xfe50) == 0xe810)
622 /* Load multiple or RFE. */
624 if (bit (inst1, 7) && !bit (inst1, 8))
630 else if (!bit (inst1, 7) && bit (inst1, 8))
636 else if (bit (inst1, 7) && bit (inst1, 8))
641 else if (!bit (inst1, 7) && !bit (inst1, 8))
650 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
652 /* MOV PC or MOVS PC. */
656 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
659 if (bits (inst1, 0, 3) == 15)
665 if ((inst2 & 0x0fc0) == 0x0000)
671 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
677 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
686 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
687 epilogue, 0 otherwise. */
690 thumb_instruction_restores_sp (unsigned short insn)
692 return (insn == 0x46bd /* mov sp, r7 */
693 || (insn & 0xff80) == 0xb000 /* add sp, imm */
694 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
697 /* Analyze a Thumb prologue, looking for a recognizable stack frame
698 and frame pointer. Scan until we encounter a store that could
699 clobber the stack frame unexpectedly, or an unknown instruction.
700 Return the last address which is definitely safe to skip for an
701 initial breakpoint. */
704 thumb_analyze_prologue (struct gdbarch *gdbarch,
705 CORE_ADDR start, CORE_ADDR limit,
706 struct arm_prologue_cache *cache)
708 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
709 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
712 struct pv_area *stack;
713 struct cleanup *back_to;
715 CORE_ADDR unrecognized_pc = 0;
717 for (i = 0; i < 16; i++)
718 regs[i] = pv_register (i, 0);
719 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
720 back_to = make_cleanup_free_pv_area (stack);
722 while (start < limit)
726 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
728 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
733 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
736 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
737 whether to save LR (R14). */
738 mask = (insn & 0xff) | ((insn & 0x100) << 6);
740 /* Calculate offsets of saved R0-R7 and LR. */
741 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
742 if (mask & (1 << regno))
744 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
746 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
749 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
751 offset = (insn & 0x7f) << 2; /* get scaled offset */
752 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
755 else if (thumb_instruction_restores_sp (insn))
757 /* Don't scan past the epilogue. */
760 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
761 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
763 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
764 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
765 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
767 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
768 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
769 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
771 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
772 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
773 && pv_is_constant (regs[bits (insn, 3, 5)]))
774 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
775 regs[bits (insn, 6, 8)]);
776 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
777 && pv_is_constant (regs[bits (insn, 3, 6)]))
779 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
780 int rm = bits (insn, 3, 6);
781 regs[rd] = pv_add (regs[rd], regs[rm]);
783 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
785 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
786 int src_reg = (insn & 0x78) >> 3;
787 regs[dst_reg] = regs[src_reg];
789 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
791 /* Handle stores to the stack. Normally pushes are used,
792 but with GCC -mtpcs-frame, there may be other stores
793 in the prologue to create the frame. */
794 int regno = (insn >> 8) & 0x7;
797 offset = (insn & 0xff) << 2;
798 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
800 if (pv_area_store_would_trash (stack, addr))
803 pv_area_store (stack, addr, 4, regs[regno]);
805 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
807 int rd = bits (insn, 0, 2);
808 int rn = bits (insn, 3, 5);
811 offset = bits (insn, 6, 10) << 2;
812 addr = pv_add_constant (regs[rn], offset);
814 if (pv_area_store_would_trash (stack, addr))
817 pv_area_store (stack, addr, 4, regs[rd]);
819 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
820 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
821 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
822 /* Ignore stores of argument registers to the stack. */
824 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
825 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
826 /* Ignore block loads from the stack, potentially copying
827 parameters from memory. */
829 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
830 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
831 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
832 /* Similarly ignore single loads from the stack. */
834 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
835 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
836 /* Skip register copies, i.e. saves to another register
837 instead of the stack. */
839 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
840 /* Recognize constant loads; even with small stacks these are necessary
842 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
843 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
845 /* Constant pool loads, for the same reason. */
846 unsigned int constant;
849 loc = start + 4 + bits (insn, 0, 7) * 4;
850 constant = read_memory_unsigned_integer (loc, 4, byte_order);
851 regs[bits (insn, 8, 10)] = pv_constant (constant);
853 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
855 unsigned short inst2;
857 inst2 = read_memory_unsigned_integer (start + 2, 2,
858 byte_order_for_code);
860 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
862 /* BL, BLX. Allow some special function calls when
863 skipping the prologue; GCC generates these before
864 storing arguments to the stack. */
866 int j1, j2, imm1, imm2;
868 imm1 = sbits (insn, 0, 10);
869 imm2 = bits (inst2, 0, 10);
870 j1 = bit (inst2, 13);
871 j2 = bit (inst2, 11);
873 offset = ((imm1 << 12) + (imm2 << 1));
874 offset ^= ((!j2) << 22) | ((!j1) << 23);
876 nextpc = start + 4 + offset;
877 /* For BLX make sure to clear the low bits. */
878 if (bit (inst2, 12) == 0)
879 nextpc = nextpc & 0xfffffffc;
881 if (!skip_prologue_function (gdbarch, nextpc,
882 bit (inst2, 12) != 0))
886 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
888 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
890 pv_t addr = regs[bits (insn, 0, 3)];
893 if (pv_area_store_would_trash (stack, addr))
896 /* Calculate offsets of saved registers. */
897 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
898 if (inst2 & (1 << regno))
900 addr = pv_add_constant (addr, -4);
901 pv_area_store (stack, addr, 4, regs[regno]);
905 regs[bits (insn, 0, 3)] = addr;
908 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
910 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
912 int regno1 = bits (inst2, 12, 15);
913 int regno2 = bits (inst2, 8, 11);
914 pv_t addr = regs[bits (insn, 0, 3)];
916 offset = inst2 & 0xff;
918 addr = pv_add_constant (addr, offset);
920 addr = pv_add_constant (addr, -offset);
922 if (pv_area_store_would_trash (stack, addr))
925 pv_area_store (stack, addr, 4, regs[regno1]);
926 pv_area_store (stack, pv_add_constant (addr, 4),
930 regs[bits (insn, 0, 3)] = addr;
933 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
934 && (inst2 & 0x0c00) == 0x0c00
935 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
937 int regno = bits (inst2, 12, 15);
938 pv_t addr = regs[bits (insn, 0, 3)];
940 offset = inst2 & 0xff;
942 addr = pv_add_constant (addr, offset);
944 addr = pv_add_constant (addr, -offset);
946 if (pv_area_store_would_trash (stack, addr))
949 pv_area_store (stack, addr, 4, regs[regno]);
952 regs[bits (insn, 0, 3)] = addr;
955 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
956 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
958 int regno = bits (inst2, 12, 15);
961 offset = inst2 & 0xfff;
962 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
964 if (pv_area_store_would_trash (stack, addr))
967 pv_area_store (stack, addr, 4, regs[regno]);
970 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
971 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
972 /* Ignore stores of argument registers to the stack. */
975 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
976 && (inst2 & 0x0d00) == 0x0c00
977 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
978 /* Ignore stores of argument registers to the stack. */
981 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
983 && (inst2 & 0x8000) == 0x0000
984 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
985 /* Ignore block loads from the stack, potentially copying
986 parameters from memory. */
989 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
991 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
992 /* Similarly ignore dual loads from the stack. */
995 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
996 && (inst2 & 0x0d00) == 0x0c00
997 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
998 /* Similarly ignore single loads from the stack. */
1001 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1002 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
1003 /* Similarly ignore single loads from the stack. */
1006 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1007 && (inst2 & 0x8000) == 0x0000)
1009 unsigned int imm = ((bits (insn, 10, 10) << 11)
1010 | (bits (inst2, 12, 14) << 8)
1011 | bits (inst2, 0, 7));
1013 regs[bits (inst2, 8, 11)]
1014 = pv_add_constant (regs[bits (insn, 0, 3)],
1015 thumb_expand_immediate (imm));
1018 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1019 && (inst2 & 0x8000) == 0x0000)
1021 unsigned int imm = ((bits (insn, 10, 10) << 11)
1022 | (bits (inst2, 12, 14) << 8)
1023 | bits (inst2, 0, 7));
1025 regs[bits (inst2, 8, 11)]
1026 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1029 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1030 && (inst2 & 0x8000) == 0x0000)
1032 unsigned int imm = ((bits (insn, 10, 10) << 11)
1033 | (bits (inst2, 12, 14) << 8)
1034 | bits (inst2, 0, 7));
1036 regs[bits (inst2, 8, 11)]
1037 = pv_add_constant (regs[bits (insn, 0, 3)],
1038 - (CORE_ADDR) thumb_expand_immediate (imm));
1041 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1042 && (inst2 & 0x8000) == 0x0000)
1044 unsigned int imm = ((bits (insn, 10, 10) << 11)
1045 | (bits (inst2, 12, 14) << 8)
1046 | bits (inst2, 0, 7));
1048 regs[bits (inst2, 8, 11)]
1049 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1052 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1054 unsigned int imm = ((bits (insn, 10, 10) << 11)
1055 | (bits (inst2, 12, 14) << 8)
1056 | bits (inst2, 0, 7));
1058 regs[bits (inst2, 8, 11)]
1059 = pv_constant (thumb_expand_immediate (imm));
1062 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1065 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1067 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1070 else if (insn == 0xea5f /* mov.w Rd,Rm */
1071 && (inst2 & 0xf0f0) == 0)
1073 int dst_reg = (inst2 & 0x0f00) >> 8;
1074 int src_reg = inst2 & 0xf;
1075 regs[dst_reg] = regs[src_reg];
1078 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1080 /* Constant pool loads. */
1081 unsigned int constant;
1084 offset = bits (inst2, 0, 11);
1086 loc = start + 4 + offset;
1088 loc = start + 4 - offset;
1090 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1091 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1094 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1096 /* Constant pool loads. */
1097 unsigned int constant;
1100 offset = bits (inst2, 0, 7) << 2;
1102 loc = start + 4 + offset;
1104 loc = start + 4 - offset;
1106 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1107 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1109 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1110 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1113 else if (thumb2_instruction_changes_pc (insn, inst2))
1115 /* Don't scan past anything that might change control flow. */
1120 /* The optimizer might shove anything into the prologue,
1121 so we just skip what we don't recognize. */
1122 unrecognized_pc = start;
1127 else if (thumb_instruction_changes_pc (insn))
1129 /* Don't scan past anything that might change control flow. */
1134 /* The optimizer might shove anything into the prologue,
1135 so we just skip what we don't recognize. */
1136 unrecognized_pc = start;
1143 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1144 paddress (gdbarch, start));
1146 if (unrecognized_pc == 0)
1147 unrecognized_pc = start;
1151 do_cleanups (back_to);
1152 return unrecognized_pc;
1155 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1157 /* Frame pointer is fp. Frame size is constant. */
1158 cache->framereg = ARM_FP_REGNUM;
1159 cache->framesize = -regs[ARM_FP_REGNUM].k;
1161 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1163 /* Frame pointer is r7. Frame size is constant. */
1164 cache->framereg = THUMB_FP_REGNUM;
1165 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1169 /* Try the stack pointer... this is a bit desperate. */
1170 cache->framereg = ARM_SP_REGNUM;
1171 cache->framesize = -regs[ARM_SP_REGNUM].k;
1174 for (i = 0; i < 16; i++)
1175 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1176 cache->saved_regs[i].addr = offset;
1178 do_cleanups (back_to);
1179 return unrecognized_pc;
1183 /* Try to analyze the instructions starting from PC, which load symbol
1184 __stack_chk_guard. Return the address of instruction after loading this
1185 symbol, set the dest register number to *BASEREG, and set the size of
1186 instructions for loading symbol in OFFSET. Return 0 if instructions are
1190 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1191 unsigned int *destreg, int *offset)
1193 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1194 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1195 unsigned int low, high, address;
1200 unsigned short insn1
1201 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1203 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1205 *destreg = bits (insn1, 8, 10);
1207 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1208 address = read_memory_unsigned_integer (address, 4,
1209 byte_order_for_code);
1211 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1213 unsigned short insn2
1214 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1216 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1219 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1221 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1223 /* movt Rd, #const */
1224 if ((insn1 & 0xfbc0) == 0xf2c0)
1226 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1227 *destreg = bits (insn2, 8, 11);
1229 address = (high << 16 | low);
1236 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1238 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1240 address = bits (insn, 0, 11) + pc + 8;
1241 address = read_memory_unsigned_integer (address, 4,
1242 byte_order_for_code);
1244 *destreg = bits (insn, 12, 15);
1247 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1249 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1252 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1254 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1256 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1257 *destreg = bits (insn, 12, 15);
1259 address = (high << 16 | low);
1267 /* Try to skip a sequence of instructions used for stack protector. If PC
1268 points to the first instruction of this sequence, return the address of
1269 first instruction after this sequence, otherwise, return original PC.
1271 On arm, this sequence of instructions is composed of mainly three steps,
1272 Step 1: load symbol __stack_chk_guard,
1273 Step 2: load from address of __stack_chk_guard,
1274 Step 3: store it to somewhere else.
1276 Usually, instructions on step 2 and step 3 are the same on various ARM
1277 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1278 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1279 instructions in step 1 vary from different ARM architectures. On ARMv7,
1282 movw Rn, #:lower16:__stack_chk_guard
1283 movt Rn, #:upper16:__stack_chk_guard
1290 .word __stack_chk_guard
1292 Since ldr/str is a very popular instruction, we can't use them as
1293 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1294 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1295 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1298 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1300 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1301 unsigned int basereg;
1302 struct bound_minimal_symbol stack_chk_guard;
1304 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1307 /* Try to parse the instructions in Step 1. */
1308 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1313 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1314 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1315 Otherwise, this sequence cannot be for stack protector. */
1316 if (stack_chk_guard.minsym == NULL
1317 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1322 unsigned int destreg;
1324 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1326 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1327 if ((insn & 0xf800) != 0x6800)
1329 if (bits (insn, 3, 5) != basereg)
1331 destreg = bits (insn, 0, 2);
1333 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1334 byte_order_for_code);
1335 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1336 if ((insn & 0xf800) != 0x6000)
1338 if (destreg != bits (insn, 0, 2))
1343 unsigned int destreg;
1345 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1347 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1348 if ((insn & 0x0e500000) != 0x04100000)
1350 if (bits (insn, 16, 19) != basereg)
1352 destreg = bits (insn, 12, 15);
1353 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1354 insn = read_memory_unsigned_integer (pc + offset + 4,
1355 4, byte_order_for_code);
1356 if ((insn & 0x0e500000) != 0x04000000)
1358 if (bits (insn, 12, 15) != destreg)
1361 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1364 return pc + offset + 4;
1366 return pc + offset + 8;
1369 /* Advance the PC across any function entry prologue instructions to
1370 reach some "real" code.
1372 The APCS (ARM Procedure Call Standard) defines the following
1376 [stmfd sp!, {a1,a2,a3,a4}]
1377 stmfd sp!, {...,fp,ip,lr,pc}
1378 [stfe f7, [sp, #-12]!]
1379 [stfe f6, [sp, #-12]!]
1380 [stfe f5, [sp, #-12]!]
1381 [stfe f4, [sp, #-12]!]
1382 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1385 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1387 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1389 CORE_ADDR func_addr, limit_pc;
1391 /* See if we can determine the end of the prologue via the symbol table.
1392 If so, then return either PC, or the PC after the prologue, whichever
1394 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1396 CORE_ADDR post_prologue_pc
1397 = skip_prologue_using_sal (gdbarch, func_addr);
1398 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1400 if (post_prologue_pc)
1402 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1405 /* GCC always emits a line note before the prologue and another
1406 one after, even if the two are at the same address or on the
1407 same line. Take advantage of this so that we do not need to
1408 know every instruction that might appear in the prologue. We
1409 will have producer information for most binaries; if it is
1410 missing (e.g. for -gstabs), assuming the GNU tools. */
1411 if (post_prologue_pc
1413 || COMPUNIT_PRODUCER (cust) == NULL
1414 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1415 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1416 return post_prologue_pc;
1418 if (post_prologue_pc != 0)
1420 CORE_ADDR analyzed_limit;
1422 /* For non-GCC compilers, make sure the entire line is an
1423 acceptable prologue; GDB will round this function's
1424 return value up to the end of the following line so we
1425 can not skip just part of a line (and we do not want to).
1427 RealView does not treat the prologue specially, but does
1428 associate prologue code with the opening brace; so this
1429 lets us skip the first line if we think it is the opening
1431 if (arm_pc_is_thumb (gdbarch, func_addr))
1432 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1433 post_prologue_pc, NULL);
1435 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1436 post_prologue_pc, NULL);
1438 if (analyzed_limit != post_prologue_pc)
1441 return post_prologue_pc;
1445 /* Can't determine prologue from the symbol table, need to examine
1448 /* Find an upper limit on the function prologue using the debug
1449 information. If the debug information could not be used to provide
1450 that bound, then use an arbitrary large number as the upper bound. */
1451 /* Like arm_scan_prologue, stop no later than pc + 64. */
1452 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1454 limit_pc = pc + 64; /* Magic. */
1457 /* Check if this is Thumb code. */
1458 if (arm_pc_is_thumb (gdbarch, pc))
1459 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1461 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1465 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1466 This function decodes a Thumb function prologue to determine:
1467 1) the size of the stack frame
1468 2) which registers are saved on it
1469 3) the offsets of saved regs
1470 4) the offset from the stack pointer to the frame pointer
1472 A typical Thumb function prologue would create this stack frame
1473 (offsets relative to FP)
1474 old SP -> 24 stack parameters
1477 R7 -> 0 local variables (16 bytes)
1478 SP -> -12 additional stack space (12 bytes)
1479 The frame size would thus be 36 bytes, and the frame offset would be
1480 12 bytes. The frame register is R7.
1482 The comments for thumb_skip_prolog() describe the algorithm we use
1483 to detect the end of the prolog. */
1487 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1488 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1490 CORE_ADDR prologue_start;
1491 CORE_ADDR prologue_end;
1493 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1496 /* See comment in arm_scan_prologue for an explanation of
1498 if (prologue_end > prologue_start + 64)
1500 prologue_end = prologue_start + 64;
1504 /* We're in the boondocks: we have no idea where the start of the
1508 prologue_end = min (prologue_end, prev_pc);
1510 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1513 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1516 arm_instruction_changes_pc (uint32_t this_instr)
1518 if (bits (this_instr, 28, 31) == INST_NV)
1519 /* Unconditional instructions. */
1520 switch (bits (this_instr, 24, 27))
1524 /* Branch with Link and change to Thumb. */
1529 /* Coprocessor register transfer. */
1530 if (bits (this_instr, 12, 15) == 15)
1531 error (_("Invalid update to pc in instruction"));
1537 switch (bits (this_instr, 25, 27))
1540 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1542 /* Multiplies and extra load/stores. */
1543 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1544 /* Neither multiplies nor extension load/stores are allowed
1548 /* Otherwise, miscellaneous instructions. */
1550 /* BX <reg>, BXJ <reg>, BLX <reg> */
1551 if (bits (this_instr, 4, 27) == 0x12fff1
1552 || bits (this_instr, 4, 27) == 0x12fff2
1553 || bits (this_instr, 4, 27) == 0x12fff3)
1556 /* Other miscellaneous instructions are unpredictable if they
1560 /* Data processing instruction. Fall through. */
1563 if (bits (this_instr, 12, 15) == 15)
1570 /* Media instructions and architecturally undefined instructions. */
1571 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1575 if (bit (this_instr, 20) == 0)
1579 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1585 /* Load/store multiple. */
1586 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1592 /* Branch and branch with link. */
1597 /* Coprocessor transfers or SWIs can not affect PC. */
1601 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1605 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1609 arm_instruction_restores_sp (unsigned int insn)
1611 if (bits (insn, 28, 31) != INST_NV)
1613 if ((insn & 0x0df0f000) == 0x0080d000
1614 /* ADD SP (register or immediate). */
1615 || (insn & 0x0df0f000) == 0x0040d000
1616 /* SUB SP (register or immediate). */
1617 || (insn & 0x0ffffff0) == 0x01a0d000
1619 || (insn & 0x0fff0000) == 0x08bd0000
1621 || (insn & 0x0fff0000) == 0x049d0000)
1622 /* POP of a single register. */
1629 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1630 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1631 fill it in. Return the first address not recognized as a prologue
1634 We recognize all the instructions typically found in ARM prologues,
1635 plus harmless instructions which can be skipped (either for analysis
1636 purposes, or a more restrictive set that can be skipped when finding
1637 the end of the prologue). */
1640 arm_analyze_prologue (struct gdbarch *gdbarch,
1641 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1642 struct arm_prologue_cache *cache)
1644 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1645 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1647 CORE_ADDR offset, current_pc;
1648 pv_t regs[ARM_FPS_REGNUM];
1649 struct pv_area *stack;
1650 struct cleanup *back_to;
1651 CORE_ADDR unrecognized_pc = 0;
1653 /* Search the prologue looking for instructions that set up the
1654 frame pointer, adjust the stack pointer, and save registers.
1656 Be careful, however, and if it doesn't look like a prologue,
1657 don't try to scan it. If, for instance, a frameless function
1658 begins with stmfd sp!, then we will tell ourselves there is
1659 a frame, which will confuse stack traceback, as well as "finish"
1660 and other operations that rely on a knowledge of the stack
1663 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1664 regs[regno] = pv_register (regno, 0);
1665 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1666 back_to = make_cleanup_free_pv_area (stack);
1668 for (current_pc = prologue_start;
1669 current_pc < prologue_end;
1673 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1675 if (insn == 0xe1a0c00d) /* mov ip, sp */
1677 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1680 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1681 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1683 unsigned imm = insn & 0xff; /* immediate value */
1684 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1685 int rd = bits (insn, 12, 15);
1686 imm = (imm >> rot) | (imm << (32 - rot));
1687 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1690 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1691 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1693 unsigned imm = insn & 0xff; /* immediate value */
1694 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1695 int rd = bits (insn, 12, 15);
1696 imm = (imm >> rot) | (imm << (32 - rot));
1697 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1700 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1703 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1705 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1706 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1707 regs[bits (insn, 12, 15)]);
1710 else if ((insn & 0xffff0000) == 0xe92d0000)
1711 /* stmfd sp!, {..., fp, ip, lr, pc}
1713 stmfd sp!, {a1, a2, a3, a4} */
1715 int mask = insn & 0xffff;
1717 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1720 /* Calculate offsets of saved registers. */
1721 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1722 if (mask & (1 << regno))
1725 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1726 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1729 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1730 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1731 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1733 /* No need to add this to saved_regs -- it's just an arg reg. */
1736 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1737 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1738 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1740 /* No need to add this to saved_regs -- it's just an arg reg. */
1743 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1745 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1747 /* No need to add this to saved_regs -- it's just arg regs. */
1750 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1752 unsigned imm = insn & 0xff; /* immediate value */
1753 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1754 imm = (imm >> rot) | (imm << (32 - rot));
1755 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1757 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1759 unsigned imm = insn & 0xff; /* immediate value */
1760 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1761 imm = (imm >> rot) | (imm << (32 - rot));
1762 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1764 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1766 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1768 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1771 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1772 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1773 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1775 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1777 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1779 int n_saved_fp_regs;
1780 unsigned int fp_start_reg, fp_bound_reg;
1782 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1785 if ((insn & 0x800) == 0x800) /* N0 is set */
1787 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1788 n_saved_fp_regs = 3;
1790 n_saved_fp_regs = 1;
1794 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1795 n_saved_fp_regs = 2;
1797 n_saved_fp_regs = 4;
1800 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1801 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1802 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1804 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1805 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1806 regs[fp_start_reg++]);
1809 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1811 /* Allow some special function calls when skipping the
1812 prologue; GCC generates these before storing arguments to
1814 CORE_ADDR dest = BranchDest (current_pc, insn);
1816 if (skip_prologue_function (gdbarch, dest, 0))
1821 else if ((insn & 0xf0000000) != 0xe0000000)
1822 break; /* Condition not true, exit early. */
1823 else if (arm_instruction_changes_pc (insn))
1824 /* Don't scan past anything that might change control flow. */
1826 else if (arm_instruction_restores_sp (insn))
1828 /* Don't scan past the epilogue. */
1831 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1832 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1833 /* Ignore block loads from the stack, potentially copying
1834 parameters from memory. */
1836 else if ((insn & 0xfc500000) == 0xe4100000
1837 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1838 /* Similarly ignore single loads from the stack. */
1840 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1841 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1842 register instead of the stack. */
1846 /* The optimizer might shove anything into the prologue, if
1847 we build up cache (cache != NULL) from scanning prologue,
1848 we just skip what we don't recognize and scan further to
1849 make cache as complete as possible. However, if we skip
1850 prologue, we'll stop immediately on unrecognized
1852 unrecognized_pc = current_pc;
1860 if (unrecognized_pc == 0)
1861 unrecognized_pc = current_pc;
1865 int framereg, framesize;
1867 /* The frame size is just the distance from the frame register
1868 to the original stack pointer. */
1869 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1871 /* Frame pointer is fp. */
1872 framereg = ARM_FP_REGNUM;
1873 framesize = -regs[ARM_FP_REGNUM].k;
1877 /* Try the stack pointer... this is a bit desperate. */
1878 framereg = ARM_SP_REGNUM;
1879 framesize = -regs[ARM_SP_REGNUM].k;
1882 cache->framereg = framereg;
1883 cache->framesize = framesize;
1885 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1886 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1887 cache->saved_regs[regno].addr = offset;
1891 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1892 paddress (gdbarch, unrecognized_pc));
1894 do_cleanups (back_to);
1895 return unrecognized_pc;
1899 arm_scan_prologue (struct frame_info *this_frame,
1900 struct arm_prologue_cache *cache)
1902 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1903 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1905 CORE_ADDR prologue_start, prologue_end, current_pc;
1906 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1907 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1908 pv_t regs[ARM_FPS_REGNUM];
1909 struct pv_area *stack;
1910 struct cleanup *back_to;
1913 /* Assume there is no frame until proven otherwise. */
1914 cache->framereg = ARM_SP_REGNUM;
1915 cache->framesize = 0;
1917 /* Check for Thumb prologue. */
1918 if (arm_frame_is_thumb (this_frame))
1920 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1924 /* Find the function prologue. If we can't find the function in
1925 the symbol table, peek in the stack frame to find the PC. */
1926 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1929 /* One way to find the end of the prologue (which works well
1930 for unoptimized code) is to do the following:
1932 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1935 prologue_end = prev_pc;
1936 else if (sal.end < prologue_end)
1937 prologue_end = sal.end;
1939 This mechanism is very accurate so long as the optimizer
1940 doesn't move any instructions from the function body into the
1941 prologue. If this happens, sal.end will be the last
1942 instruction in the first hunk of prologue code just before
1943 the first instruction that the scheduler has moved from
1944 the body to the prologue.
1946 In order to make sure that we scan all of the prologue
1947 instructions, we use a slightly less accurate mechanism which
1948 may scan more than necessary. To help compensate for this
1949 lack of accuracy, the prologue scanning loop below contains
1950 several clauses which'll cause the loop to terminate early if
1951 an implausible prologue instruction is encountered.
1957 is a suitable endpoint since it accounts for the largest
1958 possible prologue plus up to five instructions inserted by
1961 if (prologue_end > prologue_start + 64)
1963 prologue_end = prologue_start + 64; /* See above. */
1968 /* We have no symbol information. Our only option is to assume this
1969 function has a standard stack frame and the normal frame register.
1970 Then, we can find the value of our frame pointer on entrance to
1971 the callee (or at the present moment if this is the innermost frame).
1972 The value stored there should be the address of the stmfd + 8. */
1973 CORE_ADDR frame_loc;
1974 LONGEST return_value;
1976 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1977 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1981 prologue_start = gdbarch_addr_bits_remove
1982 (gdbarch, return_value) - 8;
1983 prologue_end = prologue_start + 64; /* See above. */
1987 if (prev_pc < prologue_end)
1988 prologue_end = prev_pc;
1990 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1993 static struct arm_prologue_cache *
1994 arm_make_prologue_cache (struct frame_info *this_frame)
1997 struct arm_prologue_cache *cache;
1998 CORE_ADDR unwound_fp;
2000 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2001 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2003 arm_scan_prologue (this_frame, cache);
2005 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2006 if (unwound_fp == 0)
2009 cache->prev_sp = unwound_fp + cache->framesize;
2011 /* Calculate actual addresses of saved registers using offsets
2012 determined by arm_scan_prologue. */
2013 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2014 if (trad_frame_addr_p (cache->saved_regs, reg))
2015 cache->saved_regs[reg].addr += cache->prev_sp;
2020 /* Implementation of the stop_reason hook for arm_prologue frames. */
2022 static enum unwind_stop_reason
2023 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
2026 struct arm_prologue_cache *cache;
2029 if (*this_cache == NULL)
2030 *this_cache = arm_make_prologue_cache (this_frame);
2031 cache = *this_cache;
2033 /* This is meant to halt the backtrace at "_start". */
2034 pc = get_frame_pc (this_frame);
2035 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2036 return UNWIND_OUTERMOST;
2038 /* If we've hit a wall, stop. */
2039 if (cache->prev_sp == 0)
2040 return UNWIND_OUTERMOST;
2042 return UNWIND_NO_REASON;
2045 /* Our frame ID for a normal frame is the current function's starting PC
2046 and the caller's SP when we were called. */
2049 arm_prologue_this_id (struct frame_info *this_frame,
2051 struct frame_id *this_id)
2053 struct arm_prologue_cache *cache;
2057 if (*this_cache == NULL)
2058 *this_cache = arm_make_prologue_cache (this_frame);
2059 cache = *this_cache;
2061 /* Use function start address as part of the frame ID. If we cannot
2062 identify the start address (due to missing symbol information),
2063 fall back to just using the current PC. */
2064 pc = get_frame_pc (this_frame);
2065 func = get_frame_func (this_frame);
2069 id = frame_id_build (cache->prev_sp, func);
2073 static struct value *
2074 arm_prologue_prev_register (struct frame_info *this_frame,
2078 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2079 struct arm_prologue_cache *cache;
2081 if (*this_cache == NULL)
2082 *this_cache = arm_make_prologue_cache (this_frame);
2083 cache = *this_cache;
2085 /* If we are asked to unwind the PC, then we need to return the LR
2086 instead. The prologue may save PC, but it will point into this
2087 frame's prologue, not the next frame's resume location. Also
2088 strip the saved T bit. A valid LR may have the low bit set, but
2089 a valid PC never does. */
2090 if (prev_regnum == ARM_PC_REGNUM)
2094 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2095 return frame_unwind_got_constant (this_frame, prev_regnum,
2096 arm_addr_bits_remove (gdbarch, lr));
2099 /* SP is generally not saved to the stack, but this frame is
2100 identified by the next frame's stack pointer at the time of the call.
2101 The value was already reconstructed into PREV_SP. */
2102 if (prev_regnum == ARM_SP_REGNUM)
2103 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2105 /* The CPSR may have been changed by the call instruction and by the
2106 called function. The only bit we can reconstruct is the T bit,
2107 by checking the low bit of LR as of the call. This is a reliable
2108 indicator of Thumb-ness except for some ARM v4T pre-interworking
2109 Thumb code, which could get away with a clear low bit as long as
2110 the called function did not use bx. Guess that all other
2111 bits are unchanged; the condition flags are presumably lost,
2112 but the processor status is likely valid. */
2113 if (prev_regnum == ARM_PS_REGNUM)
2116 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2118 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2119 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2120 if (IS_THUMB_ADDR (lr))
2124 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2127 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2131 struct frame_unwind arm_prologue_unwind = {
2133 arm_prologue_unwind_stop_reason,
2134 arm_prologue_this_id,
2135 arm_prologue_prev_register,
2137 default_frame_sniffer
2140 /* Maintain a list of ARM exception table entries per objfile, similar to the
2141 list of mapping symbols. We only cache entries for standard ARM-defined
2142 personality routines; the cache will contain only the frame unwinding
2143 instructions associated with the entry (not the descriptors). */
2145 static const struct objfile_data *arm_exidx_data_key;
2147 struct arm_exidx_entry
2152 typedef struct arm_exidx_entry arm_exidx_entry_s;
2153 DEF_VEC_O(arm_exidx_entry_s);
2155 struct arm_exidx_data
2157 VEC(arm_exidx_entry_s) **section_maps;
2161 arm_exidx_data_free (struct objfile *objfile, void *arg)
2163 struct arm_exidx_data *data = arg;
2166 for (i = 0; i < objfile->obfd->section_count; i++)
2167 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2171 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2172 const struct arm_exidx_entry *rhs)
2174 return lhs->addr < rhs->addr;
2177 static struct obj_section *
2178 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2180 struct obj_section *osect;
2182 ALL_OBJFILE_OSECTIONS (objfile, osect)
2183 if (bfd_get_section_flags (objfile->obfd,
2184 osect->the_bfd_section) & SEC_ALLOC)
2186 bfd_vma start, size;
2187 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2188 size = bfd_get_section_size (osect->the_bfd_section);
2190 if (start <= vma && vma < start + size)
2197 /* Parse contents of exception table and exception index sections
2198 of OBJFILE, and fill in the exception table entry cache.
2200 For each entry that refers to a standard ARM-defined personality
2201 routine, extract the frame unwinding instructions (from either
2202 the index or the table section). The unwinding instructions
2204 - extracting them from the rest of the table data
2205 - converting to host endianness
2206 - appending the implicit 0xb0 ("Finish") code
2208 The extracted and normalized instructions are stored for later
2209 retrieval by the arm_find_exidx_entry routine. */
2212 arm_exidx_new_objfile (struct objfile *objfile)
2214 struct cleanup *cleanups;
2215 struct arm_exidx_data *data;
2216 asection *exidx, *extab;
2217 bfd_vma exidx_vma = 0, extab_vma = 0;
2218 bfd_size_type exidx_size = 0, extab_size = 0;
2219 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2222 /* If we've already touched this file, do nothing. */
2223 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2225 cleanups = make_cleanup (null_cleanup, NULL);
2227 /* Read contents of exception table and index. */
2228 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2231 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2232 exidx_size = bfd_get_section_size (exidx);
2233 exidx_data = xmalloc (exidx_size);
2234 make_cleanup (xfree, exidx_data);
2236 if (!bfd_get_section_contents (objfile->obfd, exidx,
2237 exidx_data, 0, exidx_size))
2239 do_cleanups (cleanups);
2244 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2247 extab_vma = bfd_section_vma (objfile->obfd, extab);
2248 extab_size = bfd_get_section_size (extab);
2249 extab_data = xmalloc (extab_size);
2250 make_cleanup (xfree, extab_data);
2252 if (!bfd_get_section_contents (objfile->obfd, extab,
2253 extab_data, 0, extab_size))
2255 do_cleanups (cleanups);
2260 /* Allocate exception table data structure. */
2261 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2262 set_objfile_data (objfile, arm_exidx_data_key, data);
2263 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2264 objfile->obfd->section_count,
2265 VEC(arm_exidx_entry_s) *);
2267 /* Fill in exception table. */
2268 for (i = 0; i < exidx_size / 8; i++)
2270 struct arm_exidx_entry new_exidx_entry;
2271 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2272 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2273 bfd_vma addr = 0, word = 0;
2274 int n_bytes = 0, n_words = 0;
2275 struct obj_section *sec;
2276 gdb_byte *entry = NULL;
2278 /* Extract address of start of function. */
2279 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2280 idx += exidx_vma + i * 8;
2282 /* Find section containing function and compute section offset. */
2283 sec = arm_obj_section_from_vma (objfile, idx);
2286 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2288 /* Determine address of exception table entry. */
2291 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2293 else if ((val & 0xff000000) == 0x80000000)
2295 /* Exception table entry embedded in .ARM.exidx
2296 -- must be short form. */
2300 else if (!(val & 0x80000000))
2302 /* Exception table entry in .ARM.extab. */
2303 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2304 addr += exidx_vma + i * 8 + 4;
2306 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2308 word = bfd_h_get_32 (objfile->obfd,
2309 extab_data + addr - extab_vma);
2312 if ((word & 0xff000000) == 0x80000000)
2317 else if ((word & 0xff000000) == 0x81000000
2318 || (word & 0xff000000) == 0x82000000)
2322 n_words = ((word >> 16) & 0xff);
2324 else if (!(word & 0x80000000))
2327 struct obj_section *pers_sec;
2328 int gnu_personality = 0;
2330 /* Custom personality routine. */
2331 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2332 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2334 /* Check whether we've got one of the variants of the
2335 GNU personality routines. */
2336 pers_sec = arm_obj_section_from_vma (objfile, pers);
2339 static const char *personality[] =
2341 "__gcc_personality_v0",
2342 "__gxx_personality_v0",
2343 "__gcj_personality_v0",
2344 "__gnu_objc_personality_v0",
2348 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2351 for (k = 0; personality[k]; k++)
2352 if (lookup_minimal_symbol_by_pc_name
2353 (pc, personality[k], objfile))
2355 gnu_personality = 1;
2360 /* If so, the next word contains a word count in the high
2361 byte, followed by the same unwind instructions as the
2362 pre-defined forms. */
2364 && addr + 4 <= extab_vma + extab_size)
2366 word = bfd_h_get_32 (objfile->obfd,
2367 extab_data + addr - extab_vma);
2370 n_words = ((word >> 24) & 0xff);
2376 /* Sanity check address. */
2378 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2379 n_words = n_bytes = 0;
2381 /* The unwind instructions reside in WORD (only the N_BYTES least
2382 significant bytes are valid), followed by N_WORDS words in the
2383 extab section starting at ADDR. */
2384 if (n_bytes || n_words)
2386 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2387 n_bytes + n_words * 4 + 1);
2390 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2394 word = bfd_h_get_32 (objfile->obfd,
2395 extab_data + addr - extab_vma);
2398 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2399 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2400 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2401 *p++ = (gdb_byte) (word & 0xff);
2404 /* Implied "Finish" to terminate the list. */
2408 /* Push entry onto vector. They are guaranteed to always
2409 appear in order of increasing addresses. */
2410 new_exidx_entry.addr = idx;
2411 new_exidx_entry.entry = entry;
2412 VEC_safe_push (arm_exidx_entry_s,
2413 data->section_maps[sec->the_bfd_section->index],
2417 do_cleanups (cleanups);
2420 /* Search for the exception table entry covering MEMADDR. If one is found,
2421 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2422 set *START to the start of the region covered by this entry. */
2425 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2427 struct obj_section *sec;
2429 sec = find_pc_section (memaddr);
2432 struct arm_exidx_data *data;
2433 VEC(arm_exidx_entry_s) *map;
2434 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2437 data = objfile_data (sec->objfile, arm_exidx_data_key);
2440 map = data->section_maps[sec->the_bfd_section->index];
2441 if (!VEC_empty (arm_exidx_entry_s, map))
2443 struct arm_exidx_entry *map_sym;
2445 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2446 arm_compare_exidx_entries);
2448 /* VEC_lower_bound finds the earliest ordered insertion
2449 point. If the following symbol starts at this exact
2450 address, we use that; otherwise, the preceding
2451 exception table entry covers this address. */
2452 if (idx < VEC_length (arm_exidx_entry_s, map))
2454 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2455 if (map_sym->addr == map_key.addr)
2458 *start = map_sym->addr + obj_section_addr (sec);
2459 return map_sym->entry;
2465 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2467 *start = map_sym->addr + obj_section_addr (sec);
2468 return map_sym->entry;
2477 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2478 instruction list from the ARM exception table entry ENTRY, allocate and
2479 return a prologue cache structure describing how to unwind this frame.
2481 Return NULL if the unwinding instruction list contains a "spare",
2482 "reserved" or "refuse to unwind" instruction as defined in section
2483 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2484 for the ARM Architecture" document. */
2486 static struct arm_prologue_cache *
2487 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2492 struct arm_prologue_cache *cache;
2493 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2494 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2500 /* Whenever we reload SP, we actually have to retrieve its
2501 actual value in the current frame. */
2504 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2506 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2507 vsp = get_frame_register_unsigned (this_frame, reg);
2511 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2512 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2518 /* Decode next unwind instruction. */
2521 if ((insn & 0xc0) == 0)
2523 int offset = insn & 0x3f;
2524 vsp += (offset << 2) + 4;
2526 else if ((insn & 0xc0) == 0x40)
2528 int offset = insn & 0x3f;
2529 vsp -= (offset << 2) + 4;
2531 else if ((insn & 0xf0) == 0x80)
2533 int mask = ((insn & 0xf) << 8) | *entry++;
2536 /* The special case of an all-zero mask identifies
2537 "Refuse to unwind". We return NULL to fall back
2538 to the prologue analyzer. */
2542 /* Pop registers r4..r15 under mask. */
2543 for (i = 0; i < 12; i++)
2544 if (mask & (1 << i))
2546 cache->saved_regs[4 + i].addr = vsp;
2550 /* Special-case popping SP -- we need to reload vsp. */
2551 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2554 else if ((insn & 0xf0) == 0x90)
2556 int reg = insn & 0xf;
2558 /* Reserved cases. */
2559 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2562 /* Set SP from another register and mark VSP for reload. */
2563 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2566 else if ((insn & 0xf0) == 0xa0)
2568 int count = insn & 0x7;
2569 int pop_lr = (insn & 0x8) != 0;
2572 /* Pop r4..r[4+count]. */
2573 for (i = 0; i <= count; i++)
2575 cache->saved_regs[4 + i].addr = vsp;
2579 /* If indicated by flag, pop LR as well. */
2582 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2586 else if (insn == 0xb0)
2588 /* We could only have updated PC by popping into it; if so, it
2589 will show up as address. Otherwise, copy LR into PC. */
2590 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2591 cache->saved_regs[ARM_PC_REGNUM]
2592 = cache->saved_regs[ARM_LR_REGNUM];
2597 else if (insn == 0xb1)
2599 int mask = *entry++;
2602 /* All-zero mask and mask >= 16 is "spare". */
2603 if (mask == 0 || mask >= 16)
2606 /* Pop r0..r3 under mask. */
2607 for (i = 0; i < 4; i++)
2608 if (mask & (1 << i))
2610 cache->saved_regs[i].addr = vsp;
2614 else if (insn == 0xb2)
2616 ULONGEST offset = 0;
2621 offset |= (*entry & 0x7f) << shift;
2624 while (*entry++ & 0x80);
2626 vsp += 0x204 + (offset << 2);
2628 else if (insn == 0xb3)
2630 int start = *entry >> 4;
2631 int count = (*entry++) & 0xf;
2634 /* Only registers D0..D15 are valid here. */
2635 if (start + count >= 16)
2638 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2639 for (i = 0; i <= count; i++)
2641 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2645 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2648 else if ((insn & 0xf8) == 0xb8)
2650 int count = insn & 0x7;
2653 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2654 for (i = 0; i <= count; i++)
2656 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2660 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2663 else if (insn == 0xc6)
2665 int start = *entry >> 4;
2666 int count = (*entry++) & 0xf;
2669 /* Only registers WR0..WR15 are valid. */
2670 if (start + count >= 16)
2673 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2674 for (i = 0; i <= count; i++)
2676 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2680 else if (insn == 0xc7)
2682 int mask = *entry++;
2685 /* All-zero mask and mask >= 16 is "spare". */
2686 if (mask == 0 || mask >= 16)
2689 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2690 for (i = 0; i < 4; i++)
2691 if (mask & (1 << i))
2693 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2697 else if ((insn & 0xf8) == 0xc0)
2699 int count = insn & 0x7;
2702 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2703 for (i = 0; i <= count; i++)
2705 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2709 else if (insn == 0xc8)
2711 int start = *entry >> 4;
2712 int count = (*entry++) & 0xf;
2715 /* Only registers D0..D31 are valid. */
2716 if (start + count >= 16)
2719 /* Pop VFP double-precision registers
2720 D[16+start]..D[16+start+count]. */
2721 for (i = 0; i <= count; i++)
2723 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2727 else if (insn == 0xc9)
2729 int start = *entry >> 4;
2730 int count = (*entry++) & 0xf;
2733 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2734 for (i = 0; i <= count; i++)
2736 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2740 else if ((insn & 0xf8) == 0xd0)
2742 int count = insn & 0x7;
2745 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2746 for (i = 0; i <= count; i++)
2748 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2754 /* Everything else is "spare". */
2759 /* If we restore SP from a register, assume this was the frame register.
2760 Otherwise just fall back to SP as frame register. */
2761 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2762 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2764 cache->framereg = ARM_SP_REGNUM;
2766 /* Determine offset to previous frame. */
2768 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2770 /* We already got the previous SP. */
2771 cache->prev_sp = vsp;
2776 /* Unwinding via ARM exception table entries. Note that the sniffer
2777 already computes a filled-in prologue cache, which is then used
2778 with the same arm_prologue_this_id and arm_prologue_prev_register
2779 routines also used for prologue-parsing based unwinding. */
2782 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2783 struct frame_info *this_frame,
2784 void **this_prologue_cache)
2786 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2787 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2788 CORE_ADDR addr_in_block, exidx_region, func_start;
2789 struct arm_prologue_cache *cache;
2792 /* See if we have an ARM exception table entry covering this address. */
2793 addr_in_block = get_frame_address_in_block (this_frame);
2794 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2798 /* The ARM exception table does not describe unwind information
2799 for arbitrary PC values, but is guaranteed to be correct only
2800 at call sites. We have to decide here whether we want to use
2801 ARM exception table information for this frame, or fall back
2802 to using prologue parsing. (Note that if we have DWARF CFI,
2803 this sniffer isn't even called -- CFI is always preferred.)
2805 Before we make this decision, however, we check whether we
2806 actually have *symbol* information for the current frame.
2807 If not, prologue parsing would not work anyway, so we might
2808 as well use the exception table and hope for the best. */
2809 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2813 /* If the next frame is "normal", we are at a call site in this
2814 frame, so exception information is guaranteed to be valid. */
2815 if (get_next_frame (this_frame)
2816 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2819 /* We also assume exception information is valid if we're currently
2820 blocked in a system call. The system library is supposed to
2821 ensure this, so that e.g. pthread cancellation works. */
2822 if (arm_frame_is_thumb (this_frame))
2826 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2827 byte_order_for_code, &insn)
2828 && (insn & 0xff00) == 0xdf00 /* svc */)
2835 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2836 byte_order_for_code, &insn)
2837 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2841 /* Bail out if we don't know that exception information is valid. */
2845 /* The ARM exception index does not mark the *end* of the region
2846 covered by the entry, and some functions will not have any entry.
2847 To correctly recognize the end of the covered region, the linker
2848 should have inserted dummy records with a CANTUNWIND marker.
2850 Unfortunately, current versions of GNU ld do not reliably do
2851 this, and thus we may have found an incorrect entry above.
2852 As a (temporary) sanity check, we only use the entry if it
2853 lies *within* the bounds of the function. Note that this check
2854 might reject perfectly valid entries that just happen to cover
2855 multiple functions; therefore this check ought to be removed
2856 once the linker is fixed. */
2857 if (func_start > exidx_region)
2861 /* Decode the list of unwinding instructions into a prologue cache.
2862 Note that this may fail due to e.g. a "refuse to unwind" code. */
2863 cache = arm_exidx_fill_cache (this_frame, entry);
2867 *this_prologue_cache = cache;
2871 struct frame_unwind arm_exidx_unwind = {
2873 default_frame_unwind_stop_reason,
2874 arm_prologue_this_id,
2875 arm_prologue_prev_register,
2877 arm_exidx_unwind_sniffer
2880 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2881 trampoline, return the target PC. Otherwise return 0.
2883 void call0a (char c, short s, int i, long l) {}
2887 (*pointer_to_call0a) (c, s, i, l);
2890 Instead of calling a stub library function _call_via_xx (xx is
2891 the register name), GCC may inline the trampoline in the object
2892 file as below (register r2 has the address of call0a).
2895 .type main, %function
2904 The trampoline 'bx r2' doesn't belong to main. */
2907 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2909 /* The heuristics of recognizing such trampoline is that FRAME is
2910 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2911 if (arm_frame_is_thumb (frame))
2915 if (target_read_memory (pc, buf, 2) == 0)
2917 struct gdbarch *gdbarch = get_frame_arch (frame);
2918 enum bfd_endian byte_order_for_code
2919 = gdbarch_byte_order_for_code (gdbarch);
2921 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2923 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2926 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2928 /* Clear the LSB so that gdb core sets step-resume
2929 breakpoint at the right address. */
2930 return UNMAKE_THUMB_ADDR (dest);
2938 static struct arm_prologue_cache *
2939 arm_make_stub_cache (struct frame_info *this_frame)
2941 struct arm_prologue_cache *cache;
2943 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2944 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2946 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2951 /* Our frame ID for a stub frame is the current SP and LR. */
2954 arm_stub_this_id (struct frame_info *this_frame,
2956 struct frame_id *this_id)
2958 struct arm_prologue_cache *cache;
2960 if (*this_cache == NULL)
2961 *this_cache = arm_make_stub_cache (this_frame);
2962 cache = *this_cache;
2964 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2968 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2969 struct frame_info *this_frame,
2970 void **this_prologue_cache)
2972 CORE_ADDR addr_in_block;
2974 CORE_ADDR pc, start_addr;
2977 addr_in_block = get_frame_address_in_block (this_frame);
2978 pc = get_frame_pc (this_frame);
2979 if (in_plt_section (addr_in_block)
2980 /* We also use the stub winder if the target memory is unreadable
2981 to avoid having the prologue unwinder trying to read it. */
2982 || target_read_memory (pc, dummy, 4) != 0)
2985 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2986 && arm_skip_bx_reg (this_frame, pc) != 0)
2992 struct frame_unwind arm_stub_unwind = {
2994 default_frame_unwind_stop_reason,
2996 arm_prologue_prev_register,
2998 arm_stub_unwind_sniffer
3001 /* Put here the code to store, into CACHE->saved_regs, the addresses
3002 of the saved registers of frame described by THIS_FRAME. CACHE is
3005 static struct arm_prologue_cache *
3006 arm_m_exception_cache (struct frame_info *this_frame)
3008 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3009 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3010 struct arm_prologue_cache *cache;
3011 CORE_ADDR unwound_sp;
3014 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
3015 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3017 unwound_sp = get_frame_register_unsigned (this_frame,
3020 /* The hardware saves eight 32-bit words, comprising xPSR,
3021 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3022 "B1.5.6 Exception entry behavior" in
3023 "ARMv7-M Architecture Reference Manual". */
3024 cache->saved_regs[0].addr = unwound_sp;
3025 cache->saved_regs[1].addr = unwound_sp + 4;
3026 cache->saved_regs[2].addr = unwound_sp + 8;
3027 cache->saved_regs[3].addr = unwound_sp + 12;
3028 cache->saved_regs[12].addr = unwound_sp + 16;
3029 cache->saved_regs[14].addr = unwound_sp + 20;
3030 cache->saved_regs[15].addr = unwound_sp + 24;
3031 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
3033 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3034 aligner between the top of the 32-byte stack frame and the
3035 previous context's stack pointer. */
3036 cache->prev_sp = unwound_sp + 32;
3037 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
3038 && (xpsr & (1 << 9)) != 0)
3039 cache->prev_sp += 4;
3044 /* Implementation of function hook 'this_id' in
3045 'struct frame_uwnind'. */
3048 arm_m_exception_this_id (struct frame_info *this_frame,
3050 struct frame_id *this_id)
3052 struct arm_prologue_cache *cache;
3054 if (*this_cache == NULL)
3055 *this_cache = arm_m_exception_cache (this_frame);
3056 cache = *this_cache;
3058 /* Our frame ID for a stub frame is the current SP and LR. */
3059 *this_id = frame_id_build (cache->prev_sp,
3060 get_frame_pc (this_frame));
3063 /* Implementation of function hook 'prev_register' in
3064 'struct frame_uwnind'. */
3066 static struct value *
3067 arm_m_exception_prev_register (struct frame_info *this_frame,
3071 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3072 struct arm_prologue_cache *cache;
3074 if (*this_cache == NULL)
3075 *this_cache = arm_m_exception_cache (this_frame);
3076 cache = *this_cache;
3078 /* The value was already reconstructed into PREV_SP. */
3079 if (prev_regnum == ARM_SP_REGNUM)
3080 return frame_unwind_got_constant (this_frame, prev_regnum,
3083 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3087 /* Implementation of function hook 'sniffer' in
3088 'struct frame_uwnind'. */
3091 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3092 struct frame_info *this_frame,
3093 void **this_prologue_cache)
3095 CORE_ADDR this_pc = get_frame_pc (this_frame);
3097 /* No need to check is_m; this sniffer is only registered for
3098 M-profile architectures. */
3100 /* Exception frames return to one of these magic PCs. Other values
3101 are not defined as of v7-M. See details in "B1.5.8 Exception
3102 return behavior" in "ARMv7-M Architecture Reference Manual". */
3103 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3104 || this_pc == 0xfffffffd)
3110 /* Frame unwinder for M-profile exceptions. */
3112 struct frame_unwind arm_m_exception_unwind =
3115 default_frame_unwind_stop_reason,
3116 arm_m_exception_this_id,
3117 arm_m_exception_prev_register,
3119 arm_m_exception_unwind_sniffer
3123 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3125 struct arm_prologue_cache *cache;
3127 if (*this_cache == NULL)
3128 *this_cache = arm_make_prologue_cache (this_frame);
3129 cache = *this_cache;
3131 return cache->prev_sp - cache->framesize;
3134 struct frame_base arm_normal_base = {
3135 &arm_prologue_unwind,
3136 arm_normal_frame_base,
3137 arm_normal_frame_base,
3138 arm_normal_frame_base
3141 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3142 dummy frame. The frame ID's base needs to match the TOS value
3143 saved by save_dummy_frame_tos() and returned from
3144 arm_push_dummy_call, and the PC needs to match the dummy frame's
3147 static struct frame_id
3148 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3150 return frame_id_build (get_frame_register_unsigned (this_frame,
3152 get_frame_pc (this_frame));
3155 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3156 be used to construct the previous frame's ID, after looking up the
3157 containing function). */
3160 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3163 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3164 return arm_addr_bits_remove (gdbarch, pc);
3168 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3170 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3173 static struct value *
3174 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3177 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3179 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3184 /* The PC is normally copied from the return column, which
3185 describes saves of LR. However, that version may have an
3186 extra bit set to indicate Thumb state. The bit is not
3188 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3189 return frame_unwind_got_constant (this_frame, regnum,
3190 arm_addr_bits_remove (gdbarch, lr));
3193 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3194 cpsr = get_frame_register_unsigned (this_frame, regnum);
3195 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3196 if (IS_THUMB_ADDR (lr))
3200 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3203 internal_error (__FILE__, __LINE__,
3204 _("Unexpected register %d"), regnum);
3209 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3210 struct dwarf2_frame_state_reg *reg,
3211 struct frame_info *this_frame)
3217 reg->how = DWARF2_FRAME_REG_FN;
3218 reg->loc.fn = arm_dwarf2_prev_register;
3221 reg->how = DWARF2_FRAME_REG_CFA;
3226 /* Implement the stack_frame_destroyed_p gdbarch method. */
3229 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3231 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3232 unsigned int insn, insn2;
3233 int found_return = 0, found_stack_adjust = 0;
3234 CORE_ADDR func_start, func_end;
3238 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3241 /* The epilogue is a sequence of instructions along the following lines:
3243 - add stack frame size to SP or FP
3244 - [if frame pointer used] restore SP from FP
3245 - restore registers from SP [may include PC]
3246 - a return-type instruction [if PC wasn't already restored]
3248 In a first pass, we scan forward from the current PC and verify the
3249 instructions we find as compatible with this sequence, ending in a
3252 However, this is not sufficient to distinguish indirect function calls
3253 within a function from indirect tail calls in the epilogue in some cases.
3254 Therefore, if we didn't already find any SP-changing instruction during
3255 forward scan, we add a backward scanning heuristic to ensure we actually
3256 are in the epilogue. */
3259 while (scan_pc < func_end && !found_return)
3261 if (target_read_memory (scan_pc, buf, 2))
3265 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3267 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3269 else if (insn == 0x46f7) /* mov pc, lr */
3271 else if (thumb_instruction_restores_sp (insn))
3273 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3276 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3278 if (target_read_memory (scan_pc, buf, 2))
3282 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3284 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3286 if (insn2 & 0x8000) /* <registers> include PC. */
3289 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3290 && (insn2 & 0x0fff) == 0x0b04)
3292 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3295 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3296 && (insn2 & 0x0e00) == 0x0a00)
3308 /* Since any instruction in the epilogue sequence, with the possible
3309 exception of return itself, updates the stack pointer, we need to
3310 scan backwards for at most one instruction. Try either a 16-bit or
3311 a 32-bit instruction. This is just a heuristic, so we do not worry
3312 too much about false positives. */
3314 if (pc - 4 < func_start)
3316 if (target_read_memory (pc - 4, buf, 4))
3319 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3320 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3322 if (thumb_instruction_restores_sp (insn2))
3323 found_stack_adjust = 1;
3324 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3325 found_stack_adjust = 1;
3326 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3327 && (insn2 & 0x0fff) == 0x0b04)
3328 found_stack_adjust = 1;
3329 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3330 && (insn2 & 0x0e00) == 0x0a00)
3331 found_stack_adjust = 1;
3333 return found_stack_adjust;
3336 /* Implement the stack_frame_destroyed_p gdbarch method. */
3339 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3341 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3344 CORE_ADDR func_start, func_end;
3346 if (arm_pc_is_thumb (gdbarch, pc))
3347 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3349 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3352 /* We are in the epilogue if the previous instruction was a stack
3353 adjustment and the next instruction is a possible return (bx, mov
3354 pc, or pop). We could have to scan backwards to find the stack
3355 adjustment, or forwards to find the return, but this is a decent
3356 approximation. First scan forwards. */
3359 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3360 if (bits (insn, 28, 31) != INST_NV)
3362 if ((insn & 0x0ffffff0) == 0x012fff10)
3365 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3368 else if ((insn & 0x0fff0000) == 0x08bd0000
3369 && (insn & 0x0000c000) != 0)
3370 /* POP (LDMIA), including PC or LR. */
3377 /* Scan backwards. This is just a heuristic, so do not worry about
3378 false positives from mode changes. */
3380 if (pc < func_start + 4)
3383 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3384 if (arm_instruction_restores_sp (insn))
3391 /* When arguments must be pushed onto the stack, they go on in reverse
3392 order. The code below implements a FILO (stack) to do this. */
3397 struct stack_item *prev;
3401 static struct stack_item *
3402 push_stack_item (struct stack_item *prev, const void *contents, int len)
3404 struct stack_item *si;
3405 si = xmalloc (sizeof (struct stack_item));
3406 si->data = xmalloc (len);
3409 memcpy (si->data, contents, len);
3413 static struct stack_item *
3414 pop_stack_item (struct stack_item *si)
3416 struct stack_item *dead = si;
3424 /* Return the alignment (in bytes) of the given type. */
3427 arm_type_align (struct type *t)
3433 t = check_typedef (t);
3434 switch (TYPE_CODE (t))
3437 /* Should never happen. */
3438 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3442 case TYPE_CODE_ENUM:
3446 case TYPE_CODE_RANGE:
3448 case TYPE_CODE_CHAR:
3449 case TYPE_CODE_BOOL:
3450 return TYPE_LENGTH (t);
3452 case TYPE_CODE_ARRAY:
3453 case TYPE_CODE_COMPLEX:
3454 /* TODO: What about vector types? */
3455 return arm_type_align (TYPE_TARGET_TYPE (t));
3457 case TYPE_CODE_STRUCT:
3458 case TYPE_CODE_UNION:
3460 for (n = 0; n < TYPE_NFIELDS (t); n++)
3462 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3470 /* Possible base types for a candidate for passing and returning in
3473 enum arm_vfp_cprc_base_type
3482 /* The length of one element of base type B. */
3485 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3489 case VFP_CPRC_SINGLE:
3491 case VFP_CPRC_DOUBLE:
3493 case VFP_CPRC_VEC64:
3495 case VFP_CPRC_VEC128:
3498 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3503 /* The character ('s', 'd' or 'q') for the type of VFP register used
3504 for passing base type B. */
3507 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3511 case VFP_CPRC_SINGLE:
3513 case VFP_CPRC_DOUBLE:
3515 case VFP_CPRC_VEC64:
3517 case VFP_CPRC_VEC128:
3520 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3525 /* Determine whether T may be part of a candidate for passing and
3526 returning in VFP registers, ignoring the limit on the total number
3527 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3528 classification of the first valid component found; if it is not
3529 VFP_CPRC_UNKNOWN, all components must have the same classification
3530 as *BASE_TYPE. If it is found that T contains a type not permitted
3531 for passing and returning in VFP registers, a type differently
3532 classified from *BASE_TYPE, or two types differently classified
3533 from each other, return -1, otherwise return the total number of
3534 base-type elements found (possibly 0 in an empty structure or
3535 array). Vector types are not currently supported, matching the
3536 generic AAPCS support. */
3539 arm_vfp_cprc_sub_candidate (struct type *t,
3540 enum arm_vfp_cprc_base_type *base_type)
3542 t = check_typedef (t);
3543 switch (TYPE_CODE (t))
3546 switch (TYPE_LENGTH (t))
3549 if (*base_type == VFP_CPRC_UNKNOWN)
3550 *base_type = VFP_CPRC_SINGLE;
3551 else if (*base_type != VFP_CPRC_SINGLE)
3556 if (*base_type == VFP_CPRC_UNKNOWN)
3557 *base_type = VFP_CPRC_DOUBLE;
3558 else if (*base_type != VFP_CPRC_DOUBLE)
3567 case TYPE_CODE_COMPLEX:
3568 /* Arguments of complex T where T is one of the types float or
3569 double get treated as if they are implemented as:
3578 switch (TYPE_LENGTH (t))
3581 if (*base_type == VFP_CPRC_UNKNOWN)
3582 *base_type = VFP_CPRC_SINGLE;
3583 else if (*base_type != VFP_CPRC_SINGLE)
3588 if (*base_type == VFP_CPRC_UNKNOWN)
3589 *base_type = VFP_CPRC_DOUBLE;
3590 else if (*base_type != VFP_CPRC_DOUBLE)
3599 case TYPE_CODE_ARRAY:
3603 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3606 if (TYPE_LENGTH (t) == 0)
3608 gdb_assert (count == 0);
3611 else if (count == 0)
3613 unitlen = arm_vfp_cprc_unit_length (*base_type);
3614 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3615 return TYPE_LENGTH (t) / unitlen;
3619 case TYPE_CODE_STRUCT:
3624 for (i = 0; i < TYPE_NFIELDS (t); i++)
3626 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3628 if (sub_count == -1)
3632 if (TYPE_LENGTH (t) == 0)
3634 gdb_assert (count == 0);
3637 else if (count == 0)
3639 unitlen = arm_vfp_cprc_unit_length (*base_type);
3640 if (TYPE_LENGTH (t) != unitlen * count)
3645 case TYPE_CODE_UNION:
3650 for (i = 0; i < TYPE_NFIELDS (t); i++)
3652 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3654 if (sub_count == -1)
3656 count = (count > sub_count ? count : sub_count);
3658 if (TYPE_LENGTH (t) == 0)
3660 gdb_assert (count == 0);
3663 else if (count == 0)
3665 unitlen = arm_vfp_cprc_unit_length (*base_type);
3666 if (TYPE_LENGTH (t) != unitlen * count)
3678 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3679 if passed to or returned from a non-variadic function with the VFP
3680 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3681 *BASE_TYPE to the base type for T and *COUNT to the number of
3682 elements of that base type before returning. */
3685 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3688 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3689 int c = arm_vfp_cprc_sub_candidate (t, &b);
3690 if (c <= 0 || c > 4)
3697 /* Return 1 if the VFP ABI should be used for passing arguments to and
3698 returning values from a function of type FUNC_TYPE, 0
3702 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3704 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3705 /* Variadic functions always use the base ABI. Assume that functions
3706 without debug info are not variadic. */
3707 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3709 /* The VFP ABI is only supported as a variant of AAPCS. */
3710 if (tdep->arm_abi != ARM_ABI_AAPCS)
3712 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3715 /* We currently only support passing parameters in integer registers, which
3716 conforms with GCC's default model, and VFP argument passing following
3717 the VFP variant of AAPCS. Several other variants exist and
3718 we should probably support some of them based on the selected ABI. */
3721 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3722 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3723 struct value **args, CORE_ADDR sp, int struct_return,
3724 CORE_ADDR struct_addr)
3726 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3730 struct stack_item *si = NULL;
3733 unsigned vfp_regs_free = (1 << 16) - 1;
3735 /* Determine the type of this function and whether the VFP ABI
3737 ftype = check_typedef (value_type (function));
3738 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3739 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3740 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3742 /* Set the return address. For the ARM, the return breakpoint is
3743 always at BP_ADDR. */
3744 if (arm_pc_is_thumb (gdbarch, bp_addr))
3746 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3748 /* Walk through the list of args and determine how large a temporary
3749 stack is required. Need to take care here as structs may be
3750 passed on the stack, and we have to push them. */
3753 argreg = ARM_A1_REGNUM;
3756 /* The struct_return pointer occupies the first parameter
3757 passing register. */
3761 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3762 gdbarch_register_name (gdbarch, argreg),
3763 paddress (gdbarch, struct_addr));
3764 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3768 for (argnum = 0; argnum < nargs; argnum++)
3771 struct type *arg_type;
3772 struct type *target_type;
3773 enum type_code typecode;
3774 const bfd_byte *val;
3776 enum arm_vfp_cprc_base_type vfp_base_type;
3778 int may_use_core_reg = 1;
3780 arg_type = check_typedef (value_type (args[argnum]));
3781 len = TYPE_LENGTH (arg_type);
3782 target_type = TYPE_TARGET_TYPE (arg_type);
3783 typecode = TYPE_CODE (arg_type);
3784 val = value_contents (args[argnum]);
3786 align = arm_type_align (arg_type);
3787 /* Round alignment up to a whole number of words. */
3788 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3789 /* Different ABIs have different maximum alignments. */
3790 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3792 /* The APCS ABI only requires word alignment. */
3793 align = INT_REGISTER_SIZE;
3797 /* The AAPCS requires at most doubleword alignment. */
3798 if (align > INT_REGISTER_SIZE * 2)
3799 align = INT_REGISTER_SIZE * 2;
3803 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3811 /* Because this is a CPRC it cannot go in a core register or
3812 cause a core register to be skipped for alignment.
3813 Either it goes in VFP registers and the rest of this loop
3814 iteration is skipped for this argument, or it goes on the
3815 stack (and the stack alignment code is correct for this
3817 may_use_core_reg = 0;
3819 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3820 shift = unit_length / 4;
3821 mask = (1 << (shift * vfp_base_count)) - 1;
3822 for (regno = 0; regno < 16; regno += shift)
3823 if (((vfp_regs_free >> regno) & mask) == mask)
3832 vfp_regs_free &= ~(mask << regno);
3833 reg_scaled = regno / shift;
3834 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3835 for (i = 0; i < vfp_base_count; i++)
3839 if (reg_char == 'q')
3840 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3841 val + i * unit_length);
3844 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3845 reg_char, reg_scaled + i);
3846 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3848 regcache_cooked_write (regcache, regnum,
3849 val + i * unit_length);
3856 /* This CPRC could not go in VFP registers, so all VFP
3857 registers are now marked as used. */
3862 /* Push stack padding for dowubleword alignment. */
3863 if (nstack & (align - 1))
3865 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3866 nstack += INT_REGISTER_SIZE;
3869 /* Doubleword aligned quantities must go in even register pairs. */
3870 if (may_use_core_reg
3871 && argreg <= ARM_LAST_ARG_REGNUM
3872 && align > INT_REGISTER_SIZE
3876 /* If the argument is a pointer to a function, and it is a
3877 Thumb function, create a LOCAL copy of the value and set
3878 the THUMB bit in it. */
3879 if (TYPE_CODE_PTR == typecode
3880 && target_type != NULL
3881 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3883 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3884 if (arm_pc_is_thumb (gdbarch, regval))
3886 bfd_byte *copy = alloca (len);
3887 store_unsigned_integer (copy, len, byte_order,
3888 MAKE_THUMB_ADDR (regval));
3893 /* Copy the argument to general registers or the stack in
3894 register-sized pieces. Large arguments are split between
3895 registers and stack. */
3898 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3900 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3902 /* The argument is being passed in a general purpose
3905 = extract_unsigned_integer (val, partial_len, byte_order);
3906 if (byte_order == BFD_ENDIAN_BIG)
3907 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3909 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3911 gdbarch_register_name
3913 phex (regval, INT_REGISTER_SIZE));
3914 regcache_cooked_write_unsigned (regcache, argreg, regval);
3919 /* Push the arguments onto the stack. */
3921 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3923 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3924 nstack += INT_REGISTER_SIZE;
3931 /* If we have an odd number of words to push, then decrement the stack
3932 by one word now, so first stack argument will be dword aligned. */
3939 write_memory (sp, si->data, si->len);
3940 si = pop_stack_item (si);
3943 /* Finally, update teh SP register. */
3944 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3950 /* Always align the frame to an 8-byte boundary. This is required on
3951 some platforms and harmless on the rest. */
3954 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3956 /* Align the stack to eight bytes. */
3957 return sp & ~ (CORE_ADDR) 7;
3961 print_fpu_flags (struct ui_file *file, int flags)
3963 if (flags & (1 << 0))
3964 fputs_filtered ("IVO ", file);
3965 if (flags & (1 << 1))
3966 fputs_filtered ("DVZ ", file);
3967 if (flags & (1 << 2))
3968 fputs_filtered ("OFL ", file);
3969 if (flags & (1 << 3))
3970 fputs_filtered ("UFL ", file);
3971 if (flags & (1 << 4))
3972 fputs_filtered ("INX ", file);
3973 fputc_filtered ('\n', file);
3976 /* Print interesting information about the floating point processor
3977 (if present) or emulator. */
3979 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3980 struct frame_info *frame, const char *args)
3982 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3985 type = (status >> 24) & 127;
3986 if (status & (1 << 31))
3987 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3989 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3990 /* i18n: [floating point unit] mask */
3991 fputs_filtered (_("mask: "), file);
3992 print_fpu_flags (file, status >> 16);
3993 /* i18n: [floating point unit] flags */
3994 fputs_filtered (_("flags: "), file);
3995 print_fpu_flags (file, status);
3998 /* Construct the ARM extended floating point type. */
3999 static struct type *
4000 arm_ext_type (struct gdbarch *gdbarch)
4002 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4004 if (!tdep->arm_ext_type)
4006 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
4007 floatformats_arm_ext);
4009 return tdep->arm_ext_type;
4012 static struct type *
4013 arm_neon_double_type (struct gdbarch *gdbarch)
4015 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4017 if (tdep->neon_double_type == NULL)
4019 struct type *t, *elem;
4021 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
4023 elem = builtin_type (gdbarch)->builtin_uint8;
4024 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
4025 elem = builtin_type (gdbarch)->builtin_uint16;
4026 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
4027 elem = builtin_type (gdbarch)->builtin_uint32;
4028 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
4029 elem = builtin_type (gdbarch)->builtin_uint64;
4030 append_composite_type_field (t, "u64", elem);
4031 elem = builtin_type (gdbarch)->builtin_float;
4032 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
4033 elem = builtin_type (gdbarch)->builtin_double;
4034 append_composite_type_field (t, "f64", elem);
4036 TYPE_VECTOR (t) = 1;
4037 TYPE_NAME (t) = "neon_d";
4038 tdep->neon_double_type = t;
4041 return tdep->neon_double_type;
4044 /* FIXME: The vector types are not correctly ordered on big-endian
4045 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4046 bits of d0 - regardless of what unit size is being held in d0. So
4047 the offset of the first uint8 in d0 is 7, but the offset of the
4048 first float is 4. This code works as-is for little-endian
4051 static struct type *
4052 arm_neon_quad_type (struct gdbarch *gdbarch)
4054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4056 if (tdep->neon_quad_type == NULL)
4058 struct type *t, *elem;
4060 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4062 elem = builtin_type (gdbarch)->builtin_uint8;
4063 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4064 elem = builtin_type (gdbarch)->builtin_uint16;
4065 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4066 elem = builtin_type (gdbarch)->builtin_uint32;
4067 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4068 elem = builtin_type (gdbarch)->builtin_uint64;
4069 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4070 elem = builtin_type (gdbarch)->builtin_float;
4071 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4072 elem = builtin_type (gdbarch)->builtin_double;
4073 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4075 TYPE_VECTOR (t) = 1;
4076 TYPE_NAME (t) = "neon_q";
4077 tdep->neon_quad_type = t;
4080 return tdep->neon_quad_type;
4083 /* Return the GDB type object for the "standard" data type of data in
4086 static struct type *
4087 arm_register_type (struct gdbarch *gdbarch, int regnum)
4089 int num_regs = gdbarch_num_regs (gdbarch);
4091 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4092 && regnum >= num_regs && regnum < num_regs + 32)
4093 return builtin_type (gdbarch)->builtin_float;
4095 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4096 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4097 return arm_neon_quad_type (gdbarch);
4099 /* If the target description has register information, we are only
4100 in this function so that we can override the types of
4101 double-precision registers for NEON. */
4102 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4104 struct type *t = tdesc_register_type (gdbarch, regnum);
4106 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4107 && TYPE_CODE (t) == TYPE_CODE_FLT
4108 && gdbarch_tdep (gdbarch)->have_neon)
4109 return arm_neon_double_type (gdbarch);
4114 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4116 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4117 return builtin_type (gdbarch)->builtin_void;
4119 return arm_ext_type (gdbarch);
4121 else if (regnum == ARM_SP_REGNUM)
4122 return builtin_type (gdbarch)->builtin_data_ptr;
4123 else if (regnum == ARM_PC_REGNUM)
4124 return builtin_type (gdbarch)->builtin_func_ptr;
4125 else if (regnum >= ARRAY_SIZE (arm_register_names))
4126 /* These registers are only supported on targets which supply
4127 an XML description. */
4128 return builtin_type (gdbarch)->builtin_int0;
4130 return builtin_type (gdbarch)->builtin_uint32;
4133 /* Map a DWARF register REGNUM onto the appropriate GDB register
4137 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4139 /* Core integer regs. */
4140 if (reg >= 0 && reg <= 15)
4143 /* Legacy FPA encoding. These were once used in a way which
4144 overlapped with VFP register numbering, so their use is
4145 discouraged, but GDB doesn't support the ARM toolchain
4146 which used them for VFP. */
4147 if (reg >= 16 && reg <= 23)
4148 return ARM_F0_REGNUM + reg - 16;
4150 /* New assignments for the FPA registers. */
4151 if (reg >= 96 && reg <= 103)
4152 return ARM_F0_REGNUM + reg - 96;
4154 /* WMMX register assignments. */
4155 if (reg >= 104 && reg <= 111)
4156 return ARM_WCGR0_REGNUM + reg - 104;
4158 if (reg >= 112 && reg <= 127)
4159 return ARM_WR0_REGNUM + reg - 112;
4161 if (reg >= 192 && reg <= 199)
4162 return ARM_WC0_REGNUM + reg - 192;
4164 /* VFP v2 registers. A double precision value is actually
4165 in d1 rather than s2, but the ABI only defines numbering
4166 for the single precision registers. This will "just work"
4167 in GDB for little endian targets (we'll read eight bytes,
4168 starting in s0 and then progressing to s1), but will be
4169 reversed on big endian targets with VFP. This won't
4170 be a problem for the new Neon quad registers; you're supposed
4171 to use DW_OP_piece for those. */
4172 if (reg >= 64 && reg <= 95)
4176 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4177 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4181 /* VFP v3 / Neon registers. This range is also used for VFP v2
4182 registers, except that it now describes d0 instead of s0. */
4183 if (reg >= 256 && reg <= 287)
4187 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4188 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4195 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4197 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4200 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4202 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4203 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4205 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4206 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4208 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4209 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4211 if (reg < NUM_GREGS)
4212 return SIM_ARM_R0_REGNUM + reg;
4215 if (reg < NUM_FREGS)
4216 return SIM_ARM_FP0_REGNUM + reg;
4219 if (reg < NUM_SREGS)
4220 return SIM_ARM_FPS_REGNUM + reg;
4223 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4226 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4227 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4228 It is thought that this is is the floating-point register format on
4229 little-endian systems. */
4232 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4233 void *dbl, int endianess)
4237 if (endianess == BFD_ENDIAN_BIG)
4238 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4240 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4242 floatformat_from_doublest (fmt, &d, dbl);
4246 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4251 floatformat_to_doublest (fmt, ptr, &d);
4252 if (endianess == BFD_ENDIAN_BIG)
4253 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4255 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4260 condition_true (unsigned long cond, unsigned long status_reg)
4262 if (cond == INST_AL || cond == INST_NV)
4268 return ((status_reg & FLAG_Z) != 0);
4270 return ((status_reg & FLAG_Z) == 0);
4272 return ((status_reg & FLAG_C) != 0);
4274 return ((status_reg & FLAG_C) == 0);
4276 return ((status_reg & FLAG_N) != 0);
4278 return ((status_reg & FLAG_N) == 0);
4280 return ((status_reg & FLAG_V) != 0);
4282 return ((status_reg & FLAG_V) == 0);
4284 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4286 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4288 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4290 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4292 return (((status_reg & FLAG_Z) == 0)
4293 && (((status_reg & FLAG_N) == 0)
4294 == ((status_reg & FLAG_V) == 0)));
4296 return (((status_reg & FLAG_Z) != 0)
4297 || (((status_reg & FLAG_N) == 0)
4298 != ((status_reg & FLAG_V) == 0)));
4303 static unsigned long
4304 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4305 unsigned long pc_val, unsigned long status_reg)
4307 unsigned long res, shift;
4308 int rm = bits (inst, 0, 3);
4309 unsigned long shifttype = bits (inst, 5, 6);
4313 int rs = bits (inst, 8, 11);
4314 shift = (rs == 15 ? pc_val + 8
4315 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4318 shift = bits (inst, 7, 11);
4320 res = (rm == ARM_PC_REGNUM
4321 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4322 : get_frame_register_unsigned (frame, rm));
4327 res = shift >= 32 ? 0 : res << shift;
4331 res = shift >= 32 ? 0 : res >> shift;
4337 res = ((res & 0x80000000L)
4338 ? ~((~res) >> shift) : res >> shift);
4341 case 3: /* ROR/RRX */
4344 res = (res >> 1) | (carry ? 0x80000000L : 0);
4346 res = (res >> shift) | (res << (32 - shift));
4350 return res & 0xffffffff;
4353 /* Return number of 1-bits in VAL. */
4356 bitcount (unsigned long val)
4359 for (nbits = 0; val != 0; nbits++)
4360 val &= val - 1; /* Delete rightmost 1-bit in val. */
4364 /* Return the size in bytes of the complete Thumb instruction whose
4365 first halfword is INST1. */
4368 thumb_insn_size (unsigned short inst1)
4370 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4377 thumb_advance_itstate (unsigned int itstate)
4379 /* Preserve IT[7:5], the first three bits of the condition. Shift
4380 the upcoming condition flags left by one bit. */
4381 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4383 /* If we have finished the IT block, clear the state. */
4384 if ((itstate & 0x0f) == 0)
4390 /* Find the next PC after the current instruction executes. In some
4391 cases we can not statically determine the answer (see the IT state
4392 handling in this function); in that case, a breakpoint may be
4393 inserted in addition to the returned PC, which will be used to set
4394 another breakpoint by our caller. */
4397 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4399 struct gdbarch *gdbarch = get_frame_arch (frame);
4400 struct address_space *aspace = get_frame_address_space (frame);
4401 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4402 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4403 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4404 unsigned short inst1;
4405 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4406 unsigned long offset;
4407 ULONGEST status, itstate;
4409 nextpc = MAKE_THUMB_ADDR (nextpc);
4410 pc_val = MAKE_THUMB_ADDR (pc_val);
4412 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4414 /* Thumb-2 conditional execution support. There are eight bits in
4415 the CPSR which describe conditional execution state. Once
4416 reconstructed (they're in a funny order), the low five bits
4417 describe the low bit of the condition for each instruction and
4418 how many instructions remain. The high three bits describe the
4419 base condition. One of the low four bits will be set if an IT
4420 block is active. These bits read as zero on earlier
4422 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4423 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4425 /* If-Then handling. On GNU/Linux, where this routine is used, we
4426 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4427 can disable execution of the undefined instruction. So we might
4428 miss the breakpoint if we set it on a skipped conditional
4429 instruction. Because conditional instructions can change the
4430 flags, affecting the execution of further instructions, we may
4431 need to set two breakpoints. */
4433 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4435 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4437 /* An IT instruction. Because this instruction does not
4438 modify the flags, we can accurately predict the next
4439 executed instruction. */
4440 itstate = inst1 & 0x00ff;
4441 pc += thumb_insn_size (inst1);
4443 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4445 inst1 = read_memory_unsigned_integer (pc, 2,
4446 byte_order_for_code);
4447 pc += thumb_insn_size (inst1);
4448 itstate = thumb_advance_itstate (itstate);
4451 return MAKE_THUMB_ADDR (pc);
4453 else if (itstate != 0)
4455 /* We are in a conditional block. Check the condition. */
4456 if (! condition_true (itstate >> 4, status))
4458 /* Advance to the next executed instruction. */
4459 pc += thumb_insn_size (inst1);
4460 itstate = thumb_advance_itstate (itstate);
4462 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4464 inst1 = read_memory_unsigned_integer (pc, 2,
4465 byte_order_for_code);
4466 pc += thumb_insn_size (inst1);
4467 itstate = thumb_advance_itstate (itstate);
4470 return MAKE_THUMB_ADDR (pc);
4472 else if ((itstate & 0x0f) == 0x08)
4474 /* This is the last instruction of the conditional
4475 block, and it is executed. We can handle it normally
4476 because the following instruction is not conditional,
4477 and we must handle it normally because it is
4478 permitted to branch. Fall through. */
4484 /* There are conditional instructions after this one.
4485 If this instruction modifies the flags, then we can
4486 not predict what the next executed instruction will
4487 be. Fortunately, this instruction is architecturally
4488 forbidden to branch; we know it will fall through.
4489 Start by skipping past it. */
4490 pc += thumb_insn_size (inst1);
4491 itstate = thumb_advance_itstate (itstate);
4493 /* Set a breakpoint on the following instruction. */
4494 gdb_assert ((itstate & 0x0f) != 0);
4495 arm_insert_single_step_breakpoint (gdbarch, aspace,
4496 MAKE_THUMB_ADDR (pc));
4497 cond_negated = (itstate >> 4) & 1;
4499 /* Skip all following instructions with the same
4500 condition. If there is a later instruction in the IT
4501 block with the opposite condition, set the other
4502 breakpoint there. If not, then set a breakpoint on
4503 the instruction after the IT block. */
4506 inst1 = read_memory_unsigned_integer (pc, 2,
4507 byte_order_for_code);
4508 pc += thumb_insn_size (inst1);
4509 itstate = thumb_advance_itstate (itstate);
4511 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4513 return MAKE_THUMB_ADDR (pc);
4517 else if (itstate & 0x0f)
4519 /* We are in a conditional block. Check the condition. */
4520 int cond = itstate >> 4;
4522 if (! condition_true (cond, status))
4523 /* Advance to the next instruction. All the 32-bit
4524 instructions share a common prefix. */
4525 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4527 /* Otherwise, handle the instruction normally. */
4530 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4534 /* Fetch the saved PC from the stack. It's stored above
4535 all of the other registers. */
4536 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4537 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4538 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4540 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4542 unsigned long cond = bits (inst1, 8, 11);
4543 if (cond == 0x0f) /* 0x0f = SWI */
4545 struct gdbarch_tdep *tdep;
4546 tdep = gdbarch_tdep (gdbarch);
4548 if (tdep->syscall_next_pc != NULL)
4549 nextpc = tdep->syscall_next_pc (frame);
4552 else if (cond != 0x0f && condition_true (cond, status))
4553 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4555 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4557 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4559 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4561 unsigned short inst2;
4562 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4564 /* Default to the next instruction. */
4566 nextpc = MAKE_THUMB_ADDR (nextpc);
4568 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4570 /* Branches and miscellaneous control instructions. */
4572 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4575 int j1, j2, imm1, imm2;
4577 imm1 = sbits (inst1, 0, 10);
4578 imm2 = bits (inst2, 0, 10);
4579 j1 = bit (inst2, 13);
4580 j2 = bit (inst2, 11);
4582 offset = ((imm1 << 12) + (imm2 << 1));
4583 offset ^= ((!j2) << 22) | ((!j1) << 23);
4585 nextpc = pc_val + offset;
4586 /* For BLX make sure to clear the low bits. */
4587 if (bit (inst2, 12) == 0)
4588 nextpc = nextpc & 0xfffffffc;
4590 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4592 /* SUBS PC, LR, #imm8. */
4593 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4594 nextpc -= inst2 & 0x00ff;
4596 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4598 /* Conditional branch. */
4599 if (condition_true (bits (inst1, 6, 9), status))
4601 int sign, j1, j2, imm1, imm2;
4603 sign = sbits (inst1, 10, 10);
4604 imm1 = bits (inst1, 0, 5);
4605 imm2 = bits (inst2, 0, 10);
4606 j1 = bit (inst2, 13);
4607 j2 = bit (inst2, 11);
4609 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4610 offset += (imm1 << 12) + (imm2 << 1);
4612 nextpc = pc_val + offset;
4616 else if ((inst1 & 0xfe50) == 0xe810)
4618 /* Load multiple or RFE. */
4619 int rn, offset, load_pc = 1;
4621 rn = bits (inst1, 0, 3);
4622 if (bit (inst1, 7) && !bit (inst1, 8))
4625 if (!bit (inst2, 15))
4627 offset = bitcount (inst2) * 4 - 4;
4629 else if (!bit (inst1, 7) && bit (inst1, 8))
4632 if (!bit (inst2, 15))
4636 else if (bit (inst1, 7) && bit (inst1, 8))
4641 else if (!bit (inst1, 7) && !bit (inst1, 8))
4651 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4652 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4655 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4657 /* MOV PC or MOVS PC. */
4658 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4659 nextpc = MAKE_THUMB_ADDR (nextpc);
4661 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4665 int rn, load_pc = 1;
4667 rn = bits (inst1, 0, 3);
4668 base = get_frame_register_unsigned (frame, rn);
4669 if (rn == ARM_PC_REGNUM)
4671 base = (base + 4) & ~(CORE_ADDR) 0x3;
4673 base += bits (inst2, 0, 11);
4675 base -= bits (inst2, 0, 11);
4677 else if (bit (inst1, 7))
4678 base += bits (inst2, 0, 11);
4679 else if (bit (inst2, 11))
4681 if (bit (inst2, 10))
4684 base += bits (inst2, 0, 7);
4686 base -= bits (inst2, 0, 7);
4689 else if ((inst2 & 0x0fc0) == 0x0000)
4691 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4692 base += get_frame_register_unsigned (frame, rm) << shift;
4699 nextpc = get_frame_memory_unsigned (frame, base, 4);
4701 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4704 CORE_ADDR tbl_reg, table, offset, length;
4706 tbl_reg = bits (inst1, 0, 3);
4707 if (tbl_reg == 0x0f)
4708 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4710 table = get_frame_register_unsigned (frame, tbl_reg);
4712 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4713 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4714 nextpc = pc_val + length;
4716 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4719 CORE_ADDR tbl_reg, table, offset, length;
4721 tbl_reg = bits (inst1, 0, 3);
4722 if (tbl_reg == 0x0f)
4723 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4725 table = get_frame_register_unsigned (frame, tbl_reg);
4727 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4728 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4729 nextpc = pc_val + length;
4732 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4734 if (bits (inst1, 3, 6) == 0x0f)
4735 nextpc = UNMAKE_THUMB_ADDR (pc_val);
4737 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4739 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4741 if (bits (inst1, 3, 6) == 0x0f)
4744 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4746 nextpc = MAKE_THUMB_ADDR (nextpc);
4748 else if ((inst1 & 0xf500) == 0xb100)
4751 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4752 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4754 if (bit (inst1, 11) && reg != 0)
4755 nextpc = pc_val + imm;
4756 else if (!bit (inst1, 11) && reg == 0)
4757 nextpc = pc_val + imm;
4762 /* Get the raw next address. PC is the current program counter, in
4763 FRAME, which is assumed to be executing in ARM mode.
4765 The value returned has the execution state of the next instruction
4766 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4767 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4771 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4773 struct gdbarch *gdbarch = get_frame_arch (frame);
4774 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4775 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4776 unsigned long pc_val;
4777 unsigned long this_instr;
4778 unsigned long status;
4781 pc_val = (unsigned long) pc;
4782 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4784 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4785 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4787 if (bits (this_instr, 28, 31) == INST_NV)
4788 switch (bits (this_instr, 24, 27))
4793 /* Branch with Link and change to Thumb. */
4794 nextpc = BranchDest (pc, this_instr);
4795 nextpc |= bit (this_instr, 24) << 1;
4796 nextpc = MAKE_THUMB_ADDR (nextpc);
4802 /* Coprocessor register transfer. */
4803 if (bits (this_instr, 12, 15) == 15)
4804 error (_("Invalid update to pc in instruction"));
4807 else if (condition_true (bits (this_instr, 28, 31), status))
4809 switch (bits (this_instr, 24, 27))
4812 case 0x1: /* data processing */
4816 unsigned long operand1, operand2, result = 0;
4820 if (bits (this_instr, 12, 15) != 15)
4823 if (bits (this_instr, 22, 25) == 0
4824 && bits (this_instr, 4, 7) == 9) /* multiply */
4825 error (_("Invalid update to pc in instruction"));
4827 /* BX <reg>, BLX <reg> */
4828 if (bits (this_instr, 4, 27) == 0x12fff1
4829 || bits (this_instr, 4, 27) == 0x12fff3)
4831 rn = bits (this_instr, 0, 3);
4832 nextpc = ((rn == ARM_PC_REGNUM)
4834 : get_frame_register_unsigned (frame, rn));
4839 /* Multiply into PC. */
4840 c = (status & FLAG_C) ? 1 : 0;
4841 rn = bits (this_instr, 16, 19);
4842 operand1 = ((rn == ARM_PC_REGNUM)
4844 : get_frame_register_unsigned (frame, rn));
4846 if (bit (this_instr, 25))
4848 unsigned long immval = bits (this_instr, 0, 7);
4849 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4850 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4853 else /* operand 2 is a shifted register. */
4854 operand2 = shifted_reg_val (frame, this_instr, c,
4857 switch (bits (this_instr, 21, 24))
4860 result = operand1 & operand2;
4864 result = operand1 ^ operand2;
4868 result = operand1 - operand2;
4872 result = operand2 - operand1;
4876 result = operand1 + operand2;
4880 result = operand1 + operand2 + c;
4884 result = operand1 - operand2 + c;
4888 result = operand2 - operand1 + c;
4894 case 0xb: /* tst, teq, cmp, cmn */
4895 result = (unsigned long) nextpc;
4899 result = operand1 | operand2;
4903 /* Always step into a function. */
4908 result = operand1 & ~operand2;
4916 /* In 26-bit APCS the bottom two bits of the result are
4917 ignored, and we always end up in ARM state. */
4919 nextpc = arm_addr_bits_remove (gdbarch, result);
4927 case 0x5: /* data transfer */
4930 if (bit (this_instr, 20))
4933 if (bits (this_instr, 12, 15) == 15)
4939 if (bit (this_instr, 22))
4940 error (_("Invalid update to pc in instruction"));
4942 /* byte write to PC */
4943 rn = bits (this_instr, 16, 19);
4944 base = ((rn == ARM_PC_REGNUM)
4946 : get_frame_register_unsigned (frame, rn));
4948 if (bit (this_instr, 24))
4951 int c = (status & FLAG_C) ? 1 : 0;
4952 unsigned long offset =
4953 (bit (this_instr, 25)
4954 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4955 : bits (this_instr, 0, 11));
4957 if (bit (this_instr, 23))
4963 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4970 case 0x9: /* block transfer */
4971 if (bit (this_instr, 20))
4974 if (bit (this_instr, 15))
4978 unsigned long rn_val
4979 = get_frame_register_unsigned (frame,
4980 bits (this_instr, 16, 19));
4982 if (bit (this_instr, 23))
4985 unsigned long reglist = bits (this_instr, 0, 14);
4986 offset = bitcount (reglist) * 4;
4987 if (bit (this_instr, 24)) /* pre */
4990 else if (bit (this_instr, 24))
4994 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
5001 case 0xb: /* branch & link */
5002 case 0xa: /* branch */
5004 nextpc = BranchDest (pc, this_instr);
5010 case 0xe: /* coproc ops */
5014 struct gdbarch_tdep *tdep;
5015 tdep = gdbarch_tdep (gdbarch);
5017 if (tdep->syscall_next_pc != NULL)
5018 nextpc = tdep->syscall_next_pc (frame);
5024 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
5032 /* Determine next PC after current instruction executes. Will call either
5033 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5034 loop is detected. */
5037 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
5041 if (arm_frame_is_thumb (frame))
5042 nextpc = thumb_get_next_pc_raw (frame, pc);
5044 nextpc = arm_get_next_pc_raw (frame, pc);
5049 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5050 of the appropriate mode (as encoded in the PC value), even if this
5051 differs from what would be expected according to the symbol tables. */
5054 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
5055 struct address_space *aspace,
5058 struct cleanup *old_chain
5059 = make_cleanup_restore_integer (&arm_override_mode);
5061 arm_override_mode = IS_THUMB_ADDR (pc);
5062 pc = gdbarch_addr_bits_remove (gdbarch, pc);
5064 insert_single_step_breakpoint (gdbarch, aspace, pc);
5066 do_cleanups (old_chain);
5069 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5070 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5071 is found, attempt to step through it. A breakpoint is placed at the end of
5075 thumb_deal_with_atomic_sequence_raw (struct frame_info *frame)
5077 struct gdbarch *gdbarch = get_frame_arch (frame);
5078 struct address_space *aspace = get_frame_address_space (frame);
5079 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5080 CORE_ADDR pc = get_frame_pc (frame);
5081 CORE_ADDR breaks[2] = {-1, -1};
5083 unsigned short insn1, insn2;
5086 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5087 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5088 ULONGEST status, itstate;
5090 /* We currently do not support atomic sequences within an IT block. */
5091 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
5092 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5096 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5097 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5099 if (thumb_insn_size (insn1) != 4)
5102 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5104 if (!((insn1 & 0xfff0) == 0xe850
5105 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5108 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5110 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5112 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5115 if (thumb_insn_size (insn1) != 4)
5117 /* Assume that there is at most one conditional branch in the
5118 atomic sequence. If a conditional branch is found, put a
5119 breakpoint in its destination address. */
5120 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
5122 if (last_breakpoint > 0)
5123 return 0; /* More than one conditional branch found,
5124 fallback to the standard code. */
5126 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
5130 /* We do not support atomic sequences that use any *other*
5131 instructions but conditional branches to change the PC.
5132 Fall back to standard code to avoid losing control of
5134 else if (thumb_instruction_changes_pc (insn1))
5139 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5142 /* Assume that there is at most one conditional branch in the
5143 atomic sequence. If a conditional branch is found, put a
5144 breakpoint in its destination address. */
5145 if ((insn1 & 0xf800) == 0xf000
5146 && (insn2 & 0xd000) == 0x8000
5147 && (insn1 & 0x0380) != 0x0380)
5149 int sign, j1, j2, imm1, imm2;
5150 unsigned int offset;
5152 sign = sbits (insn1, 10, 10);
5153 imm1 = bits (insn1, 0, 5);
5154 imm2 = bits (insn2, 0, 10);
5155 j1 = bit (insn2, 13);
5156 j2 = bit (insn2, 11);
5158 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5159 offset += (imm1 << 12) + (imm2 << 1);
5161 if (last_breakpoint > 0)
5162 return 0; /* More than one conditional branch found,
5163 fallback to the standard code. */
5165 breaks[1] = loc + offset;
5169 /* We do not support atomic sequences that use any *other*
5170 instructions but conditional branches to change the PC.
5171 Fall back to standard code to avoid losing control of
5173 else if (thumb2_instruction_changes_pc (insn1, insn2))
5176 /* If we find a strex{,b,h,d}, we're done. */
5177 if ((insn1 & 0xfff0) == 0xe840
5178 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5183 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5184 if (insn_count == atomic_sequence_length)
5187 /* Insert a breakpoint right after the end of the atomic sequence. */
5190 /* Check for duplicated breakpoints. Check also for a breakpoint
5191 placed (branch instruction's destination) anywhere in sequence. */
5193 && (breaks[1] == breaks[0]
5194 || (breaks[1] >= pc && breaks[1] < loc)))
5195 last_breakpoint = 0;
5197 /* Effectively inserts the breakpoints. */
5198 for (index = 0; index <= last_breakpoint; index++)
5199 arm_insert_single_step_breakpoint (gdbarch, aspace,
5200 MAKE_THUMB_ADDR (breaks[index]));
5206 arm_deal_with_atomic_sequence_raw (struct frame_info *frame)
5208 struct gdbarch *gdbarch = get_frame_arch (frame);
5209 struct address_space *aspace = get_frame_address_space (frame);
5210 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5211 CORE_ADDR pc = get_frame_pc (frame);
5212 CORE_ADDR breaks[2] = {-1, -1};
5217 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5218 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5220 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5221 Note that we do not currently support conditionally executed atomic
5223 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5225 if ((insn & 0xff9000f0) != 0xe1900090)
5228 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5230 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5232 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5235 /* Assume that there is at most one conditional branch in the atomic
5236 sequence. If a conditional branch is found, put a breakpoint in
5237 its destination address. */
5238 if (bits (insn, 24, 27) == 0xa)
5240 if (last_breakpoint > 0)
5241 return 0; /* More than one conditional branch found, fallback
5242 to the standard single-step code. */
5244 breaks[1] = BranchDest (loc - 4, insn);
5248 /* We do not support atomic sequences that use any *other* instructions
5249 but conditional branches to change the PC. Fall back to standard
5250 code to avoid losing control of execution. */
5251 else if (arm_instruction_changes_pc (insn))
5254 /* If we find a strex{,b,h,d}, we're done. */
5255 if ((insn & 0xff9000f0) == 0xe1800090)
5259 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5260 if (insn_count == atomic_sequence_length)
5263 /* Insert a breakpoint right after the end of the atomic sequence. */
5266 /* Check for duplicated breakpoints. Check also for a breakpoint
5267 placed (branch instruction's destination) anywhere in sequence. */
5269 && (breaks[1] == breaks[0]
5270 || (breaks[1] >= pc && breaks[1] < loc)))
5271 last_breakpoint = 0;
5273 /* Effectively inserts the breakpoints. */
5274 for (index = 0; index <= last_breakpoint; index++)
5275 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5281 arm_deal_with_atomic_sequence (struct frame_info *frame)
5283 if (arm_frame_is_thumb (frame))
5284 return thumb_deal_with_atomic_sequence_raw (frame);
5286 return arm_deal_with_atomic_sequence_raw (frame);
5289 /* single_step() is called just before we want to resume the inferior,
5290 if we want to single-step it but there is no hardware or kernel
5291 single-step support. We find the target of the coming instruction
5292 and breakpoint it. */
5295 arm_software_single_step (struct frame_info *frame)
5297 struct gdbarch *gdbarch = get_frame_arch (frame);
5298 struct address_space *aspace = get_frame_address_space (frame);
5301 if (arm_deal_with_atomic_sequence (frame))
5304 next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
5305 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5310 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5311 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5312 NULL if an error occurs. BUF is freed. */
5315 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5316 int old_len, int new_len)
5319 int bytes_to_read = new_len - old_len;
5321 new_buf = xmalloc (new_len);
5322 memcpy (new_buf + bytes_to_read, buf, old_len);
5324 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5332 /* An IT block is at most the 2-byte IT instruction followed by
5333 four 4-byte instructions. The furthest back we must search to
5334 find an IT block that affects the current instruction is thus
5335 2 + 3 * 4 == 14 bytes. */
5336 #define MAX_IT_BLOCK_PREFIX 14
5338 /* Use a quick scan if there are more than this many bytes of
5340 #define IT_SCAN_THRESHOLD 32
5342 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5343 A breakpoint in an IT block may not be hit, depending on the
5346 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5350 CORE_ADDR boundary, func_start;
5352 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5353 int i, any, last_it, last_it_count;
5355 /* If we are using BKPT breakpoints, none of this is necessary. */
5356 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5359 /* ARM mode does not have this problem. */
5360 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5363 /* We are setting a breakpoint in Thumb code that could potentially
5364 contain an IT block. The first step is to find how much Thumb
5365 code there is; we do not need to read outside of known Thumb
5367 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5369 /* Thumb-2 code must have mapping symbols to have a chance. */
5372 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5374 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5375 && func_start > boundary)
5376 boundary = func_start;
5378 /* Search for a candidate IT instruction. We have to do some fancy
5379 footwork to distinguish a real IT instruction from the second
5380 half of a 32-bit instruction, but there is no need for that if
5381 there's no candidate. */
5382 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5384 /* No room for an IT instruction. */
5387 buf = xmalloc (buf_len);
5388 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5391 for (i = 0; i < buf_len; i += 2)
5393 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5394 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5406 /* OK, the code bytes before this instruction contain at least one
5407 halfword which resembles an IT instruction. We know that it's
5408 Thumb code, but there are still two possibilities. Either the
5409 halfword really is an IT instruction, or it is the second half of
5410 a 32-bit Thumb instruction. The only way we can tell is to
5411 scan forwards from a known instruction boundary. */
5412 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5416 /* There's a lot of code before this instruction. Start with an
5417 optimistic search; it's easy to recognize halfwords that can
5418 not be the start of a 32-bit instruction, and use that to
5419 lock on to the instruction boundaries. */
5420 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5423 buf_len = IT_SCAN_THRESHOLD;
5426 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5428 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5429 if (thumb_insn_size (inst1) == 2)
5436 /* At this point, if DEFINITE, BUF[I] is the first place we
5437 are sure that we know the instruction boundaries, and it is far
5438 enough from BPADDR that we could not miss an IT instruction
5439 affecting BPADDR. If ! DEFINITE, give up - start from a
5443 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5447 buf_len = bpaddr - boundary;
5453 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5456 buf_len = bpaddr - boundary;
5460 /* Scan forwards. Find the last IT instruction before BPADDR. */
5465 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5467 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5472 else if (inst1 & 0x0002)
5474 else if (inst1 & 0x0004)
5479 i += thumb_insn_size (inst1);
5485 /* There wasn't really an IT instruction after all. */
5488 if (last_it_count < 1)
5489 /* It was too far away. */
5492 /* This really is a trouble spot. Move the breakpoint to the IT
5494 return bpaddr - buf_len + last_it;
5497 /* ARM displaced stepping support.
5499 Generally ARM displaced stepping works as follows:
5501 1. When an instruction is to be single-stepped, it is first decoded by
5502 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5503 Depending on the type of instruction, it is then copied to a scratch
5504 location, possibly in a modified form. The copy_* set of functions
5505 performs such modification, as necessary. A breakpoint is placed after
5506 the modified instruction in the scratch space to return control to GDB.
5507 Note in particular that instructions which modify the PC will no longer
5508 do so after modification.
5510 2. The instruction is single-stepped, by setting the PC to the scratch
5511 location address, and resuming. Control returns to GDB when the
5514 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5515 function used for the current instruction. This function's job is to
5516 put the CPU/memory state back to what it would have been if the
5517 instruction had been executed unmodified in its original location. */
5519 /* NOP instruction (mov r0, r0). */
5520 #define ARM_NOP 0xe1a00000
5521 #define THUMB_NOP 0x4600
5523 /* Helper for register reads for displaced stepping. In particular, this
5524 returns the PC as it would be seen by the instruction at its original
5528 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5532 CORE_ADDR from = dsc->insn_addr;
5534 if (regno == ARM_PC_REGNUM)
5536 /* Compute pipeline offset:
5537 - When executing an ARM instruction, PC reads as the address of the
5538 current instruction plus 8.
5539 - When executing a Thumb instruction, PC reads as the address of the
5540 current instruction plus 4. */
5547 if (debug_displaced)
5548 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5549 (unsigned long) from);
5550 return (ULONGEST) from;
5554 regcache_cooked_read_unsigned (regs, regno, &ret);
5555 if (debug_displaced)
5556 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5557 regno, (unsigned long) ret);
5563 displaced_in_arm_mode (struct regcache *regs)
5566 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5568 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5570 return (ps & t_bit) == 0;
5573 /* Write to the PC as from a branch instruction. */
5576 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5580 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5581 architecture versions < 6. */
5582 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5583 val & ~(ULONGEST) 0x3);
5585 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5586 val & ~(ULONGEST) 0x1);
5589 /* Write to the PC as from a branch-exchange instruction. */
5592 bx_write_pc (struct regcache *regs, ULONGEST val)
5595 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5597 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5601 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5602 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5604 else if ((val & 2) == 0)
5606 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5607 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5611 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5612 mode, align dest to 4 bytes). */
5613 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5614 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5615 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5619 /* Write to the PC as if from a load instruction. */
5622 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5625 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5626 bx_write_pc (regs, val);
5628 branch_write_pc (regs, dsc, val);
5631 /* Write to the PC as if from an ALU instruction. */
5634 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5637 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5638 bx_write_pc (regs, val);
5640 branch_write_pc (regs, dsc, val);
5643 /* Helper for writing to registers for displaced stepping. Writing to the PC
5644 has a varying effects depending on the instruction which does the write:
5645 this is controlled by the WRITE_PC argument. */
5648 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5649 int regno, ULONGEST val, enum pc_write_style write_pc)
5651 if (regno == ARM_PC_REGNUM)
5653 if (debug_displaced)
5654 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5655 (unsigned long) val);
5658 case BRANCH_WRITE_PC:
5659 branch_write_pc (regs, dsc, val);
5663 bx_write_pc (regs, val);
5667 load_write_pc (regs, dsc, val);
5671 alu_write_pc (regs, dsc, val);
5674 case CANNOT_WRITE_PC:
5675 warning (_("Instruction wrote to PC in an unexpected way when "
5676 "single-stepping"));
5680 internal_error (__FILE__, __LINE__,
5681 _("Invalid argument to displaced_write_reg"));
5684 dsc->wrote_to_pc = 1;
5688 if (debug_displaced)
5689 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5690 regno, (unsigned long) val);
5691 regcache_cooked_write_unsigned (regs, regno, val);
5695 /* This function is used to concisely determine if an instruction INSN
5696 references PC. Register fields of interest in INSN should have the
5697 corresponding fields of BITMASK set to 0b1111. The function
5698 returns return 1 if any of these fields in INSN reference the PC
5699 (also 0b1111, r15), else it returns 0. */
5702 insn_references_pc (uint32_t insn, uint32_t bitmask)
5704 uint32_t lowbit = 1;
5706 while (bitmask != 0)
5710 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5716 mask = lowbit * 0xf;
5718 if ((insn & mask) == mask)
5727 /* The simplest copy function. Many instructions have the same effect no
5728 matter what address they are executed at: in those cases, use this. */
5731 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5732 const char *iname, struct displaced_step_closure *dsc)
5734 if (debug_displaced)
5735 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5736 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5739 dsc->modinsn[0] = insn;
5745 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5746 uint16_t insn2, const char *iname,
5747 struct displaced_step_closure *dsc)
5749 if (debug_displaced)
5750 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5751 "opcode/class '%s' unmodified\n", insn1, insn2,
5754 dsc->modinsn[0] = insn1;
5755 dsc->modinsn[1] = insn2;
5761 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5764 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5766 struct displaced_step_closure *dsc)
5768 if (debug_displaced)
5769 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5770 "opcode/class '%s' unmodified\n", insn,
5773 dsc->modinsn[0] = insn;
5778 /* Preload instructions with immediate offset. */
5781 cleanup_preload (struct gdbarch *gdbarch,
5782 struct regcache *regs, struct displaced_step_closure *dsc)
5784 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5785 if (!dsc->u.preload.immed)
5786 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5790 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5791 struct displaced_step_closure *dsc, unsigned int rn)
5794 /* Preload instructions:
5796 {pli/pld} [rn, #+/-imm]
5798 {pli/pld} [r0, #+/-imm]. */
5800 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5801 rn_val = displaced_read_reg (regs, dsc, rn);
5802 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5803 dsc->u.preload.immed = 1;
5805 dsc->cleanup = &cleanup_preload;
5809 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5810 struct displaced_step_closure *dsc)
5812 unsigned int rn = bits (insn, 16, 19);
5814 if (!insn_references_pc (insn, 0x000f0000ul))
5815 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5817 if (debug_displaced)
5818 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5819 (unsigned long) insn);
5821 dsc->modinsn[0] = insn & 0xfff0ffff;
5823 install_preload (gdbarch, regs, dsc, rn);
5829 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5830 struct regcache *regs, struct displaced_step_closure *dsc)
5832 unsigned int rn = bits (insn1, 0, 3);
5833 unsigned int u_bit = bit (insn1, 7);
5834 int imm12 = bits (insn2, 0, 11);
5837 if (rn != ARM_PC_REGNUM)
5838 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5840 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5841 PLD (literal) Encoding T1. */
5842 if (debug_displaced)
5843 fprintf_unfiltered (gdb_stdlog,
5844 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5845 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5851 /* Rewrite instruction {pli/pld} PC imm12 into:
5852 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5856 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5858 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5859 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5861 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5863 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5864 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5865 dsc->u.preload.immed = 0;
5867 /* {pli/pld} [r0, r1] */
5868 dsc->modinsn[0] = insn1 & 0xfff0;
5869 dsc->modinsn[1] = 0xf001;
5872 dsc->cleanup = &cleanup_preload;
5876 /* Preload instructions with register offset. */
5879 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5880 struct displaced_step_closure *dsc, unsigned int rn,
5883 ULONGEST rn_val, rm_val;
5885 /* Preload register-offset instructions:
5887 {pli/pld} [rn, rm {, shift}]
5889 {pli/pld} [r0, r1 {, shift}]. */
5891 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5892 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5893 rn_val = displaced_read_reg (regs, dsc, rn);
5894 rm_val = displaced_read_reg (regs, dsc, rm);
5895 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5896 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5897 dsc->u.preload.immed = 0;
5899 dsc->cleanup = &cleanup_preload;
5903 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5904 struct regcache *regs,
5905 struct displaced_step_closure *dsc)
5907 unsigned int rn = bits (insn, 16, 19);
5908 unsigned int rm = bits (insn, 0, 3);
5911 if (!insn_references_pc (insn, 0x000f000ful))
5912 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5914 if (debug_displaced)
5915 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5916 (unsigned long) insn);
5918 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5920 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5924 /* Copy/cleanup coprocessor load and store instructions. */
5927 cleanup_copro_load_store (struct gdbarch *gdbarch,
5928 struct regcache *regs,
5929 struct displaced_step_closure *dsc)
5931 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5933 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5935 if (dsc->u.ldst.writeback)
5936 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5940 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5941 struct displaced_step_closure *dsc,
5942 int writeback, unsigned int rn)
5946 /* Coprocessor load/store instructions:
5948 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5950 {stc/stc2} [r0, #+/-imm].
5952 ldc/ldc2 are handled identically. */
5954 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5955 rn_val = displaced_read_reg (regs, dsc, rn);
5956 /* PC should be 4-byte aligned. */
5957 rn_val = rn_val & 0xfffffffc;
5958 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5960 dsc->u.ldst.writeback = writeback;
5961 dsc->u.ldst.rn = rn;
5963 dsc->cleanup = &cleanup_copro_load_store;
5967 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5968 struct regcache *regs,
5969 struct displaced_step_closure *dsc)
5971 unsigned int rn = bits (insn, 16, 19);
5973 if (!insn_references_pc (insn, 0x000f0000ul))
5974 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5976 if (debug_displaced)
5977 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5978 "load/store insn %.8lx\n", (unsigned long) insn);
5980 dsc->modinsn[0] = insn & 0xfff0ffff;
5982 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5988 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5989 uint16_t insn2, struct regcache *regs,
5990 struct displaced_step_closure *dsc)
5992 unsigned int rn = bits (insn1, 0, 3);
5994 if (rn != ARM_PC_REGNUM)
5995 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5996 "copro load/store", dsc);
5998 if (debug_displaced)
5999 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
6000 "load/store insn %.4x%.4x\n", insn1, insn2);
6002 dsc->modinsn[0] = insn1 & 0xfff0;
6003 dsc->modinsn[1] = insn2;
6006 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6007 doesn't support writeback, so pass 0. */
6008 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
6013 /* Clean up branch instructions (actually perform the branch, by setting
6017 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
6018 struct displaced_step_closure *dsc)
6020 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6021 int branch_taken = condition_true (dsc->u.branch.cond, status);
6022 enum pc_write_style write_pc = dsc->u.branch.exchange
6023 ? BX_WRITE_PC : BRANCH_WRITE_PC;
6028 if (dsc->u.branch.link)
6030 /* The value of LR should be the next insn of current one. In order
6031 not to confuse logic hanlding later insn `bx lr', if current insn mode
6032 is Thumb, the bit 0 of LR value should be set to 1. */
6033 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
6036 next_insn_addr |= 0x1;
6038 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
6042 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
6045 /* Copy B/BL/BLX instructions with immediate destinations. */
6048 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
6049 struct displaced_step_closure *dsc,
6050 unsigned int cond, int exchange, int link, long offset)
6052 /* Implement "BL<cond> <label>" as:
6054 Preparation: cond <- instruction condition
6055 Insn: mov r0, r0 (nop)
6056 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6058 B<cond> similar, but don't set r14 in cleanup. */
6060 dsc->u.branch.cond = cond;
6061 dsc->u.branch.link = link;
6062 dsc->u.branch.exchange = exchange;
6064 dsc->u.branch.dest = dsc->insn_addr;
6065 if (link && exchange)
6066 /* For BLX, offset is computed from the Align (PC, 4). */
6067 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6070 dsc->u.branch.dest += 4 + offset;
6072 dsc->u.branch.dest += 8 + offset;
6074 dsc->cleanup = &cleanup_branch;
6077 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
6078 struct regcache *regs, struct displaced_step_closure *dsc)
6080 unsigned int cond = bits (insn, 28, 31);
6081 int exchange = (cond == 0xf);
6082 int link = exchange || bit (insn, 24);
6085 if (debug_displaced)
6086 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
6087 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
6088 (unsigned long) insn);
6090 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6091 then arrange the switch into Thumb mode. */
6092 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
6094 offset = bits (insn, 0, 23) << 2;
6096 if (bit (offset, 25))
6097 offset = offset | ~0x3ffffff;
6099 dsc->modinsn[0] = ARM_NOP;
6101 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6106 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
6107 uint16_t insn2, struct regcache *regs,
6108 struct displaced_step_closure *dsc)
6110 int link = bit (insn2, 14);
6111 int exchange = link && !bit (insn2, 12);
6114 int j1 = bit (insn2, 13);
6115 int j2 = bit (insn2, 11);
6116 int s = sbits (insn1, 10, 10);
6117 int i1 = !(j1 ^ bit (insn1, 10));
6118 int i2 = !(j2 ^ bit (insn1, 10));
6120 if (!link && !exchange) /* B */
6122 offset = (bits (insn2, 0, 10) << 1);
6123 if (bit (insn2, 12)) /* Encoding T4 */
6125 offset |= (bits (insn1, 0, 9) << 12)
6131 else /* Encoding T3 */
6133 offset |= (bits (insn1, 0, 5) << 12)
6137 cond = bits (insn1, 6, 9);
6142 offset = (bits (insn1, 0, 9) << 12);
6143 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6144 offset |= exchange ?
6145 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
6148 if (debug_displaced)
6149 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
6150 "%.4x %.4x with offset %.8lx\n",
6151 link ? (exchange) ? "blx" : "bl" : "b",
6152 insn1, insn2, offset);
6154 dsc->modinsn[0] = THUMB_NOP;
6156 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6160 /* Copy B Thumb instructions. */
6162 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
6163 struct displaced_step_closure *dsc)
6165 unsigned int cond = 0;
6167 unsigned short bit_12_15 = bits (insn, 12, 15);
6168 CORE_ADDR from = dsc->insn_addr;
6170 if (bit_12_15 == 0xd)
6172 /* offset = SignExtend (imm8:0, 32) */
6173 offset = sbits ((insn << 1), 0, 8);
6174 cond = bits (insn, 8, 11);
6176 else if (bit_12_15 == 0xe) /* Encoding T2 */
6178 offset = sbits ((insn << 1), 0, 11);
6182 if (debug_displaced)
6183 fprintf_unfiltered (gdb_stdlog,
6184 "displaced: copying b immediate insn %.4x "
6185 "with offset %d\n", insn, offset);
6187 dsc->u.branch.cond = cond;
6188 dsc->u.branch.link = 0;
6189 dsc->u.branch.exchange = 0;
6190 dsc->u.branch.dest = from + 4 + offset;
6192 dsc->modinsn[0] = THUMB_NOP;
6194 dsc->cleanup = &cleanup_branch;
6199 /* Copy BX/BLX with register-specified destinations. */
6202 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6203 struct displaced_step_closure *dsc, int link,
6204 unsigned int cond, unsigned int rm)
6206 /* Implement {BX,BLX}<cond> <reg>" as:
6208 Preparation: cond <- instruction condition
6209 Insn: mov r0, r0 (nop)
6210 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6212 Don't set r14 in cleanup for BX. */
6214 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6216 dsc->u.branch.cond = cond;
6217 dsc->u.branch.link = link;
6219 dsc->u.branch.exchange = 1;
6221 dsc->cleanup = &cleanup_branch;
6225 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6226 struct regcache *regs, struct displaced_step_closure *dsc)
6228 unsigned int cond = bits (insn, 28, 31);
6231 int link = bit (insn, 5);
6232 unsigned int rm = bits (insn, 0, 3);
6234 if (debug_displaced)
6235 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6236 (unsigned long) insn);
6238 dsc->modinsn[0] = ARM_NOP;
6240 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6245 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6246 struct regcache *regs,
6247 struct displaced_step_closure *dsc)
6249 int link = bit (insn, 7);
6250 unsigned int rm = bits (insn, 3, 6);
6252 if (debug_displaced)
6253 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6254 (unsigned short) insn);
6256 dsc->modinsn[0] = THUMB_NOP;
6258 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6264 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6267 cleanup_alu_imm (struct gdbarch *gdbarch,
6268 struct regcache *regs, struct displaced_step_closure *dsc)
6270 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6271 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6272 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6273 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6277 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6278 struct displaced_step_closure *dsc)
6280 unsigned int rn = bits (insn, 16, 19);
6281 unsigned int rd = bits (insn, 12, 15);
6282 unsigned int op = bits (insn, 21, 24);
6283 int is_mov = (op == 0xd);
6284 ULONGEST rd_val, rn_val;
6286 if (!insn_references_pc (insn, 0x000ff000ul))
6287 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6289 if (debug_displaced)
6290 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6291 "%.8lx\n", is_mov ? "move" : "ALU",
6292 (unsigned long) insn);
6294 /* Instruction is of form:
6296 <op><cond> rd, [rn,] #imm
6300 Preparation: tmp1, tmp2 <- r0, r1;
6302 Insn: <op><cond> r0, r1, #imm
6303 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6306 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6307 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6308 rn_val = displaced_read_reg (regs, dsc, rn);
6309 rd_val = displaced_read_reg (regs, dsc, rd);
6310 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6311 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6315 dsc->modinsn[0] = insn & 0xfff00fff;
6317 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6319 dsc->cleanup = &cleanup_alu_imm;
6325 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6326 uint16_t insn2, struct regcache *regs,
6327 struct displaced_step_closure *dsc)
6329 unsigned int op = bits (insn1, 5, 8);
6330 unsigned int rn, rm, rd;
6331 ULONGEST rd_val, rn_val;
6333 rn = bits (insn1, 0, 3); /* Rn */
6334 rm = bits (insn2, 0, 3); /* Rm */
6335 rd = bits (insn2, 8, 11); /* Rd */
6337 /* This routine is only called for instruction MOV. */
6338 gdb_assert (op == 0x2 && rn == 0xf);
6340 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6341 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6343 if (debug_displaced)
6344 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6345 "ALU", insn1, insn2);
6347 /* Instruction is of form:
6349 <op><cond> rd, [rn,] #imm
6353 Preparation: tmp1, tmp2 <- r0, r1;
6355 Insn: <op><cond> r0, r1, #imm
6356 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6359 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6360 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6361 rn_val = displaced_read_reg (regs, dsc, rn);
6362 rd_val = displaced_read_reg (regs, dsc, rd);
6363 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6364 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6367 dsc->modinsn[0] = insn1;
6368 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6371 dsc->cleanup = &cleanup_alu_imm;
6376 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6379 cleanup_alu_reg (struct gdbarch *gdbarch,
6380 struct regcache *regs, struct displaced_step_closure *dsc)
6385 rd_val = displaced_read_reg (regs, dsc, 0);
6387 for (i = 0; i < 3; i++)
6388 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6390 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6394 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6395 struct displaced_step_closure *dsc,
6396 unsigned int rd, unsigned int rn, unsigned int rm)
6398 ULONGEST rd_val, rn_val, rm_val;
6400 /* Instruction is of form:
6402 <op><cond> rd, [rn,] rm [, <shift>]
6406 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6407 r0, r1, r2 <- rd, rn, rm
6408 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
6409 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6412 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6413 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6414 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6415 rd_val = displaced_read_reg (regs, dsc, rd);
6416 rn_val = displaced_read_reg (regs, dsc, rn);
6417 rm_val = displaced_read_reg (regs, dsc, rm);
6418 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6419 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6420 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6423 dsc->cleanup = &cleanup_alu_reg;
6427 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6428 struct displaced_step_closure *dsc)
6430 unsigned int op = bits (insn, 21, 24);
6431 int is_mov = (op == 0xd);
6433 if (!insn_references_pc (insn, 0x000ff00ful))
6434 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6436 if (debug_displaced)
6437 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6438 is_mov ? "move" : "ALU", (unsigned long) insn);
6441 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6443 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6445 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6451 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6452 struct regcache *regs,
6453 struct displaced_step_closure *dsc)
6457 rm = bits (insn, 3, 6);
6458 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6460 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
6461 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6463 if (debug_displaced)
6464 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
6465 (unsigned short) insn);
6467 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
6469 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
6474 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6477 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6478 struct regcache *regs,
6479 struct displaced_step_closure *dsc)
6481 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6484 for (i = 0; i < 4; i++)
6485 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6487 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6491 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6492 struct displaced_step_closure *dsc,
6493 unsigned int rd, unsigned int rn, unsigned int rm,
6497 ULONGEST rd_val, rn_val, rm_val, rs_val;
6499 /* Instruction is of form:
6501 <op><cond> rd, [rn,] rm, <shift> rs
6505 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6506 r0, r1, r2, r3 <- rd, rn, rm, rs
6507 Insn: <op><cond> r0, r1, r2, <shift> r3
6509 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6513 for (i = 0; i < 4; i++)
6514 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6516 rd_val = displaced_read_reg (regs, dsc, rd);
6517 rn_val = displaced_read_reg (regs, dsc, rn);
6518 rm_val = displaced_read_reg (regs, dsc, rm);
6519 rs_val = displaced_read_reg (regs, dsc, rs);
6520 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6521 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6522 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6523 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6525 dsc->cleanup = &cleanup_alu_shifted_reg;
6529 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6530 struct regcache *regs,
6531 struct displaced_step_closure *dsc)
6533 unsigned int op = bits (insn, 21, 24);
6534 int is_mov = (op == 0xd);
6535 unsigned int rd, rn, rm, rs;
6537 if (!insn_references_pc (insn, 0x000fff0ful))
6538 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6540 if (debug_displaced)
6541 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6542 "%.8lx\n", is_mov ? "move" : "ALU",
6543 (unsigned long) insn);
6545 rn = bits (insn, 16, 19);
6546 rm = bits (insn, 0, 3);
6547 rs = bits (insn, 8, 11);
6548 rd = bits (insn, 12, 15);
6551 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6553 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6555 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6560 /* Clean up load instructions. */
6563 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6564 struct displaced_step_closure *dsc)
6566 ULONGEST rt_val, rt_val2 = 0, rn_val;
6568 rt_val = displaced_read_reg (regs, dsc, 0);
6569 if (dsc->u.ldst.xfersize == 8)
6570 rt_val2 = displaced_read_reg (regs, dsc, 1);
6571 rn_val = displaced_read_reg (regs, dsc, 2);
6573 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6574 if (dsc->u.ldst.xfersize > 4)
6575 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6576 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6577 if (!dsc->u.ldst.immed)
6578 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6580 /* Handle register writeback. */
6581 if (dsc->u.ldst.writeback)
6582 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6583 /* Put result in right place. */
6584 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6585 if (dsc->u.ldst.xfersize == 8)
6586 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6589 /* Clean up store instructions. */
6592 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6593 struct displaced_step_closure *dsc)
6595 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6597 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6598 if (dsc->u.ldst.xfersize > 4)
6599 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6600 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6601 if (!dsc->u.ldst.immed)
6602 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6603 if (!dsc->u.ldst.restore_r4)
6604 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6607 if (dsc->u.ldst.writeback)
6608 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6611 /* Copy "extra" load/store instructions. These are halfword/doubleword
6612 transfers, which have a different encoding to byte/word transfers. */
6615 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6616 struct regcache *regs, struct displaced_step_closure *dsc)
6618 unsigned int op1 = bits (insn, 20, 24);
6619 unsigned int op2 = bits (insn, 5, 6);
6620 unsigned int rt = bits (insn, 12, 15);
6621 unsigned int rn = bits (insn, 16, 19);
6622 unsigned int rm = bits (insn, 0, 3);
6623 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6624 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6625 int immed = (op1 & 0x4) != 0;
6627 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6629 if (!insn_references_pc (insn, 0x000ff00ful))
6630 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6632 if (debug_displaced)
6633 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6634 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6635 (unsigned long) insn);
6637 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6640 internal_error (__FILE__, __LINE__,
6641 _("copy_extra_ld_st: instruction decode error"));
6643 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6644 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6645 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6647 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6649 rt_val = displaced_read_reg (regs, dsc, rt);
6650 if (bytesize[opcode] == 8)
6651 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6652 rn_val = displaced_read_reg (regs, dsc, rn);
6654 rm_val = displaced_read_reg (regs, dsc, rm);
6656 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6657 if (bytesize[opcode] == 8)
6658 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6659 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6661 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6664 dsc->u.ldst.xfersize = bytesize[opcode];
6665 dsc->u.ldst.rn = rn;
6666 dsc->u.ldst.immed = immed;
6667 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6668 dsc->u.ldst.restore_r4 = 0;
6671 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6673 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6674 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6676 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6678 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6679 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6681 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6686 /* Copy byte/half word/word loads and stores. */
6689 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6690 struct displaced_step_closure *dsc, int load,
6691 int immed, int writeback, int size, int usermode,
6692 int rt, int rm, int rn)
6694 ULONGEST rt_val, rn_val, rm_val = 0;
6696 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6697 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6699 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6701 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6703 rt_val = displaced_read_reg (regs, dsc, rt);
6704 rn_val = displaced_read_reg (regs, dsc, rn);
6706 rm_val = displaced_read_reg (regs, dsc, rm);
6708 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6709 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6711 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6713 dsc->u.ldst.xfersize = size;
6714 dsc->u.ldst.rn = rn;
6715 dsc->u.ldst.immed = immed;
6716 dsc->u.ldst.writeback = writeback;
6718 /* To write PC we can do:
6720 Before this sequence of instructions:
6721 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6722 r2 is the Rn value got from dispalced_read_reg.
6724 Insn1: push {pc} Write address of STR instruction + offset on stack
6725 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6726 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6727 = addr(Insn1) + offset - addr(Insn3) - 8
6729 Insn4: add r4, r4, #8 r4 = offset - 8
6730 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6732 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6734 Otherwise we don't know what value to write for PC, since the offset is
6735 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6736 of this can be found in Section "Saving from r15" in
6737 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6739 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6744 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6745 uint16_t insn2, struct regcache *regs,
6746 struct displaced_step_closure *dsc, int size)
6748 unsigned int u_bit = bit (insn1, 7);
6749 unsigned int rt = bits (insn2, 12, 15);
6750 int imm12 = bits (insn2, 0, 11);
6753 if (debug_displaced)
6754 fprintf_unfiltered (gdb_stdlog,
6755 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6756 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6762 /* Rewrite instruction LDR Rt imm12 into:
6764 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6768 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6771 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6772 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6773 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6775 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6777 pc_val = pc_val & 0xfffffffc;
6779 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6780 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6784 dsc->u.ldst.xfersize = size;
6785 dsc->u.ldst.immed = 0;
6786 dsc->u.ldst.writeback = 0;
6787 dsc->u.ldst.restore_r4 = 0;
6789 /* LDR R0, R2, R3 */
6790 dsc->modinsn[0] = 0xf852;
6791 dsc->modinsn[1] = 0x3;
6794 dsc->cleanup = &cleanup_load;
6800 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6801 uint16_t insn2, struct regcache *regs,
6802 struct displaced_step_closure *dsc,
6803 int writeback, int immed)
6805 unsigned int rt = bits (insn2, 12, 15);
6806 unsigned int rn = bits (insn1, 0, 3);
6807 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6808 /* In LDR (register), there is also a register Rm, which is not allowed to
6809 be PC, so we don't have to check it. */
6811 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6812 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6815 if (debug_displaced)
6816 fprintf_unfiltered (gdb_stdlog,
6817 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6818 rt, rn, insn1, insn2);
6820 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6823 dsc->u.ldst.restore_r4 = 0;
6826 /* ldr[b]<cond> rt, [rn, #imm], etc.
6828 ldr[b]<cond> r0, [r2, #imm]. */
6830 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6831 dsc->modinsn[1] = insn2 & 0x0fff;
6834 /* ldr[b]<cond> rt, [rn, rm], etc.
6836 ldr[b]<cond> r0, [r2, r3]. */
6838 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6839 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6849 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6850 struct regcache *regs,
6851 struct displaced_step_closure *dsc,
6852 int load, int size, int usermode)
6854 int immed = !bit (insn, 25);
6855 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6856 unsigned int rt = bits (insn, 12, 15);
6857 unsigned int rn = bits (insn, 16, 19);
6858 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6860 if (!insn_references_pc (insn, 0x000ff00ful))
6861 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6863 if (debug_displaced)
6864 fprintf_unfiltered (gdb_stdlog,
6865 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6866 load ? (size == 1 ? "ldrb" : "ldr")
6867 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6869 (unsigned long) insn);
6871 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6872 usermode, rt, rm, rn);
6874 if (load || rt != ARM_PC_REGNUM)
6876 dsc->u.ldst.restore_r4 = 0;
6879 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6881 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6882 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6884 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6886 {ldr,str}[b]<cond> r0, [r2, r3]. */
6887 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6891 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6892 dsc->u.ldst.restore_r4 = 1;
6893 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6894 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6895 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6896 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6897 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6901 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6903 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6908 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6913 /* Cleanup LDM instructions with fully-populated register list. This is an
6914 unfortunate corner case: it's impossible to implement correctly by modifying
6915 the instruction. The issue is as follows: we have an instruction,
6919 which we must rewrite to avoid loading PC. A possible solution would be to
6920 do the load in two halves, something like (with suitable cleanup
6924 ldm[id][ab] r8!, {r0-r7}
6926 ldm[id][ab] r8, {r7-r14}
6929 but at present there's no suitable place for <temp>, since the scratch space
6930 is overwritten before the cleanup routine is called. For now, we simply
6931 emulate the instruction. */
6934 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6935 struct displaced_step_closure *dsc)
6937 int inc = dsc->u.block.increment;
6938 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6939 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6940 uint32_t regmask = dsc->u.block.regmask;
6941 int regno = inc ? 0 : 15;
6942 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6943 int exception_return = dsc->u.block.load && dsc->u.block.user
6944 && (regmask & 0x8000) != 0;
6945 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6946 int do_transfer = condition_true (dsc->u.block.cond, status);
6947 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6952 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6953 sensible we can do here. Complain loudly. */
6954 if (exception_return)
6955 error (_("Cannot single-step exception return"));
6957 /* We don't handle any stores here for now. */
6958 gdb_assert (dsc->u.block.load != 0);
6960 if (debug_displaced)
6961 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6962 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6963 dsc->u.block.increment ? "inc" : "dec",
6964 dsc->u.block.before ? "before" : "after");
6971 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6974 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6977 xfer_addr += bump_before;
6979 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6980 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6982 xfer_addr += bump_after;
6984 regmask &= ~(1 << regno);
6987 if (dsc->u.block.writeback)
6988 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6992 /* Clean up an STM which included the PC in the register list. */
6995 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6996 struct displaced_step_closure *dsc)
6998 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6999 int store_executed = condition_true (dsc->u.block.cond, status);
7000 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
7001 CORE_ADDR stm_insn_addr;
7004 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7006 /* If condition code fails, there's nothing else to do. */
7007 if (!store_executed)
7010 if (dsc->u.block.increment)
7012 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
7014 if (dsc->u.block.before)
7019 pc_stored_at = dsc->u.block.xfer_addr;
7021 if (dsc->u.block.before)
7025 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
7026 stm_insn_addr = dsc->scratch_base;
7027 offset = pc_val - stm_insn_addr;
7029 if (debug_displaced)
7030 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
7031 "STM instruction\n", offset);
7033 /* Rewrite the stored PC to the proper value for the non-displaced original
7035 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
7036 dsc->insn_addr + offset);
7039 /* Clean up an LDM which includes the PC in the register list. We clumped all
7040 the registers in the transferred list into a contiguous range r0...rX (to
7041 avoid loading PC directly and losing control of the debugged program), so we
7042 must undo that here. */
7045 cleanup_block_load_pc (struct gdbarch *gdbarch,
7046 struct regcache *regs,
7047 struct displaced_step_closure *dsc)
7049 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
7050 int load_executed = condition_true (dsc->u.block.cond, status);
7051 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
7052 unsigned int regs_loaded = bitcount (mask);
7053 unsigned int num_to_shuffle = regs_loaded, clobbered;
7055 /* The method employed here will fail if the register list is fully populated
7056 (we need to avoid loading PC directly). */
7057 gdb_assert (num_to_shuffle < 16);
7062 clobbered = (1 << num_to_shuffle) - 1;
7064 while (num_to_shuffle > 0)
7066 if ((mask & (1 << write_reg)) != 0)
7068 unsigned int read_reg = num_to_shuffle - 1;
7070 if (read_reg != write_reg)
7072 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
7073 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7074 if (debug_displaced)
7075 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
7076 "loaded register r%d to r%d\n"), read_reg,
7079 else if (debug_displaced)
7080 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
7081 "r%d already in the right place\n"),
7084 clobbered &= ~(1 << write_reg);
7092 /* Restore any registers we scribbled over. */
7093 for (write_reg = 0; clobbered != 0; write_reg++)
7095 if ((clobbered & (1 << write_reg)) != 0)
7097 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7099 if (debug_displaced)
7100 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
7101 "clobbered register r%d\n"), write_reg);
7102 clobbered &= ~(1 << write_reg);
7106 /* Perform register writeback manually. */
7107 if (dsc->u.block.writeback)
7109 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7111 if (dsc->u.block.increment)
7112 new_rn_val += regs_loaded * 4;
7114 new_rn_val -= regs_loaded * 4;
7116 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7121 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7122 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7125 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
7126 struct regcache *regs,
7127 struct displaced_step_closure *dsc)
7129 int load = bit (insn, 20);
7130 int user = bit (insn, 22);
7131 int increment = bit (insn, 23);
7132 int before = bit (insn, 24);
7133 int writeback = bit (insn, 21);
7134 int rn = bits (insn, 16, 19);
7136 /* Block transfers which don't mention PC can be run directly
7138 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
7139 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7141 if (rn == ARM_PC_REGNUM)
7143 warning (_("displaced: Unpredictable LDM or STM with "
7144 "base register r15"));
7145 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7148 if (debug_displaced)
7149 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7150 "%.8lx\n", (unsigned long) insn);
7152 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7153 dsc->u.block.rn = rn;
7155 dsc->u.block.load = load;
7156 dsc->u.block.user = user;
7157 dsc->u.block.increment = increment;
7158 dsc->u.block.before = before;
7159 dsc->u.block.writeback = writeback;
7160 dsc->u.block.cond = bits (insn, 28, 31);
7162 dsc->u.block.regmask = insn & 0xffff;
7166 if ((insn & 0xffff) == 0xffff)
7168 /* LDM with a fully-populated register list. This case is
7169 particularly tricky. Implement for now by fully emulating the
7170 instruction (which might not behave perfectly in all cases, but
7171 these instructions should be rare enough for that not to matter
7173 dsc->modinsn[0] = ARM_NOP;
7175 dsc->cleanup = &cleanup_block_load_all;
7179 /* LDM of a list of registers which includes PC. Implement by
7180 rewriting the list of registers to be transferred into a
7181 contiguous chunk r0...rX before doing the transfer, then shuffling
7182 registers into the correct places in the cleanup routine. */
7183 unsigned int regmask = insn & 0xffff;
7184 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7185 unsigned int to = 0, from = 0, i, new_rn;
7187 for (i = 0; i < num_in_list; i++)
7188 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7190 /* Writeback makes things complicated. We need to avoid clobbering
7191 the base register with one of the registers in our modified
7192 register list, but just using a different register can't work in
7195 ldm r14!, {r0-r13,pc}
7197 which would need to be rewritten as:
7201 but that can't work, because there's no free register for N.
7203 Solve this by turning off the writeback bit, and emulating
7204 writeback manually in the cleanup routine. */
7209 new_regmask = (1 << num_in_list) - 1;
7211 if (debug_displaced)
7212 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7213 "{..., pc}: original reg list %.4x, modified "
7214 "list %.4x\n"), rn, writeback ? "!" : "",
7215 (int) insn & 0xffff, new_regmask);
7217 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7219 dsc->cleanup = &cleanup_block_load_pc;
7224 /* STM of a list of registers which includes PC. Run the instruction
7225 as-is, but out of line: this will store the wrong value for the PC,
7226 so we must manually fix up the memory in the cleanup routine.
7227 Doing things this way has the advantage that we can auto-detect
7228 the offset of the PC write (which is architecture-dependent) in
7229 the cleanup routine. */
7230 dsc->modinsn[0] = insn;
7232 dsc->cleanup = &cleanup_block_store_pc;
7239 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7240 struct regcache *regs,
7241 struct displaced_step_closure *dsc)
7243 int rn = bits (insn1, 0, 3);
7244 int load = bit (insn1, 4);
7245 int writeback = bit (insn1, 5);
7247 /* Block transfers which don't mention PC can be run directly
7249 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7250 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7252 if (rn == ARM_PC_REGNUM)
7254 warning (_("displaced: Unpredictable LDM or STM with "
7255 "base register r15"));
7256 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7257 "unpredictable ldm/stm", dsc);
7260 if (debug_displaced)
7261 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7262 "%.4x%.4x\n", insn1, insn2);
7264 /* Clear bit 13, since it should be always zero. */
7265 dsc->u.block.regmask = (insn2 & 0xdfff);
7266 dsc->u.block.rn = rn;
7268 dsc->u.block.load = load;
7269 dsc->u.block.user = 0;
7270 dsc->u.block.increment = bit (insn1, 7);
7271 dsc->u.block.before = bit (insn1, 8);
7272 dsc->u.block.writeback = writeback;
7273 dsc->u.block.cond = INST_AL;
7274 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7278 if (dsc->u.block.regmask == 0xffff)
7280 /* This branch is impossible to happen. */
7285 unsigned int regmask = dsc->u.block.regmask;
7286 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7287 unsigned int to = 0, from = 0, i, new_rn;
7289 for (i = 0; i < num_in_list; i++)
7290 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7295 new_regmask = (1 << num_in_list) - 1;
7297 if (debug_displaced)
7298 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7299 "{..., pc}: original reg list %.4x, modified "
7300 "list %.4x\n"), rn, writeback ? "!" : "",
7301 (int) dsc->u.block.regmask, new_regmask);
7303 dsc->modinsn[0] = insn1;
7304 dsc->modinsn[1] = (new_regmask & 0xffff);
7307 dsc->cleanup = &cleanup_block_load_pc;
7312 dsc->modinsn[0] = insn1;
7313 dsc->modinsn[1] = insn2;
7315 dsc->cleanup = &cleanup_block_store_pc;
7320 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7321 for Linux, where some SVC instructions must be treated specially. */
7324 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7325 struct displaced_step_closure *dsc)
7327 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7329 if (debug_displaced)
7330 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7331 "%.8lx\n", (unsigned long) resume_addr);
7333 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7337 /* Common copy routine for svc instruciton. */
7340 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7341 struct displaced_step_closure *dsc)
7343 /* Preparation: none.
7344 Insn: unmodified svc.
7345 Cleanup: pc <- insn_addr + insn_size. */
7347 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7349 dsc->wrote_to_pc = 1;
7351 /* Allow OS-specific code to override SVC handling. */
7352 if (dsc->u.svc.copy_svc_os)
7353 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7356 dsc->cleanup = &cleanup_svc;
7362 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7363 struct regcache *regs, struct displaced_step_closure *dsc)
7366 if (debug_displaced)
7367 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7368 (unsigned long) insn);
7370 dsc->modinsn[0] = insn;
7372 return install_svc (gdbarch, regs, dsc);
7376 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7377 struct regcache *regs, struct displaced_step_closure *dsc)
7380 if (debug_displaced)
7381 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7384 dsc->modinsn[0] = insn;
7386 return install_svc (gdbarch, regs, dsc);
7389 /* Copy undefined instructions. */
7392 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7393 struct displaced_step_closure *dsc)
7395 if (debug_displaced)
7396 fprintf_unfiltered (gdb_stdlog,
7397 "displaced: copying undefined insn %.8lx\n",
7398 (unsigned long) insn);
7400 dsc->modinsn[0] = insn;
7406 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7407 struct displaced_step_closure *dsc)
7410 if (debug_displaced)
7411 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7412 "%.4x %.4x\n", (unsigned short) insn1,
7413 (unsigned short) insn2);
7415 dsc->modinsn[0] = insn1;
7416 dsc->modinsn[1] = insn2;
7422 /* Copy unpredictable instructions. */
7425 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7426 struct displaced_step_closure *dsc)
7428 if (debug_displaced)
7429 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7430 "%.8lx\n", (unsigned long) insn);
7432 dsc->modinsn[0] = insn;
7437 /* The decode_* functions are instruction decoding helpers. They mostly follow
7438 the presentation in the ARM ARM. */
7441 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7442 struct regcache *regs,
7443 struct displaced_step_closure *dsc)
7445 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7446 unsigned int rn = bits (insn, 16, 19);
7448 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7449 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7450 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7451 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7452 else if ((op1 & 0x60) == 0x20)
7453 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7454 else if ((op1 & 0x71) == 0x40)
7455 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7457 else if ((op1 & 0x77) == 0x41)
7458 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7459 else if ((op1 & 0x77) == 0x45)
7460 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7461 else if ((op1 & 0x77) == 0x51)
7464 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7466 return arm_copy_unpred (gdbarch, insn, dsc);
7468 else if ((op1 & 0x77) == 0x55)
7469 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7470 else if (op1 == 0x57)
7473 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7474 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7475 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7476 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7477 default: return arm_copy_unpred (gdbarch, insn, dsc);
7479 else if ((op1 & 0x63) == 0x43)
7480 return arm_copy_unpred (gdbarch, insn, dsc);
7481 else if ((op2 & 0x1) == 0x0)
7482 switch (op1 & ~0x80)
7485 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7487 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7488 case 0x71: case 0x75:
7490 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7491 case 0x63: case 0x67: case 0x73: case 0x77:
7492 return arm_copy_unpred (gdbarch, insn, dsc);
7494 return arm_copy_undef (gdbarch, insn, dsc);
7497 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7501 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7502 struct regcache *regs,
7503 struct displaced_step_closure *dsc)
7505 if (bit (insn, 27) == 0)
7506 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7507 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7508 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7511 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7514 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7516 case 0x4: case 0x5: case 0x6: case 0x7:
7517 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7520 switch ((insn & 0xe00000) >> 21)
7522 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7524 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7527 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7530 return arm_copy_undef (gdbarch, insn, dsc);
7535 int rn_f = (bits (insn, 16, 19) == 0xf);
7536 switch ((insn & 0xe00000) >> 21)
7539 /* ldc/ldc2 imm (undefined for rn == pc). */
7540 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7541 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7544 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7546 case 0x4: case 0x5: case 0x6: case 0x7:
7547 /* ldc/ldc2 lit (undefined for rn != pc). */
7548 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7549 : arm_copy_undef (gdbarch, insn, dsc);
7552 return arm_copy_undef (gdbarch, insn, dsc);
7557 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7560 if (bits (insn, 16, 19) == 0xf)
7562 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7564 return arm_copy_undef (gdbarch, insn, dsc);
7568 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7570 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7574 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7576 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7579 return arm_copy_undef (gdbarch, insn, dsc);
7583 /* Decode miscellaneous instructions in dp/misc encoding space. */
7586 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7587 struct regcache *regs,
7588 struct displaced_step_closure *dsc)
7590 unsigned int op2 = bits (insn, 4, 6);
7591 unsigned int op = bits (insn, 21, 22);
7592 unsigned int op1 = bits (insn, 16, 19);
7597 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7600 if (op == 0x1) /* bx. */
7601 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7603 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7605 return arm_copy_undef (gdbarch, insn, dsc);
7609 /* Not really supported. */
7610 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7612 return arm_copy_undef (gdbarch, insn, dsc);
7616 return arm_copy_bx_blx_reg (gdbarch, insn,
7617 regs, dsc); /* blx register. */
7619 return arm_copy_undef (gdbarch, insn, dsc);
7622 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7626 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7628 /* Not really supported. */
7629 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7632 return arm_copy_undef (gdbarch, insn, dsc);
7637 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7638 struct regcache *regs,
7639 struct displaced_step_closure *dsc)
7642 switch (bits (insn, 20, 24))
7645 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7648 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7650 case 0x12: case 0x16:
7651 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7654 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7658 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7660 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7661 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7662 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7663 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7664 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7665 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7666 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7667 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7668 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7669 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7670 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7671 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7672 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7673 /* 2nd arg means "unpriveleged". */
7674 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7678 /* Should be unreachable. */
7683 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7684 struct regcache *regs,
7685 struct displaced_step_closure *dsc)
7687 int a = bit (insn, 25), b = bit (insn, 4);
7688 uint32_t op1 = bits (insn, 20, 24);
7689 int rn_f = bits (insn, 16, 19) == 0xf;
7691 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7692 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7693 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7694 else if ((!a && (op1 & 0x17) == 0x02)
7695 || (a && (op1 & 0x17) == 0x02 && !b))
7696 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7697 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7698 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7699 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7700 else if ((!a && (op1 & 0x17) == 0x03)
7701 || (a && (op1 & 0x17) == 0x03 && !b))
7702 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7703 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7704 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7705 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7706 else if ((!a && (op1 & 0x17) == 0x06)
7707 || (a && (op1 & 0x17) == 0x06 && !b))
7708 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7709 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7710 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7711 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7712 else if ((!a && (op1 & 0x17) == 0x07)
7713 || (a && (op1 & 0x17) == 0x07 && !b))
7714 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7716 /* Should be unreachable. */
7721 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7722 struct displaced_step_closure *dsc)
7724 switch (bits (insn, 20, 24))
7726 case 0x00: case 0x01: case 0x02: case 0x03:
7727 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7729 case 0x04: case 0x05: case 0x06: case 0x07:
7730 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7732 case 0x08: case 0x09: case 0x0a: case 0x0b:
7733 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7734 return arm_copy_unmodified (gdbarch, insn,
7735 "decode/pack/unpack/saturate/reverse", dsc);
7738 if (bits (insn, 5, 7) == 0) /* op2. */
7740 if (bits (insn, 12, 15) == 0xf)
7741 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7743 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7746 return arm_copy_undef (gdbarch, insn, dsc);
7748 case 0x1a: case 0x1b:
7749 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7750 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7752 return arm_copy_undef (gdbarch, insn, dsc);
7754 case 0x1c: case 0x1d:
7755 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7757 if (bits (insn, 0, 3) == 0xf)
7758 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7760 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7763 return arm_copy_undef (gdbarch, insn, dsc);
7765 case 0x1e: case 0x1f:
7766 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7767 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7769 return arm_copy_undef (gdbarch, insn, dsc);
7772 /* Should be unreachable. */
7777 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7778 struct regcache *regs,
7779 struct displaced_step_closure *dsc)
7782 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7784 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7788 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7789 struct regcache *regs,
7790 struct displaced_step_closure *dsc)
7792 unsigned int opcode = bits (insn, 20, 24);
7796 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7797 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7799 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7800 case 0x12: case 0x16:
7801 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7803 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7804 case 0x13: case 0x17:
7805 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7807 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7808 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7809 /* Note: no writeback for these instructions. Bit 25 will always be
7810 zero though (via caller), so the following works OK. */
7811 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7814 /* Should be unreachable. */
7818 /* Decode shifted register instructions. */
7821 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7822 uint16_t insn2, struct regcache *regs,
7823 struct displaced_step_closure *dsc)
7825 /* PC is only allowed to be used in instruction MOV. */
7827 unsigned int op = bits (insn1, 5, 8);
7828 unsigned int rn = bits (insn1, 0, 3);
7830 if (op == 0x2 && rn == 0xf) /* MOV */
7831 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7833 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7834 "dp (shift reg)", dsc);
7838 /* Decode extension register load/store. Exactly the same as
7839 arm_decode_ext_reg_ld_st. */
7842 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7843 uint16_t insn2, struct regcache *regs,
7844 struct displaced_step_closure *dsc)
7846 unsigned int opcode = bits (insn1, 4, 8);
7850 case 0x04: case 0x05:
7851 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7852 "vfp/neon vmov", dsc);
7854 case 0x08: case 0x0c: /* 01x00 */
7855 case 0x0a: case 0x0e: /* 01x10 */
7856 case 0x12: case 0x16: /* 10x10 */
7857 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7858 "vfp/neon vstm/vpush", dsc);
7860 case 0x09: case 0x0d: /* 01x01 */
7861 case 0x0b: case 0x0f: /* 01x11 */
7862 case 0x13: case 0x17: /* 10x11 */
7863 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7864 "vfp/neon vldm/vpop", dsc);
7866 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7867 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7869 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7870 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7873 /* Should be unreachable. */
7878 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7879 struct regcache *regs, struct displaced_step_closure *dsc)
7881 unsigned int op1 = bits (insn, 20, 25);
7882 int op = bit (insn, 4);
7883 unsigned int coproc = bits (insn, 8, 11);
7884 unsigned int rn = bits (insn, 16, 19);
7886 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7887 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7888 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7889 && (coproc & 0xe) != 0xa)
7891 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7892 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7893 && (coproc & 0xe) != 0xa)
7894 /* ldc/ldc2 imm/lit. */
7895 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7896 else if ((op1 & 0x3e) == 0x00)
7897 return arm_copy_undef (gdbarch, insn, dsc);
7898 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7899 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7900 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7901 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7902 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7903 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7904 else if ((op1 & 0x30) == 0x20 && !op)
7906 if ((coproc & 0xe) == 0xa)
7907 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7909 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7911 else if ((op1 & 0x30) == 0x20 && op)
7912 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7913 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7914 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7915 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7916 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7917 else if ((op1 & 0x30) == 0x30)
7918 return arm_copy_svc (gdbarch, insn, regs, dsc);
7920 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7924 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7925 uint16_t insn2, struct regcache *regs,
7926 struct displaced_step_closure *dsc)
7928 unsigned int coproc = bits (insn2, 8, 11);
7929 unsigned int op1 = bits (insn1, 4, 9);
7930 unsigned int bit_5_8 = bits (insn1, 5, 8);
7931 unsigned int bit_9 = bit (insn1, 9);
7932 unsigned int bit_4 = bit (insn1, 4);
7933 unsigned int rn = bits (insn1, 0, 3);
7938 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7939 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7941 else if (bit_5_8 == 0) /* UNDEFINED. */
7942 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7945 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7946 if ((coproc & 0xe) == 0xa)
7947 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7949 else /* coproc is not 101x. */
7951 if (bit_4 == 0) /* STC/STC2. */
7952 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7954 else /* LDC/LDC2 {literal, immeidate}. */
7955 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7961 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7967 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7968 struct displaced_step_closure *dsc, int rd)
7974 Preparation: Rd <- PC
7980 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7981 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7985 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7986 struct displaced_step_closure *dsc,
7987 int rd, unsigned int imm)
7990 /* Encoding T2: ADDS Rd, #imm */
7991 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7993 install_pc_relative (gdbarch, regs, dsc, rd);
7999 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
8000 struct regcache *regs,
8001 struct displaced_step_closure *dsc)
8003 unsigned int rd = bits (insn, 8, 10);
8004 unsigned int imm8 = bits (insn, 0, 7);
8006 if (debug_displaced)
8007 fprintf_unfiltered (gdb_stdlog,
8008 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8011 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
8015 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
8016 uint16_t insn2, struct regcache *regs,
8017 struct displaced_step_closure *dsc)
8019 unsigned int rd = bits (insn2, 8, 11);
8020 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8021 extract raw immediate encoding rather than computing immediate. When
8022 generating ADD or SUB instruction, we can simply perform OR operation to
8023 set immediate into ADD. */
8024 unsigned int imm_3_8 = insn2 & 0x70ff;
8025 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
8027 if (debug_displaced)
8028 fprintf_unfiltered (gdb_stdlog,
8029 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8030 rd, imm_i, imm_3_8, insn1, insn2);
8032 if (bit (insn1, 7)) /* Encoding T2 */
8034 /* Encoding T3: SUB Rd, Rd, #imm */
8035 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
8036 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8038 else /* Encoding T3 */
8040 /* Encoding T3: ADD Rd, Rd, #imm */
8041 dsc->modinsn[0] = (0xf100 | rd | imm_i);
8042 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8046 install_pc_relative (gdbarch, regs, dsc, rd);
8052 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
8053 struct regcache *regs,
8054 struct displaced_step_closure *dsc)
8056 unsigned int rt = bits (insn1, 8, 10);
8058 int imm8 = (bits (insn1, 0, 7) << 2);
8059 CORE_ADDR from = dsc->insn_addr;
8065 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8067 Insn: LDR R0, [R2, R3];
8068 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8070 if (debug_displaced)
8071 fprintf_unfiltered (gdb_stdlog,
8072 "displaced: copying thumb ldr r%d [pc #%d]\n"
8075 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8076 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8077 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8078 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8079 /* The assembler calculates the required value of the offset from the
8080 Align(PC,4) value of this instruction to the label. */
8081 pc = pc & 0xfffffffc;
8083 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8084 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8087 dsc->u.ldst.xfersize = 4;
8089 dsc->u.ldst.immed = 0;
8090 dsc->u.ldst.writeback = 0;
8091 dsc->u.ldst.restore_r4 = 0;
8093 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8095 dsc->cleanup = &cleanup_load;
8100 /* Copy Thumb cbnz/cbz insruction. */
8103 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
8104 struct regcache *regs,
8105 struct displaced_step_closure *dsc)
8107 int non_zero = bit (insn1, 11);
8108 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
8109 CORE_ADDR from = dsc->insn_addr;
8110 int rn = bits (insn1, 0, 2);
8111 int rn_val = displaced_read_reg (regs, dsc, rn);
8113 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8114 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8115 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8116 condition is false, let it be, cleanup_branch will do nothing. */
8117 if (dsc->u.branch.cond)
8119 dsc->u.branch.cond = INST_AL;
8120 dsc->u.branch.dest = from + 4 + imm5;
8123 dsc->u.branch.dest = from + 2;
8125 dsc->u.branch.link = 0;
8126 dsc->u.branch.exchange = 0;
8128 if (debug_displaced)
8129 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
8130 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
8131 rn, rn_val, insn1, dsc->u.branch.dest);
8133 dsc->modinsn[0] = THUMB_NOP;
8135 dsc->cleanup = &cleanup_branch;
8139 /* Copy Table Branch Byte/Halfword */
8141 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
8142 uint16_t insn2, struct regcache *regs,
8143 struct displaced_step_closure *dsc)
8145 ULONGEST rn_val, rm_val;
8146 int is_tbh = bit (insn2, 4);
8147 CORE_ADDR halfwords = 0;
8148 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8150 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8151 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8157 target_read_memory (rn_val + 2 * rm_val, buf, 2);
8158 halfwords = extract_unsigned_integer (buf, 2, byte_order);
8164 target_read_memory (rn_val + rm_val, buf, 1);
8165 halfwords = extract_unsigned_integer (buf, 1, byte_order);
8168 if (debug_displaced)
8169 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
8170 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
8171 (unsigned int) rn_val, (unsigned int) rm_val,
8172 (unsigned int) halfwords);
8174 dsc->u.branch.cond = INST_AL;
8175 dsc->u.branch.link = 0;
8176 dsc->u.branch.exchange = 0;
8177 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8179 dsc->cleanup = &cleanup_branch;
8185 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8186 struct displaced_step_closure *dsc)
8189 int val = displaced_read_reg (regs, dsc, 7);
8190 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8193 val = displaced_read_reg (regs, dsc, 8);
8194 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8197 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8202 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8203 struct regcache *regs,
8204 struct displaced_step_closure *dsc)
8206 dsc->u.block.regmask = insn1 & 0x00ff;
8208 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8211 (1) register list is full, that is, r0-r7 are used.
8212 Prepare: tmp[0] <- r8
8214 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8215 MOV r8, r7; Move value of r7 to r8;
8216 POP {r7}; Store PC value into r7.
8218 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8220 (2) register list is not full, supposing there are N registers in
8221 register list (except PC, 0 <= N <= 7).
8222 Prepare: for each i, 0 - N, tmp[i] <- ri.
8224 POP {r0, r1, ...., rN};
8226 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8227 from tmp[] properly.
8229 if (debug_displaced)
8230 fprintf_unfiltered (gdb_stdlog,
8231 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8232 dsc->u.block.regmask, insn1);
8234 if (dsc->u.block.regmask == 0xff)
8236 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8238 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8239 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8240 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8243 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8247 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8248 unsigned int new_regmask, bit = 1;
8249 unsigned int to = 0, from = 0, i, new_rn;
8251 for (i = 0; i < num_in_list + 1; i++)
8252 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8254 new_regmask = (1 << (num_in_list + 1)) - 1;
8256 if (debug_displaced)
8257 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8258 "{..., pc}: original reg list %.4x,"
8259 " modified list %.4x\n"),
8260 (int) dsc->u.block.regmask, new_regmask);
8262 dsc->u.block.regmask |= 0x8000;
8263 dsc->u.block.writeback = 0;
8264 dsc->u.block.cond = INST_AL;
8266 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8268 dsc->cleanup = &cleanup_block_load_pc;
8275 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8276 struct regcache *regs,
8277 struct displaced_step_closure *dsc)
8279 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8280 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8283 /* 16-bit thumb instructions. */
8284 switch (op_bit_12_15)
8286 /* Shift (imme), add, subtract, move and compare. */
8287 case 0: case 1: case 2: case 3:
8288 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8289 "shift/add/sub/mov/cmp",
8293 switch (op_bit_10_11)
8295 case 0: /* Data-processing */
8296 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8300 case 1: /* Special data instructions and branch and exchange. */
8302 unsigned short op = bits (insn1, 7, 9);
8303 if (op == 6 || op == 7) /* BX or BLX */
8304 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8305 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8306 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8308 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8312 default: /* LDR (literal) */
8313 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8316 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8317 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8320 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8321 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8322 else /* Generate SP-relative address */
8323 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8325 case 11: /* Misc 16-bit instructions */
8327 switch (bits (insn1, 8, 11))
8329 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8330 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8332 case 12: case 13: /* POP */
8333 if (bit (insn1, 8)) /* PC is in register list. */
8334 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8336 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8338 case 15: /* If-Then, and hints */
8339 if (bits (insn1, 0, 3))
8340 /* If-Then makes up to four following instructions conditional.
8341 IT instruction itself is not conditional, so handle it as a
8342 common unmodified instruction. */
8343 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8346 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8349 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8354 if (op_bit_10_11 < 2) /* Store multiple registers */
8355 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8356 else /* Load multiple registers */
8357 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8359 case 13: /* Conditional branch and supervisor call */
8360 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8361 err = thumb_copy_b (gdbarch, insn1, dsc);
8363 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8365 case 14: /* Unconditional branch */
8366 err = thumb_copy_b (gdbarch, insn1, dsc);
8373 internal_error (__FILE__, __LINE__,
8374 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8378 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8379 uint16_t insn1, uint16_t insn2,
8380 struct regcache *regs,
8381 struct displaced_step_closure *dsc)
8383 int rt = bits (insn2, 12, 15);
8384 int rn = bits (insn1, 0, 3);
8385 int op1 = bits (insn1, 7, 8);
8388 switch (bits (insn1, 5, 6))
8390 case 0: /* Load byte and memory hints */
8391 if (rt == 0xf) /* PLD/PLI */
8394 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8395 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8397 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8402 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8403 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8406 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8407 "ldrb{reg, immediate}/ldrbt",
8412 case 1: /* Load halfword and memory hints. */
8413 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8414 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8415 "pld/unalloc memhint", dsc);
8419 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8422 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8426 case 2: /* Load word */
8428 int insn2_bit_8_11 = bits (insn2, 8, 11);
8431 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8432 else if (op1 == 0x1) /* Encoding T3 */
8433 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8435 else /* op1 == 0x0 */
8437 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8438 /* LDR (immediate) */
8439 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8440 dsc, bit (insn2, 8), 1);
8441 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8442 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8445 /* LDR (register) */
8446 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8452 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8459 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8460 uint16_t insn2, struct regcache *regs,
8461 struct displaced_step_closure *dsc)
8464 unsigned short op = bit (insn2, 15);
8465 unsigned int op1 = bits (insn1, 11, 12);
8471 switch (bits (insn1, 9, 10))
8476 /* Load/store {dual, execlusive}, table branch. */
8477 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8478 && bits (insn2, 5, 7) == 0)
8479 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8482 /* PC is not allowed to use in load/store {dual, exclusive}
8484 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8485 "load/store dual/ex", dsc);
8487 else /* load/store multiple */
8489 switch (bits (insn1, 7, 8))
8491 case 0: case 3: /* SRS, RFE */
8492 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8495 case 1: case 2: /* LDM/STM/PUSH/POP */
8496 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8503 /* Data-processing (shift register). */
8504 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8507 default: /* Coprocessor instructions. */
8508 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8513 case 2: /* op1 = 2 */
8514 if (op) /* Branch and misc control. */
8516 if (bit (insn2, 14) /* BLX/BL */
8517 || bit (insn2, 12) /* Unconditional branch */
8518 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8519 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8521 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8526 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8528 int op = bits (insn1, 4, 8);
8529 int rn = bits (insn1, 0, 3);
8530 if ((op == 0 || op == 0xa) && rn == 0xf)
8531 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8534 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8537 else /* Data processing (modified immeidate) */
8538 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8542 case 3: /* op1 = 3 */
8543 switch (bits (insn1, 9, 10))
8547 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8549 else /* NEON Load/Store and Store single data item */
8550 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8551 "neon elt/struct load/store",
8554 case 1: /* op1 = 3, bits (9, 10) == 1 */
8555 switch (bits (insn1, 7, 8))
8557 case 0: case 1: /* Data processing (register) */
8558 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8561 case 2: /* Multiply and absolute difference */
8562 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8563 "mul/mua/diff", dsc);
8565 case 3: /* Long multiply and divide */
8566 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8571 default: /* Coprocessor instructions */
8572 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8581 internal_error (__FILE__, __LINE__,
8582 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8587 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8588 CORE_ADDR to, struct regcache *regs,
8589 struct displaced_step_closure *dsc)
8591 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8593 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8595 if (debug_displaced)
8596 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8597 "at %.8lx\n", insn1, (unsigned long) from);
8600 dsc->insn_size = thumb_insn_size (insn1);
8601 if (thumb_insn_size (insn1) == 4)
8604 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8605 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8608 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8612 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8613 CORE_ADDR to, struct regcache *regs,
8614 struct displaced_step_closure *dsc)
8617 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8620 /* Most displaced instructions use a 1-instruction scratch space, so set this
8621 here and override below if/when necessary. */
8623 dsc->insn_addr = from;
8624 dsc->scratch_base = to;
8625 dsc->cleanup = NULL;
8626 dsc->wrote_to_pc = 0;
8628 if (!displaced_in_arm_mode (regs))
8629 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8633 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8634 if (debug_displaced)
8635 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8636 "at %.8lx\n", (unsigned long) insn,
8637 (unsigned long) from);
8639 if ((insn & 0xf0000000) == 0xf0000000)
8640 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8641 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8643 case 0x0: case 0x1: case 0x2: case 0x3:
8644 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8647 case 0x4: case 0x5: case 0x6:
8648 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8652 err = arm_decode_media (gdbarch, insn, dsc);
8655 case 0x8: case 0x9: case 0xa: case 0xb:
8656 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8659 case 0xc: case 0xd: case 0xe: case 0xf:
8660 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8665 internal_error (__FILE__, __LINE__,
8666 _("arm_process_displaced_insn: Instruction decode error"));
8669 /* Actually set up the scratch space for a displaced instruction. */
8672 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8673 CORE_ADDR to, struct displaced_step_closure *dsc)
8675 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8676 unsigned int i, len, offset;
8677 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8678 int size = dsc->is_thumb? 2 : 4;
8679 const gdb_byte *bkp_insn;
8682 /* Poke modified instruction(s). */
8683 for (i = 0; i < dsc->numinsns; i++)
8685 if (debug_displaced)
8687 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8689 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8692 fprintf_unfiltered (gdb_stdlog, "%.4x",
8693 (unsigned short)dsc->modinsn[i]);
8695 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8696 (unsigned long) to + offset);
8699 write_memory_unsigned_integer (to + offset, size,
8700 byte_order_for_code,
8705 /* Choose the correct breakpoint instruction. */
8708 bkp_insn = tdep->thumb_breakpoint;
8709 len = tdep->thumb_breakpoint_size;
8713 bkp_insn = tdep->arm_breakpoint;
8714 len = tdep->arm_breakpoint_size;
8717 /* Put breakpoint afterwards. */
8718 write_memory (to + offset, bkp_insn, len);
8720 if (debug_displaced)
8721 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8722 paddress (gdbarch, from), paddress (gdbarch, to));
8725 /* Entry point for copying an instruction into scratch space for displaced
8728 struct displaced_step_closure *
8729 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8730 CORE_ADDR from, CORE_ADDR to,
8731 struct regcache *regs)
8733 struct displaced_step_closure *dsc
8734 = xmalloc (sizeof (struct displaced_step_closure));
8735 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8736 arm_displaced_init_closure (gdbarch, from, to, dsc);
8741 /* Entry point for cleaning things up after a displaced instruction has been
8745 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8746 struct displaced_step_closure *dsc,
8747 CORE_ADDR from, CORE_ADDR to,
8748 struct regcache *regs)
8751 dsc->cleanup (gdbarch, regs, dsc);
8753 if (!dsc->wrote_to_pc)
8754 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8755 dsc->insn_addr + dsc->insn_size);
8759 #include "bfd-in2.h"
8760 #include "libcoff.h"
8763 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8765 struct gdbarch *gdbarch = info->application_data;
8767 if (arm_pc_is_thumb (gdbarch, memaddr))
8769 static asymbol *asym;
8770 static combined_entry_type ce;
8771 static struct coff_symbol_struct csym;
8772 static struct bfd fake_bfd;
8773 static bfd_target fake_target;
8775 if (csym.native == NULL)
8777 /* Create a fake symbol vector containing a Thumb symbol.
8778 This is solely so that the code in print_insn_little_arm()
8779 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8780 the presence of a Thumb symbol and switch to decoding
8781 Thumb instructions. */
8783 fake_target.flavour = bfd_target_coff_flavour;
8784 fake_bfd.xvec = &fake_target;
8785 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8787 csym.symbol.the_bfd = &fake_bfd;
8788 csym.symbol.name = "fake";
8789 asym = (asymbol *) & csym;
8792 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8793 info->symbols = &asym;
8796 info->symbols = NULL;
8798 if (info->endian == BFD_ENDIAN_BIG)
8799 return print_insn_big_arm (memaddr, info);
8801 return print_insn_little_arm (memaddr, info);
8804 /* The following define instruction sequences that will cause ARM
8805 cpu's to take an undefined instruction trap. These are used to
8806 signal a breakpoint to GDB.
8808 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8809 modes. A different instruction is required for each mode. The ARM
8810 cpu's can also be big or little endian. Thus four different
8811 instructions are needed to support all cases.
8813 Note: ARMv4 defines several new instructions that will take the
8814 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8815 not in fact add the new instructions. The new undefined
8816 instructions in ARMv4 are all instructions that had no defined
8817 behaviour in earlier chips. There is no guarantee that they will
8818 raise an exception, but may be treated as NOP's. In practice, it
8819 may only safe to rely on instructions matching:
8821 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8822 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8823 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8825 Even this may only true if the condition predicate is true. The
8826 following use a condition predicate of ALWAYS so it is always TRUE.
8828 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8829 and NetBSD all use a software interrupt rather than an undefined
8830 instruction to force a trap. This can be handled by by the
8831 abi-specific code during establishment of the gdbarch vector. */
8833 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8834 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8835 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8836 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8838 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8839 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8840 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8841 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8843 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8844 the program counter value to determine whether a 16-bit or 32-bit
8845 breakpoint should be used. It returns a pointer to a string of
8846 bytes that encode a breakpoint instruction, stores the length of
8847 the string to *lenptr, and adjusts the program counter (if
8848 necessary) to point to the actual memory location where the
8849 breakpoint should be inserted. */
8851 static const unsigned char *
8852 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8854 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8855 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8857 if (arm_pc_is_thumb (gdbarch, *pcptr))
8859 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8861 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8862 check whether we are replacing a 32-bit instruction. */
8863 if (tdep->thumb2_breakpoint != NULL)
8866 if (target_read_memory (*pcptr, buf, 2) == 0)
8868 unsigned short inst1;
8869 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8870 if (thumb_insn_size (inst1) == 4)
8872 *lenptr = tdep->thumb2_breakpoint_size;
8873 return tdep->thumb2_breakpoint;
8878 *lenptr = tdep->thumb_breakpoint_size;
8879 return tdep->thumb_breakpoint;
8883 *lenptr = tdep->arm_breakpoint_size;
8884 return tdep->arm_breakpoint;
8889 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8892 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8894 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8895 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8896 that this is not confused with a 32-bit ARM breakpoint. */
8900 /* Extract from an array REGBUF containing the (raw) register state a
8901 function return value of type TYPE, and copy that, in virtual
8902 format, into VALBUF. */
8905 arm_extract_return_value (struct type *type, struct regcache *regs,
8908 struct gdbarch *gdbarch = get_regcache_arch (regs);
8909 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8911 if (TYPE_CODE_FLT == TYPE_CODE (type))
8913 switch (gdbarch_tdep (gdbarch)->fp_model)
8917 /* The value is in register F0 in internal format. We need to
8918 extract the raw value and then convert it to the desired
8920 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8922 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8923 convert_from_extended (floatformat_from_type (type), tmpbuf,
8924 valbuf, gdbarch_byte_order (gdbarch));
8928 case ARM_FLOAT_SOFT_FPA:
8929 case ARM_FLOAT_SOFT_VFP:
8930 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8931 not using the VFP ABI code. */
8933 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8934 if (TYPE_LENGTH (type) > 4)
8935 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8936 valbuf + INT_REGISTER_SIZE);
8940 internal_error (__FILE__, __LINE__,
8941 _("arm_extract_return_value: "
8942 "Floating point model not supported"));
8946 else if (TYPE_CODE (type) == TYPE_CODE_INT
8947 || TYPE_CODE (type) == TYPE_CODE_CHAR
8948 || TYPE_CODE (type) == TYPE_CODE_BOOL
8949 || TYPE_CODE (type) == TYPE_CODE_PTR
8950 || TYPE_CODE (type) == TYPE_CODE_REF
8951 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8953 /* If the type is a plain integer, then the access is
8954 straight-forward. Otherwise we have to play around a bit
8956 int len = TYPE_LENGTH (type);
8957 int regno = ARM_A1_REGNUM;
8962 /* By using store_unsigned_integer we avoid having to do
8963 anything special for small big-endian values. */
8964 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8965 store_unsigned_integer (valbuf,
8966 (len > INT_REGISTER_SIZE
8967 ? INT_REGISTER_SIZE : len),
8969 len -= INT_REGISTER_SIZE;
8970 valbuf += INT_REGISTER_SIZE;
8975 /* For a structure or union the behaviour is as if the value had
8976 been stored to word-aligned memory and then loaded into
8977 registers with 32-bit load instruction(s). */
8978 int len = TYPE_LENGTH (type);
8979 int regno = ARM_A1_REGNUM;
8980 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8984 regcache_cooked_read (regs, regno++, tmpbuf);
8985 memcpy (valbuf, tmpbuf,
8986 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8987 len -= INT_REGISTER_SIZE;
8988 valbuf += INT_REGISTER_SIZE;
8994 /* Will a function return an aggregate type in memory or in a
8995 register? Return 0 if an aggregate type can be returned in a
8996 register, 1 if it must be returned in memory. */
8999 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
9002 enum type_code code;
9004 CHECK_TYPEDEF (type);
9006 /* In the ARM ABI, "integer" like aggregate types are returned in
9007 registers. For an aggregate type to be integer like, its size
9008 must be less than or equal to INT_REGISTER_SIZE and the
9009 offset of each addressable subfield must be zero. Note that bit
9010 fields are not addressable, and all addressable subfields of
9011 unions always start at offset zero.
9013 This function is based on the behaviour of GCC 2.95.1.
9014 See: gcc/arm.c: arm_return_in_memory() for details.
9016 Note: All versions of GCC before GCC 2.95.2 do not set up the
9017 parameters correctly for a function returning the following
9018 structure: struct { float f;}; This should be returned in memory,
9019 not a register. Richard Earnshaw sent me a patch, but I do not
9020 know of any way to detect if a function like the above has been
9021 compiled with the correct calling convention. */
9023 /* All aggregate types that won't fit in a register must be returned
9025 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
9030 /* The AAPCS says all aggregates not larger than a word are returned
9032 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
9035 /* The only aggregate types that can be returned in a register are
9036 structs and unions. Arrays must be returned in memory. */
9037 code = TYPE_CODE (type);
9038 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
9043 /* Assume all other aggregate types can be returned in a register.
9044 Run a check for structures, unions and arrays. */
9047 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
9050 /* Need to check if this struct/union is "integer" like. For
9051 this to be true, its size must be less than or equal to
9052 INT_REGISTER_SIZE and the offset of each addressable
9053 subfield must be zero. Note that bit fields are not
9054 addressable, and unions always start at offset zero. If any
9055 of the subfields is a floating point type, the struct/union
9056 cannot be an integer type. */
9058 /* For each field in the object, check:
9059 1) Is it FP? --> yes, nRc = 1;
9060 2) Is it addressable (bitpos != 0) and
9061 not packed (bitsize == 0)?
9065 for (i = 0; i < TYPE_NFIELDS (type); i++)
9067 enum type_code field_type_code;
9068 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
9071 /* Is it a floating point type field? */
9072 if (field_type_code == TYPE_CODE_FLT)
9078 /* If bitpos != 0, then we have to care about it. */
9079 if (TYPE_FIELD_BITPOS (type, i) != 0)
9081 /* Bitfields are not addressable. If the field bitsize is
9082 zero, then the field is not packed. Hence it cannot be
9083 a bitfield or any other packed type. */
9084 if (TYPE_FIELD_BITSIZE (type, i) == 0)
9096 /* Write into appropriate registers a function return value of type
9097 TYPE, given in virtual format. */
9100 arm_store_return_value (struct type *type, struct regcache *regs,
9101 const gdb_byte *valbuf)
9103 struct gdbarch *gdbarch = get_regcache_arch (regs);
9104 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9106 if (TYPE_CODE (type) == TYPE_CODE_FLT)
9108 gdb_byte buf[MAX_REGISTER_SIZE];
9110 switch (gdbarch_tdep (gdbarch)->fp_model)
9114 convert_to_extended (floatformat_from_type (type), buf, valbuf,
9115 gdbarch_byte_order (gdbarch));
9116 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
9119 case ARM_FLOAT_SOFT_FPA:
9120 case ARM_FLOAT_SOFT_VFP:
9121 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9122 not using the VFP ABI code. */
9124 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
9125 if (TYPE_LENGTH (type) > 4)
9126 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
9127 valbuf + INT_REGISTER_SIZE);
9131 internal_error (__FILE__, __LINE__,
9132 _("arm_store_return_value: Floating "
9133 "point model not supported"));
9137 else if (TYPE_CODE (type) == TYPE_CODE_INT
9138 || TYPE_CODE (type) == TYPE_CODE_CHAR
9139 || TYPE_CODE (type) == TYPE_CODE_BOOL
9140 || TYPE_CODE (type) == TYPE_CODE_PTR
9141 || TYPE_CODE (type) == TYPE_CODE_REF
9142 || TYPE_CODE (type) == TYPE_CODE_ENUM)
9144 if (TYPE_LENGTH (type) <= 4)
9146 /* Values of one word or less are zero/sign-extended and
9148 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9149 LONGEST val = unpack_long (type, valbuf);
9151 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
9152 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
9156 /* Integral values greater than one word are stored in consecutive
9157 registers starting with r0. This will always be a multiple of
9158 the regiser size. */
9159 int len = TYPE_LENGTH (type);
9160 int regno = ARM_A1_REGNUM;
9164 regcache_cooked_write (regs, regno++, valbuf);
9165 len -= INT_REGISTER_SIZE;
9166 valbuf += INT_REGISTER_SIZE;
9172 /* For a structure or union the behaviour is as if the value had
9173 been stored to word-aligned memory and then loaded into
9174 registers with 32-bit load instruction(s). */
9175 int len = TYPE_LENGTH (type);
9176 int regno = ARM_A1_REGNUM;
9177 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9181 memcpy (tmpbuf, valbuf,
9182 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9183 regcache_cooked_write (regs, regno++, tmpbuf);
9184 len -= INT_REGISTER_SIZE;
9185 valbuf += INT_REGISTER_SIZE;
9191 /* Handle function return values. */
9193 static enum return_value_convention
9194 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9195 struct type *valtype, struct regcache *regcache,
9196 gdb_byte *readbuf, const gdb_byte *writebuf)
9198 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9199 struct type *func_type = function ? value_type (function) : NULL;
9200 enum arm_vfp_cprc_base_type vfp_base_type;
9203 if (arm_vfp_abi_for_function (gdbarch, func_type)
9204 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9206 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9207 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9209 for (i = 0; i < vfp_base_count; i++)
9211 if (reg_char == 'q')
9214 arm_neon_quad_write (gdbarch, regcache, i,
9215 writebuf + i * unit_length);
9218 arm_neon_quad_read (gdbarch, regcache, i,
9219 readbuf + i * unit_length);
9226 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
9227 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9230 regcache_cooked_write (regcache, regnum,
9231 writebuf + i * unit_length);
9233 regcache_cooked_read (regcache, regnum,
9234 readbuf + i * unit_length);
9237 return RETURN_VALUE_REGISTER_CONVENTION;
9240 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9241 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9242 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9244 if (tdep->struct_return == pcc_struct_return
9245 || arm_return_in_memory (gdbarch, valtype))
9246 return RETURN_VALUE_STRUCT_CONVENTION;
9249 /* AAPCS returns complex types longer than a register in memory. */
9250 if (tdep->arm_abi != ARM_ABI_APCS
9251 && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
9252 && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE)
9253 return RETURN_VALUE_STRUCT_CONVENTION;
9256 arm_store_return_value (valtype, regcache, writebuf);
9259 arm_extract_return_value (valtype, regcache, readbuf);
9261 return RETURN_VALUE_REGISTER_CONVENTION;
9266 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9268 struct gdbarch *gdbarch = get_frame_arch (frame);
9269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9270 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9272 gdb_byte buf[INT_REGISTER_SIZE];
9274 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9276 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9280 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9284 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9285 return the target PC. Otherwise return 0. */
9288 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9292 CORE_ADDR start_addr;
9294 /* Find the starting address and name of the function containing the PC. */
9295 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9297 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9299 start_addr = arm_skip_bx_reg (frame, pc);
9300 if (start_addr != 0)
9306 /* If PC is in a Thumb call or return stub, return the address of the
9307 target PC, which is in a register. The thunk functions are called
9308 _call_via_xx, where x is the register name. The possible names
9309 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9310 functions, named __ARM_call_via_r[0-7]. */
9311 if (startswith (name, "_call_via_")
9312 || startswith (name, "__ARM_call_via_"))
9314 /* Use the name suffix to determine which register contains the
9316 static char *table[15] =
9317 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9318 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9321 int offset = strlen (name) - 2;
9323 for (regno = 0; regno <= 14; regno++)
9324 if (strcmp (&name[offset], table[regno]) == 0)
9325 return get_frame_register_unsigned (frame, regno);
9328 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9329 non-interworking calls to foo. We could decode the stubs
9330 to find the target but it's easier to use the symbol table. */
9331 namelen = strlen (name);
9332 if (name[0] == '_' && name[1] == '_'
9333 && ((namelen > 2 + strlen ("_from_thumb")
9334 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
9335 || (namelen > 2 + strlen ("_from_arm")
9336 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
9339 int target_len = namelen - 2;
9340 struct bound_minimal_symbol minsym;
9341 struct objfile *objfile;
9342 struct obj_section *sec;
9344 if (name[namelen - 1] == 'b')
9345 target_len -= strlen ("_from_thumb");
9347 target_len -= strlen ("_from_arm");
9349 target_name = alloca (target_len + 1);
9350 memcpy (target_name, name + 2, target_len);
9351 target_name[target_len] = '\0';
9353 sec = find_pc_section (pc);
9354 objfile = (sec == NULL) ? NULL : sec->objfile;
9355 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9356 if (minsym.minsym != NULL)
9357 return BMSYMBOL_VALUE_ADDRESS (minsym);
9362 return 0; /* not a stub */
9366 set_arm_command (char *args, int from_tty)
9368 printf_unfiltered (_("\
9369 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9370 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9374 show_arm_command (char *args, int from_tty)
9376 cmd_show_list (showarmcmdlist, from_tty, "");
9380 arm_update_current_architecture (void)
9382 struct gdbarch_info info;
9384 /* If the current architecture is not ARM, we have nothing to do. */
9385 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
9388 /* Update the architecture. */
9389 gdbarch_info_init (&info);
9391 if (!gdbarch_update_p (info))
9392 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9396 set_fp_model_sfunc (char *args, int from_tty,
9397 struct cmd_list_element *c)
9401 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9402 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9404 arm_fp_model = fp_model;
9408 if (fp_model == ARM_FLOAT_LAST)
9409 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9412 arm_update_current_architecture ();
9416 show_fp_model (struct ui_file *file, int from_tty,
9417 struct cmd_list_element *c, const char *value)
9419 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9421 if (arm_fp_model == ARM_FLOAT_AUTO
9422 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9423 fprintf_filtered (file, _("\
9424 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9425 fp_model_strings[tdep->fp_model]);
9427 fprintf_filtered (file, _("\
9428 The current ARM floating point model is \"%s\".\n"),
9429 fp_model_strings[arm_fp_model]);
9433 arm_set_abi (char *args, int from_tty,
9434 struct cmd_list_element *c)
9438 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9439 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9441 arm_abi_global = arm_abi;
9445 if (arm_abi == ARM_ABI_LAST)
9446 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9449 arm_update_current_architecture ();
9453 arm_show_abi (struct ui_file *file, int from_tty,
9454 struct cmd_list_element *c, const char *value)
9456 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9458 if (arm_abi_global == ARM_ABI_AUTO
9459 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9460 fprintf_filtered (file, _("\
9461 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9462 arm_abi_strings[tdep->arm_abi]);
9464 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9469 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9470 struct cmd_list_element *c, const char *value)
9472 fprintf_filtered (file,
9473 _("The current execution mode assumed "
9474 "(when symbols are unavailable) is \"%s\".\n"),
9475 arm_fallback_mode_string);
9479 arm_show_force_mode (struct ui_file *file, int from_tty,
9480 struct cmd_list_element *c, const char *value)
9482 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9484 fprintf_filtered (file,
9485 _("The current execution mode assumed "
9486 "(even when symbols are available) is \"%s\".\n"),
9487 arm_force_mode_string);
9490 /* If the user changes the register disassembly style used for info
9491 register and other commands, we have to also switch the style used
9492 in opcodes for disassembly output. This function is run in the "set
9493 arm disassembly" command, and does that. */
9496 set_disassembly_style_sfunc (char *args, int from_tty,
9497 struct cmd_list_element *c)
9499 set_disassembly_style ();
9502 /* Return the ARM register name corresponding to register I. */
9504 arm_register_name (struct gdbarch *gdbarch, int i)
9506 const int num_regs = gdbarch_num_regs (gdbarch);
9508 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9509 && i >= num_regs && i < num_regs + 32)
9511 static const char *const vfp_pseudo_names[] = {
9512 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9513 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9514 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9515 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9518 return vfp_pseudo_names[i - num_regs];
9521 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9522 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9524 static const char *const neon_pseudo_names[] = {
9525 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9526 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9529 return neon_pseudo_names[i - num_regs - 32];
9532 if (i >= ARRAY_SIZE (arm_register_names))
9533 /* These registers are only supported on targets which supply
9534 an XML description. */
9537 return arm_register_names[i];
9541 set_disassembly_style (void)
9545 /* Find the style that the user wants. */
9546 for (current = 0; current < num_disassembly_options; current++)
9547 if (disassembly_style == valid_disassembly_styles[current])
9549 gdb_assert (current < num_disassembly_options);
9551 /* Synchronize the disassembler. */
9552 set_arm_regname_option (current);
9555 /* Test whether the coff symbol specific value corresponds to a Thumb
9559 coff_sym_is_thumb (int val)
9561 return (val == C_THUMBEXT
9562 || val == C_THUMBSTAT
9563 || val == C_THUMBEXTFUNC
9564 || val == C_THUMBSTATFUNC
9565 || val == C_THUMBLABEL);
9568 /* arm_coff_make_msymbol_special()
9569 arm_elf_make_msymbol_special()
9571 These functions test whether the COFF or ELF symbol corresponds to
9572 an address in thumb code, and set a "special" bit in a minimal
9573 symbol to indicate that it does. */
9576 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9578 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9579 == ST_BRANCH_TO_THUMB)
9580 MSYMBOL_SET_SPECIAL (msym);
9584 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9586 if (coff_sym_is_thumb (val))
9587 MSYMBOL_SET_SPECIAL (msym);
9591 arm_objfile_data_free (struct objfile *objfile, void *arg)
9593 struct arm_per_objfile *data = arg;
9596 for (i = 0; i < objfile->obfd->section_count; i++)
9597 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9601 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9604 const char *name = bfd_asymbol_name (sym);
9605 struct arm_per_objfile *data;
9606 VEC(arm_mapping_symbol_s) **map_p;
9607 struct arm_mapping_symbol new_map_sym;
9609 gdb_assert (name[0] == '$');
9610 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9613 data = objfile_data (objfile, arm_objfile_data_key);
9616 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9617 struct arm_per_objfile);
9618 set_objfile_data (objfile, arm_objfile_data_key, data);
9619 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9620 objfile->obfd->section_count,
9621 VEC(arm_mapping_symbol_s) *);
9623 map_p = &data->section_maps[bfd_get_section (sym)->index];
9625 new_map_sym.value = sym->value;
9626 new_map_sym.type = name[1];
9628 /* Assume that most mapping symbols appear in order of increasing
9629 value. If they were randomly distributed, it would be faster to
9630 always push here and then sort at first use. */
9631 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9633 struct arm_mapping_symbol *prev_map_sym;
9635 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9636 if (prev_map_sym->value >= sym->value)
9639 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9640 arm_compare_mapping_symbols);
9641 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9646 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9650 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9652 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9653 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9655 /* If necessary, set the T bit. */
9658 ULONGEST val, t_bit;
9659 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9660 t_bit = arm_psr_thumb_bit (gdbarch);
9661 if (arm_pc_is_thumb (gdbarch, pc))
9662 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9665 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9670 /* Read the contents of a NEON quad register, by reading from two
9671 double registers. This is used to implement the quad pseudo
9672 registers, and for argument passing in case the quad registers are
9673 missing; vectors are passed in quad registers when using the VFP
9674 ABI, even if a NEON unit is not present. REGNUM is the index of
9675 the quad register, in [0, 15]. */
9677 static enum register_status
9678 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9679 int regnum, gdb_byte *buf)
9682 gdb_byte reg_buf[8];
9683 int offset, double_regnum;
9684 enum register_status status;
9686 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9687 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9690 /* d0 is always the least significant half of q0. */
9691 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9696 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9697 if (status != REG_VALID)
9699 memcpy (buf + offset, reg_buf, 8);
9701 offset = 8 - offset;
9702 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9703 if (status != REG_VALID)
9705 memcpy (buf + offset, reg_buf, 8);
9710 static enum register_status
9711 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9712 int regnum, gdb_byte *buf)
9714 const int num_regs = gdbarch_num_regs (gdbarch);
9716 gdb_byte reg_buf[8];
9717 int offset, double_regnum;
9719 gdb_assert (regnum >= num_regs);
9722 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9723 /* Quad-precision register. */
9724 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9727 enum register_status status;
9729 /* Single-precision register. */
9730 gdb_assert (regnum < 32);
9732 /* s0 is always the least significant half of d0. */
9733 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9734 offset = (regnum & 1) ? 0 : 4;
9736 offset = (regnum & 1) ? 4 : 0;
9738 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9739 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9742 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9743 if (status == REG_VALID)
9744 memcpy (buf, reg_buf + offset, 4);
9749 /* Store the contents of BUF to a NEON quad register, by writing to
9750 two double registers. This is used to implement the quad pseudo
9751 registers, and for argument passing in case the quad registers are
9752 missing; vectors are passed in quad registers when using the VFP
9753 ABI, even if a NEON unit is not present. REGNUM is the index
9754 of the quad register, in [0, 15]. */
9757 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9758 int regnum, const gdb_byte *buf)
9761 int offset, double_regnum;
9763 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9764 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9767 /* d0 is always the least significant half of q0. */
9768 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9773 regcache_raw_write (regcache, double_regnum, buf + offset);
9774 offset = 8 - offset;
9775 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9779 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9780 int regnum, const gdb_byte *buf)
9782 const int num_regs = gdbarch_num_regs (gdbarch);
9784 gdb_byte reg_buf[8];
9785 int offset, double_regnum;
9787 gdb_assert (regnum >= num_regs);
9790 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9791 /* Quad-precision register. */
9792 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9795 /* Single-precision register. */
9796 gdb_assert (regnum < 32);
9798 /* s0 is always the least significant half of d0. */
9799 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9800 offset = (regnum & 1) ? 0 : 4;
9802 offset = (regnum & 1) ? 4 : 0;
9804 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9805 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9808 regcache_raw_read (regcache, double_regnum, reg_buf);
9809 memcpy (reg_buf + offset, buf, 4);
9810 regcache_raw_write (regcache, double_regnum, reg_buf);
9814 static struct value *
9815 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9817 const int *reg_p = baton;
9818 return value_of_register (*reg_p, frame);
9821 static enum gdb_osabi
9822 arm_elf_osabi_sniffer (bfd *abfd)
9824 unsigned int elfosabi;
9825 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9827 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9829 if (elfosabi == ELFOSABI_ARM)
9830 /* GNU tools use this value. Check note sections in this case,
9832 bfd_map_over_sections (abfd,
9833 generic_elf_osabi_sniff_abi_tag_sections,
9836 /* Anything else will be handled by the generic ELF sniffer. */
9841 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9842 struct reggroup *group)
9844 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9845 this, FPS register belongs to save_regroup, restore_reggroup, and
9846 all_reggroup, of course. */
9847 if (regnum == ARM_FPS_REGNUM)
9848 return (group == float_reggroup
9849 || group == save_reggroup
9850 || group == restore_reggroup
9851 || group == all_reggroup);
9853 return default_register_reggroup_p (gdbarch, regnum, group);
9857 /* For backward-compatibility we allow two 'g' packet lengths with
9858 the remote protocol depending on whether FPA registers are
9859 supplied. M-profile targets do not have FPA registers, but some
9860 stubs already exist in the wild which use a 'g' packet which
9861 supplies them albeit with dummy values. The packet format which
9862 includes FPA registers should be considered deprecated for
9863 M-profile targets. */
9866 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9868 if (gdbarch_tdep (gdbarch)->is_m)
9870 /* If we know from the executable this is an M-profile target,
9871 cater for remote targets whose register set layout is the
9872 same as the FPA layout. */
9873 register_remote_g_packet_guess (gdbarch,
9874 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9875 (16 * INT_REGISTER_SIZE)
9876 + (8 * FP_REGISTER_SIZE)
9877 + (2 * INT_REGISTER_SIZE),
9878 tdesc_arm_with_m_fpa_layout);
9880 /* The regular M-profile layout. */
9881 register_remote_g_packet_guess (gdbarch,
9882 /* r0-r12,sp,lr,pc; xpsr */
9883 (16 * INT_REGISTER_SIZE)
9884 + INT_REGISTER_SIZE,
9887 /* M-profile plus M4F VFP. */
9888 register_remote_g_packet_guess (gdbarch,
9889 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9890 (16 * INT_REGISTER_SIZE)
9891 + (16 * VFP_REGISTER_SIZE)
9892 + (2 * INT_REGISTER_SIZE),
9893 tdesc_arm_with_m_vfp_d16);
9896 /* Otherwise we don't have a useful guess. */
9900 /* Initialize the current architecture based on INFO. If possible,
9901 re-use an architecture from ARCHES, which is a list of
9902 architectures already created during this debugging session.
9904 Called e.g. at program startup, when reading a core file, and when
9905 reading a binary file. */
9907 static struct gdbarch *
9908 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9910 struct gdbarch_tdep *tdep;
9911 struct gdbarch *gdbarch;
9912 struct gdbarch_list *best_arch;
9913 enum arm_abi_kind arm_abi = arm_abi_global;
9914 enum arm_float_model fp_model = arm_fp_model;
9915 struct tdesc_arch_data *tdesc_data = NULL;
9917 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9919 int have_fpa_registers = 1;
9920 const struct target_desc *tdesc = info.target_desc;
9922 /* If we have an object to base this architecture on, try to determine
9925 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9927 int ei_osabi, e_flags;
9929 switch (bfd_get_flavour (info.abfd))
9931 case bfd_target_aout_flavour:
9932 /* Assume it's an old APCS-style ABI. */
9933 arm_abi = ARM_ABI_APCS;
9936 case bfd_target_coff_flavour:
9937 /* Assume it's an old APCS-style ABI. */
9939 arm_abi = ARM_ABI_APCS;
9942 case bfd_target_elf_flavour:
9943 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9944 e_flags = elf_elfheader (info.abfd)->e_flags;
9946 if (ei_osabi == ELFOSABI_ARM)
9948 /* GNU tools used to use this value, but do not for EABI
9949 objects. There's nowhere to tag an EABI version
9950 anyway, so assume APCS. */
9951 arm_abi = ARM_ABI_APCS;
9953 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
9955 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9956 int attr_arch, attr_profile;
9960 case EF_ARM_EABI_UNKNOWN:
9961 /* Assume GNU tools. */
9962 arm_abi = ARM_ABI_APCS;
9965 case EF_ARM_EABI_VER4:
9966 case EF_ARM_EABI_VER5:
9967 arm_abi = ARM_ABI_AAPCS;
9968 /* EABI binaries default to VFP float ordering.
9969 They may also contain build attributes that can
9970 be used to identify if the VFP argument-passing
9972 if (fp_model == ARM_FLOAT_AUTO)
9975 switch (bfd_elf_get_obj_attr_int (info.abfd,
9979 case AEABI_VFP_args_base:
9980 /* "The user intended FP parameter/result
9981 passing to conform to AAPCS, base
9983 fp_model = ARM_FLOAT_SOFT_VFP;
9985 case AEABI_VFP_args_vfp:
9986 /* "The user intended FP parameter/result
9987 passing to conform to AAPCS, VFP
9989 fp_model = ARM_FLOAT_VFP;
9991 case AEABI_VFP_args_toolchain:
9992 /* "The user intended FP parameter/result
9993 passing to conform to tool chain-specific
9994 conventions" - we don't know any such
9995 conventions, so leave it as "auto". */
9997 case AEABI_VFP_args_compatible:
9998 /* "Code is compatible with both the base
9999 and VFP variants; the user did not permit
10000 non-variadic functions to pass FP
10001 parameters/results" - leave it as
10005 /* Attribute value not mentioned in the
10006 November 2012 ABI, so leave it as
10011 fp_model = ARM_FLOAT_SOFT_VFP;
10017 /* Leave it as "auto". */
10018 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
10023 /* Detect M-profile programs. This only works if the
10024 executable file includes build attributes; GCC does
10025 copy them to the executable, but e.g. RealView does
10027 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10029 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
10031 Tag_CPU_arch_profile);
10032 /* GCC specifies the profile for v6-M; RealView only
10033 specifies the profile for architectures starting with
10034 V7 (as opposed to architectures with a tag
10035 numerically greater than TAG_CPU_ARCH_V7). */
10036 if (!tdesc_has_registers (tdesc)
10037 && (attr_arch == TAG_CPU_ARCH_V6_M
10038 || attr_arch == TAG_CPU_ARCH_V6S_M
10039 || attr_profile == 'M'))
10044 if (fp_model == ARM_FLOAT_AUTO)
10046 int e_flags = elf_elfheader (info.abfd)->e_flags;
10048 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
10051 /* Leave it as "auto". Strictly speaking this case
10052 means FPA, but almost nobody uses that now, and
10053 many toolchains fail to set the appropriate bits
10054 for the floating-point model they use. */
10056 case EF_ARM_SOFT_FLOAT:
10057 fp_model = ARM_FLOAT_SOFT_FPA;
10059 case EF_ARM_VFP_FLOAT:
10060 fp_model = ARM_FLOAT_VFP;
10062 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
10063 fp_model = ARM_FLOAT_SOFT_VFP;
10068 if (e_flags & EF_ARM_BE8)
10069 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10074 /* Leave it as "auto". */
10079 /* Check any target description for validity. */
10080 if (tdesc_has_registers (tdesc))
10082 /* For most registers we require GDB's default names; but also allow
10083 the numeric names for sp / lr / pc, as a convenience. */
10084 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
10085 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
10086 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
10088 const struct tdesc_feature *feature;
10091 feature = tdesc_find_feature (tdesc,
10092 "org.gnu.gdb.arm.core");
10093 if (feature == NULL)
10095 feature = tdesc_find_feature (tdesc,
10096 "org.gnu.gdb.arm.m-profile");
10097 if (feature == NULL)
10103 tdesc_data = tdesc_data_alloc ();
10106 for (i = 0; i < ARM_SP_REGNUM; i++)
10107 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10108 arm_register_names[i]);
10109 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10112 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10115 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10119 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10120 ARM_PS_REGNUM, "xpsr");
10122 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10123 ARM_PS_REGNUM, "cpsr");
10127 tdesc_data_cleanup (tdesc_data);
10131 feature = tdesc_find_feature (tdesc,
10132 "org.gnu.gdb.arm.fpa");
10133 if (feature != NULL)
10136 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
10137 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10138 arm_register_names[i]);
10141 tdesc_data_cleanup (tdesc_data);
10146 have_fpa_registers = 0;
10148 feature = tdesc_find_feature (tdesc,
10149 "org.gnu.gdb.xscale.iwmmxt");
10150 if (feature != NULL)
10152 static const char *const iwmmxt_names[] = {
10153 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10154 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10155 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10156 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10160 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
10162 &= tdesc_numbered_register (feature, tdesc_data, i,
10163 iwmmxt_names[i - ARM_WR0_REGNUM]);
10165 /* Check for the control registers, but do not fail if they
10167 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
10168 tdesc_numbered_register (feature, tdesc_data, i,
10169 iwmmxt_names[i - ARM_WR0_REGNUM]);
10171 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
10173 &= tdesc_numbered_register (feature, tdesc_data, i,
10174 iwmmxt_names[i - ARM_WR0_REGNUM]);
10178 tdesc_data_cleanup (tdesc_data);
10183 /* If we have a VFP unit, check whether the single precision registers
10184 are present. If not, then we will synthesize them as pseudo
10186 feature = tdesc_find_feature (tdesc,
10187 "org.gnu.gdb.arm.vfp");
10188 if (feature != NULL)
10190 static const char *const vfp_double_names[] = {
10191 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10192 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10193 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10194 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10197 /* Require the double precision registers. There must be either
10200 for (i = 0; i < 32; i++)
10202 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10204 vfp_double_names[i]);
10208 if (!valid_p && i == 16)
10211 /* Also require FPSCR. */
10212 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10213 ARM_FPSCR_REGNUM, "fpscr");
10216 tdesc_data_cleanup (tdesc_data);
10220 if (tdesc_unnumbered_register (feature, "s0") == 0)
10221 have_vfp_pseudos = 1;
10223 have_vfp_registers = 1;
10225 /* If we have VFP, also check for NEON. The architecture allows
10226 NEON without VFP (integer vector operations only), but GDB
10227 does not support that. */
10228 feature = tdesc_find_feature (tdesc,
10229 "org.gnu.gdb.arm.neon");
10230 if (feature != NULL)
10232 /* NEON requires 32 double-precision registers. */
10235 tdesc_data_cleanup (tdesc_data);
10239 /* If there are quad registers defined by the stub, use
10240 their type; otherwise (normally) provide them with
10241 the default type. */
10242 if (tdesc_unnumbered_register (feature, "q0") == 0)
10243 have_neon_pseudos = 1;
10250 /* If there is already a candidate, use it. */
10251 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10253 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10255 if (arm_abi != ARM_ABI_AUTO
10256 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10259 if (fp_model != ARM_FLOAT_AUTO
10260 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10263 /* There are various other properties in tdep that we do not
10264 need to check here: those derived from a target description,
10265 since gdbarches with a different target description are
10266 automatically disqualified. */
10268 /* Do check is_m, though, since it might come from the binary. */
10269 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10272 /* Found a match. */
10276 if (best_arch != NULL)
10278 if (tdesc_data != NULL)
10279 tdesc_data_cleanup (tdesc_data);
10280 return best_arch->gdbarch;
10283 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
10284 gdbarch = gdbarch_alloc (&info, tdep);
10286 /* Record additional information about the architecture we are defining.
10287 These are gdbarch discriminators, like the OSABI. */
10288 tdep->arm_abi = arm_abi;
10289 tdep->fp_model = fp_model;
10291 tdep->have_fpa_registers = have_fpa_registers;
10292 tdep->have_vfp_registers = have_vfp_registers;
10293 tdep->have_vfp_pseudos = have_vfp_pseudos;
10294 tdep->have_neon_pseudos = have_neon_pseudos;
10295 tdep->have_neon = have_neon;
10297 arm_register_g_packet_guesses (gdbarch);
10300 switch (info.byte_order_for_code)
10302 case BFD_ENDIAN_BIG:
10303 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10304 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10305 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10306 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10310 case BFD_ENDIAN_LITTLE:
10311 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10312 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10313 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10314 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10319 internal_error (__FILE__, __LINE__,
10320 _("arm_gdbarch_init: bad byte order for float format"));
10323 /* On ARM targets char defaults to unsigned. */
10324 set_gdbarch_char_signed (gdbarch, 0);
10326 /* Note: for displaced stepping, this includes the breakpoint, and one word
10327 of additional scratch space. This setting isn't used for anything beside
10328 displaced stepping at present. */
10329 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10331 /* This should be low enough for everything. */
10332 tdep->lowest_pc = 0x20;
10333 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10335 /* The default, for both APCS and AAPCS, is to return small
10336 structures in registers. */
10337 tdep->struct_return = reg_struct_return;
10339 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10340 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10342 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10344 /* Frame handling. */
10345 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10346 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10347 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10349 frame_base_set_default (gdbarch, &arm_normal_base);
10351 /* Address manipulation. */
10352 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10354 /* Advance PC across function entry code. */
10355 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10357 /* Detect whether PC is at a point where the stack has been destroyed. */
10358 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
10360 /* Skip trampolines. */
10361 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10363 /* The stack grows downward. */
10364 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10366 /* Breakpoint manipulation. */
10367 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10368 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10369 arm_remote_breakpoint_from_pc);
10371 /* Information about registers, etc. */
10372 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10373 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10374 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10375 set_gdbarch_register_type (gdbarch, arm_register_type);
10376 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10378 /* This "info float" is FPA-specific. Use the generic version if we
10379 do not have FPA. */
10380 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10381 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10383 /* Internal <-> external register number maps. */
10384 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10385 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10387 set_gdbarch_register_name (gdbarch, arm_register_name);
10389 /* Returning results. */
10390 set_gdbarch_return_value (gdbarch, arm_return_value);
10393 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10395 /* Minsymbol frobbing. */
10396 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10397 set_gdbarch_coff_make_msymbol_special (gdbarch,
10398 arm_coff_make_msymbol_special);
10399 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10401 /* Thumb-2 IT block support. */
10402 set_gdbarch_adjust_breakpoint_address (gdbarch,
10403 arm_adjust_breakpoint_address);
10405 /* Virtual tables. */
10406 set_gdbarch_vbit_in_delta (gdbarch, 1);
10408 /* Hook in the ABI-specific overrides, if they have been registered. */
10409 gdbarch_init_osabi (info, gdbarch);
10411 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10413 /* Add some default predicates. */
10415 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
10416 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10417 dwarf2_append_unwinders (gdbarch);
10418 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10419 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10421 /* Now we have tuned the configuration, set a few final things,
10422 based on what the OS ABI has told us. */
10424 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10425 binaries are always marked. */
10426 if (tdep->arm_abi == ARM_ABI_AUTO)
10427 tdep->arm_abi = ARM_ABI_APCS;
10429 /* Watchpoints are not steppable. */
10430 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10432 /* We used to default to FPA for generic ARM, but almost nobody
10433 uses that now, and we now provide a way for the user to force
10434 the model. So default to the most useful variant. */
10435 if (tdep->fp_model == ARM_FLOAT_AUTO)
10436 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10438 if (tdep->jb_pc >= 0)
10439 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10441 /* Floating point sizes and format. */
10442 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10443 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10445 set_gdbarch_double_format
10446 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10447 set_gdbarch_long_double_format
10448 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10452 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10453 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10456 if (have_vfp_pseudos)
10458 /* NOTE: These are the only pseudo registers used by
10459 the ARM target at the moment. If more are added, a
10460 little more care in numbering will be needed. */
10462 int num_pseudos = 32;
10463 if (have_neon_pseudos)
10465 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10466 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10467 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10472 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10474 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10476 /* Override tdesc_register_type to adjust the types of VFP
10477 registers for NEON. */
10478 set_gdbarch_register_type (gdbarch, arm_register_type);
10481 /* Add standard register aliases. We add aliases even for those
10482 nanes which are used by the current architecture - it's simpler,
10483 and does no harm, since nothing ever lists user registers. */
10484 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10485 user_reg_add (gdbarch, arm_register_aliases[i].name,
10486 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10492 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10494 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10499 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10500 (unsigned long) tdep->lowest_pc);
10503 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10506 _initialize_arm_tdep (void)
10508 struct ui_file *stb;
10510 struct cmd_list_element *new_set, *new_show;
10511 const char *setname;
10512 const char *setdesc;
10513 const char *const *regnames;
10515 static char *helptext;
10516 char regdesc[1024], *rdptr = regdesc;
10517 size_t rest = sizeof (regdesc);
10519 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10521 arm_objfile_data_key
10522 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10524 /* Add ourselves to objfile event chain. */
10525 observer_attach_new_objfile (arm_exidx_new_objfile);
10527 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10529 /* Register an ELF OS ABI sniffer for ARM binaries. */
10530 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10531 bfd_target_elf_flavour,
10532 arm_elf_osabi_sniffer);
10534 /* Initialize the standard target descriptions. */
10535 initialize_tdesc_arm_with_m ();
10536 initialize_tdesc_arm_with_m_fpa_layout ();
10537 initialize_tdesc_arm_with_m_vfp_d16 ();
10538 initialize_tdesc_arm_with_iwmmxt ();
10539 initialize_tdesc_arm_with_vfpv2 ();
10540 initialize_tdesc_arm_with_vfpv3 ();
10541 initialize_tdesc_arm_with_neon ();
10543 /* Get the number of possible sets of register names defined in opcodes. */
10544 num_disassembly_options = get_arm_regname_num_options ();
10546 /* Add root prefix command for all "set arm"/"show arm" commands. */
10547 add_prefix_cmd ("arm", no_class, set_arm_command,
10548 _("Various ARM-specific commands."),
10549 &setarmcmdlist, "set arm ", 0, &setlist);
10551 add_prefix_cmd ("arm", no_class, show_arm_command,
10552 _("Various ARM-specific commands."),
10553 &showarmcmdlist, "show arm ", 0, &showlist);
10555 /* Sync the opcode insn printer with our register viewer. */
10556 parse_arm_disassembler_option ("reg-names-std");
10558 /* Initialize the array that will be passed to
10559 add_setshow_enum_cmd(). */
10560 valid_disassembly_styles
10561 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10562 for (i = 0; i < num_disassembly_options; i++)
10564 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10565 valid_disassembly_styles[i] = setname;
10566 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10569 /* When we find the default names, tell the disassembler to use
10571 if (!strcmp (setname, "std"))
10573 disassembly_style = setname;
10574 set_arm_regname_option (i);
10577 /* Mark the end of valid options. */
10578 valid_disassembly_styles[num_disassembly_options] = NULL;
10580 /* Create the help text. */
10581 stb = mem_fileopen ();
10582 fprintf_unfiltered (stb, "%s%s%s",
10583 _("The valid values are:\n"),
10585 _("The default is \"std\"."));
10586 helptext = ui_file_xstrdup (stb, NULL);
10587 ui_file_delete (stb);
10589 add_setshow_enum_cmd("disassembler", no_class,
10590 valid_disassembly_styles, &disassembly_style,
10591 _("Set the disassembly style."),
10592 _("Show the disassembly style."),
10594 set_disassembly_style_sfunc,
10595 NULL, /* FIXME: i18n: The disassembly style is
10597 &setarmcmdlist, &showarmcmdlist);
10599 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10600 _("Set usage of ARM 32-bit mode."),
10601 _("Show usage of ARM 32-bit mode."),
10602 _("When off, a 26-bit PC will be used."),
10604 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10606 &setarmcmdlist, &showarmcmdlist);
10608 /* Add a command to allow the user to force the FPU model. */
10609 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10610 _("Set the floating point type."),
10611 _("Show the floating point type."),
10612 _("auto - Determine the FP typefrom the OS-ABI.\n\
10613 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10614 fpa - FPA co-processor (GCC compiled).\n\
10615 softvfp - Software FP with pure-endian doubles.\n\
10616 vfp - VFP co-processor."),
10617 set_fp_model_sfunc, show_fp_model,
10618 &setarmcmdlist, &showarmcmdlist);
10620 /* Add a command to allow the user to force the ABI. */
10621 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10623 _("Show the ABI."),
10624 NULL, arm_set_abi, arm_show_abi,
10625 &setarmcmdlist, &showarmcmdlist);
10627 /* Add two commands to allow the user to force the assumed
10629 add_setshow_enum_cmd ("fallback-mode", class_support,
10630 arm_mode_strings, &arm_fallback_mode_string,
10631 _("Set the mode assumed when symbols are unavailable."),
10632 _("Show the mode assumed when symbols are unavailable."),
10633 NULL, NULL, arm_show_fallback_mode,
10634 &setarmcmdlist, &showarmcmdlist);
10635 add_setshow_enum_cmd ("force-mode", class_support,
10636 arm_mode_strings, &arm_force_mode_string,
10637 _("Set the mode assumed even when symbols are available."),
10638 _("Show the mode assumed even when symbols are available."),
10639 NULL, NULL, arm_show_force_mode,
10640 &setarmcmdlist, &showarmcmdlist);
10642 /* Debugging flag. */
10643 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10644 _("Set ARM debugging."),
10645 _("Show ARM debugging."),
10646 _("When on, arm-specific debugging is enabled."),
10648 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10649 &setdebuglist, &showdebuglist);
10652 /* ARM-reversible process record data structures. */
10654 #define ARM_INSN_SIZE_BYTES 4
10655 #define THUMB_INSN_SIZE_BYTES 2
10656 #define THUMB2_INSN_SIZE_BYTES 4
10659 /* Position of the bit within a 32-bit ARM instruction
10660 that defines whether the instruction is a load or store. */
10661 #define INSN_S_L_BIT_NUM 20
10663 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10666 unsigned int reg_len = LENGTH; \
10669 REGS = XNEWVEC (uint32_t, reg_len); \
10670 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10675 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10678 unsigned int mem_len = LENGTH; \
10681 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10682 memcpy(&MEMS->len, &RECORD_BUF[0], \
10683 sizeof(struct arm_mem_r) * LENGTH); \
10688 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10689 #define INSN_RECORDED(ARM_RECORD) \
10690 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10692 /* ARM memory record structure. */
10695 uint32_t len; /* Record length. */
10696 uint32_t addr; /* Memory address. */
10699 /* ARM instruction record contains opcode of current insn
10700 and execution state (before entry to decode_insn()),
10701 contains list of to-be-modified registers and
10702 memory blocks (on return from decode_insn()). */
10704 typedef struct insn_decode_record_t
10706 struct gdbarch *gdbarch;
10707 struct regcache *regcache;
10708 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10709 uint32_t arm_insn; /* Should accommodate thumb. */
10710 uint32_t cond; /* Condition code. */
10711 uint32_t opcode; /* Insn opcode. */
10712 uint32_t decode; /* Insn decode bits. */
10713 uint32_t mem_rec_count; /* No of mem records. */
10714 uint32_t reg_rec_count; /* No of reg records. */
10715 uint32_t *arm_regs; /* Registers to be saved for this record. */
10716 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10717 } insn_decode_record;
10720 /* Checks ARM SBZ and SBO mandatory fields. */
10723 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10725 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10744 enum arm_record_result
10746 ARM_RECORD_SUCCESS = 0,
10747 ARM_RECORD_FAILURE = 1
10754 } arm_record_strx_t;
10765 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10766 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10769 struct regcache *reg_cache = arm_insn_r->regcache;
10770 ULONGEST u_regval[2]= {0};
10772 uint32_t reg_src1 = 0, reg_src2 = 0;
10773 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10774 uint32_t opcode1 = 0;
10776 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10777 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10778 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10781 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10783 /* 1) Handle misc store, immediate offset. */
10784 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10785 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10786 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10787 regcache_raw_read_unsigned (reg_cache, reg_src1,
10789 if (ARM_PC_REGNUM == reg_src1)
10791 /* If R15 was used as Rn, hence current PC+8. */
10792 u_regval[0] = u_regval[0] + 8;
10794 offset_8 = (immed_high << 4) | immed_low;
10795 /* Calculate target store address. */
10796 if (14 == arm_insn_r->opcode)
10798 tgt_mem_addr = u_regval[0] + offset_8;
10802 tgt_mem_addr = u_regval[0] - offset_8;
10804 if (ARM_RECORD_STRH == str_type)
10806 record_buf_mem[0] = 2;
10807 record_buf_mem[1] = tgt_mem_addr;
10808 arm_insn_r->mem_rec_count = 1;
10810 else if (ARM_RECORD_STRD == str_type)
10812 record_buf_mem[0] = 4;
10813 record_buf_mem[1] = tgt_mem_addr;
10814 record_buf_mem[2] = 4;
10815 record_buf_mem[3] = tgt_mem_addr + 4;
10816 arm_insn_r->mem_rec_count = 2;
10819 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10821 /* 2) Store, register offset. */
10823 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10825 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10826 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10827 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10828 if (15 == reg_src2)
10830 /* If R15 was used as Rn, hence current PC+8. */
10831 u_regval[0] = u_regval[0] + 8;
10833 /* Calculate target store address, Rn +/- Rm, register offset. */
10834 if (12 == arm_insn_r->opcode)
10836 tgt_mem_addr = u_regval[0] + u_regval[1];
10840 tgt_mem_addr = u_regval[1] - u_regval[0];
10842 if (ARM_RECORD_STRH == str_type)
10844 record_buf_mem[0] = 2;
10845 record_buf_mem[1] = tgt_mem_addr;
10846 arm_insn_r->mem_rec_count = 1;
10848 else if (ARM_RECORD_STRD == str_type)
10850 record_buf_mem[0] = 4;
10851 record_buf_mem[1] = tgt_mem_addr;
10852 record_buf_mem[2] = 4;
10853 record_buf_mem[3] = tgt_mem_addr + 4;
10854 arm_insn_r->mem_rec_count = 2;
10857 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10858 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10860 /* 3) Store, immediate pre-indexed. */
10861 /* 5) Store, immediate post-indexed. */
10862 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10863 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10864 offset_8 = (immed_high << 4) | immed_low;
10865 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10866 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10867 /* Calculate target store address, Rn +/- Rm, register offset. */
10868 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10870 tgt_mem_addr = u_regval[0] + offset_8;
10874 tgt_mem_addr = u_regval[0] - offset_8;
10876 if (ARM_RECORD_STRH == str_type)
10878 record_buf_mem[0] = 2;
10879 record_buf_mem[1] = tgt_mem_addr;
10880 arm_insn_r->mem_rec_count = 1;
10882 else if (ARM_RECORD_STRD == str_type)
10884 record_buf_mem[0] = 4;
10885 record_buf_mem[1] = tgt_mem_addr;
10886 record_buf_mem[2] = 4;
10887 record_buf_mem[3] = tgt_mem_addr + 4;
10888 arm_insn_r->mem_rec_count = 2;
10890 /* Record Rn also as it changes. */
10891 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10892 arm_insn_r->reg_rec_count = 1;
10894 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10895 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10897 /* 4) Store, register pre-indexed. */
10898 /* 6) Store, register post -indexed. */
10899 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10900 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10901 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10902 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10903 /* Calculate target store address, Rn +/- Rm, register offset. */
10904 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10906 tgt_mem_addr = u_regval[0] + u_regval[1];
10910 tgt_mem_addr = u_regval[1] - u_regval[0];
10912 if (ARM_RECORD_STRH == str_type)
10914 record_buf_mem[0] = 2;
10915 record_buf_mem[1] = tgt_mem_addr;
10916 arm_insn_r->mem_rec_count = 1;
10918 else if (ARM_RECORD_STRD == str_type)
10920 record_buf_mem[0] = 4;
10921 record_buf_mem[1] = tgt_mem_addr;
10922 record_buf_mem[2] = 4;
10923 record_buf_mem[3] = tgt_mem_addr + 4;
10924 arm_insn_r->mem_rec_count = 2;
10926 /* Record Rn also as it changes. */
10927 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10928 arm_insn_r->reg_rec_count = 1;
10933 /* Handling ARM extension space insns. */
10936 arm_record_extension_space (insn_decode_record *arm_insn_r)
10938 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10939 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10940 uint32_t record_buf[8], record_buf_mem[8];
10941 uint32_t reg_src1 = 0;
10942 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10943 struct regcache *reg_cache = arm_insn_r->regcache;
10944 ULONGEST u_regval = 0;
10946 gdb_assert (!INSN_RECORDED(arm_insn_r));
10947 /* Handle unconditional insn extension space. */
10949 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10950 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10951 if (arm_insn_r->cond)
10953 /* PLD has no affect on architectural state, it just affects
10955 if (5 == ((opcode1 & 0xE0) >> 5))
10958 record_buf[0] = ARM_PS_REGNUM;
10959 record_buf[1] = ARM_LR_REGNUM;
10960 arm_insn_r->reg_rec_count = 2;
10962 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10966 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10967 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10970 /* Undefined instruction on ARM V5; need to handle if later
10971 versions define it. */
10974 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10975 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10976 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10978 /* Handle arithmetic insn extension space. */
10979 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10980 && !INSN_RECORDED(arm_insn_r))
10982 /* Handle MLA(S) and MUL(S). */
10983 if (0 <= insn_op1 && 3 >= insn_op1)
10985 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10986 record_buf[1] = ARM_PS_REGNUM;
10987 arm_insn_r->reg_rec_count = 2;
10989 else if (4 <= insn_op1 && 15 >= insn_op1)
10991 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10992 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10993 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10994 record_buf[2] = ARM_PS_REGNUM;
10995 arm_insn_r->reg_rec_count = 3;
10999 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
11000 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
11001 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
11003 /* Handle control insn extension space. */
11005 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
11006 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
11008 if (!bit (arm_insn_r->arm_insn,25))
11010 if (!bits (arm_insn_r->arm_insn, 4, 7))
11012 if ((0 == insn_op1) || (2 == insn_op1))
11015 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11016 arm_insn_r->reg_rec_count = 1;
11018 else if (1 == insn_op1)
11020 /* CSPR is going to be changed. */
11021 record_buf[0] = ARM_PS_REGNUM;
11022 arm_insn_r->reg_rec_count = 1;
11024 else if (3 == insn_op1)
11026 /* SPSR is going to be changed. */
11027 /* We need to get SPSR value, which is yet to be done. */
11028 printf_unfiltered (_("Process record does not support "
11029 "instruction 0x%0x at address %s.\n"),
11030 arm_insn_r->arm_insn,
11031 paddress (arm_insn_r->gdbarch,
11032 arm_insn_r->this_addr));
11036 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
11041 record_buf[0] = ARM_PS_REGNUM;
11042 arm_insn_r->reg_rec_count = 1;
11044 else if (3 == insn_op1)
11047 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11048 arm_insn_r->reg_rec_count = 1;
11051 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
11054 record_buf[0] = ARM_PS_REGNUM;
11055 record_buf[1] = ARM_LR_REGNUM;
11056 arm_insn_r->reg_rec_count = 2;
11058 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
11060 /* QADD, QSUB, QDADD, QDSUB */
11061 record_buf[0] = ARM_PS_REGNUM;
11062 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11063 arm_insn_r->reg_rec_count = 2;
11065 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
11068 record_buf[0] = ARM_PS_REGNUM;
11069 record_buf[1] = ARM_LR_REGNUM;
11070 arm_insn_r->reg_rec_count = 2;
11072 /* Save SPSR also;how? */
11073 printf_unfiltered (_("Process record does not support "
11074 "instruction 0x%0x at address %s.\n"),
11075 arm_insn_r->arm_insn,
11076 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11079 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
11080 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
11081 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
11082 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
11085 if (0 == insn_op1 || 1 == insn_op1)
11087 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11088 /* We dont do optimization for SMULW<y> where we
11090 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11091 record_buf[1] = ARM_PS_REGNUM;
11092 arm_insn_r->reg_rec_count = 2;
11094 else if (2 == insn_op1)
11097 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11098 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11099 arm_insn_r->reg_rec_count = 2;
11101 else if (3 == insn_op1)
11104 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11105 arm_insn_r->reg_rec_count = 1;
11111 /* MSR : immediate form. */
11114 /* CSPR is going to be changed. */
11115 record_buf[0] = ARM_PS_REGNUM;
11116 arm_insn_r->reg_rec_count = 1;
11118 else if (3 == insn_op1)
11120 /* SPSR is going to be changed. */
11121 /* we need to get SPSR value, which is yet to be done */
11122 printf_unfiltered (_("Process record does not support "
11123 "instruction 0x%0x at address %s.\n"),
11124 arm_insn_r->arm_insn,
11125 paddress (arm_insn_r->gdbarch,
11126 arm_insn_r->this_addr));
11132 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
11133 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
11134 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
11136 /* Handle load/store insn extension space. */
11138 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
11139 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
11140 && !INSN_RECORDED(arm_insn_r))
11145 /* These insn, changes register and memory as well. */
11146 /* SWP or SWPB insn. */
11147 /* Get memory address given by Rn. */
11148 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11149 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11150 /* SWP insn ?, swaps word. */
11151 if (8 == arm_insn_r->opcode)
11153 record_buf_mem[0] = 4;
11157 /* SWPB insn, swaps only byte. */
11158 record_buf_mem[0] = 1;
11160 record_buf_mem[1] = u_regval;
11161 arm_insn_r->mem_rec_count = 1;
11162 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11163 arm_insn_r->reg_rec_count = 1;
11165 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11168 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11171 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11174 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11175 record_buf[1] = record_buf[0] + 1;
11176 arm_insn_r->reg_rec_count = 2;
11178 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11181 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11184 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
11186 /* LDRH, LDRSB, LDRSH. */
11187 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11188 arm_insn_r->reg_rec_count = 1;
11193 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
11194 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
11195 && !INSN_RECORDED(arm_insn_r))
11198 /* Handle coprocessor insn extension space. */
11201 /* To be done for ARMv5 and later; as of now we return -1. */
11203 printf_unfiltered (_("Process record does not support instruction x%0x "
11204 "at address %s.\n"),arm_insn_r->arm_insn,
11205 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11208 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11209 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11214 /* Handling opcode 000 insns. */
11217 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11219 struct regcache *reg_cache = arm_insn_r->regcache;
11220 uint32_t record_buf[8], record_buf_mem[8];
11221 ULONGEST u_regval[2] = {0};
11223 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11224 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11225 uint32_t opcode1 = 0;
11227 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11228 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11229 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11231 /* Data processing insn /multiply insn. */
11232 if (9 == arm_insn_r->decode
11233 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11234 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11236 /* Handle multiply instructions. */
11237 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11238 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11240 /* Handle MLA and MUL. */
11241 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11242 record_buf[1] = ARM_PS_REGNUM;
11243 arm_insn_r->reg_rec_count = 2;
11245 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11247 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11248 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11249 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11250 record_buf[2] = ARM_PS_REGNUM;
11251 arm_insn_r->reg_rec_count = 3;
11254 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11255 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11257 /* Handle misc load insns, as 20th bit (L = 1). */
11258 /* LDR insn has a capability to do branching, if
11259 MOV LR, PC is precceded by LDR insn having Rn as R15
11260 in that case, it emulates branch and link insn, and hence we
11261 need to save CSPR and PC as well. I am not sure this is right
11262 place; as opcode = 010 LDR insn make this happen, if R15 was
11264 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11265 if (15 != reg_dest)
11267 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11268 arm_insn_r->reg_rec_count = 1;
11272 record_buf[0] = reg_dest;
11273 record_buf[1] = ARM_PS_REGNUM;
11274 arm_insn_r->reg_rec_count = 2;
11277 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11278 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11279 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11280 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11282 /* Handle MSR insn. */
11283 if (9 == arm_insn_r->opcode)
11285 /* CSPR is going to be changed. */
11286 record_buf[0] = ARM_PS_REGNUM;
11287 arm_insn_r->reg_rec_count = 1;
11291 /* SPSR is going to be changed. */
11292 /* How to read SPSR value? */
11293 printf_unfiltered (_("Process record does not support instruction "
11294 "0x%0x at address %s.\n"),
11295 arm_insn_r->arm_insn,
11296 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11300 else if (9 == arm_insn_r->decode
11301 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11302 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11304 /* Handling SWP, SWPB. */
11305 /* These insn, changes register and memory as well. */
11306 /* SWP or SWPB insn. */
11308 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11309 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11310 /* SWP insn ?, swaps word. */
11311 if (8 == arm_insn_r->opcode)
11313 record_buf_mem[0] = 4;
11317 /* SWPB insn, swaps only byte. */
11318 record_buf_mem[0] = 1;
11320 record_buf_mem[1] = u_regval[0];
11321 arm_insn_r->mem_rec_count = 1;
11322 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11323 arm_insn_r->reg_rec_count = 1;
11325 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11326 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11328 /* Handle BLX, branch and link/exchange. */
11329 if (9 == arm_insn_r->opcode)
11331 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11332 and R14 stores the return address. */
11333 record_buf[0] = ARM_PS_REGNUM;
11334 record_buf[1] = ARM_LR_REGNUM;
11335 arm_insn_r->reg_rec_count = 2;
11338 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11340 /* Handle enhanced software breakpoint insn, BKPT. */
11341 /* CPSR is changed to be executed in ARM state, disabling normal
11342 interrupts, entering abort mode. */
11343 /* According to high vector configuration PC is set. */
11344 /* user hit breakpoint and type reverse, in
11345 that case, we need to go back with previous CPSR and
11346 Program Counter. */
11347 record_buf[0] = ARM_PS_REGNUM;
11348 record_buf[1] = ARM_LR_REGNUM;
11349 arm_insn_r->reg_rec_count = 2;
11351 /* Save SPSR also; how? */
11352 printf_unfiltered (_("Process record does not support instruction "
11353 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11354 paddress (arm_insn_r->gdbarch,
11355 arm_insn_r->this_addr));
11358 else if (11 == arm_insn_r->decode
11359 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11361 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11363 /* Handle str(x) insn */
11364 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11367 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11368 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11370 /* Handle BX, branch and link/exchange. */
11371 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11372 record_buf[0] = ARM_PS_REGNUM;
11373 arm_insn_r->reg_rec_count = 1;
11375 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11376 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11377 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11379 /* Count leading zeros: CLZ. */
11380 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11381 arm_insn_r->reg_rec_count = 1;
11383 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11384 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11385 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11386 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11389 /* Handle MRS insn. */
11390 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11391 arm_insn_r->reg_rec_count = 1;
11393 else if (arm_insn_r->opcode <= 15)
11395 /* Normal data processing insns. */
11396 /* Out of 11 shifter operands mode, all the insn modifies destination
11397 register, which is specified by 13-16 decode. */
11398 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11399 record_buf[1] = ARM_PS_REGNUM;
11400 arm_insn_r->reg_rec_count = 2;
11407 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11408 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11412 /* Handling opcode 001 insns. */
11415 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11417 uint32_t record_buf[8], record_buf_mem[8];
11419 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11420 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11422 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11423 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11424 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11427 /* Handle MSR insn. */
11428 if (9 == arm_insn_r->opcode)
11430 /* CSPR is going to be changed. */
11431 record_buf[0] = ARM_PS_REGNUM;
11432 arm_insn_r->reg_rec_count = 1;
11436 /* SPSR is going to be changed. */
11439 else if (arm_insn_r->opcode <= 15)
11441 /* Normal data processing insns. */
11442 /* Out of 11 shifter operands mode, all the insn modifies destination
11443 register, which is specified by 13-16 decode. */
11444 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11445 record_buf[1] = ARM_PS_REGNUM;
11446 arm_insn_r->reg_rec_count = 2;
11453 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11454 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11458 /* Handle ARM mode instructions with opcode 010. */
11461 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11463 struct regcache *reg_cache = arm_insn_r->regcache;
11465 uint32_t reg_base , reg_dest;
11466 uint32_t offset_12, tgt_mem_addr;
11467 uint32_t record_buf[8], record_buf_mem[8];
11468 unsigned char wback;
11471 /* Calculate wback. */
11472 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
11473 || (bit (arm_insn_r->arm_insn, 21) == 1);
11475 arm_insn_r->reg_rec_count = 0;
11476 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
11478 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11480 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11483 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11484 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
11486 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11487 preceeds a LDR instruction having R15 as reg_base, it
11488 emulates a branch and link instruction, and hence we need to save
11489 CPSR and PC as well. */
11490 if (ARM_PC_REGNUM == reg_dest)
11491 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
11493 /* If wback is true, also save the base register, which is going to be
11496 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11500 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11502 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11503 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
11505 /* Handle bit U. */
11506 if (bit (arm_insn_r->arm_insn, 23))
11508 /* U == 1: Add the offset. */
11509 tgt_mem_addr = (uint32_t) u_regval + offset_12;
11513 /* U == 0: subtract the offset. */
11514 tgt_mem_addr = (uint32_t) u_regval - offset_12;
11517 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11519 if (bit (arm_insn_r->arm_insn, 22))
11521 /* STRB and STRBT: 1 byte. */
11522 record_buf_mem[0] = 1;
11526 /* STR and STRT: 4 bytes. */
11527 record_buf_mem[0] = 4;
11530 /* Handle bit P. */
11531 if (bit (arm_insn_r->arm_insn, 24))
11532 record_buf_mem[1] = tgt_mem_addr;
11534 record_buf_mem[1] = (uint32_t) u_regval;
11536 arm_insn_r->mem_rec_count = 1;
11538 /* If wback is true, also save the base register, which is going to be
11541 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11544 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11545 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11549 /* Handling opcode 011 insns. */
11552 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11554 struct regcache *reg_cache = arm_insn_r->regcache;
11556 uint32_t shift_imm = 0;
11557 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11558 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11559 uint32_t record_buf[8], record_buf_mem[8];
11562 ULONGEST u_regval[2];
11564 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11565 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11567 /* Handle enhanced store insns and LDRD DSP insn,
11568 order begins according to addressing modes for store insns
11572 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11574 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11575 /* LDR insn has a capability to do branching, if
11576 MOV LR, PC is precedded by LDR insn having Rn as R15
11577 in that case, it emulates branch and link insn, and hence we
11578 need to save CSPR and PC as well. */
11579 if (15 != reg_dest)
11581 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11582 arm_insn_r->reg_rec_count = 1;
11586 record_buf[0] = reg_dest;
11587 record_buf[1] = ARM_PS_REGNUM;
11588 arm_insn_r->reg_rec_count = 2;
11593 if (! bits (arm_insn_r->arm_insn, 4, 11))
11595 /* Store insn, register offset and register pre-indexed,
11596 register post-indexed. */
11598 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11600 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11601 regcache_raw_read_unsigned (reg_cache, reg_src1
11603 regcache_raw_read_unsigned (reg_cache, reg_src2
11605 if (15 == reg_src2)
11607 /* If R15 was used as Rn, hence current PC+8. */
11608 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11609 u_regval[0] = u_regval[0] + 8;
11611 /* Calculate target store address, Rn +/- Rm, register offset. */
11613 if (bit (arm_insn_r->arm_insn, 23))
11615 tgt_mem_addr = u_regval[0] + u_regval[1];
11619 tgt_mem_addr = u_regval[1] - u_regval[0];
11622 switch (arm_insn_r->opcode)
11636 record_buf_mem[0] = 4;
11651 record_buf_mem[0] = 1;
11655 gdb_assert_not_reached ("no decoding pattern found");
11658 record_buf_mem[1] = tgt_mem_addr;
11659 arm_insn_r->mem_rec_count = 1;
11661 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11662 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11663 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11664 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11665 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11666 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11669 /* Rn is going to be changed in pre-indexed mode and
11670 post-indexed mode as well. */
11671 record_buf[0] = reg_src2;
11672 arm_insn_r->reg_rec_count = 1;
11677 /* Store insn, scaled register offset; scaled pre-indexed. */
11678 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11680 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11682 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11683 /* Get shift_imm. */
11684 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11685 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11686 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11687 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11688 /* Offset_12 used as shift. */
11692 /* Offset_12 used as index. */
11693 offset_12 = u_regval[0] << shift_imm;
11697 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11703 if (bit (u_regval[0], 31))
11705 offset_12 = 0xFFFFFFFF;
11714 /* This is arithmetic shift. */
11715 offset_12 = s_word >> shift_imm;
11722 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11724 /* Get C flag value and shift it by 31. */
11725 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11726 | (u_regval[0]) >> 1);
11730 offset_12 = (u_regval[0] >> shift_imm) \
11732 (sizeof(uint32_t) - shift_imm));
11737 gdb_assert_not_reached ("no decoding pattern found");
11741 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11743 if (bit (arm_insn_r->arm_insn, 23))
11745 tgt_mem_addr = u_regval[1] + offset_12;
11749 tgt_mem_addr = u_regval[1] - offset_12;
11752 switch (arm_insn_r->opcode)
11766 record_buf_mem[0] = 4;
11781 record_buf_mem[0] = 1;
11785 gdb_assert_not_reached ("no decoding pattern found");
11788 record_buf_mem[1] = tgt_mem_addr;
11789 arm_insn_r->mem_rec_count = 1;
11791 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11792 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11793 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11794 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11795 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11796 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11799 /* Rn is going to be changed in register scaled pre-indexed
11800 mode,and scaled post indexed mode. */
11801 record_buf[0] = reg_src2;
11802 arm_insn_r->reg_rec_count = 1;
11807 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11808 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11812 /* Handle ARM mode instructions with opcode 100. */
11815 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11817 struct regcache *reg_cache = arm_insn_r->regcache;
11818 uint32_t register_count = 0, register_bits;
11819 uint32_t reg_base, addr_mode;
11820 uint32_t record_buf[24], record_buf_mem[48];
11824 /* Fetch the list of registers. */
11825 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11826 arm_insn_r->reg_rec_count = 0;
11828 /* Fetch the base register that contains the address we are loading data
11830 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
11832 /* Calculate wback. */
11833 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
11835 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11837 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11839 /* Find out which registers are going to be loaded from memory. */
11840 while (register_bits)
11842 if (register_bits & 0x00000001)
11843 record_buf[arm_insn_r->reg_rec_count++] = register_count;
11844 register_bits = register_bits >> 1;
11849 /* If wback is true, also save the base register, which is going to be
11852 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11854 /* Save the CPSR register. */
11855 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
11859 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11861 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11863 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
11865 /* Find out how many registers are going to be stored to memory. */
11866 while (register_bits)
11868 if (register_bits & 0x00000001)
11870 register_bits = register_bits >> 1;
11875 /* STMDA (STMED): Decrement after. */
11877 record_buf_mem[1] = (uint32_t) u_regval
11878 - register_count * INT_REGISTER_SIZE + 4;
11880 /* STM (STMIA, STMEA): Increment after. */
11882 record_buf_mem[1] = (uint32_t) u_regval;
11884 /* STMDB (STMFD): Decrement before. */
11886 record_buf_mem[1] = (uint32_t) u_regval
11887 - register_count * INT_REGISTER_SIZE;
11889 /* STMIB (STMFA): Increment before. */
11891 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
11894 gdb_assert_not_reached ("no decoding pattern found");
11898 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
11899 arm_insn_r->mem_rec_count = 1;
11901 /* If wback is true, also save the base register, which is going to be
11904 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11907 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11908 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11912 /* Handling opcode 101 insns. */
11915 arm_record_b_bl (insn_decode_record *arm_insn_r)
11917 uint32_t record_buf[8];
11919 /* Handle B, BL, BLX(1) insns. */
11920 /* B simply branches so we do nothing here. */
11921 /* Note: BLX(1) doesnt fall here but instead it falls into
11922 extension space. */
11923 if (bit (arm_insn_r->arm_insn, 24))
11925 record_buf[0] = ARM_LR_REGNUM;
11926 arm_insn_r->reg_rec_count = 1;
11929 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11934 /* Handling opcode 110 insns. */
11937 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
11939 printf_unfiltered (_("Process record does not support instruction "
11940 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11941 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11946 /* Record handler for vector data transfer instructions. */
11949 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
11951 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
11952 uint32_t record_buf[4];
11954 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
11955 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
11956 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
11957 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
11958 bit_l = bit (arm_insn_r->arm_insn, 20);
11959 bit_c = bit (arm_insn_r->arm_insn, 8);
11961 /* Handle VMOV instruction. */
11962 if (bit_l && bit_c)
11964 record_buf[0] = reg_t;
11965 arm_insn_r->reg_rec_count = 1;
11967 else if (bit_l && !bit_c)
11969 /* Handle VMOV instruction. */
11970 if (bits_a == 0x00)
11972 if (bit (arm_insn_r->arm_insn, 20))
11973 record_buf[0] = reg_t;
11975 record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
11978 arm_insn_r->reg_rec_count = 1;
11980 /* Handle VMRS instruction. */
11981 else if (bits_a == 0x07)
11984 reg_t = ARM_PS_REGNUM;
11986 record_buf[0] = reg_t;
11987 arm_insn_r->reg_rec_count = 1;
11990 else if (!bit_l && !bit_c)
11992 /* Handle VMOV instruction. */
11993 if (bits_a == 0x00)
11995 if (bit (arm_insn_r->arm_insn, 20))
11996 record_buf[0] = reg_t;
11998 record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
12001 arm_insn_r->reg_rec_count = 1;
12003 /* Handle VMSR instruction. */
12004 else if (bits_a == 0x07)
12006 record_buf[0] = ARM_FPSCR_REGNUM;
12007 arm_insn_r->reg_rec_count = 1;
12010 else if (!bit_l && bit_c)
12012 /* Handle VMOV instruction. */
12013 if (!(bits_a & 0x04))
12015 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
12017 arm_insn_r->reg_rec_count = 1;
12019 /* Handle VDUP instruction. */
12022 if (bit (arm_insn_r->arm_insn, 21))
12024 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
12025 record_buf[0] = reg_v + ARM_D0_REGNUM;
12026 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
12027 arm_insn_r->reg_rec_count = 2;
12031 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
12032 record_buf[0] = reg_v + ARM_D0_REGNUM;
12033 arm_insn_r->reg_rec_count = 1;
12038 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
12042 /* Record handler for extension register load/store instructions. */
12045 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
12047 uint32_t opcode, single_reg;
12048 uint8_t op_vldm_vstm;
12049 uint32_t record_buf[8], record_buf_mem[128];
12050 ULONGEST u_regval = 0;
12052 struct regcache *reg_cache = arm_insn_r->regcache;
12053 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
12055 opcode = bits (arm_insn_r->arm_insn, 20, 24);
12056 single_reg = bit (arm_insn_r->arm_insn, 8);
12057 op_vldm_vstm = opcode & 0x1b;
12059 /* Handle VMOV instructions. */
12060 if ((opcode & 0x1e) == 0x04)
12062 if (bit (arm_insn_r->arm_insn, 4))
12064 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
12065 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
12066 arm_insn_r->reg_rec_count = 2;
12070 uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1)
12071 | bit (arm_insn_r->arm_insn, 5);
12075 record_buf[0] = num_regs + reg_m;
12076 record_buf[1] = num_regs + reg_m + 1;
12077 arm_insn_r->reg_rec_count = 2;
12081 record_buf[0] = reg_m + ARM_D0_REGNUM;
12082 arm_insn_r->reg_rec_count = 1;
12086 /* Handle VSTM and VPUSH instructions. */
12087 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
12088 || op_vldm_vstm == 0x12)
12090 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12091 uint32_t memory_index = 0;
12093 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
12094 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12095 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
12096 imm_off32 = imm_off8 << 24;
12097 memory_count = imm_off8;
12099 if (bit (arm_insn_r->arm_insn, 23))
12100 start_address = u_regval;
12102 start_address = u_regval - imm_off32;
12104 if (bit (arm_insn_r->arm_insn, 21))
12106 record_buf[0] = reg_rn;
12107 arm_insn_r->reg_rec_count = 1;
12110 while (memory_count > 0)
12114 record_buf_mem[memory_index] = start_address;
12115 record_buf_mem[memory_index + 1] = 4;
12116 start_address = start_address + 4;
12117 memory_index = memory_index + 2;
12121 record_buf_mem[memory_index] = start_address;
12122 record_buf_mem[memory_index + 1] = 4;
12123 record_buf_mem[memory_index + 2] = start_address + 4;
12124 record_buf_mem[memory_index + 3] = 4;
12125 start_address = start_address + 8;
12126 memory_index = memory_index + 4;
12130 arm_insn_r->mem_rec_count = (memory_index >> 1);
12132 /* Handle VLDM instructions. */
12133 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
12134 || op_vldm_vstm == 0x13)
12136 uint32_t reg_count, reg_vd;
12137 uint32_t reg_index = 0;
12139 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12140 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
12143 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
12145 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
12147 if (bit (arm_insn_r->arm_insn, 21))
12148 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
12150 while (reg_count > 0)
12153 record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1;
12155 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
12159 arm_insn_r->reg_rec_count = reg_index;
12161 /* VSTR Vector store register. */
12162 else if ((opcode & 0x13) == 0x10)
12164 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12165 uint32_t memory_index = 0;
12167 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
12168 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12169 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
12170 imm_off32 = imm_off8 << 24;
12171 memory_count = imm_off8;
12173 if (bit (arm_insn_r->arm_insn, 23))
12174 start_address = u_regval + imm_off32;
12176 start_address = u_regval - imm_off32;
12180 record_buf_mem[memory_index] = start_address;
12181 record_buf_mem[memory_index + 1] = 4;
12182 arm_insn_r->mem_rec_count = 1;
12186 record_buf_mem[memory_index] = start_address;
12187 record_buf_mem[memory_index + 1] = 4;
12188 record_buf_mem[memory_index + 2] = start_address + 4;
12189 record_buf_mem[memory_index + 3] = 4;
12190 arm_insn_r->mem_rec_count = 2;
12193 /* VLDR Vector load register. */
12194 else if ((opcode & 0x13) == 0x11)
12196 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12200 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
12201 record_buf[0] = ARM_D0_REGNUM + reg_vd;
12205 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
12206 record_buf[0] = num_regs + reg_vd;
12208 arm_insn_r->reg_rec_count = 1;
12211 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
12212 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
12216 /* Record handler for arm/thumb mode VFP data processing instructions. */
12219 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
12221 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12222 uint32_t record_buf[4];
12223 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
12224 enum insn_types curr_insn_type = INSN_INV;
12226 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12227 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
12228 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
12229 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
12230 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
12231 bit_d = bit (arm_insn_r->arm_insn, 22);
12232 opc1 = opc1 & 0x04;
12234 /* Handle VMLA, VMLS. */
12237 if (bit (arm_insn_r->arm_insn, 10))
12239 if (bit (arm_insn_r->arm_insn, 6))
12240 curr_insn_type = INSN_T0;
12242 curr_insn_type = INSN_T1;
12247 curr_insn_type = INSN_T1;
12249 curr_insn_type = INSN_T2;
12252 /* Handle VNMLA, VNMLS, VNMUL. */
12253 else if (opc1 == 0x01)
12256 curr_insn_type = INSN_T1;
12258 curr_insn_type = INSN_T2;
12261 else if (opc1 == 0x02 && !(opc3 & 0x01))
12263 if (bit (arm_insn_r->arm_insn, 10))
12265 if (bit (arm_insn_r->arm_insn, 6))
12266 curr_insn_type = INSN_T0;
12268 curr_insn_type = INSN_T1;
12273 curr_insn_type = INSN_T1;
12275 curr_insn_type = INSN_T2;
12278 /* Handle VADD, VSUB. */
12279 else if (opc1 == 0x03)
12281 if (!bit (arm_insn_r->arm_insn, 9))
12283 if (bit (arm_insn_r->arm_insn, 6))
12284 curr_insn_type = INSN_T0;
12286 curr_insn_type = INSN_T1;
12291 curr_insn_type = INSN_T1;
12293 curr_insn_type = INSN_T2;
12297 else if (opc1 == 0x0b)
12300 curr_insn_type = INSN_T1;
12302 curr_insn_type = INSN_T2;
12304 /* Handle all other vfp data processing instructions. */
12305 else if (opc1 == 0x0b)
12308 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
12310 if (bit (arm_insn_r->arm_insn, 4))
12312 if (bit (arm_insn_r->arm_insn, 6))
12313 curr_insn_type = INSN_T0;
12315 curr_insn_type = INSN_T1;
12320 curr_insn_type = INSN_T1;
12322 curr_insn_type = INSN_T2;
12325 /* Handle VNEG and VABS. */
12326 else if ((opc2 == 0x01 && opc3 == 0x01)
12327 || (opc2 == 0x00 && opc3 == 0x03))
12329 if (!bit (arm_insn_r->arm_insn, 11))
12331 if (bit (arm_insn_r->arm_insn, 6))
12332 curr_insn_type = INSN_T0;
12334 curr_insn_type = INSN_T1;
12339 curr_insn_type = INSN_T1;
12341 curr_insn_type = INSN_T2;
12344 /* Handle VSQRT. */
12345 else if (opc2 == 0x01 && opc3 == 0x03)
12348 curr_insn_type = INSN_T1;
12350 curr_insn_type = INSN_T2;
12353 else if (opc2 == 0x07 && opc3 == 0x03)
12356 curr_insn_type = INSN_T1;
12358 curr_insn_type = INSN_T2;
12360 else if (opc3 & 0x01)
12363 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
12365 if (!bit (arm_insn_r->arm_insn, 18))
12366 curr_insn_type = INSN_T2;
12370 curr_insn_type = INSN_T1;
12372 curr_insn_type = INSN_T2;
12376 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
12379 curr_insn_type = INSN_T1;
12381 curr_insn_type = INSN_T2;
12383 /* Handle VCVTB, VCVTT. */
12384 else if ((opc2 & 0x0e) == 0x02)
12385 curr_insn_type = INSN_T2;
12386 /* Handle VCMP, VCMPE. */
12387 else if ((opc2 & 0x0e) == 0x04)
12388 curr_insn_type = INSN_T3;
12392 switch (curr_insn_type)
12395 reg_vd = reg_vd | (bit_d << 4);
12396 record_buf[0] = reg_vd + ARM_D0_REGNUM;
12397 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
12398 arm_insn_r->reg_rec_count = 2;
12402 reg_vd = reg_vd | (bit_d << 4);
12403 record_buf[0] = reg_vd + ARM_D0_REGNUM;
12404 arm_insn_r->reg_rec_count = 1;
12408 reg_vd = (reg_vd << 1) | bit_d;
12409 record_buf[0] = reg_vd + ARM_D0_REGNUM;
12410 arm_insn_r->reg_rec_count = 1;
12414 record_buf[0] = ARM_FPSCR_REGNUM;
12415 arm_insn_r->reg_rec_count = 1;
12419 gdb_assert_not_reached ("no decoding pattern found");
12423 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
12427 /* Handling opcode 110 insns. */
12430 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
12432 uint32_t op, op1, op1_sbit, op1_ebit, coproc;
12434 coproc = bits (arm_insn_r->arm_insn, 8, 11);
12435 op1 = bits (arm_insn_r->arm_insn, 20, 25);
12436 op1_ebit = bit (arm_insn_r->arm_insn, 20);
12438 if ((coproc & 0x0e) == 0x0a)
12440 /* Handle extension register ld/st instructions. */
12442 return arm_record_exreg_ld_st_insn (arm_insn_r);
12444 /* 64-bit transfers between arm core and extension registers. */
12445 if ((op1 & 0x3e) == 0x04)
12446 return arm_record_exreg_ld_st_insn (arm_insn_r);
12450 /* Handle coprocessor ld/st instructions. */
12455 return arm_record_unsupported_insn (arm_insn_r);
12458 return arm_record_unsupported_insn (arm_insn_r);
12461 /* Move to coprocessor from two arm core registers. */
12463 return arm_record_unsupported_insn (arm_insn_r);
12465 /* Move to two arm core registers from coprocessor. */
12470 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
12471 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
12472 arm_insn_r->reg_rec_count = 2;
12474 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
12478 return arm_record_unsupported_insn (arm_insn_r);
12481 /* Handling opcode 111 insns. */
12484 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
12486 uint32_t op, op1_sbit, op1_ebit, coproc;
12487 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
12488 struct regcache *reg_cache = arm_insn_r->regcache;
12489 ULONGEST u_regval = 0;
12491 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
12492 coproc = bits (arm_insn_r->arm_insn, 8, 11);
12493 op1_sbit = bit (arm_insn_r->arm_insn, 24);
12494 op1_ebit = bit (arm_insn_r->arm_insn, 20);
12495 op = bit (arm_insn_r->arm_insn, 4);
12497 /* Handle arm SWI/SVC system call instructions. */
12500 if (tdep->arm_syscall_record != NULL)
12502 ULONGEST svc_operand, svc_number;
12504 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
12506 if (svc_operand) /* OABI. */
12507 svc_number = svc_operand - 0x900000;
12509 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
12511 return tdep->arm_syscall_record (reg_cache, svc_number);
12515 printf_unfiltered (_("no syscall record support\n"));
12520 if ((coproc & 0x0e) == 0x0a)
12522 /* VFP data-processing instructions. */
12523 if (!op1_sbit && !op)
12524 return arm_record_vfp_data_proc_insn (arm_insn_r);
12526 /* Advanced SIMD, VFP instructions. */
12527 if (!op1_sbit && op)
12528 return arm_record_vdata_transfer_insn (arm_insn_r);
12532 /* Coprocessor data operations. */
12533 if (!op1_sbit && !op)
12534 return arm_record_unsupported_insn (arm_insn_r);
12536 /* Move to Coprocessor from ARM core register. */
12537 if (!op1_sbit && !op1_ebit && op)
12538 return arm_record_unsupported_insn (arm_insn_r);
12540 /* Move to arm core register from coprocessor. */
12541 if (!op1_sbit && op1_ebit && op)
12543 uint32_t record_buf[1];
12545 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
12546 if (record_buf[0] == 15)
12547 record_buf[0] = ARM_PS_REGNUM;
12549 arm_insn_r->reg_rec_count = 1;
12550 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
12556 return arm_record_unsupported_insn (arm_insn_r);
12559 /* Handling opcode 000 insns. */
12562 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
12564 uint32_t record_buf[8];
12565 uint32_t reg_src1 = 0;
12567 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12569 record_buf[0] = ARM_PS_REGNUM;
12570 record_buf[1] = reg_src1;
12571 thumb_insn_r->reg_rec_count = 2;
12573 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12579 /* Handling opcode 001 insns. */
12582 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
12584 uint32_t record_buf[8];
12585 uint32_t reg_src1 = 0;
12587 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12589 record_buf[0] = ARM_PS_REGNUM;
12590 record_buf[1] = reg_src1;
12591 thumb_insn_r->reg_rec_count = 2;
12593 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12598 /* Handling opcode 010 insns. */
12601 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
12603 struct regcache *reg_cache = thumb_insn_r->regcache;
12604 uint32_t record_buf[8], record_buf_mem[8];
12606 uint32_t reg_src1 = 0, reg_src2 = 0;
12607 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12609 ULONGEST u_regval[2] = {0};
12611 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
12613 if (bit (thumb_insn_r->arm_insn, 12))
12615 /* Handle load/store register offset. */
12616 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
12617 if (opcode2 >= 12 && opcode2 <= 15)
12619 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12620 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
12621 record_buf[0] = reg_src1;
12622 thumb_insn_r->reg_rec_count = 1;
12624 else if (opcode2 >= 8 && opcode2 <= 10)
12626 /* STR(2), STRB(2), STRH(2) . */
12627 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12628 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
12629 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
12630 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
12632 record_buf_mem[0] = 4; /* STR (2). */
12633 else if (10 == opcode2)
12634 record_buf_mem[0] = 1; /* STRB (2). */
12635 else if (9 == opcode2)
12636 record_buf_mem[0] = 2; /* STRH (2). */
12637 record_buf_mem[1] = u_regval[0] + u_regval[1];
12638 thumb_insn_r->mem_rec_count = 1;
12641 else if (bit (thumb_insn_r->arm_insn, 11))
12643 /* Handle load from literal pool. */
12645 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12646 record_buf[0] = reg_src1;
12647 thumb_insn_r->reg_rec_count = 1;
12651 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
12652 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
12653 if ((3 == opcode2) && (!opcode3))
12655 /* Branch with exchange. */
12656 record_buf[0] = ARM_PS_REGNUM;
12657 thumb_insn_r->reg_rec_count = 1;
12661 /* Format 8; special data processing insns. */
12662 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12663 record_buf[0] = ARM_PS_REGNUM;
12664 record_buf[1] = reg_src1;
12665 thumb_insn_r->reg_rec_count = 2;
12670 /* Format 5; data processing insns. */
12671 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12672 if (bit (thumb_insn_r->arm_insn, 7))
12674 reg_src1 = reg_src1 + 8;
12676 record_buf[0] = ARM_PS_REGNUM;
12677 record_buf[1] = reg_src1;
12678 thumb_insn_r->reg_rec_count = 2;
12681 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12682 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12688 /* Handling opcode 001 insns. */
12691 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
12693 struct regcache *reg_cache = thumb_insn_r->regcache;
12694 uint32_t record_buf[8], record_buf_mem[8];
12696 uint32_t reg_src1 = 0;
12697 uint32_t opcode = 0, immed_5 = 0;
12699 ULONGEST u_regval = 0;
12701 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12706 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12707 record_buf[0] = reg_src1;
12708 thumb_insn_r->reg_rec_count = 1;
12713 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12714 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12715 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12716 record_buf_mem[0] = 4;
12717 record_buf_mem[1] = u_regval + (immed_5 * 4);
12718 thumb_insn_r->mem_rec_count = 1;
12721 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12722 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12728 /* Handling opcode 100 insns. */
12731 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12733 struct regcache *reg_cache = thumb_insn_r->regcache;
12734 uint32_t record_buf[8], record_buf_mem[8];
12736 uint32_t reg_src1 = 0;
12737 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12739 ULONGEST u_regval = 0;
12741 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12746 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12747 record_buf[0] = reg_src1;
12748 thumb_insn_r->reg_rec_count = 1;
12750 else if (1 == opcode)
12753 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12754 record_buf[0] = reg_src1;
12755 thumb_insn_r->reg_rec_count = 1;
12757 else if (2 == opcode)
12760 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12761 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12762 record_buf_mem[0] = 4;
12763 record_buf_mem[1] = u_regval + (immed_8 * 4);
12764 thumb_insn_r->mem_rec_count = 1;
12766 else if (0 == opcode)
12769 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12770 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12771 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12772 record_buf_mem[0] = 2;
12773 record_buf_mem[1] = u_regval + (immed_5 * 2);
12774 thumb_insn_r->mem_rec_count = 1;
12777 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12778 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12784 /* Handling opcode 101 insns. */
12787 thumb_record_misc (insn_decode_record *thumb_insn_r)
12789 struct regcache *reg_cache = thumb_insn_r->regcache;
12791 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12792 uint32_t register_bits = 0, register_count = 0;
12793 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12794 uint32_t record_buf[24], record_buf_mem[48];
12797 ULONGEST u_regval = 0;
12799 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12800 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12801 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12806 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12807 while (register_bits)
12809 if (register_bits & 0x00000001)
12810 record_buf[index++] = register_count;
12811 register_bits = register_bits >> 1;
12814 record_buf[index++] = ARM_PS_REGNUM;
12815 record_buf[index++] = ARM_SP_REGNUM;
12816 thumb_insn_r->reg_rec_count = index;
12818 else if (10 == opcode2)
12821 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12822 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12823 while (register_bits)
12825 if (register_bits & 0x00000001)
12827 register_bits = register_bits >> 1;
12829 start_address = u_regval - \
12830 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12831 thumb_insn_r->mem_rec_count = register_count;
12832 while (register_count)
12834 record_buf_mem[(register_count * 2) - 1] = start_address;
12835 record_buf_mem[(register_count * 2) - 2] = 4;
12836 start_address = start_address + 4;
12839 record_buf[0] = ARM_SP_REGNUM;
12840 thumb_insn_r->reg_rec_count = 1;
12842 else if (0x1E == opcode1)
12845 /* Handle enhanced software breakpoint insn, BKPT. */
12846 /* CPSR is changed to be executed in ARM state, disabling normal
12847 interrupts, entering abort mode. */
12848 /* According to high vector configuration PC is set. */
12849 /* User hits breakpoint and type reverse, in that case, we need to go back with
12850 previous CPSR and Program Counter. */
12851 record_buf[0] = ARM_PS_REGNUM;
12852 record_buf[1] = ARM_LR_REGNUM;
12853 thumb_insn_r->reg_rec_count = 2;
12854 /* We need to save SPSR value, which is not yet done. */
12855 printf_unfiltered (_("Process record does not support instruction "
12856 "0x%0x at address %s.\n"),
12857 thumb_insn_r->arm_insn,
12858 paddress (thumb_insn_r->gdbarch,
12859 thumb_insn_r->this_addr));
12862 else if ((0 == opcode) || (1 == opcode))
12864 /* ADD(5), ADD(6). */
12865 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12866 record_buf[0] = reg_src1;
12867 thumb_insn_r->reg_rec_count = 1;
12869 else if (2 == opcode)
12871 /* ADD(7), SUB(4). */
12872 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12873 record_buf[0] = ARM_SP_REGNUM;
12874 thumb_insn_r->reg_rec_count = 1;
12877 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12878 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12884 /* Handling opcode 110 insns. */
12887 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12889 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12890 struct regcache *reg_cache = thumb_insn_r->regcache;
12892 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12893 uint32_t reg_src1 = 0;
12894 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12895 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12896 uint32_t record_buf[24], record_buf_mem[48];
12898 ULONGEST u_regval = 0;
12900 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12901 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12907 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12909 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12910 while (register_bits)
12912 if (register_bits & 0x00000001)
12913 record_buf[index++] = register_count;
12914 register_bits = register_bits >> 1;
12917 record_buf[index++] = reg_src1;
12918 thumb_insn_r->reg_rec_count = index;
12920 else if (0 == opcode2)
12922 /* It handles both STMIA. */
12923 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12925 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12926 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12927 while (register_bits)
12929 if (register_bits & 0x00000001)
12931 register_bits = register_bits >> 1;
12933 start_address = u_regval;
12934 thumb_insn_r->mem_rec_count = register_count;
12935 while (register_count)
12937 record_buf_mem[(register_count * 2) - 1] = start_address;
12938 record_buf_mem[(register_count * 2) - 2] = 4;
12939 start_address = start_address + 4;
12943 else if (0x1F == opcode1)
12945 /* Handle arm syscall insn. */
12946 if (tdep->arm_syscall_record != NULL)
12948 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
12949 ret = tdep->arm_syscall_record (reg_cache, u_regval);
12953 printf_unfiltered (_("no syscall record support\n"));
12958 /* B (1), conditional branch is automatically taken care in process_record,
12959 as PC is saved there. */
12961 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12962 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12968 /* Handling opcode 111 insns. */
12971 thumb_record_branch (insn_decode_record *thumb_insn_r)
12973 uint32_t record_buf[8];
12974 uint32_t bits_h = 0;
12976 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12978 if (2 == bits_h || 3 == bits_h)
12981 record_buf[0] = ARM_LR_REGNUM;
12982 thumb_insn_r->reg_rec_count = 1;
12984 else if (1 == bits_h)
12987 record_buf[0] = ARM_PS_REGNUM;
12988 record_buf[1] = ARM_LR_REGNUM;
12989 thumb_insn_r->reg_rec_count = 2;
12992 /* B(2) is automatically taken care in process_record, as PC is
12995 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
13000 /* Handler for thumb2 load/store multiple instructions. */
13003 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
13005 struct regcache *reg_cache = thumb2_insn_r->regcache;
13007 uint32_t reg_rn, op;
13008 uint32_t register_bits = 0, register_count = 0;
13009 uint32_t index = 0, start_address = 0;
13010 uint32_t record_buf[24], record_buf_mem[48];
13012 ULONGEST u_regval = 0;
13014 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13015 op = bits (thumb2_insn_r->arm_insn, 23, 24);
13017 if (0 == op || 3 == op)
13019 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
13021 /* Handle RFE instruction. */
13022 record_buf[0] = ARM_PS_REGNUM;
13023 thumb2_insn_r->reg_rec_count = 1;
13027 /* Handle SRS instruction after reading banked SP. */
13028 return arm_record_unsupported_insn (thumb2_insn_r);
13031 else if (1 == op || 2 == op)
13033 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
13035 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13036 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
13037 while (register_bits)
13039 if (register_bits & 0x00000001)
13040 record_buf[index++] = register_count;
13043 register_bits = register_bits >> 1;
13045 record_buf[index++] = reg_rn;
13046 record_buf[index++] = ARM_PS_REGNUM;
13047 thumb2_insn_r->reg_rec_count = index;
13051 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13052 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
13053 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
13054 while (register_bits)
13056 if (register_bits & 0x00000001)
13059 register_bits = register_bits >> 1;
13064 /* Start address calculation for LDMDB/LDMEA. */
13065 start_address = u_regval;
13069 /* Start address calculation for LDMDB/LDMEA. */
13070 start_address = u_regval - register_count * 4;
13073 thumb2_insn_r->mem_rec_count = register_count;
13074 while (register_count)
13076 record_buf_mem[register_count * 2 - 1] = start_address;
13077 record_buf_mem[register_count * 2 - 2] = 4;
13078 start_address = start_address + 4;
13081 record_buf[0] = reg_rn;
13082 record_buf[1] = ARM_PS_REGNUM;
13083 thumb2_insn_r->reg_rec_count = 2;
13087 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13089 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13091 return ARM_RECORD_SUCCESS;
13094 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13098 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
13100 struct regcache *reg_cache = thumb2_insn_r->regcache;
13102 uint32_t reg_rd, reg_rn, offset_imm;
13103 uint32_t reg_dest1, reg_dest2;
13104 uint32_t address, offset_addr;
13105 uint32_t record_buf[8], record_buf_mem[8];
13106 uint32_t op1, op2, op3;
13109 ULONGEST u_regval[2];
13111 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
13112 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
13113 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
13115 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
13117 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
13119 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
13120 record_buf[0] = reg_dest1;
13121 record_buf[1] = ARM_PS_REGNUM;
13122 thumb2_insn_r->reg_rec_count = 2;
13125 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
13127 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
13128 record_buf[2] = reg_dest2;
13129 thumb2_insn_r->reg_rec_count = 3;
13134 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13135 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
13137 if (0 == op1 && 0 == op2)
13139 /* Handle STREX. */
13140 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
13141 address = u_regval[0] + (offset_imm * 4);
13142 record_buf_mem[0] = 4;
13143 record_buf_mem[1] = address;
13144 thumb2_insn_r->mem_rec_count = 1;
13145 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
13146 record_buf[0] = reg_rd;
13147 thumb2_insn_r->reg_rec_count = 1;
13149 else if (1 == op1 && 0 == op2)
13151 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
13152 record_buf[0] = reg_rd;
13153 thumb2_insn_r->reg_rec_count = 1;
13154 address = u_regval[0];
13155 record_buf_mem[1] = address;
13159 /* Handle STREXB. */
13160 record_buf_mem[0] = 1;
13161 thumb2_insn_r->mem_rec_count = 1;
13165 /* Handle STREXH. */
13166 record_buf_mem[0] = 2 ;
13167 thumb2_insn_r->mem_rec_count = 1;
13171 /* Handle STREXD. */
13172 address = u_regval[0];
13173 record_buf_mem[0] = 4;
13174 record_buf_mem[2] = 4;
13175 record_buf_mem[3] = address + 4;
13176 thumb2_insn_r->mem_rec_count = 2;
13181 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
13183 if (bit (thumb2_insn_r->arm_insn, 24))
13185 if (bit (thumb2_insn_r->arm_insn, 23))
13186 offset_addr = u_regval[0] + (offset_imm * 4);
13188 offset_addr = u_regval[0] - (offset_imm * 4);
13190 address = offset_addr;
13193 address = u_regval[0];
13195 record_buf_mem[0] = 4;
13196 record_buf_mem[1] = address;
13197 record_buf_mem[2] = 4;
13198 record_buf_mem[3] = address + 4;
13199 thumb2_insn_r->mem_rec_count = 2;
13200 record_buf[0] = reg_rn;
13201 thumb2_insn_r->reg_rec_count = 1;
13205 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13207 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13209 return ARM_RECORD_SUCCESS;
13212 /* Handler for thumb2 data processing (shift register and modified immediate)
13216 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
13218 uint32_t reg_rd, op;
13219 uint32_t record_buf[8];
13221 op = bits (thumb2_insn_r->arm_insn, 21, 24);
13222 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
13224 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
13226 record_buf[0] = ARM_PS_REGNUM;
13227 thumb2_insn_r->reg_rec_count = 1;
13231 record_buf[0] = reg_rd;
13232 record_buf[1] = ARM_PS_REGNUM;
13233 thumb2_insn_r->reg_rec_count = 2;
13236 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13238 return ARM_RECORD_SUCCESS;
13241 /* Generic handler for thumb2 instructions which effect destination and PS
13245 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
13248 uint32_t record_buf[8];
13250 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
13252 record_buf[0] = reg_rd;
13253 record_buf[1] = ARM_PS_REGNUM;
13254 thumb2_insn_r->reg_rec_count = 2;
13256 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13258 return ARM_RECORD_SUCCESS;
13261 /* Handler for thumb2 branch and miscellaneous control instructions. */
13264 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
13266 uint32_t op, op1, op2;
13267 uint32_t record_buf[8];
13269 op = bits (thumb2_insn_r->arm_insn, 20, 26);
13270 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
13271 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
13273 /* Handle MSR insn. */
13274 if (!(op1 & 0x2) && 0x38 == op)
13278 /* CPSR is going to be changed. */
13279 record_buf[0] = ARM_PS_REGNUM;
13280 thumb2_insn_r->reg_rec_count = 1;
13284 arm_record_unsupported_insn(thumb2_insn_r);
13288 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
13291 record_buf[0] = ARM_PS_REGNUM;
13292 record_buf[1] = ARM_LR_REGNUM;
13293 thumb2_insn_r->reg_rec_count = 2;
13296 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13298 return ARM_RECORD_SUCCESS;
13301 /* Handler for thumb2 store single data item instructions. */
13304 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
13306 struct regcache *reg_cache = thumb2_insn_r->regcache;
13308 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
13309 uint32_t address, offset_addr;
13310 uint32_t record_buf[8], record_buf_mem[8];
13313 ULONGEST u_regval[2];
13315 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
13316 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
13317 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13318 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
13320 if (bit (thumb2_insn_r->arm_insn, 23))
13323 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
13324 offset_addr = u_regval[0] + offset_imm;
13325 address = offset_addr;
13330 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
13332 /* Handle STRB (register). */
13333 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
13334 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
13335 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
13336 offset_addr = u_regval[1] << shift_imm;
13337 address = u_regval[0] + offset_addr;
13341 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
13342 if (bit (thumb2_insn_r->arm_insn, 10))
13344 if (bit (thumb2_insn_r->arm_insn, 9))
13345 offset_addr = u_regval[0] + offset_imm;
13347 offset_addr = u_regval[0] - offset_imm;
13349 address = offset_addr;
13352 address = u_regval[0];
13358 /* Store byte instructions. */
13361 record_buf_mem[0] = 1;
13363 /* Store half word instructions. */
13366 record_buf_mem[0] = 2;
13368 /* Store word instructions. */
13371 record_buf_mem[0] = 4;
13375 gdb_assert_not_reached ("no decoding pattern found");
13379 record_buf_mem[1] = address;
13380 thumb2_insn_r->mem_rec_count = 1;
13381 record_buf[0] = reg_rn;
13382 thumb2_insn_r->reg_rec_count = 1;
13384 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13386 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13388 return ARM_RECORD_SUCCESS;
13391 /* Handler for thumb2 load memory hints instructions. */
13394 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
13396 uint32_t record_buf[8];
13397 uint32_t reg_rt, reg_rn;
13399 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
13400 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13402 if (ARM_PC_REGNUM != reg_rt)
13404 record_buf[0] = reg_rt;
13405 record_buf[1] = reg_rn;
13406 record_buf[2] = ARM_PS_REGNUM;
13407 thumb2_insn_r->reg_rec_count = 3;
13409 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13411 return ARM_RECORD_SUCCESS;
13414 return ARM_RECORD_FAILURE;
13417 /* Handler for thumb2 load word instructions. */
13420 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
13422 uint32_t opcode1 = 0, opcode2 = 0;
13423 uint32_t record_buf[8];
13425 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
13426 record_buf[1] = ARM_PS_REGNUM;
13427 thumb2_insn_r->reg_rec_count = 2;
13429 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13431 return ARM_RECORD_SUCCESS;
13434 /* Handler for thumb2 long multiply, long multiply accumulate, and
13435 divide instructions. */
13438 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
13440 uint32_t opcode1 = 0, opcode2 = 0;
13441 uint32_t record_buf[8];
13442 uint32_t reg_src1 = 0;
13444 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
13445 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
13447 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
13449 /* Handle SMULL, UMULL, SMULAL. */
13450 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13451 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
13452 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
13453 record_buf[2] = ARM_PS_REGNUM;
13454 thumb2_insn_r->reg_rec_count = 3;
13456 else if (1 == opcode1 || 3 == opcode2)
13458 /* Handle SDIV and UDIV. */
13459 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
13460 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
13461 record_buf[2] = ARM_PS_REGNUM;
13462 thumb2_insn_r->reg_rec_count = 3;
13465 return ARM_RECORD_FAILURE;
13467 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13469 return ARM_RECORD_SUCCESS;
13472 /* Record handler for thumb32 coprocessor instructions. */
13475 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
13477 if (bit (thumb2_insn_r->arm_insn, 25))
13478 return arm_record_coproc_data_proc (thumb2_insn_r);
13480 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
13483 /* Record handler for advance SIMD structure load/store instructions. */
13486 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
13488 struct regcache *reg_cache = thumb2_insn_r->regcache;
13489 uint32_t l_bit, a_bit, b_bits;
13490 uint32_t record_buf[128], record_buf_mem[128];
13491 uint32_t reg_rn, reg_vd, address, f_esize, f_elem;
13492 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
13495 l_bit = bit (thumb2_insn_r->arm_insn, 21);
13496 a_bit = bit (thumb2_insn_r->arm_insn, 23);
13497 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
13498 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13499 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
13500 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
13501 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
13502 f_esize = 8 * f_ebytes;
13503 f_elem = 8 / f_ebytes;
13507 ULONGEST u_regval = 0;
13508 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
13509 address = u_regval;
13514 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
13516 if (b_bits == 0x07)
13518 else if (b_bits == 0x0a)
13520 else if (b_bits == 0x06)
13522 else if (b_bits == 0x02)
13527 for (index_r = 0; index_r < bf_regs; index_r++)
13529 for (index_e = 0; index_e < f_elem; index_e++)
13531 record_buf_mem[index_m++] = f_ebytes;
13532 record_buf_mem[index_m++] = address;
13533 address = address + f_ebytes;
13534 thumb2_insn_r->mem_rec_count += 1;
13539 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
13541 if (b_bits == 0x09 || b_bits == 0x08)
13543 else if (b_bits == 0x03)
13548 for (index_r = 0; index_r < bf_regs; index_r++)
13549 for (index_e = 0; index_e < f_elem; index_e++)
13551 for (loop_t = 0; loop_t < 2; loop_t++)
13553 record_buf_mem[index_m++] = f_ebytes;
13554 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13555 thumb2_insn_r->mem_rec_count += 1;
13557 address = address + (2 * f_ebytes);
13561 else if ((b_bits & 0x0e) == 0x04)
13563 for (index_e = 0; index_e < f_elem; index_e++)
13565 for (loop_t = 0; loop_t < 3; loop_t++)
13567 record_buf_mem[index_m++] = f_ebytes;
13568 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13569 thumb2_insn_r->mem_rec_count += 1;
13571 address = address + (3 * f_ebytes);
13575 else if (!(b_bits & 0x0e))
13577 for (index_e = 0; index_e < f_elem; index_e++)
13579 for (loop_t = 0; loop_t < 4; loop_t++)
13581 record_buf_mem[index_m++] = f_ebytes;
13582 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13583 thumb2_insn_r->mem_rec_count += 1;
13585 address = address + (4 * f_ebytes);
13591 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
13593 if (bft_size == 0x00)
13595 else if (bft_size == 0x01)
13597 else if (bft_size == 0x02)
13603 if (!(b_bits & 0x0b) || b_bits == 0x08)
13604 thumb2_insn_r->mem_rec_count = 1;
13606 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
13607 thumb2_insn_r->mem_rec_count = 2;
13609 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
13610 thumb2_insn_r->mem_rec_count = 3;
13612 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
13613 thumb2_insn_r->mem_rec_count = 4;
13615 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
13617 record_buf_mem[index_m] = f_ebytes;
13618 record_buf_mem[index_m] = address + (index_m * f_ebytes);
13627 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
13628 thumb2_insn_r->reg_rec_count = 1;
13630 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
13631 thumb2_insn_r->reg_rec_count = 2;
13633 else if ((b_bits & 0x0e) == 0x04)
13634 thumb2_insn_r->reg_rec_count = 3;
13636 else if (!(b_bits & 0x0e))
13637 thumb2_insn_r->reg_rec_count = 4;
13642 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
13643 thumb2_insn_r->reg_rec_count = 1;
13645 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
13646 thumb2_insn_r->reg_rec_count = 2;
13648 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
13649 thumb2_insn_r->reg_rec_count = 3;
13651 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
13652 thumb2_insn_r->reg_rec_count = 4;
13654 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
13655 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
13659 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
13661 record_buf[index_r] = reg_rn;
13662 thumb2_insn_r->reg_rec_count += 1;
13665 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13667 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13672 /* Decodes thumb2 instruction type and invokes its record handler. */
13674 static unsigned int
13675 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
13677 uint32_t op, op1, op2;
13679 op = bit (thumb2_insn_r->arm_insn, 15);
13680 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
13681 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
13685 if (!(op2 & 0x64 ))
13687 /* Load/store multiple instruction. */
13688 return thumb2_record_ld_st_multiple (thumb2_insn_r);
13690 else if (!((op2 & 0x64) ^ 0x04))
13692 /* Load/store (dual/exclusive) and table branch instruction. */
13693 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
13695 else if (!((op2 & 0x20) ^ 0x20))
13697 /* Data-processing (shifted register). */
13698 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
13700 else if (op2 & 0x40)
13702 /* Co-processor instructions. */
13703 return thumb2_record_coproc_insn (thumb2_insn_r);
13706 else if (op1 == 0x02)
13710 /* Branches and miscellaneous control instructions. */
13711 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
13713 else if (op2 & 0x20)
13715 /* Data-processing (plain binary immediate) instruction. */
13716 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13720 /* Data-processing (modified immediate). */
13721 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
13724 else if (op1 == 0x03)
13726 if (!(op2 & 0x71 ))
13728 /* Store single data item. */
13729 return thumb2_record_str_single_data (thumb2_insn_r);
13731 else if (!((op2 & 0x71) ^ 0x10))
13733 /* Advanced SIMD or structure load/store instructions. */
13734 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
13736 else if (!((op2 & 0x67) ^ 0x01))
13738 /* Load byte, memory hints instruction. */
13739 return thumb2_record_ld_mem_hints (thumb2_insn_r);
13741 else if (!((op2 & 0x67) ^ 0x03))
13743 /* Load halfword, memory hints instruction. */
13744 return thumb2_record_ld_mem_hints (thumb2_insn_r);
13746 else if (!((op2 & 0x67) ^ 0x05))
13748 /* Load word instruction. */
13749 return thumb2_record_ld_word (thumb2_insn_r);
13751 else if (!((op2 & 0x70) ^ 0x20))
13753 /* Data-processing (register) instruction. */
13754 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13756 else if (!((op2 & 0x78) ^ 0x30))
13758 /* Multiply, multiply accumulate, abs diff instruction. */
13759 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13761 else if (!((op2 & 0x78) ^ 0x38))
13763 /* Long multiply, long multiply accumulate, and divide. */
13764 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
13766 else if (op2 & 0x40)
13768 /* Co-processor instructions. */
13769 return thumb2_record_coproc_insn (thumb2_insn_r);
13776 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13777 and positive val on fauilure. */
13780 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
13782 gdb_byte buf[insn_size];
13784 memset (&buf[0], 0, insn_size);
13786 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
13788 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
13790 gdbarch_byte_order_for_code (insn_record->gdbarch));
13794 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
13796 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13800 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
13801 uint32_t insn_size)
13804 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13805 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
13807 arm_record_data_proc_misc_ld_str, /* 000. */
13808 arm_record_data_proc_imm, /* 001. */
13809 arm_record_ld_st_imm_offset, /* 010. */
13810 arm_record_ld_st_reg_offset, /* 011. */
13811 arm_record_ld_st_multiple, /* 100. */
13812 arm_record_b_bl, /* 101. */
13813 arm_record_asimd_vfp_coproc, /* 110. */
13814 arm_record_coproc_data_proc /* 111. */
13817 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13818 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
13820 thumb_record_shift_add_sub, /* 000. */
13821 thumb_record_add_sub_cmp_mov, /* 001. */
13822 thumb_record_ld_st_reg_offset, /* 010. */
13823 thumb_record_ld_st_imm_offset, /* 011. */
13824 thumb_record_ld_st_stack, /* 100. */
13825 thumb_record_misc, /* 101. */
13826 thumb_record_ldm_stm_swi, /* 110. */
13827 thumb_record_branch /* 111. */
13830 uint32_t ret = 0; /* return value: negative:failure 0:success. */
13831 uint32_t insn_id = 0;
13833 if (extract_arm_insn (arm_record, insn_size))
13837 printf_unfiltered (_("Process record: error reading memory at "
13838 "addr %s len = %d.\n"),
13839 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
13843 else if (ARM_RECORD == record_type)
13845 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
13846 insn_id = bits (arm_record->arm_insn, 25, 27);
13847 ret = arm_record_extension_space (arm_record);
13848 /* If this insn has fallen into extension space
13849 then we need not decode it anymore. */
13850 if (ret != -1 && !INSN_RECORDED(arm_record))
13852 ret = arm_handle_insn[insn_id] (arm_record);
13855 else if (THUMB_RECORD == record_type)
13857 /* As thumb does not have condition codes, we set negative. */
13858 arm_record->cond = -1;
13859 insn_id = bits (arm_record->arm_insn, 13, 15);
13860 ret = thumb_handle_insn[insn_id] (arm_record);
13862 else if (THUMB2_RECORD == record_type)
13864 /* As thumb does not have condition codes, we set negative. */
13865 arm_record->cond = -1;
13867 /* Swap first half of 32bit thumb instruction with second half. */
13868 arm_record->arm_insn
13869 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
13871 insn_id = thumb2_record_decode_insn_handler (arm_record);
13873 if (insn_id != ARM_RECORD_SUCCESS)
13875 arm_record_unsupported_insn (arm_record);
13881 /* Throw assertion. */
13882 gdb_assert_not_reached ("not a valid instruction, could not decode");
13889 /* Cleans up local record registers and memory allocations. */
13892 deallocate_reg_mem (insn_decode_record *record)
13894 xfree (record->arm_regs);
13895 xfree (record->arm_mems);
13899 /* Parse the current instruction and record the values of the registers and
13900 memory that will be changed in current instruction to record_arch_list".
13901 Return -1 if something is wrong. */
13904 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
13905 CORE_ADDR insn_addr)
13908 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
13909 uint32_t no_of_rec = 0;
13910 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
13911 ULONGEST t_bit = 0, insn_id = 0;
13913 ULONGEST u_regval = 0;
13915 insn_decode_record arm_record;
13917 memset (&arm_record, 0, sizeof (insn_decode_record));
13918 arm_record.regcache = regcache;
13919 arm_record.this_addr = insn_addr;
13920 arm_record.gdbarch = gdbarch;
13923 if (record_debug > 1)
13925 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
13927 paddress (gdbarch, arm_record.this_addr));
13930 if (extract_arm_insn (&arm_record, 2))
13934 printf_unfiltered (_("Process record: error reading memory at "
13935 "addr %s len = %d.\n"),
13936 paddress (arm_record.gdbarch,
13937 arm_record.this_addr), 2);
13942 /* Check the insn, whether it is thumb or arm one. */
13944 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
13945 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
13948 if (!(u_regval & t_bit))
13950 /* We are decoding arm insn. */
13951 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
13955 insn_id = bits (arm_record.arm_insn, 11, 15);
13956 /* is it thumb2 insn? */
13957 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13959 ret = decode_insn (&arm_record, THUMB2_RECORD,
13960 THUMB2_INSN_SIZE_BYTES);
13964 /* We are decoding thumb insn. */
13965 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
13971 /* Record registers. */
13972 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
13973 if (arm_record.arm_regs)
13975 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
13977 if (record_full_arch_list_add_reg
13978 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
13982 /* Record memories. */
13983 if (arm_record.arm_mems)
13985 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
13987 if (record_full_arch_list_add_mem
13988 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
13989 arm_record.arm_mems[no_of_rec].len))
13994 if (record_full_arch_list_add_end ())
13999 deallocate_reg_mem (&arm_record);