1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
50 #include "gdb/sim-arm.h"
53 #include "coff/internal.h"
59 #include "record-full.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data *arm_objfile_data_key;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
93 DEF_VEC_O(arm_mapping_symbol_s);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s) **section_maps;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element *setarmcmdlist = NULL;
102 static struct cmd_list_element *showarmcmdlist = NULL;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
118 static const char *current_fp_model = "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
131 static const char *arm_abi_string = "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings[] =
142 static const char *arm_fallback_mode_string = "auto";
143 static const char *arm_force_mode_string = "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode = -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element *);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat *, const void *,
229 static void convert_to_extended (const struct floatformat *, void *,
232 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
233 struct regcache *regcache,
234 int regnum, gdb_byte *buf);
235 static void arm_neon_quad_write (struct gdbarch *gdbarch,
236 struct regcache *regcache,
237 int regnum, const gdb_byte *buf);
239 struct arm_prologue_cache
241 /* The stack pointer at the time this frame was created; i.e. the
242 caller's stack pointer when this function was called. It is used
243 to identify this frame. */
246 /* The frame base for this frame is just prev_sp - frame size.
247 FRAMESIZE is the distance from the frame pointer to the
248 initial stack pointer. */
252 /* The register used to hold the frame pointer for this frame. */
255 /* Saved register offsets. */
256 struct trad_frame_saved_reg *saved_regs;
259 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
260 CORE_ADDR prologue_start,
261 CORE_ADDR prologue_end,
262 struct arm_prologue_cache *cache);
264 /* Architecture version for displaced stepping. This effects the behaviour of
265 certain instructions, and really should not be hard-wired. */
267 #define DISPLACED_STEPPING_ARCH_VERSION 5
269 /* Set to true if the 32-bit mode is in use. */
273 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
276 arm_psr_thumb_bit (struct gdbarch *gdbarch)
278 if (gdbarch_tdep (gdbarch)->is_m)
284 /* Determine if the processor is currently executing in Thumb mode. */
287 arm_is_thumb (struct regcache *regcache)
290 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
292 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
294 return (cpsr & t_bit) != 0;
297 /* Determine if FRAME is executing in Thumb mode. */
300 arm_frame_is_thumb (struct frame_info *frame)
303 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
305 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
306 directly (from a signal frame or dummy frame) or by interpreting
307 the saved LR (from a prologue or DWARF frame). So consult it and
308 trust the unwinders. */
309 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
311 return (cpsr & t_bit) != 0;
314 /* Callback for VEC_lower_bound. */
317 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
318 const struct arm_mapping_symbol *rhs)
320 return lhs->value < rhs->value;
323 /* Search for the mapping symbol covering MEMADDR. If one is found,
324 return its type. Otherwise, return 0. If START is non-NULL,
325 set *START to the location of the mapping symbol. */
328 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
330 struct obj_section *sec;
332 /* If there are mapping symbols, consult them. */
333 sec = find_pc_section (memaddr);
336 struct arm_per_objfile *data;
337 VEC(arm_mapping_symbol_s) *map;
338 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
342 data = (struct arm_per_objfile *) objfile_data (sec->objfile,
343 arm_objfile_data_key);
346 map = data->section_maps[sec->the_bfd_section->index];
347 if (!VEC_empty (arm_mapping_symbol_s, map))
349 struct arm_mapping_symbol *map_sym;
351 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
352 arm_compare_mapping_symbols);
354 /* VEC_lower_bound finds the earliest ordered insertion
355 point. If the following symbol starts at this exact
356 address, we use that; otherwise, the preceding
357 mapping symbol covers this address. */
358 if (idx < VEC_length (arm_mapping_symbol_s, map))
360 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
361 if (map_sym->value == map_key.value)
364 *start = map_sym->value + obj_section_addr (sec);
365 return map_sym->type;
371 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
373 *start = map_sym->value + obj_section_addr (sec);
374 return map_sym->type;
383 /* Determine if the program counter specified in MEMADDR is in a Thumb
384 function. This function should be called for addresses unrelated to
385 any executing frame; otherwise, prefer arm_frame_is_thumb. */
388 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
390 struct bound_minimal_symbol sym;
392 struct displaced_step_closure* dsc
393 = get_displaced_step_closure_by_addr(memaddr);
395 /* If checking the mode of displaced instruction in copy area, the mode
396 should be determined by instruction on the original address. */
400 fprintf_unfiltered (gdb_stdlog,
401 "displaced: check mode of %.8lx instead of %.8lx\n",
402 (unsigned long) dsc->insn_addr,
403 (unsigned long) memaddr);
404 memaddr = dsc->insn_addr;
407 /* If bit 0 of the address is set, assume this is a Thumb address. */
408 if (IS_THUMB_ADDR (memaddr))
411 /* Respect internal mode override if active. */
412 if (arm_override_mode != -1)
413 return arm_override_mode;
415 /* If the user wants to override the symbol table, let him. */
416 if (strcmp (arm_force_mode_string, "arm") == 0)
418 if (strcmp (arm_force_mode_string, "thumb") == 0)
421 /* ARM v6-M and v7-M are always in Thumb mode. */
422 if (gdbarch_tdep (gdbarch)->is_m)
425 /* If there are mapping symbols, consult them. */
426 type = arm_find_mapping_symbol (memaddr, NULL);
430 /* Thumb functions have a "special" bit set in minimal symbols. */
431 sym = lookup_minimal_symbol_by_pc (memaddr);
433 return (MSYMBOL_IS_SPECIAL (sym.minsym));
435 /* If the user wants to override the fallback mode, let them. */
436 if (strcmp (arm_fallback_mode_string, "arm") == 0)
438 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
441 /* If we couldn't find any symbol, but we're talking to a running
442 target, then trust the current value of $cpsr. This lets
443 "display/i $pc" always show the correct mode (though if there is
444 a symbol table we will not reach here, so it still may not be
445 displayed in the mode it will be executed). */
446 if (target_has_registers)
447 return arm_frame_is_thumb (get_current_frame ());
449 /* Otherwise we're out of luck; we assume ARM. */
453 /* Remove useless bits from addresses in a running program. */
455 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
457 /* On M-profile devices, do not strip the low bit from EXC_RETURN
458 (the magic exception return address). */
459 if (gdbarch_tdep (gdbarch)->is_m
460 && (val & 0xfffffff0) == 0xfffffff0)
464 return UNMAKE_THUMB_ADDR (val);
466 return (val & 0x03fffffc);
469 /* Return 1 if PC is the start of a compiler helper function which
470 can be safely ignored during prologue skipping. IS_THUMB is true
471 if the function is known to be a Thumb function due to the way it
474 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
476 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
477 struct bound_minimal_symbol msym;
479 msym = lookup_minimal_symbol_by_pc (pc);
480 if (msym.minsym != NULL
481 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
482 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
484 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
486 /* The GNU linker's Thumb call stub to foo is named
488 if (strstr (name, "_from_thumb") != NULL)
491 /* On soft-float targets, __truncdfsf2 is called to convert promoted
492 arguments to their argument types in non-prototyped
494 if (startswith (name, "__truncdfsf2"))
496 if (startswith (name, "__aeabi_d2f"))
499 /* Internal functions related to thread-local storage. */
500 if (startswith (name, "__tls_get_addr"))
502 if (startswith (name, "__aeabi_read_tp"))
507 /* If we run against a stripped glibc, we may be unable to identify
508 special functions by name. Check for one important case,
509 __aeabi_read_tp, by comparing the *code* against the default
510 implementation (this is hand-written ARM assembler in glibc). */
513 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
514 == 0xe3e00a0f /* mov r0, #0xffff0fff */
515 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
516 == 0xe240f01f) /* sub pc, r0, #31 */
523 /* Support routines for instruction parsing. */
524 #define submask(x) ((1L << ((x) + 1)) - 1)
525 #define bit(obj,st) (((obj) >> (st)) & 1)
526 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
527 #define sbits(obj,st,fn) \
528 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
529 #define BranchDest(addr,instr) \
530 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
532 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
533 the first 16-bit of instruction, and INSN2 is the second 16-bit of
535 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
536 ((bits ((insn1), 0, 3) << 12) \
537 | (bits ((insn1), 10, 10) << 11) \
538 | (bits ((insn2), 12, 14) << 8) \
539 | bits ((insn2), 0, 7))
541 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
542 the 32-bit instruction. */
543 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
544 ((bits ((insn), 16, 19) << 12) \
545 | bits ((insn), 0, 11))
547 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
550 thumb_expand_immediate (unsigned int imm)
552 unsigned int count = imm >> 7;
560 return (imm & 0xff) | ((imm & 0xff) << 16);
562 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
564 return (imm & 0xff) | ((imm & 0xff) << 8)
565 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
568 return (0x80 | (imm & 0x7f)) << (32 - count);
571 /* Return 1 if the 16-bit Thumb instruction INST might change
572 control flow, 0 otherwise. */
575 thumb_instruction_changes_pc (unsigned short inst)
577 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
580 if ((inst & 0xf000) == 0xd000) /* conditional branch */
583 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
586 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
589 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
592 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
598 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
599 might change control flow, 0 otherwise. */
602 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
604 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
606 /* Branches and miscellaneous control instructions. */
608 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
613 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
615 /* SUBS PC, LR, #imm8. */
618 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
620 /* Conditional branch. */
627 if ((inst1 & 0xfe50) == 0xe810)
629 /* Load multiple or RFE. */
631 if (bit (inst1, 7) && !bit (inst1, 8))
637 else if (!bit (inst1, 7) && bit (inst1, 8))
643 else if (bit (inst1, 7) && bit (inst1, 8))
648 else if (!bit (inst1, 7) && !bit (inst1, 8))
657 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
659 /* MOV PC or MOVS PC. */
663 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
666 if (bits (inst1, 0, 3) == 15)
672 if ((inst2 & 0x0fc0) == 0x0000)
678 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
684 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
693 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
694 epilogue, 0 otherwise. */
697 thumb_instruction_restores_sp (unsigned short insn)
699 return (insn == 0x46bd /* mov sp, r7 */
700 || (insn & 0xff80) == 0xb000 /* add sp, imm */
701 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
704 /* Analyze a Thumb prologue, looking for a recognizable stack frame
705 and frame pointer. Scan until we encounter a store that could
706 clobber the stack frame unexpectedly, or an unknown instruction.
707 Return the last address which is definitely safe to skip for an
708 initial breakpoint. */
711 thumb_analyze_prologue (struct gdbarch *gdbarch,
712 CORE_ADDR start, CORE_ADDR limit,
713 struct arm_prologue_cache *cache)
715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
716 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
719 struct pv_area *stack;
720 struct cleanup *back_to;
722 CORE_ADDR unrecognized_pc = 0;
724 for (i = 0; i < 16; i++)
725 regs[i] = pv_register (i, 0);
726 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
727 back_to = make_cleanup_free_pv_area (stack);
729 while (start < limit)
733 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
735 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
740 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
743 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
744 whether to save LR (R14). */
745 mask = (insn & 0xff) | ((insn & 0x100) << 6);
747 /* Calculate offsets of saved R0-R7 and LR. */
748 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
749 if (mask & (1 << regno))
751 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
753 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
756 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
758 offset = (insn & 0x7f) << 2; /* get scaled offset */
759 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
762 else if (thumb_instruction_restores_sp (insn))
764 /* Don't scan past the epilogue. */
767 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
768 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
770 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
771 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
772 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
774 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
775 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
776 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
778 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
779 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
780 && pv_is_constant (regs[bits (insn, 3, 5)]))
781 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
782 regs[bits (insn, 6, 8)]);
783 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
784 && pv_is_constant (regs[bits (insn, 3, 6)]))
786 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
787 int rm = bits (insn, 3, 6);
788 regs[rd] = pv_add (regs[rd], regs[rm]);
790 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
792 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
793 int src_reg = (insn & 0x78) >> 3;
794 regs[dst_reg] = regs[src_reg];
796 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
798 /* Handle stores to the stack. Normally pushes are used,
799 but with GCC -mtpcs-frame, there may be other stores
800 in the prologue to create the frame. */
801 int regno = (insn >> 8) & 0x7;
804 offset = (insn & 0xff) << 2;
805 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
807 if (pv_area_store_would_trash (stack, addr))
810 pv_area_store (stack, addr, 4, regs[regno]);
812 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
814 int rd = bits (insn, 0, 2);
815 int rn = bits (insn, 3, 5);
818 offset = bits (insn, 6, 10) << 2;
819 addr = pv_add_constant (regs[rn], offset);
821 if (pv_area_store_would_trash (stack, addr))
824 pv_area_store (stack, addr, 4, regs[rd]);
826 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
827 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
828 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
829 /* Ignore stores of argument registers to the stack. */
831 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
832 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
833 /* Ignore block loads from the stack, potentially copying
834 parameters from memory. */
836 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
837 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
838 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
839 /* Similarly ignore single loads from the stack. */
841 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
842 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
843 /* Skip register copies, i.e. saves to another register
844 instead of the stack. */
846 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
847 /* Recognize constant loads; even with small stacks these are necessary
849 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
850 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
852 /* Constant pool loads, for the same reason. */
853 unsigned int constant;
856 loc = start + 4 + bits (insn, 0, 7) * 4;
857 constant = read_memory_unsigned_integer (loc, 4, byte_order);
858 regs[bits (insn, 8, 10)] = pv_constant (constant);
860 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
862 unsigned short inst2;
864 inst2 = read_memory_unsigned_integer (start + 2, 2,
865 byte_order_for_code);
867 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
869 /* BL, BLX. Allow some special function calls when
870 skipping the prologue; GCC generates these before
871 storing arguments to the stack. */
873 int j1, j2, imm1, imm2;
875 imm1 = sbits (insn, 0, 10);
876 imm2 = bits (inst2, 0, 10);
877 j1 = bit (inst2, 13);
878 j2 = bit (inst2, 11);
880 offset = ((imm1 << 12) + (imm2 << 1));
881 offset ^= ((!j2) << 22) | ((!j1) << 23);
883 nextpc = start + 4 + offset;
884 /* For BLX make sure to clear the low bits. */
885 if (bit (inst2, 12) == 0)
886 nextpc = nextpc & 0xfffffffc;
888 if (!skip_prologue_function (gdbarch, nextpc,
889 bit (inst2, 12) != 0))
893 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
895 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
897 pv_t addr = regs[bits (insn, 0, 3)];
900 if (pv_area_store_would_trash (stack, addr))
903 /* Calculate offsets of saved registers. */
904 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
905 if (inst2 & (1 << regno))
907 addr = pv_add_constant (addr, -4);
908 pv_area_store (stack, addr, 4, regs[regno]);
912 regs[bits (insn, 0, 3)] = addr;
915 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
917 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
919 int regno1 = bits (inst2, 12, 15);
920 int regno2 = bits (inst2, 8, 11);
921 pv_t addr = regs[bits (insn, 0, 3)];
923 offset = inst2 & 0xff;
925 addr = pv_add_constant (addr, offset);
927 addr = pv_add_constant (addr, -offset);
929 if (pv_area_store_would_trash (stack, addr))
932 pv_area_store (stack, addr, 4, regs[regno1]);
933 pv_area_store (stack, pv_add_constant (addr, 4),
937 regs[bits (insn, 0, 3)] = addr;
940 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
941 && (inst2 & 0x0c00) == 0x0c00
942 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
944 int regno = bits (inst2, 12, 15);
945 pv_t addr = regs[bits (insn, 0, 3)];
947 offset = inst2 & 0xff;
949 addr = pv_add_constant (addr, offset);
951 addr = pv_add_constant (addr, -offset);
953 if (pv_area_store_would_trash (stack, addr))
956 pv_area_store (stack, addr, 4, regs[regno]);
959 regs[bits (insn, 0, 3)] = addr;
962 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
963 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
965 int regno = bits (inst2, 12, 15);
968 offset = inst2 & 0xfff;
969 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
971 if (pv_area_store_would_trash (stack, addr))
974 pv_area_store (stack, addr, 4, regs[regno]);
977 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
978 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
979 /* Ignore stores of argument registers to the stack. */
982 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
983 && (inst2 & 0x0d00) == 0x0c00
984 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
985 /* Ignore stores of argument registers to the stack. */
988 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
990 && (inst2 & 0x8000) == 0x0000
991 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
992 /* Ignore block loads from the stack, potentially copying
993 parameters from memory. */
996 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
998 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
999 /* Similarly ignore dual loads from the stack. */
1002 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
1003 && (inst2 & 0x0d00) == 0x0c00
1004 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
1005 /* Similarly ignore single loads from the stack. */
1008 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1009 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
1010 /* Similarly ignore single loads from the stack. */
1013 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1014 && (inst2 & 0x8000) == 0x0000)
1016 unsigned int imm = ((bits (insn, 10, 10) << 11)
1017 | (bits (inst2, 12, 14) << 8)
1018 | bits (inst2, 0, 7));
1020 regs[bits (inst2, 8, 11)]
1021 = pv_add_constant (regs[bits (insn, 0, 3)],
1022 thumb_expand_immediate (imm));
1025 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1026 && (inst2 & 0x8000) == 0x0000)
1028 unsigned int imm = ((bits (insn, 10, 10) << 11)
1029 | (bits (inst2, 12, 14) << 8)
1030 | bits (inst2, 0, 7));
1032 regs[bits (inst2, 8, 11)]
1033 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1036 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1037 && (inst2 & 0x8000) == 0x0000)
1039 unsigned int imm = ((bits (insn, 10, 10) << 11)
1040 | (bits (inst2, 12, 14) << 8)
1041 | bits (inst2, 0, 7));
1043 regs[bits (inst2, 8, 11)]
1044 = pv_add_constant (regs[bits (insn, 0, 3)],
1045 - (CORE_ADDR) thumb_expand_immediate (imm));
1048 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1049 && (inst2 & 0x8000) == 0x0000)
1051 unsigned int imm = ((bits (insn, 10, 10) << 11)
1052 | (bits (inst2, 12, 14) << 8)
1053 | bits (inst2, 0, 7));
1055 regs[bits (inst2, 8, 11)]
1056 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1059 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1061 unsigned int imm = ((bits (insn, 10, 10) << 11)
1062 | (bits (inst2, 12, 14) << 8)
1063 | bits (inst2, 0, 7));
1065 regs[bits (inst2, 8, 11)]
1066 = pv_constant (thumb_expand_immediate (imm));
1069 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1072 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1074 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1077 else if (insn == 0xea5f /* mov.w Rd,Rm */
1078 && (inst2 & 0xf0f0) == 0)
1080 int dst_reg = (inst2 & 0x0f00) >> 8;
1081 int src_reg = inst2 & 0xf;
1082 regs[dst_reg] = regs[src_reg];
1085 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1087 /* Constant pool loads. */
1088 unsigned int constant;
1091 offset = bits (inst2, 0, 11);
1093 loc = start + 4 + offset;
1095 loc = start + 4 - offset;
1097 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1098 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1101 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1103 /* Constant pool loads. */
1104 unsigned int constant;
1107 offset = bits (inst2, 0, 7) << 2;
1109 loc = start + 4 + offset;
1111 loc = start + 4 - offset;
1113 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1114 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1116 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1117 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1120 else if (thumb2_instruction_changes_pc (insn, inst2))
1122 /* Don't scan past anything that might change control flow. */
1127 /* The optimizer might shove anything into the prologue,
1128 so we just skip what we don't recognize. */
1129 unrecognized_pc = start;
1134 else if (thumb_instruction_changes_pc (insn))
1136 /* Don't scan past anything that might change control flow. */
1141 /* The optimizer might shove anything into the prologue,
1142 so we just skip what we don't recognize. */
1143 unrecognized_pc = start;
1150 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1151 paddress (gdbarch, start));
1153 if (unrecognized_pc == 0)
1154 unrecognized_pc = start;
1158 do_cleanups (back_to);
1159 return unrecognized_pc;
1162 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1164 /* Frame pointer is fp. Frame size is constant. */
1165 cache->framereg = ARM_FP_REGNUM;
1166 cache->framesize = -regs[ARM_FP_REGNUM].k;
1168 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1170 /* Frame pointer is r7. Frame size is constant. */
1171 cache->framereg = THUMB_FP_REGNUM;
1172 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1176 /* Try the stack pointer... this is a bit desperate. */
1177 cache->framereg = ARM_SP_REGNUM;
1178 cache->framesize = -regs[ARM_SP_REGNUM].k;
1181 for (i = 0; i < 16; i++)
1182 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1183 cache->saved_regs[i].addr = offset;
1185 do_cleanups (back_to);
1186 return unrecognized_pc;
1190 /* Try to analyze the instructions starting from PC, which load symbol
1191 __stack_chk_guard. Return the address of instruction after loading this
1192 symbol, set the dest register number to *BASEREG, and set the size of
1193 instructions for loading symbol in OFFSET. Return 0 if instructions are
1197 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1198 unsigned int *destreg, int *offset)
1200 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1201 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1202 unsigned int low, high, address;
1207 unsigned short insn1
1208 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1210 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1212 *destreg = bits (insn1, 8, 10);
1214 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1215 address = read_memory_unsigned_integer (address, 4,
1216 byte_order_for_code);
1218 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1220 unsigned short insn2
1221 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1223 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1226 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1228 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1230 /* movt Rd, #const */
1231 if ((insn1 & 0xfbc0) == 0xf2c0)
1233 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1234 *destreg = bits (insn2, 8, 11);
1236 address = (high << 16 | low);
1243 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1245 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1247 address = bits (insn, 0, 11) + pc + 8;
1248 address = read_memory_unsigned_integer (address, 4,
1249 byte_order_for_code);
1251 *destreg = bits (insn, 12, 15);
1254 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1256 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1259 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1261 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1263 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1264 *destreg = bits (insn, 12, 15);
1266 address = (high << 16 | low);
1274 /* Try to skip a sequence of instructions used for stack protector. If PC
1275 points to the first instruction of this sequence, return the address of
1276 first instruction after this sequence, otherwise, return original PC.
1278 On arm, this sequence of instructions is composed of mainly three steps,
1279 Step 1: load symbol __stack_chk_guard,
1280 Step 2: load from address of __stack_chk_guard,
1281 Step 3: store it to somewhere else.
1283 Usually, instructions on step 2 and step 3 are the same on various ARM
1284 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1285 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1286 instructions in step 1 vary from different ARM architectures. On ARMv7,
1289 movw Rn, #:lower16:__stack_chk_guard
1290 movt Rn, #:upper16:__stack_chk_guard
1297 .word __stack_chk_guard
1299 Since ldr/str is a very popular instruction, we can't use them as
1300 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1301 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1302 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1305 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1307 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1308 unsigned int basereg;
1309 struct bound_minimal_symbol stack_chk_guard;
1311 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1314 /* Try to parse the instructions in Step 1. */
1315 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1320 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1321 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1322 Otherwise, this sequence cannot be for stack protector. */
1323 if (stack_chk_guard.minsym == NULL
1324 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1329 unsigned int destreg;
1331 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1333 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1334 if ((insn & 0xf800) != 0x6800)
1336 if (bits (insn, 3, 5) != basereg)
1338 destreg = bits (insn, 0, 2);
1340 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1341 byte_order_for_code);
1342 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1343 if ((insn & 0xf800) != 0x6000)
1345 if (destreg != bits (insn, 0, 2))
1350 unsigned int destreg;
1352 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1354 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1355 if ((insn & 0x0e500000) != 0x04100000)
1357 if (bits (insn, 16, 19) != basereg)
1359 destreg = bits (insn, 12, 15);
1360 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1361 insn = read_memory_unsigned_integer (pc + offset + 4,
1362 4, byte_order_for_code);
1363 if ((insn & 0x0e500000) != 0x04000000)
1365 if (bits (insn, 12, 15) != destreg)
1368 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1371 return pc + offset + 4;
1373 return pc + offset + 8;
1376 /* Advance the PC across any function entry prologue instructions to
1377 reach some "real" code.
1379 The APCS (ARM Procedure Call Standard) defines the following
1383 [stmfd sp!, {a1,a2,a3,a4}]
1384 stmfd sp!, {...,fp,ip,lr,pc}
1385 [stfe f7, [sp, #-12]!]
1386 [stfe f6, [sp, #-12]!]
1387 [stfe f5, [sp, #-12]!]
1388 [stfe f4, [sp, #-12]!]
1389 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1392 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1394 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1396 CORE_ADDR func_addr, limit_pc;
1398 /* See if we can determine the end of the prologue via the symbol table.
1399 If so, then return either PC, or the PC after the prologue, whichever
1401 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1403 CORE_ADDR post_prologue_pc
1404 = skip_prologue_using_sal (gdbarch, func_addr);
1405 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1407 if (post_prologue_pc)
1409 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1412 /* GCC always emits a line note before the prologue and another
1413 one after, even if the two are at the same address or on the
1414 same line. Take advantage of this so that we do not need to
1415 know every instruction that might appear in the prologue. We
1416 will have producer information for most binaries; if it is
1417 missing (e.g. for -gstabs), assuming the GNU tools. */
1418 if (post_prologue_pc
1420 || COMPUNIT_PRODUCER (cust) == NULL
1421 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1422 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1423 return post_prologue_pc;
1425 if (post_prologue_pc != 0)
1427 CORE_ADDR analyzed_limit;
1429 /* For non-GCC compilers, make sure the entire line is an
1430 acceptable prologue; GDB will round this function's
1431 return value up to the end of the following line so we
1432 can not skip just part of a line (and we do not want to).
1434 RealView does not treat the prologue specially, but does
1435 associate prologue code with the opening brace; so this
1436 lets us skip the first line if we think it is the opening
1438 if (arm_pc_is_thumb (gdbarch, func_addr))
1439 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1440 post_prologue_pc, NULL);
1442 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1443 post_prologue_pc, NULL);
1445 if (analyzed_limit != post_prologue_pc)
1448 return post_prologue_pc;
1452 /* Can't determine prologue from the symbol table, need to examine
1455 /* Find an upper limit on the function prologue using the debug
1456 information. If the debug information could not be used to provide
1457 that bound, then use an arbitrary large number as the upper bound. */
1458 /* Like arm_scan_prologue, stop no later than pc + 64. */
1459 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1461 limit_pc = pc + 64; /* Magic. */
1464 /* Check if this is Thumb code. */
1465 if (arm_pc_is_thumb (gdbarch, pc))
1466 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1468 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1472 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1473 This function decodes a Thumb function prologue to determine:
1474 1) the size of the stack frame
1475 2) which registers are saved on it
1476 3) the offsets of saved regs
1477 4) the offset from the stack pointer to the frame pointer
1479 A typical Thumb function prologue would create this stack frame
1480 (offsets relative to FP)
1481 old SP -> 24 stack parameters
1484 R7 -> 0 local variables (16 bytes)
1485 SP -> -12 additional stack space (12 bytes)
1486 The frame size would thus be 36 bytes, and the frame offset would be
1487 12 bytes. The frame register is R7.
1489 The comments for thumb_skip_prolog() describe the algorithm we use
1490 to detect the end of the prolog. */
1494 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1495 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1497 CORE_ADDR prologue_start;
1498 CORE_ADDR prologue_end;
1500 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1503 /* See comment in arm_scan_prologue for an explanation of
1505 if (prologue_end > prologue_start + 64)
1507 prologue_end = prologue_start + 64;
1511 /* We're in the boondocks: we have no idea where the start of the
1515 prologue_end = min (prologue_end, prev_pc);
1517 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1520 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1523 arm_instruction_changes_pc (uint32_t this_instr)
1525 if (bits (this_instr, 28, 31) == INST_NV)
1526 /* Unconditional instructions. */
1527 switch (bits (this_instr, 24, 27))
1531 /* Branch with Link and change to Thumb. */
1536 /* Coprocessor register transfer. */
1537 if (bits (this_instr, 12, 15) == 15)
1538 error (_("Invalid update to pc in instruction"));
1544 switch (bits (this_instr, 25, 27))
1547 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1549 /* Multiplies and extra load/stores. */
1550 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1551 /* Neither multiplies nor extension load/stores are allowed
1555 /* Otherwise, miscellaneous instructions. */
1557 /* BX <reg>, BXJ <reg>, BLX <reg> */
1558 if (bits (this_instr, 4, 27) == 0x12fff1
1559 || bits (this_instr, 4, 27) == 0x12fff2
1560 || bits (this_instr, 4, 27) == 0x12fff3)
1563 /* Other miscellaneous instructions are unpredictable if they
1567 /* Data processing instruction. Fall through. */
1570 if (bits (this_instr, 12, 15) == 15)
1577 /* Media instructions and architecturally undefined instructions. */
1578 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1582 if (bit (this_instr, 20) == 0)
1586 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1592 /* Load/store multiple. */
1593 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1599 /* Branch and branch with link. */
1604 /* Coprocessor transfers or SWIs can not affect PC. */
1608 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1612 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1616 arm_instruction_restores_sp (unsigned int insn)
1618 if (bits (insn, 28, 31) != INST_NV)
1620 if ((insn & 0x0df0f000) == 0x0080d000
1621 /* ADD SP (register or immediate). */
1622 || (insn & 0x0df0f000) == 0x0040d000
1623 /* SUB SP (register or immediate). */
1624 || (insn & 0x0ffffff0) == 0x01a0d000
1626 || (insn & 0x0fff0000) == 0x08bd0000
1628 || (insn & 0x0fff0000) == 0x049d0000)
1629 /* POP of a single register. */
1636 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1637 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1638 fill it in. Return the first address not recognized as a prologue
1641 We recognize all the instructions typically found in ARM prologues,
1642 plus harmless instructions which can be skipped (either for analysis
1643 purposes, or a more restrictive set that can be skipped when finding
1644 the end of the prologue). */
1647 arm_analyze_prologue (struct gdbarch *gdbarch,
1648 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1649 struct arm_prologue_cache *cache)
1651 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1652 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1654 CORE_ADDR offset, current_pc;
1655 pv_t regs[ARM_FPS_REGNUM];
1656 struct pv_area *stack;
1657 struct cleanup *back_to;
1658 CORE_ADDR unrecognized_pc = 0;
1660 /* Search the prologue looking for instructions that set up the
1661 frame pointer, adjust the stack pointer, and save registers.
1663 Be careful, however, and if it doesn't look like a prologue,
1664 don't try to scan it. If, for instance, a frameless function
1665 begins with stmfd sp!, then we will tell ourselves there is
1666 a frame, which will confuse stack traceback, as well as "finish"
1667 and other operations that rely on a knowledge of the stack
1670 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1671 regs[regno] = pv_register (regno, 0);
1672 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1673 back_to = make_cleanup_free_pv_area (stack);
1675 for (current_pc = prologue_start;
1676 current_pc < prologue_end;
1680 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1682 if (insn == 0xe1a0c00d) /* mov ip, sp */
1684 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1687 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1688 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1690 unsigned imm = insn & 0xff; /* immediate value */
1691 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1692 int rd = bits (insn, 12, 15);
1693 imm = (imm >> rot) | (imm << (32 - rot));
1694 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1697 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1698 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1700 unsigned imm = insn & 0xff; /* immediate value */
1701 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1702 int rd = bits (insn, 12, 15);
1703 imm = (imm >> rot) | (imm << (32 - rot));
1704 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1707 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1710 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1712 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1713 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1714 regs[bits (insn, 12, 15)]);
1717 else if ((insn & 0xffff0000) == 0xe92d0000)
1718 /* stmfd sp!, {..., fp, ip, lr, pc}
1720 stmfd sp!, {a1, a2, a3, a4} */
1722 int mask = insn & 0xffff;
1724 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1727 /* Calculate offsets of saved registers. */
1728 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1729 if (mask & (1 << regno))
1732 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1733 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1736 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1737 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1738 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1740 /* No need to add this to saved_regs -- it's just an arg reg. */
1743 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1744 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1745 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1747 /* No need to add this to saved_regs -- it's just an arg reg. */
1750 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1752 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1754 /* No need to add this to saved_regs -- it's just arg regs. */
1757 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1759 unsigned imm = insn & 0xff; /* immediate value */
1760 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1761 imm = (imm >> rot) | (imm << (32 - rot));
1762 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1764 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1766 unsigned imm = insn & 0xff; /* immediate value */
1767 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1768 imm = (imm >> rot) | (imm << (32 - rot));
1769 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1771 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1773 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1775 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1778 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1779 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1780 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1782 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1784 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1786 int n_saved_fp_regs;
1787 unsigned int fp_start_reg, fp_bound_reg;
1789 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1792 if ((insn & 0x800) == 0x800) /* N0 is set */
1794 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1795 n_saved_fp_regs = 3;
1797 n_saved_fp_regs = 1;
1801 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1802 n_saved_fp_regs = 2;
1804 n_saved_fp_regs = 4;
1807 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1808 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1809 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1811 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1812 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1813 regs[fp_start_reg++]);
1816 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1818 /* Allow some special function calls when skipping the
1819 prologue; GCC generates these before storing arguments to
1821 CORE_ADDR dest = BranchDest (current_pc, insn);
1823 if (skip_prologue_function (gdbarch, dest, 0))
1828 else if ((insn & 0xf0000000) != 0xe0000000)
1829 break; /* Condition not true, exit early. */
1830 else if (arm_instruction_changes_pc (insn))
1831 /* Don't scan past anything that might change control flow. */
1833 else if (arm_instruction_restores_sp (insn))
1835 /* Don't scan past the epilogue. */
1838 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1839 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1840 /* Ignore block loads from the stack, potentially copying
1841 parameters from memory. */
1843 else if ((insn & 0xfc500000) == 0xe4100000
1844 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1845 /* Similarly ignore single loads from the stack. */
1847 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1848 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1849 register instead of the stack. */
1853 /* The optimizer might shove anything into the prologue, if
1854 we build up cache (cache != NULL) from scanning prologue,
1855 we just skip what we don't recognize and scan further to
1856 make cache as complete as possible. However, if we skip
1857 prologue, we'll stop immediately on unrecognized
1859 unrecognized_pc = current_pc;
1867 if (unrecognized_pc == 0)
1868 unrecognized_pc = current_pc;
1872 int framereg, framesize;
1874 /* The frame size is just the distance from the frame register
1875 to the original stack pointer. */
1876 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1878 /* Frame pointer is fp. */
1879 framereg = ARM_FP_REGNUM;
1880 framesize = -regs[ARM_FP_REGNUM].k;
1884 /* Try the stack pointer... this is a bit desperate. */
1885 framereg = ARM_SP_REGNUM;
1886 framesize = -regs[ARM_SP_REGNUM].k;
1889 cache->framereg = framereg;
1890 cache->framesize = framesize;
1892 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1893 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1894 cache->saved_regs[regno].addr = offset;
1898 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1899 paddress (gdbarch, unrecognized_pc));
1901 do_cleanups (back_to);
1902 return unrecognized_pc;
1906 arm_scan_prologue (struct frame_info *this_frame,
1907 struct arm_prologue_cache *cache)
1909 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1910 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1912 CORE_ADDR prologue_start, prologue_end, current_pc;
1913 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1914 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1915 pv_t regs[ARM_FPS_REGNUM];
1916 struct pv_area *stack;
1917 struct cleanup *back_to;
1920 /* Assume there is no frame until proven otherwise. */
1921 cache->framereg = ARM_SP_REGNUM;
1922 cache->framesize = 0;
1924 /* Check for Thumb prologue. */
1925 if (arm_frame_is_thumb (this_frame))
1927 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1931 /* Find the function prologue. If we can't find the function in
1932 the symbol table, peek in the stack frame to find the PC. */
1933 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1936 /* One way to find the end of the prologue (which works well
1937 for unoptimized code) is to do the following:
1939 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1942 prologue_end = prev_pc;
1943 else if (sal.end < prologue_end)
1944 prologue_end = sal.end;
1946 This mechanism is very accurate so long as the optimizer
1947 doesn't move any instructions from the function body into the
1948 prologue. If this happens, sal.end will be the last
1949 instruction in the first hunk of prologue code just before
1950 the first instruction that the scheduler has moved from
1951 the body to the prologue.
1953 In order to make sure that we scan all of the prologue
1954 instructions, we use a slightly less accurate mechanism which
1955 may scan more than necessary. To help compensate for this
1956 lack of accuracy, the prologue scanning loop below contains
1957 several clauses which'll cause the loop to terminate early if
1958 an implausible prologue instruction is encountered.
1964 is a suitable endpoint since it accounts for the largest
1965 possible prologue plus up to five instructions inserted by
1968 if (prologue_end > prologue_start + 64)
1970 prologue_end = prologue_start + 64; /* See above. */
1975 /* We have no symbol information. Our only option is to assume this
1976 function has a standard stack frame and the normal frame register.
1977 Then, we can find the value of our frame pointer on entrance to
1978 the callee (or at the present moment if this is the innermost frame).
1979 The value stored there should be the address of the stmfd + 8. */
1980 CORE_ADDR frame_loc;
1981 LONGEST return_value;
1983 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1984 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1988 prologue_start = gdbarch_addr_bits_remove
1989 (gdbarch, return_value) - 8;
1990 prologue_end = prologue_start + 64; /* See above. */
1994 if (prev_pc < prologue_end)
1995 prologue_end = prev_pc;
1997 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2000 static struct arm_prologue_cache *
2001 arm_make_prologue_cache (struct frame_info *this_frame)
2004 struct arm_prologue_cache *cache;
2005 CORE_ADDR unwound_fp;
2007 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2008 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2010 arm_scan_prologue (this_frame, cache);
2012 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2013 if (unwound_fp == 0)
2016 cache->prev_sp = unwound_fp + cache->framesize;
2018 /* Calculate actual addresses of saved registers using offsets
2019 determined by arm_scan_prologue. */
2020 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2021 if (trad_frame_addr_p (cache->saved_regs, reg))
2022 cache->saved_regs[reg].addr += cache->prev_sp;
2027 /* Implementation of the stop_reason hook for arm_prologue frames. */
2029 static enum unwind_stop_reason
2030 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
2033 struct arm_prologue_cache *cache;
2036 if (*this_cache == NULL)
2037 *this_cache = arm_make_prologue_cache (this_frame);
2038 cache = (struct arm_prologue_cache *) *this_cache;
2040 /* This is meant to halt the backtrace at "_start". */
2041 pc = get_frame_pc (this_frame);
2042 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2043 return UNWIND_OUTERMOST;
2045 /* If we've hit a wall, stop. */
2046 if (cache->prev_sp == 0)
2047 return UNWIND_OUTERMOST;
2049 return UNWIND_NO_REASON;
2052 /* Our frame ID for a normal frame is the current function's starting PC
2053 and the caller's SP when we were called. */
2056 arm_prologue_this_id (struct frame_info *this_frame,
2058 struct frame_id *this_id)
2060 struct arm_prologue_cache *cache;
2064 if (*this_cache == NULL)
2065 *this_cache = arm_make_prologue_cache (this_frame);
2066 cache = (struct arm_prologue_cache *) *this_cache;
2068 /* Use function start address as part of the frame ID. If we cannot
2069 identify the start address (due to missing symbol information),
2070 fall back to just using the current PC. */
2071 pc = get_frame_pc (this_frame);
2072 func = get_frame_func (this_frame);
2076 id = frame_id_build (cache->prev_sp, func);
2080 static struct value *
2081 arm_prologue_prev_register (struct frame_info *this_frame,
2085 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2086 struct arm_prologue_cache *cache;
2088 if (*this_cache == NULL)
2089 *this_cache = arm_make_prologue_cache (this_frame);
2090 cache = (struct arm_prologue_cache *) *this_cache;
2092 /* If we are asked to unwind the PC, then we need to return the LR
2093 instead. The prologue may save PC, but it will point into this
2094 frame's prologue, not the next frame's resume location. Also
2095 strip the saved T bit. A valid LR may have the low bit set, but
2096 a valid PC never does. */
2097 if (prev_regnum == ARM_PC_REGNUM)
2101 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2102 return frame_unwind_got_constant (this_frame, prev_regnum,
2103 arm_addr_bits_remove (gdbarch, lr));
2106 /* SP is generally not saved to the stack, but this frame is
2107 identified by the next frame's stack pointer at the time of the call.
2108 The value was already reconstructed into PREV_SP. */
2109 if (prev_regnum == ARM_SP_REGNUM)
2110 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2112 /* The CPSR may have been changed by the call instruction and by the
2113 called function. The only bit we can reconstruct is the T bit,
2114 by checking the low bit of LR as of the call. This is a reliable
2115 indicator of Thumb-ness except for some ARM v4T pre-interworking
2116 Thumb code, which could get away with a clear low bit as long as
2117 the called function did not use bx. Guess that all other
2118 bits are unchanged; the condition flags are presumably lost,
2119 but the processor status is likely valid. */
2120 if (prev_regnum == ARM_PS_REGNUM)
2123 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2125 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2126 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2127 if (IS_THUMB_ADDR (lr))
2131 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2134 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2138 struct frame_unwind arm_prologue_unwind = {
2140 arm_prologue_unwind_stop_reason,
2141 arm_prologue_this_id,
2142 arm_prologue_prev_register,
2144 default_frame_sniffer
2147 /* Maintain a list of ARM exception table entries per objfile, similar to the
2148 list of mapping symbols. We only cache entries for standard ARM-defined
2149 personality routines; the cache will contain only the frame unwinding
2150 instructions associated with the entry (not the descriptors). */
2152 static const struct objfile_data *arm_exidx_data_key;
2154 struct arm_exidx_entry
2159 typedef struct arm_exidx_entry arm_exidx_entry_s;
2160 DEF_VEC_O(arm_exidx_entry_s);
2162 struct arm_exidx_data
2164 VEC(arm_exidx_entry_s) **section_maps;
2168 arm_exidx_data_free (struct objfile *objfile, void *arg)
2170 struct arm_exidx_data *data = (struct arm_exidx_data *) arg;
2173 for (i = 0; i < objfile->obfd->section_count; i++)
2174 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2178 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2179 const struct arm_exidx_entry *rhs)
2181 return lhs->addr < rhs->addr;
2184 static struct obj_section *
2185 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2187 struct obj_section *osect;
2189 ALL_OBJFILE_OSECTIONS (objfile, osect)
2190 if (bfd_get_section_flags (objfile->obfd,
2191 osect->the_bfd_section) & SEC_ALLOC)
2193 bfd_vma start, size;
2194 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2195 size = bfd_get_section_size (osect->the_bfd_section);
2197 if (start <= vma && vma < start + size)
2204 /* Parse contents of exception table and exception index sections
2205 of OBJFILE, and fill in the exception table entry cache.
2207 For each entry that refers to a standard ARM-defined personality
2208 routine, extract the frame unwinding instructions (from either
2209 the index or the table section). The unwinding instructions
2211 - extracting them from the rest of the table data
2212 - converting to host endianness
2213 - appending the implicit 0xb0 ("Finish") code
2215 The extracted and normalized instructions are stored for later
2216 retrieval by the arm_find_exidx_entry routine. */
2219 arm_exidx_new_objfile (struct objfile *objfile)
2221 struct cleanup *cleanups;
2222 struct arm_exidx_data *data;
2223 asection *exidx, *extab;
2224 bfd_vma exidx_vma = 0, extab_vma = 0;
2225 bfd_size_type exidx_size = 0, extab_size = 0;
2226 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2229 /* If we've already touched this file, do nothing. */
2230 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2232 cleanups = make_cleanup (null_cleanup, NULL);
2234 /* Read contents of exception table and index. */
2235 exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
2238 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2239 exidx_size = bfd_get_section_size (exidx);
2240 exidx_data = (gdb_byte *) xmalloc (exidx_size);
2241 make_cleanup (xfree, exidx_data);
2243 if (!bfd_get_section_contents (objfile->obfd, exidx,
2244 exidx_data, 0, exidx_size))
2246 do_cleanups (cleanups);
2251 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2254 extab_vma = bfd_section_vma (objfile->obfd, extab);
2255 extab_size = bfd_get_section_size (extab);
2256 extab_data = (gdb_byte *) xmalloc (extab_size);
2257 make_cleanup (xfree, extab_data);
2259 if (!bfd_get_section_contents (objfile->obfd, extab,
2260 extab_data, 0, extab_size))
2262 do_cleanups (cleanups);
2267 /* Allocate exception table data structure. */
2268 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2269 set_objfile_data (objfile, arm_exidx_data_key, data);
2270 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2271 objfile->obfd->section_count,
2272 VEC(arm_exidx_entry_s) *);
2274 /* Fill in exception table. */
2275 for (i = 0; i < exidx_size / 8; i++)
2277 struct arm_exidx_entry new_exidx_entry;
2278 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2279 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2280 bfd_vma addr = 0, word = 0;
2281 int n_bytes = 0, n_words = 0;
2282 struct obj_section *sec;
2283 gdb_byte *entry = NULL;
2285 /* Extract address of start of function. */
2286 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2287 idx += exidx_vma + i * 8;
2289 /* Find section containing function and compute section offset. */
2290 sec = arm_obj_section_from_vma (objfile, idx);
2293 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2295 /* Determine address of exception table entry. */
2298 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2300 else if ((val & 0xff000000) == 0x80000000)
2302 /* Exception table entry embedded in .ARM.exidx
2303 -- must be short form. */
2307 else if (!(val & 0x80000000))
2309 /* Exception table entry in .ARM.extab. */
2310 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2311 addr += exidx_vma + i * 8 + 4;
2313 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2315 word = bfd_h_get_32 (objfile->obfd,
2316 extab_data + addr - extab_vma);
2319 if ((word & 0xff000000) == 0x80000000)
2324 else if ((word & 0xff000000) == 0x81000000
2325 || (word & 0xff000000) == 0x82000000)
2329 n_words = ((word >> 16) & 0xff);
2331 else if (!(word & 0x80000000))
2334 struct obj_section *pers_sec;
2335 int gnu_personality = 0;
2337 /* Custom personality routine. */
2338 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2339 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2341 /* Check whether we've got one of the variants of the
2342 GNU personality routines. */
2343 pers_sec = arm_obj_section_from_vma (objfile, pers);
2346 static const char *personality[] =
2348 "__gcc_personality_v0",
2349 "__gxx_personality_v0",
2350 "__gcj_personality_v0",
2351 "__gnu_objc_personality_v0",
2355 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2358 for (k = 0; personality[k]; k++)
2359 if (lookup_minimal_symbol_by_pc_name
2360 (pc, personality[k], objfile))
2362 gnu_personality = 1;
2367 /* If so, the next word contains a word count in the high
2368 byte, followed by the same unwind instructions as the
2369 pre-defined forms. */
2371 && addr + 4 <= extab_vma + extab_size)
2373 word = bfd_h_get_32 (objfile->obfd,
2374 extab_data + addr - extab_vma);
2377 n_words = ((word >> 24) & 0xff);
2383 /* Sanity check address. */
2385 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2386 n_words = n_bytes = 0;
2388 /* The unwind instructions reside in WORD (only the N_BYTES least
2389 significant bytes are valid), followed by N_WORDS words in the
2390 extab section starting at ADDR. */
2391 if (n_bytes || n_words)
2394 = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack,
2395 n_bytes + n_words * 4 + 1);
2398 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2402 word = bfd_h_get_32 (objfile->obfd,
2403 extab_data + addr - extab_vma);
2406 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2407 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2408 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2409 *p++ = (gdb_byte) (word & 0xff);
2412 /* Implied "Finish" to terminate the list. */
2416 /* Push entry onto vector. They are guaranteed to always
2417 appear in order of increasing addresses. */
2418 new_exidx_entry.addr = idx;
2419 new_exidx_entry.entry = entry;
2420 VEC_safe_push (arm_exidx_entry_s,
2421 data->section_maps[sec->the_bfd_section->index],
2425 do_cleanups (cleanups);
2428 /* Search for the exception table entry covering MEMADDR. If one is found,
2429 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2430 set *START to the start of the region covered by this entry. */
2433 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2435 struct obj_section *sec;
2437 sec = find_pc_section (memaddr);
2440 struct arm_exidx_data *data;
2441 VEC(arm_exidx_entry_s) *map;
2442 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2445 data = ((struct arm_exidx_data *)
2446 objfile_data (sec->objfile, arm_exidx_data_key));
2449 map = data->section_maps[sec->the_bfd_section->index];
2450 if (!VEC_empty (arm_exidx_entry_s, map))
2452 struct arm_exidx_entry *map_sym;
2454 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2455 arm_compare_exidx_entries);
2457 /* VEC_lower_bound finds the earliest ordered insertion
2458 point. If the following symbol starts at this exact
2459 address, we use that; otherwise, the preceding
2460 exception table entry covers this address. */
2461 if (idx < VEC_length (arm_exidx_entry_s, map))
2463 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2464 if (map_sym->addr == map_key.addr)
2467 *start = map_sym->addr + obj_section_addr (sec);
2468 return map_sym->entry;
2474 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2476 *start = map_sym->addr + obj_section_addr (sec);
2477 return map_sym->entry;
2486 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2487 instruction list from the ARM exception table entry ENTRY, allocate and
2488 return a prologue cache structure describing how to unwind this frame.
2490 Return NULL if the unwinding instruction list contains a "spare",
2491 "reserved" or "refuse to unwind" instruction as defined in section
2492 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2493 for the ARM Architecture" document. */
2495 static struct arm_prologue_cache *
2496 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2501 struct arm_prologue_cache *cache;
2502 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2503 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2509 /* Whenever we reload SP, we actually have to retrieve its
2510 actual value in the current frame. */
2513 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2515 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2516 vsp = get_frame_register_unsigned (this_frame, reg);
2520 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2521 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2527 /* Decode next unwind instruction. */
2530 if ((insn & 0xc0) == 0)
2532 int offset = insn & 0x3f;
2533 vsp += (offset << 2) + 4;
2535 else if ((insn & 0xc0) == 0x40)
2537 int offset = insn & 0x3f;
2538 vsp -= (offset << 2) + 4;
2540 else if ((insn & 0xf0) == 0x80)
2542 int mask = ((insn & 0xf) << 8) | *entry++;
2545 /* The special case of an all-zero mask identifies
2546 "Refuse to unwind". We return NULL to fall back
2547 to the prologue analyzer. */
2551 /* Pop registers r4..r15 under mask. */
2552 for (i = 0; i < 12; i++)
2553 if (mask & (1 << i))
2555 cache->saved_regs[4 + i].addr = vsp;
2559 /* Special-case popping SP -- we need to reload vsp. */
2560 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2563 else if ((insn & 0xf0) == 0x90)
2565 int reg = insn & 0xf;
2567 /* Reserved cases. */
2568 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2571 /* Set SP from another register and mark VSP for reload. */
2572 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2575 else if ((insn & 0xf0) == 0xa0)
2577 int count = insn & 0x7;
2578 int pop_lr = (insn & 0x8) != 0;
2581 /* Pop r4..r[4+count]. */
2582 for (i = 0; i <= count; i++)
2584 cache->saved_regs[4 + i].addr = vsp;
2588 /* If indicated by flag, pop LR as well. */
2591 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2595 else if (insn == 0xb0)
2597 /* We could only have updated PC by popping into it; if so, it
2598 will show up as address. Otherwise, copy LR into PC. */
2599 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2600 cache->saved_regs[ARM_PC_REGNUM]
2601 = cache->saved_regs[ARM_LR_REGNUM];
2606 else if (insn == 0xb1)
2608 int mask = *entry++;
2611 /* All-zero mask and mask >= 16 is "spare". */
2612 if (mask == 0 || mask >= 16)
2615 /* Pop r0..r3 under mask. */
2616 for (i = 0; i < 4; i++)
2617 if (mask & (1 << i))
2619 cache->saved_regs[i].addr = vsp;
2623 else if (insn == 0xb2)
2625 ULONGEST offset = 0;
2630 offset |= (*entry & 0x7f) << shift;
2633 while (*entry++ & 0x80);
2635 vsp += 0x204 + (offset << 2);
2637 else if (insn == 0xb3)
2639 int start = *entry >> 4;
2640 int count = (*entry++) & 0xf;
2643 /* Only registers D0..D15 are valid here. */
2644 if (start + count >= 16)
2647 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2648 for (i = 0; i <= count; i++)
2650 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2654 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2657 else if ((insn & 0xf8) == 0xb8)
2659 int count = insn & 0x7;
2662 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2663 for (i = 0; i <= count; i++)
2665 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2669 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2672 else if (insn == 0xc6)
2674 int start = *entry >> 4;
2675 int count = (*entry++) & 0xf;
2678 /* Only registers WR0..WR15 are valid. */
2679 if (start + count >= 16)
2682 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2683 for (i = 0; i <= count; i++)
2685 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2689 else if (insn == 0xc7)
2691 int mask = *entry++;
2694 /* All-zero mask and mask >= 16 is "spare". */
2695 if (mask == 0 || mask >= 16)
2698 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2699 for (i = 0; i < 4; i++)
2700 if (mask & (1 << i))
2702 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2706 else if ((insn & 0xf8) == 0xc0)
2708 int count = insn & 0x7;
2711 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2712 for (i = 0; i <= count; i++)
2714 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2718 else if (insn == 0xc8)
2720 int start = *entry >> 4;
2721 int count = (*entry++) & 0xf;
2724 /* Only registers D0..D31 are valid. */
2725 if (start + count >= 16)
2728 /* Pop VFP double-precision registers
2729 D[16+start]..D[16+start+count]. */
2730 for (i = 0; i <= count; i++)
2732 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2736 else if (insn == 0xc9)
2738 int start = *entry >> 4;
2739 int count = (*entry++) & 0xf;
2742 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2743 for (i = 0; i <= count; i++)
2745 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2749 else if ((insn & 0xf8) == 0xd0)
2751 int count = insn & 0x7;
2754 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2755 for (i = 0; i <= count; i++)
2757 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2763 /* Everything else is "spare". */
2768 /* If we restore SP from a register, assume this was the frame register.
2769 Otherwise just fall back to SP as frame register. */
2770 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2771 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2773 cache->framereg = ARM_SP_REGNUM;
2775 /* Determine offset to previous frame. */
2777 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2779 /* We already got the previous SP. */
2780 cache->prev_sp = vsp;
2785 /* Unwinding via ARM exception table entries. Note that the sniffer
2786 already computes a filled-in prologue cache, which is then used
2787 with the same arm_prologue_this_id and arm_prologue_prev_register
2788 routines also used for prologue-parsing based unwinding. */
2791 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2792 struct frame_info *this_frame,
2793 void **this_prologue_cache)
2795 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2796 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2797 CORE_ADDR addr_in_block, exidx_region, func_start;
2798 struct arm_prologue_cache *cache;
2801 /* See if we have an ARM exception table entry covering this address. */
2802 addr_in_block = get_frame_address_in_block (this_frame);
2803 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2807 /* The ARM exception table does not describe unwind information
2808 for arbitrary PC values, but is guaranteed to be correct only
2809 at call sites. We have to decide here whether we want to use
2810 ARM exception table information for this frame, or fall back
2811 to using prologue parsing. (Note that if we have DWARF CFI,
2812 this sniffer isn't even called -- CFI is always preferred.)
2814 Before we make this decision, however, we check whether we
2815 actually have *symbol* information for the current frame.
2816 If not, prologue parsing would not work anyway, so we might
2817 as well use the exception table and hope for the best. */
2818 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2822 /* If the next frame is "normal", we are at a call site in this
2823 frame, so exception information is guaranteed to be valid. */
2824 if (get_next_frame (this_frame)
2825 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2828 /* We also assume exception information is valid if we're currently
2829 blocked in a system call. The system library is supposed to
2830 ensure this, so that e.g. pthread cancellation works.
2832 But before verifying the instruction at the point of call, make
2833 sure this_frame is actually making a call (or, said differently,
2834 that it is not the innermost frame). For that, we compare
2835 this_frame's PC vs this_frame's addr_in_block. If equal, it means
2836 there is no call (otherwise, the PC would be the return address,
2837 which is the instruction after the call). */
2839 if (get_frame_pc (this_frame) != addr_in_block)
2841 if (arm_frame_is_thumb (this_frame))
2845 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2846 byte_order_for_code, &insn)
2847 && (insn & 0xff00) == 0xdf00 /* svc */)
2854 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2855 byte_order_for_code, &insn)
2856 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2861 /* Bail out if we don't know that exception information is valid. */
2865 /* The ARM exception index does not mark the *end* of the region
2866 covered by the entry, and some functions will not have any entry.
2867 To correctly recognize the end of the covered region, the linker
2868 should have inserted dummy records with a CANTUNWIND marker.
2870 Unfortunately, current versions of GNU ld do not reliably do
2871 this, and thus we may have found an incorrect entry above.
2872 As a (temporary) sanity check, we only use the entry if it
2873 lies *within* the bounds of the function. Note that this check
2874 might reject perfectly valid entries that just happen to cover
2875 multiple functions; therefore this check ought to be removed
2876 once the linker is fixed. */
2877 if (func_start > exidx_region)
2881 /* Decode the list of unwinding instructions into a prologue cache.
2882 Note that this may fail due to e.g. a "refuse to unwind" code. */
2883 cache = arm_exidx_fill_cache (this_frame, entry);
2887 *this_prologue_cache = cache;
2891 struct frame_unwind arm_exidx_unwind = {
2893 default_frame_unwind_stop_reason,
2894 arm_prologue_this_id,
2895 arm_prologue_prev_register,
2897 arm_exidx_unwind_sniffer
2900 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2901 trampoline, return the target PC. Otherwise return 0.
2903 void call0a (char c, short s, int i, long l) {}
2907 (*pointer_to_call0a) (c, s, i, l);
2910 Instead of calling a stub library function _call_via_xx (xx is
2911 the register name), GCC may inline the trampoline in the object
2912 file as below (register r2 has the address of call0a).
2915 .type main, %function
2924 The trampoline 'bx r2' doesn't belong to main. */
2927 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2929 /* The heuristics of recognizing such trampoline is that FRAME is
2930 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2931 if (arm_frame_is_thumb (frame))
2935 if (target_read_memory (pc, buf, 2) == 0)
2937 struct gdbarch *gdbarch = get_frame_arch (frame);
2938 enum bfd_endian byte_order_for_code
2939 = gdbarch_byte_order_for_code (gdbarch);
2941 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2943 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2946 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2948 /* Clear the LSB so that gdb core sets step-resume
2949 breakpoint at the right address. */
2950 return UNMAKE_THUMB_ADDR (dest);
2958 static struct arm_prologue_cache *
2959 arm_make_stub_cache (struct frame_info *this_frame)
2961 struct arm_prologue_cache *cache;
2963 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2964 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2966 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2971 /* Our frame ID for a stub frame is the current SP and LR. */
2974 arm_stub_this_id (struct frame_info *this_frame,
2976 struct frame_id *this_id)
2978 struct arm_prologue_cache *cache;
2980 if (*this_cache == NULL)
2981 *this_cache = arm_make_stub_cache (this_frame);
2982 cache = (struct arm_prologue_cache *) *this_cache;
2984 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2988 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2989 struct frame_info *this_frame,
2990 void **this_prologue_cache)
2992 CORE_ADDR addr_in_block;
2994 CORE_ADDR pc, start_addr;
2997 addr_in_block = get_frame_address_in_block (this_frame);
2998 pc = get_frame_pc (this_frame);
2999 if (in_plt_section (addr_in_block)
3000 /* We also use the stub winder if the target memory is unreadable
3001 to avoid having the prologue unwinder trying to read it. */
3002 || target_read_memory (pc, dummy, 4) != 0)
3005 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
3006 && arm_skip_bx_reg (this_frame, pc) != 0)
3012 struct frame_unwind arm_stub_unwind = {
3014 default_frame_unwind_stop_reason,
3016 arm_prologue_prev_register,
3018 arm_stub_unwind_sniffer
3021 /* Put here the code to store, into CACHE->saved_regs, the addresses
3022 of the saved registers of frame described by THIS_FRAME. CACHE is
3025 static struct arm_prologue_cache *
3026 arm_m_exception_cache (struct frame_info *this_frame)
3028 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3029 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3030 struct arm_prologue_cache *cache;
3031 CORE_ADDR unwound_sp;
3034 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
3035 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3037 unwound_sp = get_frame_register_unsigned (this_frame,
3040 /* The hardware saves eight 32-bit words, comprising xPSR,
3041 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3042 "B1.5.6 Exception entry behavior" in
3043 "ARMv7-M Architecture Reference Manual". */
3044 cache->saved_regs[0].addr = unwound_sp;
3045 cache->saved_regs[1].addr = unwound_sp + 4;
3046 cache->saved_regs[2].addr = unwound_sp + 8;
3047 cache->saved_regs[3].addr = unwound_sp + 12;
3048 cache->saved_regs[12].addr = unwound_sp + 16;
3049 cache->saved_regs[14].addr = unwound_sp + 20;
3050 cache->saved_regs[15].addr = unwound_sp + 24;
3051 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
3053 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3054 aligner between the top of the 32-byte stack frame and the
3055 previous context's stack pointer. */
3056 cache->prev_sp = unwound_sp + 32;
3057 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
3058 && (xpsr & (1 << 9)) != 0)
3059 cache->prev_sp += 4;
3064 /* Implementation of function hook 'this_id' in
3065 'struct frame_uwnind'. */
3068 arm_m_exception_this_id (struct frame_info *this_frame,
3070 struct frame_id *this_id)
3072 struct arm_prologue_cache *cache;
3074 if (*this_cache == NULL)
3075 *this_cache = arm_m_exception_cache (this_frame);
3076 cache = (struct arm_prologue_cache *) *this_cache;
3078 /* Our frame ID for a stub frame is the current SP and LR. */
3079 *this_id = frame_id_build (cache->prev_sp,
3080 get_frame_pc (this_frame));
3083 /* Implementation of function hook 'prev_register' in
3084 'struct frame_uwnind'. */
3086 static struct value *
3087 arm_m_exception_prev_register (struct frame_info *this_frame,
3091 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3092 struct arm_prologue_cache *cache;
3094 if (*this_cache == NULL)
3095 *this_cache = arm_m_exception_cache (this_frame);
3096 cache = (struct arm_prologue_cache *) *this_cache;
3098 /* The value was already reconstructed into PREV_SP. */
3099 if (prev_regnum == ARM_SP_REGNUM)
3100 return frame_unwind_got_constant (this_frame, prev_regnum,
3103 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3107 /* Implementation of function hook 'sniffer' in
3108 'struct frame_uwnind'. */
3111 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3112 struct frame_info *this_frame,
3113 void **this_prologue_cache)
3115 CORE_ADDR this_pc = get_frame_pc (this_frame);
3117 /* No need to check is_m; this sniffer is only registered for
3118 M-profile architectures. */
3120 /* Exception frames return to one of these magic PCs. Other values
3121 are not defined as of v7-M. See details in "B1.5.8 Exception
3122 return behavior" in "ARMv7-M Architecture Reference Manual". */
3123 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3124 || this_pc == 0xfffffffd)
3130 /* Frame unwinder for M-profile exceptions. */
3132 struct frame_unwind arm_m_exception_unwind =
3135 default_frame_unwind_stop_reason,
3136 arm_m_exception_this_id,
3137 arm_m_exception_prev_register,
3139 arm_m_exception_unwind_sniffer
3143 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3145 struct arm_prologue_cache *cache;
3147 if (*this_cache == NULL)
3148 *this_cache = arm_make_prologue_cache (this_frame);
3149 cache = (struct arm_prologue_cache *) *this_cache;
3151 return cache->prev_sp - cache->framesize;
3154 struct frame_base arm_normal_base = {
3155 &arm_prologue_unwind,
3156 arm_normal_frame_base,
3157 arm_normal_frame_base,
3158 arm_normal_frame_base
3161 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3162 dummy frame. The frame ID's base needs to match the TOS value
3163 saved by save_dummy_frame_tos() and returned from
3164 arm_push_dummy_call, and the PC needs to match the dummy frame's
3167 static struct frame_id
3168 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3170 return frame_id_build (get_frame_register_unsigned (this_frame,
3172 get_frame_pc (this_frame));
3175 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3176 be used to construct the previous frame's ID, after looking up the
3177 containing function). */
3180 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3183 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3184 return arm_addr_bits_remove (gdbarch, pc);
3188 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3190 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3193 static struct value *
3194 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3197 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3199 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3204 /* The PC is normally copied from the return column, which
3205 describes saves of LR. However, that version may have an
3206 extra bit set to indicate Thumb state. The bit is not
3208 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3209 return frame_unwind_got_constant (this_frame, regnum,
3210 arm_addr_bits_remove (gdbarch, lr));
3213 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3214 cpsr = get_frame_register_unsigned (this_frame, regnum);
3215 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3216 if (IS_THUMB_ADDR (lr))
3220 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3223 internal_error (__FILE__, __LINE__,
3224 _("Unexpected register %d"), regnum);
3229 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3230 struct dwarf2_frame_state_reg *reg,
3231 struct frame_info *this_frame)
3237 reg->how = DWARF2_FRAME_REG_FN;
3238 reg->loc.fn = arm_dwarf2_prev_register;
3241 reg->how = DWARF2_FRAME_REG_CFA;
3246 /* Implement the stack_frame_destroyed_p gdbarch method. */
3249 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3251 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3252 unsigned int insn, insn2;
3253 int found_return = 0, found_stack_adjust = 0;
3254 CORE_ADDR func_start, func_end;
3258 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3261 /* The epilogue is a sequence of instructions along the following lines:
3263 - add stack frame size to SP or FP
3264 - [if frame pointer used] restore SP from FP
3265 - restore registers from SP [may include PC]
3266 - a return-type instruction [if PC wasn't already restored]
3268 In a first pass, we scan forward from the current PC and verify the
3269 instructions we find as compatible with this sequence, ending in a
3272 However, this is not sufficient to distinguish indirect function calls
3273 within a function from indirect tail calls in the epilogue in some cases.
3274 Therefore, if we didn't already find any SP-changing instruction during
3275 forward scan, we add a backward scanning heuristic to ensure we actually
3276 are in the epilogue. */
3279 while (scan_pc < func_end && !found_return)
3281 if (target_read_memory (scan_pc, buf, 2))
3285 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3287 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3289 else if (insn == 0x46f7) /* mov pc, lr */
3291 else if (thumb_instruction_restores_sp (insn))
3293 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3296 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3298 if (target_read_memory (scan_pc, buf, 2))
3302 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3304 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3306 if (insn2 & 0x8000) /* <registers> include PC. */
3309 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3310 && (insn2 & 0x0fff) == 0x0b04)
3312 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3315 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3316 && (insn2 & 0x0e00) == 0x0a00)
3328 /* Since any instruction in the epilogue sequence, with the possible
3329 exception of return itself, updates the stack pointer, we need to
3330 scan backwards for at most one instruction. Try either a 16-bit or
3331 a 32-bit instruction. This is just a heuristic, so we do not worry
3332 too much about false positives. */
3334 if (pc - 4 < func_start)
3336 if (target_read_memory (pc - 4, buf, 4))
3339 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3340 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3342 if (thumb_instruction_restores_sp (insn2))
3343 found_stack_adjust = 1;
3344 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3345 found_stack_adjust = 1;
3346 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3347 && (insn2 & 0x0fff) == 0x0b04)
3348 found_stack_adjust = 1;
3349 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3350 && (insn2 & 0x0e00) == 0x0a00)
3351 found_stack_adjust = 1;
3353 return found_stack_adjust;
3356 /* Implement the stack_frame_destroyed_p gdbarch method. */
3359 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3361 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3364 CORE_ADDR func_start, func_end;
3366 if (arm_pc_is_thumb (gdbarch, pc))
3367 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3369 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3372 /* We are in the epilogue if the previous instruction was a stack
3373 adjustment and the next instruction is a possible return (bx, mov
3374 pc, or pop). We could have to scan backwards to find the stack
3375 adjustment, or forwards to find the return, but this is a decent
3376 approximation. First scan forwards. */
3379 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3380 if (bits (insn, 28, 31) != INST_NV)
3382 if ((insn & 0x0ffffff0) == 0x012fff10)
3385 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3388 else if ((insn & 0x0fff0000) == 0x08bd0000
3389 && (insn & 0x0000c000) != 0)
3390 /* POP (LDMIA), including PC or LR. */
3397 /* Scan backwards. This is just a heuristic, so do not worry about
3398 false positives from mode changes. */
3400 if (pc < func_start + 4)
3403 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3404 if (arm_instruction_restores_sp (insn))
3411 /* When arguments must be pushed onto the stack, they go on in reverse
3412 order. The code below implements a FILO (stack) to do this. */
3417 struct stack_item *prev;
3421 static struct stack_item *
3422 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
3424 struct stack_item *si;
3425 si = XNEW (struct stack_item);
3426 si->data = (gdb_byte *) xmalloc (len);
3429 memcpy (si->data, contents, len);
3433 static struct stack_item *
3434 pop_stack_item (struct stack_item *si)
3436 struct stack_item *dead = si;
3444 /* Return the alignment (in bytes) of the given type. */
3447 arm_type_align (struct type *t)
3453 t = check_typedef (t);
3454 switch (TYPE_CODE (t))
3457 /* Should never happen. */
3458 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3462 case TYPE_CODE_ENUM:
3466 case TYPE_CODE_RANGE:
3468 case TYPE_CODE_CHAR:
3469 case TYPE_CODE_BOOL:
3470 return TYPE_LENGTH (t);
3472 case TYPE_CODE_ARRAY:
3473 if (TYPE_VECTOR (t))
3475 /* Use the natural alignment for vector types (the same for
3476 scalar type), but the maximum alignment is 64-bit. */
3477 if (TYPE_LENGTH (t) > 8)
3480 return TYPE_LENGTH (t);
3483 return arm_type_align (TYPE_TARGET_TYPE (t));
3484 case TYPE_CODE_COMPLEX:
3485 return arm_type_align (TYPE_TARGET_TYPE (t));
3487 case TYPE_CODE_STRUCT:
3488 case TYPE_CODE_UNION:
3490 for (n = 0; n < TYPE_NFIELDS (t); n++)
3492 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3500 /* Possible base types for a candidate for passing and returning in
3503 enum arm_vfp_cprc_base_type
3512 /* The length of one element of base type B. */
3515 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3519 case VFP_CPRC_SINGLE:
3521 case VFP_CPRC_DOUBLE:
3523 case VFP_CPRC_VEC64:
3525 case VFP_CPRC_VEC128:
3528 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3533 /* The character ('s', 'd' or 'q') for the type of VFP register used
3534 for passing base type B. */
3537 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3541 case VFP_CPRC_SINGLE:
3543 case VFP_CPRC_DOUBLE:
3545 case VFP_CPRC_VEC64:
3547 case VFP_CPRC_VEC128:
3550 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3555 /* Determine whether T may be part of a candidate for passing and
3556 returning in VFP registers, ignoring the limit on the total number
3557 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3558 classification of the first valid component found; if it is not
3559 VFP_CPRC_UNKNOWN, all components must have the same classification
3560 as *BASE_TYPE. If it is found that T contains a type not permitted
3561 for passing and returning in VFP registers, a type differently
3562 classified from *BASE_TYPE, or two types differently classified
3563 from each other, return -1, otherwise return the total number of
3564 base-type elements found (possibly 0 in an empty structure or
3565 array). Vector types are not currently supported, matching the
3566 generic AAPCS support. */
3569 arm_vfp_cprc_sub_candidate (struct type *t,
3570 enum arm_vfp_cprc_base_type *base_type)
3572 t = check_typedef (t);
3573 switch (TYPE_CODE (t))
3576 switch (TYPE_LENGTH (t))
3579 if (*base_type == VFP_CPRC_UNKNOWN)
3580 *base_type = VFP_CPRC_SINGLE;
3581 else if (*base_type != VFP_CPRC_SINGLE)
3586 if (*base_type == VFP_CPRC_UNKNOWN)
3587 *base_type = VFP_CPRC_DOUBLE;
3588 else if (*base_type != VFP_CPRC_DOUBLE)
3597 case TYPE_CODE_COMPLEX:
3598 /* Arguments of complex T where T is one of the types float or
3599 double get treated as if they are implemented as:
3608 switch (TYPE_LENGTH (t))
3611 if (*base_type == VFP_CPRC_UNKNOWN)
3612 *base_type = VFP_CPRC_SINGLE;
3613 else if (*base_type != VFP_CPRC_SINGLE)
3618 if (*base_type == VFP_CPRC_UNKNOWN)
3619 *base_type = VFP_CPRC_DOUBLE;
3620 else if (*base_type != VFP_CPRC_DOUBLE)
3629 case TYPE_CODE_ARRAY:
3631 if (TYPE_VECTOR (t))
3633 /* A 64-bit or 128-bit containerized vector type are VFP
3635 switch (TYPE_LENGTH (t))
3638 if (*base_type == VFP_CPRC_UNKNOWN)
3639 *base_type = VFP_CPRC_VEC64;
3642 if (*base_type == VFP_CPRC_UNKNOWN)
3643 *base_type = VFP_CPRC_VEC128;
3654 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t),
3658 if (TYPE_LENGTH (t) == 0)
3660 gdb_assert (count == 0);
3663 else if (count == 0)
3665 unitlen = arm_vfp_cprc_unit_length (*base_type);
3666 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3667 return TYPE_LENGTH (t) / unitlen;
3672 case TYPE_CODE_STRUCT:
3677 for (i = 0; i < TYPE_NFIELDS (t); i++)
3679 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3681 if (sub_count == -1)
3685 if (TYPE_LENGTH (t) == 0)
3687 gdb_assert (count == 0);
3690 else if (count == 0)
3692 unitlen = arm_vfp_cprc_unit_length (*base_type);
3693 if (TYPE_LENGTH (t) != unitlen * count)
3698 case TYPE_CODE_UNION:
3703 for (i = 0; i < TYPE_NFIELDS (t); i++)
3705 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3707 if (sub_count == -1)
3709 count = (count > sub_count ? count : sub_count);
3711 if (TYPE_LENGTH (t) == 0)
3713 gdb_assert (count == 0);
3716 else if (count == 0)
3718 unitlen = arm_vfp_cprc_unit_length (*base_type);
3719 if (TYPE_LENGTH (t) != unitlen * count)
3731 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3732 if passed to or returned from a non-variadic function with the VFP
3733 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3734 *BASE_TYPE to the base type for T and *COUNT to the number of
3735 elements of that base type before returning. */
3738 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3741 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3742 int c = arm_vfp_cprc_sub_candidate (t, &b);
3743 if (c <= 0 || c > 4)
3750 /* Return 1 if the VFP ABI should be used for passing arguments to and
3751 returning values from a function of type FUNC_TYPE, 0
3755 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3757 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3758 /* Variadic functions always use the base ABI. Assume that functions
3759 without debug info are not variadic. */
3760 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3762 /* The VFP ABI is only supported as a variant of AAPCS. */
3763 if (tdep->arm_abi != ARM_ABI_AAPCS)
3765 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3768 /* We currently only support passing parameters in integer registers, which
3769 conforms with GCC's default model, and VFP argument passing following
3770 the VFP variant of AAPCS. Several other variants exist and
3771 we should probably support some of them based on the selected ABI. */
3774 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3775 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3776 struct value **args, CORE_ADDR sp, int struct_return,
3777 CORE_ADDR struct_addr)
3779 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3783 struct stack_item *si = NULL;
3786 unsigned vfp_regs_free = (1 << 16) - 1;
3788 /* Determine the type of this function and whether the VFP ABI
3790 ftype = check_typedef (value_type (function));
3791 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3792 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3793 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3795 /* Set the return address. For the ARM, the return breakpoint is
3796 always at BP_ADDR. */
3797 if (arm_pc_is_thumb (gdbarch, bp_addr))
3799 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3801 /* Walk through the list of args and determine how large a temporary
3802 stack is required. Need to take care here as structs may be
3803 passed on the stack, and we have to push them. */
3806 argreg = ARM_A1_REGNUM;
3809 /* The struct_return pointer occupies the first parameter
3810 passing register. */
3814 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3815 gdbarch_register_name (gdbarch, argreg),
3816 paddress (gdbarch, struct_addr));
3817 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3821 for (argnum = 0; argnum < nargs; argnum++)
3824 struct type *arg_type;
3825 struct type *target_type;
3826 enum type_code typecode;
3827 const bfd_byte *val;
3829 enum arm_vfp_cprc_base_type vfp_base_type;
3831 int may_use_core_reg = 1;
3833 arg_type = check_typedef (value_type (args[argnum]));
3834 len = TYPE_LENGTH (arg_type);
3835 target_type = TYPE_TARGET_TYPE (arg_type);
3836 typecode = TYPE_CODE (arg_type);
3837 val = value_contents (args[argnum]);
3839 align = arm_type_align (arg_type);
3840 /* Round alignment up to a whole number of words. */
3841 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3842 /* Different ABIs have different maximum alignments. */
3843 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3845 /* The APCS ABI only requires word alignment. */
3846 align = INT_REGISTER_SIZE;
3850 /* The AAPCS requires at most doubleword alignment. */
3851 if (align > INT_REGISTER_SIZE * 2)
3852 align = INT_REGISTER_SIZE * 2;
3856 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3864 /* Because this is a CPRC it cannot go in a core register or
3865 cause a core register to be skipped for alignment.
3866 Either it goes in VFP registers and the rest of this loop
3867 iteration is skipped for this argument, or it goes on the
3868 stack (and the stack alignment code is correct for this
3870 may_use_core_reg = 0;
3872 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3873 shift = unit_length / 4;
3874 mask = (1 << (shift * vfp_base_count)) - 1;
3875 for (regno = 0; regno < 16; regno += shift)
3876 if (((vfp_regs_free >> regno) & mask) == mask)
3885 vfp_regs_free &= ~(mask << regno);
3886 reg_scaled = regno / shift;
3887 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3888 for (i = 0; i < vfp_base_count; i++)
3892 if (reg_char == 'q')
3893 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3894 val + i * unit_length);
3897 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3898 reg_char, reg_scaled + i);
3899 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3901 regcache_cooked_write (regcache, regnum,
3902 val + i * unit_length);
3909 /* This CPRC could not go in VFP registers, so all VFP
3910 registers are now marked as used. */
3915 /* Push stack padding for dowubleword alignment. */
3916 if (nstack & (align - 1))
3918 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3919 nstack += INT_REGISTER_SIZE;
3922 /* Doubleword aligned quantities must go in even register pairs. */
3923 if (may_use_core_reg
3924 && argreg <= ARM_LAST_ARG_REGNUM
3925 && align > INT_REGISTER_SIZE
3929 /* If the argument is a pointer to a function, and it is a
3930 Thumb function, create a LOCAL copy of the value and set
3931 the THUMB bit in it. */
3932 if (TYPE_CODE_PTR == typecode
3933 && target_type != NULL
3934 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3936 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3937 if (arm_pc_is_thumb (gdbarch, regval))
3939 bfd_byte *copy = (bfd_byte *) alloca (len);
3940 store_unsigned_integer (copy, len, byte_order,
3941 MAKE_THUMB_ADDR (regval));
3946 /* Copy the argument to general registers or the stack in
3947 register-sized pieces. Large arguments are split between
3948 registers and stack. */
3951 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3953 = extract_unsigned_integer (val, partial_len, byte_order);
3955 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3957 /* The argument is being passed in a general purpose
3959 if (byte_order == BFD_ENDIAN_BIG)
3960 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3962 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3964 gdbarch_register_name
3966 phex (regval, INT_REGISTER_SIZE));
3967 regcache_cooked_write_unsigned (regcache, argreg, regval);
3972 gdb_byte buf[INT_REGISTER_SIZE];
3974 memset (buf, 0, sizeof (buf));
3975 store_unsigned_integer (buf, partial_len, byte_order, regval);
3977 /* Push the arguments onto the stack. */
3979 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3981 si = push_stack_item (si, buf, INT_REGISTER_SIZE);
3982 nstack += INT_REGISTER_SIZE;
3989 /* If we have an odd number of words to push, then decrement the stack
3990 by one word now, so first stack argument will be dword aligned. */
3997 write_memory (sp, si->data, si->len);
3998 si = pop_stack_item (si);
4001 /* Finally, update teh SP register. */
4002 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
4008 /* Always align the frame to an 8-byte boundary. This is required on
4009 some platforms and harmless on the rest. */
4012 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
4014 /* Align the stack to eight bytes. */
4015 return sp & ~ (CORE_ADDR) 7;
4019 print_fpu_flags (struct ui_file *file, int flags)
4021 if (flags & (1 << 0))
4022 fputs_filtered ("IVO ", file);
4023 if (flags & (1 << 1))
4024 fputs_filtered ("DVZ ", file);
4025 if (flags & (1 << 2))
4026 fputs_filtered ("OFL ", file);
4027 if (flags & (1 << 3))
4028 fputs_filtered ("UFL ", file);
4029 if (flags & (1 << 4))
4030 fputs_filtered ("INX ", file);
4031 fputc_filtered ('\n', file);
4034 /* Print interesting information about the floating point processor
4035 (if present) or emulator. */
4037 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
4038 struct frame_info *frame, const char *args)
4040 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
4043 type = (status >> 24) & 127;
4044 if (status & (1 << 31))
4045 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
4047 fprintf_filtered (file, _("Software FPU type %d\n"), type);
4048 /* i18n: [floating point unit] mask */
4049 fputs_filtered (_("mask: "), file);
4050 print_fpu_flags (file, status >> 16);
4051 /* i18n: [floating point unit] flags */
4052 fputs_filtered (_("flags: "), file);
4053 print_fpu_flags (file, status);
4056 /* Construct the ARM extended floating point type. */
4057 static struct type *
4058 arm_ext_type (struct gdbarch *gdbarch)
4060 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4062 if (!tdep->arm_ext_type)
4064 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
4065 floatformats_arm_ext);
4067 return tdep->arm_ext_type;
4070 static struct type *
4071 arm_neon_double_type (struct gdbarch *gdbarch)
4073 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4075 if (tdep->neon_double_type == NULL)
4077 struct type *t, *elem;
4079 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
4081 elem = builtin_type (gdbarch)->builtin_uint8;
4082 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
4083 elem = builtin_type (gdbarch)->builtin_uint16;
4084 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
4085 elem = builtin_type (gdbarch)->builtin_uint32;
4086 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
4087 elem = builtin_type (gdbarch)->builtin_uint64;
4088 append_composite_type_field (t, "u64", elem);
4089 elem = builtin_type (gdbarch)->builtin_float;
4090 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
4091 elem = builtin_type (gdbarch)->builtin_double;
4092 append_composite_type_field (t, "f64", elem);
4094 TYPE_VECTOR (t) = 1;
4095 TYPE_NAME (t) = "neon_d";
4096 tdep->neon_double_type = t;
4099 return tdep->neon_double_type;
4102 /* FIXME: The vector types are not correctly ordered on big-endian
4103 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4104 bits of d0 - regardless of what unit size is being held in d0. So
4105 the offset of the first uint8 in d0 is 7, but the offset of the
4106 first float is 4. This code works as-is for little-endian
4109 static struct type *
4110 arm_neon_quad_type (struct gdbarch *gdbarch)
4112 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4114 if (tdep->neon_quad_type == NULL)
4116 struct type *t, *elem;
4118 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4120 elem = builtin_type (gdbarch)->builtin_uint8;
4121 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4122 elem = builtin_type (gdbarch)->builtin_uint16;
4123 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4124 elem = builtin_type (gdbarch)->builtin_uint32;
4125 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4126 elem = builtin_type (gdbarch)->builtin_uint64;
4127 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4128 elem = builtin_type (gdbarch)->builtin_float;
4129 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4130 elem = builtin_type (gdbarch)->builtin_double;
4131 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4133 TYPE_VECTOR (t) = 1;
4134 TYPE_NAME (t) = "neon_q";
4135 tdep->neon_quad_type = t;
4138 return tdep->neon_quad_type;
4141 /* Return the GDB type object for the "standard" data type of data in
4144 static struct type *
4145 arm_register_type (struct gdbarch *gdbarch, int regnum)
4147 int num_regs = gdbarch_num_regs (gdbarch);
4149 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4150 && regnum >= num_regs && regnum < num_regs + 32)
4151 return builtin_type (gdbarch)->builtin_float;
4153 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4154 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4155 return arm_neon_quad_type (gdbarch);
4157 /* If the target description has register information, we are only
4158 in this function so that we can override the types of
4159 double-precision registers for NEON. */
4160 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4162 struct type *t = tdesc_register_type (gdbarch, regnum);
4164 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4165 && TYPE_CODE (t) == TYPE_CODE_FLT
4166 && gdbarch_tdep (gdbarch)->have_neon)
4167 return arm_neon_double_type (gdbarch);
4172 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4174 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4175 return builtin_type (gdbarch)->builtin_void;
4177 return arm_ext_type (gdbarch);
4179 else if (regnum == ARM_SP_REGNUM)
4180 return builtin_type (gdbarch)->builtin_data_ptr;
4181 else if (regnum == ARM_PC_REGNUM)
4182 return builtin_type (gdbarch)->builtin_func_ptr;
4183 else if (regnum >= ARRAY_SIZE (arm_register_names))
4184 /* These registers are only supported on targets which supply
4185 an XML description. */
4186 return builtin_type (gdbarch)->builtin_int0;
4188 return builtin_type (gdbarch)->builtin_uint32;
4191 /* Map a DWARF register REGNUM onto the appropriate GDB register
4195 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4197 /* Core integer regs. */
4198 if (reg >= 0 && reg <= 15)
4201 /* Legacy FPA encoding. These were once used in a way which
4202 overlapped with VFP register numbering, so their use is
4203 discouraged, but GDB doesn't support the ARM toolchain
4204 which used them for VFP. */
4205 if (reg >= 16 && reg <= 23)
4206 return ARM_F0_REGNUM + reg - 16;
4208 /* New assignments for the FPA registers. */
4209 if (reg >= 96 && reg <= 103)
4210 return ARM_F0_REGNUM + reg - 96;
4212 /* WMMX register assignments. */
4213 if (reg >= 104 && reg <= 111)
4214 return ARM_WCGR0_REGNUM + reg - 104;
4216 if (reg >= 112 && reg <= 127)
4217 return ARM_WR0_REGNUM + reg - 112;
4219 if (reg >= 192 && reg <= 199)
4220 return ARM_WC0_REGNUM + reg - 192;
4222 /* VFP v2 registers. A double precision value is actually
4223 in d1 rather than s2, but the ABI only defines numbering
4224 for the single precision registers. This will "just work"
4225 in GDB for little endian targets (we'll read eight bytes,
4226 starting in s0 and then progressing to s1), but will be
4227 reversed on big endian targets with VFP. This won't
4228 be a problem for the new Neon quad registers; you're supposed
4229 to use DW_OP_piece for those. */
4230 if (reg >= 64 && reg <= 95)
4234 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4235 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4239 /* VFP v3 / Neon registers. This range is also used for VFP v2
4240 registers, except that it now describes d0 instead of s0. */
4241 if (reg >= 256 && reg <= 287)
4245 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4246 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4253 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4255 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4258 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4260 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4261 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4263 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4264 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4266 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4267 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4269 if (reg < NUM_GREGS)
4270 return SIM_ARM_R0_REGNUM + reg;
4273 if (reg < NUM_FREGS)
4274 return SIM_ARM_FP0_REGNUM + reg;
4277 if (reg < NUM_SREGS)
4278 return SIM_ARM_FPS_REGNUM + reg;
4281 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4284 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4285 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4286 It is thought that this is is the floating-point register format on
4287 little-endian systems. */
4290 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4291 void *dbl, int endianess)
4295 if (endianess == BFD_ENDIAN_BIG)
4296 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4298 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4300 floatformat_from_doublest (fmt, &d, dbl);
4304 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4309 floatformat_to_doublest (fmt, ptr, &d);
4310 if (endianess == BFD_ENDIAN_BIG)
4311 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4313 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4317 static unsigned long
4318 shifted_reg_val (struct regcache *regcache, unsigned long inst, int carry,
4319 unsigned long pc_val, unsigned long status_reg)
4321 unsigned long res, shift;
4322 int rm = bits (inst, 0, 3);
4323 unsigned long shifttype = bits (inst, 5, 6);
4327 int rs = bits (inst, 8, 11);
4328 shift = (rs == 15 ? pc_val + 8
4329 : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
4332 shift = bits (inst, 7, 11);
4334 res = (rm == ARM_PC_REGNUM
4335 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4336 : regcache_raw_get_unsigned (regcache, rm));
4341 res = shift >= 32 ? 0 : res << shift;
4345 res = shift >= 32 ? 0 : res >> shift;
4351 res = ((res & 0x80000000L)
4352 ? ~((~res) >> shift) : res >> shift);
4355 case 3: /* ROR/RRX */
4358 res = (res >> 1) | (carry ? 0x80000000L : 0);
4360 res = (res >> shift) | (res << (32 - shift));
4364 return res & 0xffffffff;
4368 thumb_advance_itstate (unsigned int itstate)
4370 /* Preserve IT[7:5], the first three bits of the condition. Shift
4371 the upcoming condition flags left by one bit. */
4372 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4374 /* If we have finished the IT block, clear the state. */
4375 if ((itstate & 0x0f) == 0)
4381 /* Find the next PC after the current instruction executes. In some
4382 cases we can not statically determine the answer (see the IT state
4383 handling in this function); in that case, a breakpoint may be
4384 inserted in addition to the returned PC, which will be used to set
4385 another breakpoint by our caller. */
4388 thumb_get_next_pc_raw (struct regcache *regcache, CORE_ADDR pc)
4390 struct gdbarch *gdbarch = get_regcache_arch (regcache);
4391 struct address_space *aspace = get_regcache_aspace (regcache);
4392 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4393 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4394 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4395 unsigned short inst1;
4396 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4397 unsigned long offset;
4398 ULONGEST status, itstate;
4400 nextpc = MAKE_THUMB_ADDR (nextpc);
4401 pc_val = MAKE_THUMB_ADDR (pc_val);
4403 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4405 /* Thumb-2 conditional execution support. There are eight bits in
4406 the CPSR which describe conditional execution state. Once
4407 reconstructed (they're in a funny order), the low five bits
4408 describe the low bit of the condition for each instruction and
4409 how many instructions remain. The high three bits describe the
4410 base condition. One of the low four bits will be set if an IT
4411 block is active. These bits read as zero on earlier
4413 status = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
4414 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4416 /* If-Then handling. On GNU/Linux, where this routine is used, we
4417 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4418 can disable execution of the undefined instruction. So we might
4419 miss the breakpoint if we set it on a skipped conditional
4420 instruction. Because conditional instructions can change the
4421 flags, affecting the execution of further instructions, we may
4422 need to set two breakpoints. */
4424 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4426 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4428 /* An IT instruction. Because this instruction does not
4429 modify the flags, we can accurately predict the next
4430 executed instruction. */
4431 itstate = inst1 & 0x00ff;
4432 pc += thumb_insn_size (inst1);
4434 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4436 inst1 = read_memory_unsigned_integer (pc, 2,
4437 byte_order_for_code);
4438 pc += thumb_insn_size (inst1);
4439 itstate = thumb_advance_itstate (itstate);
4442 return MAKE_THUMB_ADDR (pc);
4444 else if (itstate != 0)
4446 /* We are in a conditional block. Check the condition. */
4447 if (! condition_true (itstate >> 4, status))
4449 /* Advance to the next executed instruction. */
4450 pc += thumb_insn_size (inst1);
4451 itstate = thumb_advance_itstate (itstate);
4453 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4455 inst1 = read_memory_unsigned_integer (pc, 2,
4456 byte_order_for_code);
4457 pc += thumb_insn_size (inst1);
4458 itstate = thumb_advance_itstate (itstate);
4461 return MAKE_THUMB_ADDR (pc);
4463 else if ((itstate & 0x0f) == 0x08)
4465 /* This is the last instruction of the conditional
4466 block, and it is executed. We can handle it normally
4467 because the following instruction is not conditional,
4468 and we must handle it normally because it is
4469 permitted to branch. Fall through. */
4475 /* There are conditional instructions after this one.
4476 If this instruction modifies the flags, then we can
4477 not predict what the next executed instruction will
4478 be. Fortunately, this instruction is architecturally
4479 forbidden to branch; we know it will fall through.
4480 Start by skipping past it. */
4481 pc += thumb_insn_size (inst1);
4482 itstate = thumb_advance_itstate (itstate);
4484 /* Set a breakpoint on the following instruction. */
4485 gdb_assert ((itstate & 0x0f) != 0);
4486 arm_insert_single_step_breakpoint (gdbarch, aspace,
4487 MAKE_THUMB_ADDR (pc));
4488 cond_negated = (itstate >> 4) & 1;
4490 /* Skip all following instructions with the same
4491 condition. If there is a later instruction in the IT
4492 block with the opposite condition, set the other
4493 breakpoint there. If not, then set a breakpoint on
4494 the instruction after the IT block. */
4497 inst1 = read_memory_unsigned_integer (pc, 2,
4498 byte_order_for_code);
4499 pc += thumb_insn_size (inst1);
4500 itstate = thumb_advance_itstate (itstate);
4502 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4504 return MAKE_THUMB_ADDR (pc);
4508 else if (itstate & 0x0f)
4510 /* We are in a conditional block. Check the condition. */
4511 int cond = itstate >> 4;
4513 if (! condition_true (cond, status))
4514 /* Advance to the next instruction. All the 32-bit
4515 instructions share a common prefix. */
4516 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4518 /* Otherwise, handle the instruction normally. */
4521 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4525 /* Fetch the saved PC from the stack. It's stored above
4526 all of the other registers. */
4527 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4528 sp = regcache_raw_get_unsigned (regcache, ARM_SP_REGNUM);
4529 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4531 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4533 unsigned long cond = bits (inst1, 8, 11);
4534 if (cond == 0x0f) /* 0x0f = SWI */
4536 struct gdbarch_tdep *tdep;
4537 tdep = gdbarch_tdep (gdbarch);
4539 if (tdep->syscall_next_pc != NULL)
4540 nextpc = tdep->syscall_next_pc (regcache);
4543 else if (cond != 0x0f && condition_true (cond, status))
4544 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4546 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4548 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4550 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4552 unsigned short inst2;
4553 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4555 /* Default to the next instruction. */
4557 nextpc = MAKE_THUMB_ADDR (nextpc);
4559 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4561 /* Branches and miscellaneous control instructions. */
4563 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4566 int j1, j2, imm1, imm2;
4568 imm1 = sbits (inst1, 0, 10);
4569 imm2 = bits (inst2, 0, 10);
4570 j1 = bit (inst2, 13);
4571 j2 = bit (inst2, 11);
4573 offset = ((imm1 << 12) + (imm2 << 1));
4574 offset ^= ((!j2) << 22) | ((!j1) << 23);
4576 nextpc = pc_val + offset;
4577 /* For BLX make sure to clear the low bits. */
4578 if (bit (inst2, 12) == 0)
4579 nextpc = nextpc & 0xfffffffc;
4581 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4583 /* SUBS PC, LR, #imm8. */
4584 nextpc = regcache_raw_get_unsigned (regcache, ARM_LR_REGNUM);
4585 nextpc -= inst2 & 0x00ff;
4587 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4589 /* Conditional branch. */
4590 if (condition_true (bits (inst1, 6, 9), status))
4592 int sign, j1, j2, imm1, imm2;
4594 sign = sbits (inst1, 10, 10);
4595 imm1 = bits (inst1, 0, 5);
4596 imm2 = bits (inst2, 0, 10);
4597 j1 = bit (inst2, 13);
4598 j2 = bit (inst2, 11);
4600 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4601 offset += (imm1 << 12) + (imm2 << 1);
4603 nextpc = pc_val + offset;
4607 else if ((inst1 & 0xfe50) == 0xe810)
4609 /* Load multiple or RFE. */
4610 int rn, offset, load_pc = 1;
4612 rn = bits (inst1, 0, 3);
4613 if (bit (inst1, 7) && !bit (inst1, 8))
4616 if (!bit (inst2, 15))
4618 offset = bitcount (inst2) * 4 - 4;
4620 else if (!bit (inst1, 7) && bit (inst1, 8))
4623 if (!bit (inst2, 15))
4627 else if (bit (inst1, 7) && bit (inst1, 8))
4632 else if (!bit (inst1, 7) && !bit (inst1, 8))
4642 CORE_ADDR addr = regcache_raw_get_unsigned (regcache, rn);
4643 nextpc = read_memory_unsigned_integer (addr + offset, 4,
4647 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4649 /* MOV PC or MOVS PC. */
4650 nextpc = regcache_raw_get_unsigned (regcache, bits (inst2, 0, 3));
4651 nextpc = MAKE_THUMB_ADDR (nextpc);
4653 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4657 int rn, load_pc = 1;
4659 rn = bits (inst1, 0, 3);
4660 base = regcache_raw_get_unsigned (regcache, rn);
4661 if (rn == ARM_PC_REGNUM)
4663 base = (base + 4) & ~(CORE_ADDR) 0x3;
4665 base += bits (inst2, 0, 11);
4667 base -= bits (inst2, 0, 11);
4669 else if (bit (inst1, 7))
4670 base += bits (inst2, 0, 11);
4671 else if (bit (inst2, 11))
4673 if (bit (inst2, 10))
4676 base += bits (inst2, 0, 7);
4678 base -= bits (inst2, 0, 7);
4681 else if ((inst2 & 0x0fc0) == 0x0000)
4683 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4684 base += regcache_raw_get_unsigned (regcache, rm) << shift;
4691 nextpc = read_memory_unsigned_integer (base, 4, byte_order);
4693 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4696 CORE_ADDR tbl_reg, table, offset, length;
4698 tbl_reg = bits (inst1, 0, 3);
4699 if (tbl_reg == 0x0f)
4700 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4702 table = regcache_raw_get_unsigned (regcache, tbl_reg);
4704 offset = regcache_raw_get_unsigned (regcache, bits (inst2, 0, 3));
4705 length = 2 * read_memory_unsigned_integer (table + offset, 1,
4707 nextpc = pc_val + length;
4709 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4712 CORE_ADDR tbl_reg, table, offset, length;
4714 tbl_reg = bits (inst1, 0, 3);
4715 if (tbl_reg == 0x0f)
4716 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4718 table = regcache_raw_get_unsigned (regcache, tbl_reg);
4720 offset = 2 * regcache_raw_get_unsigned (regcache, bits (inst2, 0, 3));
4721 length = 2 * read_memory_unsigned_integer (table + offset, 2,
4723 nextpc = pc_val + length;
4726 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4728 if (bits (inst1, 3, 6) == 0x0f)
4729 nextpc = UNMAKE_THUMB_ADDR (pc_val);
4731 nextpc = regcache_raw_get_unsigned (regcache, bits (inst1, 3, 6));
4733 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4735 if (bits (inst1, 3, 6) == 0x0f)
4738 nextpc = regcache_raw_get_unsigned (regcache, bits (inst1, 3, 6));
4740 nextpc = MAKE_THUMB_ADDR (nextpc);
4742 else if ((inst1 & 0xf500) == 0xb100)
4745 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4746 ULONGEST reg = regcache_raw_get_unsigned (regcache, bits (inst1, 0, 2));
4748 if (bit (inst1, 11) && reg != 0)
4749 nextpc = pc_val + imm;
4750 else if (!bit (inst1, 11) && reg == 0)
4751 nextpc = pc_val + imm;
4756 /* Get the raw next address. PC is the current program counter, in
4757 FRAME, which is assumed to be executing in ARM mode.
4759 The value returned has the execution state of the next instruction
4760 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4761 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4765 arm_get_next_pc_raw (struct regcache *regcache, CORE_ADDR pc)
4767 struct gdbarch *gdbarch = get_regcache_arch (regcache);
4768 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4769 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4770 unsigned long pc_val;
4771 unsigned long this_instr;
4772 unsigned long status;
4775 pc_val = (unsigned long) pc;
4776 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4778 status = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
4779 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4781 if (bits (this_instr, 28, 31) == INST_NV)
4782 switch (bits (this_instr, 24, 27))
4787 /* Branch with Link and change to Thumb. */
4788 nextpc = BranchDest (pc, this_instr);
4789 nextpc |= bit (this_instr, 24) << 1;
4790 nextpc = MAKE_THUMB_ADDR (nextpc);
4796 /* Coprocessor register transfer. */
4797 if (bits (this_instr, 12, 15) == 15)
4798 error (_("Invalid update to pc in instruction"));
4801 else if (condition_true (bits (this_instr, 28, 31), status))
4803 switch (bits (this_instr, 24, 27))
4806 case 0x1: /* data processing */
4810 unsigned long operand1, operand2, result = 0;
4814 if (bits (this_instr, 12, 15) != 15)
4817 if (bits (this_instr, 22, 25) == 0
4818 && bits (this_instr, 4, 7) == 9) /* multiply */
4819 error (_("Invalid update to pc in instruction"));
4821 /* BX <reg>, BLX <reg> */
4822 if (bits (this_instr, 4, 27) == 0x12fff1
4823 || bits (this_instr, 4, 27) == 0x12fff3)
4825 rn = bits (this_instr, 0, 3);
4826 nextpc = ((rn == ARM_PC_REGNUM)
4828 : regcache_raw_get_unsigned (regcache, rn));
4833 /* Multiply into PC. */
4834 c = (status & FLAG_C) ? 1 : 0;
4835 rn = bits (this_instr, 16, 19);
4836 operand1 = ((rn == ARM_PC_REGNUM)
4838 : regcache_raw_get_unsigned (regcache, rn));
4840 if (bit (this_instr, 25))
4842 unsigned long immval = bits (this_instr, 0, 7);
4843 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4844 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4847 else /* operand 2 is a shifted register. */
4848 operand2 = shifted_reg_val (regcache, this_instr, c,
4851 switch (bits (this_instr, 21, 24))
4854 result = operand1 & operand2;
4858 result = operand1 ^ operand2;
4862 result = operand1 - operand2;
4866 result = operand2 - operand1;
4870 result = operand1 + operand2;
4874 result = operand1 + operand2 + c;
4878 result = operand1 - operand2 + c;
4882 result = operand2 - operand1 + c;
4888 case 0xb: /* tst, teq, cmp, cmn */
4889 result = (unsigned long) nextpc;
4893 result = operand1 | operand2;
4897 /* Always step into a function. */
4902 result = operand1 & ~operand2;
4910 /* In 26-bit APCS the bottom two bits of the result are
4911 ignored, and we always end up in ARM state. */
4913 nextpc = arm_addr_bits_remove (gdbarch, result);
4921 case 0x5: /* data transfer */
4924 if (bits (this_instr, 25, 27) == 0x3 && bit (this_instr, 4) == 1)
4926 /* Media instructions and architecturally undefined
4931 if (bit (this_instr, 20))
4934 if (bits (this_instr, 12, 15) == 15)
4940 if (bit (this_instr, 22))
4941 error (_("Invalid update to pc in instruction"));
4943 /* byte write to PC */
4944 rn = bits (this_instr, 16, 19);
4945 base = ((rn == ARM_PC_REGNUM)
4947 : regcache_raw_get_unsigned (regcache, rn));
4949 if (bit (this_instr, 24))
4952 int c = (status & FLAG_C) ? 1 : 0;
4953 unsigned long offset =
4954 (bit (this_instr, 25)
4955 ? shifted_reg_val (regcache, this_instr, c, pc_val,
4957 : bits (this_instr, 0, 11));
4959 if (bit (this_instr, 23))
4965 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4972 case 0x9: /* block transfer */
4973 if (bit (this_instr, 20))
4976 if (bit (this_instr, 15))
4980 unsigned long rn_val
4981 = regcache_raw_get_unsigned (regcache,
4982 bits (this_instr, 16, 19));
4984 if (bit (this_instr, 23))
4987 unsigned long reglist = bits (this_instr, 0, 14);
4988 offset = bitcount (reglist) * 4;
4989 if (bit (this_instr, 24)) /* pre */
4992 else if (bit (this_instr, 24))
4996 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
5003 case 0xb: /* branch & link */
5004 case 0xa: /* branch */
5006 nextpc = BranchDest (pc, this_instr);
5012 case 0xe: /* coproc ops */
5016 struct gdbarch_tdep *tdep;
5017 tdep = gdbarch_tdep (gdbarch);
5019 if (tdep->syscall_next_pc != NULL)
5020 nextpc = tdep->syscall_next_pc (regcache);
5026 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
5034 /* Determine next PC after current instruction executes. Will call either
5035 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5036 loop is detected. */
5039 arm_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
5043 if (arm_is_thumb (regcache))
5044 nextpc = thumb_get_next_pc_raw (regcache, pc);
5046 nextpc = arm_get_next_pc_raw (regcache, pc);
5051 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5052 of the appropriate mode (as encoded in the PC value), even if this
5053 differs from what would be expected according to the symbol tables. */
5056 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
5057 struct address_space *aspace,
5060 struct cleanup *old_chain
5061 = make_cleanup_restore_integer (&arm_override_mode);
5063 arm_override_mode = IS_THUMB_ADDR (pc);
5064 pc = gdbarch_addr_bits_remove (gdbarch, pc);
5066 insert_single_step_breakpoint (gdbarch, aspace, pc);
5068 do_cleanups (old_chain);
5071 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5072 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5073 is found, attempt to step through it. A breakpoint is placed at the end of
5077 thumb_deal_with_atomic_sequence_raw (struct regcache *regcache)
5079 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5080 struct address_space *aspace = get_regcache_aspace (regcache);
5081 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5082 CORE_ADDR pc = regcache_read_pc (regcache);
5083 CORE_ADDR breaks[2] = {-1, -1};
5085 unsigned short insn1, insn2;
5088 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5089 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5090 ULONGEST status, itstate;
5092 /* We currently do not support atomic sequences within an IT block. */
5093 status = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
5094 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5098 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5099 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5101 if (thumb_insn_size (insn1) != 4)
5104 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5106 if (!((insn1 & 0xfff0) == 0xe850
5107 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5110 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5112 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5114 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5117 if (thumb_insn_size (insn1) != 4)
5119 /* Assume that there is at most one conditional branch in the
5120 atomic sequence. If a conditional branch is found, put a
5121 breakpoint in its destination address. */
5122 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
5124 if (last_breakpoint > 0)
5125 return 0; /* More than one conditional branch found,
5126 fallback to the standard code. */
5128 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
5132 /* We do not support atomic sequences that use any *other*
5133 instructions but conditional branches to change the PC.
5134 Fall back to standard code to avoid losing control of
5136 else if (thumb_instruction_changes_pc (insn1))
5141 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5144 /* Assume that there is at most one conditional branch in the
5145 atomic sequence. If a conditional branch is found, put a
5146 breakpoint in its destination address. */
5147 if ((insn1 & 0xf800) == 0xf000
5148 && (insn2 & 0xd000) == 0x8000
5149 && (insn1 & 0x0380) != 0x0380)
5151 int sign, j1, j2, imm1, imm2;
5152 unsigned int offset;
5154 sign = sbits (insn1, 10, 10);
5155 imm1 = bits (insn1, 0, 5);
5156 imm2 = bits (insn2, 0, 10);
5157 j1 = bit (insn2, 13);
5158 j2 = bit (insn2, 11);
5160 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5161 offset += (imm1 << 12) + (imm2 << 1);
5163 if (last_breakpoint > 0)
5164 return 0; /* More than one conditional branch found,
5165 fallback to the standard code. */
5167 breaks[1] = loc + offset;
5171 /* We do not support atomic sequences that use any *other*
5172 instructions but conditional branches to change the PC.
5173 Fall back to standard code to avoid losing control of
5175 else if (thumb2_instruction_changes_pc (insn1, insn2))
5178 /* If we find a strex{,b,h,d}, we're done. */
5179 if ((insn1 & 0xfff0) == 0xe840
5180 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5185 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5186 if (insn_count == atomic_sequence_length)
5189 /* Insert a breakpoint right after the end of the atomic sequence. */
5192 /* Check for duplicated breakpoints. Check also for a breakpoint
5193 placed (branch instruction's destination) anywhere in sequence. */
5195 && (breaks[1] == breaks[0]
5196 || (breaks[1] >= pc && breaks[1] < loc)))
5197 last_breakpoint = 0;
5199 /* Effectively inserts the breakpoints. */
5200 for (index = 0; index <= last_breakpoint; index++)
5201 arm_insert_single_step_breakpoint (gdbarch, aspace,
5202 MAKE_THUMB_ADDR (breaks[index]));
5208 arm_deal_with_atomic_sequence_raw (struct regcache *regcache)
5210 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5211 struct address_space *aspace = get_regcache_aspace (regcache);
5212 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5213 CORE_ADDR pc = regcache_read_pc (regcache);
5214 CORE_ADDR breaks[2] = {-1, -1};
5219 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5220 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5222 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5223 Note that we do not currently support conditionally executed atomic
5225 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5227 if ((insn & 0xff9000f0) != 0xe1900090)
5230 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5232 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5234 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5237 /* Assume that there is at most one conditional branch in the atomic
5238 sequence. If a conditional branch is found, put a breakpoint in
5239 its destination address. */
5240 if (bits (insn, 24, 27) == 0xa)
5242 if (last_breakpoint > 0)
5243 return 0; /* More than one conditional branch found, fallback
5244 to the standard single-step code. */
5246 breaks[1] = BranchDest (loc - 4, insn);
5250 /* We do not support atomic sequences that use any *other* instructions
5251 but conditional branches to change the PC. Fall back to standard
5252 code to avoid losing control of execution. */
5253 else if (arm_instruction_changes_pc (insn))
5256 /* If we find a strex{,b,h,d}, we're done. */
5257 if ((insn & 0xff9000f0) == 0xe1800090)
5261 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5262 if (insn_count == atomic_sequence_length)
5265 /* Insert a breakpoint right after the end of the atomic sequence. */
5268 /* Check for duplicated breakpoints. Check also for a breakpoint
5269 placed (branch instruction's destination) anywhere in sequence. */
5271 && (breaks[1] == breaks[0]
5272 || (breaks[1] >= pc && breaks[1] < loc)))
5273 last_breakpoint = 0;
5275 /* Effectively inserts the breakpoints. */
5276 for (index = 0; index <= last_breakpoint; index++)
5277 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5283 arm_deal_with_atomic_sequence (struct regcache *regcache)
5285 if (arm_is_thumb (regcache))
5286 return thumb_deal_with_atomic_sequence_raw (regcache);
5288 return arm_deal_with_atomic_sequence_raw (regcache);
5291 /* single_step() is called just before we want to resume the inferior,
5292 if we want to single-step it but there is no hardware or kernel
5293 single-step support. We find the target of the coming instruction
5294 and breakpoint it. */
5297 arm_software_single_step (struct frame_info *frame)
5299 struct regcache *regcache = get_current_regcache ();
5300 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5301 struct address_space *aspace = get_regcache_aspace (regcache);
5304 if (arm_deal_with_atomic_sequence (regcache))
5307 next_pc = arm_get_next_pc (regcache, regcache_read_pc (regcache));
5308 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5313 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5314 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5315 NULL if an error occurs. BUF is freed. */
5318 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5319 int old_len, int new_len)
5322 int bytes_to_read = new_len - old_len;
5324 new_buf = (gdb_byte *) xmalloc (new_len);
5325 memcpy (new_buf + bytes_to_read, buf, old_len);
5327 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5335 /* An IT block is at most the 2-byte IT instruction followed by
5336 four 4-byte instructions. The furthest back we must search to
5337 find an IT block that affects the current instruction is thus
5338 2 + 3 * 4 == 14 bytes. */
5339 #define MAX_IT_BLOCK_PREFIX 14
5341 /* Use a quick scan if there are more than this many bytes of
5343 #define IT_SCAN_THRESHOLD 32
5345 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5346 A breakpoint in an IT block may not be hit, depending on the
5349 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5353 CORE_ADDR boundary, func_start;
5355 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5356 int i, any, last_it, last_it_count;
5358 /* If we are using BKPT breakpoints, none of this is necessary. */
5359 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5362 /* ARM mode does not have this problem. */
5363 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5366 /* We are setting a breakpoint in Thumb code that could potentially
5367 contain an IT block. The first step is to find how much Thumb
5368 code there is; we do not need to read outside of known Thumb
5370 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5372 /* Thumb-2 code must have mapping symbols to have a chance. */
5375 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5377 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5378 && func_start > boundary)
5379 boundary = func_start;
5381 /* Search for a candidate IT instruction. We have to do some fancy
5382 footwork to distinguish a real IT instruction from the second
5383 half of a 32-bit instruction, but there is no need for that if
5384 there's no candidate. */
5385 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5387 /* No room for an IT instruction. */
5390 buf = (gdb_byte *) xmalloc (buf_len);
5391 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5394 for (i = 0; i < buf_len; i += 2)
5396 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5397 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5409 /* OK, the code bytes before this instruction contain at least one
5410 halfword which resembles an IT instruction. We know that it's
5411 Thumb code, but there are still two possibilities. Either the
5412 halfword really is an IT instruction, or it is the second half of
5413 a 32-bit Thumb instruction. The only way we can tell is to
5414 scan forwards from a known instruction boundary. */
5415 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5419 /* There's a lot of code before this instruction. Start with an
5420 optimistic search; it's easy to recognize halfwords that can
5421 not be the start of a 32-bit instruction, and use that to
5422 lock on to the instruction boundaries. */
5423 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5426 buf_len = IT_SCAN_THRESHOLD;
5429 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5431 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5432 if (thumb_insn_size (inst1) == 2)
5439 /* At this point, if DEFINITE, BUF[I] is the first place we
5440 are sure that we know the instruction boundaries, and it is far
5441 enough from BPADDR that we could not miss an IT instruction
5442 affecting BPADDR. If ! DEFINITE, give up - start from a
5446 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5450 buf_len = bpaddr - boundary;
5456 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5459 buf_len = bpaddr - boundary;
5463 /* Scan forwards. Find the last IT instruction before BPADDR. */
5468 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5470 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5475 else if (inst1 & 0x0002)
5477 else if (inst1 & 0x0004)
5482 i += thumb_insn_size (inst1);
5488 /* There wasn't really an IT instruction after all. */
5491 if (last_it_count < 1)
5492 /* It was too far away. */
5495 /* This really is a trouble spot. Move the breakpoint to the IT
5497 return bpaddr - buf_len + last_it;
5500 /* ARM displaced stepping support.
5502 Generally ARM displaced stepping works as follows:
5504 1. When an instruction is to be single-stepped, it is first decoded by
5505 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5506 Depending on the type of instruction, it is then copied to a scratch
5507 location, possibly in a modified form. The copy_* set of functions
5508 performs such modification, as necessary. A breakpoint is placed after
5509 the modified instruction in the scratch space to return control to GDB.
5510 Note in particular that instructions which modify the PC will no longer
5511 do so after modification.
5513 2. The instruction is single-stepped, by setting the PC to the scratch
5514 location address, and resuming. Control returns to GDB when the
5517 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5518 function used for the current instruction. This function's job is to
5519 put the CPU/memory state back to what it would have been if the
5520 instruction had been executed unmodified in its original location. */
5522 /* NOP instruction (mov r0, r0). */
5523 #define ARM_NOP 0xe1a00000
5524 #define THUMB_NOP 0x4600
5526 /* Helper for register reads for displaced stepping. In particular, this
5527 returns the PC as it would be seen by the instruction at its original
5531 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5535 CORE_ADDR from = dsc->insn_addr;
5537 if (regno == ARM_PC_REGNUM)
5539 /* Compute pipeline offset:
5540 - When executing an ARM instruction, PC reads as the address of the
5541 current instruction plus 8.
5542 - When executing a Thumb instruction, PC reads as the address of the
5543 current instruction plus 4. */
5550 if (debug_displaced)
5551 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5552 (unsigned long) from);
5553 return (ULONGEST) from;
5557 regcache_cooked_read_unsigned (regs, regno, &ret);
5558 if (debug_displaced)
5559 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5560 regno, (unsigned long) ret);
5566 displaced_in_arm_mode (struct regcache *regs)
5569 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5571 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5573 return (ps & t_bit) == 0;
5576 /* Write to the PC as from a branch instruction. */
5579 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5583 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5584 architecture versions < 6. */
5585 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5586 val & ~(ULONGEST) 0x3);
5588 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5589 val & ~(ULONGEST) 0x1);
5592 /* Write to the PC as from a branch-exchange instruction. */
5595 bx_write_pc (struct regcache *regs, ULONGEST val)
5598 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5600 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5604 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5605 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5607 else if ((val & 2) == 0)
5609 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5610 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5614 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5615 mode, align dest to 4 bytes). */
5616 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5617 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5618 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5622 /* Write to the PC as if from a load instruction. */
5625 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5628 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5629 bx_write_pc (regs, val);
5631 branch_write_pc (regs, dsc, val);
5634 /* Write to the PC as if from an ALU instruction. */
5637 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5640 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5641 bx_write_pc (regs, val);
5643 branch_write_pc (regs, dsc, val);
5646 /* Helper for writing to registers for displaced stepping. Writing to the PC
5647 has a varying effects depending on the instruction which does the write:
5648 this is controlled by the WRITE_PC argument. */
5651 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5652 int regno, ULONGEST val, enum pc_write_style write_pc)
5654 if (regno == ARM_PC_REGNUM)
5656 if (debug_displaced)
5657 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5658 (unsigned long) val);
5661 case BRANCH_WRITE_PC:
5662 branch_write_pc (regs, dsc, val);
5666 bx_write_pc (regs, val);
5670 load_write_pc (regs, dsc, val);
5674 alu_write_pc (regs, dsc, val);
5677 case CANNOT_WRITE_PC:
5678 warning (_("Instruction wrote to PC in an unexpected way when "
5679 "single-stepping"));
5683 internal_error (__FILE__, __LINE__,
5684 _("Invalid argument to displaced_write_reg"));
5687 dsc->wrote_to_pc = 1;
5691 if (debug_displaced)
5692 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5693 regno, (unsigned long) val);
5694 regcache_cooked_write_unsigned (regs, regno, val);
5698 /* This function is used to concisely determine if an instruction INSN
5699 references PC. Register fields of interest in INSN should have the
5700 corresponding fields of BITMASK set to 0b1111. The function
5701 returns return 1 if any of these fields in INSN reference the PC
5702 (also 0b1111, r15), else it returns 0. */
5705 insn_references_pc (uint32_t insn, uint32_t bitmask)
5707 uint32_t lowbit = 1;
5709 while (bitmask != 0)
5713 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5719 mask = lowbit * 0xf;
5721 if ((insn & mask) == mask)
5730 /* The simplest copy function. Many instructions have the same effect no
5731 matter what address they are executed at: in those cases, use this. */
5734 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5735 const char *iname, struct displaced_step_closure *dsc)
5737 if (debug_displaced)
5738 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5739 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5742 dsc->modinsn[0] = insn;
5748 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5749 uint16_t insn2, const char *iname,
5750 struct displaced_step_closure *dsc)
5752 if (debug_displaced)
5753 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5754 "opcode/class '%s' unmodified\n", insn1, insn2,
5757 dsc->modinsn[0] = insn1;
5758 dsc->modinsn[1] = insn2;
5764 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5767 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5769 struct displaced_step_closure *dsc)
5771 if (debug_displaced)
5772 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5773 "opcode/class '%s' unmodified\n", insn,
5776 dsc->modinsn[0] = insn;
5781 /* Preload instructions with immediate offset. */
5784 cleanup_preload (struct gdbarch *gdbarch,
5785 struct regcache *regs, struct displaced_step_closure *dsc)
5787 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5788 if (!dsc->u.preload.immed)
5789 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5793 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5794 struct displaced_step_closure *dsc, unsigned int rn)
5797 /* Preload instructions:
5799 {pli/pld} [rn, #+/-imm]
5801 {pli/pld} [r0, #+/-imm]. */
5803 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5804 rn_val = displaced_read_reg (regs, dsc, rn);
5805 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5806 dsc->u.preload.immed = 1;
5808 dsc->cleanup = &cleanup_preload;
5812 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5813 struct displaced_step_closure *dsc)
5815 unsigned int rn = bits (insn, 16, 19);
5817 if (!insn_references_pc (insn, 0x000f0000ul))
5818 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5820 if (debug_displaced)
5821 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5822 (unsigned long) insn);
5824 dsc->modinsn[0] = insn & 0xfff0ffff;
5826 install_preload (gdbarch, regs, dsc, rn);
5832 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5833 struct regcache *regs, struct displaced_step_closure *dsc)
5835 unsigned int rn = bits (insn1, 0, 3);
5836 unsigned int u_bit = bit (insn1, 7);
5837 int imm12 = bits (insn2, 0, 11);
5840 if (rn != ARM_PC_REGNUM)
5841 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5843 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5844 PLD (literal) Encoding T1. */
5845 if (debug_displaced)
5846 fprintf_unfiltered (gdb_stdlog,
5847 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5848 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5854 /* Rewrite instruction {pli/pld} PC imm12 into:
5855 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5859 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5861 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5862 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5864 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5866 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5867 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5868 dsc->u.preload.immed = 0;
5870 /* {pli/pld} [r0, r1] */
5871 dsc->modinsn[0] = insn1 & 0xfff0;
5872 dsc->modinsn[1] = 0xf001;
5875 dsc->cleanup = &cleanup_preload;
5879 /* Preload instructions with register offset. */
5882 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5883 struct displaced_step_closure *dsc, unsigned int rn,
5886 ULONGEST rn_val, rm_val;
5888 /* Preload register-offset instructions:
5890 {pli/pld} [rn, rm {, shift}]
5892 {pli/pld} [r0, r1 {, shift}]. */
5894 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5895 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5896 rn_val = displaced_read_reg (regs, dsc, rn);
5897 rm_val = displaced_read_reg (regs, dsc, rm);
5898 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5899 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5900 dsc->u.preload.immed = 0;
5902 dsc->cleanup = &cleanup_preload;
5906 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5907 struct regcache *regs,
5908 struct displaced_step_closure *dsc)
5910 unsigned int rn = bits (insn, 16, 19);
5911 unsigned int rm = bits (insn, 0, 3);
5914 if (!insn_references_pc (insn, 0x000f000ful))
5915 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5917 if (debug_displaced)
5918 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5919 (unsigned long) insn);
5921 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5923 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5927 /* Copy/cleanup coprocessor load and store instructions. */
5930 cleanup_copro_load_store (struct gdbarch *gdbarch,
5931 struct regcache *regs,
5932 struct displaced_step_closure *dsc)
5934 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5936 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5938 if (dsc->u.ldst.writeback)
5939 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5943 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5944 struct displaced_step_closure *dsc,
5945 int writeback, unsigned int rn)
5949 /* Coprocessor load/store instructions:
5951 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5953 {stc/stc2} [r0, #+/-imm].
5955 ldc/ldc2 are handled identically. */
5957 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5958 rn_val = displaced_read_reg (regs, dsc, rn);
5959 /* PC should be 4-byte aligned. */
5960 rn_val = rn_val & 0xfffffffc;
5961 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5963 dsc->u.ldst.writeback = writeback;
5964 dsc->u.ldst.rn = rn;
5966 dsc->cleanup = &cleanup_copro_load_store;
5970 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5971 struct regcache *regs,
5972 struct displaced_step_closure *dsc)
5974 unsigned int rn = bits (insn, 16, 19);
5976 if (!insn_references_pc (insn, 0x000f0000ul))
5977 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5979 if (debug_displaced)
5980 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5981 "load/store insn %.8lx\n", (unsigned long) insn);
5983 dsc->modinsn[0] = insn & 0xfff0ffff;
5985 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5991 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5992 uint16_t insn2, struct regcache *regs,
5993 struct displaced_step_closure *dsc)
5995 unsigned int rn = bits (insn1, 0, 3);
5997 if (rn != ARM_PC_REGNUM)
5998 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5999 "copro load/store", dsc);
6001 if (debug_displaced)
6002 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
6003 "load/store insn %.4x%.4x\n", insn1, insn2);
6005 dsc->modinsn[0] = insn1 & 0xfff0;
6006 dsc->modinsn[1] = insn2;
6009 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6010 doesn't support writeback, so pass 0. */
6011 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
6016 /* Clean up branch instructions (actually perform the branch, by setting
6020 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
6021 struct displaced_step_closure *dsc)
6023 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6024 int branch_taken = condition_true (dsc->u.branch.cond, status);
6025 enum pc_write_style write_pc = dsc->u.branch.exchange
6026 ? BX_WRITE_PC : BRANCH_WRITE_PC;
6031 if (dsc->u.branch.link)
6033 /* The value of LR should be the next insn of current one. In order
6034 not to confuse logic hanlding later insn `bx lr', if current insn mode
6035 is Thumb, the bit 0 of LR value should be set to 1. */
6036 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
6039 next_insn_addr |= 0x1;
6041 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
6045 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
6048 /* Copy B/BL/BLX instructions with immediate destinations. */
6051 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
6052 struct displaced_step_closure *dsc,
6053 unsigned int cond, int exchange, int link, long offset)
6055 /* Implement "BL<cond> <label>" as:
6057 Preparation: cond <- instruction condition
6058 Insn: mov r0, r0 (nop)
6059 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6061 B<cond> similar, but don't set r14 in cleanup. */
6063 dsc->u.branch.cond = cond;
6064 dsc->u.branch.link = link;
6065 dsc->u.branch.exchange = exchange;
6067 dsc->u.branch.dest = dsc->insn_addr;
6068 if (link && exchange)
6069 /* For BLX, offset is computed from the Align (PC, 4). */
6070 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6073 dsc->u.branch.dest += 4 + offset;
6075 dsc->u.branch.dest += 8 + offset;
6077 dsc->cleanup = &cleanup_branch;
6080 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
6081 struct regcache *regs, struct displaced_step_closure *dsc)
6083 unsigned int cond = bits (insn, 28, 31);
6084 int exchange = (cond == 0xf);
6085 int link = exchange || bit (insn, 24);
6088 if (debug_displaced)
6089 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
6090 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
6091 (unsigned long) insn);
6093 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6094 then arrange the switch into Thumb mode. */
6095 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
6097 offset = bits (insn, 0, 23) << 2;
6099 if (bit (offset, 25))
6100 offset = offset | ~0x3ffffff;
6102 dsc->modinsn[0] = ARM_NOP;
6104 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6109 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
6110 uint16_t insn2, struct regcache *regs,
6111 struct displaced_step_closure *dsc)
6113 int link = bit (insn2, 14);
6114 int exchange = link && !bit (insn2, 12);
6117 int j1 = bit (insn2, 13);
6118 int j2 = bit (insn2, 11);
6119 int s = sbits (insn1, 10, 10);
6120 int i1 = !(j1 ^ bit (insn1, 10));
6121 int i2 = !(j2 ^ bit (insn1, 10));
6123 if (!link && !exchange) /* B */
6125 offset = (bits (insn2, 0, 10) << 1);
6126 if (bit (insn2, 12)) /* Encoding T4 */
6128 offset |= (bits (insn1, 0, 9) << 12)
6134 else /* Encoding T3 */
6136 offset |= (bits (insn1, 0, 5) << 12)
6140 cond = bits (insn1, 6, 9);
6145 offset = (bits (insn1, 0, 9) << 12);
6146 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6147 offset |= exchange ?
6148 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
6151 if (debug_displaced)
6152 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
6153 "%.4x %.4x with offset %.8lx\n",
6154 link ? (exchange) ? "blx" : "bl" : "b",
6155 insn1, insn2, offset);
6157 dsc->modinsn[0] = THUMB_NOP;
6159 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6163 /* Copy B Thumb instructions. */
6165 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
6166 struct displaced_step_closure *dsc)
6168 unsigned int cond = 0;
6170 unsigned short bit_12_15 = bits (insn, 12, 15);
6171 CORE_ADDR from = dsc->insn_addr;
6173 if (bit_12_15 == 0xd)
6175 /* offset = SignExtend (imm8:0, 32) */
6176 offset = sbits ((insn << 1), 0, 8);
6177 cond = bits (insn, 8, 11);
6179 else if (bit_12_15 == 0xe) /* Encoding T2 */
6181 offset = sbits ((insn << 1), 0, 11);
6185 if (debug_displaced)
6186 fprintf_unfiltered (gdb_stdlog,
6187 "displaced: copying b immediate insn %.4x "
6188 "with offset %d\n", insn, offset);
6190 dsc->u.branch.cond = cond;
6191 dsc->u.branch.link = 0;
6192 dsc->u.branch.exchange = 0;
6193 dsc->u.branch.dest = from + 4 + offset;
6195 dsc->modinsn[0] = THUMB_NOP;
6197 dsc->cleanup = &cleanup_branch;
6202 /* Copy BX/BLX with register-specified destinations. */
6205 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6206 struct displaced_step_closure *dsc, int link,
6207 unsigned int cond, unsigned int rm)
6209 /* Implement {BX,BLX}<cond> <reg>" as:
6211 Preparation: cond <- instruction condition
6212 Insn: mov r0, r0 (nop)
6213 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6215 Don't set r14 in cleanup for BX. */
6217 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6219 dsc->u.branch.cond = cond;
6220 dsc->u.branch.link = link;
6222 dsc->u.branch.exchange = 1;
6224 dsc->cleanup = &cleanup_branch;
6228 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6229 struct regcache *regs, struct displaced_step_closure *dsc)
6231 unsigned int cond = bits (insn, 28, 31);
6234 int link = bit (insn, 5);
6235 unsigned int rm = bits (insn, 0, 3);
6237 if (debug_displaced)
6238 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6239 (unsigned long) insn);
6241 dsc->modinsn[0] = ARM_NOP;
6243 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6248 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6249 struct regcache *regs,
6250 struct displaced_step_closure *dsc)
6252 int link = bit (insn, 7);
6253 unsigned int rm = bits (insn, 3, 6);
6255 if (debug_displaced)
6256 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6257 (unsigned short) insn);
6259 dsc->modinsn[0] = THUMB_NOP;
6261 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6267 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6270 cleanup_alu_imm (struct gdbarch *gdbarch,
6271 struct regcache *regs, struct displaced_step_closure *dsc)
6273 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6274 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6275 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6276 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6280 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6281 struct displaced_step_closure *dsc)
6283 unsigned int rn = bits (insn, 16, 19);
6284 unsigned int rd = bits (insn, 12, 15);
6285 unsigned int op = bits (insn, 21, 24);
6286 int is_mov = (op == 0xd);
6287 ULONGEST rd_val, rn_val;
6289 if (!insn_references_pc (insn, 0x000ff000ul))
6290 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6292 if (debug_displaced)
6293 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6294 "%.8lx\n", is_mov ? "move" : "ALU",
6295 (unsigned long) insn);
6297 /* Instruction is of form:
6299 <op><cond> rd, [rn,] #imm
6303 Preparation: tmp1, tmp2 <- r0, r1;
6305 Insn: <op><cond> r0, r1, #imm
6306 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6309 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6310 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6311 rn_val = displaced_read_reg (regs, dsc, rn);
6312 rd_val = displaced_read_reg (regs, dsc, rd);
6313 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6314 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6318 dsc->modinsn[0] = insn & 0xfff00fff;
6320 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6322 dsc->cleanup = &cleanup_alu_imm;
6328 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6329 uint16_t insn2, struct regcache *regs,
6330 struct displaced_step_closure *dsc)
6332 unsigned int op = bits (insn1, 5, 8);
6333 unsigned int rn, rm, rd;
6334 ULONGEST rd_val, rn_val;
6336 rn = bits (insn1, 0, 3); /* Rn */
6337 rm = bits (insn2, 0, 3); /* Rm */
6338 rd = bits (insn2, 8, 11); /* Rd */
6340 /* This routine is only called for instruction MOV. */
6341 gdb_assert (op == 0x2 && rn == 0xf);
6343 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6344 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6346 if (debug_displaced)
6347 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6348 "ALU", insn1, insn2);
6350 /* Instruction is of form:
6352 <op><cond> rd, [rn,] #imm
6356 Preparation: tmp1, tmp2 <- r0, r1;
6358 Insn: <op><cond> r0, r1, #imm
6359 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6362 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6363 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6364 rn_val = displaced_read_reg (regs, dsc, rn);
6365 rd_val = displaced_read_reg (regs, dsc, rd);
6366 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6367 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6370 dsc->modinsn[0] = insn1;
6371 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6374 dsc->cleanup = &cleanup_alu_imm;
6379 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6382 cleanup_alu_reg (struct gdbarch *gdbarch,
6383 struct regcache *regs, struct displaced_step_closure *dsc)
6388 rd_val = displaced_read_reg (regs, dsc, 0);
6390 for (i = 0; i < 3; i++)
6391 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6393 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6397 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6398 struct displaced_step_closure *dsc,
6399 unsigned int rd, unsigned int rn, unsigned int rm)
6401 ULONGEST rd_val, rn_val, rm_val;
6403 /* Instruction is of form:
6405 <op><cond> rd, [rn,] rm [, <shift>]
6409 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6410 r0, r1, r2 <- rd, rn, rm
6411 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
6412 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6415 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6416 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6417 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6418 rd_val = displaced_read_reg (regs, dsc, rd);
6419 rn_val = displaced_read_reg (regs, dsc, rn);
6420 rm_val = displaced_read_reg (regs, dsc, rm);
6421 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6422 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6423 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6426 dsc->cleanup = &cleanup_alu_reg;
6430 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6431 struct displaced_step_closure *dsc)
6433 unsigned int op = bits (insn, 21, 24);
6434 int is_mov = (op == 0xd);
6436 if (!insn_references_pc (insn, 0x000ff00ful))
6437 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6439 if (debug_displaced)
6440 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6441 is_mov ? "move" : "ALU", (unsigned long) insn);
6444 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6446 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6448 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6454 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6455 struct regcache *regs,
6456 struct displaced_step_closure *dsc)
6460 rm = bits (insn, 3, 6);
6461 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6463 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
6464 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6466 if (debug_displaced)
6467 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
6468 (unsigned short) insn);
6470 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
6472 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
6477 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6480 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6481 struct regcache *regs,
6482 struct displaced_step_closure *dsc)
6484 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6487 for (i = 0; i < 4; i++)
6488 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6490 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6494 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6495 struct displaced_step_closure *dsc,
6496 unsigned int rd, unsigned int rn, unsigned int rm,
6500 ULONGEST rd_val, rn_val, rm_val, rs_val;
6502 /* Instruction is of form:
6504 <op><cond> rd, [rn,] rm, <shift> rs
6508 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6509 r0, r1, r2, r3 <- rd, rn, rm, rs
6510 Insn: <op><cond> r0, r1, r2, <shift> r3
6512 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6516 for (i = 0; i < 4; i++)
6517 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6519 rd_val = displaced_read_reg (regs, dsc, rd);
6520 rn_val = displaced_read_reg (regs, dsc, rn);
6521 rm_val = displaced_read_reg (regs, dsc, rm);
6522 rs_val = displaced_read_reg (regs, dsc, rs);
6523 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6524 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6525 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6526 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6528 dsc->cleanup = &cleanup_alu_shifted_reg;
6532 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6533 struct regcache *regs,
6534 struct displaced_step_closure *dsc)
6536 unsigned int op = bits (insn, 21, 24);
6537 int is_mov = (op == 0xd);
6538 unsigned int rd, rn, rm, rs;
6540 if (!insn_references_pc (insn, 0x000fff0ful))
6541 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6543 if (debug_displaced)
6544 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6545 "%.8lx\n", is_mov ? "move" : "ALU",
6546 (unsigned long) insn);
6548 rn = bits (insn, 16, 19);
6549 rm = bits (insn, 0, 3);
6550 rs = bits (insn, 8, 11);
6551 rd = bits (insn, 12, 15);
6554 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6556 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6558 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6563 /* Clean up load instructions. */
6566 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6567 struct displaced_step_closure *dsc)
6569 ULONGEST rt_val, rt_val2 = 0, rn_val;
6571 rt_val = displaced_read_reg (regs, dsc, 0);
6572 if (dsc->u.ldst.xfersize == 8)
6573 rt_val2 = displaced_read_reg (regs, dsc, 1);
6574 rn_val = displaced_read_reg (regs, dsc, 2);
6576 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6577 if (dsc->u.ldst.xfersize > 4)
6578 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6579 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6580 if (!dsc->u.ldst.immed)
6581 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6583 /* Handle register writeback. */
6584 if (dsc->u.ldst.writeback)
6585 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6586 /* Put result in right place. */
6587 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6588 if (dsc->u.ldst.xfersize == 8)
6589 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6592 /* Clean up store instructions. */
6595 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6596 struct displaced_step_closure *dsc)
6598 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6600 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6601 if (dsc->u.ldst.xfersize > 4)
6602 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6603 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6604 if (!dsc->u.ldst.immed)
6605 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6606 if (!dsc->u.ldst.restore_r4)
6607 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6610 if (dsc->u.ldst.writeback)
6611 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6614 /* Copy "extra" load/store instructions. These are halfword/doubleword
6615 transfers, which have a different encoding to byte/word transfers. */
6618 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6619 struct regcache *regs, struct displaced_step_closure *dsc)
6621 unsigned int op1 = bits (insn, 20, 24);
6622 unsigned int op2 = bits (insn, 5, 6);
6623 unsigned int rt = bits (insn, 12, 15);
6624 unsigned int rn = bits (insn, 16, 19);
6625 unsigned int rm = bits (insn, 0, 3);
6626 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6627 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6628 int immed = (op1 & 0x4) != 0;
6630 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6632 if (!insn_references_pc (insn, 0x000ff00ful))
6633 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6635 if (debug_displaced)
6636 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6637 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6638 (unsigned long) insn);
6640 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6643 internal_error (__FILE__, __LINE__,
6644 _("copy_extra_ld_st: instruction decode error"));
6646 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6647 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6648 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6650 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6652 rt_val = displaced_read_reg (regs, dsc, rt);
6653 if (bytesize[opcode] == 8)
6654 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6655 rn_val = displaced_read_reg (regs, dsc, rn);
6657 rm_val = displaced_read_reg (regs, dsc, rm);
6659 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6660 if (bytesize[opcode] == 8)
6661 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6662 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6664 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6667 dsc->u.ldst.xfersize = bytesize[opcode];
6668 dsc->u.ldst.rn = rn;
6669 dsc->u.ldst.immed = immed;
6670 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6671 dsc->u.ldst.restore_r4 = 0;
6674 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6676 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6677 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6679 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6681 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6682 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6684 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6689 /* Copy byte/half word/word loads and stores. */
6692 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6693 struct displaced_step_closure *dsc, int load,
6694 int immed, int writeback, int size, int usermode,
6695 int rt, int rm, int rn)
6697 ULONGEST rt_val, rn_val, rm_val = 0;
6699 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6700 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6702 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6704 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6706 rt_val = displaced_read_reg (regs, dsc, rt);
6707 rn_val = displaced_read_reg (regs, dsc, rn);
6709 rm_val = displaced_read_reg (regs, dsc, rm);
6711 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6712 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6714 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6716 dsc->u.ldst.xfersize = size;
6717 dsc->u.ldst.rn = rn;
6718 dsc->u.ldst.immed = immed;
6719 dsc->u.ldst.writeback = writeback;
6721 /* To write PC we can do:
6723 Before this sequence of instructions:
6724 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6725 r2 is the Rn value got from dispalced_read_reg.
6727 Insn1: push {pc} Write address of STR instruction + offset on stack
6728 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6729 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6730 = addr(Insn1) + offset - addr(Insn3) - 8
6732 Insn4: add r4, r4, #8 r4 = offset - 8
6733 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6735 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6737 Otherwise we don't know what value to write for PC, since the offset is
6738 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6739 of this can be found in Section "Saving from r15" in
6740 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6742 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6747 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6748 uint16_t insn2, struct regcache *regs,
6749 struct displaced_step_closure *dsc, int size)
6751 unsigned int u_bit = bit (insn1, 7);
6752 unsigned int rt = bits (insn2, 12, 15);
6753 int imm12 = bits (insn2, 0, 11);
6756 if (debug_displaced)
6757 fprintf_unfiltered (gdb_stdlog,
6758 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6759 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6765 /* Rewrite instruction LDR Rt imm12 into:
6767 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6771 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6774 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6775 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6776 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6778 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6780 pc_val = pc_val & 0xfffffffc;
6782 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6783 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6787 dsc->u.ldst.xfersize = size;
6788 dsc->u.ldst.immed = 0;
6789 dsc->u.ldst.writeback = 0;
6790 dsc->u.ldst.restore_r4 = 0;
6792 /* LDR R0, R2, R3 */
6793 dsc->modinsn[0] = 0xf852;
6794 dsc->modinsn[1] = 0x3;
6797 dsc->cleanup = &cleanup_load;
6803 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6804 uint16_t insn2, struct regcache *regs,
6805 struct displaced_step_closure *dsc,
6806 int writeback, int immed)
6808 unsigned int rt = bits (insn2, 12, 15);
6809 unsigned int rn = bits (insn1, 0, 3);
6810 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6811 /* In LDR (register), there is also a register Rm, which is not allowed to
6812 be PC, so we don't have to check it. */
6814 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6815 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6818 if (debug_displaced)
6819 fprintf_unfiltered (gdb_stdlog,
6820 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6821 rt, rn, insn1, insn2);
6823 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6826 dsc->u.ldst.restore_r4 = 0;
6829 /* ldr[b]<cond> rt, [rn, #imm], etc.
6831 ldr[b]<cond> r0, [r2, #imm]. */
6833 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6834 dsc->modinsn[1] = insn2 & 0x0fff;
6837 /* ldr[b]<cond> rt, [rn, rm], etc.
6839 ldr[b]<cond> r0, [r2, r3]. */
6841 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6842 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6852 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6853 struct regcache *regs,
6854 struct displaced_step_closure *dsc,
6855 int load, int size, int usermode)
6857 int immed = !bit (insn, 25);
6858 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6859 unsigned int rt = bits (insn, 12, 15);
6860 unsigned int rn = bits (insn, 16, 19);
6861 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6863 if (!insn_references_pc (insn, 0x000ff00ful))
6864 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6866 if (debug_displaced)
6867 fprintf_unfiltered (gdb_stdlog,
6868 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6869 load ? (size == 1 ? "ldrb" : "ldr")
6870 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6872 (unsigned long) insn);
6874 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6875 usermode, rt, rm, rn);
6877 if (load || rt != ARM_PC_REGNUM)
6879 dsc->u.ldst.restore_r4 = 0;
6882 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6884 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6885 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6887 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6889 {ldr,str}[b]<cond> r0, [r2, r3]. */
6890 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6894 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6895 dsc->u.ldst.restore_r4 = 1;
6896 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6897 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6898 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6899 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6900 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6904 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6906 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6911 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6916 /* Cleanup LDM instructions with fully-populated register list. This is an
6917 unfortunate corner case: it's impossible to implement correctly by modifying
6918 the instruction. The issue is as follows: we have an instruction,
6922 which we must rewrite to avoid loading PC. A possible solution would be to
6923 do the load in two halves, something like (with suitable cleanup
6927 ldm[id][ab] r8!, {r0-r7}
6929 ldm[id][ab] r8, {r7-r14}
6932 but at present there's no suitable place for <temp>, since the scratch space
6933 is overwritten before the cleanup routine is called. For now, we simply
6934 emulate the instruction. */
6937 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6938 struct displaced_step_closure *dsc)
6940 int inc = dsc->u.block.increment;
6941 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6942 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6943 uint32_t regmask = dsc->u.block.regmask;
6944 int regno = inc ? 0 : 15;
6945 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6946 int exception_return = dsc->u.block.load && dsc->u.block.user
6947 && (regmask & 0x8000) != 0;
6948 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6949 int do_transfer = condition_true (dsc->u.block.cond, status);
6950 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6955 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6956 sensible we can do here. Complain loudly. */
6957 if (exception_return)
6958 error (_("Cannot single-step exception return"));
6960 /* We don't handle any stores here for now. */
6961 gdb_assert (dsc->u.block.load != 0);
6963 if (debug_displaced)
6964 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6965 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6966 dsc->u.block.increment ? "inc" : "dec",
6967 dsc->u.block.before ? "before" : "after");
6974 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6977 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6980 xfer_addr += bump_before;
6982 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6983 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6985 xfer_addr += bump_after;
6987 regmask &= ~(1 << regno);
6990 if (dsc->u.block.writeback)
6991 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6995 /* Clean up an STM which included the PC in the register list. */
6998 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6999 struct displaced_step_closure *dsc)
7001 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
7002 int store_executed = condition_true (dsc->u.block.cond, status);
7003 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
7004 CORE_ADDR stm_insn_addr;
7007 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7009 /* If condition code fails, there's nothing else to do. */
7010 if (!store_executed)
7013 if (dsc->u.block.increment)
7015 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
7017 if (dsc->u.block.before)
7022 pc_stored_at = dsc->u.block.xfer_addr;
7024 if (dsc->u.block.before)
7028 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
7029 stm_insn_addr = dsc->scratch_base;
7030 offset = pc_val - stm_insn_addr;
7032 if (debug_displaced)
7033 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
7034 "STM instruction\n", offset);
7036 /* Rewrite the stored PC to the proper value for the non-displaced original
7038 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
7039 dsc->insn_addr + offset);
7042 /* Clean up an LDM which includes the PC in the register list. We clumped all
7043 the registers in the transferred list into a contiguous range r0...rX (to
7044 avoid loading PC directly and losing control of the debugged program), so we
7045 must undo that here. */
7048 cleanup_block_load_pc (struct gdbarch *gdbarch,
7049 struct regcache *regs,
7050 struct displaced_step_closure *dsc)
7052 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
7053 int load_executed = condition_true (dsc->u.block.cond, status);
7054 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
7055 unsigned int regs_loaded = bitcount (mask);
7056 unsigned int num_to_shuffle = regs_loaded, clobbered;
7058 /* The method employed here will fail if the register list is fully populated
7059 (we need to avoid loading PC directly). */
7060 gdb_assert (num_to_shuffle < 16);
7065 clobbered = (1 << num_to_shuffle) - 1;
7067 while (num_to_shuffle > 0)
7069 if ((mask & (1 << write_reg)) != 0)
7071 unsigned int read_reg = num_to_shuffle - 1;
7073 if (read_reg != write_reg)
7075 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
7076 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7077 if (debug_displaced)
7078 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
7079 "loaded register r%d to r%d\n"), read_reg,
7082 else if (debug_displaced)
7083 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
7084 "r%d already in the right place\n"),
7087 clobbered &= ~(1 << write_reg);
7095 /* Restore any registers we scribbled over. */
7096 for (write_reg = 0; clobbered != 0; write_reg++)
7098 if ((clobbered & (1 << write_reg)) != 0)
7100 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7102 if (debug_displaced)
7103 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
7104 "clobbered register r%d\n"), write_reg);
7105 clobbered &= ~(1 << write_reg);
7109 /* Perform register writeback manually. */
7110 if (dsc->u.block.writeback)
7112 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7114 if (dsc->u.block.increment)
7115 new_rn_val += regs_loaded * 4;
7117 new_rn_val -= regs_loaded * 4;
7119 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7124 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7125 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7128 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
7129 struct regcache *regs,
7130 struct displaced_step_closure *dsc)
7132 int load = bit (insn, 20);
7133 int user = bit (insn, 22);
7134 int increment = bit (insn, 23);
7135 int before = bit (insn, 24);
7136 int writeback = bit (insn, 21);
7137 int rn = bits (insn, 16, 19);
7139 /* Block transfers which don't mention PC can be run directly
7141 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
7142 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7144 if (rn == ARM_PC_REGNUM)
7146 warning (_("displaced: Unpredictable LDM or STM with "
7147 "base register r15"));
7148 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7151 if (debug_displaced)
7152 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7153 "%.8lx\n", (unsigned long) insn);
7155 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7156 dsc->u.block.rn = rn;
7158 dsc->u.block.load = load;
7159 dsc->u.block.user = user;
7160 dsc->u.block.increment = increment;
7161 dsc->u.block.before = before;
7162 dsc->u.block.writeback = writeback;
7163 dsc->u.block.cond = bits (insn, 28, 31);
7165 dsc->u.block.regmask = insn & 0xffff;
7169 if ((insn & 0xffff) == 0xffff)
7171 /* LDM with a fully-populated register list. This case is
7172 particularly tricky. Implement for now by fully emulating the
7173 instruction (which might not behave perfectly in all cases, but
7174 these instructions should be rare enough for that not to matter
7176 dsc->modinsn[0] = ARM_NOP;
7178 dsc->cleanup = &cleanup_block_load_all;
7182 /* LDM of a list of registers which includes PC. Implement by
7183 rewriting the list of registers to be transferred into a
7184 contiguous chunk r0...rX before doing the transfer, then shuffling
7185 registers into the correct places in the cleanup routine. */
7186 unsigned int regmask = insn & 0xffff;
7187 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7188 unsigned int to = 0, from = 0, i, new_rn;
7190 for (i = 0; i < num_in_list; i++)
7191 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7193 /* Writeback makes things complicated. We need to avoid clobbering
7194 the base register with one of the registers in our modified
7195 register list, but just using a different register can't work in
7198 ldm r14!, {r0-r13,pc}
7200 which would need to be rewritten as:
7204 but that can't work, because there's no free register for N.
7206 Solve this by turning off the writeback bit, and emulating
7207 writeback manually in the cleanup routine. */
7212 new_regmask = (1 << num_in_list) - 1;
7214 if (debug_displaced)
7215 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7216 "{..., pc}: original reg list %.4x, modified "
7217 "list %.4x\n"), rn, writeback ? "!" : "",
7218 (int) insn & 0xffff, new_regmask);
7220 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7222 dsc->cleanup = &cleanup_block_load_pc;
7227 /* STM of a list of registers which includes PC. Run the instruction
7228 as-is, but out of line: this will store the wrong value for the PC,
7229 so we must manually fix up the memory in the cleanup routine.
7230 Doing things this way has the advantage that we can auto-detect
7231 the offset of the PC write (which is architecture-dependent) in
7232 the cleanup routine. */
7233 dsc->modinsn[0] = insn;
7235 dsc->cleanup = &cleanup_block_store_pc;
7242 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7243 struct regcache *regs,
7244 struct displaced_step_closure *dsc)
7246 int rn = bits (insn1, 0, 3);
7247 int load = bit (insn1, 4);
7248 int writeback = bit (insn1, 5);
7250 /* Block transfers which don't mention PC can be run directly
7252 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7253 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7255 if (rn == ARM_PC_REGNUM)
7257 warning (_("displaced: Unpredictable LDM or STM with "
7258 "base register r15"));
7259 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7260 "unpredictable ldm/stm", dsc);
7263 if (debug_displaced)
7264 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7265 "%.4x%.4x\n", insn1, insn2);
7267 /* Clear bit 13, since it should be always zero. */
7268 dsc->u.block.regmask = (insn2 & 0xdfff);
7269 dsc->u.block.rn = rn;
7271 dsc->u.block.load = load;
7272 dsc->u.block.user = 0;
7273 dsc->u.block.increment = bit (insn1, 7);
7274 dsc->u.block.before = bit (insn1, 8);
7275 dsc->u.block.writeback = writeback;
7276 dsc->u.block.cond = INST_AL;
7277 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7281 if (dsc->u.block.regmask == 0xffff)
7283 /* This branch is impossible to happen. */
7288 unsigned int regmask = dsc->u.block.regmask;
7289 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7290 unsigned int to = 0, from = 0, i, new_rn;
7292 for (i = 0; i < num_in_list; i++)
7293 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7298 new_regmask = (1 << num_in_list) - 1;
7300 if (debug_displaced)
7301 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7302 "{..., pc}: original reg list %.4x, modified "
7303 "list %.4x\n"), rn, writeback ? "!" : "",
7304 (int) dsc->u.block.regmask, new_regmask);
7306 dsc->modinsn[0] = insn1;
7307 dsc->modinsn[1] = (new_regmask & 0xffff);
7310 dsc->cleanup = &cleanup_block_load_pc;
7315 dsc->modinsn[0] = insn1;
7316 dsc->modinsn[1] = insn2;
7318 dsc->cleanup = &cleanup_block_store_pc;
7323 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7324 for Linux, where some SVC instructions must be treated specially. */
7327 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7328 struct displaced_step_closure *dsc)
7330 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7332 if (debug_displaced)
7333 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7334 "%.8lx\n", (unsigned long) resume_addr);
7336 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7340 /* Common copy routine for svc instruciton. */
7343 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7344 struct displaced_step_closure *dsc)
7346 /* Preparation: none.
7347 Insn: unmodified svc.
7348 Cleanup: pc <- insn_addr + insn_size. */
7350 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7352 dsc->wrote_to_pc = 1;
7354 /* Allow OS-specific code to override SVC handling. */
7355 if (dsc->u.svc.copy_svc_os)
7356 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7359 dsc->cleanup = &cleanup_svc;
7365 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7366 struct regcache *regs, struct displaced_step_closure *dsc)
7369 if (debug_displaced)
7370 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7371 (unsigned long) insn);
7373 dsc->modinsn[0] = insn;
7375 return install_svc (gdbarch, regs, dsc);
7379 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7380 struct regcache *regs, struct displaced_step_closure *dsc)
7383 if (debug_displaced)
7384 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7387 dsc->modinsn[0] = insn;
7389 return install_svc (gdbarch, regs, dsc);
7392 /* Copy undefined instructions. */
7395 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7396 struct displaced_step_closure *dsc)
7398 if (debug_displaced)
7399 fprintf_unfiltered (gdb_stdlog,
7400 "displaced: copying undefined insn %.8lx\n",
7401 (unsigned long) insn);
7403 dsc->modinsn[0] = insn;
7409 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7410 struct displaced_step_closure *dsc)
7413 if (debug_displaced)
7414 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7415 "%.4x %.4x\n", (unsigned short) insn1,
7416 (unsigned short) insn2);
7418 dsc->modinsn[0] = insn1;
7419 dsc->modinsn[1] = insn2;
7425 /* Copy unpredictable instructions. */
7428 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7429 struct displaced_step_closure *dsc)
7431 if (debug_displaced)
7432 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7433 "%.8lx\n", (unsigned long) insn);
7435 dsc->modinsn[0] = insn;
7440 /* The decode_* functions are instruction decoding helpers. They mostly follow
7441 the presentation in the ARM ARM. */
7444 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7445 struct regcache *regs,
7446 struct displaced_step_closure *dsc)
7448 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7449 unsigned int rn = bits (insn, 16, 19);
7451 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7452 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7453 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7454 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7455 else if ((op1 & 0x60) == 0x20)
7456 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7457 else if ((op1 & 0x71) == 0x40)
7458 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7460 else if ((op1 & 0x77) == 0x41)
7461 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7462 else if ((op1 & 0x77) == 0x45)
7463 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7464 else if ((op1 & 0x77) == 0x51)
7467 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7469 return arm_copy_unpred (gdbarch, insn, dsc);
7471 else if ((op1 & 0x77) == 0x55)
7472 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7473 else if (op1 == 0x57)
7476 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7477 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7478 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7479 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7480 default: return arm_copy_unpred (gdbarch, insn, dsc);
7482 else if ((op1 & 0x63) == 0x43)
7483 return arm_copy_unpred (gdbarch, insn, dsc);
7484 else if ((op2 & 0x1) == 0x0)
7485 switch (op1 & ~0x80)
7488 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7490 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7491 case 0x71: case 0x75:
7493 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7494 case 0x63: case 0x67: case 0x73: case 0x77:
7495 return arm_copy_unpred (gdbarch, insn, dsc);
7497 return arm_copy_undef (gdbarch, insn, dsc);
7500 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7504 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7505 struct regcache *regs,
7506 struct displaced_step_closure *dsc)
7508 if (bit (insn, 27) == 0)
7509 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7510 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7511 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7514 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7517 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7519 case 0x4: case 0x5: case 0x6: case 0x7:
7520 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7523 switch ((insn & 0xe00000) >> 21)
7525 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7527 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7530 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7533 return arm_copy_undef (gdbarch, insn, dsc);
7538 int rn_f = (bits (insn, 16, 19) == 0xf);
7539 switch ((insn & 0xe00000) >> 21)
7542 /* ldc/ldc2 imm (undefined for rn == pc). */
7543 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7544 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7547 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7549 case 0x4: case 0x5: case 0x6: case 0x7:
7550 /* ldc/ldc2 lit (undefined for rn != pc). */
7551 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7552 : arm_copy_undef (gdbarch, insn, dsc);
7555 return arm_copy_undef (gdbarch, insn, dsc);
7560 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7563 if (bits (insn, 16, 19) == 0xf)
7565 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7567 return arm_copy_undef (gdbarch, insn, dsc);
7571 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7573 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7577 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7579 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7582 return arm_copy_undef (gdbarch, insn, dsc);
7586 /* Decode miscellaneous instructions in dp/misc encoding space. */
7589 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7590 struct regcache *regs,
7591 struct displaced_step_closure *dsc)
7593 unsigned int op2 = bits (insn, 4, 6);
7594 unsigned int op = bits (insn, 21, 22);
7595 unsigned int op1 = bits (insn, 16, 19);
7600 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7603 if (op == 0x1) /* bx. */
7604 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7606 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7608 return arm_copy_undef (gdbarch, insn, dsc);
7612 /* Not really supported. */
7613 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7615 return arm_copy_undef (gdbarch, insn, dsc);
7619 return arm_copy_bx_blx_reg (gdbarch, insn,
7620 regs, dsc); /* blx register. */
7622 return arm_copy_undef (gdbarch, insn, dsc);
7625 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7629 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7631 /* Not really supported. */
7632 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7635 return arm_copy_undef (gdbarch, insn, dsc);
7640 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7641 struct regcache *regs,
7642 struct displaced_step_closure *dsc)
7645 switch (bits (insn, 20, 24))
7648 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7651 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7653 case 0x12: case 0x16:
7654 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7657 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7661 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7663 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7664 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7665 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7666 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7667 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7668 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7669 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7670 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7671 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7672 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7673 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7674 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7675 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7676 /* 2nd arg means "unpriveleged". */
7677 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7681 /* Should be unreachable. */
7686 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7687 struct regcache *regs,
7688 struct displaced_step_closure *dsc)
7690 int a = bit (insn, 25), b = bit (insn, 4);
7691 uint32_t op1 = bits (insn, 20, 24);
7692 int rn_f = bits (insn, 16, 19) == 0xf;
7694 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7695 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7696 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7697 else if ((!a && (op1 & 0x17) == 0x02)
7698 || (a && (op1 & 0x17) == 0x02 && !b))
7699 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7700 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7701 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7702 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7703 else if ((!a && (op1 & 0x17) == 0x03)
7704 || (a && (op1 & 0x17) == 0x03 && !b))
7705 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7706 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7707 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7708 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7709 else if ((!a && (op1 & 0x17) == 0x06)
7710 || (a && (op1 & 0x17) == 0x06 && !b))
7711 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7712 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7713 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7714 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7715 else if ((!a && (op1 & 0x17) == 0x07)
7716 || (a && (op1 & 0x17) == 0x07 && !b))
7717 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7719 /* Should be unreachable. */
7724 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7725 struct displaced_step_closure *dsc)
7727 switch (bits (insn, 20, 24))
7729 case 0x00: case 0x01: case 0x02: case 0x03:
7730 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7732 case 0x04: case 0x05: case 0x06: case 0x07:
7733 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7735 case 0x08: case 0x09: case 0x0a: case 0x0b:
7736 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7737 return arm_copy_unmodified (gdbarch, insn,
7738 "decode/pack/unpack/saturate/reverse", dsc);
7741 if (bits (insn, 5, 7) == 0) /* op2. */
7743 if (bits (insn, 12, 15) == 0xf)
7744 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7746 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7749 return arm_copy_undef (gdbarch, insn, dsc);
7751 case 0x1a: case 0x1b:
7752 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7753 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7755 return arm_copy_undef (gdbarch, insn, dsc);
7757 case 0x1c: case 0x1d:
7758 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7760 if (bits (insn, 0, 3) == 0xf)
7761 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7763 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7766 return arm_copy_undef (gdbarch, insn, dsc);
7768 case 0x1e: case 0x1f:
7769 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7770 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7772 return arm_copy_undef (gdbarch, insn, dsc);
7775 /* Should be unreachable. */
7780 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7781 struct regcache *regs,
7782 struct displaced_step_closure *dsc)
7785 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7787 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7791 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7792 struct regcache *regs,
7793 struct displaced_step_closure *dsc)
7795 unsigned int opcode = bits (insn, 20, 24);
7799 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7800 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7802 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7803 case 0x12: case 0x16:
7804 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7806 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7807 case 0x13: case 0x17:
7808 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7810 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7811 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7812 /* Note: no writeback for these instructions. Bit 25 will always be
7813 zero though (via caller), so the following works OK. */
7814 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7817 /* Should be unreachable. */
7821 /* Decode shifted register instructions. */
7824 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7825 uint16_t insn2, struct regcache *regs,
7826 struct displaced_step_closure *dsc)
7828 /* PC is only allowed to be used in instruction MOV. */
7830 unsigned int op = bits (insn1, 5, 8);
7831 unsigned int rn = bits (insn1, 0, 3);
7833 if (op == 0x2 && rn == 0xf) /* MOV */
7834 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7836 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7837 "dp (shift reg)", dsc);
7841 /* Decode extension register load/store. Exactly the same as
7842 arm_decode_ext_reg_ld_st. */
7845 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7846 uint16_t insn2, struct regcache *regs,
7847 struct displaced_step_closure *dsc)
7849 unsigned int opcode = bits (insn1, 4, 8);
7853 case 0x04: case 0x05:
7854 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7855 "vfp/neon vmov", dsc);
7857 case 0x08: case 0x0c: /* 01x00 */
7858 case 0x0a: case 0x0e: /* 01x10 */
7859 case 0x12: case 0x16: /* 10x10 */
7860 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7861 "vfp/neon vstm/vpush", dsc);
7863 case 0x09: case 0x0d: /* 01x01 */
7864 case 0x0b: case 0x0f: /* 01x11 */
7865 case 0x13: case 0x17: /* 10x11 */
7866 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7867 "vfp/neon vldm/vpop", dsc);
7869 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7870 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7872 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7873 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7876 /* Should be unreachable. */
7881 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7882 struct regcache *regs, struct displaced_step_closure *dsc)
7884 unsigned int op1 = bits (insn, 20, 25);
7885 int op = bit (insn, 4);
7886 unsigned int coproc = bits (insn, 8, 11);
7887 unsigned int rn = bits (insn, 16, 19);
7889 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7890 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7891 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7892 && (coproc & 0xe) != 0xa)
7894 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7895 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7896 && (coproc & 0xe) != 0xa)
7897 /* ldc/ldc2 imm/lit. */
7898 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7899 else if ((op1 & 0x3e) == 0x00)
7900 return arm_copy_undef (gdbarch, insn, dsc);
7901 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7902 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7903 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7904 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7905 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7906 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7907 else if ((op1 & 0x30) == 0x20 && !op)
7909 if ((coproc & 0xe) == 0xa)
7910 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7912 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7914 else if ((op1 & 0x30) == 0x20 && op)
7915 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7916 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7917 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7918 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7919 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7920 else if ((op1 & 0x30) == 0x30)
7921 return arm_copy_svc (gdbarch, insn, regs, dsc);
7923 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7927 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7928 uint16_t insn2, struct regcache *regs,
7929 struct displaced_step_closure *dsc)
7931 unsigned int coproc = bits (insn2, 8, 11);
7932 unsigned int op1 = bits (insn1, 4, 9);
7933 unsigned int bit_5_8 = bits (insn1, 5, 8);
7934 unsigned int bit_9 = bit (insn1, 9);
7935 unsigned int bit_4 = bit (insn1, 4);
7936 unsigned int rn = bits (insn1, 0, 3);
7941 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7942 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7944 else if (bit_5_8 == 0) /* UNDEFINED. */
7945 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7948 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7949 if ((coproc & 0xe) == 0xa)
7950 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7952 else /* coproc is not 101x. */
7954 if (bit_4 == 0) /* STC/STC2. */
7955 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7957 else /* LDC/LDC2 {literal, immeidate}. */
7958 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7964 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7970 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7971 struct displaced_step_closure *dsc, int rd)
7977 Preparation: Rd <- PC
7983 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7984 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7988 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7989 struct displaced_step_closure *dsc,
7990 int rd, unsigned int imm)
7993 /* Encoding T2: ADDS Rd, #imm */
7994 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7996 install_pc_relative (gdbarch, regs, dsc, rd);
8002 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
8003 struct regcache *regs,
8004 struct displaced_step_closure *dsc)
8006 unsigned int rd = bits (insn, 8, 10);
8007 unsigned int imm8 = bits (insn, 0, 7);
8009 if (debug_displaced)
8010 fprintf_unfiltered (gdb_stdlog,
8011 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8014 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
8018 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
8019 uint16_t insn2, struct regcache *regs,
8020 struct displaced_step_closure *dsc)
8022 unsigned int rd = bits (insn2, 8, 11);
8023 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8024 extract raw immediate encoding rather than computing immediate. When
8025 generating ADD or SUB instruction, we can simply perform OR operation to
8026 set immediate into ADD. */
8027 unsigned int imm_3_8 = insn2 & 0x70ff;
8028 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
8030 if (debug_displaced)
8031 fprintf_unfiltered (gdb_stdlog,
8032 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8033 rd, imm_i, imm_3_8, insn1, insn2);
8035 if (bit (insn1, 7)) /* Encoding T2 */
8037 /* Encoding T3: SUB Rd, Rd, #imm */
8038 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
8039 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8041 else /* Encoding T3 */
8043 /* Encoding T3: ADD Rd, Rd, #imm */
8044 dsc->modinsn[0] = (0xf100 | rd | imm_i);
8045 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8049 install_pc_relative (gdbarch, regs, dsc, rd);
8055 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
8056 struct regcache *regs,
8057 struct displaced_step_closure *dsc)
8059 unsigned int rt = bits (insn1, 8, 10);
8061 int imm8 = (bits (insn1, 0, 7) << 2);
8062 CORE_ADDR from = dsc->insn_addr;
8068 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8070 Insn: LDR R0, [R2, R3];
8071 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8073 if (debug_displaced)
8074 fprintf_unfiltered (gdb_stdlog,
8075 "displaced: copying thumb ldr r%d [pc #%d]\n"
8078 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8079 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8080 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8081 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8082 /* The assembler calculates the required value of the offset from the
8083 Align(PC,4) value of this instruction to the label. */
8084 pc = pc & 0xfffffffc;
8086 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8087 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8090 dsc->u.ldst.xfersize = 4;
8092 dsc->u.ldst.immed = 0;
8093 dsc->u.ldst.writeback = 0;
8094 dsc->u.ldst.restore_r4 = 0;
8096 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8098 dsc->cleanup = &cleanup_load;
8103 /* Copy Thumb cbnz/cbz insruction. */
8106 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
8107 struct regcache *regs,
8108 struct displaced_step_closure *dsc)
8110 int non_zero = bit (insn1, 11);
8111 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
8112 CORE_ADDR from = dsc->insn_addr;
8113 int rn = bits (insn1, 0, 2);
8114 int rn_val = displaced_read_reg (regs, dsc, rn);
8116 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8117 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8118 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8119 condition is false, let it be, cleanup_branch will do nothing. */
8120 if (dsc->u.branch.cond)
8122 dsc->u.branch.cond = INST_AL;
8123 dsc->u.branch.dest = from + 4 + imm5;
8126 dsc->u.branch.dest = from + 2;
8128 dsc->u.branch.link = 0;
8129 dsc->u.branch.exchange = 0;
8131 if (debug_displaced)
8132 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
8133 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
8134 rn, rn_val, insn1, dsc->u.branch.dest);
8136 dsc->modinsn[0] = THUMB_NOP;
8138 dsc->cleanup = &cleanup_branch;
8142 /* Copy Table Branch Byte/Halfword */
8144 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
8145 uint16_t insn2, struct regcache *regs,
8146 struct displaced_step_closure *dsc)
8148 ULONGEST rn_val, rm_val;
8149 int is_tbh = bit (insn2, 4);
8150 CORE_ADDR halfwords = 0;
8151 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8153 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8154 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8160 target_read_memory (rn_val + 2 * rm_val, buf, 2);
8161 halfwords = extract_unsigned_integer (buf, 2, byte_order);
8167 target_read_memory (rn_val + rm_val, buf, 1);
8168 halfwords = extract_unsigned_integer (buf, 1, byte_order);
8171 if (debug_displaced)
8172 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
8173 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
8174 (unsigned int) rn_val, (unsigned int) rm_val,
8175 (unsigned int) halfwords);
8177 dsc->u.branch.cond = INST_AL;
8178 dsc->u.branch.link = 0;
8179 dsc->u.branch.exchange = 0;
8180 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8182 dsc->cleanup = &cleanup_branch;
8188 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8189 struct displaced_step_closure *dsc)
8192 int val = displaced_read_reg (regs, dsc, 7);
8193 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8196 val = displaced_read_reg (regs, dsc, 8);
8197 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8200 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8205 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8206 struct regcache *regs,
8207 struct displaced_step_closure *dsc)
8209 dsc->u.block.regmask = insn1 & 0x00ff;
8211 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8214 (1) register list is full, that is, r0-r7 are used.
8215 Prepare: tmp[0] <- r8
8217 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8218 MOV r8, r7; Move value of r7 to r8;
8219 POP {r7}; Store PC value into r7.
8221 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8223 (2) register list is not full, supposing there are N registers in
8224 register list (except PC, 0 <= N <= 7).
8225 Prepare: for each i, 0 - N, tmp[i] <- ri.
8227 POP {r0, r1, ...., rN};
8229 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8230 from tmp[] properly.
8232 if (debug_displaced)
8233 fprintf_unfiltered (gdb_stdlog,
8234 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8235 dsc->u.block.regmask, insn1);
8237 if (dsc->u.block.regmask == 0xff)
8239 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8241 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8242 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8243 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8246 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8250 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8251 unsigned int new_regmask, bit = 1;
8252 unsigned int to = 0, from = 0, i, new_rn;
8254 for (i = 0; i < num_in_list + 1; i++)
8255 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8257 new_regmask = (1 << (num_in_list + 1)) - 1;
8259 if (debug_displaced)
8260 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8261 "{..., pc}: original reg list %.4x,"
8262 " modified list %.4x\n"),
8263 (int) dsc->u.block.regmask, new_regmask);
8265 dsc->u.block.regmask |= 0x8000;
8266 dsc->u.block.writeback = 0;
8267 dsc->u.block.cond = INST_AL;
8269 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8271 dsc->cleanup = &cleanup_block_load_pc;
8278 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8279 struct regcache *regs,
8280 struct displaced_step_closure *dsc)
8282 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8283 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8286 /* 16-bit thumb instructions. */
8287 switch (op_bit_12_15)
8289 /* Shift (imme), add, subtract, move and compare. */
8290 case 0: case 1: case 2: case 3:
8291 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8292 "shift/add/sub/mov/cmp",
8296 switch (op_bit_10_11)
8298 case 0: /* Data-processing */
8299 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8303 case 1: /* Special data instructions and branch and exchange. */
8305 unsigned short op = bits (insn1, 7, 9);
8306 if (op == 6 || op == 7) /* BX or BLX */
8307 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8308 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8309 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8311 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8315 default: /* LDR (literal) */
8316 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8319 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8320 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8323 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8324 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8325 else /* Generate SP-relative address */
8326 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8328 case 11: /* Misc 16-bit instructions */
8330 switch (bits (insn1, 8, 11))
8332 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8333 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8335 case 12: case 13: /* POP */
8336 if (bit (insn1, 8)) /* PC is in register list. */
8337 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8339 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8341 case 15: /* If-Then, and hints */
8342 if (bits (insn1, 0, 3))
8343 /* If-Then makes up to four following instructions conditional.
8344 IT instruction itself is not conditional, so handle it as a
8345 common unmodified instruction. */
8346 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8349 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8352 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8357 if (op_bit_10_11 < 2) /* Store multiple registers */
8358 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8359 else /* Load multiple registers */
8360 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8362 case 13: /* Conditional branch and supervisor call */
8363 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8364 err = thumb_copy_b (gdbarch, insn1, dsc);
8366 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8368 case 14: /* Unconditional branch */
8369 err = thumb_copy_b (gdbarch, insn1, dsc);
8376 internal_error (__FILE__, __LINE__,
8377 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8381 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8382 uint16_t insn1, uint16_t insn2,
8383 struct regcache *regs,
8384 struct displaced_step_closure *dsc)
8386 int rt = bits (insn2, 12, 15);
8387 int rn = bits (insn1, 0, 3);
8388 int op1 = bits (insn1, 7, 8);
8391 switch (bits (insn1, 5, 6))
8393 case 0: /* Load byte and memory hints */
8394 if (rt == 0xf) /* PLD/PLI */
8397 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8398 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8400 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8405 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8406 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8409 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8410 "ldrb{reg, immediate}/ldrbt",
8415 case 1: /* Load halfword and memory hints. */
8416 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8417 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8418 "pld/unalloc memhint", dsc);
8422 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8425 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8429 case 2: /* Load word */
8431 int insn2_bit_8_11 = bits (insn2, 8, 11);
8434 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8435 else if (op1 == 0x1) /* Encoding T3 */
8436 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8438 else /* op1 == 0x0 */
8440 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8441 /* LDR (immediate) */
8442 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8443 dsc, bit (insn2, 8), 1);
8444 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8445 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8448 /* LDR (register) */
8449 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8455 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8462 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8463 uint16_t insn2, struct regcache *regs,
8464 struct displaced_step_closure *dsc)
8467 unsigned short op = bit (insn2, 15);
8468 unsigned int op1 = bits (insn1, 11, 12);
8474 switch (bits (insn1, 9, 10))
8479 /* Load/store {dual, execlusive}, table branch. */
8480 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8481 && bits (insn2, 5, 7) == 0)
8482 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8485 /* PC is not allowed to use in load/store {dual, exclusive}
8487 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8488 "load/store dual/ex", dsc);
8490 else /* load/store multiple */
8492 switch (bits (insn1, 7, 8))
8494 case 0: case 3: /* SRS, RFE */
8495 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8498 case 1: case 2: /* LDM/STM/PUSH/POP */
8499 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8506 /* Data-processing (shift register). */
8507 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8510 default: /* Coprocessor instructions. */
8511 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8516 case 2: /* op1 = 2 */
8517 if (op) /* Branch and misc control. */
8519 if (bit (insn2, 14) /* BLX/BL */
8520 || bit (insn2, 12) /* Unconditional branch */
8521 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8522 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8524 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8529 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8531 int op = bits (insn1, 4, 8);
8532 int rn = bits (insn1, 0, 3);
8533 if ((op == 0 || op == 0xa) && rn == 0xf)
8534 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8537 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8540 else /* Data processing (modified immeidate) */
8541 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8545 case 3: /* op1 = 3 */
8546 switch (bits (insn1, 9, 10))
8550 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8552 else /* NEON Load/Store and Store single data item */
8553 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8554 "neon elt/struct load/store",
8557 case 1: /* op1 = 3, bits (9, 10) == 1 */
8558 switch (bits (insn1, 7, 8))
8560 case 0: case 1: /* Data processing (register) */
8561 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8564 case 2: /* Multiply and absolute difference */
8565 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8566 "mul/mua/diff", dsc);
8568 case 3: /* Long multiply and divide */
8569 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8574 default: /* Coprocessor instructions */
8575 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8584 internal_error (__FILE__, __LINE__,
8585 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8590 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8591 CORE_ADDR to, struct regcache *regs,
8592 struct displaced_step_closure *dsc)
8594 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8596 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8598 if (debug_displaced)
8599 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8600 "at %.8lx\n", insn1, (unsigned long) from);
8603 dsc->insn_size = thumb_insn_size (insn1);
8604 if (thumb_insn_size (insn1) == 4)
8607 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8608 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8611 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8615 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8616 CORE_ADDR to, struct regcache *regs,
8617 struct displaced_step_closure *dsc)
8620 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8623 /* Most displaced instructions use a 1-instruction scratch space, so set this
8624 here and override below if/when necessary. */
8626 dsc->insn_addr = from;
8627 dsc->scratch_base = to;
8628 dsc->cleanup = NULL;
8629 dsc->wrote_to_pc = 0;
8631 if (!displaced_in_arm_mode (regs))
8632 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8636 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8637 if (debug_displaced)
8638 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8639 "at %.8lx\n", (unsigned long) insn,
8640 (unsigned long) from);
8642 if ((insn & 0xf0000000) == 0xf0000000)
8643 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8644 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8646 case 0x0: case 0x1: case 0x2: case 0x3:
8647 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8650 case 0x4: case 0x5: case 0x6:
8651 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8655 err = arm_decode_media (gdbarch, insn, dsc);
8658 case 0x8: case 0x9: case 0xa: case 0xb:
8659 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8662 case 0xc: case 0xd: case 0xe: case 0xf:
8663 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8668 internal_error (__FILE__, __LINE__,
8669 _("arm_process_displaced_insn: Instruction decode error"));
8672 /* Actually set up the scratch space for a displaced instruction. */
8675 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8676 CORE_ADDR to, struct displaced_step_closure *dsc)
8678 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8679 unsigned int i, len, offset;
8680 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8681 int size = dsc->is_thumb? 2 : 4;
8682 const gdb_byte *bkp_insn;
8685 /* Poke modified instruction(s). */
8686 for (i = 0; i < dsc->numinsns; i++)
8688 if (debug_displaced)
8690 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8692 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8695 fprintf_unfiltered (gdb_stdlog, "%.4x",
8696 (unsigned short)dsc->modinsn[i]);
8698 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8699 (unsigned long) to + offset);
8702 write_memory_unsigned_integer (to + offset, size,
8703 byte_order_for_code,
8708 /* Choose the correct breakpoint instruction. */
8711 bkp_insn = tdep->thumb_breakpoint;
8712 len = tdep->thumb_breakpoint_size;
8716 bkp_insn = tdep->arm_breakpoint;
8717 len = tdep->arm_breakpoint_size;
8720 /* Put breakpoint afterwards. */
8721 write_memory (to + offset, bkp_insn, len);
8723 if (debug_displaced)
8724 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8725 paddress (gdbarch, from), paddress (gdbarch, to));
8728 /* Entry point for copying an instruction into scratch space for displaced
8731 struct displaced_step_closure *
8732 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8733 CORE_ADDR from, CORE_ADDR to,
8734 struct regcache *regs)
8736 struct displaced_step_closure *dsc = XNEW (struct displaced_step_closure);
8738 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8739 arm_displaced_init_closure (gdbarch, from, to, dsc);
8744 /* Entry point for cleaning things up after a displaced instruction has been
8748 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8749 struct displaced_step_closure *dsc,
8750 CORE_ADDR from, CORE_ADDR to,
8751 struct regcache *regs)
8754 dsc->cleanup (gdbarch, regs, dsc);
8756 if (!dsc->wrote_to_pc)
8757 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8758 dsc->insn_addr + dsc->insn_size);
8762 #include "bfd-in2.h"
8763 #include "libcoff.h"
8766 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8768 struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
8770 if (arm_pc_is_thumb (gdbarch, memaddr))
8772 static asymbol *asym;
8773 static combined_entry_type ce;
8774 static struct coff_symbol_struct csym;
8775 static struct bfd fake_bfd;
8776 static bfd_target fake_target;
8778 if (csym.native == NULL)
8780 /* Create a fake symbol vector containing a Thumb symbol.
8781 This is solely so that the code in print_insn_little_arm()
8782 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8783 the presence of a Thumb symbol and switch to decoding
8784 Thumb instructions. */
8786 fake_target.flavour = bfd_target_coff_flavour;
8787 fake_bfd.xvec = &fake_target;
8788 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8790 csym.symbol.the_bfd = &fake_bfd;
8791 csym.symbol.name = "fake";
8792 asym = (asymbol *) & csym;
8795 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8796 info->symbols = &asym;
8799 info->symbols = NULL;
8801 if (info->endian == BFD_ENDIAN_BIG)
8802 return print_insn_big_arm (memaddr, info);
8804 return print_insn_little_arm (memaddr, info);
8807 /* The following define instruction sequences that will cause ARM
8808 cpu's to take an undefined instruction trap. These are used to
8809 signal a breakpoint to GDB.
8811 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8812 modes. A different instruction is required for each mode. The ARM
8813 cpu's can also be big or little endian. Thus four different
8814 instructions are needed to support all cases.
8816 Note: ARMv4 defines several new instructions that will take the
8817 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8818 not in fact add the new instructions. The new undefined
8819 instructions in ARMv4 are all instructions that had no defined
8820 behaviour in earlier chips. There is no guarantee that they will
8821 raise an exception, but may be treated as NOP's. In practice, it
8822 may only safe to rely on instructions matching:
8824 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8825 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8826 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8828 Even this may only true if the condition predicate is true. The
8829 following use a condition predicate of ALWAYS so it is always TRUE.
8831 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8832 and NetBSD all use a software interrupt rather than an undefined
8833 instruction to force a trap. This can be handled by by the
8834 abi-specific code during establishment of the gdbarch vector. */
8836 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8837 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8838 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8839 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8841 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8842 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8843 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8844 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8846 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8847 the program counter value to determine whether a 16-bit or 32-bit
8848 breakpoint should be used. It returns a pointer to a string of
8849 bytes that encode a breakpoint instruction, stores the length of
8850 the string to *lenptr, and adjusts the program counter (if
8851 necessary) to point to the actual memory location where the
8852 breakpoint should be inserted. */
8854 static const unsigned char *
8855 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8857 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8858 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8860 if (arm_pc_is_thumb (gdbarch, *pcptr))
8862 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8864 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8865 check whether we are replacing a 32-bit instruction. */
8866 if (tdep->thumb2_breakpoint != NULL)
8869 if (target_read_memory (*pcptr, buf, 2) == 0)
8871 unsigned short inst1;
8872 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8873 if (thumb_insn_size (inst1) == 4)
8875 *lenptr = tdep->thumb2_breakpoint_size;
8876 return tdep->thumb2_breakpoint;
8881 *lenptr = tdep->thumb_breakpoint_size;
8882 return tdep->thumb_breakpoint;
8886 *lenptr = tdep->arm_breakpoint_size;
8887 return tdep->arm_breakpoint;
8892 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8895 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8897 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8898 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8899 that this is not confused with a 32-bit ARM breakpoint. */
8903 /* Extract from an array REGBUF containing the (raw) register state a
8904 function return value of type TYPE, and copy that, in virtual
8905 format, into VALBUF. */
8908 arm_extract_return_value (struct type *type, struct regcache *regs,
8911 struct gdbarch *gdbarch = get_regcache_arch (regs);
8912 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8914 if (TYPE_CODE_FLT == TYPE_CODE (type))
8916 switch (gdbarch_tdep (gdbarch)->fp_model)
8920 /* The value is in register F0 in internal format. We need to
8921 extract the raw value and then convert it to the desired
8923 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8925 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8926 convert_from_extended (floatformat_from_type (type), tmpbuf,
8927 valbuf, gdbarch_byte_order (gdbarch));
8931 case ARM_FLOAT_SOFT_FPA:
8932 case ARM_FLOAT_SOFT_VFP:
8933 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8934 not using the VFP ABI code. */
8936 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8937 if (TYPE_LENGTH (type) > 4)
8938 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8939 valbuf + INT_REGISTER_SIZE);
8943 internal_error (__FILE__, __LINE__,
8944 _("arm_extract_return_value: "
8945 "Floating point model not supported"));
8949 else if (TYPE_CODE (type) == TYPE_CODE_INT
8950 || TYPE_CODE (type) == TYPE_CODE_CHAR
8951 || TYPE_CODE (type) == TYPE_CODE_BOOL
8952 || TYPE_CODE (type) == TYPE_CODE_PTR
8953 || TYPE_CODE (type) == TYPE_CODE_REF
8954 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8956 /* If the type is a plain integer, then the access is
8957 straight-forward. Otherwise we have to play around a bit
8959 int len = TYPE_LENGTH (type);
8960 int regno = ARM_A1_REGNUM;
8965 /* By using store_unsigned_integer we avoid having to do
8966 anything special for small big-endian values. */
8967 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8968 store_unsigned_integer (valbuf,
8969 (len > INT_REGISTER_SIZE
8970 ? INT_REGISTER_SIZE : len),
8972 len -= INT_REGISTER_SIZE;
8973 valbuf += INT_REGISTER_SIZE;
8978 /* For a structure or union the behaviour is as if the value had
8979 been stored to word-aligned memory and then loaded into
8980 registers with 32-bit load instruction(s). */
8981 int len = TYPE_LENGTH (type);
8982 int regno = ARM_A1_REGNUM;
8983 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8987 regcache_cooked_read (regs, regno++, tmpbuf);
8988 memcpy (valbuf, tmpbuf,
8989 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8990 len -= INT_REGISTER_SIZE;
8991 valbuf += INT_REGISTER_SIZE;
8997 /* Will a function return an aggregate type in memory or in a
8998 register? Return 0 if an aggregate type can be returned in a
8999 register, 1 if it must be returned in memory. */
9002 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
9004 enum type_code code;
9006 type = check_typedef (type);
9008 /* Simple, non-aggregate types (ie not including vectors and
9009 complex) are always returned in a register (or registers). */
9010 code = TYPE_CODE (type);
9011 if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code
9012 && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code)
9015 if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type))
9017 /* Vector values should be returned using ARM registers if they
9018 are not over 16 bytes. */
9019 return (TYPE_LENGTH (type) > 16);
9022 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
9024 /* The AAPCS says all aggregates not larger than a word are returned
9026 if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
9035 /* All aggregate types that won't fit in a register must be returned
9037 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
9040 /* In the ARM ABI, "integer" like aggregate types are returned in
9041 registers. For an aggregate type to be integer like, its size
9042 must be less than or equal to INT_REGISTER_SIZE and the
9043 offset of each addressable subfield must be zero. Note that bit
9044 fields are not addressable, and all addressable subfields of
9045 unions always start at offset zero.
9047 This function is based on the behaviour of GCC 2.95.1.
9048 See: gcc/arm.c: arm_return_in_memory() for details.
9050 Note: All versions of GCC before GCC 2.95.2 do not set up the
9051 parameters correctly for a function returning the following
9052 structure: struct { float f;}; This should be returned in memory,
9053 not a register. Richard Earnshaw sent me a patch, but I do not
9054 know of any way to detect if a function like the above has been
9055 compiled with the correct calling convention. */
9057 /* Assume all other aggregate types can be returned in a register.
9058 Run a check for structures, unions and arrays. */
9061 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
9064 /* Need to check if this struct/union is "integer" like. For
9065 this to be true, its size must be less than or equal to
9066 INT_REGISTER_SIZE and the offset of each addressable
9067 subfield must be zero. Note that bit fields are not
9068 addressable, and unions always start at offset zero. If any
9069 of the subfields is a floating point type, the struct/union
9070 cannot be an integer type. */
9072 /* For each field in the object, check:
9073 1) Is it FP? --> yes, nRc = 1;
9074 2) Is it addressable (bitpos != 0) and
9075 not packed (bitsize == 0)?
9079 for (i = 0; i < TYPE_NFIELDS (type); i++)
9081 enum type_code field_type_code;
9084 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
9087 /* Is it a floating point type field? */
9088 if (field_type_code == TYPE_CODE_FLT)
9094 /* If bitpos != 0, then we have to care about it. */
9095 if (TYPE_FIELD_BITPOS (type, i) != 0)
9097 /* Bitfields are not addressable. If the field bitsize is
9098 zero, then the field is not packed. Hence it cannot be
9099 a bitfield or any other packed type. */
9100 if (TYPE_FIELD_BITSIZE (type, i) == 0)
9113 /* Write into appropriate registers a function return value of type
9114 TYPE, given in virtual format. */
9117 arm_store_return_value (struct type *type, struct regcache *regs,
9118 const gdb_byte *valbuf)
9120 struct gdbarch *gdbarch = get_regcache_arch (regs);
9121 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9123 if (TYPE_CODE (type) == TYPE_CODE_FLT)
9125 gdb_byte buf[MAX_REGISTER_SIZE];
9127 switch (gdbarch_tdep (gdbarch)->fp_model)
9131 convert_to_extended (floatformat_from_type (type), buf, valbuf,
9132 gdbarch_byte_order (gdbarch));
9133 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
9136 case ARM_FLOAT_SOFT_FPA:
9137 case ARM_FLOAT_SOFT_VFP:
9138 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9139 not using the VFP ABI code. */
9141 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
9142 if (TYPE_LENGTH (type) > 4)
9143 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
9144 valbuf + INT_REGISTER_SIZE);
9148 internal_error (__FILE__, __LINE__,
9149 _("arm_store_return_value: Floating "
9150 "point model not supported"));
9154 else if (TYPE_CODE (type) == TYPE_CODE_INT
9155 || TYPE_CODE (type) == TYPE_CODE_CHAR
9156 || TYPE_CODE (type) == TYPE_CODE_BOOL
9157 || TYPE_CODE (type) == TYPE_CODE_PTR
9158 || TYPE_CODE (type) == TYPE_CODE_REF
9159 || TYPE_CODE (type) == TYPE_CODE_ENUM)
9161 if (TYPE_LENGTH (type) <= 4)
9163 /* Values of one word or less are zero/sign-extended and
9165 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9166 LONGEST val = unpack_long (type, valbuf);
9168 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
9169 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
9173 /* Integral values greater than one word are stored in consecutive
9174 registers starting with r0. This will always be a multiple of
9175 the regiser size. */
9176 int len = TYPE_LENGTH (type);
9177 int regno = ARM_A1_REGNUM;
9181 regcache_cooked_write (regs, regno++, valbuf);
9182 len -= INT_REGISTER_SIZE;
9183 valbuf += INT_REGISTER_SIZE;
9189 /* For a structure or union the behaviour is as if the value had
9190 been stored to word-aligned memory and then loaded into
9191 registers with 32-bit load instruction(s). */
9192 int len = TYPE_LENGTH (type);
9193 int regno = ARM_A1_REGNUM;
9194 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9198 memcpy (tmpbuf, valbuf,
9199 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9200 regcache_cooked_write (regs, regno++, tmpbuf);
9201 len -= INT_REGISTER_SIZE;
9202 valbuf += INT_REGISTER_SIZE;
9208 /* Handle function return values. */
9210 static enum return_value_convention
9211 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9212 struct type *valtype, struct regcache *regcache,
9213 gdb_byte *readbuf, const gdb_byte *writebuf)
9215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9216 struct type *func_type = function ? value_type (function) : NULL;
9217 enum arm_vfp_cprc_base_type vfp_base_type;
9220 if (arm_vfp_abi_for_function (gdbarch, func_type)
9221 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9223 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9224 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9226 for (i = 0; i < vfp_base_count; i++)
9228 if (reg_char == 'q')
9231 arm_neon_quad_write (gdbarch, regcache, i,
9232 writebuf + i * unit_length);
9235 arm_neon_quad_read (gdbarch, regcache, i,
9236 readbuf + i * unit_length);
9243 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
9244 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9247 regcache_cooked_write (regcache, regnum,
9248 writebuf + i * unit_length);
9250 regcache_cooked_read (regcache, regnum,
9251 readbuf + i * unit_length);
9254 return RETURN_VALUE_REGISTER_CONVENTION;
9257 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9258 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9259 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9261 if (tdep->struct_return == pcc_struct_return
9262 || arm_return_in_memory (gdbarch, valtype))
9263 return RETURN_VALUE_STRUCT_CONVENTION;
9265 else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX)
9267 if (arm_return_in_memory (gdbarch, valtype))
9268 return RETURN_VALUE_STRUCT_CONVENTION;
9272 arm_store_return_value (valtype, regcache, writebuf);
9275 arm_extract_return_value (valtype, regcache, readbuf);
9277 return RETURN_VALUE_REGISTER_CONVENTION;
9282 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9284 struct gdbarch *gdbarch = get_frame_arch (frame);
9285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9286 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9288 gdb_byte buf[INT_REGISTER_SIZE];
9290 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9292 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9296 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9300 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9301 return the target PC. Otherwise return 0. */
9304 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9308 CORE_ADDR start_addr;
9310 /* Find the starting address and name of the function containing the PC. */
9311 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9313 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9315 start_addr = arm_skip_bx_reg (frame, pc);
9316 if (start_addr != 0)
9322 /* If PC is in a Thumb call or return stub, return the address of the
9323 target PC, which is in a register. The thunk functions are called
9324 _call_via_xx, where x is the register name. The possible names
9325 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9326 functions, named __ARM_call_via_r[0-7]. */
9327 if (startswith (name, "_call_via_")
9328 || startswith (name, "__ARM_call_via_"))
9330 /* Use the name suffix to determine which register contains the
9332 static char *table[15] =
9333 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9334 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9337 int offset = strlen (name) - 2;
9339 for (regno = 0; regno <= 14; regno++)
9340 if (strcmp (&name[offset], table[regno]) == 0)
9341 return get_frame_register_unsigned (frame, regno);
9344 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9345 non-interworking calls to foo. We could decode the stubs
9346 to find the target but it's easier to use the symbol table. */
9347 namelen = strlen (name);
9348 if (name[0] == '_' && name[1] == '_'
9349 && ((namelen > 2 + strlen ("_from_thumb")
9350 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
9351 || (namelen > 2 + strlen ("_from_arm")
9352 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
9355 int target_len = namelen - 2;
9356 struct bound_minimal_symbol minsym;
9357 struct objfile *objfile;
9358 struct obj_section *sec;
9360 if (name[namelen - 1] == 'b')
9361 target_len -= strlen ("_from_thumb");
9363 target_len -= strlen ("_from_arm");
9365 target_name = (char *) alloca (target_len + 1);
9366 memcpy (target_name, name + 2, target_len);
9367 target_name[target_len] = '\0';
9369 sec = find_pc_section (pc);
9370 objfile = (sec == NULL) ? NULL : sec->objfile;
9371 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9372 if (minsym.minsym != NULL)
9373 return BMSYMBOL_VALUE_ADDRESS (minsym);
9378 return 0; /* not a stub */
9382 set_arm_command (char *args, int from_tty)
9384 printf_unfiltered (_("\
9385 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9386 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9390 show_arm_command (char *args, int from_tty)
9392 cmd_show_list (showarmcmdlist, from_tty, "");
9396 arm_update_current_architecture (void)
9398 struct gdbarch_info info;
9400 /* If the current architecture is not ARM, we have nothing to do. */
9401 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
9404 /* Update the architecture. */
9405 gdbarch_info_init (&info);
9407 if (!gdbarch_update_p (info))
9408 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9412 set_fp_model_sfunc (char *args, int from_tty,
9413 struct cmd_list_element *c)
9417 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9418 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9420 arm_fp_model = (enum arm_float_model) fp_model;
9424 if (fp_model == ARM_FLOAT_LAST)
9425 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9428 arm_update_current_architecture ();
9432 show_fp_model (struct ui_file *file, int from_tty,
9433 struct cmd_list_element *c, const char *value)
9435 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9437 if (arm_fp_model == ARM_FLOAT_AUTO
9438 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9439 fprintf_filtered (file, _("\
9440 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9441 fp_model_strings[tdep->fp_model]);
9443 fprintf_filtered (file, _("\
9444 The current ARM floating point model is \"%s\".\n"),
9445 fp_model_strings[arm_fp_model]);
9449 arm_set_abi (char *args, int from_tty,
9450 struct cmd_list_element *c)
9454 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9455 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9457 arm_abi_global = (enum arm_abi_kind) arm_abi;
9461 if (arm_abi == ARM_ABI_LAST)
9462 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9465 arm_update_current_architecture ();
9469 arm_show_abi (struct ui_file *file, int from_tty,
9470 struct cmd_list_element *c, const char *value)
9472 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9474 if (arm_abi_global == ARM_ABI_AUTO
9475 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9476 fprintf_filtered (file, _("\
9477 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9478 arm_abi_strings[tdep->arm_abi]);
9480 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9485 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9486 struct cmd_list_element *c, const char *value)
9488 fprintf_filtered (file,
9489 _("The current execution mode assumed "
9490 "(when symbols are unavailable) is \"%s\".\n"),
9491 arm_fallback_mode_string);
9495 arm_show_force_mode (struct ui_file *file, int from_tty,
9496 struct cmd_list_element *c, const char *value)
9498 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9500 fprintf_filtered (file,
9501 _("The current execution mode assumed "
9502 "(even when symbols are available) is \"%s\".\n"),
9503 arm_force_mode_string);
9506 /* If the user changes the register disassembly style used for info
9507 register and other commands, we have to also switch the style used
9508 in opcodes for disassembly output. This function is run in the "set
9509 arm disassembly" command, and does that. */
9512 set_disassembly_style_sfunc (char *args, int from_tty,
9513 struct cmd_list_element *c)
9515 set_disassembly_style ();
9518 /* Return the ARM register name corresponding to register I. */
9520 arm_register_name (struct gdbarch *gdbarch, int i)
9522 const int num_regs = gdbarch_num_regs (gdbarch);
9524 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9525 && i >= num_regs && i < num_regs + 32)
9527 static const char *const vfp_pseudo_names[] = {
9528 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9529 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9530 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9531 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9534 return vfp_pseudo_names[i - num_regs];
9537 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9538 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9540 static const char *const neon_pseudo_names[] = {
9541 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9542 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9545 return neon_pseudo_names[i - num_regs - 32];
9548 if (i >= ARRAY_SIZE (arm_register_names))
9549 /* These registers are only supported on targets which supply
9550 an XML description. */
9553 return arm_register_names[i];
9557 set_disassembly_style (void)
9561 /* Find the style that the user wants. */
9562 for (current = 0; current < num_disassembly_options; current++)
9563 if (disassembly_style == valid_disassembly_styles[current])
9565 gdb_assert (current < num_disassembly_options);
9567 /* Synchronize the disassembler. */
9568 set_arm_regname_option (current);
9571 /* Test whether the coff symbol specific value corresponds to a Thumb
9575 coff_sym_is_thumb (int val)
9577 return (val == C_THUMBEXT
9578 || val == C_THUMBSTAT
9579 || val == C_THUMBEXTFUNC
9580 || val == C_THUMBSTATFUNC
9581 || val == C_THUMBLABEL);
9584 /* arm_coff_make_msymbol_special()
9585 arm_elf_make_msymbol_special()
9587 These functions test whether the COFF or ELF symbol corresponds to
9588 an address in thumb code, and set a "special" bit in a minimal
9589 symbol to indicate that it does. */
9592 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9594 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9595 == ST_BRANCH_TO_THUMB)
9596 MSYMBOL_SET_SPECIAL (msym);
9600 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9602 if (coff_sym_is_thumb (val))
9603 MSYMBOL_SET_SPECIAL (msym);
9607 arm_objfile_data_free (struct objfile *objfile, void *arg)
9609 struct arm_per_objfile *data = (struct arm_per_objfile *) arg;
9612 for (i = 0; i < objfile->obfd->section_count; i++)
9613 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9617 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9620 const char *name = bfd_asymbol_name (sym);
9621 struct arm_per_objfile *data;
9622 VEC(arm_mapping_symbol_s) **map_p;
9623 struct arm_mapping_symbol new_map_sym;
9625 gdb_assert (name[0] == '$');
9626 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9629 data = (struct arm_per_objfile *) objfile_data (objfile,
9630 arm_objfile_data_key);
9633 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9634 struct arm_per_objfile);
9635 set_objfile_data (objfile, arm_objfile_data_key, data);
9636 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9637 objfile->obfd->section_count,
9638 VEC(arm_mapping_symbol_s) *);
9640 map_p = &data->section_maps[bfd_get_section (sym)->index];
9642 new_map_sym.value = sym->value;
9643 new_map_sym.type = name[1];
9645 /* Assume that most mapping symbols appear in order of increasing
9646 value. If they were randomly distributed, it would be faster to
9647 always push here and then sort at first use. */
9648 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9650 struct arm_mapping_symbol *prev_map_sym;
9652 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9653 if (prev_map_sym->value >= sym->value)
9656 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9657 arm_compare_mapping_symbols);
9658 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9663 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9667 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9669 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9670 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9672 /* If necessary, set the T bit. */
9675 ULONGEST val, t_bit;
9676 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9677 t_bit = arm_psr_thumb_bit (gdbarch);
9678 if (arm_pc_is_thumb (gdbarch, pc))
9679 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9682 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9687 /* Read the contents of a NEON quad register, by reading from two
9688 double registers. This is used to implement the quad pseudo
9689 registers, and for argument passing in case the quad registers are
9690 missing; vectors are passed in quad registers when using the VFP
9691 ABI, even if a NEON unit is not present. REGNUM is the index of
9692 the quad register, in [0, 15]. */
9694 static enum register_status
9695 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9696 int regnum, gdb_byte *buf)
9699 gdb_byte reg_buf[8];
9700 int offset, double_regnum;
9701 enum register_status status;
9703 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9704 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9707 /* d0 is always the least significant half of q0. */
9708 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9713 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9714 if (status != REG_VALID)
9716 memcpy (buf + offset, reg_buf, 8);
9718 offset = 8 - offset;
9719 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9720 if (status != REG_VALID)
9722 memcpy (buf + offset, reg_buf, 8);
9727 static enum register_status
9728 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9729 int regnum, gdb_byte *buf)
9731 const int num_regs = gdbarch_num_regs (gdbarch);
9733 gdb_byte reg_buf[8];
9734 int offset, double_regnum;
9736 gdb_assert (regnum >= num_regs);
9739 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9740 /* Quad-precision register. */
9741 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9744 enum register_status status;
9746 /* Single-precision register. */
9747 gdb_assert (regnum < 32);
9749 /* s0 is always the least significant half of d0. */
9750 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9751 offset = (regnum & 1) ? 0 : 4;
9753 offset = (regnum & 1) ? 4 : 0;
9755 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9756 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9759 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9760 if (status == REG_VALID)
9761 memcpy (buf, reg_buf + offset, 4);
9766 /* Store the contents of BUF to a NEON quad register, by writing to
9767 two double registers. This is used to implement the quad pseudo
9768 registers, and for argument passing in case the quad registers are
9769 missing; vectors are passed in quad registers when using the VFP
9770 ABI, even if a NEON unit is not present. REGNUM is the index
9771 of the quad register, in [0, 15]. */
9774 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9775 int regnum, const gdb_byte *buf)
9778 int offset, double_regnum;
9780 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9781 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9784 /* d0 is always the least significant half of q0. */
9785 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9790 regcache_raw_write (regcache, double_regnum, buf + offset);
9791 offset = 8 - offset;
9792 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9796 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9797 int regnum, const gdb_byte *buf)
9799 const int num_regs = gdbarch_num_regs (gdbarch);
9801 gdb_byte reg_buf[8];
9802 int offset, double_regnum;
9804 gdb_assert (regnum >= num_regs);
9807 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9808 /* Quad-precision register. */
9809 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9812 /* Single-precision register. */
9813 gdb_assert (regnum < 32);
9815 /* s0 is always the least significant half of d0. */
9816 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9817 offset = (regnum & 1) ? 0 : 4;
9819 offset = (regnum & 1) ? 4 : 0;
9821 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9822 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9825 regcache_raw_read (regcache, double_regnum, reg_buf);
9826 memcpy (reg_buf + offset, buf, 4);
9827 regcache_raw_write (regcache, double_regnum, reg_buf);
9831 static struct value *
9832 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9834 const int *reg_p = (const int *) baton;
9835 return value_of_register (*reg_p, frame);
9838 static enum gdb_osabi
9839 arm_elf_osabi_sniffer (bfd *abfd)
9841 unsigned int elfosabi;
9842 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9844 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9846 if (elfosabi == ELFOSABI_ARM)
9847 /* GNU tools use this value. Check note sections in this case,
9849 bfd_map_over_sections (abfd,
9850 generic_elf_osabi_sniff_abi_tag_sections,
9853 /* Anything else will be handled by the generic ELF sniffer. */
9858 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9859 struct reggroup *group)
9861 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9862 this, FPS register belongs to save_regroup, restore_reggroup, and
9863 all_reggroup, of course. */
9864 if (regnum == ARM_FPS_REGNUM)
9865 return (group == float_reggroup
9866 || group == save_reggroup
9867 || group == restore_reggroup
9868 || group == all_reggroup);
9870 return default_register_reggroup_p (gdbarch, regnum, group);
9874 /* For backward-compatibility we allow two 'g' packet lengths with
9875 the remote protocol depending on whether FPA registers are
9876 supplied. M-profile targets do not have FPA registers, but some
9877 stubs already exist in the wild which use a 'g' packet which
9878 supplies them albeit with dummy values. The packet format which
9879 includes FPA registers should be considered deprecated for
9880 M-profile targets. */
9883 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9885 if (gdbarch_tdep (gdbarch)->is_m)
9887 /* If we know from the executable this is an M-profile target,
9888 cater for remote targets whose register set layout is the
9889 same as the FPA layout. */
9890 register_remote_g_packet_guess (gdbarch,
9891 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9892 (16 * INT_REGISTER_SIZE)
9893 + (8 * FP_REGISTER_SIZE)
9894 + (2 * INT_REGISTER_SIZE),
9895 tdesc_arm_with_m_fpa_layout);
9897 /* The regular M-profile layout. */
9898 register_remote_g_packet_guess (gdbarch,
9899 /* r0-r12,sp,lr,pc; xpsr */
9900 (16 * INT_REGISTER_SIZE)
9901 + INT_REGISTER_SIZE,
9904 /* M-profile plus M4F VFP. */
9905 register_remote_g_packet_guess (gdbarch,
9906 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9907 (16 * INT_REGISTER_SIZE)
9908 + (16 * VFP_REGISTER_SIZE)
9909 + (2 * INT_REGISTER_SIZE),
9910 tdesc_arm_with_m_vfp_d16);
9913 /* Otherwise we don't have a useful guess. */
9917 /* Initialize the current architecture based on INFO. If possible,
9918 re-use an architecture from ARCHES, which is a list of
9919 architectures already created during this debugging session.
9921 Called e.g. at program startup, when reading a core file, and when
9922 reading a binary file. */
9924 static struct gdbarch *
9925 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9927 struct gdbarch_tdep *tdep;
9928 struct gdbarch *gdbarch;
9929 struct gdbarch_list *best_arch;
9930 enum arm_abi_kind arm_abi = arm_abi_global;
9931 enum arm_float_model fp_model = arm_fp_model;
9932 struct tdesc_arch_data *tdesc_data = NULL;
9934 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9935 int have_wmmx_registers = 0;
9937 int have_fpa_registers = 1;
9938 const struct target_desc *tdesc = info.target_desc;
9940 /* If we have an object to base this architecture on, try to determine
9943 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9945 int ei_osabi, e_flags;
9947 switch (bfd_get_flavour (info.abfd))
9949 case bfd_target_aout_flavour:
9950 /* Assume it's an old APCS-style ABI. */
9951 arm_abi = ARM_ABI_APCS;
9954 case bfd_target_coff_flavour:
9955 /* Assume it's an old APCS-style ABI. */
9957 arm_abi = ARM_ABI_APCS;
9960 case bfd_target_elf_flavour:
9961 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9962 e_flags = elf_elfheader (info.abfd)->e_flags;
9964 if (ei_osabi == ELFOSABI_ARM)
9966 /* GNU tools used to use this value, but do not for EABI
9967 objects. There's nowhere to tag an EABI version
9968 anyway, so assume APCS. */
9969 arm_abi = ARM_ABI_APCS;
9971 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
9973 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9974 int attr_arch, attr_profile;
9978 case EF_ARM_EABI_UNKNOWN:
9979 /* Assume GNU tools. */
9980 arm_abi = ARM_ABI_APCS;
9983 case EF_ARM_EABI_VER4:
9984 case EF_ARM_EABI_VER5:
9985 arm_abi = ARM_ABI_AAPCS;
9986 /* EABI binaries default to VFP float ordering.
9987 They may also contain build attributes that can
9988 be used to identify if the VFP argument-passing
9990 if (fp_model == ARM_FLOAT_AUTO)
9993 switch (bfd_elf_get_obj_attr_int (info.abfd,
9997 case AEABI_VFP_args_base:
9998 /* "The user intended FP parameter/result
9999 passing to conform to AAPCS, base
10001 fp_model = ARM_FLOAT_SOFT_VFP;
10003 case AEABI_VFP_args_vfp:
10004 /* "The user intended FP parameter/result
10005 passing to conform to AAPCS, VFP
10007 fp_model = ARM_FLOAT_VFP;
10009 case AEABI_VFP_args_toolchain:
10010 /* "The user intended FP parameter/result
10011 passing to conform to tool chain-specific
10012 conventions" - we don't know any such
10013 conventions, so leave it as "auto". */
10015 case AEABI_VFP_args_compatible:
10016 /* "Code is compatible with both the base
10017 and VFP variants; the user did not permit
10018 non-variadic functions to pass FP
10019 parameters/results" - leave it as
10023 /* Attribute value not mentioned in the
10024 November 2012 ABI, so leave it as
10029 fp_model = ARM_FLOAT_SOFT_VFP;
10035 /* Leave it as "auto". */
10036 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
10041 /* Detect M-profile programs. This only works if the
10042 executable file includes build attributes; GCC does
10043 copy them to the executable, but e.g. RealView does
10045 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10047 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
10049 Tag_CPU_arch_profile);
10050 /* GCC specifies the profile for v6-M; RealView only
10051 specifies the profile for architectures starting with
10052 V7 (as opposed to architectures with a tag
10053 numerically greater than TAG_CPU_ARCH_V7). */
10054 if (!tdesc_has_registers (tdesc)
10055 && (attr_arch == TAG_CPU_ARCH_V6_M
10056 || attr_arch == TAG_CPU_ARCH_V6S_M
10057 || attr_profile == 'M'))
10062 if (fp_model == ARM_FLOAT_AUTO)
10064 int e_flags = elf_elfheader (info.abfd)->e_flags;
10066 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
10069 /* Leave it as "auto". Strictly speaking this case
10070 means FPA, but almost nobody uses that now, and
10071 many toolchains fail to set the appropriate bits
10072 for the floating-point model they use. */
10074 case EF_ARM_SOFT_FLOAT:
10075 fp_model = ARM_FLOAT_SOFT_FPA;
10077 case EF_ARM_VFP_FLOAT:
10078 fp_model = ARM_FLOAT_VFP;
10080 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
10081 fp_model = ARM_FLOAT_SOFT_VFP;
10086 if (e_flags & EF_ARM_BE8)
10087 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10092 /* Leave it as "auto". */
10097 /* Check any target description for validity. */
10098 if (tdesc_has_registers (tdesc))
10100 /* For most registers we require GDB's default names; but also allow
10101 the numeric names for sp / lr / pc, as a convenience. */
10102 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
10103 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
10104 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
10106 const struct tdesc_feature *feature;
10109 feature = tdesc_find_feature (tdesc,
10110 "org.gnu.gdb.arm.core");
10111 if (feature == NULL)
10113 feature = tdesc_find_feature (tdesc,
10114 "org.gnu.gdb.arm.m-profile");
10115 if (feature == NULL)
10121 tdesc_data = tdesc_data_alloc ();
10124 for (i = 0; i < ARM_SP_REGNUM; i++)
10125 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10126 arm_register_names[i]);
10127 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10130 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10133 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10137 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10138 ARM_PS_REGNUM, "xpsr");
10140 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10141 ARM_PS_REGNUM, "cpsr");
10145 tdesc_data_cleanup (tdesc_data);
10149 feature = tdesc_find_feature (tdesc,
10150 "org.gnu.gdb.arm.fpa");
10151 if (feature != NULL)
10154 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
10155 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10156 arm_register_names[i]);
10159 tdesc_data_cleanup (tdesc_data);
10164 have_fpa_registers = 0;
10166 feature = tdesc_find_feature (tdesc,
10167 "org.gnu.gdb.xscale.iwmmxt");
10168 if (feature != NULL)
10170 static const char *const iwmmxt_names[] = {
10171 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10172 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10173 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10174 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10178 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
10180 &= tdesc_numbered_register (feature, tdesc_data, i,
10181 iwmmxt_names[i - ARM_WR0_REGNUM]);
10183 /* Check for the control registers, but do not fail if they
10185 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
10186 tdesc_numbered_register (feature, tdesc_data, i,
10187 iwmmxt_names[i - ARM_WR0_REGNUM]);
10189 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
10191 &= tdesc_numbered_register (feature, tdesc_data, i,
10192 iwmmxt_names[i - ARM_WR0_REGNUM]);
10196 tdesc_data_cleanup (tdesc_data);
10200 have_wmmx_registers = 1;
10203 /* If we have a VFP unit, check whether the single precision registers
10204 are present. If not, then we will synthesize them as pseudo
10206 feature = tdesc_find_feature (tdesc,
10207 "org.gnu.gdb.arm.vfp");
10208 if (feature != NULL)
10210 static const char *const vfp_double_names[] = {
10211 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10212 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10213 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10214 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10217 /* Require the double precision registers. There must be either
10220 for (i = 0; i < 32; i++)
10222 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10224 vfp_double_names[i]);
10228 if (!valid_p && i == 16)
10231 /* Also require FPSCR. */
10232 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10233 ARM_FPSCR_REGNUM, "fpscr");
10236 tdesc_data_cleanup (tdesc_data);
10240 if (tdesc_unnumbered_register (feature, "s0") == 0)
10241 have_vfp_pseudos = 1;
10243 vfp_register_count = i;
10245 /* If we have VFP, also check for NEON. The architecture allows
10246 NEON without VFP (integer vector operations only), but GDB
10247 does not support that. */
10248 feature = tdesc_find_feature (tdesc,
10249 "org.gnu.gdb.arm.neon");
10250 if (feature != NULL)
10252 /* NEON requires 32 double-precision registers. */
10255 tdesc_data_cleanup (tdesc_data);
10259 /* If there are quad registers defined by the stub, use
10260 their type; otherwise (normally) provide them with
10261 the default type. */
10262 if (tdesc_unnumbered_register (feature, "q0") == 0)
10263 have_neon_pseudos = 1;
10270 /* If there is already a candidate, use it. */
10271 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10273 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10275 if (arm_abi != ARM_ABI_AUTO
10276 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10279 if (fp_model != ARM_FLOAT_AUTO
10280 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10283 /* There are various other properties in tdep that we do not
10284 need to check here: those derived from a target description,
10285 since gdbarches with a different target description are
10286 automatically disqualified. */
10288 /* Do check is_m, though, since it might come from the binary. */
10289 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10292 /* Found a match. */
10296 if (best_arch != NULL)
10298 if (tdesc_data != NULL)
10299 tdesc_data_cleanup (tdesc_data);
10300 return best_arch->gdbarch;
10303 tdep = XCNEW (struct gdbarch_tdep);
10304 gdbarch = gdbarch_alloc (&info, tdep);
10306 /* Record additional information about the architecture we are defining.
10307 These are gdbarch discriminators, like the OSABI. */
10308 tdep->arm_abi = arm_abi;
10309 tdep->fp_model = fp_model;
10311 tdep->have_fpa_registers = have_fpa_registers;
10312 tdep->have_wmmx_registers = have_wmmx_registers;
10313 gdb_assert (vfp_register_count == 0
10314 || vfp_register_count == 16
10315 || vfp_register_count == 32);
10316 tdep->vfp_register_count = vfp_register_count;
10317 tdep->have_vfp_pseudos = have_vfp_pseudos;
10318 tdep->have_neon_pseudos = have_neon_pseudos;
10319 tdep->have_neon = have_neon;
10321 arm_register_g_packet_guesses (gdbarch);
10324 switch (info.byte_order_for_code)
10326 case BFD_ENDIAN_BIG:
10327 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10328 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10329 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10330 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10334 case BFD_ENDIAN_LITTLE:
10335 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10336 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10337 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10338 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10343 internal_error (__FILE__, __LINE__,
10344 _("arm_gdbarch_init: bad byte order for float format"));
10347 /* On ARM targets char defaults to unsigned. */
10348 set_gdbarch_char_signed (gdbarch, 0);
10350 /* Note: for displaced stepping, this includes the breakpoint, and one word
10351 of additional scratch space. This setting isn't used for anything beside
10352 displaced stepping at present. */
10353 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10355 /* This should be low enough for everything. */
10356 tdep->lowest_pc = 0x20;
10357 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10359 /* The default, for both APCS and AAPCS, is to return small
10360 structures in registers. */
10361 tdep->struct_return = reg_struct_return;
10363 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10364 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10366 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10368 /* Frame handling. */
10369 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10370 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10371 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10373 frame_base_set_default (gdbarch, &arm_normal_base);
10375 /* Address manipulation. */
10376 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10378 /* Advance PC across function entry code. */
10379 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10381 /* Detect whether PC is at a point where the stack has been destroyed. */
10382 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
10384 /* Skip trampolines. */
10385 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10387 /* The stack grows downward. */
10388 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10390 /* Breakpoint manipulation. */
10391 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10392 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10393 arm_remote_breakpoint_from_pc);
10395 /* Information about registers, etc. */
10396 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10397 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10398 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10399 set_gdbarch_register_type (gdbarch, arm_register_type);
10400 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10402 /* This "info float" is FPA-specific. Use the generic version if we
10403 do not have FPA. */
10404 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10405 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10407 /* Internal <-> external register number maps. */
10408 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10409 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10411 set_gdbarch_register_name (gdbarch, arm_register_name);
10413 /* Returning results. */
10414 set_gdbarch_return_value (gdbarch, arm_return_value);
10417 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10419 /* Minsymbol frobbing. */
10420 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10421 set_gdbarch_coff_make_msymbol_special (gdbarch,
10422 arm_coff_make_msymbol_special);
10423 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10425 /* Thumb-2 IT block support. */
10426 set_gdbarch_adjust_breakpoint_address (gdbarch,
10427 arm_adjust_breakpoint_address);
10429 /* Virtual tables. */
10430 set_gdbarch_vbit_in_delta (gdbarch, 1);
10432 /* Hook in the ABI-specific overrides, if they have been registered. */
10433 gdbarch_init_osabi (info, gdbarch);
10435 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10437 /* Add some default predicates. */
10439 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
10440 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10441 dwarf2_append_unwinders (gdbarch);
10442 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10443 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10445 /* Now we have tuned the configuration, set a few final things,
10446 based on what the OS ABI has told us. */
10448 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10449 binaries are always marked. */
10450 if (tdep->arm_abi == ARM_ABI_AUTO)
10451 tdep->arm_abi = ARM_ABI_APCS;
10453 /* Watchpoints are not steppable. */
10454 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10456 /* We used to default to FPA for generic ARM, but almost nobody
10457 uses that now, and we now provide a way for the user to force
10458 the model. So default to the most useful variant. */
10459 if (tdep->fp_model == ARM_FLOAT_AUTO)
10460 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10462 if (tdep->jb_pc >= 0)
10463 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10465 /* Floating point sizes and format. */
10466 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10467 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10469 set_gdbarch_double_format
10470 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10471 set_gdbarch_long_double_format
10472 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10476 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10477 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10480 if (have_vfp_pseudos)
10482 /* NOTE: These are the only pseudo registers used by
10483 the ARM target at the moment. If more are added, a
10484 little more care in numbering will be needed. */
10486 int num_pseudos = 32;
10487 if (have_neon_pseudos)
10489 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10490 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10491 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10496 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10498 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10500 /* Override tdesc_register_type to adjust the types of VFP
10501 registers for NEON. */
10502 set_gdbarch_register_type (gdbarch, arm_register_type);
10505 /* Add standard register aliases. We add aliases even for those
10506 nanes which are used by the current architecture - it's simpler,
10507 and does no harm, since nothing ever lists user registers. */
10508 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10509 user_reg_add (gdbarch, arm_register_aliases[i].name,
10510 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10516 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10518 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10523 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10524 (unsigned long) tdep->lowest_pc);
10527 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10530 _initialize_arm_tdep (void)
10532 struct ui_file *stb;
10534 struct cmd_list_element *new_set, *new_show;
10535 const char *setname;
10536 const char *setdesc;
10537 const char *const *regnames;
10539 static char *helptext;
10540 char regdesc[1024], *rdptr = regdesc;
10541 size_t rest = sizeof (regdesc);
10543 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10545 arm_objfile_data_key
10546 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10548 /* Add ourselves to objfile event chain. */
10549 observer_attach_new_objfile (arm_exidx_new_objfile);
10551 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10553 /* Register an ELF OS ABI sniffer for ARM binaries. */
10554 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10555 bfd_target_elf_flavour,
10556 arm_elf_osabi_sniffer);
10558 /* Initialize the standard target descriptions. */
10559 initialize_tdesc_arm_with_m ();
10560 initialize_tdesc_arm_with_m_fpa_layout ();
10561 initialize_tdesc_arm_with_m_vfp_d16 ();
10562 initialize_tdesc_arm_with_iwmmxt ();
10563 initialize_tdesc_arm_with_vfpv2 ();
10564 initialize_tdesc_arm_with_vfpv3 ();
10565 initialize_tdesc_arm_with_neon ();
10567 /* Get the number of possible sets of register names defined in opcodes. */
10568 num_disassembly_options = get_arm_regname_num_options ();
10570 /* Add root prefix command for all "set arm"/"show arm" commands. */
10571 add_prefix_cmd ("arm", no_class, set_arm_command,
10572 _("Various ARM-specific commands."),
10573 &setarmcmdlist, "set arm ", 0, &setlist);
10575 add_prefix_cmd ("arm", no_class, show_arm_command,
10576 _("Various ARM-specific commands."),
10577 &showarmcmdlist, "show arm ", 0, &showlist);
10579 /* Sync the opcode insn printer with our register viewer. */
10580 parse_arm_disassembler_option ("reg-names-std");
10582 /* Initialize the array that will be passed to
10583 add_setshow_enum_cmd(). */
10584 valid_disassembly_styles = XNEWVEC (const char *,
10585 num_disassembly_options + 1);
10586 for (i = 0; i < num_disassembly_options; i++)
10588 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10589 valid_disassembly_styles[i] = setname;
10590 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10593 /* When we find the default names, tell the disassembler to use
10595 if (!strcmp (setname, "std"))
10597 disassembly_style = setname;
10598 set_arm_regname_option (i);
10601 /* Mark the end of valid options. */
10602 valid_disassembly_styles[num_disassembly_options] = NULL;
10604 /* Create the help text. */
10605 stb = mem_fileopen ();
10606 fprintf_unfiltered (stb, "%s%s%s",
10607 _("The valid values are:\n"),
10609 _("The default is \"std\"."));
10610 helptext = ui_file_xstrdup (stb, NULL);
10611 ui_file_delete (stb);
10613 add_setshow_enum_cmd("disassembler", no_class,
10614 valid_disassembly_styles, &disassembly_style,
10615 _("Set the disassembly style."),
10616 _("Show the disassembly style."),
10618 set_disassembly_style_sfunc,
10619 NULL, /* FIXME: i18n: The disassembly style is
10621 &setarmcmdlist, &showarmcmdlist);
10623 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10624 _("Set usage of ARM 32-bit mode."),
10625 _("Show usage of ARM 32-bit mode."),
10626 _("When off, a 26-bit PC will be used."),
10628 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10630 &setarmcmdlist, &showarmcmdlist);
10632 /* Add a command to allow the user to force the FPU model. */
10633 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10634 _("Set the floating point type."),
10635 _("Show the floating point type."),
10636 _("auto - Determine the FP typefrom the OS-ABI.\n\
10637 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10638 fpa - FPA co-processor (GCC compiled).\n\
10639 softvfp - Software FP with pure-endian doubles.\n\
10640 vfp - VFP co-processor."),
10641 set_fp_model_sfunc, show_fp_model,
10642 &setarmcmdlist, &showarmcmdlist);
10644 /* Add a command to allow the user to force the ABI. */
10645 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10647 _("Show the ABI."),
10648 NULL, arm_set_abi, arm_show_abi,
10649 &setarmcmdlist, &showarmcmdlist);
10651 /* Add two commands to allow the user to force the assumed
10653 add_setshow_enum_cmd ("fallback-mode", class_support,
10654 arm_mode_strings, &arm_fallback_mode_string,
10655 _("Set the mode assumed when symbols are unavailable."),
10656 _("Show the mode assumed when symbols are unavailable."),
10657 NULL, NULL, arm_show_fallback_mode,
10658 &setarmcmdlist, &showarmcmdlist);
10659 add_setshow_enum_cmd ("force-mode", class_support,
10660 arm_mode_strings, &arm_force_mode_string,
10661 _("Set the mode assumed even when symbols are available."),
10662 _("Show the mode assumed even when symbols are available."),
10663 NULL, NULL, arm_show_force_mode,
10664 &setarmcmdlist, &showarmcmdlist);
10666 /* Debugging flag. */
10667 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10668 _("Set ARM debugging."),
10669 _("Show ARM debugging."),
10670 _("When on, arm-specific debugging is enabled."),
10672 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10673 &setdebuglist, &showdebuglist);
10676 /* ARM-reversible process record data structures. */
10678 #define ARM_INSN_SIZE_BYTES 4
10679 #define THUMB_INSN_SIZE_BYTES 2
10680 #define THUMB2_INSN_SIZE_BYTES 4
10683 /* Position of the bit within a 32-bit ARM instruction
10684 that defines whether the instruction is a load or store. */
10685 #define INSN_S_L_BIT_NUM 20
10687 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10690 unsigned int reg_len = LENGTH; \
10693 REGS = XNEWVEC (uint32_t, reg_len); \
10694 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10699 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10702 unsigned int mem_len = LENGTH; \
10705 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10706 memcpy(&MEMS->len, &RECORD_BUF[0], \
10707 sizeof(struct arm_mem_r) * LENGTH); \
10712 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10713 #define INSN_RECORDED(ARM_RECORD) \
10714 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10716 /* ARM memory record structure. */
10719 uint32_t len; /* Record length. */
10720 uint32_t addr; /* Memory address. */
10723 /* ARM instruction record contains opcode of current insn
10724 and execution state (before entry to decode_insn()),
10725 contains list of to-be-modified registers and
10726 memory blocks (on return from decode_insn()). */
10728 typedef struct insn_decode_record_t
10730 struct gdbarch *gdbarch;
10731 struct regcache *regcache;
10732 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10733 uint32_t arm_insn; /* Should accommodate thumb. */
10734 uint32_t cond; /* Condition code. */
10735 uint32_t opcode; /* Insn opcode. */
10736 uint32_t decode; /* Insn decode bits. */
10737 uint32_t mem_rec_count; /* No of mem records. */
10738 uint32_t reg_rec_count; /* No of reg records. */
10739 uint32_t *arm_regs; /* Registers to be saved for this record. */
10740 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10741 } insn_decode_record;
10744 /* Checks ARM SBZ and SBO mandatory fields. */
10747 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10749 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10768 enum arm_record_result
10770 ARM_RECORD_SUCCESS = 0,
10771 ARM_RECORD_FAILURE = 1
10778 } arm_record_strx_t;
10789 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10790 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10793 struct regcache *reg_cache = arm_insn_r->regcache;
10794 ULONGEST u_regval[2]= {0};
10796 uint32_t reg_src1 = 0, reg_src2 = 0;
10797 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10798 uint32_t opcode1 = 0;
10800 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10801 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10802 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10805 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10807 /* 1) Handle misc store, immediate offset. */
10808 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10809 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10810 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10811 regcache_raw_read_unsigned (reg_cache, reg_src1,
10813 if (ARM_PC_REGNUM == reg_src1)
10815 /* If R15 was used as Rn, hence current PC+8. */
10816 u_regval[0] = u_regval[0] + 8;
10818 offset_8 = (immed_high << 4) | immed_low;
10819 /* Calculate target store address. */
10820 if (14 == arm_insn_r->opcode)
10822 tgt_mem_addr = u_regval[0] + offset_8;
10826 tgt_mem_addr = u_regval[0] - offset_8;
10828 if (ARM_RECORD_STRH == str_type)
10830 record_buf_mem[0] = 2;
10831 record_buf_mem[1] = tgt_mem_addr;
10832 arm_insn_r->mem_rec_count = 1;
10834 else if (ARM_RECORD_STRD == str_type)
10836 record_buf_mem[0] = 4;
10837 record_buf_mem[1] = tgt_mem_addr;
10838 record_buf_mem[2] = 4;
10839 record_buf_mem[3] = tgt_mem_addr + 4;
10840 arm_insn_r->mem_rec_count = 2;
10843 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10845 /* 2) Store, register offset. */
10847 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10849 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10850 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10851 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10852 if (15 == reg_src2)
10854 /* If R15 was used as Rn, hence current PC+8. */
10855 u_regval[0] = u_regval[0] + 8;
10857 /* Calculate target store address, Rn +/- Rm, register offset. */
10858 if (12 == arm_insn_r->opcode)
10860 tgt_mem_addr = u_regval[0] + u_regval[1];
10864 tgt_mem_addr = u_regval[1] - u_regval[0];
10866 if (ARM_RECORD_STRH == str_type)
10868 record_buf_mem[0] = 2;
10869 record_buf_mem[1] = tgt_mem_addr;
10870 arm_insn_r->mem_rec_count = 1;
10872 else if (ARM_RECORD_STRD == str_type)
10874 record_buf_mem[0] = 4;
10875 record_buf_mem[1] = tgt_mem_addr;
10876 record_buf_mem[2] = 4;
10877 record_buf_mem[3] = tgt_mem_addr + 4;
10878 arm_insn_r->mem_rec_count = 2;
10881 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10882 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10884 /* 3) Store, immediate pre-indexed. */
10885 /* 5) Store, immediate post-indexed. */
10886 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10887 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10888 offset_8 = (immed_high << 4) | immed_low;
10889 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10890 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10891 /* Calculate target store address, Rn +/- Rm, register offset. */
10892 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10894 tgt_mem_addr = u_regval[0] + offset_8;
10898 tgt_mem_addr = u_regval[0] - offset_8;
10900 if (ARM_RECORD_STRH == str_type)
10902 record_buf_mem[0] = 2;
10903 record_buf_mem[1] = tgt_mem_addr;
10904 arm_insn_r->mem_rec_count = 1;
10906 else if (ARM_RECORD_STRD == str_type)
10908 record_buf_mem[0] = 4;
10909 record_buf_mem[1] = tgt_mem_addr;
10910 record_buf_mem[2] = 4;
10911 record_buf_mem[3] = tgt_mem_addr + 4;
10912 arm_insn_r->mem_rec_count = 2;
10914 /* Record Rn also as it changes. */
10915 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10916 arm_insn_r->reg_rec_count = 1;
10918 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10919 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10921 /* 4) Store, register pre-indexed. */
10922 /* 6) Store, register post -indexed. */
10923 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10924 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10925 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10926 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10927 /* Calculate target store address, Rn +/- Rm, register offset. */
10928 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10930 tgt_mem_addr = u_regval[0] + u_regval[1];
10934 tgt_mem_addr = u_regval[1] - u_regval[0];
10936 if (ARM_RECORD_STRH == str_type)
10938 record_buf_mem[0] = 2;
10939 record_buf_mem[1] = tgt_mem_addr;
10940 arm_insn_r->mem_rec_count = 1;
10942 else if (ARM_RECORD_STRD == str_type)
10944 record_buf_mem[0] = 4;
10945 record_buf_mem[1] = tgt_mem_addr;
10946 record_buf_mem[2] = 4;
10947 record_buf_mem[3] = tgt_mem_addr + 4;
10948 arm_insn_r->mem_rec_count = 2;
10950 /* Record Rn also as it changes. */
10951 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10952 arm_insn_r->reg_rec_count = 1;
10957 /* Handling ARM extension space insns. */
10960 arm_record_extension_space (insn_decode_record *arm_insn_r)
10962 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10963 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10964 uint32_t record_buf[8], record_buf_mem[8];
10965 uint32_t reg_src1 = 0;
10966 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10967 struct regcache *reg_cache = arm_insn_r->regcache;
10968 ULONGEST u_regval = 0;
10970 gdb_assert (!INSN_RECORDED(arm_insn_r));
10971 /* Handle unconditional insn extension space. */
10973 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10974 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10975 if (arm_insn_r->cond)
10977 /* PLD has no affect on architectural state, it just affects
10979 if (5 == ((opcode1 & 0xE0) >> 5))
10982 record_buf[0] = ARM_PS_REGNUM;
10983 record_buf[1] = ARM_LR_REGNUM;
10984 arm_insn_r->reg_rec_count = 2;
10986 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10990 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10991 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10994 /* Undefined instruction on ARM V5; need to handle if later
10995 versions define it. */
10998 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10999 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
11000 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
11002 /* Handle arithmetic insn extension space. */
11003 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
11004 && !INSN_RECORDED(arm_insn_r))
11006 /* Handle MLA(S) and MUL(S). */
11007 if (0 <= insn_op1 && 3 >= insn_op1)
11009 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11010 record_buf[1] = ARM_PS_REGNUM;
11011 arm_insn_r->reg_rec_count = 2;
11013 else if (4 <= insn_op1 && 15 >= insn_op1)
11015 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
11016 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11017 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11018 record_buf[2] = ARM_PS_REGNUM;
11019 arm_insn_r->reg_rec_count = 3;
11023 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
11024 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
11025 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
11027 /* Handle control insn extension space. */
11029 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
11030 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
11032 if (!bit (arm_insn_r->arm_insn,25))
11034 if (!bits (arm_insn_r->arm_insn, 4, 7))
11036 if ((0 == insn_op1) || (2 == insn_op1))
11039 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11040 arm_insn_r->reg_rec_count = 1;
11042 else if (1 == insn_op1)
11044 /* CSPR is going to be changed. */
11045 record_buf[0] = ARM_PS_REGNUM;
11046 arm_insn_r->reg_rec_count = 1;
11048 else if (3 == insn_op1)
11050 /* SPSR is going to be changed. */
11051 /* We need to get SPSR value, which is yet to be done. */
11052 printf_unfiltered (_("Process record does not support "
11053 "instruction 0x%0x at address %s.\n"),
11054 arm_insn_r->arm_insn,
11055 paddress (arm_insn_r->gdbarch,
11056 arm_insn_r->this_addr));
11060 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
11065 record_buf[0] = ARM_PS_REGNUM;
11066 arm_insn_r->reg_rec_count = 1;
11068 else if (3 == insn_op1)
11071 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11072 arm_insn_r->reg_rec_count = 1;
11075 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
11078 record_buf[0] = ARM_PS_REGNUM;
11079 record_buf[1] = ARM_LR_REGNUM;
11080 arm_insn_r->reg_rec_count = 2;
11082 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
11084 /* QADD, QSUB, QDADD, QDSUB */
11085 record_buf[0] = ARM_PS_REGNUM;
11086 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11087 arm_insn_r->reg_rec_count = 2;
11089 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
11092 record_buf[0] = ARM_PS_REGNUM;
11093 record_buf[1] = ARM_LR_REGNUM;
11094 arm_insn_r->reg_rec_count = 2;
11096 /* Save SPSR also;how? */
11097 printf_unfiltered (_("Process record does not support "
11098 "instruction 0x%0x at address %s.\n"),
11099 arm_insn_r->arm_insn,
11100 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11103 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
11104 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
11105 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
11106 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
11109 if (0 == insn_op1 || 1 == insn_op1)
11111 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11112 /* We dont do optimization for SMULW<y> where we
11114 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11115 record_buf[1] = ARM_PS_REGNUM;
11116 arm_insn_r->reg_rec_count = 2;
11118 else if (2 == insn_op1)
11121 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11122 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11123 arm_insn_r->reg_rec_count = 2;
11125 else if (3 == insn_op1)
11128 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11129 arm_insn_r->reg_rec_count = 1;
11135 /* MSR : immediate form. */
11138 /* CSPR is going to be changed. */
11139 record_buf[0] = ARM_PS_REGNUM;
11140 arm_insn_r->reg_rec_count = 1;
11142 else if (3 == insn_op1)
11144 /* SPSR is going to be changed. */
11145 /* we need to get SPSR value, which is yet to be done */
11146 printf_unfiltered (_("Process record does not support "
11147 "instruction 0x%0x at address %s.\n"),
11148 arm_insn_r->arm_insn,
11149 paddress (arm_insn_r->gdbarch,
11150 arm_insn_r->this_addr));
11156 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
11157 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
11158 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
11160 /* Handle load/store insn extension space. */
11162 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
11163 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
11164 && !INSN_RECORDED(arm_insn_r))
11169 /* These insn, changes register and memory as well. */
11170 /* SWP or SWPB insn. */
11171 /* Get memory address given by Rn. */
11172 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11173 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11174 /* SWP insn ?, swaps word. */
11175 if (8 == arm_insn_r->opcode)
11177 record_buf_mem[0] = 4;
11181 /* SWPB insn, swaps only byte. */
11182 record_buf_mem[0] = 1;
11184 record_buf_mem[1] = u_regval;
11185 arm_insn_r->mem_rec_count = 1;
11186 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11187 arm_insn_r->reg_rec_count = 1;
11189 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11192 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11195 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11198 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11199 record_buf[1] = record_buf[0] + 1;
11200 arm_insn_r->reg_rec_count = 2;
11202 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11205 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11208 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
11210 /* LDRH, LDRSB, LDRSH. */
11211 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11212 arm_insn_r->reg_rec_count = 1;
11217 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
11218 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
11219 && !INSN_RECORDED(arm_insn_r))
11222 /* Handle coprocessor insn extension space. */
11225 /* To be done for ARMv5 and later; as of now we return -1. */
11227 printf_unfiltered (_("Process record does not support instruction x%0x "
11228 "at address %s.\n"),arm_insn_r->arm_insn,
11229 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11232 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11233 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11238 /* Handling opcode 000 insns. */
11241 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11243 struct regcache *reg_cache = arm_insn_r->regcache;
11244 uint32_t record_buf[8], record_buf_mem[8];
11245 ULONGEST u_regval[2] = {0};
11247 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11248 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11249 uint32_t opcode1 = 0;
11251 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11252 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11253 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11255 /* Data processing insn /multiply insn. */
11256 if (9 == arm_insn_r->decode
11257 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11258 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11260 /* Handle multiply instructions. */
11261 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11262 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11264 /* Handle MLA and MUL. */
11265 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11266 record_buf[1] = ARM_PS_REGNUM;
11267 arm_insn_r->reg_rec_count = 2;
11269 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11271 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11272 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11273 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11274 record_buf[2] = ARM_PS_REGNUM;
11275 arm_insn_r->reg_rec_count = 3;
11278 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11279 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11281 /* Handle misc load insns, as 20th bit (L = 1). */
11282 /* LDR insn has a capability to do branching, if
11283 MOV LR, PC is precceded by LDR insn having Rn as R15
11284 in that case, it emulates branch and link insn, and hence we
11285 need to save CSPR and PC as well. I am not sure this is right
11286 place; as opcode = 010 LDR insn make this happen, if R15 was
11288 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11289 if (15 != reg_dest)
11291 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11292 arm_insn_r->reg_rec_count = 1;
11296 record_buf[0] = reg_dest;
11297 record_buf[1] = ARM_PS_REGNUM;
11298 arm_insn_r->reg_rec_count = 2;
11301 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11302 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11303 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11304 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11306 /* Handle MSR insn. */
11307 if (9 == arm_insn_r->opcode)
11309 /* CSPR is going to be changed. */
11310 record_buf[0] = ARM_PS_REGNUM;
11311 arm_insn_r->reg_rec_count = 1;
11315 /* SPSR is going to be changed. */
11316 /* How to read SPSR value? */
11317 printf_unfiltered (_("Process record does not support instruction "
11318 "0x%0x at address %s.\n"),
11319 arm_insn_r->arm_insn,
11320 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11324 else if (9 == arm_insn_r->decode
11325 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11326 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11328 /* Handling SWP, SWPB. */
11329 /* These insn, changes register and memory as well. */
11330 /* SWP or SWPB insn. */
11332 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11333 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11334 /* SWP insn ?, swaps word. */
11335 if (8 == arm_insn_r->opcode)
11337 record_buf_mem[0] = 4;
11341 /* SWPB insn, swaps only byte. */
11342 record_buf_mem[0] = 1;
11344 record_buf_mem[1] = u_regval[0];
11345 arm_insn_r->mem_rec_count = 1;
11346 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11347 arm_insn_r->reg_rec_count = 1;
11349 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11350 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11352 /* Handle BLX, branch and link/exchange. */
11353 if (9 == arm_insn_r->opcode)
11355 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11356 and R14 stores the return address. */
11357 record_buf[0] = ARM_PS_REGNUM;
11358 record_buf[1] = ARM_LR_REGNUM;
11359 arm_insn_r->reg_rec_count = 2;
11362 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11364 /* Handle enhanced software breakpoint insn, BKPT. */
11365 /* CPSR is changed to be executed in ARM state, disabling normal
11366 interrupts, entering abort mode. */
11367 /* According to high vector configuration PC is set. */
11368 /* user hit breakpoint and type reverse, in
11369 that case, we need to go back with previous CPSR and
11370 Program Counter. */
11371 record_buf[0] = ARM_PS_REGNUM;
11372 record_buf[1] = ARM_LR_REGNUM;
11373 arm_insn_r->reg_rec_count = 2;
11375 /* Save SPSR also; how? */
11376 printf_unfiltered (_("Process record does not support instruction "
11377 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11378 paddress (arm_insn_r->gdbarch,
11379 arm_insn_r->this_addr));
11382 else if (11 == arm_insn_r->decode
11383 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11385 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11387 /* Handle str(x) insn */
11388 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11391 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11392 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11394 /* Handle BX, branch and link/exchange. */
11395 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11396 record_buf[0] = ARM_PS_REGNUM;
11397 arm_insn_r->reg_rec_count = 1;
11399 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11400 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11401 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11403 /* Count leading zeros: CLZ. */
11404 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11405 arm_insn_r->reg_rec_count = 1;
11407 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11408 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11409 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11410 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11413 /* Handle MRS insn. */
11414 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11415 arm_insn_r->reg_rec_count = 1;
11417 else if (arm_insn_r->opcode <= 15)
11419 /* Normal data processing insns. */
11420 /* Out of 11 shifter operands mode, all the insn modifies destination
11421 register, which is specified by 13-16 decode. */
11422 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11423 record_buf[1] = ARM_PS_REGNUM;
11424 arm_insn_r->reg_rec_count = 2;
11431 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11432 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11436 /* Handling opcode 001 insns. */
11439 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11441 uint32_t record_buf[8], record_buf_mem[8];
11443 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11444 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11446 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11447 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11448 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11451 /* Handle MSR insn. */
11452 if (9 == arm_insn_r->opcode)
11454 /* CSPR is going to be changed. */
11455 record_buf[0] = ARM_PS_REGNUM;
11456 arm_insn_r->reg_rec_count = 1;
11460 /* SPSR is going to be changed. */
11463 else if (arm_insn_r->opcode <= 15)
11465 /* Normal data processing insns. */
11466 /* Out of 11 shifter operands mode, all the insn modifies destination
11467 register, which is specified by 13-16 decode. */
11468 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11469 record_buf[1] = ARM_PS_REGNUM;
11470 arm_insn_r->reg_rec_count = 2;
11477 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11478 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11482 /* Handle ARM mode instructions with opcode 010. */
11485 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11487 struct regcache *reg_cache = arm_insn_r->regcache;
11489 uint32_t reg_base , reg_dest;
11490 uint32_t offset_12, tgt_mem_addr;
11491 uint32_t record_buf[8], record_buf_mem[8];
11492 unsigned char wback;
11495 /* Calculate wback. */
11496 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
11497 || (bit (arm_insn_r->arm_insn, 21) == 1);
11499 arm_insn_r->reg_rec_count = 0;
11500 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
11502 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11504 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11507 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11508 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
11510 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11511 preceeds a LDR instruction having R15 as reg_base, it
11512 emulates a branch and link instruction, and hence we need to save
11513 CPSR and PC as well. */
11514 if (ARM_PC_REGNUM == reg_dest)
11515 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
11517 /* If wback is true, also save the base register, which is going to be
11520 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11524 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11526 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11527 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
11529 /* Handle bit U. */
11530 if (bit (arm_insn_r->arm_insn, 23))
11532 /* U == 1: Add the offset. */
11533 tgt_mem_addr = (uint32_t) u_regval + offset_12;
11537 /* U == 0: subtract the offset. */
11538 tgt_mem_addr = (uint32_t) u_regval - offset_12;
11541 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11543 if (bit (arm_insn_r->arm_insn, 22))
11545 /* STRB and STRBT: 1 byte. */
11546 record_buf_mem[0] = 1;
11550 /* STR and STRT: 4 bytes. */
11551 record_buf_mem[0] = 4;
11554 /* Handle bit P. */
11555 if (bit (arm_insn_r->arm_insn, 24))
11556 record_buf_mem[1] = tgt_mem_addr;
11558 record_buf_mem[1] = (uint32_t) u_regval;
11560 arm_insn_r->mem_rec_count = 1;
11562 /* If wback is true, also save the base register, which is going to be
11565 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11568 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11569 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11573 /* Handling opcode 011 insns. */
11576 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11578 struct regcache *reg_cache = arm_insn_r->regcache;
11580 uint32_t shift_imm = 0;
11581 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11582 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11583 uint32_t record_buf[8], record_buf_mem[8];
11586 ULONGEST u_regval[2];
11588 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11589 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11591 /* Handle enhanced store insns and LDRD DSP insn,
11592 order begins according to addressing modes for store insns
11596 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11598 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11599 /* LDR insn has a capability to do branching, if
11600 MOV LR, PC is precedded by LDR insn having Rn as R15
11601 in that case, it emulates branch and link insn, and hence we
11602 need to save CSPR and PC as well. */
11603 if (15 != reg_dest)
11605 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11606 arm_insn_r->reg_rec_count = 1;
11610 record_buf[0] = reg_dest;
11611 record_buf[1] = ARM_PS_REGNUM;
11612 arm_insn_r->reg_rec_count = 2;
11617 if (! bits (arm_insn_r->arm_insn, 4, 11))
11619 /* Store insn, register offset and register pre-indexed,
11620 register post-indexed. */
11622 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11624 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11625 regcache_raw_read_unsigned (reg_cache, reg_src1
11627 regcache_raw_read_unsigned (reg_cache, reg_src2
11629 if (15 == reg_src2)
11631 /* If R15 was used as Rn, hence current PC+8. */
11632 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11633 u_regval[0] = u_regval[0] + 8;
11635 /* Calculate target store address, Rn +/- Rm, register offset. */
11637 if (bit (arm_insn_r->arm_insn, 23))
11639 tgt_mem_addr = u_regval[0] + u_regval[1];
11643 tgt_mem_addr = u_regval[1] - u_regval[0];
11646 switch (arm_insn_r->opcode)
11660 record_buf_mem[0] = 4;
11675 record_buf_mem[0] = 1;
11679 gdb_assert_not_reached ("no decoding pattern found");
11682 record_buf_mem[1] = tgt_mem_addr;
11683 arm_insn_r->mem_rec_count = 1;
11685 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11686 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11687 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11688 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11689 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11690 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11693 /* Rn is going to be changed in pre-indexed mode and
11694 post-indexed mode as well. */
11695 record_buf[0] = reg_src2;
11696 arm_insn_r->reg_rec_count = 1;
11701 /* Store insn, scaled register offset; scaled pre-indexed. */
11702 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11704 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11706 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11707 /* Get shift_imm. */
11708 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11709 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11710 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11711 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11712 /* Offset_12 used as shift. */
11716 /* Offset_12 used as index. */
11717 offset_12 = u_regval[0] << shift_imm;
11721 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11727 if (bit (u_regval[0], 31))
11729 offset_12 = 0xFFFFFFFF;
11738 /* This is arithmetic shift. */
11739 offset_12 = s_word >> shift_imm;
11746 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11748 /* Get C flag value and shift it by 31. */
11749 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11750 | (u_regval[0]) >> 1);
11754 offset_12 = (u_regval[0] >> shift_imm) \
11756 (sizeof(uint32_t) - shift_imm));
11761 gdb_assert_not_reached ("no decoding pattern found");
11765 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11767 if (bit (arm_insn_r->arm_insn, 23))
11769 tgt_mem_addr = u_regval[1] + offset_12;
11773 tgt_mem_addr = u_regval[1] - offset_12;
11776 switch (arm_insn_r->opcode)
11790 record_buf_mem[0] = 4;
11805 record_buf_mem[0] = 1;
11809 gdb_assert_not_reached ("no decoding pattern found");
11812 record_buf_mem[1] = tgt_mem_addr;
11813 arm_insn_r->mem_rec_count = 1;
11815 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11816 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11817 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11818 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11819 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11820 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11823 /* Rn is going to be changed in register scaled pre-indexed
11824 mode,and scaled post indexed mode. */
11825 record_buf[0] = reg_src2;
11826 arm_insn_r->reg_rec_count = 1;
11831 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11832 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11836 /* Handle ARM mode instructions with opcode 100. */
11839 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11841 struct regcache *reg_cache = arm_insn_r->regcache;
11842 uint32_t register_count = 0, register_bits;
11843 uint32_t reg_base, addr_mode;
11844 uint32_t record_buf[24], record_buf_mem[48];
11848 /* Fetch the list of registers. */
11849 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11850 arm_insn_r->reg_rec_count = 0;
11852 /* Fetch the base register that contains the address we are loading data
11854 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
11856 /* Calculate wback. */
11857 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
11859 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11861 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11863 /* Find out which registers are going to be loaded from memory. */
11864 while (register_bits)
11866 if (register_bits & 0x00000001)
11867 record_buf[arm_insn_r->reg_rec_count++] = register_count;
11868 register_bits = register_bits >> 1;
11873 /* If wback is true, also save the base register, which is going to be
11876 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11878 /* Save the CPSR register. */
11879 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
11883 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11885 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11887 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
11889 /* Find out how many registers are going to be stored to memory. */
11890 while (register_bits)
11892 if (register_bits & 0x00000001)
11894 register_bits = register_bits >> 1;
11899 /* STMDA (STMED): Decrement after. */
11901 record_buf_mem[1] = (uint32_t) u_regval
11902 - register_count * INT_REGISTER_SIZE + 4;
11904 /* STM (STMIA, STMEA): Increment after. */
11906 record_buf_mem[1] = (uint32_t) u_regval;
11908 /* STMDB (STMFD): Decrement before. */
11910 record_buf_mem[1] = (uint32_t) u_regval
11911 - register_count * INT_REGISTER_SIZE;
11913 /* STMIB (STMFA): Increment before. */
11915 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
11918 gdb_assert_not_reached ("no decoding pattern found");
11922 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
11923 arm_insn_r->mem_rec_count = 1;
11925 /* If wback is true, also save the base register, which is going to be
11928 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11931 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11932 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11936 /* Handling opcode 101 insns. */
11939 arm_record_b_bl (insn_decode_record *arm_insn_r)
11941 uint32_t record_buf[8];
11943 /* Handle B, BL, BLX(1) insns. */
11944 /* B simply branches so we do nothing here. */
11945 /* Note: BLX(1) doesnt fall here but instead it falls into
11946 extension space. */
11947 if (bit (arm_insn_r->arm_insn, 24))
11949 record_buf[0] = ARM_LR_REGNUM;
11950 arm_insn_r->reg_rec_count = 1;
11953 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11958 /* Handling opcode 110 insns. */
11961 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
11963 printf_unfiltered (_("Process record does not support instruction "
11964 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11965 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11970 /* Record handler for vector data transfer instructions. */
11973 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
11975 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
11976 uint32_t record_buf[4];
11978 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
11979 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
11980 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
11981 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
11982 bit_l = bit (arm_insn_r->arm_insn, 20);
11983 bit_c = bit (arm_insn_r->arm_insn, 8);
11985 /* Handle VMOV instruction. */
11986 if (bit_l && bit_c)
11988 record_buf[0] = reg_t;
11989 arm_insn_r->reg_rec_count = 1;
11991 else if (bit_l && !bit_c)
11993 /* Handle VMOV instruction. */
11994 if (bits_a == 0x00)
11996 if (bit (arm_insn_r->arm_insn, 20))
11997 record_buf[0] = reg_t;
11999 record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
12002 arm_insn_r->reg_rec_count = 1;
12004 /* Handle VMRS instruction. */
12005 else if (bits_a == 0x07)
12008 reg_t = ARM_PS_REGNUM;
12010 record_buf[0] = reg_t;
12011 arm_insn_r->reg_rec_count = 1;
12014 else if (!bit_l && !bit_c)
12016 /* Handle VMOV instruction. */
12017 if (bits_a == 0x00)
12019 if (bit (arm_insn_r->arm_insn, 20))
12020 record_buf[0] = reg_t;
12022 record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
12025 arm_insn_r->reg_rec_count = 1;
12027 /* Handle VMSR instruction. */
12028 else if (bits_a == 0x07)
12030 record_buf[0] = ARM_FPSCR_REGNUM;
12031 arm_insn_r->reg_rec_count = 1;
12034 else if (!bit_l && bit_c)
12036 /* Handle VMOV instruction. */
12037 if (!(bits_a & 0x04))
12039 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
12041 arm_insn_r->reg_rec_count = 1;
12043 /* Handle VDUP instruction. */
12046 if (bit (arm_insn_r->arm_insn, 21))
12048 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
12049 record_buf[0] = reg_v + ARM_D0_REGNUM;
12050 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
12051 arm_insn_r->reg_rec_count = 2;
12055 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
12056 record_buf[0] = reg_v + ARM_D0_REGNUM;
12057 arm_insn_r->reg_rec_count = 1;
12062 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
12066 /* Record handler for extension register load/store instructions. */
12069 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
12071 uint32_t opcode, single_reg;
12072 uint8_t op_vldm_vstm;
12073 uint32_t record_buf[8], record_buf_mem[128];
12074 ULONGEST u_regval = 0;
12076 struct regcache *reg_cache = arm_insn_r->regcache;
12077 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
12079 opcode = bits (arm_insn_r->arm_insn, 20, 24);
12080 single_reg = bit (arm_insn_r->arm_insn, 8);
12081 op_vldm_vstm = opcode & 0x1b;
12083 /* Handle VMOV instructions. */
12084 if ((opcode & 0x1e) == 0x04)
12086 if (bit (arm_insn_r->arm_insn, 4))
12088 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
12089 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
12090 arm_insn_r->reg_rec_count = 2;
12094 uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1)
12095 | bit (arm_insn_r->arm_insn, 5);
12099 record_buf[0] = num_regs + reg_m;
12100 record_buf[1] = num_regs + reg_m + 1;
12101 arm_insn_r->reg_rec_count = 2;
12105 record_buf[0] = reg_m + ARM_D0_REGNUM;
12106 arm_insn_r->reg_rec_count = 1;
12110 /* Handle VSTM and VPUSH instructions. */
12111 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
12112 || op_vldm_vstm == 0x12)
12114 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12115 uint32_t memory_index = 0;
12117 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
12118 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12119 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
12120 imm_off32 = imm_off8 << 24;
12121 memory_count = imm_off8;
12123 if (bit (arm_insn_r->arm_insn, 23))
12124 start_address = u_regval;
12126 start_address = u_regval - imm_off32;
12128 if (bit (arm_insn_r->arm_insn, 21))
12130 record_buf[0] = reg_rn;
12131 arm_insn_r->reg_rec_count = 1;
12134 while (memory_count > 0)
12138 record_buf_mem[memory_index] = start_address;
12139 record_buf_mem[memory_index + 1] = 4;
12140 start_address = start_address + 4;
12141 memory_index = memory_index + 2;
12145 record_buf_mem[memory_index] = start_address;
12146 record_buf_mem[memory_index + 1] = 4;
12147 record_buf_mem[memory_index + 2] = start_address + 4;
12148 record_buf_mem[memory_index + 3] = 4;
12149 start_address = start_address + 8;
12150 memory_index = memory_index + 4;
12154 arm_insn_r->mem_rec_count = (memory_index >> 1);
12156 /* Handle VLDM instructions. */
12157 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
12158 || op_vldm_vstm == 0x13)
12160 uint32_t reg_count, reg_vd;
12161 uint32_t reg_index = 0;
12163 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12164 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
12167 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
12169 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
12171 if (bit (arm_insn_r->arm_insn, 21))
12172 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
12174 while (reg_count > 0)
12177 record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1;
12179 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
12183 arm_insn_r->reg_rec_count = reg_index;
12185 /* VSTR Vector store register. */
12186 else if ((opcode & 0x13) == 0x10)
12188 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12189 uint32_t memory_index = 0;
12191 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
12192 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12193 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
12194 imm_off32 = imm_off8 << 24;
12195 memory_count = imm_off8;
12197 if (bit (arm_insn_r->arm_insn, 23))
12198 start_address = u_regval + imm_off32;
12200 start_address = u_regval - imm_off32;
12204 record_buf_mem[memory_index] = start_address;
12205 record_buf_mem[memory_index + 1] = 4;
12206 arm_insn_r->mem_rec_count = 1;
12210 record_buf_mem[memory_index] = start_address;
12211 record_buf_mem[memory_index + 1] = 4;
12212 record_buf_mem[memory_index + 2] = start_address + 4;
12213 record_buf_mem[memory_index + 3] = 4;
12214 arm_insn_r->mem_rec_count = 2;
12217 /* VLDR Vector load register. */
12218 else if ((opcode & 0x13) == 0x11)
12220 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12224 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
12225 record_buf[0] = ARM_D0_REGNUM + reg_vd;
12229 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
12230 record_buf[0] = num_regs + reg_vd;
12232 arm_insn_r->reg_rec_count = 1;
12235 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
12236 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
12240 /* Record handler for arm/thumb mode VFP data processing instructions. */
12243 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
12245 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12246 uint32_t record_buf[4];
12247 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
12248 enum insn_types curr_insn_type = INSN_INV;
12250 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12251 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
12252 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
12253 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
12254 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
12255 bit_d = bit (arm_insn_r->arm_insn, 22);
12256 opc1 = opc1 & 0x04;
12258 /* Handle VMLA, VMLS. */
12261 if (bit (arm_insn_r->arm_insn, 10))
12263 if (bit (arm_insn_r->arm_insn, 6))
12264 curr_insn_type = INSN_T0;
12266 curr_insn_type = INSN_T1;
12271 curr_insn_type = INSN_T1;
12273 curr_insn_type = INSN_T2;
12276 /* Handle VNMLA, VNMLS, VNMUL. */
12277 else if (opc1 == 0x01)
12280 curr_insn_type = INSN_T1;
12282 curr_insn_type = INSN_T2;
12285 else if (opc1 == 0x02 && !(opc3 & 0x01))
12287 if (bit (arm_insn_r->arm_insn, 10))
12289 if (bit (arm_insn_r->arm_insn, 6))
12290 curr_insn_type = INSN_T0;
12292 curr_insn_type = INSN_T1;
12297 curr_insn_type = INSN_T1;
12299 curr_insn_type = INSN_T2;
12302 /* Handle VADD, VSUB. */
12303 else if (opc1 == 0x03)
12305 if (!bit (arm_insn_r->arm_insn, 9))
12307 if (bit (arm_insn_r->arm_insn, 6))
12308 curr_insn_type = INSN_T0;
12310 curr_insn_type = INSN_T1;
12315 curr_insn_type = INSN_T1;
12317 curr_insn_type = INSN_T2;
12321 else if (opc1 == 0x0b)
12324 curr_insn_type = INSN_T1;
12326 curr_insn_type = INSN_T2;
12328 /* Handle all other vfp data processing instructions. */
12329 else if (opc1 == 0x0b)
12332 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
12334 if (bit (arm_insn_r->arm_insn, 4))
12336 if (bit (arm_insn_r->arm_insn, 6))
12337 curr_insn_type = INSN_T0;
12339 curr_insn_type = INSN_T1;
12344 curr_insn_type = INSN_T1;
12346 curr_insn_type = INSN_T2;
12349 /* Handle VNEG and VABS. */
12350 else if ((opc2 == 0x01 && opc3 == 0x01)
12351 || (opc2 == 0x00 && opc3 == 0x03))
12353 if (!bit (arm_insn_r->arm_insn, 11))
12355 if (bit (arm_insn_r->arm_insn, 6))
12356 curr_insn_type = INSN_T0;
12358 curr_insn_type = INSN_T1;
12363 curr_insn_type = INSN_T1;
12365 curr_insn_type = INSN_T2;
12368 /* Handle VSQRT. */
12369 else if (opc2 == 0x01 && opc3 == 0x03)
12372 curr_insn_type = INSN_T1;
12374 curr_insn_type = INSN_T2;
12377 else if (opc2 == 0x07 && opc3 == 0x03)
12380 curr_insn_type = INSN_T1;
12382 curr_insn_type = INSN_T2;
12384 else if (opc3 & 0x01)
12387 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
12389 if (!bit (arm_insn_r->arm_insn, 18))
12390 curr_insn_type = INSN_T2;
12394 curr_insn_type = INSN_T1;
12396 curr_insn_type = INSN_T2;
12400 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
12403 curr_insn_type = INSN_T1;
12405 curr_insn_type = INSN_T2;
12407 /* Handle VCVTB, VCVTT. */
12408 else if ((opc2 & 0x0e) == 0x02)
12409 curr_insn_type = INSN_T2;
12410 /* Handle VCMP, VCMPE. */
12411 else if ((opc2 & 0x0e) == 0x04)
12412 curr_insn_type = INSN_T3;
12416 switch (curr_insn_type)
12419 reg_vd = reg_vd | (bit_d << 4);
12420 record_buf[0] = reg_vd + ARM_D0_REGNUM;
12421 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
12422 arm_insn_r->reg_rec_count = 2;
12426 reg_vd = reg_vd | (bit_d << 4);
12427 record_buf[0] = reg_vd + ARM_D0_REGNUM;
12428 arm_insn_r->reg_rec_count = 1;
12432 reg_vd = (reg_vd << 1) | bit_d;
12433 record_buf[0] = reg_vd + ARM_D0_REGNUM;
12434 arm_insn_r->reg_rec_count = 1;
12438 record_buf[0] = ARM_FPSCR_REGNUM;
12439 arm_insn_r->reg_rec_count = 1;
12443 gdb_assert_not_reached ("no decoding pattern found");
12447 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
12451 /* Handling opcode 110 insns. */
12454 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
12456 uint32_t op, op1, op1_sbit, op1_ebit, coproc;
12458 coproc = bits (arm_insn_r->arm_insn, 8, 11);
12459 op1 = bits (arm_insn_r->arm_insn, 20, 25);
12460 op1_ebit = bit (arm_insn_r->arm_insn, 20);
12462 if ((coproc & 0x0e) == 0x0a)
12464 /* Handle extension register ld/st instructions. */
12466 return arm_record_exreg_ld_st_insn (arm_insn_r);
12468 /* 64-bit transfers between arm core and extension registers. */
12469 if ((op1 & 0x3e) == 0x04)
12470 return arm_record_exreg_ld_st_insn (arm_insn_r);
12474 /* Handle coprocessor ld/st instructions. */
12479 return arm_record_unsupported_insn (arm_insn_r);
12482 return arm_record_unsupported_insn (arm_insn_r);
12485 /* Move to coprocessor from two arm core registers. */
12487 return arm_record_unsupported_insn (arm_insn_r);
12489 /* Move to two arm core registers from coprocessor. */
12494 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
12495 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
12496 arm_insn_r->reg_rec_count = 2;
12498 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
12502 return arm_record_unsupported_insn (arm_insn_r);
12505 /* Handling opcode 111 insns. */
12508 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
12510 uint32_t op, op1_sbit, op1_ebit, coproc;
12511 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
12512 struct regcache *reg_cache = arm_insn_r->regcache;
12513 ULONGEST u_regval = 0;
12515 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
12516 coproc = bits (arm_insn_r->arm_insn, 8, 11);
12517 op1_sbit = bit (arm_insn_r->arm_insn, 24);
12518 op1_ebit = bit (arm_insn_r->arm_insn, 20);
12519 op = bit (arm_insn_r->arm_insn, 4);
12521 /* Handle arm SWI/SVC system call instructions. */
12524 if (tdep->arm_syscall_record != NULL)
12526 ULONGEST svc_operand, svc_number;
12528 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
12530 if (svc_operand) /* OABI. */
12531 svc_number = svc_operand - 0x900000;
12533 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
12535 return tdep->arm_syscall_record (reg_cache, svc_number);
12539 printf_unfiltered (_("no syscall record support\n"));
12544 if ((coproc & 0x0e) == 0x0a)
12546 /* VFP data-processing instructions. */
12547 if (!op1_sbit && !op)
12548 return arm_record_vfp_data_proc_insn (arm_insn_r);
12550 /* Advanced SIMD, VFP instructions. */
12551 if (!op1_sbit && op)
12552 return arm_record_vdata_transfer_insn (arm_insn_r);
12556 /* Coprocessor data operations. */
12557 if (!op1_sbit && !op)
12558 return arm_record_unsupported_insn (arm_insn_r);
12560 /* Move to Coprocessor from ARM core register. */
12561 if (!op1_sbit && !op1_ebit && op)
12562 return arm_record_unsupported_insn (arm_insn_r);
12564 /* Move to arm core register from coprocessor. */
12565 if (!op1_sbit && op1_ebit && op)
12567 uint32_t record_buf[1];
12569 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
12570 if (record_buf[0] == 15)
12571 record_buf[0] = ARM_PS_REGNUM;
12573 arm_insn_r->reg_rec_count = 1;
12574 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
12580 return arm_record_unsupported_insn (arm_insn_r);
12583 /* Handling opcode 000 insns. */
12586 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
12588 uint32_t record_buf[8];
12589 uint32_t reg_src1 = 0;
12591 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12593 record_buf[0] = ARM_PS_REGNUM;
12594 record_buf[1] = reg_src1;
12595 thumb_insn_r->reg_rec_count = 2;
12597 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12603 /* Handling opcode 001 insns. */
12606 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
12608 uint32_t record_buf[8];
12609 uint32_t reg_src1 = 0;
12611 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12613 record_buf[0] = ARM_PS_REGNUM;
12614 record_buf[1] = reg_src1;
12615 thumb_insn_r->reg_rec_count = 2;
12617 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12622 /* Handling opcode 010 insns. */
12625 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
12627 struct regcache *reg_cache = thumb_insn_r->regcache;
12628 uint32_t record_buf[8], record_buf_mem[8];
12630 uint32_t reg_src1 = 0, reg_src2 = 0;
12631 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12633 ULONGEST u_regval[2] = {0};
12635 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
12637 if (bit (thumb_insn_r->arm_insn, 12))
12639 /* Handle load/store register offset. */
12640 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
12641 if (opcode2 >= 12 && opcode2 <= 15)
12643 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12644 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
12645 record_buf[0] = reg_src1;
12646 thumb_insn_r->reg_rec_count = 1;
12648 else if (opcode2 >= 8 && opcode2 <= 10)
12650 /* STR(2), STRB(2), STRH(2) . */
12651 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12652 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
12653 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
12654 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
12656 record_buf_mem[0] = 4; /* STR (2). */
12657 else if (10 == opcode2)
12658 record_buf_mem[0] = 1; /* STRB (2). */
12659 else if (9 == opcode2)
12660 record_buf_mem[0] = 2; /* STRH (2). */
12661 record_buf_mem[1] = u_regval[0] + u_regval[1];
12662 thumb_insn_r->mem_rec_count = 1;
12665 else if (bit (thumb_insn_r->arm_insn, 11))
12667 /* Handle load from literal pool. */
12669 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12670 record_buf[0] = reg_src1;
12671 thumb_insn_r->reg_rec_count = 1;
12675 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
12676 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
12677 if ((3 == opcode2) && (!opcode3))
12679 /* Branch with exchange. */
12680 record_buf[0] = ARM_PS_REGNUM;
12681 thumb_insn_r->reg_rec_count = 1;
12685 /* Format 8; special data processing insns. */
12686 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12687 record_buf[0] = ARM_PS_REGNUM;
12688 record_buf[1] = reg_src1;
12689 thumb_insn_r->reg_rec_count = 2;
12694 /* Format 5; data processing insns. */
12695 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12696 if (bit (thumb_insn_r->arm_insn, 7))
12698 reg_src1 = reg_src1 + 8;
12700 record_buf[0] = ARM_PS_REGNUM;
12701 record_buf[1] = reg_src1;
12702 thumb_insn_r->reg_rec_count = 2;
12705 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12706 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12712 /* Handling opcode 001 insns. */
12715 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
12717 struct regcache *reg_cache = thumb_insn_r->regcache;
12718 uint32_t record_buf[8], record_buf_mem[8];
12720 uint32_t reg_src1 = 0;
12721 uint32_t opcode = 0, immed_5 = 0;
12723 ULONGEST u_regval = 0;
12725 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12730 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12731 record_buf[0] = reg_src1;
12732 thumb_insn_r->reg_rec_count = 1;
12737 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12738 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12739 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12740 record_buf_mem[0] = 4;
12741 record_buf_mem[1] = u_regval + (immed_5 * 4);
12742 thumb_insn_r->mem_rec_count = 1;
12745 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12746 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12752 /* Handling opcode 100 insns. */
12755 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12757 struct regcache *reg_cache = thumb_insn_r->regcache;
12758 uint32_t record_buf[8], record_buf_mem[8];
12760 uint32_t reg_src1 = 0;
12761 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12763 ULONGEST u_regval = 0;
12765 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12770 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12771 record_buf[0] = reg_src1;
12772 thumb_insn_r->reg_rec_count = 1;
12774 else if (1 == opcode)
12777 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12778 record_buf[0] = reg_src1;
12779 thumb_insn_r->reg_rec_count = 1;
12781 else if (2 == opcode)
12784 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12785 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12786 record_buf_mem[0] = 4;
12787 record_buf_mem[1] = u_regval + (immed_8 * 4);
12788 thumb_insn_r->mem_rec_count = 1;
12790 else if (0 == opcode)
12793 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12794 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12795 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12796 record_buf_mem[0] = 2;
12797 record_buf_mem[1] = u_regval + (immed_5 * 2);
12798 thumb_insn_r->mem_rec_count = 1;
12801 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12802 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12808 /* Handling opcode 101 insns. */
12811 thumb_record_misc (insn_decode_record *thumb_insn_r)
12813 struct regcache *reg_cache = thumb_insn_r->regcache;
12815 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12816 uint32_t register_bits = 0, register_count = 0;
12817 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12818 uint32_t record_buf[24], record_buf_mem[48];
12821 ULONGEST u_regval = 0;
12823 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12824 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12825 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12830 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12831 while (register_bits)
12833 if (register_bits & 0x00000001)
12834 record_buf[index++] = register_count;
12835 register_bits = register_bits >> 1;
12838 record_buf[index++] = ARM_PS_REGNUM;
12839 record_buf[index++] = ARM_SP_REGNUM;
12840 thumb_insn_r->reg_rec_count = index;
12842 else if (10 == opcode2)
12845 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12846 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12847 while (register_bits)
12849 if (register_bits & 0x00000001)
12851 register_bits = register_bits >> 1;
12853 start_address = u_regval - \
12854 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12855 thumb_insn_r->mem_rec_count = register_count;
12856 while (register_count)
12858 record_buf_mem[(register_count * 2) - 1] = start_address;
12859 record_buf_mem[(register_count * 2) - 2] = 4;
12860 start_address = start_address + 4;
12863 record_buf[0] = ARM_SP_REGNUM;
12864 thumb_insn_r->reg_rec_count = 1;
12866 else if (0x1E == opcode1)
12869 /* Handle enhanced software breakpoint insn, BKPT. */
12870 /* CPSR is changed to be executed in ARM state, disabling normal
12871 interrupts, entering abort mode. */
12872 /* According to high vector configuration PC is set. */
12873 /* User hits breakpoint and type reverse, in that case, we need to go back with
12874 previous CPSR and Program Counter. */
12875 record_buf[0] = ARM_PS_REGNUM;
12876 record_buf[1] = ARM_LR_REGNUM;
12877 thumb_insn_r->reg_rec_count = 2;
12878 /* We need to save SPSR value, which is not yet done. */
12879 printf_unfiltered (_("Process record does not support instruction "
12880 "0x%0x at address %s.\n"),
12881 thumb_insn_r->arm_insn,
12882 paddress (thumb_insn_r->gdbarch,
12883 thumb_insn_r->this_addr));
12886 else if ((0 == opcode) || (1 == opcode))
12888 /* ADD(5), ADD(6). */
12889 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12890 record_buf[0] = reg_src1;
12891 thumb_insn_r->reg_rec_count = 1;
12893 else if (2 == opcode)
12895 /* ADD(7), SUB(4). */
12896 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12897 record_buf[0] = ARM_SP_REGNUM;
12898 thumb_insn_r->reg_rec_count = 1;
12901 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12902 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12908 /* Handling opcode 110 insns. */
12911 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12913 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12914 struct regcache *reg_cache = thumb_insn_r->regcache;
12916 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12917 uint32_t reg_src1 = 0;
12918 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12919 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12920 uint32_t record_buf[24], record_buf_mem[48];
12922 ULONGEST u_regval = 0;
12924 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12925 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12931 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12933 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12934 while (register_bits)
12936 if (register_bits & 0x00000001)
12937 record_buf[index++] = register_count;
12938 register_bits = register_bits >> 1;
12941 record_buf[index++] = reg_src1;
12942 thumb_insn_r->reg_rec_count = index;
12944 else if (0 == opcode2)
12946 /* It handles both STMIA. */
12947 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12949 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12950 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12951 while (register_bits)
12953 if (register_bits & 0x00000001)
12955 register_bits = register_bits >> 1;
12957 start_address = u_regval;
12958 thumb_insn_r->mem_rec_count = register_count;
12959 while (register_count)
12961 record_buf_mem[(register_count * 2) - 1] = start_address;
12962 record_buf_mem[(register_count * 2) - 2] = 4;
12963 start_address = start_address + 4;
12967 else if (0x1F == opcode1)
12969 /* Handle arm syscall insn. */
12970 if (tdep->arm_syscall_record != NULL)
12972 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
12973 ret = tdep->arm_syscall_record (reg_cache, u_regval);
12977 printf_unfiltered (_("no syscall record support\n"));
12982 /* B (1), conditional branch is automatically taken care in process_record,
12983 as PC is saved there. */
12985 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12986 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12992 /* Handling opcode 111 insns. */
12995 thumb_record_branch (insn_decode_record *thumb_insn_r)
12997 uint32_t record_buf[8];
12998 uint32_t bits_h = 0;
13000 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
13002 if (2 == bits_h || 3 == bits_h)
13005 record_buf[0] = ARM_LR_REGNUM;
13006 thumb_insn_r->reg_rec_count = 1;
13008 else if (1 == bits_h)
13011 record_buf[0] = ARM_PS_REGNUM;
13012 record_buf[1] = ARM_LR_REGNUM;
13013 thumb_insn_r->reg_rec_count = 2;
13016 /* B(2) is automatically taken care in process_record, as PC is
13019 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
13024 /* Handler for thumb2 load/store multiple instructions. */
13027 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
13029 struct regcache *reg_cache = thumb2_insn_r->regcache;
13031 uint32_t reg_rn, op;
13032 uint32_t register_bits = 0, register_count = 0;
13033 uint32_t index = 0, start_address = 0;
13034 uint32_t record_buf[24], record_buf_mem[48];
13036 ULONGEST u_regval = 0;
13038 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13039 op = bits (thumb2_insn_r->arm_insn, 23, 24);
13041 if (0 == op || 3 == op)
13043 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
13045 /* Handle RFE instruction. */
13046 record_buf[0] = ARM_PS_REGNUM;
13047 thumb2_insn_r->reg_rec_count = 1;
13051 /* Handle SRS instruction after reading banked SP. */
13052 return arm_record_unsupported_insn (thumb2_insn_r);
13055 else if (1 == op || 2 == op)
13057 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
13059 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13060 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
13061 while (register_bits)
13063 if (register_bits & 0x00000001)
13064 record_buf[index++] = register_count;
13067 register_bits = register_bits >> 1;
13069 record_buf[index++] = reg_rn;
13070 record_buf[index++] = ARM_PS_REGNUM;
13071 thumb2_insn_r->reg_rec_count = index;
13075 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13076 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
13077 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
13078 while (register_bits)
13080 if (register_bits & 0x00000001)
13083 register_bits = register_bits >> 1;
13088 /* Start address calculation for LDMDB/LDMEA. */
13089 start_address = u_regval;
13093 /* Start address calculation for LDMDB/LDMEA. */
13094 start_address = u_regval - register_count * 4;
13097 thumb2_insn_r->mem_rec_count = register_count;
13098 while (register_count)
13100 record_buf_mem[register_count * 2 - 1] = start_address;
13101 record_buf_mem[register_count * 2 - 2] = 4;
13102 start_address = start_address + 4;
13105 record_buf[0] = reg_rn;
13106 record_buf[1] = ARM_PS_REGNUM;
13107 thumb2_insn_r->reg_rec_count = 2;
13111 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13113 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13115 return ARM_RECORD_SUCCESS;
13118 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13122 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
13124 struct regcache *reg_cache = thumb2_insn_r->regcache;
13126 uint32_t reg_rd, reg_rn, offset_imm;
13127 uint32_t reg_dest1, reg_dest2;
13128 uint32_t address, offset_addr;
13129 uint32_t record_buf[8], record_buf_mem[8];
13130 uint32_t op1, op2, op3;
13133 ULONGEST u_regval[2];
13135 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
13136 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
13137 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
13139 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
13141 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
13143 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
13144 record_buf[0] = reg_dest1;
13145 record_buf[1] = ARM_PS_REGNUM;
13146 thumb2_insn_r->reg_rec_count = 2;
13149 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
13151 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
13152 record_buf[2] = reg_dest2;
13153 thumb2_insn_r->reg_rec_count = 3;
13158 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13159 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
13161 if (0 == op1 && 0 == op2)
13163 /* Handle STREX. */
13164 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
13165 address = u_regval[0] + (offset_imm * 4);
13166 record_buf_mem[0] = 4;
13167 record_buf_mem[1] = address;
13168 thumb2_insn_r->mem_rec_count = 1;
13169 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
13170 record_buf[0] = reg_rd;
13171 thumb2_insn_r->reg_rec_count = 1;
13173 else if (1 == op1 && 0 == op2)
13175 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
13176 record_buf[0] = reg_rd;
13177 thumb2_insn_r->reg_rec_count = 1;
13178 address = u_regval[0];
13179 record_buf_mem[1] = address;
13183 /* Handle STREXB. */
13184 record_buf_mem[0] = 1;
13185 thumb2_insn_r->mem_rec_count = 1;
13189 /* Handle STREXH. */
13190 record_buf_mem[0] = 2 ;
13191 thumb2_insn_r->mem_rec_count = 1;
13195 /* Handle STREXD. */
13196 address = u_regval[0];
13197 record_buf_mem[0] = 4;
13198 record_buf_mem[2] = 4;
13199 record_buf_mem[3] = address + 4;
13200 thumb2_insn_r->mem_rec_count = 2;
13205 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
13207 if (bit (thumb2_insn_r->arm_insn, 24))
13209 if (bit (thumb2_insn_r->arm_insn, 23))
13210 offset_addr = u_regval[0] + (offset_imm * 4);
13212 offset_addr = u_regval[0] - (offset_imm * 4);
13214 address = offset_addr;
13217 address = u_regval[0];
13219 record_buf_mem[0] = 4;
13220 record_buf_mem[1] = address;
13221 record_buf_mem[2] = 4;
13222 record_buf_mem[3] = address + 4;
13223 thumb2_insn_r->mem_rec_count = 2;
13224 record_buf[0] = reg_rn;
13225 thumb2_insn_r->reg_rec_count = 1;
13229 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13231 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13233 return ARM_RECORD_SUCCESS;
13236 /* Handler for thumb2 data processing (shift register and modified immediate)
13240 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
13242 uint32_t reg_rd, op;
13243 uint32_t record_buf[8];
13245 op = bits (thumb2_insn_r->arm_insn, 21, 24);
13246 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
13248 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
13250 record_buf[0] = ARM_PS_REGNUM;
13251 thumb2_insn_r->reg_rec_count = 1;
13255 record_buf[0] = reg_rd;
13256 record_buf[1] = ARM_PS_REGNUM;
13257 thumb2_insn_r->reg_rec_count = 2;
13260 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13262 return ARM_RECORD_SUCCESS;
13265 /* Generic handler for thumb2 instructions which effect destination and PS
13269 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
13272 uint32_t record_buf[8];
13274 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
13276 record_buf[0] = reg_rd;
13277 record_buf[1] = ARM_PS_REGNUM;
13278 thumb2_insn_r->reg_rec_count = 2;
13280 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13282 return ARM_RECORD_SUCCESS;
13285 /* Handler for thumb2 branch and miscellaneous control instructions. */
13288 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
13290 uint32_t op, op1, op2;
13291 uint32_t record_buf[8];
13293 op = bits (thumb2_insn_r->arm_insn, 20, 26);
13294 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
13295 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
13297 /* Handle MSR insn. */
13298 if (!(op1 & 0x2) && 0x38 == op)
13302 /* CPSR is going to be changed. */
13303 record_buf[0] = ARM_PS_REGNUM;
13304 thumb2_insn_r->reg_rec_count = 1;
13308 arm_record_unsupported_insn(thumb2_insn_r);
13312 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
13315 record_buf[0] = ARM_PS_REGNUM;
13316 record_buf[1] = ARM_LR_REGNUM;
13317 thumb2_insn_r->reg_rec_count = 2;
13320 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13322 return ARM_RECORD_SUCCESS;
13325 /* Handler for thumb2 store single data item instructions. */
13328 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
13330 struct regcache *reg_cache = thumb2_insn_r->regcache;
13332 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
13333 uint32_t address, offset_addr;
13334 uint32_t record_buf[8], record_buf_mem[8];
13337 ULONGEST u_regval[2];
13339 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
13340 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
13341 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13342 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
13344 if (bit (thumb2_insn_r->arm_insn, 23))
13347 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
13348 offset_addr = u_regval[0] + offset_imm;
13349 address = offset_addr;
13354 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
13356 /* Handle STRB (register). */
13357 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
13358 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
13359 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
13360 offset_addr = u_regval[1] << shift_imm;
13361 address = u_regval[0] + offset_addr;
13365 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
13366 if (bit (thumb2_insn_r->arm_insn, 10))
13368 if (bit (thumb2_insn_r->arm_insn, 9))
13369 offset_addr = u_regval[0] + offset_imm;
13371 offset_addr = u_regval[0] - offset_imm;
13373 address = offset_addr;
13376 address = u_regval[0];
13382 /* Store byte instructions. */
13385 record_buf_mem[0] = 1;
13387 /* Store half word instructions. */
13390 record_buf_mem[0] = 2;
13392 /* Store word instructions. */
13395 record_buf_mem[0] = 4;
13399 gdb_assert_not_reached ("no decoding pattern found");
13403 record_buf_mem[1] = address;
13404 thumb2_insn_r->mem_rec_count = 1;
13405 record_buf[0] = reg_rn;
13406 thumb2_insn_r->reg_rec_count = 1;
13408 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13410 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13412 return ARM_RECORD_SUCCESS;
13415 /* Handler for thumb2 load memory hints instructions. */
13418 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
13420 uint32_t record_buf[8];
13421 uint32_t reg_rt, reg_rn;
13423 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
13424 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13426 if (ARM_PC_REGNUM != reg_rt)
13428 record_buf[0] = reg_rt;
13429 record_buf[1] = reg_rn;
13430 record_buf[2] = ARM_PS_REGNUM;
13431 thumb2_insn_r->reg_rec_count = 3;
13433 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13435 return ARM_RECORD_SUCCESS;
13438 return ARM_RECORD_FAILURE;
13441 /* Handler for thumb2 load word instructions. */
13444 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
13446 uint32_t opcode1 = 0, opcode2 = 0;
13447 uint32_t record_buf[8];
13449 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
13450 record_buf[1] = ARM_PS_REGNUM;
13451 thumb2_insn_r->reg_rec_count = 2;
13453 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13455 return ARM_RECORD_SUCCESS;
13458 /* Handler for thumb2 long multiply, long multiply accumulate, and
13459 divide instructions. */
13462 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
13464 uint32_t opcode1 = 0, opcode2 = 0;
13465 uint32_t record_buf[8];
13466 uint32_t reg_src1 = 0;
13468 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
13469 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
13471 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
13473 /* Handle SMULL, UMULL, SMULAL. */
13474 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13475 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
13476 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
13477 record_buf[2] = ARM_PS_REGNUM;
13478 thumb2_insn_r->reg_rec_count = 3;
13480 else if (1 == opcode1 || 3 == opcode2)
13482 /* Handle SDIV and UDIV. */
13483 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
13484 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
13485 record_buf[2] = ARM_PS_REGNUM;
13486 thumb2_insn_r->reg_rec_count = 3;
13489 return ARM_RECORD_FAILURE;
13491 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13493 return ARM_RECORD_SUCCESS;
13496 /* Record handler for thumb32 coprocessor instructions. */
13499 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
13501 if (bit (thumb2_insn_r->arm_insn, 25))
13502 return arm_record_coproc_data_proc (thumb2_insn_r);
13504 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
13507 /* Record handler for advance SIMD structure load/store instructions. */
13510 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
13512 struct regcache *reg_cache = thumb2_insn_r->regcache;
13513 uint32_t l_bit, a_bit, b_bits;
13514 uint32_t record_buf[128], record_buf_mem[128];
13515 uint32_t reg_rn, reg_vd, address, f_esize, f_elem;
13516 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
13519 l_bit = bit (thumb2_insn_r->arm_insn, 21);
13520 a_bit = bit (thumb2_insn_r->arm_insn, 23);
13521 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
13522 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
13523 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
13524 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
13525 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
13526 f_esize = 8 * f_ebytes;
13527 f_elem = 8 / f_ebytes;
13531 ULONGEST u_regval = 0;
13532 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
13533 address = u_regval;
13538 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
13540 if (b_bits == 0x07)
13542 else if (b_bits == 0x0a)
13544 else if (b_bits == 0x06)
13546 else if (b_bits == 0x02)
13551 for (index_r = 0; index_r < bf_regs; index_r++)
13553 for (index_e = 0; index_e < f_elem; index_e++)
13555 record_buf_mem[index_m++] = f_ebytes;
13556 record_buf_mem[index_m++] = address;
13557 address = address + f_ebytes;
13558 thumb2_insn_r->mem_rec_count += 1;
13563 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
13565 if (b_bits == 0x09 || b_bits == 0x08)
13567 else if (b_bits == 0x03)
13572 for (index_r = 0; index_r < bf_regs; index_r++)
13573 for (index_e = 0; index_e < f_elem; index_e++)
13575 for (loop_t = 0; loop_t < 2; loop_t++)
13577 record_buf_mem[index_m++] = f_ebytes;
13578 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13579 thumb2_insn_r->mem_rec_count += 1;
13581 address = address + (2 * f_ebytes);
13585 else if ((b_bits & 0x0e) == 0x04)
13587 for (index_e = 0; index_e < f_elem; index_e++)
13589 for (loop_t = 0; loop_t < 3; loop_t++)
13591 record_buf_mem[index_m++] = f_ebytes;
13592 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13593 thumb2_insn_r->mem_rec_count += 1;
13595 address = address + (3 * f_ebytes);
13599 else if (!(b_bits & 0x0e))
13601 for (index_e = 0; index_e < f_elem; index_e++)
13603 for (loop_t = 0; loop_t < 4; loop_t++)
13605 record_buf_mem[index_m++] = f_ebytes;
13606 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13607 thumb2_insn_r->mem_rec_count += 1;
13609 address = address + (4 * f_ebytes);
13615 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
13617 if (bft_size == 0x00)
13619 else if (bft_size == 0x01)
13621 else if (bft_size == 0x02)
13627 if (!(b_bits & 0x0b) || b_bits == 0x08)
13628 thumb2_insn_r->mem_rec_count = 1;
13630 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
13631 thumb2_insn_r->mem_rec_count = 2;
13633 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
13634 thumb2_insn_r->mem_rec_count = 3;
13636 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
13637 thumb2_insn_r->mem_rec_count = 4;
13639 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
13641 record_buf_mem[index_m] = f_ebytes;
13642 record_buf_mem[index_m] = address + (index_m * f_ebytes);
13651 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
13652 thumb2_insn_r->reg_rec_count = 1;
13654 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
13655 thumb2_insn_r->reg_rec_count = 2;
13657 else if ((b_bits & 0x0e) == 0x04)
13658 thumb2_insn_r->reg_rec_count = 3;
13660 else if (!(b_bits & 0x0e))
13661 thumb2_insn_r->reg_rec_count = 4;
13666 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
13667 thumb2_insn_r->reg_rec_count = 1;
13669 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
13670 thumb2_insn_r->reg_rec_count = 2;
13672 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
13673 thumb2_insn_r->reg_rec_count = 3;
13675 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
13676 thumb2_insn_r->reg_rec_count = 4;
13678 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
13679 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
13683 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
13685 record_buf[index_r] = reg_rn;
13686 thumb2_insn_r->reg_rec_count += 1;
13689 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
13691 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
13696 /* Decodes thumb2 instruction type and invokes its record handler. */
13698 static unsigned int
13699 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
13701 uint32_t op, op1, op2;
13703 op = bit (thumb2_insn_r->arm_insn, 15);
13704 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
13705 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
13709 if (!(op2 & 0x64 ))
13711 /* Load/store multiple instruction. */
13712 return thumb2_record_ld_st_multiple (thumb2_insn_r);
13714 else if (!((op2 & 0x64) ^ 0x04))
13716 /* Load/store (dual/exclusive) and table branch instruction. */
13717 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
13719 else if (!((op2 & 0x20) ^ 0x20))
13721 /* Data-processing (shifted register). */
13722 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
13724 else if (op2 & 0x40)
13726 /* Co-processor instructions. */
13727 return thumb2_record_coproc_insn (thumb2_insn_r);
13730 else if (op1 == 0x02)
13734 /* Branches and miscellaneous control instructions. */
13735 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
13737 else if (op2 & 0x20)
13739 /* Data-processing (plain binary immediate) instruction. */
13740 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13744 /* Data-processing (modified immediate). */
13745 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
13748 else if (op1 == 0x03)
13750 if (!(op2 & 0x71 ))
13752 /* Store single data item. */
13753 return thumb2_record_str_single_data (thumb2_insn_r);
13755 else if (!((op2 & 0x71) ^ 0x10))
13757 /* Advanced SIMD or structure load/store instructions. */
13758 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
13760 else if (!((op2 & 0x67) ^ 0x01))
13762 /* Load byte, memory hints instruction. */
13763 return thumb2_record_ld_mem_hints (thumb2_insn_r);
13765 else if (!((op2 & 0x67) ^ 0x03))
13767 /* Load halfword, memory hints instruction. */
13768 return thumb2_record_ld_mem_hints (thumb2_insn_r);
13770 else if (!((op2 & 0x67) ^ 0x05))
13772 /* Load word instruction. */
13773 return thumb2_record_ld_word (thumb2_insn_r);
13775 else if (!((op2 & 0x70) ^ 0x20))
13777 /* Data-processing (register) instruction. */
13778 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13780 else if (!((op2 & 0x78) ^ 0x30))
13782 /* Multiply, multiply accumulate, abs diff instruction. */
13783 return thumb2_record_ps_dest_generic (thumb2_insn_r);
13785 else if (!((op2 & 0x78) ^ 0x38))
13787 /* Long multiply, long multiply accumulate, and divide. */
13788 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
13790 else if (op2 & 0x40)
13792 /* Co-processor instructions. */
13793 return thumb2_record_coproc_insn (thumb2_insn_r);
13800 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13801 and positive val on fauilure. */
13804 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
13806 gdb_byte buf[insn_size];
13808 memset (&buf[0], 0, insn_size);
13810 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
13812 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
13814 gdbarch_byte_order_for_code (insn_record->gdbarch));
13818 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
13820 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13824 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
13825 uint32_t insn_size)
13828 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13829 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
13831 arm_record_data_proc_misc_ld_str, /* 000. */
13832 arm_record_data_proc_imm, /* 001. */
13833 arm_record_ld_st_imm_offset, /* 010. */
13834 arm_record_ld_st_reg_offset, /* 011. */
13835 arm_record_ld_st_multiple, /* 100. */
13836 arm_record_b_bl, /* 101. */
13837 arm_record_asimd_vfp_coproc, /* 110. */
13838 arm_record_coproc_data_proc /* 111. */
13841 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13842 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
13844 thumb_record_shift_add_sub, /* 000. */
13845 thumb_record_add_sub_cmp_mov, /* 001. */
13846 thumb_record_ld_st_reg_offset, /* 010. */
13847 thumb_record_ld_st_imm_offset, /* 011. */
13848 thumb_record_ld_st_stack, /* 100. */
13849 thumb_record_misc, /* 101. */
13850 thumb_record_ldm_stm_swi, /* 110. */
13851 thumb_record_branch /* 111. */
13854 uint32_t ret = 0; /* return value: negative:failure 0:success. */
13855 uint32_t insn_id = 0;
13857 if (extract_arm_insn (arm_record, insn_size))
13861 printf_unfiltered (_("Process record: error reading memory at "
13862 "addr %s len = %d.\n"),
13863 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
13867 else if (ARM_RECORD == record_type)
13869 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
13870 insn_id = bits (arm_record->arm_insn, 25, 27);
13871 ret = arm_record_extension_space (arm_record);
13872 /* If this insn has fallen into extension space
13873 then we need not decode it anymore. */
13874 if (ret != -1 && !INSN_RECORDED(arm_record))
13876 ret = arm_handle_insn[insn_id] (arm_record);
13879 else if (THUMB_RECORD == record_type)
13881 /* As thumb does not have condition codes, we set negative. */
13882 arm_record->cond = -1;
13883 insn_id = bits (arm_record->arm_insn, 13, 15);
13884 ret = thumb_handle_insn[insn_id] (arm_record);
13886 else if (THUMB2_RECORD == record_type)
13888 /* As thumb does not have condition codes, we set negative. */
13889 arm_record->cond = -1;
13891 /* Swap first half of 32bit thumb instruction with second half. */
13892 arm_record->arm_insn
13893 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
13895 insn_id = thumb2_record_decode_insn_handler (arm_record);
13897 if (insn_id != ARM_RECORD_SUCCESS)
13899 arm_record_unsupported_insn (arm_record);
13905 /* Throw assertion. */
13906 gdb_assert_not_reached ("not a valid instruction, could not decode");
13913 /* Cleans up local record registers and memory allocations. */
13916 deallocate_reg_mem (insn_decode_record *record)
13918 xfree (record->arm_regs);
13919 xfree (record->arm_mems);
13923 /* Parse the current instruction and record the values of the registers and
13924 memory that will be changed in current instruction to record_arch_list".
13925 Return -1 if something is wrong. */
13928 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
13929 CORE_ADDR insn_addr)
13932 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
13933 uint32_t no_of_rec = 0;
13934 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
13935 ULONGEST t_bit = 0, insn_id = 0;
13937 ULONGEST u_regval = 0;
13939 insn_decode_record arm_record;
13941 memset (&arm_record, 0, sizeof (insn_decode_record));
13942 arm_record.regcache = regcache;
13943 arm_record.this_addr = insn_addr;
13944 arm_record.gdbarch = gdbarch;
13947 if (record_debug > 1)
13949 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
13951 paddress (gdbarch, arm_record.this_addr));
13954 if (extract_arm_insn (&arm_record, 2))
13958 printf_unfiltered (_("Process record: error reading memory at "
13959 "addr %s len = %d.\n"),
13960 paddress (arm_record.gdbarch,
13961 arm_record.this_addr), 2);
13966 /* Check the insn, whether it is thumb or arm one. */
13968 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
13969 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
13972 if (!(u_regval & t_bit))
13974 /* We are decoding arm insn. */
13975 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
13979 insn_id = bits (arm_record.arm_insn, 11, 15);
13980 /* is it thumb2 insn? */
13981 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13983 ret = decode_insn (&arm_record, THUMB2_RECORD,
13984 THUMB2_INSN_SIZE_BYTES);
13988 /* We are decoding thumb insn. */
13989 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
13995 /* Record registers. */
13996 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
13997 if (arm_record.arm_regs)
13999 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
14001 if (record_full_arch_list_add_reg
14002 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
14006 /* Record memories. */
14007 if (arm_record.arm_mems)
14009 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
14011 if (record_full_arch_list_add_mem
14012 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
14013 arm_record.arm_mems[no_of_rec].len))
14018 if (record_full_arch_list_add_end ())
14023 deallocate_reg_mem (&arm_record);