1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
62 #include "features/arm-with-m.c"
63 #include "features/arm-with-m-fpa-layout.c"
64 #include "features/arm-with-m-vfp-d16.c"
65 #include "features/arm-with-iwmmxt.c"
66 #include "features/arm-with-vfpv2.c"
67 #include "features/arm-with-vfpv3.c"
68 #include "features/arm-with-neon.c"
72 /* Macros for setting and testing a bit in a minimal symbol that marks
73 it as Thumb function. The MSB of the minimal symbol's "info" field
74 is used for this purpose.
76 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
77 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
79 #define MSYMBOL_SET_SPECIAL(msym) \
80 MSYMBOL_TARGET_FLAG_1 (msym) = 1
82 #define MSYMBOL_IS_SPECIAL(msym) \
83 MSYMBOL_TARGET_FLAG_1 (msym)
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data *arm_objfile_data_key;
88 struct arm_mapping_symbol
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
94 DEF_VEC_O(arm_mapping_symbol_s);
96 struct arm_per_objfile
98 VEC(arm_mapping_symbol_s) **section_maps;
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element *setarmcmdlist = NULL;
103 static struct cmd_list_element *showarmcmdlist = NULL;
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *const fp_model_strings[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
119 static const char *current_fp_model = "auto";
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *const arm_abi_strings[] =
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
132 static const char *arm_abi_string = "auto";
134 /* The execution mode to assume. */
135 static const char *const arm_mode_strings[] =
143 static const char *arm_fallback_mode_string = "auto";
144 static const char *arm_force_mode_string = "auto";
146 /* Internal override of the execution mode. -1 means no override,
147 0 means override to ARM mode, 1 means override to Thumb mode.
148 The effect is the same as if arm_force_mode has been set by the
149 user (except the internal override has precedence over a user's
150 arm_force_mode override). */
151 static int arm_override_mode = -1;
153 /* Number of different reg name sets (options). */
154 static int num_disassembly_options;
156 /* The standard register names, and all the valid aliases for them. Note
157 that `fp', `sp' and `pc' are not added in this alias list, because they
158 have been added as builtin user registers in
159 std-regs.c:_initialize_frame_reg. */
164 } arm_register_aliases[] = {
165 /* Basic register numbers. */
182 /* Synonyms (argument and variable registers). */
195 /* Other platform-specific names for r9. */
201 /* Names used by GCC (not listed in the ARM EABI). */
203 /* A special name from the older ATPCS. */
207 static const char *const arm_register_names[] =
208 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
209 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
210 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
211 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
212 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
213 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
214 "fps", "cpsr" }; /* 24 25 */
216 /* Valid register name styles. */
217 static const char **valid_disassembly_styles;
219 /* Disassembly style to use. Default to "std" register names. */
220 static const char *disassembly_style;
222 /* This is used to keep the bfd arch_info in sync with the disassembly
224 static void set_disassembly_style_sfunc(char *, int,
225 struct cmd_list_element *);
226 static void set_disassembly_style (void);
228 static void convert_from_extended (const struct floatformat *, const void *,
230 static void convert_to_extended (const struct floatformat *, void *,
233 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
234 struct regcache *regcache,
235 int regnum, gdb_byte *buf);
236 static void arm_neon_quad_write (struct gdbarch *gdbarch,
237 struct regcache *regcache,
238 int regnum, const gdb_byte *buf);
241 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self);
244 /* get_next_pcs operations. */
245 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = {
246 arm_get_next_pcs_read_memory_unsigned_integer,
247 arm_get_next_pcs_syscall_next_pc,
248 arm_get_next_pcs_addr_bits_remove,
249 arm_get_next_pcs_is_thumb,
253 struct arm_prologue_cache
255 /* The stack pointer at the time this frame was created; i.e. the
256 caller's stack pointer when this function was called. It is used
257 to identify this frame. */
260 /* The frame base for this frame is just prev_sp - frame size.
261 FRAMESIZE is the distance from the frame pointer to the
262 initial stack pointer. */
266 /* The register used to hold the frame pointer for this frame. */
269 /* Saved register offsets. */
270 struct trad_frame_saved_reg *saved_regs;
273 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
274 CORE_ADDR prologue_start,
275 CORE_ADDR prologue_end,
276 struct arm_prologue_cache *cache);
278 /* Architecture version for displaced stepping. This effects the behaviour of
279 certain instructions, and really should not be hard-wired. */
281 #define DISPLACED_STEPPING_ARCH_VERSION 5
283 /* Set to true if the 32-bit mode is in use. */
287 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
290 arm_psr_thumb_bit (struct gdbarch *gdbarch)
292 if (gdbarch_tdep (gdbarch)->is_m)
298 /* Determine if the processor is currently executing in Thumb mode. */
301 arm_is_thumb (struct regcache *regcache)
304 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
306 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
308 return (cpsr & t_bit) != 0;
311 /* Determine if FRAME is executing in Thumb mode. */
314 arm_frame_is_thumb (struct frame_info *frame)
317 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
319 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
320 directly (from a signal frame or dummy frame) or by interpreting
321 the saved LR (from a prologue or DWARF frame). So consult it and
322 trust the unwinders. */
323 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
325 return (cpsr & t_bit) != 0;
328 /* Callback for VEC_lower_bound. */
331 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
332 const struct arm_mapping_symbol *rhs)
334 return lhs->value < rhs->value;
337 /* Search for the mapping symbol covering MEMADDR. If one is found,
338 return its type. Otherwise, return 0. If START is non-NULL,
339 set *START to the location of the mapping symbol. */
342 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
344 struct obj_section *sec;
346 /* If there are mapping symbols, consult them. */
347 sec = find_pc_section (memaddr);
350 struct arm_per_objfile *data;
351 VEC(arm_mapping_symbol_s) *map;
352 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
356 data = (struct arm_per_objfile *) objfile_data (sec->objfile,
357 arm_objfile_data_key);
360 map = data->section_maps[sec->the_bfd_section->index];
361 if (!VEC_empty (arm_mapping_symbol_s, map))
363 struct arm_mapping_symbol *map_sym;
365 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
366 arm_compare_mapping_symbols);
368 /* VEC_lower_bound finds the earliest ordered insertion
369 point. If the following symbol starts at this exact
370 address, we use that; otherwise, the preceding
371 mapping symbol covers this address. */
372 if (idx < VEC_length (arm_mapping_symbol_s, map))
374 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
375 if (map_sym->value == map_key.value)
378 *start = map_sym->value + obj_section_addr (sec);
379 return map_sym->type;
385 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
387 *start = map_sym->value + obj_section_addr (sec);
388 return map_sym->type;
397 /* Determine if the program counter specified in MEMADDR is in a Thumb
398 function. This function should be called for addresses unrelated to
399 any executing frame; otherwise, prefer arm_frame_is_thumb. */
402 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
404 struct bound_minimal_symbol sym;
406 struct displaced_step_closure* dsc
407 = get_displaced_step_closure_by_addr(memaddr);
409 /* If checking the mode of displaced instruction in copy area, the mode
410 should be determined by instruction on the original address. */
414 fprintf_unfiltered (gdb_stdlog,
415 "displaced: check mode of %.8lx instead of %.8lx\n",
416 (unsigned long) dsc->insn_addr,
417 (unsigned long) memaddr);
418 memaddr = dsc->insn_addr;
421 /* If bit 0 of the address is set, assume this is a Thumb address. */
422 if (IS_THUMB_ADDR (memaddr))
425 /* Respect internal mode override if active. */
426 if (arm_override_mode != -1)
427 return arm_override_mode;
429 /* If the user wants to override the symbol table, let him. */
430 if (strcmp (arm_force_mode_string, "arm") == 0)
432 if (strcmp (arm_force_mode_string, "thumb") == 0)
435 /* ARM v6-M and v7-M are always in Thumb mode. */
436 if (gdbarch_tdep (gdbarch)->is_m)
439 /* If there are mapping symbols, consult them. */
440 type = arm_find_mapping_symbol (memaddr, NULL);
444 /* Thumb functions have a "special" bit set in minimal symbols. */
445 sym = lookup_minimal_symbol_by_pc (memaddr);
447 return (MSYMBOL_IS_SPECIAL (sym.minsym));
449 /* If the user wants to override the fallback mode, let them. */
450 if (strcmp (arm_fallback_mode_string, "arm") == 0)
452 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
455 /* If we couldn't find any symbol, but we're talking to a running
456 target, then trust the current value of $cpsr. This lets
457 "display/i $pc" always show the correct mode (though if there is
458 a symbol table we will not reach here, so it still may not be
459 displayed in the mode it will be executed). */
460 if (target_has_registers)
461 return arm_frame_is_thumb (get_current_frame ());
463 /* Otherwise we're out of luck; we assume ARM. */
467 /* Remove useless bits from addresses in a running program. */
469 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
471 /* On M-profile devices, do not strip the low bit from EXC_RETURN
472 (the magic exception return address). */
473 if (gdbarch_tdep (gdbarch)->is_m
474 && (val & 0xfffffff0) == 0xfffffff0)
478 return UNMAKE_THUMB_ADDR (val);
480 return (val & 0x03fffffc);
483 /* Return 1 if PC is the start of a compiler helper function which
484 can be safely ignored during prologue skipping. IS_THUMB is true
485 if the function is known to be a Thumb function due to the way it
488 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
490 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
491 struct bound_minimal_symbol msym;
493 msym = lookup_minimal_symbol_by_pc (pc);
494 if (msym.minsym != NULL
495 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
496 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
498 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
500 /* The GNU linker's Thumb call stub to foo is named
502 if (strstr (name, "_from_thumb") != NULL)
505 /* On soft-float targets, __truncdfsf2 is called to convert promoted
506 arguments to their argument types in non-prototyped
508 if (startswith (name, "__truncdfsf2"))
510 if (startswith (name, "__aeabi_d2f"))
513 /* Internal functions related to thread-local storage. */
514 if (startswith (name, "__tls_get_addr"))
516 if (startswith (name, "__aeabi_read_tp"))
521 /* If we run against a stripped glibc, we may be unable to identify
522 special functions by name. Check for one important case,
523 __aeabi_read_tp, by comparing the *code* against the default
524 implementation (this is hand-written ARM assembler in glibc). */
527 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
528 == 0xe3e00a0f /* mov r0, #0xffff0fff */
529 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
530 == 0xe240f01f) /* sub pc, r0, #31 */
537 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
538 the first 16-bit of instruction, and INSN2 is the second 16-bit of
540 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
541 ((bits ((insn1), 0, 3) << 12) \
542 | (bits ((insn1), 10, 10) << 11) \
543 | (bits ((insn2), 12, 14) << 8) \
544 | bits ((insn2), 0, 7))
546 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
547 the 32-bit instruction. */
548 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
549 ((bits ((insn), 16, 19) << 12) \
550 | bits ((insn), 0, 11))
552 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
555 thumb_expand_immediate (unsigned int imm)
557 unsigned int count = imm >> 7;
565 return (imm & 0xff) | ((imm & 0xff) << 16);
567 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
569 return (imm & 0xff) | ((imm & 0xff) << 8)
570 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
573 return (0x80 | (imm & 0x7f)) << (32 - count);
576 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
577 epilogue, 0 otherwise. */
580 thumb_instruction_restores_sp (unsigned short insn)
582 return (insn == 0x46bd /* mov sp, r7 */
583 || (insn & 0xff80) == 0xb000 /* add sp, imm */
584 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
587 /* Analyze a Thumb prologue, looking for a recognizable stack frame
588 and frame pointer. Scan until we encounter a store that could
589 clobber the stack frame unexpectedly, or an unknown instruction.
590 Return the last address which is definitely safe to skip for an
591 initial breakpoint. */
594 thumb_analyze_prologue (struct gdbarch *gdbarch,
595 CORE_ADDR start, CORE_ADDR limit,
596 struct arm_prologue_cache *cache)
598 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
599 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
602 struct pv_area *stack;
603 struct cleanup *back_to;
605 CORE_ADDR unrecognized_pc = 0;
607 for (i = 0; i < 16; i++)
608 regs[i] = pv_register (i, 0);
609 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
610 back_to = make_cleanup_free_pv_area (stack);
612 while (start < limit)
616 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
618 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
623 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
626 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
627 whether to save LR (R14). */
628 mask = (insn & 0xff) | ((insn & 0x100) << 6);
630 /* Calculate offsets of saved R0-R7 and LR. */
631 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
632 if (mask & (1 << regno))
634 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
636 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
639 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
641 offset = (insn & 0x7f) << 2; /* get scaled offset */
642 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
645 else if (thumb_instruction_restores_sp (insn))
647 /* Don't scan past the epilogue. */
650 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
651 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
653 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
654 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
655 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
657 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
658 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
659 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
661 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
662 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
663 && pv_is_constant (regs[bits (insn, 3, 5)]))
664 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
665 regs[bits (insn, 6, 8)]);
666 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
667 && pv_is_constant (regs[bits (insn, 3, 6)]))
669 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
670 int rm = bits (insn, 3, 6);
671 regs[rd] = pv_add (regs[rd], regs[rm]);
673 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
675 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
676 int src_reg = (insn & 0x78) >> 3;
677 regs[dst_reg] = regs[src_reg];
679 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
681 /* Handle stores to the stack. Normally pushes are used,
682 but with GCC -mtpcs-frame, there may be other stores
683 in the prologue to create the frame. */
684 int regno = (insn >> 8) & 0x7;
687 offset = (insn & 0xff) << 2;
688 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
690 if (pv_area_store_would_trash (stack, addr))
693 pv_area_store (stack, addr, 4, regs[regno]);
695 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
697 int rd = bits (insn, 0, 2);
698 int rn = bits (insn, 3, 5);
701 offset = bits (insn, 6, 10) << 2;
702 addr = pv_add_constant (regs[rn], offset);
704 if (pv_area_store_would_trash (stack, addr))
707 pv_area_store (stack, addr, 4, regs[rd]);
709 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
710 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
711 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
712 /* Ignore stores of argument registers to the stack. */
714 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
715 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
716 /* Ignore block loads from the stack, potentially copying
717 parameters from memory. */
719 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
720 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
721 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
722 /* Similarly ignore single loads from the stack. */
724 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
725 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
726 /* Skip register copies, i.e. saves to another register
727 instead of the stack. */
729 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
730 /* Recognize constant loads; even with small stacks these are necessary
732 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
733 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
735 /* Constant pool loads, for the same reason. */
736 unsigned int constant;
739 loc = start + 4 + bits (insn, 0, 7) * 4;
740 constant = read_memory_unsigned_integer (loc, 4, byte_order);
741 regs[bits (insn, 8, 10)] = pv_constant (constant);
743 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
745 unsigned short inst2;
747 inst2 = read_memory_unsigned_integer (start + 2, 2,
748 byte_order_for_code);
750 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
752 /* BL, BLX. Allow some special function calls when
753 skipping the prologue; GCC generates these before
754 storing arguments to the stack. */
756 int j1, j2, imm1, imm2;
758 imm1 = sbits (insn, 0, 10);
759 imm2 = bits (inst2, 0, 10);
760 j1 = bit (inst2, 13);
761 j2 = bit (inst2, 11);
763 offset = ((imm1 << 12) + (imm2 << 1));
764 offset ^= ((!j2) << 22) | ((!j1) << 23);
766 nextpc = start + 4 + offset;
767 /* For BLX make sure to clear the low bits. */
768 if (bit (inst2, 12) == 0)
769 nextpc = nextpc & 0xfffffffc;
771 if (!skip_prologue_function (gdbarch, nextpc,
772 bit (inst2, 12) != 0))
776 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
778 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
780 pv_t addr = regs[bits (insn, 0, 3)];
783 if (pv_area_store_would_trash (stack, addr))
786 /* Calculate offsets of saved registers. */
787 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
788 if (inst2 & (1 << regno))
790 addr = pv_add_constant (addr, -4);
791 pv_area_store (stack, addr, 4, regs[regno]);
795 regs[bits (insn, 0, 3)] = addr;
798 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
800 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
802 int regno1 = bits (inst2, 12, 15);
803 int regno2 = bits (inst2, 8, 11);
804 pv_t addr = regs[bits (insn, 0, 3)];
806 offset = inst2 & 0xff;
808 addr = pv_add_constant (addr, offset);
810 addr = pv_add_constant (addr, -offset);
812 if (pv_area_store_would_trash (stack, addr))
815 pv_area_store (stack, addr, 4, regs[regno1]);
816 pv_area_store (stack, pv_add_constant (addr, 4),
820 regs[bits (insn, 0, 3)] = addr;
823 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
824 && (inst2 & 0x0c00) == 0x0c00
825 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
827 int regno = bits (inst2, 12, 15);
828 pv_t addr = regs[bits (insn, 0, 3)];
830 offset = inst2 & 0xff;
832 addr = pv_add_constant (addr, offset);
834 addr = pv_add_constant (addr, -offset);
836 if (pv_area_store_would_trash (stack, addr))
839 pv_area_store (stack, addr, 4, regs[regno]);
842 regs[bits (insn, 0, 3)] = addr;
845 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
846 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
848 int regno = bits (inst2, 12, 15);
851 offset = inst2 & 0xfff;
852 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
854 if (pv_area_store_would_trash (stack, addr))
857 pv_area_store (stack, addr, 4, regs[regno]);
860 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
861 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
862 /* Ignore stores of argument registers to the stack. */
865 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
866 && (inst2 & 0x0d00) == 0x0c00
867 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
868 /* Ignore stores of argument registers to the stack. */
871 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
873 && (inst2 & 0x8000) == 0x0000
874 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
875 /* Ignore block loads from the stack, potentially copying
876 parameters from memory. */
879 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
881 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
882 /* Similarly ignore dual loads from the stack. */
885 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
886 && (inst2 & 0x0d00) == 0x0c00
887 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
888 /* Similarly ignore single loads from the stack. */
891 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
892 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
893 /* Similarly ignore single loads from the stack. */
896 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
897 && (inst2 & 0x8000) == 0x0000)
899 unsigned int imm = ((bits (insn, 10, 10) << 11)
900 | (bits (inst2, 12, 14) << 8)
901 | bits (inst2, 0, 7));
903 regs[bits (inst2, 8, 11)]
904 = pv_add_constant (regs[bits (insn, 0, 3)],
905 thumb_expand_immediate (imm));
908 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
909 && (inst2 & 0x8000) == 0x0000)
911 unsigned int imm = ((bits (insn, 10, 10) << 11)
912 | (bits (inst2, 12, 14) << 8)
913 | bits (inst2, 0, 7));
915 regs[bits (inst2, 8, 11)]
916 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
919 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
920 && (inst2 & 0x8000) == 0x0000)
922 unsigned int imm = ((bits (insn, 10, 10) << 11)
923 | (bits (inst2, 12, 14) << 8)
924 | bits (inst2, 0, 7));
926 regs[bits (inst2, 8, 11)]
927 = pv_add_constant (regs[bits (insn, 0, 3)],
928 - (CORE_ADDR) thumb_expand_immediate (imm));
931 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
932 && (inst2 & 0x8000) == 0x0000)
934 unsigned int imm = ((bits (insn, 10, 10) << 11)
935 | (bits (inst2, 12, 14) << 8)
936 | bits (inst2, 0, 7));
938 regs[bits (inst2, 8, 11)]
939 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
942 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
944 unsigned int imm = ((bits (insn, 10, 10) << 11)
945 | (bits (inst2, 12, 14) << 8)
946 | bits (inst2, 0, 7));
948 regs[bits (inst2, 8, 11)]
949 = pv_constant (thumb_expand_immediate (imm));
952 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
955 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
957 regs[bits (inst2, 8, 11)] = pv_constant (imm);
960 else if (insn == 0xea5f /* mov.w Rd,Rm */
961 && (inst2 & 0xf0f0) == 0)
963 int dst_reg = (inst2 & 0x0f00) >> 8;
964 int src_reg = inst2 & 0xf;
965 regs[dst_reg] = regs[src_reg];
968 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
970 /* Constant pool loads. */
971 unsigned int constant;
974 offset = bits (inst2, 0, 11);
976 loc = start + 4 + offset;
978 loc = start + 4 - offset;
980 constant = read_memory_unsigned_integer (loc, 4, byte_order);
981 regs[bits (inst2, 12, 15)] = pv_constant (constant);
984 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
986 /* Constant pool loads. */
987 unsigned int constant;
990 offset = bits (inst2, 0, 7) << 2;
992 loc = start + 4 + offset;
994 loc = start + 4 - offset;
996 constant = read_memory_unsigned_integer (loc, 4, byte_order);
997 regs[bits (inst2, 12, 15)] = pv_constant (constant);
999 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1000 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1003 else if (thumb2_instruction_changes_pc (insn, inst2))
1005 /* Don't scan past anything that might change control flow. */
1010 /* The optimizer might shove anything into the prologue,
1011 so we just skip what we don't recognize. */
1012 unrecognized_pc = start;
1017 else if (thumb_instruction_changes_pc (insn))
1019 /* Don't scan past anything that might change control flow. */
1024 /* The optimizer might shove anything into the prologue,
1025 so we just skip what we don't recognize. */
1026 unrecognized_pc = start;
1033 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1034 paddress (gdbarch, start));
1036 if (unrecognized_pc == 0)
1037 unrecognized_pc = start;
1041 do_cleanups (back_to);
1042 return unrecognized_pc;
1045 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1047 /* Frame pointer is fp. Frame size is constant. */
1048 cache->framereg = ARM_FP_REGNUM;
1049 cache->framesize = -regs[ARM_FP_REGNUM].k;
1051 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1053 /* Frame pointer is r7. Frame size is constant. */
1054 cache->framereg = THUMB_FP_REGNUM;
1055 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1059 /* Try the stack pointer... this is a bit desperate. */
1060 cache->framereg = ARM_SP_REGNUM;
1061 cache->framesize = -regs[ARM_SP_REGNUM].k;
1064 for (i = 0; i < 16; i++)
1065 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1066 cache->saved_regs[i].addr = offset;
1068 do_cleanups (back_to);
1069 return unrecognized_pc;
1073 /* Try to analyze the instructions starting from PC, which load symbol
1074 __stack_chk_guard. Return the address of instruction after loading this
1075 symbol, set the dest register number to *BASEREG, and set the size of
1076 instructions for loading symbol in OFFSET. Return 0 if instructions are
1080 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1081 unsigned int *destreg, int *offset)
1083 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1084 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1085 unsigned int low, high, address;
1090 unsigned short insn1
1091 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1093 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1095 *destreg = bits (insn1, 8, 10);
1097 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1098 address = read_memory_unsigned_integer (address, 4,
1099 byte_order_for_code);
1101 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1103 unsigned short insn2
1104 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1106 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1109 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1111 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1113 /* movt Rd, #const */
1114 if ((insn1 & 0xfbc0) == 0xf2c0)
1116 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1117 *destreg = bits (insn2, 8, 11);
1119 address = (high << 16 | low);
1126 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1128 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1130 address = bits (insn, 0, 11) + pc + 8;
1131 address = read_memory_unsigned_integer (address, 4,
1132 byte_order_for_code);
1134 *destreg = bits (insn, 12, 15);
1137 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1139 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1142 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1144 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1146 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1147 *destreg = bits (insn, 12, 15);
1149 address = (high << 16 | low);
1157 /* Try to skip a sequence of instructions used for stack protector. If PC
1158 points to the first instruction of this sequence, return the address of
1159 first instruction after this sequence, otherwise, return original PC.
1161 On arm, this sequence of instructions is composed of mainly three steps,
1162 Step 1: load symbol __stack_chk_guard,
1163 Step 2: load from address of __stack_chk_guard,
1164 Step 3: store it to somewhere else.
1166 Usually, instructions on step 2 and step 3 are the same on various ARM
1167 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1168 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1169 instructions in step 1 vary from different ARM architectures. On ARMv7,
1172 movw Rn, #:lower16:__stack_chk_guard
1173 movt Rn, #:upper16:__stack_chk_guard
1180 .word __stack_chk_guard
1182 Since ldr/str is a very popular instruction, we can't use them as
1183 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1184 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1185 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1188 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1190 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1191 unsigned int basereg;
1192 struct bound_minimal_symbol stack_chk_guard;
1194 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1197 /* Try to parse the instructions in Step 1. */
1198 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1203 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1204 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1205 Otherwise, this sequence cannot be for stack protector. */
1206 if (stack_chk_guard.minsym == NULL
1207 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1212 unsigned int destreg;
1214 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1216 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1217 if ((insn & 0xf800) != 0x6800)
1219 if (bits (insn, 3, 5) != basereg)
1221 destreg = bits (insn, 0, 2);
1223 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1224 byte_order_for_code);
1225 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1226 if ((insn & 0xf800) != 0x6000)
1228 if (destreg != bits (insn, 0, 2))
1233 unsigned int destreg;
1235 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1237 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1238 if ((insn & 0x0e500000) != 0x04100000)
1240 if (bits (insn, 16, 19) != basereg)
1242 destreg = bits (insn, 12, 15);
1243 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1244 insn = read_memory_unsigned_integer (pc + offset + 4,
1245 4, byte_order_for_code);
1246 if ((insn & 0x0e500000) != 0x04000000)
1248 if (bits (insn, 12, 15) != destreg)
1251 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1254 return pc + offset + 4;
1256 return pc + offset + 8;
1259 /* Advance the PC across any function entry prologue instructions to
1260 reach some "real" code.
1262 The APCS (ARM Procedure Call Standard) defines the following
1266 [stmfd sp!, {a1,a2,a3,a4}]
1267 stmfd sp!, {...,fp,ip,lr,pc}
1268 [stfe f7, [sp, #-12]!]
1269 [stfe f6, [sp, #-12]!]
1270 [stfe f5, [sp, #-12]!]
1271 [stfe f4, [sp, #-12]!]
1272 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1275 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1277 CORE_ADDR func_addr, limit_pc;
1279 /* See if we can determine the end of the prologue via the symbol table.
1280 If so, then return either PC, or the PC after the prologue, whichever
1282 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1284 CORE_ADDR post_prologue_pc
1285 = skip_prologue_using_sal (gdbarch, func_addr);
1286 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1288 if (post_prologue_pc)
1290 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1293 /* GCC always emits a line note before the prologue and another
1294 one after, even if the two are at the same address or on the
1295 same line. Take advantage of this so that we do not need to
1296 know every instruction that might appear in the prologue. We
1297 will have producer information for most binaries; if it is
1298 missing (e.g. for -gstabs), assuming the GNU tools. */
1299 if (post_prologue_pc
1301 || COMPUNIT_PRODUCER (cust) == NULL
1302 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1303 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1304 return post_prologue_pc;
1306 if (post_prologue_pc != 0)
1308 CORE_ADDR analyzed_limit;
1310 /* For non-GCC compilers, make sure the entire line is an
1311 acceptable prologue; GDB will round this function's
1312 return value up to the end of the following line so we
1313 can not skip just part of a line (and we do not want to).
1315 RealView does not treat the prologue specially, but does
1316 associate prologue code with the opening brace; so this
1317 lets us skip the first line if we think it is the opening
1319 if (arm_pc_is_thumb (gdbarch, func_addr))
1320 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1321 post_prologue_pc, NULL);
1323 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1324 post_prologue_pc, NULL);
1326 if (analyzed_limit != post_prologue_pc)
1329 return post_prologue_pc;
1333 /* Can't determine prologue from the symbol table, need to examine
1336 /* Find an upper limit on the function prologue using the debug
1337 information. If the debug information could not be used to provide
1338 that bound, then use an arbitrary large number as the upper bound. */
1339 /* Like arm_scan_prologue, stop no later than pc + 64. */
1340 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1342 limit_pc = pc + 64; /* Magic. */
1345 /* Check if this is Thumb code. */
1346 if (arm_pc_is_thumb (gdbarch, pc))
1347 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1349 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1353 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1354 This function decodes a Thumb function prologue to determine:
1355 1) the size of the stack frame
1356 2) which registers are saved on it
1357 3) the offsets of saved regs
1358 4) the offset from the stack pointer to the frame pointer
1360 A typical Thumb function prologue would create this stack frame
1361 (offsets relative to FP)
1362 old SP -> 24 stack parameters
1365 R7 -> 0 local variables (16 bytes)
1366 SP -> -12 additional stack space (12 bytes)
1367 The frame size would thus be 36 bytes, and the frame offset would be
1368 12 bytes. The frame register is R7.
1370 The comments for thumb_skip_prolog() describe the algorithm we use
1371 to detect the end of the prolog. */
1375 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1376 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1378 CORE_ADDR prologue_start;
1379 CORE_ADDR prologue_end;
1381 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1384 /* See comment in arm_scan_prologue for an explanation of
1386 if (prologue_end > prologue_start + 64)
1388 prologue_end = prologue_start + 64;
1392 /* We're in the boondocks: we have no idea where the start of the
1396 prologue_end = min (prologue_end, prev_pc);
1398 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1401 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1405 arm_instruction_restores_sp (unsigned int insn)
1407 if (bits (insn, 28, 31) != INST_NV)
1409 if ((insn & 0x0df0f000) == 0x0080d000
1410 /* ADD SP (register or immediate). */
1411 || (insn & 0x0df0f000) == 0x0040d000
1412 /* SUB SP (register or immediate). */
1413 || (insn & 0x0ffffff0) == 0x01a0d000
1415 || (insn & 0x0fff0000) == 0x08bd0000
1417 || (insn & 0x0fff0000) == 0x049d0000)
1418 /* POP of a single register. */
1425 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1426 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1427 fill it in. Return the first address not recognized as a prologue
1430 We recognize all the instructions typically found in ARM prologues,
1431 plus harmless instructions which can be skipped (either for analysis
1432 purposes, or a more restrictive set that can be skipped when finding
1433 the end of the prologue). */
1436 arm_analyze_prologue (struct gdbarch *gdbarch,
1437 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1438 struct arm_prologue_cache *cache)
1440 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1442 CORE_ADDR offset, current_pc;
1443 pv_t regs[ARM_FPS_REGNUM];
1444 struct pv_area *stack;
1445 struct cleanup *back_to;
1446 CORE_ADDR unrecognized_pc = 0;
1448 /* Search the prologue looking for instructions that set up the
1449 frame pointer, adjust the stack pointer, and save registers.
1451 Be careful, however, and if it doesn't look like a prologue,
1452 don't try to scan it. If, for instance, a frameless function
1453 begins with stmfd sp!, then we will tell ourselves there is
1454 a frame, which will confuse stack traceback, as well as "finish"
1455 and other operations that rely on a knowledge of the stack
1458 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1459 regs[regno] = pv_register (regno, 0);
1460 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1461 back_to = make_cleanup_free_pv_area (stack);
1463 for (current_pc = prologue_start;
1464 current_pc < prologue_end;
1468 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1470 if (insn == 0xe1a0c00d) /* mov ip, sp */
1472 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1475 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1476 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1478 unsigned imm = insn & 0xff; /* immediate value */
1479 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1480 int rd = bits (insn, 12, 15);
1481 imm = (imm >> rot) | (imm << (32 - rot));
1482 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1485 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1486 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1488 unsigned imm = insn & 0xff; /* immediate value */
1489 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1490 int rd = bits (insn, 12, 15);
1491 imm = (imm >> rot) | (imm << (32 - rot));
1492 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1495 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1498 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1500 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1501 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1502 regs[bits (insn, 12, 15)]);
1505 else if ((insn & 0xffff0000) == 0xe92d0000)
1506 /* stmfd sp!, {..., fp, ip, lr, pc}
1508 stmfd sp!, {a1, a2, a3, a4} */
1510 int mask = insn & 0xffff;
1512 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1515 /* Calculate offsets of saved registers. */
1516 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1517 if (mask & (1 << regno))
1520 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1521 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1524 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1525 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1526 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1528 /* No need to add this to saved_regs -- it's just an arg reg. */
1531 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1532 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1533 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1535 /* No need to add this to saved_regs -- it's just an arg reg. */
1538 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1540 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1542 /* No need to add this to saved_regs -- it's just arg regs. */
1545 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1547 unsigned imm = insn & 0xff; /* immediate value */
1548 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1549 imm = (imm >> rot) | (imm << (32 - rot));
1550 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1552 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1554 unsigned imm = insn & 0xff; /* immediate value */
1555 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1556 imm = (imm >> rot) | (imm << (32 - rot));
1557 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1559 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1561 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1563 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1566 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1567 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1568 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1570 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1572 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1574 int n_saved_fp_regs;
1575 unsigned int fp_start_reg, fp_bound_reg;
1577 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1580 if ((insn & 0x800) == 0x800) /* N0 is set */
1582 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1583 n_saved_fp_regs = 3;
1585 n_saved_fp_regs = 1;
1589 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1590 n_saved_fp_regs = 2;
1592 n_saved_fp_regs = 4;
1595 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1596 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1597 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1599 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1600 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1601 regs[fp_start_reg++]);
1604 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1606 /* Allow some special function calls when skipping the
1607 prologue; GCC generates these before storing arguments to
1609 CORE_ADDR dest = BranchDest (current_pc, insn);
1611 if (skip_prologue_function (gdbarch, dest, 0))
1616 else if ((insn & 0xf0000000) != 0xe0000000)
1617 break; /* Condition not true, exit early. */
1618 else if (arm_instruction_changes_pc (insn))
1619 /* Don't scan past anything that might change control flow. */
1621 else if (arm_instruction_restores_sp (insn))
1623 /* Don't scan past the epilogue. */
1626 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1627 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1628 /* Ignore block loads from the stack, potentially copying
1629 parameters from memory. */
1631 else if ((insn & 0xfc500000) == 0xe4100000
1632 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1633 /* Similarly ignore single loads from the stack. */
1635 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1636 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1637 register instead of the stack. */
1641 /* The optimizer might shove anything into the prologue, if
1642 we build up cache (cache != NULL) from scanning prologue,
1643 we just skip what we don't recognize and scan further to
1644 make cache as complete as possible. However, if we skip
1645 prologue, we'll stop immediately on unrecognized
1647 unrecognized_pc = current_pc;
1655 if (unrecognized_pc == 0)
1656 unrecognized_pc = current_pc;
1660 int framereg, framesize;
1662 /* The frame size is just the distance from the frame register
1663 to the original stack pointer. */
1664 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1666 /* Frame pointer is fp. */
1667 framereg = ARM_FP_REGNUM;
1668 framesize = -regs[ARM_FP_REGNUM].k;
1672 /* Try the stack pointer... this is a bit desperate. */
1673 framereg = ARM_SP_REGNUM;
1674 framesize = -regs[ARM_SP_REGNUM].k;
1677 cache->framereg = framereg;
1678 cache->framesize = framesize;
1680 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1681 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1682 cache->saved_regs[regno].addr = offset;
1686 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1687 paddress (gdbarch, unrecognized_pc));
1689 do_cleanups (back_to);
1690 return unrecognized_pc;
1694 arm_scan_prologue (struct frame_info *this_frame,
1695 struct arm_prologue_cache *cache)
1697 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1698 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1699 CORE_ADDR prologue_start, prologue_end;
1700 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1701 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1703 /* Assume there is no frame until proven otherwise. */
1704 cache->framereg = ARM_SP_REGNUM;
1705 cache->framesize = 0;
1707 /* Check for Thumb prologue. */
1708 if (arm_frame_is_thumb (this_frame))
1710 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1714 /* Find the function prologue. If we can't find the function in
1715 the symbol table, peek in the stack frame to find the PC. */
1716 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1719 /* One way to find the end of the prologue (which works well
1720 for unoptimized code) is to do the following:
1722 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1725 prologue_end = prev_pc;
1726 else if (sal.end < prologue_end)
1727 prologue_end = sal.end;
1729 This mechanism is very accurate so long as the optimizer
1730 doesn't move any instructions from the function body into the
1731 prologue. If this happens, sal.end will be the last
1732 instruction in the first hunk of prologue code just before
1733 the first instruction that the scheduler has moved from
1734 the body to the prologue.
1736 In order to make sure that we scan all of the prologue
1737 instructions, we use a slightly less accurate mechanism which
1738 may scan more than necessary. To help compensate for this
1739 lack of accuracy, the prologue scanning loop below contains
1740 several clauses which'll cause the loop to terminate early if
1741 an implausible prologue instruction is encountered.
1747 is a suitable endpoint since it accounts for the largest
1748 possible prologue plus up to five instructions inserted by
1751 if (prologue_end > prologue_start + 64)
1753 prologue_end = prologue_start + 64; /* See above. */
1758 /* We have no symbol information. Our only option is to assume this
1759 function has a standard stack frame and the normal frame register.
1760 Then, we can find the value of our frame pointer on entrance to
1761 the callee (or at the present moment if this is the innermost frame).
1762 The value stored there should be the address of the stmfd + 8. */
1763 CORE_ADDR frame_loc;
1764 LONGEST return_value;
1766 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1767 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1771 prologue_start = gdbarch_addr_bits_remove
1772 (gdbarch, return_value) - 8;
1773 prologue_end = prologue_start + 64; /* See above. */
1777 if (prev_pc < prologue_end)
1778 prologue_end = prev_pc;
1780 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1783 static struct arm_prologue_cache *
1784 arm_make_prologue_cache (struct frame_info *this_frame)
1787 struct arm_prologue_cache *cache;
1788 CORE_ADDR unwound_fp;
1790 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1791 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1793 arm_scan_prologue (this_frame, cache);
1795 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1796 if (unwound_fp == 0)
1799 cache->prev_sp = unwound_fp + cache->framesize;
1801 /* Calculate actual addresses of saved registers using offsets
1802 determined by arm_scan_prologue. */
1803 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1804 if (trad_frame_addr_p (cache->saved_regs, reg))
1805 cache->saved_regs[reg].addr += cache->prev_sp;
1810 /* Implementation of the stop_reason hook for arm_prologue frames. */
1812 static enum unwind_stop_reason
1813 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
1816 struct arm_prologue_cache *cache;
1819 if (*this_cache == NULL)
1820 *this_cache = arm_make_prologue_cache (this_frame);
1821 cache = (struct arm_prologue_cache *) *this_cache;
1823 /* This is meant to halt the backtrace at "_start". */
1824 pc = get_frame_pc (this_frame);
1825 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1826 return UNWIND_OUTERMOST;
1828 /* If we've hit a wall, stop. */
1829 if (cache->prev_sp == 0)
1830 return UNWIND_OUTERMOST;
1832 return UNWIND_NO_REASON;
1835 /* Our frame ID for a normal frame is the current function's starting PC
1836 and the caller's SP when we were called. */
1839 arm_prologue_this_id (struct frame_info *this_frame,
1841 struct frame_id *this_id)
1843 struct arm_prologue_cache *cache;
1847 if (*this_cache == NULL)
1848 *this_cache = arm_make_prologue_cache (this_frame);
1849 cache = (struct arm_prologue_cache *) *this_cache;
1851 /* Use function start address as part of the frame ID. If we cannot
1852 identify the start address (due to missing symbol information),
1853 fall back to just using the current PC. */
1854 pc = get_frame_pc (this_frame);
1855 func = get_frame_func (this_frame);
1859 id = frame_id_build (cache->prev_sp, func);
1863 static struct value *
1864 arm_prologue_prev_register (struct frame_info *this_frame,
1868 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1869 struct arm_prologue_cache *cache;
1871 if (*this_cache == NULL)
1872 *this_cache = arm_make_prologue_cache (this_frame);
1873 cache = (struct arm_prologue_cache *) *this_cache;
1875 /* If we are asked to unwind the PC, then we need to return the LR
1876 instead. The prologue may save PC, but it will point into this
1877 frame's prologue, not the next frame's resume location. Also
1878 strip the saved T bit. A valid LR may have the low bit set, but
1879 a valid PC never does. */
1880 if (prev_regnum == ARM_PC_REGNUM)
1884 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1885 return frame_unwind_got_constant (this_frame, prev_regnum,
1886 arm_addr_bits_remove (gdbarch, lr));
1889 /* SP is generally not saved to the stack, but this frame is
1890 identified by the next frame's stack pointer at the time of the call.
1891 The value was already reconstructed into PREV_SP. */
1892 if (prev_regnum == ARM_SP_REGNUM)
1893 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1895 /* The CPSR may have been changed by the call instruction and by the
1896 called function. The only bit we can reconstruct is the T bit,
1897 by checking the low bit of LR as of the call. This is a reliable
1898 indicator of Thumb-ness except for some ARM v4T pre-interworking
1899 Thumb code, which could get away with a clear low bit as long as
1900 the called function did not use bx. Guess that all other
1901 bits are unchanged; the condition flags are presumably lost,
1902 but the processor status is likely valid. */
1903 if (prev_regnum == ARM_PS_REGNUM)
1906 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
1908 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1909 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1910 if (IS_THUMB_ADDR (lr))
1914 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1917 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1921 struct frame_unwind arm_prologue_unwind = {
1923 arm_prologue_unwind_stop_reason,
1924 arm_prologue_this_id,
1925 arm_prologue_prev_register,
1927 default_frame_sniffer
1930 /* Maintain a list of ARM exception table entries per objfile, similar to the
1931 list of mapping symbols. We only cache entries for standard ARM-defined
1932 personality routines; the cache will contain only the frame unwinding
1933 instructions associated with the entry (not the descriptors). */
1935 static const struct objfile_data *arm_exidx_data_key;
1937 struct arm_exidx_entry
1942 typedef struct arm_exidx_entry arm_exidx_entry_s;
1943 DEF_VEC_O(arm_exidx_entry_s);
1945 struct arm_exidx_data
1947 VEC(arm_exidx_entry_s) **section_maps;
1951 arm_exidx_data_free (struct objfile *objfile, void *arg)
1953 struct arm_exidx_data *data = (struct arm_exidx_data *) arg;
1956 for (i = 0; i < objfile->obfd->section_count; i++)
1957 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
1961 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
1962 const struct arm_exidx_entry *rhs)
1964 return lhs->addr < rhs->addr;
1967 static struct obj_section *
1968 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
1970 struct obj_section *osect;
1972 ALL_OBJFILE_OSECTIONS (objfile, osect)
1973 if (bfd_get_section_flags (objfile->obfd,
1974 osect->the_bfd_section) & SEC_ALLOC)
1976 bfd_vma start, size;
1977 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
1978 size = bfd_get_section_size (osect->the_bfd_section);
1980 if (start <= vma && vma < start + size)
1987 /* Parse contents of exception table and exception index sections
1988 of OBJFILE, and fill in the exception table entry cache.
1990 For each entry that refers to a standard ARM-defined personality
1991 routine, extract the frame unwinding instructions (from either
1992 the index or the table section). The unwinding instructions
1994 - extracting them from the rest of the table data
1995 - converting to host endianness
1996 - appending the implicit 0xb0 ("Finish") code
1998 The extracted and normalized instructions are stored for later
1999 retrieval by the arm_find_exidx_entry routine. */
2002 arm_exidx_new_objfile (struct objfile *objfile)
2004 struct cleanup *cleanups;
2005 struct arm_exidx_data *data;
2006 asection *exidx, *extab;
2007 bfd_vma exidx_vma = 0, extab_vma = 0;
2008 bfd_size_type exidx_size = 0, extab_size = 0;
2009 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2012 /* If we've already touched this file, do nothing. */
2013 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2015 cleanups = make_cleanup (null_cleanup, NULL);
2017 /* Read contents of exception table and index. */
2018 exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
2021 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2022 exidx_size = bfd_get_section_size (exidx);
2023 exidx_data = (gdb_byte *) xmalloc (exidx_size);
2024 make_cleanup (xfree, exidx_data);
2026 if (!bfd_get_section_contents (objfile->obfd, exidx,
2027 exidx_data, 0, exidx_size))
2029 do_cleanups (cleanups);
2034 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2037 extab_vma = bfd_section_vma (objfile->obfd, extab);
2038 extab_size = bfd_get_section_size (extab);
2039 extab_data = (gdb_byte *) xmalloc (extab_size);
2040 make_cleanup (xfree, extab_data);
2042 if (!bfd_get_section_contents (objfile->obfd, extab,
2043 extab_data, 0, extab_size))
2045 do_cleanups (cleanups);
2050 /* Allocate exception table data structure. */
2051 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2052 set_objfile_data (objfile, arm_exidx_data_key, data);
2053 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2054 objfile->obfd->section_count,
2055 VEC(arm_exidx_entry_s) *);
2057 /* Fill in exception table. */
2058 for (i = 0; i < exidx_size / 8; i++)
2060 struct arm_exidx_entry new_exidx_entry;
2061 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2062 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2063 bfd_vma addr = 0, word = 0;
2064 int n_bytes = 0, n_words = 0;
2065 struct obj_section *sec;
2066 gdb_byte *entry = NULL;
2068 /* Extract address of start of function. */
2069 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2070 idx += exidx_vma + i * 8;
2072 /* Find section containing function and compute section offset. */
2073 sec = arm_obj_section_from_vma (objfile, idx);
2076 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2078 /* Determine address of exception table entry. */
2081 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2083 else if ((val & 0xff000000) == 0x80000000)
2085 /* Exception table entry embedded in .ARM.exidx
2086 -- must be short form. */
2090 else if (!(val & 0x80000000))
2092 /* Exception table entry in .ARM.extab. */
2093 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2094 addr += exidx_vma + i * 8 + 4;
2096 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2098 word = bfd_h_get_32 (objfile->obfd,
2099 extab_data + addr - extab_vma);
2102 if ((word & 0xff000000) == 0x80000000)
2107 else if ((word & 0xff000000) == 0x81000000
2108 || (word & 0xff000000) == 0x82000000)
2112 n_words = ((word >> 16) & 0xff);
2114 else if (!(word & 0x80000000))
2117 struct obj_section *pers_sec;
2118 int gnu_personality = 0;
2120 /* Custom personality routine. */
2121 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2122 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2124 /* Check whether we've got one of the variants of the
2125 GNU personality routines. */
2126 pers_sec = arm_obj_section_from_vma (objfile, pers);
2129 static const char *personality[] =
2131 "__gcc_personality_v0",
2132 "__gxx_personality_v0",
2133 "__gcj_personality_v0",
2134 "__gnu_objc_personality_v0",
2138 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2141 for (k = 0; personality[k]; k++)
2142 if (lookup_minimal_symbol_by_pc_name
2143 (pc, personality[k], objfile))
2145 gnu_personality = 1;
2150 /* If so, the next word contains a word count in the high
2151 byte, followed by the same unwind instructions as the
2152 pre-defined forms. */
2154 && addr + 4 <= extab_vma + extab_size)
2156 word = bfd_h_get_32 (objfile->obfd,
2157 extab_data + addr - extab_vma);
2160 n_words = ((word >> 24) & 0xff);
2166 /* Sanity check address. */
2168 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2169 n_words = n_bytes = 0;
2171 /* The unwind instructions reside in WORD (only the N_BYTES least
2172 significant bytes are valid), followed by N_WORDS words in the
2173 extab section starting at ADDR. */
2174 if (n_bytes || n_words)
2177 = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack,
2178 n_bytes + n_words * 4 + 1);
2181 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2185 word = bfd_h_get_32 (objfile->obfd,
2186 extab_data + addr - extab_vma);
2189 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2190 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2191 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2192 *p++ = (gdb_byte) (word & 0xff);
2195 /* Implied "Finish" to terminate the list. */
2199 /* Push entry onto vector. They are guaranteed to always
2200 appear in order of increasing addresses. */
2201 new_exidx_entry.addr = idx;
2202 new_exidx_entry.entry = entry;
2203 VEC_safe_push (arm_exidx_entry_s,
2204 data->section_maps[sec->the_bfd_section->index],
2208 do_cleanups (cleanups);
2211 /* Search for the exception table entry covering MEMADDR. If one is found,
2212 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2213 set *START to the start of the region covered by this entry. */
2216 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2218 struct obj_section *sec;
2220 sec = find_pc_section (memaddr);
2223 struct arm_exidx_data *data;
2224 VEC(arm_exidx_entry_s) *map;
2225 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2228 data = ((struct arm_exidx_data *)
2229 objfile_data (sec->objfile, arm_exidx_data_key));
2232 map = data->section_maps[sec->the_bfd_section->index];
2233 if (!VEC_empty (arm_exidx_entry_s, map))
2235 struct arm_exidx_entry *map_sym;
2237 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2238 arm_compare_exidx_entries);
2240 /* VEC_lower_bound finds the earliest ordered insertion
2241 point. If the following symbol starts at this exact
2242 address, we use that; otherwise, the preceding
2243 exception table entry covers this address. */
2244 if (idx < VEC_length (arm_exidx_entry_s, map))
2246 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2247 if (map_sym->addr == map_key.addr)
2250 *start = map_sym->addr + obj_section_addr (sec);
2251 return map_sym->entry;
2257 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2259 *start = map_sym->addr + obj_section_addr (sec);
2260 return map_sym->entry;
2269 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2270 instruction list from the ARM exception table entry ENTRY, allocate and
2271 return a prologue cache structure describing how to unwind this frame.
2273 Return NULL if the unwinding instruction list contains a "spare",
2274 "reserved" or "refuse to unwind" instruction as defined in section
2275 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2276 for the ARM Architecture" document. */
2278 static struct arm_prologue_cache *
2279 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2284 struct arm_prologue_cache *cache;
2285 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2286 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2292 /* Whenever we reload SP, we actually have to retrieve its
2293 actual value in the current frame. */
2296 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2298 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2299 vsp = get_frame_register_unsigned (this_frame, reg);
2303 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2304 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2310 /* Decode next unwind instruction. */
2313 if ((insn & 0xc0) == 0)
2315 int offset = insn & 0x3f;
2316 vsp += (offset << 2) + 4;
2318 else if ((insn & 0xc0) == 0x40)
2320 int offset = insn & 0x3f;
2321 vsp -= (offset << 2) + 4;
2323 else if ((insn & 0xf0) == 0x80)
2325 int mask = ((insn & 0xf) << 8) | *entry++;
2328 /* The special case of an all-zero mask identifies
2329 "Refuse to unwind". We return NULL to fall back
2330 to the prologue analyzer. */
2334 /* Pop registers r4..r15 under mask. */
2335 for (i = 0; i < 12; i++)
2336 if (mask & (1 << i))
2338 cache->saved_regs[4 + i].addr = vsp;
2342 /* Special-case popping SP -- we need to reload vsp. */
2343 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2346 else if ((insn & 0xf0) == 0x90)
2348 int reg = insn & 0xf;
2350 /* Reserved cases. */
2351 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2354 /* Set SP from another register and mark VSP for reload. */
2355 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2358 else if ((insn & 0xf0) == 0xa0)
2360 int count = insn & 0x7;
2361 int pop_lr = (insn & 0x8) != 0;
2364 /* Pop r4..r[4+count]. */
2365 for (i = 0; i <= count; i++)
2367 cache->saved_regs[4 + i].addr = vsp;
2371 /* If indicated by flag, pop LR as well. */
2374 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2378 else if (insn == 0xb0)
2380 /* We could only have updated PC by popping into it; if so, it
2381 will show up as address. Otherwise, copy LR into PC. */
2382 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2383 cache->saved_regs[ARM_PC_REGNUM]
2384 = cache->saved_regs[ARM_LR_REGNUM];
2389 else if (insn == 0xb1)
2391 int mask = *entry++;
2394 /* All-zero mask and mask >= 16 is "spare". */
2395 if (mask == 0 || mask >= 16)
2398 /* Pop r0..r3 under mask. */
2399 for (i = 0; i < 4; i++)
2400 if (mask & (1 << i))
2402 cache->saved_regs[i].addr = vsp;
2406 else if (insn == 0xb2)
2408 ULONGEST offset = 0;
2413 offset |= (*entry & 0x7f) << shift;
2416 while (*entry++ & 0x80);
2418 vsp += 0x204 + (offset << 2);
2420 else if (insn == 0xb3)
2422 int start = *entry >> 4;
2423 int count = (*entry++) & 0xf;
2426 /* Only registers D0..D15 are valid here. */
2427 if (start + count >= 16)
2430 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2431 for (i = 0; i <= count; i++)
2433 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2437 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2440 else if ((insn & 0xf8) == 0xb8)
2442 int count = insn & 0x7;
2445 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2446 for (i = 0; i <= count; i++)
2448 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2452 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2455 else if (insn == 0xc6)
2457 int start = *entry >> 4;
2458 int count = (*entry++) & 0xf;
2461 /* Only registers WR0..WR15 are valid. */
2462 if (start + count >= 16)
2465 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2466 for (i = 0; i <= count; i++)
2468 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2472 else if (insn == 0xc7)
2474 int mask = *entry++;
2477 /* All-zero mask and mask >= 16 is "spare". */
2478 if (mask == 0 || mask >= 16)
2481 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2482 for (i = 0; i < 4; i++)
2483 if (mask & (1 << i))
2485 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2489 else if ((insn & 0xf8) == 0xc0)
2491 int count = insn & 0x7;
2494 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2495 for (i = 0; i <= count; i++)
2497 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2501 else if (insn == 0xc8)
2503 int start = *entry >> 4;
2504 int count = (*entry++) & 0xf;
2507 /* Only registers D0..D31 are valid. */
2508 if (start + count >= 16)
2511 /* Pop VFP double-precision registers
2512 D[16+start]..D[16+start+count]. */
2513 for (i = 0; i <= count; i++)
2515 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2519 else if (insn == 0xc9)
2521 int start = *entry >> 4;
2522 int count = (*entry++) & 0xf;
2525 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2526 for (i = 0; i <= count; i++)
2528 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2532 else if ((insn & 0xf8) == 0xd0)
2534 int count = insn & 0x7;
2537 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2538 for (i = 0; i <= count; i++)
2540 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2546 /* Everything else is "spare". */
2551 /* If we restore SP from a register, assume this was the frame register.
2552 Otherwise just fall back to SP as frame register. */
2553 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2554 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2556 cache->framereg = ARM_SP_REGNUM;
2558 /* Determine offset to previous frame. */
2560 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2562 /* We already got the previous SP. */
2563 cache->prev_sp = vsp;
2568 /* Unwinding via ARM exception table entries. Note that the sniffer
2569 already computes a filled-in prologue cache, which is then used
2570 with the same arm_prologue_this_id and arm_prologue_prev_register
2571 routines also used for prologue-parsing based unwinding. */
2574 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2575 struct frame_info *this_frame,
2576 void **this_prologue_cache)
2578 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2579 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2580 CORE_ADDR addr_in_block, exidx_region, func_start;
2581 struct arm_prologue_cache *cache;
2584 /* See if we have an ARM exception table entry covering this address. */
2585 addr_in_block = get_frame_address_in_block (this_frame);
2586 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2590 /* The ARM exception table does not describe unwind information
2591 for arbitrary PC values, but is guaranteed to be correct only
2592 at call sites. We have to decide here whether we want to use
2593 ARM exception table information for this frame, or fall back
2594 to using prologue parsing. (Note that if we have DWARF CFI,
2595 this sniffer isn't even called -- CFI is always preferred.)
2597 Before we make this decision, however, we check whether we
2598 actually have *symbol* information for the current frame.
2599 If not, prologue parsing would not work anyway, so we might
2600 as well use the exception table and hope for the best. */
2601 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2605 /* If the next frame is "normal", we are at a call site in this
2606 frame, so exception information is guaranteed to be valid. */
2607 if (get_next_frame (this_frame)
2608 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2611 /* We also assume exception information is valid if we're currently
2612 blocked in a system call. The system library is supposed to
2613 ensure this, so that e.g. pthread cancellation works. */
2614 if (arm_frame_is_thumb (this_frame))
2618 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2619 byte_order_for_code, &insn)
2620 && (insn & 0xff00) == 0xdf00 /* svc */)
2627 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2628 byte_order_for_code, &insn)
2629 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2633 /* Bail out if we don't know that exception information is valid. */
2637 /* The ARM exception index does not mark the *end* of the region
2638 covered by the entry, and some functions will not have any entry.
2639 To correctly recognize the end of the covered region, the linker
2640 should have inserted dummy records with a CANTUNWIND marker.
2642 Unfortunately, current versions of GNU ld do not reliably do
2643 this, and thus we may have found an incorrect entry above.
2644 As a (temporary) sanity check, we only use the entry if it
2645 lies *within* the bounds of the function. Note that this check
2646 might reject perfectly valid entries that just happen to cover
2647 multiple functions; therefore this check ought to be removed
2648 once the linker is fixed. */
2649 if (func_start > exidx_region)
2653 /* Decode the list of unwinding instructions into a prologue cache.
2654 Note that this may fail due to e.g. a "refuse to unwind" code. */
2655 cache = arm_exidx_fill_cache (this_frame, entry);
2659 *this_prologue_cache = cache;
2663 struct frame_unwind arm_exidx_unwind = {
2665 default_frame_unwind_stop_reason,
2666 arm_prologue_this_id,
2667 arm_prologue_prev_register,
2669 arm_exidx_unwind_sniffer
2672 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2673 trampoline, return the target PC. Otherwise return 0.
2675 void call0a (char c, short s, int i, long l) {}
2679 (*pointer_to_call0a) (c, s, i, l);
2682 Instead of calling a stub library function _call_via_xx (xx is
2683 the register name), GCC may inline the trampoline in the object
2684 file as below (register r2 has the address of call0a).
2687 .type main, %function
2696 The trampoline 'bx r2' doesn't belong to main. */
2699 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2701 /* The heuristics of recognizing such trampoline is that FRAME is
2702 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2703 if (arm_frame_is_thumb (frame))
2707 if (target_read_memory (pc, buf, 2) == 0)
2709 struct gdbarch *gdbarch = get_frame_arch (frame);
2710 enum bfd_endian byte_order_for_code
2711 = gdbarch_byte_order_for_code (gdbarch);
2713 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2715 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2718 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2720 /* Clear the LSB so that gdb core sets step-resume
2721 breakpoint at the right address. */
2722 return UNMAKE_THUMB_ADDR (dest);
2730 static struct arm_prologue_cache *
2731 arm_make_stub_cache (struct frame_info *this_frame)
2733 struct arm_prologue_cache *cache;
2735 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2736 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2738 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2743 /* Our frame ID for a stub frame is the current SP and LR. */
2746 arm_stub_this_id (struct frame_info *this_frame,
2748 struct frame_id *this_id)
2750 struct arm_prologue_cache *cache;
2752 if (*this_cache == NULL)
2753 *this_cache = arm_make_stub_cache (this_frame);
2754 cache = (struct arm_prologue_cache *) *this_cache;
2756 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2760 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2761 struct frame_info *this_frame,
2762 void **this_prologue_cache)
2764 CORE_ADDR addr_in_block;
2766 CORE_ADDR pc, start_addr;
2769 addr_in_block = get_frame_address_in_block (this_frame);
2770 pc = get_frame_pc (this_frame);
2771 if (in_plt_section (addr_in_block)
2772 /* We also use the stub winder if the target memory is unreadable
2773 to avoid having the prologue unwinder trying to read it. */
2774 || target_read_memory (pc, dummy, 4) != 0)
2777 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2778 && arm_skip_bx_reg (this_frame, pc) != 0)
2784 struct frame_unwind arm_stub_unwind = {
2786 default_frame_unwind_stop_reason,
2788 arm_prologue_prev_register,
2790 arm_stub_unwind_sniffer
2793 /* Put here the code to store, into CACHE->saved_regs, the addresses
2794 of the saved registers of frame described by THIS_FRAME. CACHE is
2797 static struct arm_prologue_cache *
2798 arm_m_exception_cache (struct frame_info *this_frame)
2800 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2801 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2802 struct arm_prologue_cache *cache;
2803 CORE_ADDR unwound_sp;
2806 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2807 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2809 unwound_sp = get_frame_register_unsigned (this_frame,
2812 /* The hardware saves eight 32-bit words, comprising xPSR,
2813 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2814 "B1.5.6 Exception entry behavior" in
2815 "ARMv7-M Architecture Reference Manual". */
2816 cache->saved_regs[0].addr = unwound_sp;
2817 cache->saved_regs[1].addr = unwound_sp + 4;
2818 cache->saved_regs[2].addr = unwound_sp + 8;
2819 cache->saved_regs[3].addr = unwound_sp + 12;
2820 cache->saved_regs[12].addr = unwound_sp + 16;
2821 cache->saved_regs[14].addr = unwound_sp + 20;
2822 cache->saved_regs[15].addr = unwound_sp + 24;
2823 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2825 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2826 aligner between the top of the 32-byte stack frame and the
2827 previous context's stack pointer. */
2828 cache->prev_sp = unwound_sp + 32;
2829 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2830 && (xpsr & (1 << 9)) != 0)
2831 cache->prev_sp += 4;
2836 /* Implementation of function hook 'this_id' in
2837 'struct frame_uwnind'. */
2840 arm_m_exception_this_id (struct frame_info *this_frame,
2842 struct frame_id *this_id)
2844 struct arm_prologue_cache *cache;
2846 if (*this_cache == NULL)
2847 *this_cache = arm_m_exception_cache (this_frame);
2848 cache = (struct arm_prologue_cache *) *this_cache;
2850 /* Our frame ID for a stub frame is the current SP and LR. */
2851 *this_id = frame_id_build (cache->prev_sp,
2852 get_frame_pc (this_frame));
2855 /* Implementation of function hook 'prev_register' in
2856 'struct frame_uwnind'. */
2858 static struct value *
2859 arm_m_exception_prev_register (struct frame_info *this_frame,
2863 struct arm_prologue_cache *cache;
2865 if (*this_cache == NULL)
2866 *this_cache = arm_m_exception_cache (this_frame);
2867 cache = (struct arm_prologue_cache *) *this_cache;
2869 /* The value was already reconstructed into PREV_SP. */
2870 if (prev_regnum == ARM_SP_REGNUM)
2871 return frame_unwind_got_constant (this_frame, prev_regnum,
2874 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2878 /* Implementation of function hook 'sniffer' in
2879 'struct frame_uwnind'. */
2882 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
2883 struct frame_info *this_frame,
2884 void **this_prologue_cache)
2886 CORE_ADDR this_pc = get_frame_pc (this_frame);
2888 /* No need to check is_m; this sniffer is only registered for
2889 M-profile architectures. */
2891 /* Exception frames return to one of these magic PCs. Other values
2892 are not defined as of v7-M. See details in "B1.5.8 Exception
2893 return behavior" in "ARMv7-M Architecture Reference Manual". */
2894 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
2895 || this_pc == 0xfffffffd)
2901 /* Frame unwinder for M-profile exceptions. */
2903 struct frame_unwind arm_m_exception_unwind =
2906 default_frame_unwind_stop_reason,
2907 arm_m_exception_this_id,
2908 arm_m_exception_prev_register,
2910 arm_m_exception_unwind_sniffer
2914 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
2916 struct arm_prologue_cache *cache;
2918 if (*this_cache == NULL)
2919 *this_cache = arm_make_prologue_cache (this_frame);
2920 cache = (struct arm_prologue_cache *) *this_cache;
2922 return cache->prev_sp - cache->framesize;
2925 struct frame_base arm_normal_base = {
2926 &arm_prologue_unwind,
2927 arm_normal_frame_base,
2928 arm_normal_frame_base,
2929 arm_normal_frame_base
2932 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2933 dummy frame. The frame ID's base needs to match the TOS value
2934 saved by save_dummy_frame_tos() and returned from
2935 arm_push_dummy_call, and the PC needs to match the dummy frame's
2938 static struct frame_id
2939 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2941 return frame_id_build (get_frame_register_unsigned (this_frame,
2943 get_frame_pc (this_frame));
2946 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2947 be used to construct the previous frame's ID, after looking up the
2948 containing function). */
2951 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
2954 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
2955 return arm_addr_bits_remove (gdbarch, pc);
2959 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
2961 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
2964 static struct value *
2965 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
2968 struct gdbarch * gdbarch = get_frame_arch (this_frame);
2970 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2975 /* The PC is normally copied from the return column, which
2976 describes saves of LR. However, that version may have an
2977 extra bit set to indicate Thumb state. The bit is not
2979 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2980 return frame_unwind_got_constant (this_frame, regnum,
2981 arm_addr_bits_remove (gdbarch, lr));
2984 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
2985 cpsr = get_frame_register_unsigned (this_frame, regnum);
2986 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2987 if (IS_THUMB_ADDR (lr))
2991 return frame_unwind_got_constant (this_frame, regnum, cpsr);
2994 internal_error (__FILE__, __LINE__,
2995 _("Unexpected register %d"), regnum);
3000 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3001 struct dwarf2_frame_state_reg *reg,
3002 struct frame_info *this_frame)
3008 reg->how = DWARF2_FRAME_REG_FN;
3009 reg->loc.fn = arm_dwarf2_prev_register;
3012 reg->how = DWARF2_FRAME_REG_CFA;
3017 /* Implement the stack_frame_destroyed_p gdbarch method. */
3020 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3022 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3023 unsigned int insn, insn2;
3024 int found_return = 0, found_stack_adjust = 0;
3025 CORE_ADDR func_start, func_end;
3029 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3032 /* The epilogue is a sequence of instructions along the following lines:
3034 - add stack frame size to SP or FP
3035 - [if frame pointer used] restore SP from FP
3036 - restore registers from SP [may include PC]
3037 - a return-type instruction [if PC wasn't already restored]
3039 In a first pass, we scan forward from the current PC and verify the
3040 instructions we find as compatible with this sequence, ending in a
3043 However, this is not sufficient to distinguish indirect function calls
3044 within a function from indirect tail calls in the epilogue in some cases.
3045 Therefore, if we didn't already find any SP-changing instruction during
3046 forward scan, we add a backward scanning heuristic to ensure we actually
3047 are in the epilogue. */
3050 while (scan_pc < func_end && !found_return)
3052 if (target_read_memory (scan_pc, buf, 2))
3056 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3058 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3060 else if (insn == 0x46f7) /* mov pc, lr */
3062 else if (thumb_instruction_restores_sp (insn))
3064 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3067 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3069 if (target_read_memory (scan_pc, buf, 2))
3073 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3075 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3077 if (insn2 & 0x8000) /* <registers> include PC. */
3080 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3081 && (insn2 & 0x0fff) == 0x0b04)
3083 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3086 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3087 && (insn2 & 0x0e00) == 0x0a00)
3099 /* Since any instruction in the epilogue sequence, with the possible
3100 exception of return itself, updates the stack pointer, we need to
3101 scan backwards for at most one instruction. Try either a 16-bit or
3102 a 32-bit instruction. This is just a heuristic, so we do not worry
3103 too much about false positives. */
3105 if (pc - 4 < func_start)
3107 if (target_read_memory (pc - 4, buf, 4))
3110 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3111 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3113 if (thumb_instruction_restores_sp (insn2))
3114 found_stack_adjust = 1;
3115 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3116 found_stack_adjust = 1;
3117 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3118 && (insn2 & 0x0fff) == 0x0b04)
3119 found_stack_adjust = 1;
3120 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3121 && (insn2 & 0x0e00) == 0x0a00)
3122 found_stack_adjust = 1;
3124 return found_stack_adjust;
3128 arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc)
3130 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3133 CORE_ADDR func_start, func_end;
3135 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3138 /* We are in the epilogue if the previous instruction was a stack
3139 adjustment and the next instruction is a possible return (bx, mov
3140 pc, or pop). We could have to scan backwards to find the stack
3141 adjustment, or forwards to find the return, but this is a decent
3142 approximation. First scan forwards. */
3145 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3146 if (bits (insn, 28, 31) != INST_NV)
3148 if ((insn & 0x0ffffff0) == 0x012fff10)
3151 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3154 else if ((insn & 0x0fff0000) == 0x08bd0000
3155 && (insn & 0x0000c000) != 0)
3156 /* POP (LDMIA), including PC or LR. */
3163 /* Scan backwards. This is just a heuristic, so do not worry about
3164 false positives from mode changes. */
3166 if (pc < func_start + 4)
3169 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3170 if (arm_instruction_restores_sp (insn))
3176 /* Implement the stack_frame_destroyed_p gdbarch method. */
3179 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3181 if (arm_pc_is_thumb (gdbarch, pc))
3182 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3184 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
3187 /* When arguments must be pushed onto the stack, they go on in reverse
3188 order. The code below implements a FILO (stack) to do this. */
3193 struct stack_item *prev;
3197 static struct stack_item *
3198 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
3200 struct stack_item *si;
3201 si = XNEW (struct stack_item);
3202 si->data = (gdb_byte *) xmalloc (len);
3205 memcpy (si->data, contents, len);
3209 static struct stack_item *
3210 pop_stack_item (struct stack_item *si)
3212 struct stack_item *dead = si;
3220 /* Return the alignment (in bytes) of the given type. */
3223 arm_type_align (struct type *t)
3229 t = check_typedef (t);
3230 switch (TYPE_CODE (t))
3233 /* Should never happen. */
3234 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3238 case TYPE_CODE_ENUM:
3242 case TYPE_CODE_RANGE:
3244 case TYPE_CODE_CHAR:
3245 case TYPE_CODE_BOOL:
3246 return TYPE_LENGTH (t);
3248 case TYPE_CODE_ARRAY:
3249 if (TYPE_VECTOR (t))
3251 /* Use the natural alignment for vector types (the same for
3252 scalar type), but the maximum alignment is 64-bit. */
3253 if (TYPE_LENGTH (t) > 8)
3256 return TYPE_LENGTH (t);
3259 return arm_type_align (TYPE_TARGET_TYPE (t));
3260 case TYPE_CODE_COMPLEX:
3261 return arm_type_align (TYPE_TARGET_TYPE (t));
3263 case TYPE_CODE_STRUCT:
3264 case TYPE_CODE_UNION:
3266 for (n = 0; n < TYPE_NFIELDS (t); n++)
3268 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3276 /* Possible base types for a candidate for passing and returning in
3279 enum arm_vfp_cprc_base_type
3288 /* The length of one element of base type B. */
3291 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3295 case VFP_CPRC_SINGLE:
3297 case VFP_CPRC_DOUBLE:
3299 case VFP_CPRC_VEC64:
3301 case VFP_CPRC_VEC128:
3304 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3309 /* The character ('s', 'd' or 'q') for the type of VFP register used
3310 for passing base type B. */
3313 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3317 case VFP_CPRC_SINGLE:
3319 case VFP_CPRC_DOUBLE:
3321 case VFP_CPRC_VEC64:
3323 case VFP_CPRC_VEC128:
3326 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3331 /* Determine whether T may be part of a candidate for passing and
3332 returning in VFP registers, ignoring the limit on the total number
3333 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3334 classification of the first valid component found; if it is not
3335 VFP_CPRC_UNKNOWN, all components must have the same classification
3336 as *BASE_TYPE. If it is found that T contains a type not permitted
3337 for passing and returning in VFP registers, a type differently
3338 classified from *BASE_TYPE, or two types differently classified
3339 from each other, return -1, otherwise return the total number of
3340 base-type elements found (possibly 0 in an empty structure or
3341 array). Vector types are not currently supported, matching the
3342 generic AAPCS support. */
3345 arm_vfp_cprc_sub_candidate (struct type *t,
3346 enum arm_vfp_cprc_base_type *base_type)
3348 t = check_typedef (t);
3349 switch (TYPE_CODE (t))
3352 switch (TYPE_LENGTH (t))
3355 if (*base_type == VFP_CPRC_UNKNOWN)
3356 *base_type = VFP_CPRC_SINGLE;
3357 else if (*base_type != VFP_CPRC_SINGLE)
3362 if (*base_type == VFP_CPRC_UNKNOWN)
3363 *base_type = VFP_CPRC_DOUBLE;
3364 else if (*base_type != VFP_CPRC_DOUBLE)
3373 case TYPE_CODE_COMPLEX:
3374 /* Arguments of complex T where T is one of the types float or
3375 double get treated as if they are implemented as:
3384 switch (TYPE_LENGTH (t))
3387 if (*base_type == VFP_CPRC_UNKNOWN)
3388 *base_type = VFP_CPRC_SINGLE;
3389 else if (*base_type != VFP_CPRC_SINGLE)
3394 if (*base_type == VFP_CPRC_UNKNOWN)
3395 *base_type = VFP_CPRC_DOUBLE;
3396 else if (*base_type != VFP_CPRC_DOUBLE)
3405 case TYPE_CODE_ARRAY:
3407 if (TYPE_VECTOR (t))
3409 /* A 64-bit or 128-bit containerized vector type are VFP
3411 switch (TYPE_LENGTH (t))
3414 if (*base_type == VFP_CPRC_UNKNOWN)
3415 *base_type = VFP_CPRC_VEC64;
3418 if (*base_type == VFP_CPRC_UNKNOWN)
3419 *base_type = VFP_CPRC_VEC128;
3430 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t),
3434 if (TYPE_LENGTH (t) == 0)
3436 gdb_assert (count == 0);
3439 else if (count == 0)
3441 unitlen = arm_vfp_cprc_unit_length (*base_type);
3442 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3443 return TYPE_LENGTH (t) / unitlen;
3448 case TYPE_CODE_STRUCT:
3453 for (i = 0; i < TYPE_NFIELDS (t); i++)
3455 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3457 if (sub_count == -1)
3461 if (TYPE_LENGTH (t) == 0)
3463 gdb_assert (count == 0);
3466 else if (count == 0)
3468 unitlen = arm_vfp_cprc_unit_length (*base_type);
3469 if (TYPE_LENGTH (t) != unitlen * count)
3474 case TYPE_CODE_UNION:
3479 for (i = 0; i < TYPE_NFIELDS (t); i++)
3481 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3483 if (sub_count == -1)
3485 count = (count > sub_count ? count : sub_count);
3487 if (TYPE_LENGTH (t) == 0)
3489 gdb_assert (count == 0);
3492 else if (count == 0)
3494 unitlen = arm_vfp_cprc_unit_length (*base_type);
3495 if (TYPE_LENGTH (t) != unitlen * count)
3507 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3508 if passed to or returned from a non-variadic function with the VFP
3509 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3510 *BASE_TYPE to the base type for T and *COUNT to the number of
3511 elements of that base type before returning. */
3514 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3517 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3518 int c = arm_vfp_cprc_sub_candidate (t, &b);
3519 if (c <= 0 || c > 4)
3526 /* Return 1 if the VFP ABI should be used for passing arguments to and
3527 returning values from a function of type FUNC_TYPE, 0
3531 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3533 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3534 /* Variadic functions always use the base ABI. Assume that functions
3535 without debug info are not variadic. */
3536 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3538 /* The VFP ABI is only supported as a variant of AAPCS. */
3539 if (tdep->arm_abi != ARM_ABI_AAPCS)
3541 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3544 /* We currently only support passing parameters in integer registers, which
3545 conforms with GCC's default model, and VFP argument passing following
3546 the VFP variant of AAPCS. Several other variants exist and
3547 we should probably support some of them based on the selected ABI. */
3550 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3551 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3552 struct value **args, CORE_ADDR sp, int struct_return,
3553 CORE_ADDR struct_addr)
3555 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3559 struct stack_item *si = NULL;
3562 unsigned vfp_regs_free = (1 << 16) - 1;
3564 /* Determine the type of this function and whether the VFP ABI
3566 ftype = check_typedef (value_type (function));
3567 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3568 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3569 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3571 /* Set the return address. For the ARM, the return breakpoint is
3572 always at BP_ADDR. */
3573 if (arm_pc_is_thumb (gdbarch, bp_addr))
3575 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3577 /* Walk through the list of args and determine how large a temporary
3578 stack is required. Need to take care here as structs may be
3579 passed on the stack, and we have to push them. */
3582 argreg = ARM_A1_REGNUM;
3585 /* The struct_return pointer occupies the first parameter
3586 passing register. */
3590 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3591 gdbarch_register_name (gdbarch, argreg),
3592 paddress (gdbarch, struct_addr));
3593 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3597 for (argnum = 0; argnum < nargs; argnum++)
3600 struct type *arg_type;
3601 struct type *target_type;
3602 enum type_code typecode;
3603 const bfd_byte *val;
3605 enum arm_vfp_cprc_base_type vfp_base_type;
3607 int may_use_core_reg = 1;
3609 arg_type = check_typedef (value_type (args[argnum]));
3610 len = TYPE_LENGTH (arg_type);
3611 target_type = TYPE_TARGET_TYPE (arg_type);
3612 typecode = TYPE_CODE (arg_type);
3613 val = value_contents (args[argnum]);
3615 align = arm_type_align (arg_type);
3616 /* Round alignment up to a whole number of words. */
3617 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3618 /* Different ABIs have different maximum alignments. */
3619 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3621 /* The APCS ABI only requires word alignment. */
3622 align = INT_REGISTER_SIZE;
3626 /* The AAPCS requires at most doubleword alignment. */
3627 if (align > INT_REGISTER_SIZE * 2)
3628 align = INT_REGISTER_SIZE * 2;
3632 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3640 /* Because this is a CPRC it cannot go in a core register or
3641 cause a core register to be skipped for alignment.
3642 Either it goes in VFP registers and the rest of this loop
3643 iteration is skipped for this argument, or it goes on the
3644 stack (and the stack alignment code is correct for this
3646 may_use_core_reg = 0;
3648 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3649 shift = unit_length / 4;
3650 mask = (1 << (shift * vfp_base_count)) - 1;
3651 for (regno = 0; regno < 16; regno += shift)
3652 if (((vfp_regs_free >> regno) & mask) == mask)
3661 vfp_regs_free &= ~(mask << regno);
3662 reg_scaled = regno / shift;
3663 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3664 for (i = 0; i < vfp_base_count; i++)
3668 if (reg_char == 'q')
3669 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3670 val + i * unit_length);
3673 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3674 reg_char, reg_scaled + i);
3675 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3677 regcache_cooked_write (regcache, regnum,
3678 val + i * unit_length);
3685 /* This CPRC could not go in VFP registers, so all VFP
3686 registers are now marked as used. */
3691 /* Push stack padding for dowubleword alignment. */
3692 if (nstack & (align - 1))
3694 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3695 nstack += INT_REGISTER_SIZE;
3698 /* Doubleword aligned quantities must go in even register pairs. */
3699 if (may_use_core_reg
3700 && argreg <= ARM_LAST_ARG_REGNUM
3701 && align > INT_REGISTER_SIZE
3705 /* If the argument is a pointer to a function, and it is a
3706 Thumb function, create a LOCAL copy of the value and set
3707 the THUMB bit in it. */
3708 if (TYPE_CODE_PTR == typecode
3709 && target_type != NULL
3710 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3712 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3713 if (arm_pc_is_thumb (gdbarch, regval))
3715 bfd_byte *copy = (bfd_byte *) alloca (len);
3716 store_unsigned_integer (copy, len, byte_order,
3717 MAKE_THUMB_ADDR (regval));
3722 /* Copy the argument to general registers or the stack in
3723 register-sized pieces. Large arguments are split between
3724 registers and stack. */
3727 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3729 = extract_unsigned_integer (val, partial_len, byte_order);
3731 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3733 /* The argument is being passed in a general purpose
3735 if (byte_order == BFD_ENDIAN_BIG)
3736 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3738 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3740 gdbarch_register_name
3742 phex (regval, INT_REGISTER_SIZE));
3743 regcache_cooked_write_unsigned (regcache, argreg, regval);
3748 gdb_byte buf[INT_REGISTER_SIZE];
3750 memset (buf, 0, sizeof (buf));
3751 store_unsigned_integer (buf, partial_len, byte_order, regval);
3753 /* Push the arguments onto the stack. */
3755 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3757 si = push_stack_item (si, buf, INT_REGISTER_SIZE);
3758 nstack += INT_REGISTER_SIZE;
3765 /* If we have an odd number of words to push, then decrement the stack
3766 by one word now, so first stack argument will be dword aligned. */
3773 write_memory (sp, si->data, si->len);
3774 si = pop_stack_item (si);
3777 /* Finally, update teh SP register. */
3778 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3784 /* Always align the frame to an 8-byte boundary. This is required on
3785 some platforms and harmless on the rest. */
3788 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3790 /* Align the stack to eight bytes. */
3791 return sp & ~ (CORE_ADDR) 7;
3795 print_fpu_flags (struct ui_file *file, int flags)
3797 if (flags & (1 << 0))
3798 fputs_filtered ("IVO ", file);
3799 if (flags & (1 << 1))
3800 fputs_filtered ("DVZ ", file);
3801 if (flags & (1 << 2))
3802 fputs_filtered ("OFL ", file);
3803 if (flags & (1 << 3))
3804 fputs_filtered ("UFL ", file);
3805 if (flags & (1 << 4))
3806 fputs_filtered ("INX ", file);
3807 fputc_filtered ('\n', file);
3810 /* Print interesting information about the floating point processor
3811 (if present) or emulator. */
3813 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3814 struct frame_info *frame, const char *args)
3816 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3819 type = (status >> 24) & 127;
3820 if (status & (1 << 31))
3821 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3823 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3824 /* i18n: [floating point unit] mask */
3825 fputs_filtered (_("mask: "), file);
3826 print_fpu_flags (file, status >> 16);
3827 /* i18n: [floating point unit] flags */
3828 fputs_filtered (_("flags: "), file);
3829 print_fpu_flags (file, status);
3832 /* Construct the ARM extended floating point type. */
3833 static struct type *
3834 arm_ext_type (struct gdbarch *gdbarch)
3836 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3838 if (!tdep->arm_ext_type)
3840 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3841 floatformats_arm_ext);
3843 return tdep->arm_ext_type;
3846 static struct type *
3847 arm_neon_double_type (struct gdbarch *gdbarch)
3849 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3851 if (tdep->neon_double_type == NULL)
3853 struct type *t, *elem;
3855 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3857 elem = builtin_type (gdbarch)->builtin_uint8;
3858 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3859 elem = builtin_type (gdbarch)->builtin_uint16;
3860 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3861 elem = builtin_type (gdbarch)->builtin_uint32;
3862 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3863 elem = builtin_type (gdbarch)->builtin_uint64;
3864 append_composite_type_field (t, "u64", elem);
3865 elem = builtin_type (gdbarch)->builtin_float;
3866 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3867 elem = builtin_type (gdbarch)->builtin_double;
3868 append_composite_type_field (t, "f64", elem);
3870 TYPE_VECTOR (t) = 1;
3871 TYPE_NAME (t) = "neon_d";
3872 tdep->neon_double_type = t;
3875 return tdep->neon_double_type;
3878 /* FIXME: The vector types are not correctly ordered on big-endian
3879 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3880 bits of d0 - regardless of what unit size is being held in d0. So
3881 the offset of the first uint8 in d0 is 7, but the offset of the
3882 first float is 4. This code works as-is for little-endian
3885 static struct type *
3886 arm_neon_quad_type (struct gdbarch *gdbarch)
3888 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3890 if (tdep->neon_quad_type == NULL)
3892 struct type *t, *elem;
3894 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3896 elem = builtin_type (gdbarch)->builtin_uint8;
3897 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3898 elem = builtin_type (gdbarch)->builtin_uint16;
3899 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3900 elem = builtin_type (gdbarch)->builtin_uint32;
3901 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3902 elem = builtin_type (gdbarch)->builtin_uint64;
3903 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
3904 elem = builtin_type (gdbarch)->builtin_float;
3905 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
3906 elem = builtin_type (gdbarch)->builtin_double;
3907 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
3909 TYPE_VECTOR (t) = 1;
3910 TYPE_NAME (t) = "neon_q";
3911 tdep->neon_quad_type = t;
3914 return tdep->neon_quad_type;
3917 /* Return the GDB type object for the "standard" data type of data in
3920 static struct type *
3921 arm_register_type (struct gdbarch *gdbarch, int regnum)
3923 int num_regs = gdbarch_num_regs (gdbarch);
3925 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
3926 && regnum >= num_regs && regnum < num_regs + 32)
3927 return builtin_type (gdbarch)->builtin_float;
3929 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
3930 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
3931 return arm_neon_quad_type (gdbarch);
3933 /* If the target description has register information, we are only
3934 in this function so that we can override the types of
3935 double-precision registers for NEON. */
3936 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
3938 struct type *t = tdesc_register_type (gdbarch, regnum);
3940 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
3941 && TYPE_CODE (t) == TYPE_CODE_FLT
3942 && gdbarch_tdep (gdbarch)->have_neon)
3943 return arm_neon_double_type (gdbarch);
3948 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
3950 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
3951 return builtin_type (gdbarch)->builtin_void;
3953 return arm_ext_type (gdbarch);
3955 else if (regnum == ARM_SP_REGNUM)
3956 return builtin_type (gdbarch)->builtin_data_ptr;
3957 else if (regnum == ARM_PC_REGNUM)
3958 return builtin_type (gdbarch)->builtin_func_ptr;
3959 else if (regnum >= ARRAY_SIZE (arm_register_names))
3960 /* These registers are only supported on targets which supply
3961 an XML description. */
3962 return builtin_type (gdbarch)->builtin_int0;
3964 return builtin_type (gdbarch)->builtin_uint32;
3967 /* Map a DWARF register REGNUM onto the appropriate GDB register
3971 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3973 /* Core integer regs. */
3974 if (reg >= 0 && reg <= 15)
3977 /* Legacy FPA encoding. These were once used in a way which
3978 overlapped with VFP register numbering, so their use is
3979 discouraged, but GDB doesn't support the ARM toolchain
3980 which used them for VFP. */
3981 if (reg >= 16 && reg <= 23)
3982 return ARM_F0_REGNUM + reg - 16;
3984 /* New assignments for the FPA registers. */
3985 if (reg >= 96 && reg <= 103)
3986 return ARM_F0_REGNUM + reg - 96;
3988 /* WMMX register assignments. */
3989 if (reg >= 104 && reg <= 111)
3990 return ARM_WCGR0_REGNUM + reg - 104;
3992 if (reg >= 112 && reg <= 127)
3993 return ARM_WR0_REGNUM + reg - 112;
3995 if (reg >= 192 && reg <= 199)
3996 return ARM_WC0_REGNUM + reg - 192;
3998 /* VFP v2 registers. A double precision value is actually
3999 in d1 rather than s2, but the ABI only defines numbering
4000 for the single precision registers. This will "just work"
4001 in GDB for little endian targets (we'll read eight bytes,
4002 starting in s0 and then progressing to s1), but will be
4003 reversed on big endian targets with VFP. This won't
4004 be a problem for the new Neon quad registers; you're supposed
4005 to use DW_OP_piece for those. */
4006 if (reg >= 64 && reg <= 95)
4010 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4011 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4015 /* VFP v3 / Neon registers. This range is also used for VFP v2
4016 registers, except that it now describes d0 instead of s0. */
4017 if (reg >= 256 && reg <= 287)
4021 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4022 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4029 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4031 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4034 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4036 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4037 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4039 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4040 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4042 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4043 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4045 if (reg < NUM_GREGS)
4046 return SIM_ARM_R0_REGNUM + reg;
4049 if (reg < NUM_FREGS)
4050 return SIM_ARM_FP0_REGNUM + reg;
4053 if (reg < NUM_SREGS)
4054 return SIM_ARM_FPS_REGNUM + reg;
4057 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4060 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4061 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4062 It is thought that this is is the floating-point register format on
4063 little-endian systems. */
4066 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4067 void *dbl, int endianess)
4071 if (endianess == BFD_ENDIAN_BIG)
4072 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4074 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4076 floatformat_from_doublest (fmt, &d, dbl);
4080 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4085 floatformat_to_doublest (fmt, ptr, &d);
4086 if (endianess == BFD_ENDIAN_BIG)
4087 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4089 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4093 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4094 of the appropriate mode (as encoded in the PC value), even if this
4095 differs from what would be expected according to the symbol tables. */
4098 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
4099 struct address_space *aspace,
4102 struct cleanup *old_chain
4103 = make_cleanup_restore_integer (&arm_override_mode);
4105 arm_override_mode = IS_THUMB_ADDR (pc);
4106 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4108 insert_single_step_breakpoint (gdbarch, aspace, pc);
4110 do_cleanups (old_chain);
4113 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4114 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4115 NULL if an error occurs. BUF is freed. */
4118 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4119 int old_len, int new_len)
4122 int bytes_to_read = new_len - old_len;
4124 new_buf = (gdb_byte *) xmalloc (new_len);
4125 memcpy (new_buf + bytes_to_read, buf, old_len);
4127 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4135 /* An IT block is at most the 2-byte IT instruction followed by
4136 four 4-byte instructions. The furthest back we must search to
4137 find an IT block that affects the current instruction is thus
4138 2 + 3 * 4 == 14 bytes. */
4139 #define MAX_IT_BLOCK_PREFIX 14
4141 /* Use a quick scan if there are more than this many bytes of
4143 #define IT_SCAN_THRESHOLD 32
4145 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4146 A breakpoint in an IT block may not be hit, depending on the
4149 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4153 CORE_ADDR boundary, func_start;
4155 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4156 int i, any, last_it, last_it_count;
4158 /* If we are using BKPT breakpoints, none of this is necessary. */
4159 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4162 /* ARM mode does not have this problem. */
4163 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4166 /* We are setting a breakpoint in Thumb code that could potentially
4167 contain an IT block. The first step is to find how much Thumb
4168 code there is; we do not need to read outside of known Thumb
4170 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4172 /* Thumb-2 code must have mapping symbols to have a chance. */
4175 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4177 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4178 && func_start > boundary)
4179 boundary = func_start;
4181 /* Search for a candidate IT instruction. We have to do some fancy
4182 footwork to distinguish a real IT instruction from the second
4183 half of a 32-bit instruction, but there is no need for that if
4184 there's no candidate. */
4185 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
4187 /* No room for an IT instruction. */
4190 buf = (gdb_byte *) xmalloc (buf_len);
4191 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4194 for (i = 0; i < buf_len; i += 2)
4196 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4197 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4210 /* OK, the code bytes before this instruction contain at least one
4211 halfword which resembles an IT instruction. We know that it's
4212 Thumb code, but there are still two possibilities. Either the
4213 halfword really is an IT instruction, or it is the second half of
4214 a 32-bit Thumb instruction. The only way we can tell is to
4215 scan forwards from a known instruction boundary. */
4216 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
4220 /* There's a lot of code before this instruction. Start with an
4221 optimistic search; it's easy to recognize halfwords that can
4222 not be the start of a 32-bit instruction, and use that to
4223 lock on to the instruction boundaries. */
4224 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
4227 buf_len = IT_SCAN_THRESHOLD;
4230 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
4232 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4233 if (thumb_insn_size (inst1) == 2)
4240 /* At this point, if DEFINITE, BUF[I] is the first place we
4241 are sure that we know the instruction boundaries, and it is far
4242 enough from BPADDR that we could not miss an IT instruction
4243 affecting BPADDR. If ! DEFINITE, give up - start from a
4247 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
4251 buf_len = bpaddr - boundary;
4257 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4260 buf_len = bpaddr - boundary;
4264 /* Scan forwards. Find the last IT instruction before BPADDR. */
4269 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4271 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4276 else if (inst1 & 0x0002)
4278 else if (inst1 & 0x0004)
4283 i += thumb_insn_size (inst1);
4289 /* There wasn't really an IT instruction after all. */
4292 if (last_it_count < 1)
4293 /* It was too far away. */
4296 /* This really is a trouble spot. Move the breakpoint to the IT
4298 return bpaddr - buf_len + last_it;
4301 /* ARM displaced stepping support.
4303 Generally ARM displaced stepping works as follows:
4305 1. When an instruction is to be single-stepped, it is first decoded by
4306 arm_process_displaced_insn. Depending on the type of instruction, it is
4307 then copied to a scratch location, possibly in a modified form. The
4308 copy_* set of functions performs such modification, as necessary. A
4309 breakpoint is placed after the modified instruction in the scratch space
4310 to return control to GDB. Note in particular that instructions which
4311 modify the PC will no longer do so after modification.
4313 2. The instruction is single-stepped, by setting the PC to the scratch
4314 location address, and resuming. Control returns to GDB when the
4317 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4318 function used for the current instruction. This function's job is to
4319 put the CPU/memory state back to what it would have been if the
4320 instruction had been executed unmodified in its original location. */
4322 /* NOP instruction (mov r0, r0). */
4323 #define ARM_NOP 0xe1a00000
4324 #define THUMB_NOP 0x4600
4326 /* Helper for register reads for displaced stepping. In particular, this
4327 returns the PC as it would be seen by the instruction at its original
4331 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4335 CORE_ADDR from = dsc->insn_addr;
4337 if (regno == ARM_PC_REGNUM)
4339 /* Compute pipeline offset:
4340 - When executing an ARM instruction, PC reads as the address of the
4341 current instruction plus 8.
4342 - When executing a Thumb instruction, PC reads as the address of the
4343 current instruction plus 4. */
4350 if (debug_displaced)
4351 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
4352 (unsigned long) from);
4353 return (ULONGEST) from;
4357 regcache_cooked_read_unsigned (regs, regno, &ret);
4358 if (debug_displaced)
4359 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
4360 regno, (unsigned long) ret);
4366 displaced_in_arm_mode (struct regcache *regs)
4369 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4371 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4373 return (ps & t_bit) == 0;
4376 /* Write to the PC as from a branch instruction. */
4379 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4383 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4384 architecture versions < 6. */
4385 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4386 val & ~(ULONGEST) 0x3);
4388 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4389 val & ~(ULONGEST) 0x1);
4392 /* Write to the PC as from a branch-exchange instruction. */
4395 bx_write_pc (struct regcache *regs, ULONGEST val)
4398 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4400 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4404 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
4405 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
4407 else if ((val & 2) == 0)
4409 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4410 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
4414 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4415 mode, align dest to 4 bytes). */
4416 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4417 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4418 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
4422 /* Write to the PC as if from a load instruction. */
4425 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4428 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
4429 bx_write_pc (regs, val);
4431 branch_write_pc (regs, dsc, val);
4434 /* Write to the PC as if from an ALU instruction. */
4437 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4440 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
4441 bx_write_pc (regs, val);
4443 branch_write_pc (regs, dsc, val);
4446 /* Helper for writing to registers for displaced stepping. Writing to the PC
4447 has a varying effects depending on the instruction which does the write:
4448 this is controlled by the WRITE_PC argument. */
4451 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4452 int regno, ULONGEST val, enum pc_write_style write_pc)
4454 if (regno == ARM_PC_REGNUM)
4456 if (debug_displaced)
4457 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
4458 (unsigned long) val);
4461 case BRANCH_WRITE_PC:
4462 branch_write_pc (regs, dsc, val);
4466 bx_write_pc (regs, val);
4470 load_write_pc (regs, dsc, val);
4474 alu_write_pc (regs, dsc, val);
4477 case CANNOT_WRITE_PC:
4478 warning (_("Instruction wrote to PC in an unexpected way when "
4479 "single-stepping"));
4483 internal_error (__FILE__, __LINE__,
4484 _("Invalid argument to displaced_write_reg"));
4487 dsc->wrote_to_pc = 1;
4491 if (debug_displaced)
4492 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
4493 regno, (unsigned long) val);
4494 regcache_cooked_write_unsigned (regs, regno, val);
4498 /* This function is used to concisely determine if an instruction INSN
4499 references PC. Register fields of interest in INSN should have the
4500 corresponding fields of BITMASK set to 0b1111. The function
4501 returns return 1 if any of these fields in INSN reference the PC
4502 (also 0b1111, r15), else it returns 0. */
4505 insn_references_pc (uint32_t insn, uint32_t bitmask)
4507 uint32_t lowbit = 1;
4509 while (bitmask != 0)
4513 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
4519 mask = lowbit * 0xf;
4521 if ((insn & mask) == mask)
4530 /* The simplest copy function. Many instructions have the same effect no
4531 matter what address they are executed at: in those cases, use this. */
4534 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
4535 const char *iname, struct displaced_step_closure *dsc)
4537 if (debug_displaced)
4538 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
4539 "opcode/class '%s' unmodified\n", (unsigned long) insn,
4542 dsc->modinsn[0] = insn;
4548 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
4549 uint16_t insn2, const char *iname,
4550 struct displaced_step_closure *dsc)
4552 if (debug_displaced)
4553 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
4554 "opcode/class '%s' unmodified\n", insn1, insn2,
4557 dsc->modinsn[0] = insn1;
4558 dsc->modinsn[1] = insn2;
4564 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4567 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn,
4569 struct displaced_step_closure *dsc)
4571 if (debug_displaced)
4572 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
4573 "opcode/class '%s' unmodified\n", insn,
4576 dsc->modinsn[0] = insn;
4581 /* Preload instructions with immediate offset. */
4584 cleanup_preload (struct gdbarch *gdbarch,
4585 struct regcache *regs, struct displaced_step_closure *dsc)
4587 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4588 if (!dsc->u.preload.immed)
4589 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4593 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
4594 struct displaced_step_closure *dsc, unsigned int rn)
4597 /* Preload instructions:
4599 {pli/pld} [rn, #+/-imm]
4601 {pli/pld} [r0, #+/-imm]. */
4603 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4604 rn_val = displaced_read_reg (regs, dsc, rn);
4605 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4606 dsc->u.preload.immed = 1;
4608 dsc->cleanup = &cleanup_preload;
4612 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4613 struct displaced_step_closure *dsc)
4615 unsigned int rn = bits (insn, 16, 19);
4617 if (!insn_references_pc (insn, 0x000f0000ul))
4618 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
4620 if (debug_displaced)
4621 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4622 (unsigned long) insn);
4624 dsc->modinsn[0] = insn & 0xfff0ffff;
4626 install_preload (gdbarch, regs, dsc, rn);
4632 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
4633 struct regcache *regs, struct displaced_step_closure *dsc)
4635 unsigned int rn = bits (insn1, 0, 3);
4636 unsigned int u_bit = bit (insn1, 7);
4637 int imm12 = bits (insn2, 0, 11);
4640 if (rn != ARM_PC_REGNUM)
4641 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
4643 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4644 PLD (literal) Encoding T1. */
4645 if (debug_displaced)
4646 fprintf_unfiltered (gdb_stdlog,
4647 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4648 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
4654 /* Rewrite instruction {pli/pld} PC imm12 into:
4655 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4659 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4661 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4662 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4664 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
4666 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
4667 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
4668 dsc->u.preload.immed = 0;
4670 /* {pli/pld} [r0, r1] */
4671 dsc->modinsn[0] = insn1 & 0xfff0;
4672 dsc->modinsn[1] = 0xf001;
4675 dsc->cleanup = &cleanup_preload;
4679 /* Preload instructions with register offset. */
4682 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
4683 struct displaced_step_closure *dsc, unsigned int rn,
4686 ULONGEST rn_val, rm_val;
4688 /* Preload register-offset instructions:
4690 {pli/pld} [rn, rm {, shift}]
4692 {pli/pld} [r0, r1 {, shift}]. */
4694 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4695 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4696 rn_val = displaced_read_reg (regs, dsc, rn);
4697 rm_val = displaced_read_reg (regs, dsc, rm);
4698 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4699 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
4700 dsc->u.preload.immed = 0;
4702 dsc->cleanup = &cleanup_preload;
4706 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
4707 struct regcache *regs,
4708 struct displaced_step_closure *dsc)
4710 unsigned int rn = bits (insn, 16, 19);
4711 unsigned int rm = bits (insn, 0, 3);
4714 if (!insn_references_pc (insn, 0x000f000ful))
4715 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
4717 if (debug_displaced)
4718 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4719 (unsigned long) insn);
4721 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
4723 install_preload_reg (gdbarch, regs, dsc, rn, rm);
4727 /* Copy/cleanup coprocessor load and store instructions. */
4730 cleanup_copro_load_store (struct gdbarch *gdbarch,
4731 struct regcache *regs,
4732 struct displaced_step_closure *dsc)
4734 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
4736 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4738 if (dsc->u.ldst.writeback)
4739 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
4743 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
4744 struct displaced_step_closure *dsc,
4745 int writeback, unsigned int rn)
4749 /* Coprocessor load/store instructions:
4751 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4753 {stc/stc2} [r0, #+/-imm].
4755 ldc/ldc2 are handled identically. */
4757 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4758 rn_val = displaced_read_reg (regs, dsc, rn);
4759 /* PC should be 4-byte aligned. */
4760 rn_val = rn_val & 0xfffffffc;
4761 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4763 dsc->u.ldst.writeback = writeback;
4764 dsc->u.ldst.rn = rn;
4766 dsc->cleanup = &cleanup_copro_load_store;
4770 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
4771 struct regcache *regs,
4772 struct displaced_step_closure *dsc)
4774 unsigned int rn = bits (insn, 16, 19);
4776 if (!insn_references_pc (insn, 0x000f0000ul))
4777 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
4779 if (debug_displaced)
4780 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4781 "load/store insn %.8lx\n", (unsigned long) insn);
4783 dsc->modinsn[0] = insn & 0xfff0ffff;
4785 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
4791 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
4792 uint16_t insn2, struct regcache *regs,
4793 struct displaced_step_closure *dsc)
4795 unsigned int rn = bits (insn1, 0, 3);
4797 if (rn != ARM_PC_REGNUM)
4798 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
4799 "copro load/store", dsc);
4801 if (debug_displaced)
4802 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4803 "load/store insn %.4x%.4x\n", insn1, insn2);
4805 dsc->modinsn[0] = insn1 & 0xfff0;
4806 dsc->modinsn[1] = insn2;
4809 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4810 doesn't support writeback, so pass 0. */
4811 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
4816 /* Clean up branch instructions (actually perform the branch, by setting
4820 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
4821 struct displaced_step_closure *dsc)
4823 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
4824 int branch_taken = condition_true (dsc->u.branch.cond, status);
4825 enum pc_write_style write_pc = dsc->u.branch.exchange
4826 ? BX_WRITE_PC : BRANCH_WRITE_PC;
4831 if (dsc->u.branch.link)
4833 /* The value of LR should be the next insn of current one. In order
4834 not to confuse logic hanlding later insn `bx lr', if current insn mode
4835 is Thumb, the bit 0 of LR value should be set to 1. */
4836 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
4839 next_insn_addr |= 0x1;
4841 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
4845 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
4848 /* Copy B/BL/BLX instructions with immediate destinations. */
4851 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
4852 struct displaced_step_closure *dsc,
4853 unsigned int cond, int exchange, int link, long offset)
4855 /* Implement "BL<cond> <label>" as:
4857 Preparation: cond <- instruction condition
4858 Insn: mov r0, r0 (nop)
4859 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4861 B<cond> similar, but don't set r14 in cleanup. */
4863 dsc->u.branch.cond = cond;
4864 dsc->u.branch.link = link;
4865 dsc->u.branch.exchange = exchange;
4867 dsc->u.branch.dest = dsc->insn_addr;
4868 if (link && exchange)
4869 /* For BLX, offset is computed from the Align (PC, 4). */
4870 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
4873 dsc->u.branch.dest += 4 + offset;
4875 dsc->u.branch.dest += 8 + offset;
4877 dsc->cleanup = &cleanup_branch;
4880 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
4881 struct regcache *regs, struct displaced_step_closure *dsc)
4883 unsigned int cond = bits (insn, 28, 31);
4884 int exchange = (cond == 0xf);
4885 int link = exchange || bit (insn, 24);
4888 if (debug_displaced)
4889 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
4890 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
4891 (unsigned long) insn);
4893 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4894 then arrange the switch into Thumb mode. */
4895 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
4897 offset = bits (insn, 0, 23) << 2;
4899 if (bit (offset, 25))
4900 offset = offset | ~0x3ffffff;
4902 dsc->modinsn[0] = ARM_NOP;
4904 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
4909 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
4910 uint16_t insn2, struct regcache *regs,
4911 struct displaced_step_closure *dsc)
4913 int link = bit (insn2, 14);
4914 int exchange = link && !bit (insn2, 12);
4917 int j1 = bit (insn2, 13);
4918 int j2 = bit (insn2, 11);
4919 int s = sbits (insn1, 10, 10);
4920 int i1 = !(j1 ^ bit (insn1, 10));
4921 int i2 = !(j2 ^ bit (insn1, 10));
4923 if (!link && !exchange) /* B */
4925 offset = (bits (insn2, 0, 10) << 1);
4926 if (bit (insn2, 12)) /* Encoding T4 */
4928 offset |= (bits (insn1, 0, 9) << 12)
4934 else /* Encoding T3 */
4936 offset |= (bits (insn1, 0, 5) << 12)
4940 cond = bits (insn1, 6, 9);
4945 offset = (bits (insn1, 0, 9) << 12);
4946 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
4947 offset |= exchange ?
4948 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
4951 if (debug_displaced)
4952 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
4953 "%.4x %.4x with offset %.8lx\n",
4954 link ? (exchange) ? "blx" : "bl" : "b",
4955 insn1, insn2, offset);
4957 dsc->modinsn[0] = THUMB_NOP;
4959 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
4963 /* Copy B Thumb instructions. */
4965 thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn,
4966 struct displaced_step_closure *dsc)
4968 unsigned int cond = 0;
4970 unsigned short bit_12_15 = bits (insn, 12, 15);
4971 CORE_ADDR from = dsc->insn_addr;
4973 if (bit_12_15 == 0xd)
4975 /* offset = SignExtend (imm8:0, 32) */
4976 offset = sbits ((insn << 1), 0, 8);
4977 cond = bits (insn, 8, 11);
4979 else if (bit_12_15 == 0xe) /* Encoding T2 */
4981 offset = sbits ((insn << 1), 0, 11);
4985 if (debug_displaced)
4986 fprintf_unfiltered (gdb_stdlog,
4987 "displaced: copying b immediate insn %.4x "
4988 "with offset %d\n", insn, offset);
4990 dsc->u.branch.cond = cond;
4991 dsc->u.branch.link = 0;
4992 dsc->u.branch.exchange = 0;
4993 dsc->u.branch.dest = from + 4 + offset;
4995 dsc->modinsn[0] = THUMB_NOP;
4997 dsc->cleanup = &cleanup_branch;
5002 /* Copy BX/BLX with register-specified destinations. */
5005 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5006 struct displaced_step_closure *dsc, int link,
5007 unsigned int cond, unsigned int rm)
5009 /* Implement {BX,BLX}<cond> <reg>" as:
5011 Preparation: cond <- instruction condition
5012 Insn: mov r0, r0 (nop)
5013 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5015 Don't set r14 in cleanup for BX. */
5017 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5019 dsc->u.branch.cond = cond;
5020 dsc->u.branch.link = link;
5022 dsc->u.branch.exchange = 1;
5024 dsc->cleanup = &cleanup_branch;
5028 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5029 struct regcache *regs, struct displaced_step_closure *dsc)
5031 unsigned int cond = bits (insn, 28, 31);
5034 int link = bit (insn, 5);
5035 unsigned int rm = bits (insn, 0, 3);
5037 if (debug_displaced)
5038 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5039 (unsigned long) insn);
5041 dsc->modinsn[0] = ARM_NOP;
5043 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5048 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
5049 struct regcache *regs,
5050 struct displaced_step_closure *dsc)
5052 int link = bit (insn, 7);
5053 unsigned int rm = bits (insn, 3, 6);
5055 if (debug_displaced)
5056 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
5057 (unsigned short) insn);
5059 dsc->modinsn[0] = THUMB_NOP;
5061 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
5067 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5070 cleanup_alu_imm (struct gdbarch *gdbarch,
5071 struct regcache *regs, struct displaced_step_closure *dsc)
5073 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5074 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5075 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5076 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5080 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5081 struct displaced_step_closure *dsc)
5083 unsigned int rn = bits (insn, 16, 19);
5084 unsigned int rd = bits (insn, 12, 15);
5085 unsigned int op = bits (insn, 21, 24);
5086 int is_mov = (op == 0xd);
5087 ULONGEST rd_val, rn_val;
5089 if (!insn_references_pc (insn, 0x000ff000ul))
5090 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5092 if (debug_displaced)
5093 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5094 "%.8lx\n", is_mov ? "move" : "ALU",
5095 (unsigned long) insn);
5097 /* Instruction is of form:
5099 <op><cond> rd, [rn,] #imm
5103 Preparation: tmp1, tmp2 <- r0, r1;
5105 Insn: <op><cond> r0, r1, #imm
5106 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5109 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5110 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5111 rn_val = displaced_read_reg (regs, dsc, rn);
5112 rd_val = displaced_read_reg (regs, dsc, rd);
5113 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5114 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5118 dsc->modinsn[0] = insn & 0xfff00fff;
5120 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5122 dsc->cleanup = &cleanup_alu_imm;
5128 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
5129 uint16_t insn2, struct regcache *regs,
5130 struct displaced_step_closure *dsc)
5132 unsigned int op = bits (insn1, 5, 8);
5133 unsigned int rn, rm, rd;
5134 ULONGEST rd_val, rn_val;
5136 rn = bits (insn1, 0, 3); /* Rn */
5137 rm = bits (insn2, 0, 3); /* Rm */
5138 rd = bits (insn2, 8, 11); /* Rd */
5140 /* This routine is only called for instruction MOV. */
5141 gdb_assert (op == 0x2 && rn == 0xf);
5143 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
5144 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
5146 if (debug_displaced)
5147 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
5148 "ALU", insn1, insn2);
5150 /* Instruction is of form:
5152 <op><cond> rd, [rn,] #imm
5156 Preparation: tmp1, tmp2 <- r0, r1;
5158 Insn: <op><cond> r0, r1, #imm
5159 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5162 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5163 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5164 rn_val = displaced_read_reg (regs, dsc, rn);
5165 rd_val = displaced_read_reg (regs, dsc, rd);
5166 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5167 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5170 dsc->modinsn[0] = insn1;
5171 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
5174 dsc->cleanup = &cleanup_alu_imm;
5179 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5182 cleanup_alu_reg (struct gdbarch *gdbarch,
5183 struct regcache *regs, struct displaced_step_closure *dsc)
5188 rd_val = displaced_read_reg (regs, dsc, 0);
5190 for (i = 0; i < 3; i++)
5191 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5193 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5197 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
5198 struct displaced_step_closure *dsc,
5199 unsigned int rd, unsigned int rn, unsigned int rm)
5201 ULONGEST rd_val, rn_val, rm_val;
5203 /* Instruction is of form:
5205 <op><cond> rd, [rn,] rm [, <shift>]
5209 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5210 r0, r1, r2 <- rd, rn, rm
5211 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5212 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5215 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5216 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5217 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5218 rd_val = displaced_read_reg (regs, dsc, rd);
5219 rn_val = displaced_read_reg (regs, dsc, rn);
5220 rm_val = displaced_read_reg (regs, dsc, rm);
5221 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5222 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5223 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5226 dsc->cleanup = &cleanup_alu_reg;
5230 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5231 struct displaced_step_closure *dsc)
5233 unsigned int op = bits (insn, 21, 24);
5234 int is_mov = (op == 0xd);
5236 if (!insn_references_pc (insn, 0x000ff00ful))
5237 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
5239 if (debug_displaced)
5240 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
5241 is_mov ? "move" : "ALU", (unsigned long) insn);
5244 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
5246 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
5248 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
5254 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
5255 struct regcache *regs,
5256 struct displaced_step_closure *dsc)
5260 rm = bits (insn, 3, 6);
5261 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
5263 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
5264 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
5266 if (debug_displaced)
5267 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
5268 (unsigned short) insn);
5270 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
5272 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
5277 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5280 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
5281 struct regcache *regs,
5282 struct displaced_step_closure *dsc)
5284 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5287 for (i = 0; i < 4; i++)
5288 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5290 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5294 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
5295 struct displaced_step_closure *dsc,
5296 unsigned int rd, unsigned int rn, unsigned int rm,
5300 ULONGEST rd_val, rn_val, rm_val, rs_val;
5302 /* Instruction is of form:
5304 <op><cond> rd, [rn,] rm, <shift> rs
5308 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5309 r0, r1, r2, r3 <- rd, rn, rm, rs
5310 Insn: <op><cond> r0, r1, r2, <shift> r3
5312 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5316 for (i = 0; i < 4; i++)
5317 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5319 rd_val = displaced_read_reg (regs, dsc, rd);
5320 rn_val = displaced_read_reg (regs, dsc, rn);
5321 rm_val = displaced_read_reg (regs, dsc, rm);
5322 rs_val = displaced_read_reg (regs, dsc, rs);
5323 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5324 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5325 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5326 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
5328 dsc->cleanup = &cleanup_alu_shifted_reg;
5332 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
5333 struct regcache *regs,
5334 struct displaced_step_closure *dsc)
5336 unsigned int op = bits (insn, 21, 24);
5337 int is_mov = (op == 0xd);
5338 unsigned int rd, rn, rm, rs;
5340 if (!insn_references_pc (insn, 0x000fff0ful))
5341 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
5343 if (debug_displaced)
5344 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
5345 "%.8lx\n", is_mov ? "move" : "ALU",
5346 (unsigned long) insn);
5348 rn = bits (insn, 16, 19);
5349 rm = bits (insn, 0, 3);
5350 rs = bits (insn, 8, 11);
5351 rd = bits (insn, 12, 15);
5354 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
5356 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
5358 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
5363 /* Clean up load instructions. */
5366 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
5367 struct displaced_step_closure *dsc)
5369 ULONGEST rt_val, rt_val2 = 0, rn_val;
5371 rt_val = displaced_read_reg (regs, dsc, 0);
5372 if (dsc->u.ldst.xfersize == 8)
5373 rt_val2 = displaced_read_reg (regs, dsc, 1);
5374 rn_val = displaced_read_reg (regs, dsc, 2);
5376 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5377 if (dsc->u.ldst.xfersize > 4)
5378 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5379 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5380 if (!dsc->u.ldst.immed)
5381 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5383 /* Handle register writeback. */
5384 if (dsc->u.ldst.writeback)
5385 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5386 /* Put result in right place. */
5387 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
5388 if (dsc->u.ldst.xfersize == 8)
5389 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5392 /* Clean up store instructions. */
5395 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5396 struct displaced_step_closure *dsc)
5398 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
5400 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5401 if (dsc->u.ldst.xfersize > 4)
5402 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5403 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5404 if (!dsc->u.ldst.immed)
5405 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5406 if (!dsc->u.ldst.restore_r4)
5407 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5410 if (dsc->u.ldst.writeback)
5411 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5414 /* Copy "extra" load/store instructions. These are halfword/doubleword
5415 transfers, which have a different encoding to byte/word transfers. */
5418 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged,
5419 struct regcache *regs, struct displaced_step_closure *dsc)
5421 unsigned int op1 = bits (insn, 20, 24);
5422 unsigned int op2 = bits (insn, 5, 6);
5423 unsigned int rt = bits (insn, 12, 15);
5424 unsigned int rn = bits (insn, 16, 19);
5425 unsigned int rm = bits (insn, 0, 3);
5426 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5427 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5428 int immed = (op1 & 0x4) != 0;
5430 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5432 if (!insn_references_pc (insn, 0x000ff00ful))
5433 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5435 if (debug_displaced)
5436 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5437 "insn %.8lx\n", unprivileged ? "unprivileged " : "",
5438 (unsigned long) insn);
5440 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5443 internal_error (__FILE__, __LINE__,
5444 _("copy_extra_ld_st: instruction decode error"));
5446 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5447 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5448 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5450 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5452 rt_val = displaced_read_reg (regs, dsc, rt);
5453 if (bytesize[opcode] == 8)
5454 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
5455 rn_val = displaced_read_reg (regs, dsc, rn);
5457 rm_val = displaced_read_reg (regs, dsc, rm);
5459 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5460 if (bytesize[opcode] == 8)
5461 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5462 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5464 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5467 dsc->u.ldst.xfersize = bytesize[opcode];
5468 dsc->u.ldst.rn = rn;
5469 dsc->u.ldst.immed = immed;
5470 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5471 dsc->u.ldst.restore_r4 = 0;
5474 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5476 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5477 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5479 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5481 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5482 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5484 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5489 /* Copy byte/half word/word loads and stores. */
5492 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5493 struct displaced_step_closure *dsc, int load,
5494 int immed, int writeback, int size, int usermode,
5495 int rt, int rm, int rn)
5497 ULONGEST rt_val, rn_val, rm_val = 0;
5499 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5500 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5502 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5504 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
5506 rt_val = displaced_read_reg (regs, dsc, rt);
5507 rn_val = displaced_read_reg (regs, dsc, rn);
5509 rm_val = displaced_read_reg (regs, dsc, rm);
5511 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5512 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5514 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5516 dsc->u.ldst.xfersize = size;
5517 dsc->u.ldst.rn = rn;
5518 dsc->u.ldst.immed = immed;
5519 dsc->u.ldst.writeback = writeback;
5521 /* To write PC we can do:
5523 Before this sequence of instructions:
5524 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5525 r2 is the Rn value got from dispalced_read_reg.
5527 Insn1: push {pc} Write address of STR instruction + offset on stack
5528 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5529 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5530 = addr(Insn1) + offset - addr(Insn3) - 8
5532 Insn4: add r4, r4, #8 r4 = offset - 8
5533 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5535 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5537 Otherwise we don't know what value to write for PC, since the offset is
5538 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5539 of this can be found in Section "Saving from r15" in
5540 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5542 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5547 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
5548 uint16_t insn2, struct regcache *regs,
5549 struct displaced_step_closure *dsc, int size)
5551 unsigned int u_bit = bit (insn1, 7);
5552 unsigned int rt = bits (insn2, 12, 15);
5553 int imm12 = bits (insn2, 0, 11);
5556 if (debug_displaced)
5557 fprintf_unfiltered (gdb_stdlog,
5558 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5559 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
5565 /* Rewrite instruction LDR Rt imm12 into:
5567 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5571 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5574 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5575 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5576 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5578 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5580 pc_val = pc_val & 0xfffffffc;
5582 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
5583 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
5587 dsc->u.ldst.xfersize = size;
5588 dsc->u.ldst.immed = 0;
5589 dsc->u.ldst.writeback = 0;
5590 dsc->u.ldst.restore_r4 = 0;
5592 /* LDR R0, R2, R3 */
5593 dsc->modinsn[0] = 0xf852;
5594 dsc->modinsn[1] = 0x3;
5597 dsc->cleanup = &cleanup_load;
5603 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
5604 uint16_t insn2, struct regcache *regs,
5605 struct displaced_step_closure *dsc,
5606 int writeback, int immed)
5608 unsigned int rt = bits (insn2, 12, 15);
5609 unsigned int rn = bits (insn1, 0, 3);
5610 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
5611 /* In LDR (register), there is also a register Rm, which is not allowed to
5612 be PC, so we don't have to check it. */
5614 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
5615 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
5618 if (debug_displaced)
5619 fprintf_unfiltered (gdb_stdlog,
5620 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5621 rt, rn, insn1, insn2);
5623 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
5626 dsc->u.ldst.restore_r4 = 0;
5629 /* ldr[b]<cond> rt, [rn, #imm], etc.
5631 ldr[b]<cond> r0, [r2, #imm]. */
5633 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5634 dsc->modinsn[1] = insn2 & 0x0fff;
5637 /* ldr[b]<cond> rt, [rn, rm], etc.
5639 ldr[b]<cond> r0, [r2, r3]. */
5641 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5642 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
5652 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
5653 struct regcache *regs,
5654 struct displaced_step_closure *dsc,
5655 int load, int size, int usermode)
5657 int immed = !bit (insn, 25);
5658 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
5659 unsigned int rt = bits (insn, 12, 15);
5660 unsigned int rn = bits (insn, 16, 19);
5661 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
5663 if (!insn_references_pc (insn, 0x000ff00ful))
5664 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
5666 if (debug_displaced)
5667 fprintf_unfiltered (gdb_stdlog,
5668 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5669 load ? (size == 1 ? "ldrb" : "ldr")
5670 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
5672 (unsigned long) insn);
5674 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
5675 usermode, rt, rm, rn);
5677 if (load || rt != ARM_PC_REGNUM)
5679 dsc->u.ldst.restore_r4 = 0;
5682 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5684 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5685 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5687 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5689 {ldr,str}[b]<cond> r0, [r2, r3]. */
5690 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5694 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5695 dsc->u.ldst.restore_r4 = 1;
5696 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
5697 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
5698 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
5699 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
5700 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
5704 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
5706 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
5711 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5716 /* Cleanup LDM instructions with fully-populated register list. This is an
5717 unfortunate corner case: it's impossible to implement correctly by modifying
5718 the instruction. The issue is as follows: we have an instruction,
5722 which we must rewrite to avoid loading PC. A possible solution would be to
5723 do the load in two halves, something like (with suitable cleanup
5727 ldm[id][ab] r8!, {r0-r7}
5729 ldm[id][ab] r8, {r7-r14}
5732 but at present there's no suitable place for <temp>, since the scratch space
5733 is overwritten before the cleanup routine is called. For now, we simply
5734 emulate the instruction. */
5737 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
5738 struct displaced_step_closure *dsc)
5740 int inc = dsc->u.block.increment;
5741 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
5742 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
5743 uint32_t regmask = dsc->u.block.regmask;
5744 int regno = inc ? 0 : 15;
5745 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
5746 int exception_return = dsc->u.block.load && dsc->u.block.user
5747 && (regmask & 0x8000) != 0;
5748 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5749 int do_transfer = condition_true (dsc->u.block.cond, status);
5750 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5755 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5756 sensible we can do here. Complain loudly. */
5757 if (exception_return)
5758 error (_("Cannot single-step exception return"));
5760 /* We don't handle any stores here for now. */
5761 gdb_assert (dsc->u.block.load != 0);
5763 if (debug_displaced)
5764 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
5765 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
5766 dsc->u.block.increment ? "inc" : "dec",
5767 dsc->u.block.before ? "before" : "after");
5774 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
5777 while (regno >= 0 && (regmask & (1 << regno)) == 0)
5780 xfer_addr += bump_before;
5782 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
5783 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
5785 xfer_addr += bump_after;
5787 regmask &= ~(1 << regno);
5790 if (dsc->u.block.writeback)
5791 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
5795 /* Clean up an STM which included the PC in the register list. */
5798 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
5799 struct displaced_step_closure *dsc)
5801 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5802 int store_executed = condition_true (dsc->u.block.cond, status);
5803 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
5804 CORE_ADDR stm_insn_addr;
5807 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5809 /* If condition code fails, there's nothing else to do. */
5810 if (!store_executed)
5813 if (dsc->u.block.increment)
5815 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
5817 if (dsc->u.block.before)
5822 pc_stored_at = dsc->u.block.xfer_addr;
5824 if (dsc->u.block.before)
5828 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
5829 stm_insn_addr = dsc->scratch_base;
5830 offset = pc_val - stm_insn_addr;
5832 if (debug_displaced)
5833 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
5834 "STM instruction\n", offset);
5836 /* Rewrite the stored PC to the proper value for the non-displaced original
5838 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
5839 dsc->insn_addr + offset);
5842 /* Clean up an LDM which includes the PC in the register list. We clumped all
5843 the registers in the transferred list into a contiguous range r0...rX (to
5844 avoid loading PC directly and losing control of the debugged program), so we
5845 must undo that here. */
5848 cleanup_block_load_pc (struct gdbarch *gdbarch,
5849 struct regcache *regs,
5850 struct displaced_step_closure *dsc)
5852 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5853 int load_executed = condition_true (dsc->u.block.cond, status);
5854 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
5855 unsigned int regs_loaded = bitcount (mask);
5856 unsigned int num_to_shuffle = regs_loaded, clobbered;
5858 /* The method employed here will fail if the register list is fully populated
5859 (we need to avoid loading PC directly). */
5860 gdb_assert (num_to_shuffle < 16);
5865 clobbered = (1 << num_to_shuffle) - 1;
5867 while (num_to_shuffle > 0)
5869 if ((mask & (1 << write_reg)) != 0)
5871 unsigned int read_reg = num_to_shuffle - 1;
5873 if (read_reg != write_reg)
5875 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
5876 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
5877 if (debug_displaced)
5878 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
5879 "loaded register r%d to r%d\n"), read_reg,
5882 else if (debug_displaced)
5883 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
5884 "r%d already in the right place\n"),
5887 clobbered &= ~(1 << write_reg);
5895 /* Restore any registers we scribbled over. */
5896 for (write_reg = 0; clobbered != 0; write_reg++)
5898 if ((clobbered & (1 << write_reg)) != 0)
5900 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
5902 if (debug_displaced)
5903 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
5904 "clobbered register r%d\n"), write_reg);
5905 clobbered &= ~(1 << write_reg);
5909 /* Perform register writeback manually. */
5910 if (dsc->u.block.writeback)
5912 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
5914 if (dsc->u.block.increment)
5915 new_rn_val += regs_loaded * 4;
5917 new_rn_val -= regs_loaded * 4;
5919 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
5924 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
5925 in user-level code (in particular exception return, ldm rn, {...pc}^). */
5928 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
5929 struct regcache *regs,
5930 struct displaced_step_closure *dsc)
5932 int load = bit (insn, 20);
5933 int user = bit (insn, 22);
5934 int increment = bit (insn, 23);
5935 int before = bit (insn, 24);
5936 int writeback = bit (insn, 21);
5937 int rn = bits (insn, 16, 19);
5939 /* Block transfers which don't mention PC can be run directly
5941 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
5942 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
5944 if (rn == ARM_PC_REGNUM)
5946 warning (_("displaced: Unpredictable LDM or STM with "
5947 "base register r15"));
5948 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
5951 if (debug_displaced)
5952 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
5953 "%.8lx\n", (unsigned long) insn);
5955 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
5956 dsc->u.block.rn = rn;
5958 dsc->u.block.load = load;
5959 dsc->u.block.user = user;
5960 dsc->u.block.increment = increment;
5961 dsc->u.block.before = before;
5962 dsc->u.block.writeback = writeback;
5963 dsc->u.block.cond = bits (insn, 28, 31);
5965 dsc->u.block.regmask = insn & 0xffff;
5969 if ((insn & 0xffff) == 0xffff)
5971 /* LDM with a fully-populated register list. This case is
5972 particularly tricky. Implement for now by fully emulating the
5973 instruction (which might not behave perfectly in all cases, but
5974 these instructions should be rare enough for that not to matter
5976 dsc->modinsn[0] = ARM_NOP;
5978 dsc->cleanup = &cleanup_block_load_all;
5982 /* LDM of a list of registers which includes PC. Implement by
5983 rewriting the list of registers to be transferred into a
5984 contiguous chunk r0...rX before doing the transfer, then shuffling
5985 registers into the correct places in the cleanup routine. */
5986 unsigned int regmask = insn & 0xffff;
5987 unsigned int num_in_list = bitcount (regmask), new_regmask;
5990 for (i = 0; i < num_in_list; i++)
5991 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5993 /* Writeback makes things complicated. We need to avoid clobbering
5994 the base register with one of the registers in our modified
5995 register list, but just using a different register can't work in
5998 ldm r14!, {r0-r13,pc}
6000 which would need to be rewritten as:
6004 but that can't work, because there's no free register for N.
6006 Solve this by turning off the writeback bit, and emulating
6007 writeback manually in the cleanup routine. */
6012 new_regmask = (1 << num_in_list) - 1;
6014 if (debug_displaced)
6015 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6016 "{..., pc}: original reg list %.4x, modified "
6017 "list %.4x\n"), rn, writeback ? "!" : "",
6018 (int) insn & 0xffff, new_regmask);
6020 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6022 dsc->cleanup = &cleanup_block_load_pc;
6027 /* STM of a list of registers which includes PC. Run the instruction
6028 as-is, but out of line: this will store the wrong value for the PC,
6029 so we must manually fix up the memory in the cleanup routine.
6030 Doing things this way has the advantage that we can auto-detect
6031 the offset of the PC write (which is architecture-dependent) in
6032 the cleanup routine. */
6033 dsc->modinsn[0] = insn;
6035 dsc->cleanup = &cleanup_block_store_pc;
6042 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6043 struct regcache *regs,
6044 struct displaced_step_closure *dsc)
6046 int rn = bits (insn1, 0, 3);
6047 int load = bit (insn1, 4);
6048 int writeback = bit (insn1, 5);
6050 /* Block transfers which don't mention PC can be run directly
6052 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
6053 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
6055 if (rn == ARM_PC_REGNUM)
6057 warning (_("displaced: Unpredictable LDM or STM with "
6058 "base register r15"));
6059 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6060 "unpredictable ldm/stm", dsc);
6063 if (debug_displaced)
6064 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6065 "%.4x%.4x\n", insn1, insn2);
6067 /* Clear bit 13, since it should be always zero. */
6068 dsc->u.block.regmask = (insn2 & 0xdfff);
6069 dsc->u.block.rn = rn;
6071 dsc->u.block.load = load;
6072 dsc->u.block.user = 0;
6073 dsc->u.block.increment = bit (insn1, 7);
6074 dsc->u.block.before = bit (insn1, 8);
6075 dsc->u.block.writeback = writeback;
6076 dsc->u.block.cond = INST_AL;
6077 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6081 if (dsc->u.block.regmask == 0xffff)
6083 /* This branch is impossible to happen. */
6088 unsigned int regmask = dsc->u.block.regmask;
6089 unsigned int num_in_list = bitcount (regmask), new_regmask;
6092 for (i = 0; i < num_in_list; i++)
6093 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6098 new_regmask = (1 << num_in_list) - 1;
6100 if (debug_displaced)
6101 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6102 "{..., pc}: original reg list %.4x, modified "
6103 "list %.4x\n"), rn, writeback ? "!" : "",
6104 (int) dsc->u.block.regmask, new_regmask);
6106 dsc->modinsn[0] = insn1;
6107 dsc->modinsn[1] = (new_regmask & 0xffff);
6110 dsc->cleanup = &cleanup_block_load_pc;
6115 dsc->modinsn[0] = insn1;
6116 dsc->modinsn[1] = insn2;
6118 dsc->cleanup = &cleanup_block_store_pc;
6123 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6124 This is used to avoid a dependency on BFD's bfd_endian enum. */
6127 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len,
6130 return read_memory_unsigned_integer (memaddr, len,
6131 (enum bfd_endian) byte_order);
6134 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6137 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
6140 return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val);
6143 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6146 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self)
6151 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6154 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self)
6156 return arm_is_thumb (self->regcache);
6159 /* single_step() is called just before we want to resume the inferior,
6160 if we want to single-step it but there is no hardware or kernel
6161 single-step support. We find the target of the coming instructions
6162 and breakpoint them. */
6165 arm_software_single_step (struct frame_info *frame)
6167 struct regcache *regcache = get_current_regcache ();
6168 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6169 struct address_space *aspace = get_regcache_aspace (regcache);
6170 struct arm_get_next_pcs next_pcs_ctx;
6173 VEC (CORE_ADDR) *next_pcs = NULL;
6174 struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
6176 arm_get_next_pcs_ctor (&next_pcs_ctx,
6177 &arm_get_next_pcs_ops,
6178 gdbarch_byte_order (gdbarch),
6179 gdbarch_byte_order_for_code (gdbarch),
6183 next_pcs = arm_get_next_pcs (&next_pcs_ctx);
6185 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
6186 arm_insert_single_step_breakpoint (gdbarch, aspace, pc);
6188 do_cleanups (old_chain);
6193 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6194 for Linux, where some SVC instructions must be treated specially. */
6197 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6198 struct displaced_step_closure *dsc)
6200 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6202 if (debug_displaced)
6203 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6204 "%.8lx\n", (unsigned long) resume_addr);
6206 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6210 /* Common copy routine for svc instruciton. */
6213 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
6214 struct displaced_step_closure *dsc)
6216 /* Preparation: none.
6217 Insn: unmodified svc.
6218 Cleanup: pc <- insn_addr + insn_size. */
6220 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6222 dsc->wrote_to_pc = 1;
6224 /* Allow OS-specific code to override SVC handling. */
6225 if (dsc->u.svc.copy_svc_os)
6226 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6229 dsc->cleanup = &cleanup_svc;
6235 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6236 struct regcache *regs, struct displaced_step_closure *dsc)
6239 if (debug_displaced)
6240 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6241 (unsigned long) insn);
6243 dsc->modinsn[0] = insn;
6245 return install_svc (gdbarch, regs, dsc);
6249 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
6250 struct regcache *regs, struct displaced_step_closure *dsc)
6253 if (debug_displaced)
6254 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
6257 dsc->modinsn[0] = insn;
6259 return install_svc (gdbarch, regs, dsc);
6262 /* Copy undefined instructions. */
6265 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6266 struct displaced_step_closure *dsc)
6268 if (debug_displaced)
6269 fprintf_unfiltered (gdb_stdlog,
6270 "displaced: copying undefined insn %.8lx\n",
6271 (unsigned long) insn);
6273 dsc->modinsn[0] = insn;
6279 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6280 struct displaced_step_closure *dsc)
6283 if (debug_displaced)
6284 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
6285 "%.4x %.4x\n", (unsigned short) insn1,
6286 (unsigned short) insn2);
6288 dsc->modinsn[0] = insn1;
6289 dsc->modinsn[1] = insn2;
6295 /* Copy unpredictable instructions. */
6298 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
6299 struct displaced_step_closure *dsc)
6301 if (debug_displaced)
6302 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
6303 "%.8lx\n", (unsigned long) insn);
6305 dsc->modinsn[0] = insn;
6310 /* The decode_* functions are instruction decoding helpers. They mostly follow
6311 the presentation in the ARM ARM. */
6314 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
6315 struct regcache *regs,
6316 struct displaced_step_closure *dsc)
6318 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
6319 unsigned int rn = bits (insn, 16, 19);
6321 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
6322 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
6323 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
6324 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
6325 else if ((op1 & 0x60) == 0x20)
6326 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
6327 else if ((op1 & 0x71) == 0x40)
6328 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
6330 else if ((op1 & 0x77) == 0x41)
6331 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6332 else if ((op1 & 0x77) == 0x45)
6333 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
6334 else if ((op1 & 0x77) == 0x51)
6337 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6339 return arm_copy_unpred (gdbarch, insn, dsc);
6341 else if ((op1 & 0x77) == 0x55)
6342 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6343 else if (op1 == 0x57)
6346 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
6347 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
6348 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
6349 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
6350 default: return arm_copy_unpred (gdbarch, insn, dsc);
6352 else if ((op1 & 0x63) == 0x43)
6353 return arm_copy_unpred (gdbarch, insn, dsc);
6354 else if ((op2 & 0x1) == 0x0)
6355 switch (op1 & ~0x80)
6358 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6360 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
6361 case 0x71: case 0x75:
6363 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
6364 case 0x63: case 0x67: case 0x73: case 0x77:
6365 return arm_copy_unpred (gdbarch, insn, dsc);
6367 return arm_copy_undef (gdbarch, insn, dsc);
6370 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
6374 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
6375 struct regcache *regs,
6376 struct displaced_step_closure *dsc)
6378 if (bit (insn, 27) == 0)
6379 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
6380 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6381 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
6384 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
6387 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
6389 case 0x4: case 0x5: case 0x6: case 0x7:
6390 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6393 switch ((insn & 0xe00000) >> 21)
6395 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6397 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6400 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6403 return arm_copy_undef (gdbarch, insn, dsc);
6408 int rn_f = (bits (insn, 16, 19) == 0xf);
6409 switch ((insn & 0xe00000) >> 21)
6412 /* ldc/ldc2 imm (undefined for rn == pc). */
6413 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
6414 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6417 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6419 case 0x4: case 0x5: case 0x6: case 0x7:
6420 /* ldc/ldc2 lit (undefined for rn != pc). */
6421 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
6422 : arm_copy_undef (gdbarch, insn, dsc);
6425 return arm_copy_undef (gdbarch, insn, dsc);
6430 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
6433 if (bits (insn, 16, 19) == 0xf)
6435 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6437 return arm_copy_undef (gdbarch, insn, dsc);
6441 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6443 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6447 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6449 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6452 return arm_copy_undef (gdbarch, insn, dsc);
6456 /* Decode miscellaneous instructions in dp/misc encoding space. */
6459 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
6460 struct regcache *regs,
6461 struct displaced_step_closure *dsc)
6463 unsigned int op2 = bits (insn, 4, 6);
6464 unsigned int op = bits (insn, 21, 22);
6469 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
6472 if (op == 0x1) /* bx. */
6473 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
6475 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
6477 return arm_copy_undef (gdbarch, insn, dsc);
6481 /* Not really supported. */
6482 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
6484 return arm_copy_undef (gdbarch, insn, dsc);
6488 return arm_copy_bx_blx_reg (gdbarch, insn,
6489 regs, dsc); /* blx register. */
6491 return arm_copy_undef (gdbarch, insn, dsc);
6494 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
6498 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
6500 /* Not really supported. */
6501 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
6504 return arm_copy_undef (gdbarch, insn, dsc);
6509 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
6510 struct regcache *regs,
6511 struct displaced_step_closure *dsc)
6514 switch (bits (insn, 20, 24))
6517 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
6520 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
6522 case 0x12: case 0x16:
6523 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
6526 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
6530 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
6532 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
6533 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
6534 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
6535 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
6536 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
6537 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
6538 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
6539 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
6540 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
6541 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
6542 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
6543 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
6544 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
6545 /* 2nd arg means "unprivileged". */
6546 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
6550 /* Should be unreachable. */
6555 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
6556 struct regcache *regs,
6557 struct displaced_step_closure *dsc)
6559 int a = bit (insn, 25), b = bit (insn, 4);
6560 uint32_t op1 = bits (insn, 20, 24);
6562 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
6563 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
6564 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
6565 else if ((!a && (op1 & 0x17) == 0x02)
6566 || (a && (op1 & 0x17) == 0x02 && !b))
6567 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
6568 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
6569 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
6570 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
6571 else if ((!a && (op1 & 0x17) == 0x03)
6572 || (a && (op1 & 0x17) == 0x03 && !b))
6573 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
6574 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
6575 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
6576 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
6577 else if ((!a && (op1 & 0x17) == 0x06)
6578 || (a && (op1 & 0x17) == 0x06 && !b))
6579 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
6580 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
6581 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
6582 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
6583 else if ((!a && (op1 & 0x17) == 0x07)
6584 || (a && (op1 & 0x17) == 0x07 && !b))
6585 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
6587 /* Should be unreachable. */
6592 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
6593 struct displaced_step_closure *dsc)
6595 switch (bits (insn, 20, 24))
6597 case 0x00: case 0x01: case 0x02: case 0x03:
6598 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
6600 case 0x04: case 0x05: case 0x06: case 0x07:
6601 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
6603 case 0x08: case 0x09: case 0x0a: case 0x0b:
6604 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6605 return arm_copy_unmodified (gdbarch, insn,
6606 "decode/pack/unpack/saturate/reverse", dsc);
6609 if (bits (insn, 5, 7) == 0) /* op2. */
6611 if (bits (insn, 12, 15) == 0xf)
6612 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
6614 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
6617 return arm_copy_undef (gdbarch, insn, dsc);
6619 case 0x1a: case 0x1b:
6620 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6621 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
6623 return arm_copy_undef (gdbarch, insn, dsc);
6625 case 0x1c: case 0x1d:
6626 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
6628 if (bits (insn, 0, 3) == 0xf)
6629 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
6631 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
6634 return arm_copy_undef (gdbarch, insn, dsc);
6636 case 0x1e: case 0x1f:
6637 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6638 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
6640 return arm_copy_undef (gdbarch, insn, dsc);
6643 /* Should be unreachable. */
6648 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn,
6649 struct regcache *regs,
6650 struct displaced_step_closure *dsc)
6653 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6655 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
6659 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
6660 struct regcache *regs,
6661 struct displaced_step_closure *dsc)
6663 unsigned int opcode = bits (insn, 20, 24);
6667 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6668 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
6670 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6671 case 0x12: case 0x16:
6672 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
6674 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6675 case 0x13: case 0x17:
6676 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
6678 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6679 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6680 /* Note: no writeback for these instructions. Bit 25 will always be
6681 zero though (via caller), so the following works OK. */
6682 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6685 /* Should be unreachable. */
6689 /* Decode shifted register instructions. */
6692 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
6693 uint16_t insn2, struct regcache *regs,
6694 struct displaced_step_closure *dsc)
6696 /* PC is only allowed to be used in instruction MOV. */
6698 unsigned int op = bits (insn1, 5, 8);
6699 unsigned int rn = bits (insn1, 0, 3);
6701 if (op == 0x2 && rn == 0xf) /* MOV */
6702 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
6704 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6705 "dp (shift reg)", dsc);
6709 /* Decode extension register load/store. Exactly the same as
6710 arm_decode_ext_reg_ld_st. */
6713 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
6714 uint16_t insn2, struct regcache *regs,
6715 struct displaced_step_closure *dsc)
6717 unsigned int opcode = bits (insn1, 4, 8);
6721 case 0x04: case 0x05:
6722 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6723 "vfp/neon vmov", dsc);
6725 case 0x08: case 0x0c: /* 01x00 */
6726 case 0x0a: case 0x0e: /* 01x10 */
6727 case 0x12: case 0x16: /* 10x10 */
6728 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6729 "vfp/neon vstm/vpush", dsc);
6731 case 0x09: case 0x0d: /* 01x01 */
6732 case 0x0b: case 0x0f: /* 01x11 */
6733 case 0x13: case 0x17: /* 10x11 */
6734 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6735 "vfp/neon vldm/vpop", dsc);
6737 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6738 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6740 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6741 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
6744 /* Should be unreachable. */
6749 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn,
6750 struct regcache *regs, struct displaced_step_closure *dsc)
6752 unsigned int op1 = bits (insn, 20, 25);
6753 int op = bit (insn, 4);
6754 unsigned int coproc = bits (insn, 8, 11);
6756 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
6757 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
6758 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
6759 && (coproc & 0xe) != 0xa)
6761 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6762 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
6763 && (coproc & 0xe) != 0xa)
6764 /* ldc/ldc2 imm/lit. */
6765 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6766 else if ((op1 & 0x3e) == 0x00)
6767 return arm_copy_undef (gdbarch, insn, dsc);
6768 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6769 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6770 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6771 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6772 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6773 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6774 else if ((op1 & 0x30) == 0x20 && !op)
6776 if ((coproc & 0xe) == 0xa)
6777 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6779 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6781 else if ((op1 & 0x30) == 0x20 && op)
6782 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6783 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6784 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6785 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6786 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6787 else if ((op1 & 0x30) == 0x30)
6788 return arm_copy_svc (gdbarch, insn, regs, dsc);
6790 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6794 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
6795 uint16_t insn2, struct regcache *regs,
6796 struct displaced_step_closure *dsc)
6798 unsigned int coproc = bits (insn2, 8, 11);
6799 unsigned int bit_5_8 = bits (insn1, 5, 8);
6800 unsigned int bit_9 = bit (insn1, 9);
6801 unsigned int bit_4 = bit (insn1, 4);
6806 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6807 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6809 else if (bit_5_8 == 0) /* UNDEFINED. */
6810 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
6813 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6814 if ((coproc & 0xe) == 0xa)
6815 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
6817 else /* coproc is not 101x. */
6819 if (bit_4 == 0) /* STC/STC2. */
6820 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6822 else /* LDC/LDC2 {literal, immeidate}. */
6823 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
6829 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
6835 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
6836 struct displaced_step_closure *dsc, int rd)
6842 Preparation: Rd <- PC
6848 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6849 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
6853 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
6854 struct displaced_step_closure *dsc,
6855 int rd, unsigned int imm)
6858 /* Encoding T2: ADDS Rd, #imm */
6859 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
6861 install_pc_relative (gdbarch, regs, dsc, rd);
6867 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
6868 struct regcache *regs,
6869 struct displaced_step_closure *dsc)
6871 unsigned int rd = bits (insn, 8, 10);
6872 unsigned int imm8 = bits (insn, 0, 7);
6874 if (debug_displaced)
6875 fprintf_unfiltered (gdb_stdlog,
6876 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6879 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
6883 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
6884 uint16_t insn2, struct regcache *regs,
6885 struct displaced_step_closure *dsc)
6887 unsigned int rd = bits (insn2, 8, 11);
6888 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6889 extract raw immediate encoding rather than computing immediate. When
6890 generating ADD or SUB instruction, we can simply perform OR operation to
6891 set immediate into ADD. */
6892 unsigned int imm_3_8 = insn2 & 0x70ff;
6893 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
6895 if (debug_displaced)
6896 fprintf_unfiltered (gdb_stdlog,
6897 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
6898 rd, imm_i, imm_3_8, insn1, insn2);
6900 if (bit (insn1, 7)) /* Encoding T2 */
6902 /* Encoding T3: SUB Rd, Rd, #imm */
6903 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
6904 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
6906 else /* Encoding T3 */
6908 /* Encoding T3: ADD Rd, Rd, #imm */
6909 dsc->modinsn[0] = (0xf100 | rd | imm_i);
6910 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
6914 install_pc_relative (gdbarch, regs, dsc, rd);
6920 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1,
6921 struct regcache *regs,
6922 struct displaced_step_closure *dsc)
6924 unsigned int rt = bits (insn1, 8, 10);
6926 int imm8 = (bits (insn1, 0, 7) << 2);
6932 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
6934 Insn: LDR R0, [R2, R3];
6935 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
6937 if (debug_displaced)
6938 fprintf_unfiltered (gdb_stdlog,
6939 "displaced: copying thumb ldr r%d [pc #%d]\n"
6942 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6943 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6944 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6945 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6946 /* The assembler calculates the required value of the offset from the
6947 Align(PC,4) value of this instruction to the label. */
6948 pc = pc & 0xfffffffc;
6950 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
6951 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
6954 dsc->u.ldst.xfersize = 4;
6956 dsc->u.ldst.immed = 0;
6957 dsc->u.ldst.writeback = 0;
6958 dsc->u.ldst.restore_r4 = 0;
6960 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
6962 dsc->cleanup = &cleanup_load;
6967 /* Copy Thumb cbnz/cbz insruction. */
6970 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
6971 struct regcache *regs,
6972 struct displaced_step_closure *dsc)
6974 int non_zero = bit (insn1, 11);
6975 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
6976 CORE_ADDR from = dsc->insn_addr;
6977 int rn = bits (insn1, 0, 2);
6978 int rn_val = displaced_read_reg (regs, dsc, rn);
6980 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
6981 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
6982 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
6983 condition is false, let it be, cleanup_branch will do nothing. */
6984 if (dsc->u.branch.cond)
6986 dsc->u.branch.cond = INST_AL;
6987 dsc->u.branch.dest = from + 4 + imm5;
6990 dsc->u.branch.dest = from + 2;
6992 dsc->u.branch.link = 0;
6993 dsc->u.branch.exchange = 0;
6995 if (debug_displaced)
6996 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
6997 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
6998 rn, rn_val, insn1, dsc->u.branch.dest);
7000 dsc->modinsn[0] = THUMB_NOP;
7002 dsc->cleanup = &cleanup_branch;
7006 /* Copy Table Branch Byte/Halfword */
7008 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7009 uint16_t insn2, struct regcache *regs,
7010 struct displaced_step_closure *dsc)
7012 ULONGEST rn_val, rm_val;
7013 int is_tbh = bit (insn2, 4);
7014 CORE_ADDR halfwords = 0;
7015 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7017 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7018 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7024 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7025 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7031 target_read_memory (rn_val + rm_val, buf, 1);
7032 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7035 if (debug_displaced)
7036 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7037 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7038 (unsigned int) rn_val, (unsigned int) rm_val,
7039 (unsigned int) halfwords);
7041 dsc->u.branch.cond = INST_AL;
7042 dsc->u.branch.link = 0;
7043 dsc->u.branch.exchange = 0;
7044 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7046 dsc->cleanup = &cleanup_branch;
7052 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
7053 struct displaced_step_closure *dsc)
7056 int val = displaced_read_reg (regs, dsc, 7);
7057 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
7060 val = displaced_read_reg (regs, dsc, 8);
7061 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
7064 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
7069 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1,
7070 struct regcache *regs,
7071 struct displaced_step_closure *dsc)
7073 dsc->u.block.regmask = insn1 & 0x00ff;
7075 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7078 (1) register list is full, that is, r0-r7 are used.
7079 Prepare: tmp[0] <- r8
7081 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7082 MOV r8, r7; Move value of r7 to r8;
7083 POP {r7}; Store PC value into r7.
7085 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7087 (2) register list is not full, supposing there are N registers in
7088 register list (except PC, 0 <= N <= 7).
7089 Prepare: for each i, 0 - N, tmp[i] <- ri.
7091 POP {r0, r1, ...., rN};
7093 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7094 from tmp[] properly.
7096 if (debug_displaced)
7097 fprintf_unfiltered (gdb_stdlog,
7098 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7099 dsc->u.block.regmask, insn1);
7101 if (dsc->u.block.regmask == 0xff)
7103 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
7105 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
7106 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
7107 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
7110 dsc->cleanup = &cleanup_pop_pc_16bit_all;
7114 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
7116 unsigned int new_regmask;
7118 for (i = 0; i < num_in_list + 1; i++)
7119 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7121 new_regmask = (1 << (num_in_list + 1)) - 1;
7123 if (debug_displaced)
7124 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
7125 "{..., pc}: original reg list %.4x,"
7126 " modified list %.4x\n"),
7127 (int) dsc->u.block.regmask, new_regmask);
7129 dsc->u.block.regmask |= 0x8000;
7130 dsc->u.block.writeback = 0;
7131 dsc->u.block.cond = INST_AL;
7133 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
7135 dsc->cleanup = &cleanup_block_load_pc;
7142 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7143 struct regcache *regs,
7144 struct displaced_step_closure *dsc)
7146 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
7147 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
7150 /* 16-bit thumb instructions. */
7151 switch (op_bit_12_15)
7153 /* Shift (imme), add, subtract, move and compare. */
7154 case 0: case 1: case 2: case 3:
7155 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7156 "shift/add/sub/mov/cmp",
7160 switch (op_bit_10_11)
7162 case 0: /* Data-processing */
7163 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7167 case 1: /* Special data instructions and branch and exchange. */
7169 unsigned short op = bits (insn1, 7, 9);
7170 if (op == 6 || op == 7) /* BX or BLX */
7171 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
7172 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7173 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
7175 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
7179 default: /* LDR (literal) */
7180 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
7183 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7184 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
7187 if (op_bit_10_11 < 2) /* Generate PC-relative address */
7188 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
7189 else /* Generate SP-relative address */
7190 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
7192 case 11: /* Misc 16-bit instructions */
7194 switch (bits (insn1, 8, 11))
7196 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7197 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
7199 case 12: case 13: /* POP */
7200 if (bit (insn1, 8)) /* PC is in register list. */
7201 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
7203 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
7205 case 15: /* If-Then, and hints */
7206 if (bits (insn1, 0, 3))
7207 /* If-Then makes up to four following instructions conditional.
7208 IT instruction itself is not conditional, so handle it as a
7209 common unmodified instruction. */
7210 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
7213 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
7216 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
7221 if (op_bit_10_11 < 2) /* Store multiple registers */
7222 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
7223 else /* Load multiple registers */
7224 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
7226 case 13: /* Conditional branch and supervisor call */
7227 if (bits (insn1, 9, 11) != 7) /* conditional branch */
7228 err = thumb_copy_b (gdbarch, insn1, dsc);
7230 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
7232 case 14: /* Unconditional branch */
7233 err = thumb_copy_b (gdbarch, insn1, dsc);
7240 internal_error (__FILE__, __LINE__,
7241 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7245 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
7246 uint16_t insn1, uint16_t insn2,
7247 struct regcache *regs,
7248 struct displaced_step_closure *dsc)
7250 int rt = bits (insn2, 12, 15);
7251 int rn = bits (insn1, 0, 3);
7252 int op1 = bits (insn1, 7, 8);
7254 switch (bits (insn1, 5, 6))
7256 case 0: /* Load byte and memory hints */
7257 if (rt == 0xf) /* PLD/PLI */
7260 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7261 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
7263 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7268 if (rn == 0xf) /* LDRB/LDRSB (literal) */
7269 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7272 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7273 "ldrb{reg, immediate}/ldrbt",
7278 case 1: /* Load halfword and memory hints. */
7279 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
7280 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7281 "pld/unalloc memhint", dsc);
7285 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7288 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7292 case 2: /* Load word */
7294 int insn2_bit_8_11 = bits (insn2, 8, 11);
7297 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
7298 else if (op1 == 0x1) /* Encoding T3 */
7299 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
7301 else /* op1 == 0x0 */
7303 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
7304 /* LDR (immediate) */
7305 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7306 dsc, bit (insn2, 8), 1);
7307 else if (insn2_bit_8_11 == 0xe) /* LDRT */
7308 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7311 /* LDR (register) */
7312 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7318 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7325 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7326 uint16_t insn2, struct regcache *regs,
7327 struct displaced_step_closure *dsc)
7330 unsigned short op = bit (insn2, 15);
7331 unsigned int op1 = bits (insn1, 11, 12);
7337 switch (bits (insn1, 9, 10))
7342 /* Load/store {dual, execlusive}, table branch. */
7343 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
7344 && bits (insn2, 5, 7) == 0)
7345 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
7348 /* PC is not allowed to use in load/store {dual, exclusive}
7350 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7351 "load/store dual/ex", dsc);
7353 else /* load/store multiple */
7355 switch (bits (insn1, 7, 8))
7357 case 0: case 3: /* SRS, RFE */
7358 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7361 case 1: case 2: /* LDM/STM/PUSH/POP */
7362 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
7369 /* Data-processing (shift register). */
7370 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
7373 default: /* Coprocessor instructions. */
7374 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7379 case 2: /* op1 = 2 */
7380 if (op) /* Branch and misc control. */
7382 if (bit (insn2, 14) /* BLX/BL */
7383 || bit (insn2, 12) /* Unconditional branch */
7384 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
7385 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
7387 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7392 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
7394 int op = bits (insn1, 4, 8);
7395 int rn = bits (insn1, 0, 3);
7396 if ((op == 0 || op == 0xa) && rn == 0xf)
7397 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
7400 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7403 else /* Data processing (modified immeidate) */
7404 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7408 case 3: /* op1 = 3 */
7409 switch (bits (insn1, 9, 10))
7413 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
7415 else /* NEON Load/Store and Store single data item */
7416 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7417 "neon elt/struct load/store",
7420 case 1: /* op1 = 3, bits (9, 10) == 1 */
7421 switch (bits (insn1, 7, 8))
7423 case 0: case 1: /* Data processing (register) */
7424 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7427 case 2: /* Multiply and absolute difference */
7428 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7429 "mul/mua/diff", dsc);
7431 case 3: /* Long multiply and divide */
7432 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7437 default: /* Coprocessor instructions */
7438 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7447 internal_error (__FILE__, __LINE__,
7448 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7453 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7454 struct regcache *regs,
7455 struct displaced_step_closure *dsc)
7457 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7459 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
7461 if (debug_displaced)
7462 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
7463 "at %.8lx\n", insn1, (unsigned long) from);
7466 dsc->insn_size = thumb_insn_size (insn1);
7467 if (thumb_insn_size (insn1) == 4)
7470 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
7471 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
7474 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
7478 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7479 CORE_ADDR to, struct regcache *regs,
7480 struct displaced_step_closure *dsc)
7483 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7486 /* Most displaced instructions use a 1-instruction scratch space, so set this
7487 here and override below if/when necessary. */
7489 dsc->insn_addr = from;
7490 dsc->scratch_base = to;
7491 dsc->cleanup = NULL;
7492 dsc->wrote_to_pc = 0;
7494 if (!displaced_in_arm_mode (regs))
7495 return thumb_process_displaced_insn (gdbarch, from, regs, dsc);
7499 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
7500 if (debug_displaced)
7501 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
7502 "at %.8lx\n", (unsigned long) insn,
7503 (unsigned long) from);
7505 if ((insn & 0xf0000000) == 0xf0000000)
7506 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
7507 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
7509 case 0x0: case 0x1: case 0x2: case 0x3:
7510 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
7513 case 0x4: case 0x5: case 0x6:
7514 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
7518 err = arm_decode_media (gdbarch, insn, dsc);
7521 case 0x8: case 0x9: case 0xa: case 0xb:
7522 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
7525 case 0xc: case 0xd: case 0xe: case 0xf:
7526 err = arm_decode_svc_copro (gdbarch, insn, regs, dsc);
7531 internal_error (__FILE__, __LINE__,
7532 _("arm_process_displaced_insn: Instruction decode error"));
7535 /* Actually set up the scratch space for a displaced instruction. */
7538 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
7539 CORE_ADDR to, struct displaced_step_closure *dsc)
7541 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7542 unsigned int i, len, offset;
7543 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7544 int size = dsc->is_thumb? 2 : 4;
7545 const gdb_byte *bkp_insn;
7548 /* Poke modified instruction(s). */
7549 for (i = 0; i < dsc->numinsns; i++)
7551 if (debug_displaced)
7553 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
7555 fprintf_unfiltered (gdb_stdlog, "%.8lx",
7558 fprintf_unfiltered (gdb_stdlog, "%.4x",
7559 (unsigned short)dsc->modinsn[i]);
7561 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
7562 (unsigned long) to + offset);
7565 write_memory_unsigned_integer (to + offset, size,
7566 byte_order_for_code,
7571 /* Choose the correct breakpoint instruction. */
7574 bkp_insn = tdep->thumb_breakpoint;
7575 len = tdep->thumb_breakpoint_size;
7579 bkp_insn = tdep->arm_breakpoint;
7580 len = tdep->arm_breakpoint_size;
7583 /* Put breakpoint afterwards. */
7584 write_memory (to + offset, bkp_insn, len);
7586 if (debug_displaced)
7587 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
7588 paddress (gdbarch, from), paddress (gdbarch, to));
7591 /* Entry point for cleaning things up after a displaced instruction has been
7595 arm_displaced_step_fixup (struct gdbarch *gdbarch,
7596 struct displaced_step_closure *dsc,
7597 CORE_ADDR from, CORE_ADDR to,
7598 struct regcache *regs)
7601 dsc->cleanup (gdbarch, regs, dsc);
7603 if (!dsc->wrote_to_pc)
7604 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
7605 dsc->insn_addr + dsc->insn_size);
7609 #include "bfd-in2.h"
7610 #include "libcoff.h"
7613 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
7615 struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
7617 if (arm_pc_is_thumb (gdbarch, memaddr))
7619 static asymbol *asym;
7620 static combined_entry_type ce;
7621 static struct coff_symbol_struct csym;
7622 static struct bfd fake_bfd;
7623 static bfd_target fake_target;
7625 if (csym.native == NULL)
7627 /* Create a fake symbol vector containing a Thumb symbol.
7628 This is solely so that the code in print_insn_little_arm()
7629 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7630 the presence of a Thumb symbol and switch to decoding
7631 Thumb instructions. */
7633 fake_target.flavour = bfd_target_coff_flavour;
7634 fake_bfd.xvec = &fake_target;
7635 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
7637 csym.symbol.the_bfd = &fake_bfd;
7638 csym.symbol.name = "fake";
7639 asym = (asymbol *) & csym;
7642 memaddr = UNMAKE_THUMB_ADDR (memaddr);
7643 info->symbols = &asym;
7646 info->symbols = NULL;
7648 if (info->endian == BFD_ENDIAN_BIG)
7649 return print_insn_big_arm (memaddr, info);
7651 return print_insn_little_arm (memaddr, info);
7654 /* The following define instruction sequences that will cause ARM
7655 cpu's to take an undefined instruction trap. These are used to
7656 signal a breakpoint to GDB.
7658 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7659 modes. A different instruction is required for each mode. The ARM
7660 cpu's can also be big or little endian. Thus four different
7661 instructions are needed to support all cases.
7663 Note: ARMv4 defines several new instructions that will take the
7664 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7665 not in fact add the new instructions. The new undefined
7666 instructions in ARMv4 are all instructions that had no defined
7667 behaviour in earlier chips. There is no guarantee that they will
7668 raise an exception, but may be treated as NOP's. In practice, it
7669 may only safe to rely on instructions matching:
7671 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7672 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7673 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7675 Even this may only true if the condition predicate is true. The
7676 following use a condition predicate of ALWAYS so it is always TRUE.
7678 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7679 and NetBSD all use a software interrupt rather than an undefined
7680 instruction to force a trap. This can be handled by by the
7681 abi-specific code during establishment of the gdbarch vector. */
7683 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7684 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7685 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7686 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7688 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
7689 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
7690 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
7691 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
7693 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7694 the program counter value to determine whether a 16-bit or 32-bit
7695 breakpoint should be used. It returns a pointer to a string of
7696 bytes that encode a breakpoint instruction, stores the length of
7697 the string to *lenptr, and adjusts the program counter (if
7698 necessary) to point to the actual memory location where the
7699 breakpoint should be inserted. */
7701 static const unsigned char *
7702 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
7704 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7705 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7707 if (arm_pc_is_thumb (gdbarch, *pcptr))
7709 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
7711 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7712 check whether we are replacing a 32-bit instruction. */
7713 if (tdep->thumb2_breakpoint != NULL)
7716 if (target_read_memory (*pcptr, buf, 2) == 0)
7718 unsigned short inst1;
7719 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
7720 if (thumb_insn_size (inst1) == 4)
7722 *lenptr = tdep->thumb2_breakpoint_size;
7723 return tdep->thumb2_breakpoint;
7728 *lenptr = tdep->thumb_breakpoint_size;
7729 return tdep->thumb_breakpoint;
7733 *lenptr = tdep->arm_breakpoint_size;
7734 return tdep->arm_breakpoint;
7739 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
7742 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
7744 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
7745 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7746 that this is not confused with a 32-bit ARM breakpoint. */
7750 /* Extract from an array REGBUF containing the (raw) register state a
7751 function return value of type TYPE, and copy that, in virtual
7752 format, into VALBUF. */
7755 arm_extract_return_value (struct type *type, struct regcache *regs,
7758 struct gdbarch *gdbarch = get_regcache_arch (regs);
7759 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7761 if (TYPE_CODE_FLT == TYPE_CODE (type))
7763 switch (gdbarch_tdep (gdbarch)->fp_model)
7767 /* The value is in register F0 in internal format. We need to
7768 extract the raw value and then convert it to the desired
7770 bfd_byte tmpbuf[FP_REGISTER_SIZE];
7772 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
7773 convert_from_extended (floatformat_from_type (type), tmpbuf,
7774 valbuf, gdbarch_byte_order (gdbarch));
7778 case ARM_FLOAT_SOFT_FPA:
7779 case ARM_FLOAT_SOFT_VFP:
7780 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7781 not using the VFP ABI code. */
7783 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
7784 if (TYPE_LENGTH (type) > 4)
7785 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7786 valbuf + INT_REGISTER_SIZE);
7790 internal_error (__FILE__, __LINE__,
7791 _("arm_extract_return_value: "
7792 "Floating point model not supported"));
7796 else if (TYPE_CODE (type) == TYPE_CODE_INT
7797 || TYPE_CODE (type) == TYPE_CODE_CHAR
7798 || TYPE_CODE (type) == TYPE_CODE_BOOL
7799 || TYPE_CODE (type) == TYPE_CODE_PTR
7800 || TYPE_CODE (type) == TYPE_CODE_REF
7801 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7803 /* If the type is a plain integer, then the access is
7804 straight-forward. Otherwise we have to play around a bit
7806 int len = TYPE_LENGTH (type);
7807 int regno = ARM_A1_REGNUM;
7812 /* By using store_unsigned_integer we avoid having to do
7813 anything special for small big-endian values. */
7814 regcache_cooked_read_unsigned (regs, regno++, &tmp);
7815 store_unsigned_integer (valbuf,
7816 (len > INT_REGISTER_SIZE
7817 ? INT_REGISTER_SIZE : len),
7819 len -= INT_REGISTER_SIZE;
7820 valbuf += INT_REGISTER_SIZE;
7825 /* For a structure or union the behaviour is as if the value had
7826 been stored to word-aligned memory and then loaded into
7827 registers with 32-bit load instruction(s). */
7828 int len = TYPE_LENGTH (type);
7829 int regno = ARM_A1_REGNUM;
7830 bfd_byte tmpbuf[INT_REGISTER_SIZE];
7834 regcache_cooked_read (regs, regno++, tmpbuf);
7835 memcpy (valbuf, tmpbuf,
7836 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
7837 len -= INT_REGISTER_SIZE;
7838 valbuf += INT_REGISTER_SIZE;
7844 /* Will a function return an aggregate type in memory or in a
7845 register? Return 0 if an aggregate type can be returned in a
7846 register, 1 if it must be returned in memory. */
7849 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
7851 enum type_code code;
7853 type = check_typedef (type);
7855 /* Simple, non-aggregate types (ie not including vectors and
7856 complex) are always returned in a register (or registers). */
7857 code = TYPE_CODE (type);
7858 if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code
7859 && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code)
7862 if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type))
7864 /* Vector values should be returned using ARM registers if they
7865 are not over 16 bytes. */
7866 return (TYPE_LENGTH (type) > 16);
7869 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
7871 /* The AAPCS says all aggregates not larger than a word are returned
7873 if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
7882 /* All aggregate types that won't fit in a register must be returned
7884 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
7887 /* In the ARM ABI, "integer" like aggregate types are returned in
7888 registers. For an aggregate type to be integer like, its size
7889 must be less than or equal to INT_REGISTER_SIZE and the
7890 offset of each addressable subfield must be zero. Note that bit
7891 fields are not addressable, and all addressable subfields of
7892 unions always start at offset zero.
7894 This function is based on the behaviour of GCC 2.95.1.
7895 See: gcc/arm.c: arm_return_in_memory() for details.
7897 Note: All versions of GCC before GCC 2.95.2 do not set up the
7898 parameters correctly for a function returning the following
7899 structure: struct { float f;}; This should be returned in memory,
7900 not a register. Richard Earnshaw sent me a patch, but I do not
7901 know of any way to detect if a function like the above has been
7902 compiled with the correct calling convention. */
7904 /* Assume all other aggregate types can be returned in a register.
7905 Run a check for structures, unions and arrays. */
7908 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
7911 /* Need to check if this struct/union is "integer" like. For
7912 this to be true, its size must be less than or equal to
7913 INT_REGISTER_SIZE and the offset of each addressable
7914 subfield must be zero. Note that bit fields are not
7915 addressable, and unions always start at offset zero. If any
7916 of the subfields is a floating point type, the struct/union
7917 cannot be an integer type. */
7919 /* For each field in the object, check:
7920 1) Is it FP? --> yes, nRc = 1;
7921 2) Is it addressable (bitpos != 0) and
7922 not packed (bitsize == 0)?
7926 for (i = 0; i < TYPE_NFIELDS (type); i++)
7928 enum type_code field_type_code;
7931 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
7934 /* Is it a floating point type field? */
7935 if (field_type_code == TYPE_CODE_FLT)
7941 /* If bitpos != 0, then we have to care about it. */
7942 if (TYPE_FIELD_BITPOS (type, i) != 0)
7944 /* Bitfields are not addressable. If the field bitsize is
7945 zero, then the field is not packed. Hence it cannot be
7946 a bitfield or any other packed type. */
7947 if (TYPE_FIELD_BITSIZE (type, i) == 0)
7960 /* Write into appropriate registers a function return value of type
7961 TYPE, given in virtual format. */
7964 arm_store_return_value (struct type *type, struct regcache *regs,
7965 const gdb_byte *valbuf)
7967 struct gdbarch *gdbarch = get_regcache_arch (regs);
7968 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7970 if (TYPE_CODE (type) == TYPE_CODE_FLT)
7972 gdb_byte buf[MAX_REGISTER_SIZE];
7974 switch (gdbarch_tdep (gdbarch)->fp_model)
7978 convert_to_extended (floatformat_from_type (type), buf, valbuf,
7979 gdbarch_byte_order (gdbarch));
7980 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
7983 case ARM_FLOAT_SOFT_FPA:
7984 case ARM_FLOAT_SOFT_VFP:
7985 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7986 not using the VFP ABI code. */
7988 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
7989 if (TYPE_LENGTH (type) > 4)
7990 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
7991 valbuf + INT_REGISTER_SIZE);
7995 internal_error (__FILE__, __LINE__,
7996 _("arm_store_return_value: Floating "
7997 "point model not supported"));
8001 else if (TYPE_CODE (type) == TYPE_CODE_INT
8002 || TYPE_CODE (type) == TYPE_CODE_CHAR
8003 || TYPE_CODE (type) == TYPE_CODE_BOOL
8004 || TYPE_CODE (type) == TYPE_CODE_PTR
8005 || TYPE_CODE (type) == TYPE_CODE_REF
8006 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8008 if (TYPE_LENGTH (type) <= 4)
8010 /* Values of one word or less are zero/sign-extended and
8012 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8013 LONGEST val = unpack_long (type, valbuf);
8015 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8016 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8020 /* Integral values greater than one word are stored in consecutive
8021 registers starting with r0. This will always be a multiple of
8022 the regiser size. */
8023 int len = TYPE_LENGTH (type);
8024 int regno = ARM_A1_REGNUM;
8028 regcache_cooked_write (regs, regno++, valbuf);
8029 len -= INT_REGISTER_SIZE;
8030 valbuf += INT_REGISTER_SIZE;
8036 /* For a structure or union the behaviour is as if the value had
8037 been stored to word-aligned memory and then loaded into
8038 registers with 32-bit load instruction(s). */
8039 int len = TYPE_LENGTH (type);
8040 int regno = ARM_A1_REGNUM;
8041 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8045 memcpy (tmpbuf, valbuf,
8046 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8047 regcache_cooked_write (regs, regno++, tmpbuf);
8048 len -= INT_REGISTER_SIZE;
8049 valbuf += INT_REGISTER_SIZE;
8055 /* Handle function return values. */
8057 static enum return_value_convention
8058 arm_return_value (struct gdbarch *gdbarch, struct value *function,
8059 struct type *valtype, struct regcache *regcache,
8060 gdb_byte *readbuf, const gdb_byte *writebuf)
8062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8063 struct type *func_type = function ? value_type (function) : NULL;
8064 enum arm_vfp_cprc_base_type vfp_base_type;
8067 if (arm_vfp_abi_for_function (gdbarch, func_type)
8068 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
8070 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
8071 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
8073 for (i = 0; i < vfp_base_count; i++)
8075 if (reg_char == 'q')
8078 arm_neon_quad_write (gdbarch, regcache, i,
8079 writebuf + i * unit_length);
8082 arm_neon_quad_read (gdbarch, regcache, i,
8083 readbuf + i * unit_length);
8090 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
8091 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8094 regcache_cooked_write (regcache, regnum,
8095 writebuf + i * unit_length);
8097 regcache_cooked_read (regcache, regnum,
8098 readbuf + i * unit_length);
8101 return RETURN_VALUE_REGISTER_CONVENTION;
8104 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
8105 || TYPE_CODE (valtype) == TYPE_CODE_UNION
8106 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
8108 if (tdep->struct_return == pcc_struct_return
8109 || arm_return_in_memory (gdbarch, valtype))
8110 return RETURN_VALUE_STRUCT_CONVENTION;
8112 else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX)
8114 if (arm_return_in_memory (gdbarch, valtype))
8115 return RETURN_VALUE_STRUCT_CONVENTION;
8119 arm_store_return_value (valtype, regcache, writebuf);
8122 arm_extract_return_value (valtype, regcache, readbuf);
8124 return RETURN_VALUE_REGISTER_CONVENTION;
8129 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
8131 struct gdbarch *gdbarch = get_frame_arch (frame);
8132 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8133 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8135 gdb_byte buf[INT_REGISTER_SIZE];
8137 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
8139 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
8143 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
8147 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8148 return the target PC. Otherwise return 0. */
8151 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
8155 CORE_ADDR start_addr;
8157 /* Find the starting address and name of the function containing the PC. */
8158 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
8160 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8162 start_addr = arm_skip_bx_reg (frame, pc);
8163 if (start_addr != 0)
8169 /* If PC is in a Thumb call or return stub, return the address of the
8170 target PC, which is in a register. The thunk functions are called
8171 _call_via_xx, where x is the register name. The possible names
8172 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8173 functions, named __ARM_call_via_r[0-7]. */
8174 if (startswith (name, "_call_via_")
8175 || startswith (name, "__ARM_call_via_"))
8177 /* Use the name suffix to determine which register contains the
8179 static char *table[15] =
8180 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8181 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8184 int offset = strlen (name) - 2;
8186 for (regno = 0; regno <= 14; regno++)
8187 if (strcmp (&name[offset], table[regno]) == 0)
8188 return get_frame_register_unsigned (frame, regno);
8191 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8192 non-interworking calls to foo. We could decode the stubs
8193 to find the target but it's easier to use the symbol table. */
8194 namelen = strlen (name);
8195 if (name[0] == '_' && name[1] == '_'
8196 && ((namelen > 2 + strlen ("_from_thumb")
8197 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
8198 || (namelen > 2 + strlen ("_from_arm")
8199 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
8202 int target_len = namelen - 2;
8203 struct bound_minimal_symbol minsym;
8204 struct objfile *objfile;
8205 struct obj_section *sec;
8207 if (name[namelen - 1] == 'b')
8208 target_len -= strlen ("_from_thumb");
8210 target_len -= strlen ("_from_arm");
8212 target_name = (char *) alloca (target_len + 1);
8213 memcpy (target_name, name + 2, target_len);
8214 target_name[target_len] = '\0';
8216 sec = find_pc_section (pc);
8217 objfile = (sec == NULL) ? NULL : sec->objfile;
8218 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
8219 if (minsym.minsym != NULL)
8220 return BMSYMBOL_VALUE_ADDRESS (minsym);
8225 return 0; /* not a stub */
8229 set_arm_command (char *args, int from_tty)
8231 printf_unfiltered (_("\
8232 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8233 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
8237 show_arm_command (char *args, int from_tty)
8239 cmd_show_list (showarmcmdlist, from_tty, "");
8243 arm_update_current_architecture (void)
8245 struct gdbarch_info info;
8247 /* If the current architecture is not ARM, we have nothing to do. */
8248 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
8251 /* Update the architecture. */
8252 gdbarch_info_init (&info);
8254 if (!gdbarch_update_p (info))
8255 internal_error (__FILE__, __LINE__, _("could not update architecture"));
8259 set_fp_model_sfunc (char *args, int from_tty,
8260 struct cmd_list_element *c)
8264 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
8265 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
8267 arm_fp_model = (enum arm_float_model) fp_model;
8271 if (fp_model == ARM_FLOAT_LAST)
8272 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
8275 arm_update_current_architecture ();
8279 show_fp_model (struct ui_file *file, int from_tty,
8280 struct cmd_list_element *c, const char *value)
8282 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8284 if (arm_fp_model == ARM_FLOAT_AUTO
8285 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8286 fprintf_filtered (file, _("\
8287 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8288 fp_model_strings[tdep->fp_model]);
8290 fprintf_filtered (file, _("\
8291 The current ARM floating point model is \"%s\".\n"),
8292 fp_model_strings[arm_fp_model]);
8296 arm_set_abi (char *args, int from_tty,
8297 struct cmd_list_element *c)
8301 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
8302 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
8304 arm_abi_global = (enum arm_abi_kind) arm_abi;
8308 if (arm_abi == ARM_ABI_LAST)
8309 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
8312 arm_update_current_architecture ();
8316 arm_show_abi (struct ui_file *file, int from_tty,
8317 struct cmd_list_element *c, const char *value)
8319 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8321 if (arm_abi_global == ARM_ABI_AUTO
8322 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8323 fprintf_filtered (file, _("\
8324 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8325 arm_abi_strings[tdep->arm_abi]);
8327 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
8332 arm_show_fallback_mode (struct ui_file *file, int from_tty,
8333 struct cmd_list_element *c, const char *value)
8335 fprintf_filtered (file,
8336 _("The current execution mode assumed "
8337 "(when symbols are unavailable) is \"%s\".\n"),
8338 arm_fallback_mode_string);
8342 arm_show_force_mode (struct ui_file *file, int from_tty,
8343 struct cmd_list_element *c, const char *value)
8345 fprintf_filtered (file,
8346 _("The current execution mode assumed "
8347 "(even when symbols are available) is \"%s\".\n"),
8348 arm_force_mode_string);
8351 /* If the user changes the register disassembly style used for info
8352 register and other commands, we have to also switch the style used
8353 in opcodes for disassembly output. This function is run in the "set
8354 arm disassembly" command, and does that. */
8357 set_disassembly_style_sfunc (char *args, int from_tty,
8358 struct cmd_list_element *c)
8360 set_disassembly_style ();
8363 /* Return the ARM register name corresponding to register I. */
8365 arm_register_name (struct gdbarch *gdbarch, int i)
8367 const int num_regs = gdbarch_num_regs (gdbarch);
8369 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
8370 && i >= num_regs && i < num_regs + 32)
8372 static const char *const vfp_pseudo_names[] = {
8373 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8374 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8375 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8376 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8379 return vfp_pseudo_names[i - num_regs];
8382 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
8383 && i >= num_regs + 32 && i < num_regs + 32 + 16)
8385 static const char *const neon_pseudo_names[] = {
8386 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8387 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8390 return neon_pseudo_names[i - num_regs - 32];
8393 if (i >= ARRAY_SIZE (arm_register_names))
8394 /* These registers are only supported on targets which supply
8395 an XML description. */
8398 return arm_register_names[i];
8402 set_disassembly_style (void)
8406 /* Find the style that the user wants. */
8407 for (current = 0; current < num_disassembly_options; current++)
8408 if (disassembly_style == valid_disassembly_styles[current])
8410 gdb_assert (current < num_disassembly_options);
8412 /* Synchronize the disassembler. */
8413 set_arm_regname_option (current);
8416 /* Test whether the coff symbol specific value corresponds to a Thumb
8420 coff_sym_is_thumb (int val)
8422 return (val == C_THUMBEXT
8423 || val == C_THUMBSTAT
8424 || val == C_THUMBEXTFUNC
8425 || val == C_THUMBSTATFUNC
8426 || val == C_THUMBLABEL);
8429 /* arm_coff_make_msymbol_special()
8430 arm_elf_make_msymbol_special()
8432 These functions test whether the COFF or ELF symbol corresponds to
8433 an address in thumb code, and set a "special" bit in a minimal
8434 symbol to indicate that it does. */
8437 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
8439 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
8440 == ST_BRANCH_TO_THUMB)
8441 MSYMBOL_SET_SPECIAL (msym);
8445 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
8447 if (coff_sym_is_thumb (val))
8448 MSYMBOL_SET_SPECIAL (msym);
8452 arm_objfile_data_free (struct objfile *objfile, void *arg)
8454 struct arm_per_objfile *data = (struct arm_per_objfile *) arg;
8457 for (i = 0; i < objfile->obfd->section_count; i++)
8458 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
8462 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
8465 const char *name = bfd_asymbol_name (sym);
8466 struct arm_per_objfile *data;
8467 VEC(arm_mapping_symbol_s) **map_p;
8468 struct arm_mapping_symbol new_map_sym;
8470 gdb_assert (name[0] == '$');
8471 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
8474 data = (struct arm_per_objfile *) objfile_data (objfile,
8475 arm_objfile_data_key);
8478 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
8479 struct arm_per_objfile);
8480 set_objfile_data (objfile, arm_objfile_data_key, data);
8481 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
8482 objfile->obfd->section_count,
8483 VEC(arm_mapping_symbol_s) *);
8485 map_p = &data->section_maps[bfd_get_section (sym)->index];
8487 new_map_sym.value = sym->value;
8488 new_map_sym.type = name[1];
8490 /* Assume that most mapping symbols appear in order of increasing
8491 value. If they were randomly distributed, it would be faster to
8492 always push here and then sort at first use. */
8493 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
8495 struct arm_mapping_symbol *prev_map_sym;
8497 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
8498 if (prev_map_sym->value >= sym->value)
8501 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
8502 arm_compare_mapping_symbols);
8503 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
8508 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
8512 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
8514 struct gdbarch *gdbarch = get_regcache_arch (regcache);
8515 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
8517 /* If necessary, set the T bit. */
8520 ULONGEST val, t_bit;
8521 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
8522 t_bit = arm_psr_thumb_bit (gdbarch);
8523 if (arm_pc_is_thumb (gdbarch, pc))
8524 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8527 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8532 /* Read the contents of a NEON quad register, by reading from two
8533 double registers. This is used to implement the quad pseudo
8534 registers, and for argument passing in case the quad registers are
8535 missing; vectors are passed in quad registers when using the VFP
8536 ABI, even if a NEON unit is not present. REGNUM is the index of
8537 the quad register, in [0, 15]. */
8539 static enum register_status
8540 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
8541 int regnum, gdb_byte *buf)
8544 gdb_byte reg_buf[8];
8545 int offset, double_regnum;
8546 enum register_status status;
8548 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8549 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8552 /* d0 is always the least significant half of q0. */
8553 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8558 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8559 if (status != REG_VALID)
8561 memcpy (buf + offset, reg_buf, 8);
8563 offset = 8 - offset;
8564 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
8565 if (status != REG_VALID)
8567 memcpy (buf + offset, reg_buf, 8);
8572 static enum register_status
8573 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
8574 int regnum, gdb_byte *buf)
8576 const int num_regs = gdbarch_num_regs (gdbarch);
8578 gdb_byte reg_buf[8];
8579 int offset, double_regnum;
8581 gdb_assert (regnum >= num_regs);
8584 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8585 /* Quad-precision register. */
8586 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
8589 enum register_status status;
8591 /* Single-precision register. */
8592 gdb_assert (regnum < 32);
8594 /* s0 is always the least significant half of d0. */
8595 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8596 offset = (regnum & 1) ? 0 : 4;
8598 offset = (regnum & 1) ? 4 : 0;
8600 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8601 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8604 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8605 if (status == REG_VALID)
8606 memcpy (buf, reg_buf + offset, 4);
8611 /* Store the contents of BUF to a NEON quad register, by writing to
8612 two double registers. This is used to implement the quad pseudo
8613 registers, and for argument passing in case the quad registers are
8614 missing; vectors are passed in quad registers when using the VFP
8615 ABI, even if a NEON unit is not present. REGNUM is the index
8616 of the quad register, in [0, 15]. */
8619 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
8620 int regnum, const gdb_byte *buf)
8623 int offset, double_regnum;
8625 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8626 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8629 /* d0 is always the least significant half of q0. */
8630 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8635 regcache_raw_write (regcache, double_regnum, buf + offset);
8636 offset = 8 - offset;
8637 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
8641 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
8642 int regnum, const gdb_byte *buf)
8644 const int num_regs = gdbarch_num_regs (gdbarch);
8646 gdb_byte reg_buf[8];
8647 int offset, double_regnum;
8649 gdb_assert (regnum >= num_regs);
8652 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8653 /* Quad-precision register. */
8654 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
8657 /* Single-precision register. */
8658 gdb_assert (regnum < 32);
8660 /* s0 is always the least significant half of d0. */
8661 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8662 offset = (regnum & 1) ? 0 : 4;
8664 offset = (regnum & 1) ? 4 : 0;
8666 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8667 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8670 regcache_raw_read (regcache, double_regnum, reg_buf);
8671 memcpy (reg_buf + offset, buf, 4);
8672 regcache_raw_write (regcache, double_regnum, reg_buf);
8676 static struct value *
8677 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
8679 const int *reg_p = (const int *) baton;
8680 return value_of_register (*reg_p, frame);
8683 static enum gdb_osabi
8684 arm_elf_osabi_sniffer (bfd *abfd)
8686 unsigned int elfosabi;
8687 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
8689 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
8691 if (elfosabi == ELFOSABI_ARM)
8692 /* GNU tools use this value. Check note sections in this case,
8694 bfd_map_over_sections (abfd,
8695 generic_elf_osabi_sniff_abi_tag_sections,
8698 /* Anything else will be handled by the generic ELF sniffer. */
8703 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
8704 struct reggroup *group)
8706 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8707 this, FPS register belongs to save_regroup, restore_reggroup, and
8708 all_reggroup, of course. */
8709 if (regnum == ARM_FPS_REGNUM)
8710 return (group == float_reggroup
8711 || group == save_reggroup
8712 || group == restore_reggroup
8713 || group == all_reggroup);
8715 return default_register_reggroup_p (gdbarch, regnum, group);
8719 /* For backward-compatibility we allow two 'g' packet lengths with
8720 the remote protocol depending on whether FPA registers are
8721 supplied. M-profile targets do not have FPA registers, but some
8722 stubs already exist in the wild which use a 'g' packet which
8723 supplies them albeit with dummy values. The packet format which
8724 includes FPA registers should be considered deprecated for
8725 M-profile targets. */
8728 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
8730 if (gdbarch_tdep (gdbarch)->is_m)
8732 /* If we know from the executable this is an M-profile target,
8733 cater for remote targets whose register set layout is the
8734 same as the FPA layout. */
8735 register_remote_g_packet_guess (gdbarch,
8736 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8737 (16 * INT_REGISTER_SIZE)
8738 + (8 * FP_REGISTER_SIZE)
8739 + (2 * INT_REGISTER_SIZE),
8740 tdesc_arm_with_m_fpa_layout);
8742 /* The regular M-profile layout. */
8743 register_remote_g_packet_guess (gdbarch,
8744 /* r0-r12,sp,lr,pc; xpsr */
8745 (16 * INT_REGISTER_SIZE)
8746 + INT_REGISTER_SIZE,
8749 /* M-profile plus M4F VFP. */
8750 register_remote_g_packet_guess (gdbarch,
8751 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8752 (16 * INT_REGISTER_SIZE)
8753 + (16 * VFP_REGISTER_SIZE)
8754 + (2 * INT_REGISTER_SIZE),
8755 tdesc_arm_with_m_vfp_d16);
8758 /* Otherwise we don't have a useful guess. */
8762 /* Initialize the current architecture based on INFO. If possible,
8763 re-use an architecture from ARCHES, which is a list of
8764 architectures already created during this debugging session.
8766 Called e.g. at program startup, when reading a core file, and when
8767 reading a binary file. */
8769 static struct gdbarch *
8770 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8772 struct gdbarch_tdep *tdep;
8773 struct gdbarch *gdbarch;
8774 struct gdbarch_list *best_arch;
8775 enum arm_abi_kind arm_abi = arm_abi_global;
8776 enum arm_float_model fp_model = arm_fp_model;
8777 struct tdesc_arch_data *tdesc_data = NULL;
8779 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
8780 int have_wmmx_registers = 0;
8782 int have_fpa_registers = 1;
8783 const struct target_desc *tdesc = info.target_desc;
8785 /* If we have an object to base this architecture on, try to determine
8788 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
8790 int ei_osabi, e_flags;
8792 switch (bfd_get_flavour (info.abfd))
8794 case bfd_target_aout_flavour:
8795 /* Assume it's an old APCS-style ABI. */
8796 arm_abi = ARM_ABI_APCS;
8799 case bfd_target_coff_flavour:
8800 /* Assume it's an old APCS-style ABI. */
8802 arm_abi = ARM_ABI_APCS;
8805 case bfd_target_elf_flavour:
8806 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
8807 e_flags = elf_elfheader (info.abfd)->e_flags;
8809 if (ei_osabi == ELFOSABI_ARM)
8811 /* GNU tools used to use this value, but do not for EABI
8812 objects. There's nowhere to tag an EABI version
8813 anyway, so assume APCS. */
8814 arm_abi = ARM_ABI_APCS;
8816 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
8818 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
8819 int attr_arch, attr_profile;
8823 case EF_ARM_EABI_UNKNOWN:
8824 /* Assume GNU tools. */
8825 arm_abi = ARM_ABI_APCS;
8828 case EF_ARM_EABI_VER4:
8829 case EF_ARM_EABI_VER5:
8830 arm_abi = ARM_ABI_AAPCS;
8831 /* EABI binaries default to VFP float ordering.
8832 They may also contain build attributes that can
8833 be used to identify if the VFP argument-passing
8835 if (fp_model == ARM_FLOAT_AUTO)
8838 switch (bfd_elf_get_obj_attr_int (info.abfd,
8842 case AEABI_VFP_args_base:
8843 /* "The user intended FP parameter/result
8844 passing to conform to AAPCS, base
8846 fp_model = ARM_FLOAT_SOFT_VFP;
8848 case AEABI_VFP_args_vfp:
8849 /* "The user intended FP parameter/result
8850 passing to conform to AAPCS, VFP
8852 fp_model = ARM_FLOAT_VFP;
8854 case AEABI_VFP_args_toolchain:
8855 /* "The user intended FP parameter/result
8856 passing to conform to tool chain-specific
8857 conventions" - we don't know any such
8858 conventions, so leave it as "auto". */
8860 case AEABI_VFP_args_compatible:
8861 /* "Code is compatible with both the base
8862 and VFP variants; the user did not permit
8863 non-variadic functions to pass FP
8864 parameters/results" - leave it as
8868 /* Attribute value not mentioned in the
8869 November 2012 ABI, so leave it as
8874 fp_model = ARM_FLOAT_SOFT_VFP;
8880 /* Leave it as "auto". */
8881 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
8886 /* Detect M-profile programs. This only works if the
8887 executable file includes build attributes; GCC does
8888 copy them to the executable, but e.g. RealView does
8890 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
8892 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
8894 Tag_CPU_arch_profile);
8895 /* GCC specifies the profile for v6-M; RealView only
8896 specifies the profile for architectures starting with
8897 V7 (as opposed to architectures with a tag
8898 numerically greater than TAG_CPU_ARCH_V7). */
8899 if (!tdesc_has_registers (tdesc)
8900 && (attr_arch == TAG_CPU_ARCH_V6_M
8901 || attr_arch == TAG_CPU_ARCH_V6S_M
8902 || attr_profile == 'M'))
8907 if (fp_model == ARM_FLOAT_AUTO)
8909 int e_flags = elf_elfheader (info.abfd)->e_flags;
8911 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
8914 /* Leave it as "auto". Strictly speaking this case
8915 means FPA, but almost nobody uses that now, and
8916 many toolchains fail to set the appropriate bits
8917 for the floating-point model they use. */
8919 case EF_ARM_SOFT_FLOAT:
8920 fp_model = ARM_FLOAT_SOFT_FPA;
8922 case EF_ARM_VFP_FLOAT:
8923 fp_model = ARM_FLOAT_VFP;
8925 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
8926 fp_model = ARM_FLOAT_SOFT_VFP;
8931 if (e_flags & EF_ARM_BE8)
8932 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
8937 /* Leave it as "auto". */
8942 /* Check any target description for validity. */
8943 if (tdesc_has_registers (tdesc))
8945 /* For most registers we require GDB's default names; but also allow
8946 the numeric names for sp / lr / pc, as a convenience. */
8947 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
8948 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
8949 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
8951 const struct tdesc_feature *feature;
8954 feature = tdesc_find_feature (tdesc,
8955 "org.gnu.gdb.arm.core");
8956 if (feature == NULL)
8958 feature = tdesc_find_feature (tdesc,
8959 "org.gnu.gdb.arm.m-profile");
8960 if (feature == NULL)
8966 tdesc_data = tdesc_data_alloc ();
8969 for (i = 0; i < ARM_SP_REGNUM; i++)
8970 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8971 arm_register_names[i]);
8972 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8975 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8978 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8982 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8983 ARM_PS_REGNUM, "xpsr");
8985 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8986 ARM_PS_REGNUM, "cpsr");
8990 tdesc_data_cleanup (tdesc_data);
8994 feature = tdesc_find_feature (tdesc,
8995 "org.gnu.gdb.arm.fpa");
8996 if (feature != NULL)
8999 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9000 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9001 arm_register_names[i]);
9004 tdesc_data_cleanup (tdesc_data);
9009 have_fpa_registers = 0;
9011 feature = tdesc_find_feature (tdesc,
9012 "org.gnu.gdb.xscale.iwmmxt");
9013 if (feature != NULL)
9015 static const char *const iwmmxt_names[] = {
9016 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9017 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9018 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9019 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9023 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9025 &= tdesc_numbered_register (feature, tdesc_data, i,
9026 iwmmxt_names[i - ARM_WR0_REGNUM]);
9028 /* Check for the control registers, but do not fail if they
9030 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9031 tdesc_numbered_register (feature, tdesc_data, i,
9032 iwmmxt_names[i - ARM_WR0_REGNUM]);
9034 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9036 &= tdesc_numbered_register (feature, tdesc_data, i,
9037 iwmmxt_names[i - ARM_WR0_REGNUM]);
9041 tdesc_data_cleanup (tdesc_data);
9045 have_wmmx_registers = 1;
9048 /* If we have a VFP unit, check whether the single precision registers
9049 are present. If not, then we will synthesize them as pseudo
9051 feature = tdesc_find_feature (tdesc,
9052 "org.gnu.gdb.arm.vfp");
9053 if (feature != NULL)
9055 static const char *const vfp_double_names[] = {
9056 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9057 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9058 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9059 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9062 /* Require the double precision registers. There must be either
9065 for (i = 0; i < 32; i++)
9067 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9069 vfp_double_names[i]);
9073 if (!valid_p && i == 16)
9076 /* Also require FPSCR. */
9077 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9078 ARM_FPSCR_REGNUM, "fpscr");
9081 tdesc_data_cleanup (tdesc_data);
9085 if (tdesc_unnumbered_register (feature, "s0") == 0)
9086 have_vfp_pseudos = 1;
9088 vfp_register_count = i;
9090 /* If we have VFP, also check for NEON. The architecture allows
9091 NEON without VFP (integer vector operations only), but GDB
9092 does not support that. */
9093 feature = tdesc_find_feature (tdesc,
9094 "org.gnu.gdb.arm.neon");
9095 if (feature != NULL)
9097 /* NEON requires 32 double-precision registers. */
9100 tdesc_data_cleanup (tdesc_data);
9104 /* If there are quad registers defined by the stub, use
9105 their type; otherwise (normally) provide them with
9106 the default type. */
9107 if (tdesc_unnumbered_register (feature, "q0") == 0)
9108 have_neon_pseudos = 1;
9115 /* If there is already a candidate, use it. */
9116 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
9118 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
9120 if (arm_abi != ARM_ABI_AUTO
9121 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
9124 if (fp_model != ARM_FLOAT_AUTO
9125 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
9128 /* There are various other properties in tdep that we do not
9129 need to check here: those derived from a target description,
9130 since gdbarches with a different target description are
9131 automatically disqualified. */
9133 /* Do check is_m, though, since it might come from the binary. */
9134 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
9137 /* Found a match. */
9141 if (best_arch != NULL)
9143 if (tdesc_data != NULL)
9144 tdesc_data_cleanup (tdesc_data);
9145 return best_arch->gdbarch;
9148 tdep = XCNEW (struct gdbarch_tdep);
9149 gdbarch = gdbarch_alloc (&info, tdep);
9151 /* Record additional information about the architecture we are defining.
9152 These are gdbarch discriminators, like the OSABI. */
9153 tdep->arm_abi = arm_abi;
9154 tdep->fp_model = fp_model;
9156 tdep->have_fpa_registers = have_fpa_registers;
9157 tdep->have_wmmx_registers = have_wmmx_registers;
9158 gdb_assert (vfp_register_count == 0
9159 || vfp_register_count == 16
9160 || vfp_register_count == 32);
9161 tdep->vfp_register_count = vfp_register_count;
9162 tdep->have_vfp_pseudos = have_vfp_pseudos;
9163 tdep->have_neon_pseudos = have_neon_pseudos;
9164 tdep->have_neon = have_neon;
9166 arm_register_g_packet_guesses (gdbarch);
9169 switch (info.byte_order_for_code)
9171 case BFD_ENDIAN_BIG:
9172 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
9173 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
9174 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
9175 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
9179 case BFD_ENDIAN_LITTLE:
9180 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
9181 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
9182 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
9183 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
9188 internal_error (__FILE__, __LINE__,
9189 _("arm_gdbarch_init: bad byte order for float format"));
9192 /* On ARM targets char defaults to unsigned. */
9193 set_gdbarch_char_signed (gdbarch, 0);
9195 /* Note: for displaced stepping, this includes the breakpoint, and one word
9196 of additional scratch space. This setting isn't used for anything beside
9197 displaced stepping at present. */
9198 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
9200 /* This should be low enough for everything. */
9201 tdep->lowest_pc = 0x20;
9202 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
9204 /* The default, for both APCS and AAPCS, is to return small
9205 structures in registers. */
9206 tdep->struct_return = reg_struct_return;
9208 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
9209 set_gdbarch_frame_align (gdbarch, arm_frame_align);
9211 set_gdbarch_write_pc (gdbarch, arm_write_pc);
9213 /* Frame handling. */
9214 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
9215 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
9216 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
9218 frame_base_set_default (gdbarch, &arm_normal_base);
9220 /* Address manipulation. */
9221 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
9223 /* Advance PC across function entry code. */
9224 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
9226 /* Detect whether PC is at a point where the stack has been destroyed. */
9227 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
9229 /* Skip trampolines. */
9230 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
9232 /* The stack grows downward. */
9233 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
9235 /* Breakpoint manipulation. */
9236 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
9237 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
9238 arm_remote_breakpoint_from_pc);
9240 /* Information about registers, etc. */
9241 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
9242 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
9243 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
9244 set_gdbarch_register_type (gdbarch, arm_register_type);
9245 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
9247 /* This "info float" is FPA-specific. Use the generic version if we
9249 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
9250 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
9252 /* Internal <-> external register number maps. */
9253 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
9254 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
9256 set_gdbarch_register_name (gdbarch, arm_register_name);
9258 /* Returning results. */
9259 set_gdbarch_return_value (gdbarch, arm_return_value);
9262 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
9264 /* Minsymbol frobbing. */
9265 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
9266 set_gdbarch_coff_make_msymbol_special (gdbarch,
9267 arm_coff_make_msymbol_special);
9268 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
9270 /* Thumb-2 IT block support. */
9271 set_gdbarch_adjust_breakpoint_address (gdbarch,
9272 arm_adjust_breakpoint_address);
9274 /* Virtual tables. */
9275 set_gdbarch_vbit_in_delta (gdbarch, 1);
9277 /* Hook in the ABI-specific overrides, if they have been registered. */
9278 gdbarch_init_osabi (info, gdbarch);
9280 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
9282 /* Add some default predicates. */
9284 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
9285 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
9286 dwarf2_append_unwinders (gdbarch);
9287 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
9288 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
9290 /* Now we have tuned the configuration, set a few final things,
9291 based on what the OS ABI has told us. */
9293 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9294 binaries are always marked. */
9295 if (tdep->arm_abi == ARM_ABI_AUTO)
9296 tdep->arm_abi = ARM_ABI_APCS;
9298 /* Watchpoints are not steppable. */
9299 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9301 /* We used to default to FPA for generic ARM, but almost nobody
9302 uses that now, and we now provide a way for the user to force
9303 the model. So default to the most useful variant. */
9304 if (tdep->fp_model == ARM_FLOAT_AUTO)
9305 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
9307 if (tdep->jb_pc >= 0)
9308 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
9310 /* Floating point sizes and format. */
9311 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
9312 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
9314 set_gdbarch_double_format
9315 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9316 set_gdbarch_long_double_format
9317 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9321 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
9322 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
9325 if (have_vfp_pseudos)
9327 /* NOTE: These are the only pseudo registers used by
9328 the ARM target at the moment. If more are added, a
9329 little more care in numbering will be needed. */
9331 int num_pseudos = 32;
9332 if (have_neon_pseudos)
9334 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
9335 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
9336 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
9341 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
9343 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
9345 /* Override tdesc_register_type to adjust the types of VFP
9346 registers for NEON. */
9347 set_gdbarch_register_type (gdbarch, arm_register_type);
9350 /* Add standard register aliases. We add aliases even for those
9351 nanes which are used by the current architecture - it's simpler,
9352 and does no harm, since nothing ever lists user registers. */
9353 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
9354 user_reg_add (gdbarch, arm_register_aliases[i].name,
9355 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
9361 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
9363 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9368 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9369 (unsigned long) tdep->lowest_pc);
9372 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
9375 _initialize_arm_tdep (void)
9377 struct ui_file *stb;
9379 const char *setname;
9380 const char *setdesc;
9381 const char *const *regnames;
9383 static char *helptext;
9384 char regdesc[1024], *rdptr = regdesc;
9385 size_t rest = sizeof (regdesc);
9387 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
9389 arm_objfile_data_key
9390 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
9392 /* Add ourselves to objfile event chain. */
9393 observer_attach_new_objfile (arm_exidx_new_objfile);
9395 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
9397 /* Register an ELF OS ABI sniffer for ARM binaries. */
9398 gdbarch_register_osabi_sniffer (bfd_arch_arm,
9399 bfd_target_elf_flavour,
9400 arm_elf_osabi_sniffer);
9402 /* Initialize the standard target descriptions. */
9403 initialize_tdesc_arm_with_m ();
9404 initialize_tdesc_arm_with_m_fpa_layout ();
9405 initialize_tdesc_arm_with_m_vfp_d16 ();
9406 initialize_tdesc_arm_with_iwmmxt ();
9407 initialize_tdesc_arm_with_vfpv2 ();
9408 initialize_tdesc_arm_with_vfpv3 ();
9409 initialize_tdesc_arm_with_neon ();
9411 /* Get the number of possible sets of register names defined in opcodes. */
9412 num_disassembly_options = get_arm_regname_num_options ();
9414 /* Add root prefix command for all "set arm"/"show arm" commands. */
9415 add_prefix_cmd ("arm", no_class, set_arm_command,
9416 _("Various ARM-specific commands."),
9417 &setarmcmdlist, "set arm ", 0, &setlist);
9419 add_prefix_cmd ("arm", no_class, show_arm_command,
9420 _("Various ARM-specific commands."),
9421 &showarmcmdlist, "show arm ", 0, &showlist);
9423 /* Sync the opcode insn printer with our register viewer. */
9424 parse_arm_disassembler_option ("reg-names-std");
9426 /* Initialize the array that will be passed to
9427 add_setshow_enum_cmd(). */
9428 valid_disassembly_styles = XNEWVEC (const char *,
9429 num_disassembly_options + 1);
9430 for (i = 0; i < num_disassembly_options; i++)
9432 get_arm_regnames (i, &setname, &setdesc, ®names);
9433 valid_disassembly_styles[i] = setname;
9434 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
9437 /* When we find the default names, tell the disassembler to use
9439 if (!strcmp (setname, "std"))
9441 disassembly_style = setname;
9442 set_arm_regname_option (i);
9445 /* Mark the end of valid options. */
9446 valid_disassembly_styles[num_disassembly_options] = NULL;
9448 /* Create the help text. */
9449 stb = mem_fileopen ();
9450 fprintf_unfiltered (stb, "%s%s%s",
9451 _("The valid values are:\n"),
9453 _("The default is \"std\"."));
9454 helptext = ui_file_xstrdup (stb, NULL);
9455 ui_file_delete (stb);
9457 add_setshow_enum_cmd("disassembler", no_class,
9458 valid_disassembly_styles, &disassembly_style,
9459 _("Set the disassembly style."),
9460 _("Show the disassembly style."),
9462 set_disassembly_style_sfunc,
9463 NULL, /* FIXME: i18n: The disassembly style is
9465 &setarmcmdlist, &showarmcmdlist);
9467 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
9468 _("Set usage of ARM 32-bit mode."),
9469 _("Show usage of ARM 32-bit mode."),
9470 _("When off, a 26-bit PC will be used."),
9472 NULL, /* FIXME: i18n: Usage of ARM 32-bit
9474 &setarmcmdlist, &showarmcmdlist);
9476 /* Add a command to allow the user to force the FPU model. */
9477 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
9478 _("Set the floating point type."),
9479 _("Show the floating point type."),
9480 _("auto - Determine the FP typefrom the OS-ABI.\n\
9481 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9482 fpa - FPA co-processor (GCC compiled).\n\
9483 softvfp - Software FP with pure-endian doubles.\n\
9484 vfp - VFP co-processor."),
9485 set_fp_model_sfunc, show_fp_model,
9486 &setarmcmdlist, &showarmcmdlist);
9488 /* Add a command to allow the user to force the ABI. */
9489 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
9492 NULL, arm_set_abi, arm_show_abi,
9493 &setarmcmdlist, &showarmcmdlist);
9495 /* Add two commands to allow the user to force the assumed
9497 add_setshow_enum_cmd ("fallback-mode", class_support,
9498 arm_mode_strings, &arm_fallback_mode_string,
9499 _("Set the mode assumed when symbols are unavailable."),
9500 _("Show the mode assumed when symbols are unavailable."),
9501 NULL, NULL, arm_show_fallback_mode,
9502 &setarmcmdlist, &showarmcmdlist);
9503 add_setshow_enum_cmd ("force-mode", class_support,
9504 arm_mode_strings, &arm_force_mode_string,
9505 _("Set the mode assumed even when symbols are available."),
9506 _("Show the mode assumed even when symbols are available."),
9507 NULL, NULL, arm_show_force_mode,
9508 &setarmcmdlist, &showarmcmdlist);
9510 /* Debugging flag. */
9511 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
9512 _("Set ARM debugging."),
9513 _("Show ARM debugging."),
9514 _("When on, arm-specific debugging is enabled."),
9516 NULL, /* FIXME: i18n: "ARM debugging is %s. */
9517 &setdebuglist, &showdebuglist);
9520 /* ARM-reversible process record data structures. */
9522 #define ARM_INSN_SIZE_BYTES 4
9523 #define THUMB_INSN_SIZE_BYTES 2
9524 #define THUMB2_INSN_SIZE_BYTES 4
9527 /* Position of the bit within a 32-bit ARM instruction
9528 that defines whether the instruction is a load or store. */
9529 #define INSN_S_L_BIT_NUM 20
9531 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9534 unsigned int reg_len = LENGTH; \
9537 REGS = XNEWVEC (uint32_t, reg_len); \
9538 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9543 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9546 unsigned int mem_len = LENGTH; \
9549 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9550 memcpy(&MEMS->len, &RECORD_BUF[0], \
9551 sizeof(struct arm_mem_r) * LENGTH); \
9556 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9557 #define INSN_RECORDED(ARM_RECORD) \
9558 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9560 /* ARM memory record structure. */
9563 uint32_t len; /* Record length. */
9564 uint32_t addr; /* Memory address. */
9567 /* ARM instruction record contains opcode of current insn
9568 and execution state (before entry to decode_insn()),
9569 contains list of to-be-modified registers and
9570 memory blocks (on return from decode_insn()). */
9572 typedef struct insn_decode_record_t
9574 struct gdbarch *gdbarch;
9575 struct regcache *regcache;
9576 CORE_ADDR this_addr; /* Address of the insn being decoded. */
9577 uint32_t arm_insn; /* Should accommodate thumb. */
9578 uint32_t cond; /* Condition code. */
9579 uint32_t opcode; /* Insn opcode. */
9580 uint32_t decode; /* Insn decode bits. */
9581 uint32_t mem_rec_count; /* No of mem records. */
9582 uint32_t reg_rec_count; /* No of reg records. */
9583 uint32_t *arm_regs; /* Registers to be saved for this record. */
9584 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
9585 } insn_decode_record;
9588 /* Checks ARM SBZ and SBO mandatory fields. */
9591 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
9593 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
9612 enum arm_record_result
9614 ARM_RECORD_SUCCESS = 0,
9615 ARM_RECORD_FAILURE = 1
9622 } arm_record_strx_t;
9633 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
9634 uint32_t *record_buf_mem, arm_record_strx_t str_type)
9637 struct regcache *reg_cache = arm_insn_r->regcache;
9638 ULONGEST u_regval[2]= {0};
9640 uint32_t reg_src1 = 0, reg_src2 = 0;
9641 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
9643 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
9644 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
9646 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
9648 /* 1) Handle misc store, immediate offset. */
9649 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9650 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9651 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9652 regcache_raw_read_unsigned (reg_cache, reg_src1,
9654 if (ARM_PC_REGNUM == reg_src1)
9656 /* If R15 was used as Rn, hence current PC+8. */
9657 u_regval[0] = u_regval[0] + 8;
9659 offset_8 = (immed_high << 4) | immed_low;
9660 /* Calculate target store address. */
9661 if (14 == arm_insn_r->opcode)
9663 tgt_mem_addr = u_regval[0] + offset_8;
9667 tgt_mem_addr = u_regval[0] - offset_8;
9669 if (ARM_RECORD_STRH == str_type)
9671 record_buf_mem[0] = 2;
9672 record_buf_mem[1] = tgt_mem_addr;
9673 arm_insn_r->mem_rec_count = 1;
9675 else if (ARM_RECORD_STRD == str_type)
9677 record_buf_mem[0] = 4;
9678 record_buf_mem[1] = tgt_mem_addr;
9679 record_buf_mem[2] = 4;
9680 record_buf_mem[3] = tgt_mem_addr + 4;
9681 arm_insn_r->mem_rec_count = 2;
9684 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
9686 /* 2) Store, register offset. */
9688 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9690 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9691 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9692 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9695 /* If R15 was used as Rn, hence current PC+8. */
9696 u_regval[0] = u_regval[0] + 8;
9698 /* Calculate target store address, Rn +/- Rm, register offset. */
9699 if (12 == arm_insn_r->opcode)
9701 tgt_mem_addr = u_regval[0] + u_regval[1];
9705 tgt_mem_addr = u_regval[1] - u_regval[0];
9707 if (ARM_RECORD_STRH == str_type)
9709 record_buf_mem[0] = 2;
9710 record_buf_mem[1] = tgt_mem_addr;
9711 arm_insn_r->mem_rec_count = 1;
9713 else if (ARM_RECORD_STRD == str_type)
9715 record_buf_mem[0] = 4;
9716 record_buf_mem[1] = tgt_mem_addr;
9717 record_buf_mem[2] = 4;
9718 record_buf_mem[3] = tgt_mem_addr + 4;
9719 arm_insn_r->mem_rec_count = 2;
9722 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
9723 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9725 /* 3) Store, immediate pre-indexed. */
9726 /* 5) Store, immediate post-indexed. */
9727 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9728 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9729 offset_8 = (immed_high << 4) | immed_low;
9730 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9731 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9732 /* Calculate target store address, Rn +/- Rm, register offset. */
9733 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9735 tgt_mem_addr = u_regval[0] + offset_8;
9739 tgt_mem_addr = u_regval[0] - offset_8;
9741 if (ARM_RECORD_STRH == str_type)
9743 record_buf_mem[0] = 2;
9744 record_buf_mem[1] = tgt_mem_addr;
9745 arm_insn_r->mem_rec_count = 1;
9747 else if (ARM_RECORD_STRD == str_type)
9749 record_buf_mem[0] = 4;
9750 record_buf_mem[1] = tgt_mem_addr;
9751 record_buf_mem[2] = 4;
9752 record_buf_mem[3] = tgt_mem_addr + 4;
9753 arm_insn_r->mem_rec_count = 2;
9755 /* Record Rn also as it changes. */
9756 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9757 arm_insn_r->reg_rec_count = 1;
9759 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
9760 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9762 /* 4) Store, register pre-indexed. */
9763 /* 6) Store, register post -indexed. */
9764 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9765 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9766 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9767 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9768 /* Calculate target store address, Rn +/- Rm, register offset. */
9769 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9771 tgt_mem_addr = u_regval[0] + u_regval[1];
9775 tgt_mem_addr = u_regval[1] - u_regval[0];
9777 if (ARM_RECORD_STRH == str_type)
9779 record_buf_mem[0] = 2;
9780 record_buf_mem[1] = tgt_mem_addr;
9781 arm_insn_r->mem_rec_count = 1;
9783 else if (ARM_RECORD_STRD == str_type)
9785 record_buf_mem[0] = 4;
9786 record_buf_mem[1] = tgt_mem_addr;
9787 record_buf_mem[2] = 4;
9788 record_buf_mem[3] = tgt_mem_addr + 4;
9789 arm_insn_r->mem_rec_count = 2;
9791 /* Record Rn also as it changes. */
9792 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9793 arm_insn_r->reg_rec_count = 1;
9798 /* Handling ARM extension space insns. */
9801 arm_record_extension_space (insn_decode_record *arm_insn_r)
9803 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
9804 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
9805 uint32_t record_buf[8], record_buf_mem[8];
9806 uint32_t reg_src1 = 0;
9807 struct regcache *reg_cache = arm_insn_r->regcache;
9808 ULONGEST u_regval = 0;
9810 gdb_assert (!INSN_RECORDED(arm_insn_r));
9811 /* Handle unconditional insn extension space. */
9813 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
9814 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
9815 if (arm_insn_r->cond)
9817 /* PLD has no affect on architectural state, it just affects
9819 if (5 == ((opcode1 & 0xE0) >> 5))
9822 record_buf[0] = ARM_PS_REGNUM;
9823 record_buf[1] = ARM_LR_REGNUM;
9824 arm_insn_r->reg_rec_count = 2;
9826 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9830 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
9831 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
9834 /* Undefined instruction on ARM V5; need to handle if later
9835 versions define it. */
9838 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
9839 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
9840 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
9842 /* Handle arithmetic insn extension space. */
9843 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
9844 && !INSN_RECORDED(arm_insn_r))
9846 /* Handle MLA(S) and MUL(S). */
9847 if (0 <= insn_op1 && 3 >= insn_op1)
9849 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9850 record_buf[1] = ARM_PS_REGNUM;
9851 arm_insn_r->reg_rec_count = 2;
9853 else if (4 <= insn_op1 && 15 >= insn_op1)
9855 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9856 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
9857 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
9858 record_buf[2] = ARM_PS_REGNUM;
9859 arm_insn_r->reg_rec_count = 3;
9863 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
9864 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
9865 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
9867 /* Handle control insn extension space. */
9869 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
9870 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
9872 if (!bit (arm_insn_r->arm_insn,25))
9874 if (!bits (arm_insn_r->arm_insn, 4, 7))
9876 if ((0 == insn_op1) || (2 == insn_op1))
9879 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9880 arm_insn_r->reg_rec_count = 1;
9882 else if (1 == insn_op1)
9884 /* CSPR is going to be changed. */
9885 record_buf[0] = ARM_PS_REGNUM;
9886 arm_insn_r->reg_rec_count = 1;
9888 else if (3 == insn_op1)
9890 /* SPSR is going to be changed. */
9891 /* We need to get SPSR value, which is yet to be done. */
9895 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
9900 record_buf[0] = ARM_PS_REGNUM;
9901 arm_insn_r->reg_rec_count = 1;
9903 else if (3 == insn_op1)
9906 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9907 arm_insn_r->reg_rec_count = 1;
9910 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
9913 record_buf[0] = ARM_PS_REGNUM;
9914 record_buf[1] = ARM_LR_REGNUM;
9915 arm_insn_r->reg_rec_count = 2;
9917 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
9919 /* QADD, QSUB, QDADD, QDSUB */
9920 record_buf[0] = ARM_PS_REGNUM;
9921 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
9922 arm_insn_r->reg_rec_count = 2;
9924 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
9927 record_buf[0] = ARM_PS_REGNUM;
9928 record_buf[1] = ARM_LR_REGNUM;
9929 arm_insn_r->reg_rec_count = 2;
9931 /* Save SPSR also;how? */
9934 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
9935 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
9936 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
9937 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
9940 if (0 == insn_op1 || 1 == insn_op1)
9942 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
9943 /* We dont do optimization for SMULW<y> where we
9945 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9946 record_buf[1] = ARM_PS_REGNUM;
9947 arm_insn_r->reg_rec_count = 2;
9949 else if (2 == insn_op1)
9952 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9953 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
9954 arm_insn_r->reg_rec_count = 2;
9956 else if (3 == insn_op1)
9959 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9960 arm_insn_r->reg_rec_count = 1;
9966 /* MSR : immediate form. */
9969 /* CSPR is going to be changed. */
9970 record_buf[0] = ARM_PS_REGNUM;
9971 arm_insn_r->reg_rec_count = 1;
9973 else if (3 == insn_op1)
9975 /* SPSR is going to be changed. */
9976 /* we need to get SPSR value, which is yet to be done */
9982 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
9983 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
9984 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
9986 /* Handle load/store insn extension space. */
9988 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
9989 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
9990 && !INSN_RECORDED(arm_insn_r))
9995 /* These insn, changes register and memory as well. */
9996 /* SWP or SWPB insn. */
9997 /* Get memory address given by Rn. */
9998 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9999 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
10000 /* SWP insn ?, swaps word. */
10001 if (8 == arm_insn_r->opcode)
10003 record_buf_mem[0] = 4;
10007 /* SWPB insn, swaps only byte. */
10008 record_buf_mem[0] = 1;
10010 record_buf_mem[1] = u_regval;
10011 arm_insn_r->mem_rec_count = 1;
10012 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10013 arm_insn_r->reg_rec_count = 1;
10015 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10018 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10021 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10024 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10025 record_buf[1] = record_buf[0] + 1;
10026 arm_insn_r->reg_rec_count = 2;
10028 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10031 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10034 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
10036 /* LDRH, LDRSB, LDRSH. */
10037 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10038 arm_insn_r->reg_rec_count = 1;
10043 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
10044 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
10045 && !INSN_RECORDED(arm_insn_r))
10048 /* Handle coprocessor insn extension space. */
10051 /* To be done for ARMv5 and later; as of now we return -1. */
10055 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10056 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10061 /* Handling opcode 000 insns. */
10064 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
10066 struct regcache *reg_cache = arm_insn_r->regcache;
10067 uint32_t record_buf[8], record_buf_mem[8];
10068 ULONGEST u_regval[2] = {0};
10070 uint32_t reg_src1 = 0, reg_dest = 0;
10071 uint32_t opcode1 = 0;
10073 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10074 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10075 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10077 /* Data processing insn /multiply insn. */
10078 if (9 == arm_insn_r->decode
10079 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10080 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
10082 /* Handle multiply instructions. */
10083 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10084 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
10086 /* Handle MLA and MUL. */
10087 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10088 record_buf[1] = ARM_PS_REGNUM;
10089 arm_insn_r->reg_rec_count = 2;
10091 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10093 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10094 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10095 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10096 record_buf[2] = ARM_PS_REGNUM;
10097 arm_insn_r->reg_rec_count = 3;
10100 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10101 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
10103 /* Handle misc load insns, as 20th bit (L = 1). */
10104 /* LDR insn has a capability to do branching, if
10105 MOV LR, PC is precceded by LDR insn having Rn as R15
10106 in that case, it emulates branch and link insn, and hence we
10107 need to save CSPR and PC as well. I am not sure this is right
10108 place; as opcode = 010 LDR insn make this happen, if R15 was
10110 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10111 if (15 != reg_dest)
10113 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10114 arm_insn_r->reg_rec_count = 1;
10118 record_buf[0] = reg_dest;
10119 record_buf[1] = ARM_PS_REGNUM;
10120 arm_insn_r->reg_rec_count = 2;
10123 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10124 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
10125 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10126 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
10128 /* Handle MSR insn. */
10129 if (9 == arm_insn_r->opcode)
10131 /* CSPR is going to be changed. */
10132 record_buf[0] = ARM_PS_REGNUM;
10133 arm_insn_r->reg_rec_count = 1;
10137 /* SPSR is going to be changed. */
10138 /* How to read SPSR value? */
10142 else if (9 == arm_insn_r->decode
10143 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10144 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10146 /* Handling SWP, SWPB. */
10147 /* These insn, changes register and memory as well. */
10148 /* SWP or SWPB insn. */
10150 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10151 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10152 /* SWP insn ?, swaps word. */
10153 if (8 == arm_insn_r->opcode)
10155 record_buf_mem[0] = 4;
10159 /* SWPB insn, swaps only byte. */
10160 record_buf_mem[0] = 1;
10162 record_buf_mem[1] = u_regval[0];
10163 arm_insn_r->mem_rec_count = 1;
10164 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10165 arm_insn_r->reg_rec_count = 1;
10167 else if (3 == arm_insn_r->decode && 0x12 == opcode1
10168 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10170 /* Handle BLX, branch and link/exchange. */
10171 if (9 == arm_insn_r->opcode)
10173 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10174 and R14 stores the return address. */
10175 record_buf[0] = ARM_PS_REGNUM;
10176 record_buf[1] = ARM_LR_REGNUM;
10177 arm_insn_r->reg_rec_count = 2;
10180 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
10182 /* Handle enhanced software breakpoint insn, BKPT. */
10183 /* CPSR is changed to be executed in ARM state, disabling normal
10184 interrupts, entering abort mode. */
10185 /* According to high vector configuration PC is set. */
10186 /* user hit breakpoint and type reverse, in
10187 that case, we need to go back with previous CPSR and
10188 Program Counter. */
10189 record_buf[0] = ARM_PS_REGNUM;
10190 record_buf[1] = ARM_LR_REGNUM;
10191 arm_insn_r->reg_rec_count = 2;
10193 /* Save SPSR also; how? */
10196 else if (11 == arm_insn_r->decode
10197 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10199 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10201 /* Handle str(x) insn */
10202 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10205 else if (1 == arm_insn_r->decode && 0x12 == opcode1
10206 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10208 /* Handle BX, branch and link/exchange. */
10209 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10210 record_buf[0] = ARM_PS_REGNUM;
10211 arm_insn_r->reg_rec_count = 1;
10213 else if (1 == arm_insn_r->decode && 0x16 == opcode1
10214 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
10215 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
10217 /* Count leading zeros: CLZ. */
10218 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10219 arm_insn_r->reg_rec_count = 1;
10221 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10222 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10223 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
10224 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
10227 /* Handle MRS insn. */
10228 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10229 arm_insn_r->reg_rec_count = 1;
10231 else if (arm_insn_r->opcode <= 15)
10233 /* Normal data processing insns. */
10234 /* Out of 11 shifter operands mode, all the insn modifies destination
10235 register, which is specified by 13-16 decode. */
10236 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10237 record_buf[1] = ARM_PS_REGNUM;
10238 arm_insn_r->reg_rec_count = 2;
10245 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10246 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10250 /* Handling opcode 001 insns. */
10253 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
10255 uint32_t record_buf[8], record_buf_mem[8];
10257 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10258 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10260 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10261 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
10262 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10265 /* Handle MSR insn. */
10266 if (9 == arm_insn_r->opcode)
10268 /* CSPR is going to be changed. */
10269 record_buf[0] = ARM_PS_REGNUM;
10270 arm_insn_r->reg_rec_count = 1;
10274 /* SPSR is going to be changed. */
10277 else if (arm_insn_r->opcode <= 15)
10279 /* Normal data processing insns. */
10280 /* Out of 11 shifter operands mode, all the insn modifies destination
10281 register, which is specified by 13-16 decode. */
10282 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10283 record_buf[1] = ARM_PS_REGNUM;
10284 arm_insn_r->reg_rec_count = 2;
10291 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10292 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10297 arm_record_media (insn_decode_record *arm_insn_r)
10299 uint32_t record_buf[8];
10301 switch (bits (arm_insn_r->arm_insn, 22, 24))
10304 /* Parallel addition and subtraction, signed */
10306 /* Parallel addition and subtraction, unsigned */
10309 /* Packing, unpacking, saturation and reversal */
10311 int rd = bits (arm_insn_r->arm_insn, 12, 15);
10313 record_buf[arm_insn_r->reg_rec_count++] = rd;
10319 /* Signed multiplies */
10321 int rd = bits (arm_insn_r->arm_insn, 16, 19);
10322 unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22);
10324 record_buf[arm_insn_r->reg_rec_count++] = rd;
10326 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10327 else if (op1 == 0x4)
10328 record_buf[arm_insn_r->reg_rec_count++]
10329 = bits (arm_insn_r->arm_insn, 12, 15);
10335 if (bit (arm_insn_r->arm_insn, 21)
10336 && bits (arm_insn_r->arm_insn, 5, 6) == 0x2)
10339 record_buf[arm_insn_r->reg_rec_count++]
10340 = bits (arm_insn_r->arm_insn, 12, 15);
10342 else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0
10343 && bits (arm_insn_r->arm_insn, 5, 7) == 0x0)
10345 /* USAD8 and USADA8 */
10346 record_buf[arm_insn_r->reg_rec_count++]
10347 = bits (arm_insn_r->arm_insn, 16, 19);
10354 if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3
10355 && bits (arm_insn_r->arm_insn, 5, 7) == 0x7)
10357 /* Permanently UNDEFINED */
10362 /* BFC, BFI and UBFX */
10363 record_buf[arm_insn_r->reg_rec_count++]
10364 = bits (arm_insn_r->arm_insn, 12, 15);
10373 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10378 /* Handle ARM mode instructions with opcode 010. */
10381 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
10383 struct regcache *reg_cache = arm_insn_r->regcache;
10385 uint32_t reg_base , reg_dest;
10386 uint32_t offset_12, tgt_mem_addr;
10387 uint32_t record_buf[8], record_buf_mem[8];
10388 unsigned char wback;
10391 /* Calculate wback. */
10392 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
10393 || (bit (arm_insn_r->arm_insn, 21) == 1);
10395 arm_insn_r->reg_rec_count = 0;
10396 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10398 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10400 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10403 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10404 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
10406 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10407 preceeds a LDR instruction having R15 as reg_base, it
10408 emulates a branch and link instruction, and hence we need to save
10409 CPSR and PC as well. */
10410 if (ARM_PC_REGNUM == reg_dest)
10411 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10413 /* If wback is true, also save the base register, which is going to be
10416 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10420 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10422 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
10423 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10425 /* Handle bit U. */
10426 if (bit (arm_insn_r->arm_insn, 23))
10428 /* U == 1: Add the offset. */
10429 tgt_mem_addr = (uint32_t) u_regval + offset_12;
10433 /* U == 0: subtract the offset. */
10434 tgt_mem_addr = (uint32_t) u_regval - offset_12;
10437 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10439 if (bit (arm_insn_r->arm_insn, 22))
10441 /* STRB and STRBT: 1 byte. */
10442 record_buf_mem[0] = 1;
10446 /* STR and STRT: 4 bytes. */
10447 record_buf_mem[0] = 4;
10450 /* Handle bit P. */
10451 if (bit (arm_insn_r->arm_insn, 24))
10452 record_buf_mem[1] = tgt_mem_addr;
10454 record_buf_mem[1] = (uint32_t) u_regval;
10456 arm_insn_r->mem_rec_count = 1;
10458 /* If wback is true, also save the base register, which is going to be
10461 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10464 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10465 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10469 /* Handling opcode 011 insns. */
10472 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
10474 struct regcache *reg_cache = arm_insn_r->regcache;
10476 uint32_t shift_imm = 0;
10477 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
10478 uint32_t offset_12 = 0, tgt_mem_addr = 0;
10479 uint32_t record_buf[8], record_buf_mem[8];
10482 ULONGEST u_regval[2];
10484 if (bit (arm_insn_r->arm_insn, 4))
10485 return arm_record_media (arm_insn_r);
10487 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10488 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10490 /* Handle enhanced store insns and LDRD DSP insn,
10491 order begins according to addressing modes for store insns
10495 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10497 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10498 /* LDR insn has a capability to do branching, if
10499 MOV LR, PC is precedded by LDR insn having Rn as R15
10500 in that case, it emulates branch and link insn, and hence we
10501 need to save CSPR and PC as well. */
10502 if (15 != reg_dest)
10504 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10505 arm_insn_r->reg_rec_count = 1;
10509 record_buf[0] = reg_dest;
10510 record_buf[1] = ARM_PS_REGNUM;
10511 arm_insn_r->reg_rec_count = 2;
10516 if (! bits (arm_insn_r->arm_insn, 4, 11))
10518 /* Store insn, register offset and register pre-indexed,
10519 register post-indexed. */
10521 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10523 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10524 regcache_raw_read_unsigned (reg_cache, reg_src1
10526 regcache_raw_read_unsigned (reg_cache, reg_src2
10528 if (15 == reg_src2)
10530 /* If R15 was used as Rn, hence current PC+8. */
10531 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10532 u_regval[0] = u_regval[0] + 8;
10534 /* Calculate target store address, Rn +/- Rm, register offset. */
10536 if (bit (arm_insn_r->arm_insn, 23))
10538 tgt_mem_addr = u_regval[0] + u_regval[1];
10542 tgt_mem_addr = u_regval[1] - u_regval[0];
10545 switch (arm_insn_r->opcode)
10559 record_buf_mem[0] = 4;
10574 record_buf_mem[0] = 1;
10578 gdb_assert_not_reached ("no decoding pattern found");
10581 record_buf_mem[1] = tgt_mem_addr;
10582 arm_insn_r->mem_rec_count = 1;
10584 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10585 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10586 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10587 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10588 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10589 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10592 /* Rn is going to be changed in pre-indexed mode and
10593 post-indexed mode as well. */
10594 record_buf[0] = reg_src2;
10595 arm_insn_r->reg_rec_count = 1;
10600 /* Store insn, scaled register offset; scaled pre-indexed. */
10601 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
10603 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10605 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10606 /* Get shift_imm. */
10607 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
10608 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10609 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
10610 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10611 /* Offset_12 used as shift. */
10615 /* Offset_12 used as index. */
10616 offset_12 = u_regval[0] << shift_imm;
10620 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
10626 if (bit (u_regval[0], 31))
10628 offset_12 = 0xFFFFFFFF;
10637 /* This is arithmetic shift. */
10638 offset_12 = s_word >> shift_imm;
10645 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
10647 /* Get C flag value and shift it by 31. */
10648 offset_12 = (((bit (u_regval[1], 29)) << 31) \
10649 | (u_regval[0]) >> 1);
10653 offset_12 = (u_regval[0] >> shift_imm) \
10655 (sizeof(uint32_t) - shift_imm));
10660 gdb_assert_not_reached ("no decoding pattern found");
10664 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10666 if (bit (arm_insn_r->arm_insn, 23))
10668 tgt_mem_addr = u_regval[1] + offset_12;
10672 tgt_mem_addr = u_regval[1] - offset_12;
10675 switch (arm_insn_r->opcode)
10689 record_buf_mem[0] = 4;
10704 record_buf_mem[0] = 1;
10708 gdb_assert_not_reached ("no decoding pattern found");
10711 record_buf_mem[1] = tgt_mem_addr;
10712 arm_insn_r->mem_rec_count = 1;
10714 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10715 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10716 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10717 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10718 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10719 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10722 /* Rn is going to be changed in register scaled pre-indexed
10723 mode,and scaled post indexed mode. */
10724 record_buf[0] = reg_src2;
10725 arm_insn_r->reg_rec_count = 1;
10730 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10731 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10735 /* Handle ARM mode instructions with opcode 100. */
10738 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
10740 struct regcache *reg_cache = arm_insn_r->regcache;
10741 uint32_t register_count = 0, register_bits;
10742 uint32_t reg_base, addr_mode;
10743 uint32_t record_buf[24], record_buf_mem[48];
10747 /* Fetch the list of registers. */
10748 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
10749 arm_insn_r->reg_rec_count = 0;
10751 /* Fetch the base register that contains the address we are loading data
10753 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10755 /* Calculate wback. */
10756 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
10758 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10760 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10762 /* Find out which registers are going to be loaded from memory. */
10763 while (register_bits)
10765 if (register_bits & 0x00000001)
10766 record_buf[arm_insn_r->reg_rec_count++] = register_count;
10767 register_bits = register_bits >> 1;
10772 /* If wback is true, also save the base register, which is going to be
10775 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10777 /* Save the CPSR register. */
10778 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10782 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10784 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
10786 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10788 /* Find out how many registers are going to be stored to memory. */
10789 while (register_bits)
10791 if (register_bits & 0x00000001)
10793 register_bits = register_bits >> 1;
10798 /* STMDA (STMED): Decrement after. */
10800 record_buf_mem[1] = (uint32_t) u_regval
10801 - register_count * INT_REGISTER_SIZE + 4;
10803 /* STM (STMIA, STMEA): Increment after. */
10805 record_buf_mem[1] = (uint32_t) u_regval;
10807 /* STMDB (STMFD): Decrement before. */
10809 record_buf_mem[1] = (uint32_t) u_regval
10810 - register_count * INT_REGISTER_SIZE;
10812 /* STMIB (STMFA): Increment before. */
10814 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
10817 gdb_assert_not_reached ("no decoding pattern found");
10821 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
10822 arm_insn_r->mem_rec_count = 1;
10824 /* If wback is true, also save the base register, which is going to be
10827 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10830 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10831 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10835 /* Handling opcode 101 insns. */
10838 arm_record_b_bl (insn_decode_record *arm_insn_r)
10840 uint32_t record_buf[8];
10842 /* Handle B, BL, BLX(1) insns. */
10843 /* B simply branches so we do nothing here. */
10844 /* Note: BLX(1) doesnt fall here but instead it falls into
10845 extension space. */
10846 if (bit (arm_insn_r->arm_insn, 24))
10848 record_buf[0] = ARM_LR_REGNUM;
10849 arm_insn_r->reg_rec_count = 1;
10852 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10858 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
10860 printf_unfiltered (_("Process record does not support instruction "
10861 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
10862 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
10867 /* Record handler for vector data transfer instructions. */
10870 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
10872 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
10873 uint32_t record_buf[4];
10875 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
10876 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
10877 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
10878 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
10879 bit_l = bit (arm_insn_r->arm_insn, 20);
10880 bit_c = bit (arm_insn_r->arm_insn, 8);
10882 /* Handle VMOV instruction. */
10883 if (bit_l && bit_c)
10885 record_buf[0] = reg_t;
10886 arm_insn_r->reg_rec_count = 1;
10888 else if (bit_l && !bit_c)
10890 /* Handle VMOV instruction. */
10891 if (bits_a == 0x00)
10893 record_buf[0] = reg_t;
10894 arm_insn_r->reg_rec_count = 1;
10896 /* Handle VMRS instruction. */
10897 else if (bits_a == 0x07)
10900 reg_t = ARM_PS_REGNUM;
10902 record_buf[0] = reg_t;
10903 arm_insn_r->reg_rec_count = 1;
10906 else if (!bit_l && !bit_c)
10908 /* Handle VMOV instruction. */
10909 if (bits_a == 0x00)
10911 record_buf[0] = ARM_D0_REGNUM + reg_v;
10913 arm_insn_r->reg_rec_count = 1;
10915 /* Handle VMSR instruction. */
10916 else if (bits_a == 0x07)
10918 record_buf[0] = ARM_FPSCR_REGNUM;
10919 arm_insn_r->reg_rec_count = 1;
10922 else if (!bit_l && bit_c)
10924 /* Handle VMOV instruction. */
10925 if (!(bits_a & 0x04))
10927 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
10929 arm_insn_r->reg_rec_count = 1;
10931 /* Handle VDUP instruction. */
10934 if (bit (arm_insn_r->arm_insn, 21))
10936 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
10937 record_buf[0] = reg_v + ARM_D0_REGNUM;
10938 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
10939 arm_insn_r->reg_rec_count = 2;
10943 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
10944 record_buf[0] = reg_v + ARM_D0_REGNUM;
10945 arm_insn_r->reg_rec_count = 1;
10950 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10954 /* Record handler for extension register load/store instructions. */
10957 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
10959 uint32_t opcode, single_reg;
10960 uint8_t op_vldm_vstm;
10961 uint32_t record_buf[8], record_buf_mem[128];
10962 ULONGEST u_regval = 0;
10964 struct regcache *reg_cache = arm_insn_r->regcache;
10965 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
10967 opcode = bits (arm_insn_r->arm_insn, 20, 24);
10968 single_reg = !bit (arm_insn_r->arm_insn, 8);
10969 op_vldm_vstm = opcode & 0x1b;
10971 /* Handle VMOV instructions. */
10972 if ((opcode & 0x1e) == 0x04)
10974 if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */
10976 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10977 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
10978 arm_insn_r->reg_rec_count = 2;
10982 uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3);
10983 uint8_t bit_m = bit (arm_insn_r->arm_insn, 5);
10987 /* The first S register number m is REG_M:M (M is bit 5),
10988 the corresponding D register number is REG_M:M / 2, which
10990 record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m;
10991 /* The second S register number is REG_M:M + 1, the
10992 corresponding D register number is (REG_M:M + 1) / 2.
10993 IOW, if bit M is 1, the first and second S registers
10994 are mapped to different D registers, otherwise, they are
10995 in the same D register. */
10998 record_buf[arm_insn_r->reg_rec_count++]
10999 = ARM_D0_REGNUM + reg_m + 1;
11004 record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM);
11005 arm_insn_r->reg_rec_count = 1;
11009 /* Handle VSTM and VPUSH instructions. */
11010 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
11011 || op_vldm_vstm == 0x12)
11013 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
11014 uint32_t memory_index = 0;
11016 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11017 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11018 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11019 imm_off32 = imm_off8 << 2;
11020 memory_count = imm_off8;
11022 if (bit (arm_insn_r->arm_insn, 23))
11023 start_address = u_regval;
11025 start_address = u_regval - imm_off32;
11027 if (bit (arm_insn_r->arm_insn, 21))
11029 record_buf[0] = reg_rn;
11030 arm_insn_r->reg_rec_count = 1;
11033 while (memory_count > 0)
11037 record_buf_mem[memory_index] = 4;
11038 record_buf_mem[memory_index + 1] = start_address;
11039 start_address = start_address + 4;
11040 memory_index = memory_index + 2;
11044 record_buf_mem[memory_index] = 4;
11045 record_buf_mem[memory_index + 1] = start_address;
11046 record_buf_mem[memory_index + 2] = 4;
11047 record_buf_mem[memory_index + 3] = start_address + 4;
11048 start_address = start_address + 8;
11049 memory_index = memory_index + 4;
11053 arm_insn_r->mem_rec_count = (memory_index >> 1);
11055 /* Handle VLDM instructions. */
11056 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
11057 || op_vldm_vstm == 0x13)
11059 uint32_t reg_count, reg_vd;
11060 uint32_t reg_index = 0;
11061 uint32_t bit_d = bit (arm_insn_r->arm_insn, 22);
11063 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11064 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
11066 /* REG_VD is the first D register number. If the instruction
11067 loads memory to S registers (SINGLE_REG is TRUE), the register
11068 number is (REG_VD << 1 | bit D), so the corresponding D
11069 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11071 reg_vd = reg_vd | (bit_d << 4);
11073 if (bit (arm_insn_r->arm_insn, 21) /* write back */)
11074 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
11076 /* If the instruction loads memory to D register, REG_COUNT should
11077 be divided by 2, according to the ARM Architecture Reference
11078 Manual. If the instruction loads memory to S register, divide by
11079 2 as well because two S registers are mapped to D register. */
11080 reg_count = reg_count / 2;
11081 if (single_reg && bit_d)
11083 /* Increase the register count if S register list starts from
11084 an odd number (bit d is one). */
11088 while (reg_count > 0)
11090 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
11093 arm_insn_r->reg_rec_count = reg_index;
11095 /* VSTR Vector store register. */
11096 else if ((opcode & 0x13) == 0x10)
11098 uint32_t start_address, reg_rn, imm_off32, imm_off8;
11099 uint32_t memory_index = 0;
11101 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11102 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11103 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11104 imm_off32 = imm_off8 << 2;
11106 if (bit (arm_insn_r->arm_insn, 23))
11107 start_address = u_regval + imm_off32;
11109 start_address = u_regval - imm_off32;
11113 record_buf_mem[memory_index] = 4;
11114 record_buf_mem[memory_index + 1] = start_address;
11115 arm_insn_r->mem_rec_count = 1;
11119 record_buf_mem[memory_index] = 4;
11120 record_buf_mem[memory_index + 1] = start_address;
11121 record_buf_mem[memory_index + 2] = 4;
11122 record_buf_mem[memory_index + 3] = start_address + 4;
11123 arm_insn_r->mem_rec_count = 2;
11126 /* VLDR Vector load register. */
11127 else if ((opcode & 0x13) == 0x11)
11129 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11133 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
11134 record_buf[0] = ARM_D0_REGNUM + reg_vd;
11138 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
11139 /* Record register D rather than pseudo register S. */
11140 record_buf[0] = ARM_D0_REGNUM + reg_vd / 2;
11142 arm_insn_r->reg_rec_count = 1;
11145 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11146 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11150 /* Record handler for arm/thumb mode VFP data processing instructions. */
11153 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
11155 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
11156 uint32_t record_buf[4];
11157 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
11158 enum insn_types curr_insn_type = INSN_INV;
11160 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11161 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
11162 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
11163 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
11164 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
11165 bit_d = bit (arm_insn_r->arm_insn, 22);
11166 opc1 = opc1 & 0x04;
11168 /* Handle VMLA, VMLS. */
11171 if (bit (arm_insn_r->arm_insn, 10))
11173 if (bit (arm_insn_r->arm_insn, 6))
11174 curr_insn_type = INSN_T0;
11176 curr_insn_type = INSN_T1;
11181 curr_insn_type = INSN_T1;
11183 curr_insn_type = INSN_T2;
11186 /* Handle VNMLA, VNMLS, VNMUL. */
11187 else if (opc1 == 0x01)
11190 curr_insn_type = INSN_T1;
11192 curr_insn_type = INSN_T2;
11195 else if (opc1 == 0x02 && !(opc3 & 0x01))
11197 if (bit (arm_insn_r->arm_insn, 10))
11199 if (bit (arm_insn_r->arm_insn, 6))
11200 curr_insn_type = INSN_T0;
11202 curr_insn_type = INSN_T1;
11207 curr_insn_type = INSN_T1;
11209 curr_insn_type = INSN_T2;
11212 /* Handle VADD, VSUB. */
11213 else if (opc1 == 0x03)
11215 if (!bit (arm_insn_r->arm_insn, 9))
11217 if (bit (arm_insn_r->arm_insn, 6))
11218 curr_insn_type = INSN_T0;
11220 curr_insn_type = INSN_T1;
11225 curr_insn_type = INSN_T1;
11227 curr_insn_type = INSN_T2;
11231 else if (opc1 == 0x0b)
11234 curr_insn_type = INSN_T1;
11236 curr_insn_type = INSN_T2;
11238 /* Handle all other vfp data processing instructions. */
11239 else if (opc1 == 0x0b)
11242 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
11244 if (bit (arm_insn_r->arm_insn, 4))
11246 if (bit (arm_insn_r->arm_insn, 6))
11247 curr_insn_type = INSN_T0;
11249 curr_insn_type = INSN_T1;
11254 curr_insn_type = INSN_T1;
11256 curr_insn_type = INSN_T2;
11259 /* Handle VNEG and VABS. */
11260 else if ((opc2 == 0x01 && opc3 == 0x01)
11261 || (opc2 == 0x00 && opc3 == 0x03))
11263 if (!bit (arm_insn_r->arm_insn, 11))
11265 if (bit (arm_insn_r->arm_insn, 6))
11266 curr_insn_type = INSN_T0;
11268 curr_insn_type = INSN_T1;
11273 curr_insn_type = INSN_T1;
11275 curr_insn_type = INSN_T2;
11278 /* Handle VSQRT. */
11279 else if (opc2 == 0x01 && opc3 == 0x03)
11282 curr_insn_type = INSN_T1;
11284 curr_insn_type = INSN_T2;
11287 else if (opc2 == 0x07 && opc3 == 0x03)
11290 curr_insn_type = INSN_T1;
11292 curr_insn_type = INSN_T2;
11294 else if (opc3 & 0x01)
11297 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
11299 if (!bit (arm_insn_r->arm_insn, 18))
11300 curr_insn_type = INSN_T2;
11304 curr_insn_type = INSN_T1;
11306 curr_insn_type = INSN_T2;
11310 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
11313 curr_insn_type = INSN_T1;
11315 curr_insn_type = INSN_T2;
11317 /* Handle VCVTB, VCVTT. */
11318 else if ((opc2 & 0x0e) == 0x02)
11319 curr_insn_type = INSN_T2;
11320 /* Handle VCMP, VCMPE. */
11321 else if ((opc2 & 0x0e) == 0x04)
11322 curr_insn_type = INSN_T3;
11326 switch (curr_insn_type)
11329 reg_vd = reg_vd | (bit_d << 4);
11330 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11331 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
11332 arm_insn_r->reg_rec_count = 2;
11336 reg_vd = reg_vd | (bit_d << 4);
11337 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11338 arm_insn_r->reg_rec_count = 1;
11342 reg_vd = (reg_vd << 1) | bit_d;
11343 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11344 arm_insn_r->reg_rec_count = 1;
11348 record_buf[0] = ARM_FPSCR_REGNUM;
11349 arm_insn_r->reg_rec_count = 1;
11353 gdb_assert_not_reached ("no decoding pattern found");
11357 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11361 /* Handling opcode 110 insns. */
11364 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
11366 uint32_t op1, op1_ebit, coproc;
11368 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11369 op1 = bits (arm_insn_r->arm_insn, 20, 25);
11370 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11372 if ((coproc & 0x0e) == 0x0a)
11374 /* Handle extension register ld/st instructions. */
11376 return arm_record_exreg_ld_st_insn (arm_insn_r);
11378 /* 64-bit transfers between arm core and extension registers. */
11379 if ((op1 & 0x3e) == 0x04)
11380 return arm_record_exreg_ld_st_insn (arm_insn_r);
11384 /* Handle coprocessor ld/st instructions. */
11389 return arm_record_unsupported_insn (arm_insn_r);
11392 return arm_record_unsupported_insn (arm_insn_r);
11395 /* Move to coprocessor from two arm core registers. */
11397 return arm_record_unsupported_insn (arm_insn_r);
11399 /* Move to two arm core registers from coprocessor. */
11404 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
11405 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
11406 arm_insn_r->reg_rec_count = 2;
11408 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
11412 return arm_record_unsupported_insn (arm_insn_r);
11415 /* Handling opcode 111 insns. */
11418 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11420 uint32_t op, op1_sbit, op1_ebit, coproc;
11421 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11422 struct regcache *reg_cache = arm_insn_r->regcache;
11424 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11425 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11426 op1_sbit = bit (arm_insn_r->arm_insn, 24);
11427 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11428 op = bit (arm_insn_r->arm_insn, 4);
11430 /* Handle arm SWI/SVC system call instructions. */
11433 if (tdep->arm_syscall_record != NULL)
11435 ULONGEST svc_operand, svc_number;
11437 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
11439 if (svc_operand) /* OABI. */
11440 svc_number = svc_operand - 0x900000;
11442 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
11444 return tdep->arm_syscall_record (reg_cache, svc_number);
11448 printf_unfiltered (_("no syscall record support\n"));
11453 if ((coproc & 0x0e) == 0x0a)
11455 /* VFP data-processing instructions. */
11456 if (!op1_sbit && !op)
11457 return arm_record_vfp_data_proc_insn (arm_insn_r);
11459 /* Advanced SIMD, VFP instructions. */
11460 if (!op1_sbit && op)
11461 return arm_record_vdata_transfer_insn (arm_insn_r);
11465 /* Coprocessor data operations. */
11466 if (!op1_sbit && !op)
11467 return arm_record_unsupported_insn (arm_insn_r);
11469 /* Move to Coprocessor from ARM core register. */
11470 if (!op1_sbit && !op1_ebit && op)
11471 return arm_record_unsupported_insn (arm_insn_r);
11473 /* Move to arm core register from coprocessor. */
11474 if (!op1_sbit && op1_ebit && op)
11476 uint32_t record_buf[1];
11478 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11479 if (record_buf[0] == 15)
11480 record_buf[0] = ARM_PS_REGNUM;
11482 arm_insn_r->reg_rec_count = 1;
11483 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
11489 return arm_record_unsupported_insn (arm_insn_r);
11492 /* Handling opcode 000 insns. */
11495 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11497 uint32_t record_buf[8];
11498 uint32_t reg_src1 = 0;
11500 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11502 record_buf[0] = ARM_PS_REGNUM;
11503 record_buf[1] = reg_src1;
11504 thumb_insn_r->reg_rec_count = 2;
11506 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11512 /* Handling opcode 001 insns. */
11515 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11517 uint32_t record_buf[8];
11518 uint32_t reg_src1 = 0;
11520 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11522 record_buf[0] = ARM_PS_REGNUM;
11523 record_buf[1] = reg_src1;
11524 thumb_insn_r->reg_rec_count = 2;
11526 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11531 /* Handling opcode 010 insns. */
11534 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
11536 struct regcache *reg_cache = thumb_insn_r->regcache;
11537 uint32_t record_buf[8], record_buf_mem[8];
11539 uint32_t reg_src1 = 0, reg_src2 = 0;
11540 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
11542 ULONGEST u_regval[2] = {0};
11544 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
11546 if (bit (thumb_insn_r->arm_insn, 12))
11548 /* Handle load/store register offset. */
11549 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
11550 if (opcode2 >= 12 && opcode2 <= 15)
11552 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11553 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
11554 record_buf[0] = reg_src1;
11555 thumb_insn_r->reg_rec_count = 1;
11557 else if (opcode2 >= 8 && opcode2 <= 10)
11559 /* STR(2), STRB(2), STRH(2) . */
11560 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11561 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
11562 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11563 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11565 record_buf_mem[0] = 4; /* STR (2). */
11566 else if (10 == opcode2)
11567 record_buf_mem[0] = 1; /* STRB (2). */
11568 else if (9 == opcode2)
11569 record_buf_mem[0] = 2; /* STRH (2). */
11570 record_buf_mem[1] = u_regval[0] + u_regval[1];
11571 thumb_insn_r->mem_rec_count = 1;
11574 else if (bit (thumb_insn_r->arm_insn, 11))
11576 /* Handle load from literal pool. */
11578 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11579 record_buf[0] = reg_src1;
11580 thumb_insn_r->reg_rec_count = 1;
11584 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
11585 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
11586 if ((3 == opcode2) && (!opcode3))
11588 /* Branch with exchange. */
11589 record_buf[0] = ARM_PS_REGNUM;
11590 thumb_insn_r->reg_rec_count = 1;
11594 /* Format 8; special data processing insns. */
11595 record_buf[0] = ARM_PS_REGNUM;
11596 record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3
11597 | bits (thumb_insn_r->arm_insn, 0, 2));
11598 thumb_insn_r->reg_rec_count = 2;
11603 /* Format 5; data processing insns. */
11604 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11605 if (bit (thumb_insn_r->arm_insn, 7))
11607 reg_src1 = reg_src1 + 8;
11609 record_buf[0] = ARM_PS_REGNUM;
11610 record_buf[1] = reg_src1;
11611 thumb_insn_r->reg_rec_count = 2;
11614 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11615 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11621 /* Handling opcode 001 insns. */
11624 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
11626 struct regcache *reg_cache = thumb_insn_r->regcache;
11627 uint32_t record_buf[8], record_buf_mem[8];
11629 uint32_t reg_src1 = 0;
11630 uint32_t opcode = 0, immed_5 = 0;
11632 ULONGEST u_regval = 0;
11634 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11639 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11640 record_buf[0] = reg_src1;
11641 thumb_insn_r->reg_rec_count = 1;
11646 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11647 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11648 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11649 record_buf_mem[0] = 4;
11650 record_buf_mem[1] = u_regval + (immed_5 * 4);
11651 thumb_insn_r->mem_rec_count = 1;
11654 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11655 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11661 /* Handling opcode 100 insns. */
11664 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
11666 struct regcache *reg_cache = thumb_insn_r->regcache;
11667 uint32_t record_buf[8], record_buf_mem[8];
11669 uint32_t reg_src1 = 0;
11670 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
11672 ULONGEST u_regval = 0;
11674 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11679 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11680 record_buf[0] = reg_src1;
11681 thumb_insn_r->reg_rec_count = 1;
11683 else if (1 == opcode)
11686 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11687 record_buf[0] = reg_src1;
11688 thumb_insn_r->reg_rec_count = 1;
11690 else if (2 == opcode)
11693 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
11694 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11695 record_buf_mem[0] = 4;
11696 record_buf_mem[1] = u_regval + (immed_8 * 4);
11697 thumb_insn_r->mem_rec_count = 1;
11699 else if (0 == opcode)
11702 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11703 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11704 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11705 record_buf_mem[0] = 2;
11706 record_buf_mem[1] = u_regval + (immed_5 * 2);
11707 thumb_insn_r->mem_rec_count = 1;
11710 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11711 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11717 /* Handling opcode 101 insns. */
11720 thumb_record_misc (insn_decode_record *thumb_insn_r)
11722 struct regcache *reg_cache = thumb_insn_r->regcache;
11724 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
11725 uint32_t register_bits = 0, register_count = 0;
11726 uint32_t index = 0, start_address = 0;
11727 uint32_t record_buf[24], record_buf_mem[48];
11730 ULONGEST u_regval = 0;
11732 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11733 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
11734 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
11739 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11740 while (register_bits)
11742 if (register_bits & 0x00000001)
11743 record_buf[index++] = register_count;
11744 register_bits = register_bits >> 1;
11747 record_buf[index++] = ARM_PS_REGNUM;
11748 record_buf[index++] = ARM_SP_REGNUM;
11749 thumb_insn_r->reg_rec_count = index;
11751 else if (10 == opcode2)
11754 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11755 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11756 while (register_bits)
11758 if (register_bits & 0x00000001)
11760 register_bits = register_bits >> 1;
11762 start_address = u_regval - \
11763 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
11764 thumb_insn_r->mem_rec_count = register_count;
11765 while (register_count)
11767 record_buf_mem[(register_count * 2) - 1] = start_address;
11768 record_buf_mem[(register_count * 2) - 2] = 4;
11769 start_address = start_address + 4;
11772 record_buf[0] = ARM_SP_REGNUM;
11773 thumb_insn_r->reg_rec_count = 1;
11775 else if (0x1E == opcode1)
11778 /* Handle enhanced software breakpoint insn, BKPT. */
11779 /* CPSR is changed to be executed in ARM state, disabling normal
11780 interrupts, entering abort mode. */
11781 /* According to high vector configuration PC is set. */
11782 /* User hits breakpoint and type reverse, in that case, we need to go back with
11783 previous CPSR and Program Counter. */
11784 record_buf[0] = ARM_PS_REGNUM;
11785 record_buf[1] = ARM_LR_REGNUM;
11786 thumb_insn_r->reg_rec_count = 2;
11787 /* We need to save SPSR value, which is not yet done. */
11788 printf_unfiltered (_("Process record does not support instruction "
11789 "0x%0x at address %s.\n"),
11790 thumb_insn_r->arm_insn,
11791 paddress (thumb_insn_r->gdbarch,
11792 thumb_insn_r->this_addr));
11795 else if ((0 == opcode) || (1 == opcode))
11797 /* ADD(5), ADD(6). */
11798 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11799 record_buf[0] = reg_src1;
11800 thumb_insn_r->reg_rec_count = 1;
11802 else if (2 == opcode)
11804 /* ADD(7), SUB(4). */
11805 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11806 record_buf[0] = ARM_SP_REGNUM;
11807 thumb_insn_r->reg_rec_count = 1;
11810 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11811 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11817 /* Handling opcode 110 insns. */
11820 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
11822 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
11823 struct regcache *reg_cache = thumb_insn_r->regcache;
11825 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
11826 uint32_t reg_src1 = 0;
11827 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
11828 uint32_t index = 0, start_address = 0;
11829 uint32_t record_buf[24], record_buf_mem[48];
11831 ULONGEST u_regval = 0;
11833 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
11834 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
11840 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11842 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11843 while (register_bits)
11845 if (register_bits & 0x00000001)
11846 record_buf[index++] = register_count;
11847 register_bits = register_bits >> 1;
11850 record_buf[index++] = reg_src1;
11851 thumb_insn_r->reg_rec_count = index;
11853 else if (0 == opcode2)
11855 /* It handles both STMIA. */
11856 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11858 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11859 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11860 while (register_bits)
11862 if (register_bits & 0x00000001)
11864 register_bits = register_bits >> 1;
11866 start_address = u_regval;
11867 thumb_insn_r->mem_rec_count = register_count;
11868 while (register_count)
11870 record_buf_mem[(register_count * 2) - 1] = start_address;
11871 record_buf_mem[(register_count * 2) - 2] = 4;
11872 start_address = start_address + 4;
11876 else if (0x1F == opcode1)
11878 /* Handle arm syscall insn. */
11879 if (tdep->arm_syscall_record != NULL)
11881 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
11882 ret = tdep->arm_syscall_record (reg_cache, u_regval);
11886 printf_unfiltered (_("no syscall record support\n"));
11891 /* B (1), conditional branch is automatically taken care in process_record,
11892 as PC is saved there. */
11894 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11895 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11901 /* Handling opcode 111 insns. */
11904 thumb_record_branch (insn_decode_record *thumb_insn_r)
11906 uint32_t record_buf[8];
11907 uint32_t bits_h = 0;
11909 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
11911 if (2 == bits_h || 3 == bits_h)
11914 record_buf[0] = ARM_LR_REGNUM;
11915 thumb_insn_r->reg_rec_count = 1;
11917 else if (1 == bits_h)
11920 record_buf[0] = ARM_PS_REGNUM;
11921 record_buf[1] = ARM_LR_REGNUM;
11922 thumb_insn_r->reg_rec_count = 2;
11925 /* B(2) is automatically taken care in process_record, as PC is
11928 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11933 /* Handler for thumb2 load/store multiple instructions. */
11936 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
11938 struct regcache *reg_cache = thumb2_insn_r->regcache;
11940 uint32_t reg_rn, op;
11941 uint32_t register_bits = 0, register_count = 0;
11942 uint32_t index = 0, start_address = 0;
11943 uint32_t record_buf[24], record_buf_mem[48];
11945 ULONGEST u_regval = 0;
11947 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
11948 op = bits (thumb2_insn_r->arm_insn, 23, 24);
11950 if (0 == op || 3 == op)
11952 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11954 /* Handle RFE instruction. */
11955 record_buf[0] = ARM_PS_REGNUM;
11956 thumb2_insn_r->reg_rec_count = 1;
11960 /* Handle SRS instruction after reading banked SP. */
11961 return arm_record_unsupported_insn (thumb2_insn_r);
11964 else if (1 == op || 2 == op)
11966 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11968 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
11969 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
11970 while (register_bits)
11972 if (register_bits & 0x00000001)
11973 record_buf[index++] = register_count;
11976 register_bits = register_bits >> 1;
11978 record_buf[index++] = reg_rn;
11979 record_buf[index++] = ARM_PS_REGNUM;
11980 thumb2_insn_r->reg_rec_count = index;
11984 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
11985 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
11986 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11987 while (register_bits)
11989 if (register_bits & 0x00000001)
11992 register_bits = register_bits >> 1;
11997 /* Start address calculation for LDMDB/LDMEA. */
11998 start_address = u_regval;
12002 /* Start address calculation for LDMDB/LDMEA. */
12003 start_address = u_regval - register_count * 4;
12006 thumb2_insn_r->mem_rec_count = register_count;
12007 while (register_count)
12009 record_buf_mem[register_count * 2 - 1] = start_address;
12010 record_buf_mem[register_count * 2 - 2] = 4;
12011 start_address = start_address + 4;
12014 record_buf[0] = reg_rn;
12015 record_buf[1] = ARM_PS_REGNUM;
12016 thumb2_insn_r->reg_rec_count = 2;
12020 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12022 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12024 return ARM_RECORD_SUCCESS;
12027 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12031 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
12033 struct regcache *reg_cache = thumb2_insn_r->regcache;
12035 uint32_t reg_rd, reg_rn, offset_imm;
12036 uint32_t reg_dest1, reg_dest2;
12037 uint32_t address, offset_addr;
12038 uint32_t record_buf[8], record_buf_mem[8];
12039 uint32_t op1, op2, op3;
12041 ULONGEST u_regval[2];
12043 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
12044 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
12045 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
12047 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12049 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
12051 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
12052 record_buf[0] = reg_dest1;
12053 record_buf[1] = ARM_PS_REGNUM;
12054 thumb2_insn_r->reg_rec_count = 2;
12057 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
12059 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12060 record_buf[2] = reg_dest2;
12061 thumb2_insn_r->reg_rec_count = 3;
12066 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12067 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12069 if (0 == op1 && 0 == op2)
12071 /* Handle STREX. */
12072 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12073 address = u_regval[0] + (offset_imm * 4);
12074 record_buf_mem[0] = 4;
12075 record_buf_mem[1] = address;
12076 thumb2_insn_r->mem_rec_count = 1;
12077 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12078 record_buf[0] = reg_rd;
12079 thumb2_insn_r->reg_rec_count = 1;
12081 else if (1 == op1 && 0 == op2)
12083 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12084 record_buf[0] = reg_rd;
12085 thumb2_insn_r->reg_rec_count = 1;
12086 address = u_regval[0];
12087 record_buf_mem[1] = address;
12091 /* Handle STREXB. */
12092 record_buf_mem[0] = 1;
12093 thumb2_insn_r->mem_rec_count = 1;
12097 /* Handle STREXH. */
12098 record_buf_mem[0] = 2 ;
12099 thumb2_insn_r->mem_rec_count = 1;
12103 /* Handle STREXD. */
12104 address = u_regval[0];
12105 record_buf_mem[0] = 4;
12106 record_buf_mem[2] = 4;
12107 record_buf_mem[3] = address + 4;
12108 thumb2_insn_r->mem_rec_count = 2;
12113 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12115 if (bit (thumb2_insn_r->arm_insn, 24))
12117 if (bit (thumb2_insn_r->arm_insn, 23))
12118 offset_addr = u_regval[0] + (offset_imm * 4);
12120 offset_addr = u_regval[0] - (offset_imm * 4);
12122 address = offset_addr;
12125 address = u_regval[0];
12127 record_buf_mem[0] = 4;
12128 record_buf_mem[1] = address;
12129 record_buf_mem[2] = 4;
12130 record_buf_mem[3] = address + 4;
12131 thumb2_insn_r->mem_rec_count = 2;
12132 record_buf[0] = reg_rn;
12133 thumb2_insn_r->reg_rec_count = 1;
12137 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12139 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12141 return ARM_RECORD_SUCCESS;
12144 /* Handler for thumb2 data processing (shift register and modified immediate)
12148 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
12150 uint32_t reg_rd, op;
12151 uint32_t record_buf[8];
12153 op = bits (thumb2_insn_r->arm_insn, 21, 24);
12154 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12156 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
12158 record_buf[0] = ARM_PS_REGNUM;
12159 thumb2_insn_r->reg_rec_count = 1;
12163 record_buf[0] = reg_rd;
12164 record_buf[1] = ARM_PS_REGNUM;
12165 thumb2_insn_r->reg_rec_count = 2;
12168 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12170 return ARM_RECORD_SUCCESS;
12173 /* Generic handler for thumb2 instructions which effect destination and PS
12177 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
12180 uint32_t record_buf[8];
12182 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12184 record_buf[0] = reg_rd;
12185 record_buf[1] = ARM_PS_REGNUM;
12186 thumb2_insn_r->reg_rec_count = 2;
12188 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12190 return ARM_RECORD_SUCCESS;
12193 /* Handler for thumb2 branch and miscellaneous control instructions. */
12196 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
12198 uint32_t op, op1, op2;
12199 uint32_t record_buf[8];
12201 op = bits (thumb2_insn_r->arm_insn, 20, 26);
12202 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
12203 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12205 /* Handle MSR insn. */
12206 if (!(op1 & 0x2) && 0x38 == op)
12210 /* CPSR is going to be changed. */
12211 record_buf[0] = ARM_PS_REGNUM;
12212 thumb2_insn_r->reg_rec_count = 1;
12216 arm_record_unsupported_insn(thumb2_insn_r);
12220 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
12223 record_buf[0] = ARM_PS_REGNUM;
12224 record_buf[1] = ARM_LR_REGNUM;
12225 thumb2_insn_r->reg_rec_count = 2;
12228 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12230 return ARM_RECORD_SUCCESS;
12233 /* Handler for thumb2 store single data item instructions. */
12236 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
12238 struct regcache *reg_cache = thumb2_insn_r->regcache;
12240 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
12241 uint32_t address, offset_addr;
12242 uint32_t record_buf[8], record_buf_mem[8];
12245 ULONGEST u_regval[2];
12247 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
12248 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
12249 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12250 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12252 if (bit (thumb2_insn_r->arm_insn, 23))
12255 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
12256 offset_addr = u_regval[0] + offset_imm;
12257 address = offset_addr;
12262 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
12264 /* Handle STRB (register). */
12265 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
12266 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
12267 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
12268 offset_addr = u_regval[1] << shift_imm;
12269 address = u_regval[0] + offset_addr;
12273 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12274 if (bit (thumb2_insn_r->arm_insn, 10))
12276 if (bit (thumb2_insn_r->arm_insn, 9))
12277 offset_addr = u_regval[0] + offset_imm;
12279 offset_addr = u_regval[0] - offset_imm;
12281 address = offset_addr;
12284 address = u_regval[0];
12290 /* Store byte instructions. */
12293 record_buf_mem[0] = 1;
12295 /* Store half word instructions. */
12298 record_buf_mem[0] = 2;
12300 /* Store word instructions. */
12303 record_buf_mem[0] = 4;
12307 gdb_assert_not_reached ("no decoding pattern found");
12311 record_buf_mem[1] = address;
12312 thumb2_insn_r->mem_rec_count = 1;
12313 record_buf[0] = reg_rn;
12314 thumb2_insn_r->reg_rec_count = 1;
12316 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12318 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12320 return ARM_RECORD_SUCCESS;
12323 /* Handler for thumb2 load memory hints instructions. */
12326 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
12328 uint32_t record_buf[8];
12329 uint32_t reg_rt, reg_rn;
12331 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
12332 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12334 if (ARM_PC_REGNUM != reg_rt)
12336 record_buf[0] = reg_rt;
12337 record_buf[1] = reg_rn;
12338 record_buf[2] = ARM_PS_REGNUM;
12339 thumb2_insn_r->reg_rec_count = 3;
12341 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12343 return ARM_RECORD_SUCCESS;
12346 return ARM_RECORD_FAILURE;
12349 /* Handler for thumb2 load word instructions. */
12352 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
12354 uint32_t record_buf[8];
12356 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
12357 record_buf[1] = ARM_PS_REGNUM;
12358 thumb2_insn_r->reg_rec_count = 2;
12360 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12362 return ARM_RECORD_SUCCESS;
12365 /* Handler for thumb2 long multiply, long multiply accumulate, and
12366 divide instructions. */
12369 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
12371 uint32_t opcode1 = 0, opcode2 = 0;
12372 uint32_t record_buf[8];
12374 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
12375 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
12377 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
12379 /* Handle SMULL, UMULL, SMULAL. */
12380 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12381 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12382 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12383 record_buf[2] = ARM_PS_REGNUM;
12384 thumb2_insn_r->reg_rec_count = 3;
12386 else if (1 == opcode1 || 3 == opcode2)
12388 /* Handle SDIV and UDIV. */
12389 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12390 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12391 record_buf[2] = ARM_PS_REGNUM;
12392 thumb2_insn_r->reg_rec_count = 3;
12395 return ARM_RECORD_FAILURE;
12397 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12399 return ARM_RECORD_SUCCESS;
12402 /* Record handler for thumb32 coprocessor instructions. */
12405 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
12407 if (bit (thumb2_insn_r->arm_insn, 25))
12408 return arm_record_coproc_data_proc (thumb2_insn_r);
12410 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
12413 /* Record handler for advance SIMD structure load/store instructions. */
12416 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
12418 struct regcache *reg_cache = thumb2_insn_r->regcache;
12419 uint32_t l_bit, a_bit, b_bits;
12420 uint32_t record_buf[128], record_buf_mem[128];
12421 uint32_t reg_rn, reg_vd, address, f_elem;
12422 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
12425 l_bit = bit (thumb2_insn_r->arm_insn, 21);
12426 a_bit = bit (thumb2_insn_r->arm_insn, 23);
12427 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
12428 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12429 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
12430 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
12431 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
12432 f_elem = 8 / f_ebytes;
12436 ULONGEST u_regval = 0;
12437 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12438 address = u_regval;
12443 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12445 if (b_bits == 0x07)
12447 else if (b_bits == 0x0a)
12449 else if (b_bits == 0x06)
12451 else if (b_bits == 0x02)
12456 for (index_r = 0; index_r < bf_regs; index_r++)
12458 for (index_e = 0; index_e < f_elem; index_e++)
12460 record_buf_mem[index_m++] = f_ebytes;
12461 record_buf_mem[index_m++] = address;
12462 address = address + f_ebytes;
12463 thumb2_insn_r->mem_rec_count += 1;
12468 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12470 if (b_bits == 0x09 || b_bits == 0x08)
12472 else if (b_bits == 0x03)
12477 for (index_r = 0; index_r < bf_regs; index_r++)
12478 for (index_e = 0; index_e < f_elem; index_e++)
12480 for (loop_t = 0; loop_t < 2; loop_t++)
12482 record_buf_mem[index_m++] = f_ebytes;
12483 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12484 thumb2_insn_r->mem_rec_count += 1;
12486 address = address + (2 * f_ebytes);
12490 else if ((b_bits & 0x0e) == 0x04)
12492 for (index_e = 0; index_e < f_elem; index_e++)
12494 for (loop_t = 0; loop_t < 3; loop_t++)
12496 record_buf_mem[index_m++] = f_ebytes;
12497 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12498 thumb2_insn_r->mem_rec_count += 1;
12500 address = address + (3 * f_ebytes);
12504 else if (!(b_bits & 0x0e))
12506 for (index_e = 0; index_e < f_elem; index_e++)
12508 for (loop_t = 0; loop_t < 4; loop_t++)
12510 record_buf_mem[index_m++] = f_ebytes;
12511 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12512 thumb2_insn_r->mem_rec_count += 1;
12514 address = address + (4 * f_ebytes);
12520 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
12522 if (bft_size == 0x00)
12524 else if (bft_size == 0x01)
12526 else if (bft_size == 0x02)
12532 if (!(b_bits & 0x0b) || b_bits == 0x08)
12533 thumb2_insn_r->mem_rec_count = 1;
12535 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
12536 thumb2_insn_r->mem_rec_count = 2;
12538 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
12539 thumb2_insn_r->mem_rec_count = 3;
12541 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
12542 thumb2_insn_r->mem_rec_count = 4;
12544 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
12546 record_buf_mem[index_m] = f_ebytes;
12547 record_buf_mem[index_m] = address + (index_m * f_ebytes);
12556 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12557 thumb2_insn_r->reg_rec_count = 1;
12559 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12560 thumb2_insn_r->reg_rec_count = 2;
12562 else if ((b_bits & 0x0e) == 0x04)
12563 thumb2_insn_r->reg_rec_count = 3;
12565 else if (!(b_bits & 0x0e))
12566 thumb2_insn_r->reg_rec_count = 4;
12571 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
12572 thumb2_insn_r->reg_rec_count = 1;
12574 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
12575 thumb2_insn_r->reg_rec_count = 2;
12577 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
12578 thumb2_insn_r->reg_rec_count = 3;
12580 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
12581 thumb2_insn_r->reg_rec_count = 4;
12583 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
12584 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
12588 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
12590 record_buf[index_r] = reg_rn;
12591 thumb2_insn_r->reg_rec_count += 1;
12594 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12596 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12601 /* Decodes thumb2 instruction type and invokes its record handler. */
12603 static unsigned int
12604 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
12606 uint32_t op, op1, op2;
12608 op = bit (thumb2_insn_r->arm_insn, 15);
12609 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
12610 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
12614 if (!(op2 & 0x64 ))
12616 /* Load/store multiple instruction. */
12617 return thumb2_record_ld_st_multiple (thumb2_insn_r);
12619 else if (!((op2 & 0x64) ^ 0x04))
12621 /* Load/store (dual/exclusive) and table branch instruction. */
12622 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
12624 else if (!((op2 & 0x20) ^ 0x20))
12626 /* Data-processing (shifted register). */
12627 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12629 else if (op2 & 0x40)
12631 /* Co-processor instructions. */
12632 return thumb2_record_coproc_insn (thumb2_insn_r);
12635 else if (op1 == 0x02)
12639 /* Branches and miscellaneous control instructions. */
12640 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
12642 else if (op2 & 0x20)
12644 /* Data-processing (plain binary immediate) instruction. */
12645 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12649 /* Data-processing (modified immediate). */
12650 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12653 else if (op1 == 0x03)
12655 if (!(op2 & 0x71 ))
12657 /* Store single data item. */
12658 return thumb2_record_str_single_data (thumb2_insn_r);
12660 else if (!((op2 & 0x71) ^ 0x10))
12662 /* Advanced SIMD or structure load/store instructions. */
12663 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
12665 else if (!((op2 & 0x67) ^ 0x01))
12667 /* Load byte, memory hints instruction. */
12668 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12670 else if (!((op2 & 0x67) ^ 0x03))
12672 /* Load halfword, memory hints instruction. */
12673 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12675 else if (!((op2 & 0x67) ^ 0x05))
12677 /* Load word instruction. */
12678 return thumb2_record_ld_word (thumb2_insn_r);
12680 else if (!((op2 & 0x70) ^ 0x20))
12682 /* Data-processing (register) instruction. */
12683 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12685 else if (!((op2 & 0x78) ^ 0x30))
12687 /* Multiply, multiply accumulate, abs diff instruction. */
12688 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12690 else if (!((op2 & 0x78) ^ 0x38))
12692 /* Long multiply, long multiply accumulate, and divide. */
12693 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
12695 else if (op2 & 0x40)
12697 /* Co-processor instructions. */
12698 return thumb2_record_coproc_insn (thumb2_insn_r);
12705 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12706 and positive val on fauilure. */
12709 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12711 gdb_byte buf[insn_size];
12713 memset (&buf[0], 0, insn_size);
12715 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12717 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12719 gdbarch_byte_order_for_code (insn_record->gdbarch));
12723 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12725 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12729 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12730 uint32_t insn_size)
12733 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12735 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
12737 arm_record_data_proc_misc_ld_str, /* 000. */
12738 arm_record_data_proc_imm, /* 001. */
12739 arm_record_ld_st_imm_offset, /* 010. */
12740 arm_record_ld_st_reg_offset, /* 011. */
12741 arm_record_ld_st_multiple, /* 100. */
12742 arm_record_b_bl, /* 101. */
12743 arm_record_asimd_vfp_coproc, /* 110. */
12744 arm_record_coproc_data_proc /* 111. */
12747 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12749 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
12751 thumb_record_shift_add_sub, /* 000. */
12752 thumb_record_add_sub_cmp_mov, /* 001. */
12753 thumb_record_ld_st_reg_offset, /* 010. */
12754 thumb_record_ld_st_imm_offset, /* 011. */
12755 thumb_record_ld_st_stack, /* 100. */
12756 thumb_record_misc, /* 101. */
12757 thumb_record_ldm_stm_swi, /* 110. */
12758 thumb_record_branch /* 111. */
12761 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12762 uint32_t insn_id = 0;
12764 if (extract_arm_insn (arm_record, insn_size))
12768 printf_unfiltered (_("Process record: error reading memory at "
12769 "addr %s len = %d.\n"),
12770 paddress (arm_record->gdbarch,
12771 arm_record->this_addr), insn_size);
12775 else if (ARM_RECORD == record_type)
12777 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12778 insn_id = bits (arm_record->arm_insn, 25, 27);
12780 if (arm_record->cond == 0xf)
12781 ret = arm_record_extension_space (arm_record);
12784 /* If this insn has fallen into extension space
12785 then we need not decode it anymore. */
12786 ret = arm_handle_insn[insn_id] (arm_record);
12788 if (ret != ARM_RECORD_SUCCESS)
12790 arm_record_unsupported_insn (arm_record);
12794 else if (THUMB_RECORD == record_type)
12796 /* As thumb does not have condition codes, we set negative. */
12797 arm_record->cond = -1;
12798 insn_id = bits (arm_record->arm_insn, 13, 15);
12799 ret = thumb_handle_insn[insn_id] (arm_record);
12800 if (ret != ARM_RECORD_SUCCESS)
12802 arm_record_unsupported_insn (arm_record);
12806 else if (THUMB2_RECORD == record_type)
12808 /* As thumb does not have condition codes, we set negative. */
12809 arm_record->cond = -1;
12811 /* Swap first half of 32bit thumb instruction with second half. */
12812 arm_record->arm_insn
12813 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
12815 ret = thumb2_record_decode_insn_handler (arm_record);
12817 if (ret != ARM_RECORD_SUCCESS)
12819 arm_record_unsupported_insn (arm_record);
12825 /* Throw assertion. */
12826 gdb_assert_not_reached ("not a valid instruction, could not decode");
12833 /* Cleans up local record registers and memory allocations. */
12836 deallocate_reg_mem (insn_decode_record *record)
12838 xfree (record->arm_regs);
12839 xfree (record->arm_mems);
12843 /* Parse the current instruction and record the values of the registers and
12844 memory that will be changed in current instruction to record_arch_list".
12845 Return -1 if something is wrong. */
12848 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
12849 CORE_ADDR insn_addr)
12852 uint32_t no_of_rec = 0;
12853 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
12854 ULONGEST t_bit = 0, insn_id = 0;
12856 ULONGEST u_regval = 0;
12858 insn_decode_record arm_record;
12860 memset (&arm_record, 0, sizeof (insn_decode_record));
12861 arm_record.regcache = regcache;
12862 arm_record.this_addr = insn_addr;
12863 arm_record.gdbarch = gdbarch;
12866 if (record_debug > 1)
12868 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
12870 paddress (gdbarch, arm_record.this_addr));
12873 if (extract_arm_insn (&arm_record, 2))
12877 printf_unfiltered (_("Process record: error reading memory at "
12878 "addr %s len = %d.\n"),
12879 paddress (arm_record.gdbarch,
12880 arm_record.this_addr), 2);
12885 /* Check the insn, whether it is thumb or arm one. */
12887 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
12888 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
12891 if (!(u_regval & t_bit))
12893 /* We are decoding arm insn. */
12894 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
12898 insn_id = bits (arm_record.arm_insn, 11, 15);
12899 /* is it thumb2 insn? */
12900 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
12902 ret = decode_insn (&arm_record, THUMB2_RECORD,
12903 THUMB2_INSN_SIZE_BYTES);
12907 /* We are decoding thumb insn. */
12908 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
12914 /* Record registers. */
12915 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
12916 if (arm_record.arm_regs)
12918 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
12920 if (record_full_arch_list_add_reg
12921 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
12925 /* Record memories. */
12926 if (arm_record.arm_mems)
12928 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
12930 if (record_full_arch_list_add_mem
12931 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
12932 arm_record.arm_mems[no_of_rec].len))
12937 if (record_full_arch_list_add_end ())
12942 deallocate_reg_mem (&arm_record);