1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
31 extern void _initialize_arm_tdep (void);
33 /* From opcodes/arm-dis.c */
35 extern int get_arm_regname_num_options (void);
37 extern int set_arm_regname_option (int option);
39 extern int get_arm_regnames (int option, const char **setname,
40 const char **setdescription,
41 const char ***regnames);
43 /* Number of different reg name sets (options). */
44 static int num_flavor_options;
46 /* We have more registers than the disassembler as gdb can print the value
47 of special registers as well.
48 The general register names are overwritten by whatever is being used by
49 the disassembler at the moment. We also adjust the case of cpsr and fps. */
51 /* Initial value: Register names used in ARM's ISA documentation. */
52 static char * arm_register_name_strings[] =
53 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
54 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
55 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
56 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
57 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
58 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
59 "fps", "cpsr" }; /* 24 25 */
60 char **arm_register_names = arm_register_name_strings;
62 /* Valid register name flavors. */
63 static char **valid_flavors;
65 /* Disassembly flavor to use. Default to "std" register names. */
66 static char *disassembly_flavor;
67 static int current_option; /* Index to that option in the opcodes table. */
69 /* This is used to keep the bfd arch_info in sync with the disassembly
71 static void set_disassembly_flavor_sfunc(char *, int,
72 struct cmd_list_element *);
73 static void set_disassembly_flavor (void);
75 static void convert_from_extended (void *ptr, void *dbl);
77 /* Define other aspects of the stack frame. We keep the offsets of
78 all saved registers, 'cause we need 'em a lot! We also keep the
79 current size of the stack frame, and the offset of the frame
80 pointer from the stack pointer (for frameless functions, and when
81 we're still in the prologue of a function with a frame) */
83 struct frame_extra_info
85 struct frame_saved_regs fsr;
91 /* Addresses for calling Thumb functions have the bit 0 set.
92 Here are some macros to test, set, or clear bit 0 of addresses. */
93 #define IS_THUMB_ADDR(addr) ((addr) & 1)
94 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
95 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
97 #define SWAP_TARGET_AND_HOST(buffer,len) \
100 if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
103 char *p = (char *)(buffer); \
104 char *q = ((char *)(buffer)) + len - 1; \
105 for (; p < q; p++, q--) \
115 /* Will a function return an aggregate type in memory or in a
116 register? Return 0 if an aggregate type can be returned in a
117 register, 1 if it must be returned in memory. */
120 arm_use_struct_convention (int gcc_p, struct type *type)
123 register enum type_code code;
125 /* In the ARM ABI, "integer" like aggregate types are returned in
126 registers. For an aggregate type to be integer like, its size
127 must be less than or equal to REGISTER_SIZE and the offset of
128 each addressable subfield must be zero. Note that bit fields are
129 not addressable, and all addressable subfields of unions always
130 start at offset zero.
132 This function is based on the behaviour of GCC 2.95.1.
133 See: gcc/arm.c: arm_return_in_memory() for details.
135 Note: All versions of GCC before GCC 2.95.2 do not set up the
136 parameters correctly for a function returning the following
137 structure: struct { float f;}; This should be returned in memory,
138 not a register. Richard Earnshaw sent me a patch, but I do not
139 know of any way to detect if a function like the above has been
140 compiled with the correct calling convention. */
142 /* All aggregate types that won't fit in a register must be returned
144 if (TYPE_LENGTH (type) > REGISTER_SIZE)
149 /* The only aggregate types that can be returned in a register are
150 structs and unions. Arrays must be returned in memory. */
151 code = TYPE_CODE (type);
152 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
157 /* Assume all other aggregate types can be returned in a register.
158 Run a check for structures, unions and arrays. */
161 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
164 /* Need to check if this struct/union is "integer" like. For
165 this to be true, its size must be less than or equal to
166 REGISTER_SIZE and the offset of each addressable subfield
167 must be zero. Note that bit fields are not addressable, and
168 unions always start at offset zero. If any of the subfields
169 is a floating point type, the struct/union cannot be an
172 /* For each field in the object, check:
173 1) Is it FP? --> yes, nRc = 1;
174 2) Is it addressable (bitpos != 0) and
175 not packed (bitsize == 0)?
179 for (i = 0; i < TYPE_NFIELDS (type); i++)
181 enum type_code field_type_code;
182 field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
184 /* Is it a floating point type field? */
185 if (field_type_code == TYPE_CODE_FLT)
191 /* If bitpos != 0, then we have to care about it. */
192 if (TYPE_FIELD_BITPOS (type, i) != 0)
194 /* Bitfields are not addressable. If the field bitsize is
195 zero, then the field is not packed. Hence it cannot be
196 a bitfield or any other packed type. */
197 if (TYPE_FIELD_BITSIZE (type, i) == 0)
210 arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
212 return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
215 /* Set to true if the 32-bit mode is in use. */
219 /* Flag set by arm_fix_call_dummy that tells whether the target
220 function is a Thumb function. This flag is checked by
221 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
222 its use in valops.c) to pass the function address as an additional
225 static int target_is_thumb;
227 /* Flag set by arm_fix_call_dummy that tells whether the calling
228 function is a Thumb function. This flag is checked by
229 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
231 static int caller_is_thumb;
233 /* Determine if the program counter specified in MEMADDR is in a Thumb
237 arm_pc_is_thumb (bfd_vma memaddr)
239 struct minimal_symbol *sym;
241 /* If bit 0 of the address is set, assume this is a Thumb address. */
242 if (IS_THUMB_ADDR (memaddr))
245 /* Thumb functions have a "special" bit set in minimal symbols. */
246 sym = lookup_minimal_symbol_by_pc (memaddr);
249 return (MSYMBOL_IS_SPECIAL (sym));
257 /* Determine if the program counter specified in MEMADDR is in a call
258 dummy being called from a Thumb function. */
261 arm_pc_is_thumb_dummy (bfd_vma memaddr)
263 CORE_ADDR sp = read_sp ();
265 /* FIXME: Until we switch for the new call dummy macros, this heuristic
266 is the best we can do. We are trying to determine if the pc is on
267 the stack, which (hopefully) will only happen in a call dummy.
268 We hope the current stack pointer is not so far alway from the dummy
269 frame location (true if we have not pushed large data structures or
270 gone too many levels deep) and that our 1024 is not enough to consider
271 code regions as part of the stack (true for most practical purposes) */
272 if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
273 return caller_is_thumb;
279 arm_addr_bits_remove (CORE_ADDR val)
281 if (arm_pc_is_thumb (val))
282 return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
284 return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
288 arm_saved_pc_after_call (struct frame_info *frame)
290 return ADDR_BITS_REMOVE (read_register (LR_REGNUM));
294 arm_frameless_function_invocation (struct frame_info *fi)
296 CORE_ADDR func_start, after_prologue;
299 func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
300 after_prologue = SKIP_PROLOGUE (func_start);
302 /* There are some frameless functions whose first two instructions
303 follow the standard APCS form, in which case after_prologue will
304 be func_start + 8. */
306 frameless = (after_prologue < func_start + 12);
310 /* A typical Thumb prologue looks like this:
314 Sometimes the latter instruction may be replaced by:
322 or, on tpcs, like this:
329 There is always one instruction of three classes:
334 When we have found at least one of each class we are done with the prolog.
335 Note that the "sub sp, #NN" before the push does not count.
339 thumb_skip_prologue (CORE_ADDR pc)
341 CORE_ADDR current_pc;
342 int findmask = 0; /* findmask:
343 bit 0 - push { rlist }
344 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
345 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
348 for (current_pc = pc; current_pc < pc + 40; current_pc += 2)
350 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
352 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
354 findmask |= 1; /* push found */
356 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
358 if ((findmask & 1) == 0) /* before push ? */
361 findmask |= 4; /* add/sub sp found */
363 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
365 findmask |= 2; /* setting of r7 found */
367 else if (insn == 0x466f) /* mov r7, sp */
369 findmask |= 2; /* setting of r7 found */
372 continue; /* something in the prolog that we don't care about or some
373 instruction from outside the prolog scheduled here for optimization */
379 /* The APCS (ARM Procedure Call Standard) defines the following
383 [stmfd sp!, {a1,a2,a3,a4}]
384 stmfd sp!, {...,fp,ip,lr,pc}
385 [stfe f7, [sp, #-12]!]
386 [stfe f6, [sp, #-12]!]
387 [stfe f5, [sp, #-12]!]
388 [stfe f4, [sp, #-12]!]
389 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
392 arm_skip_prologue (CORE_ADDR pc)
396 CORE_ADDR func_addr, func_end;
397 struct symtab_and_line sal;
399 /* See what the symbol table says. */
401 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
403 sal = find_pc_line (func_addr, 0);
404 if ((sal.line != 0) && (sal.end < func_end))
408 /* Check if this is Thumb code. */
409 if (arm_pc_is_thumb (pc))
410 return thumb_skip_prologue (pc);
412 /* Can't find the prologue end in the symbol table, try it the hard way
413 by disassembling the instructions. */
415 inst = read_memory_integer (skip_pc, 4);
416 if (inst != 0xe1a0c00d) /* mov ip, sp */
420 inst = read_memory_integer (skip_pc, 4);
421 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
424 inst = read_memory_integer (skip_pc, 4);
427 if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
431 inst = read_memory_integer (skip_pc, 4);
433 /* Any insns after this point may float into the code, if it makes
434 for better instruction scheduling, so we skip them only if we
435 find them, but still consdier the function to be frame-ful. */
437 /* We may have either one sfmfd instruction here, or several stfe
438 insns, depending on the version of floating point code we
440 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
443 inst = read_memory_integer (skip_pc, 4);
447 while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
450 inst = read_memory_integer (skip_pc, 4);
454 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
460 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
461 This function decodes a Thumb function prologue to determine:
462 1) the size of the stack frame
463 2) which registers are saved on it
464 3) the offsets of saved regs
465 4) the offset from the stack pointer to the frame pointer
466 This information is stored in the "extra" fields of the frame_info.
468 A typical Thumb function prologue would create this stack frame
469 (offsets relative to FP)
470 old SP -> 24 stack parameters
473 R7 -> 0 local variables (16 bytes)
474 SP -> -12 additional stack space (12 bytes)
475 The frame size would thus be 36 bytes, and the frame offset would be
476 12 bytes. The frame register is R7.
478 The comments for thumb_skip_prolog() describe the algorithm we use to detect
479 the end of the prolog */
483 thumb_scan_prologue (struct frame_info *fi)
485 CORE_ADDR prologue_start;
486 CORE_ADDR prologue_end;
487 CORE_ADDR current_pc;
488 int saved_reg[16]; /* which register has been copied to register n? */
489 int findmask = 0; /* findmask:
490 bit 0 - push { rlist }
491 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
492 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
496 if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
498 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
500 if (sal.line == 0) /* no line info, use current PC */
501 prologue_end = fi->pc;
502 else if (sal.end < prologue_end) /* next line begins after fn end */
503 prologue_end = sal.end; /* (probably means no prologue) */
506 prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */
507 /* 16 pushes, an add, and "mv fp,sp" */
509 prologue_end = min (prologue_end, fi->pc);
511 /* Initialize the saved register map. When register H is copied to
512 register L, we will put H in saved_reg[L]. */
513 for (i = 0; i < 16; i++)
516 /* Search the prologue looking for instructions that set up the
517 frame pointer, adjust the stack pointer, and save registers.
518 Do this until all basic prolog instructions are found. */
521 for (current_pc = prologue_start;
522 (current_pc < prologue_end) && ((findmask & 7) != 7);
529 insn = read_memory_unsigned_integer (current_pc, 2);
531 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
534 findmask |= 1; /* push found */
535 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
536 whether to save LR (R14). */
537 mask = (insn & 0xff) | ((insn & 0x100) << 6);
539 /* Calculate offsets of saved R0-R7 and LR. */
540 for (regno = LR_REGNUM; regno >= 0; regno--)
541 if (mask & (1 << regno))
544 fi->fsr.regs[saved_reg[regno]] = -(fi->framesize);
545 saved_reg[regno] = regno; /* reset saved register map */
548 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
550 if ((findmask & 1) == 0) /* before push ? */
553 findmask |= 4; /* add/sub sp found */
555 offset = (insn & 0x7f) << 2; /* get scaled offset */
556 if (insn & 0x80) /* is it signed? (==subtracting) */
558 fi->frameoffset += offset;
561 fi->framesize -= offset;
563 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
565 findmask |= 2; /* setting of r7 found */
566 fi->framereg = THUMB_FP_REGNUM;
567 fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */
569 else if (insn == 0x466f) /* mov r7, sp */
571 findmask |= 2; /* setting of r7 found */
572 fi->framereg = THUMB_FP_REGNUM;
574 saved_reg[THUMB_FP_REGNUM] = SP_REGNUM;
576 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
578 int lo_reg = insn & 7; /* dest. register (r0-r7) */
579 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
580 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
583 continue; /* something in the prolog that we don't care about or some
584 instruction from outside the prolog scheduled here for optimization */
588 /* Check if prologue for this frame's PC has already been scanned. If
589 it has, copy the relevant information about that prologue and
590 return non-zero. Otherwise do not copy anything and return zero.
592 The information saved in the cache includes:
593 * the frame register number;
594 * the size of the stack frame;
595 * the offsets of saved regs (relative to the old SP); and
596 * the offset from the stack pointer to the frame pointer
598 The cache contains only one entry, since this is adequate for the
599 typical sequence of prologue scan requests we get. When performing
600 a backtrace, GDB will usually ask to scan the same function twice
601 in a row (once to get the frame chain, and once to fill in the
602 extra frame information). */
604 static struct frame_info prologue_cache;
607 check_prologue_cache (struct frame_info *fi)
611 if (fi->pc == prologue_cache.pc)
613 fi->framereg = prologue_cache.framereg;
614 fi->framesize = prologue_cache.framesize;
615 fi->frameoffset = prologue_cache.frameoffset;
616 for (i = 0; i <= NUM_REGS; i++)
617 fi->fsr.regs[i] = prologue_cache.fsr.regs[i];
625 /* Copy the prologue information from fi to the prologue cache. */
628 save_prologue_cache (struct frame_info *fi)
632 prologue_cache.pc = fi->pc;
633 prologue_cache.framereg = fi->framereg;
634 prologue_cache.framesize = fi->framesize;
635 prologue_cache.frameoffset = fi->frameoffset;
637 for (i = 0; i <= NUM_REGS; i++)
638 prologue_cache.fsr.regs[i] = fi->fsr.regs[i];
642 /* This function decodes an ARM function prologue to determine:
643 1) the size of the stack frame
644 2) which registers are saved on it
645 3) the offsets of saved regs
646 4) the offset from the stack pointer to the frame pointer
647 This information is stored in the "extra" fields of the frame_info.
649 There are two basic forms for the ARM prologue. The fixed argument
650 function call will look like:
653 stmfd sp!, {fp, ip, lr, pc}
657 Which would create this stack frame (offsets relative to FP):
658 IP -> 4 (caller's stack)
659 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
660 -4 LR (return address in caller)
661 -8 IP (copy of caller's SP)
663 SP -> -28 Local variables
665 The frame size would thus be 32 bytes, and the frame offset would be
666 28 bytes. The stmfd call can also save any of the vN registers it
667 plans to use, which increases the frame size accordingly.
669 Note: The stored PC is 8 off of the STMFD instruction that stored it
670 because the ARM Store instructions always store PC + 8 when you read
673 A variable argument function call will look like:
676 stmfd sp!, {a1, a2, a3, a4}
677 stmfd sp!, {fp, ip, lr, pc}
680 Which would create this stack frame (offsets relative to FP):
681 IP -> 20 (caller's stack)
686 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
687 -4 LR (return address in caller)
688 -8 IP (copy of caller's SP)
690 SP -> -28 Local variables
692 The frame size would thus be 48 bytes, and the frame offset would be
695 There is another potential complication, which is that the optimizer
696 will try to separate the store of fp in the "stmfd" instruction from
697 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
698 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
700 Also, note, the original version of the ARM toolchain claimed that there
703 instruction at the end of the prologue. I have never seen GCC produce
704 this, and the ARM docs don't mention it. We still test for it below in
710 arm_scan_prologue (struct frame_info *fi)
712 int regno, sp_offset, fp_offset;
713 CORE_ADDR prologue_start, prologue_end, current_pc;
715 /* Check if this function is already in the cache of frame information. */
716 if (check_prologue_cache (fi))
719 /* Assume there is no frame until proven otherwise. */
720 fi->framereg = SP_REGNUM;
724 /* Check for Thumb prologue. */
725 if (arm_pc_is_thumb (fi->pc))
727 thumb_scan_prologue (fi);
728 save_prologue_cache (fi);
732 /* Find the function prologue. If we can't find the function in
733 the symbol table, peek in the stack frame to find the PC. */
734 if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
736 /* Assume the prologue is everything between the first instruction
737 in the function and the first source line. */
738 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
740 if (sal.line == 0) /* no line info, use current PC */
741 prologue_end = fi->pc;
742 else if (sal.end < prologue_end) /* next line begins after fn end */
743 prologue_end = sal.end; /* (probably means no prologue) */
747 /* Get address of the stmfd in the prologue of the callee; the saved
748 PC is the address of the stmfd + 8. */
749 prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4))
751 prologue_end = prologue_start + 64; /* This is all the insn's
752 that could be in the prologue,
753 plus room for 5 insn's inserted
757 /* Now search the prologue looking for instructions that set up the
758 frame pointer, adjust the stack pointer, and save registers.
760 Be careful, however, and if it doesn't look like a prologue,
761 don't try to scan it. If, for instance, a frameless function
762 begins with stmfd sp!, then we will tell ourselves there is
763 a frame, which will confuse stack traceback, as well ad"finish"
764 and other operations that rely on a knowledge of the stack
767 In the APCS, the prologue should start with "mov ip, sp" so
768 if we don't see this as the first insn, we will stop. */
770 sp_offset = fp_offset = 0;
772 if (read_memory_unsigned_integer (prologue_start, 4)
773 == 0xe1a0c00d) /* mov ip, sp */
775 for (current_pc = prologue_start + 4; current_pc < prologue_end;
778 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
780 if ((insn & 0xffff0000) == 0xe92d0000)
781 /* stmfd sp!, {..., fp, ip, lr, pc}
783 stmfd sp!, {a1, a2, a3, a4} */
785 int mask = insn & 0xffff;
787 /* Calculate offsets of saved registers. */
788 for (regno = PC_REGNUM; regno >= 0; regno--)
789 if (mask & (1 << regno))
792 fi->fsr.regs[regno] = sp_offset;
795 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
797 unsigned imm = insn & 0xff; /* immediate value */
798 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
799 imm = (imm >> rot) | (imm << (32 - rot));
801 fi->framereg = FP_REGNUM;
803 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
805 unsigned imm = insn & 0xff; /* immediate value */
806 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
807 imm = (imm >> rot) | (imm << (32 - rot));
810 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
813 regno = F0_REGNUM + ((insn >> 12) & 0x07);
814 fi->fsr.regs[regno] = sp_offset;
816 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
819 unsigned int fp_start_reg, fp_bound_reg;
821 if ((insn & 0x800) == 0x800) /* N0 is set */
823 if ((insn & 0x40000) == 0x40000) /* N1 is set */
830 if ((insn & 0x40000) == 0x40000) /* N1 is set */
836 fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7);
837 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
838 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
841 fi->fsr.regs[fp_start_reg++] = sp_offset;
845 /* The optimizer might shove anything into the prologue,
846 so we just skip what we don't recognize. */
851 /* The frame size is just the negative of the offset (from the original SP)
852 of the last thing thing we pushed on the stack. The frame offset is
853 [new FP] - [new SP]. */
854 fi->framesize = -sp_offset;
855 fi->frameoffset = fp_offset - sp_offset;
857 save_prologue_cache (fi);
860 /* Find REGNUM on the stack. Otherwise, it's in an active register.
861 One thing we might want to do here is to check REGNUM against the
862 clobber mask, and somehow flag it as invalid if it isn't saved on
863 the stack somewhere. This would provide a graceful failure mode
864 when trying to get the value of caller-saves registers for an inner
868 arm_find_callers_reg (struct frame_info *fi, int regnum)
870 for (; fi; fi = fi->next)
872 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
873 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
874 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
877 if (fi->fsr.regs[regnum] != 0)
878 return read_memory_integer (fi->fsr.regs[regnum],
879 REGISTER_RAW_SIZE (regnum));
880 return read_register (regnum);
883 /* Function: frame_chain
884 Given a GDB frame, determine the address of the calling function's frame.
885 This will be used to create a new GDB frame struct, and then
886 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
887 For ARM, we save the frame size when we initialize the frame_info.
889 The original definition of this function was a macro in tm-arm.h:
890 { In the case of the ARM, the frame's nominal address is the FP value,
891 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
893 #define FRAME_CHAIN(thisframe) \
894 ((thisframe)->pc >= LOWEST_PC ? \
895 read_memory_integer ((thisframe)->frame - 12, 4) :\
901 arm_frame_chain (struct frame_info *fi)
903 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
904 CORE_ADDR fn_start, callers_pc, fp;
906 /* is this a dummy frame? */
907 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
908 return fi->frame; /* dummy frame same as caller's frame */
910 /* is caller-of-this a dummy frame? */
911 callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */
912 fp = arm_find_callers_reg (fi, FP_REGNUM);
913 if (PC_IN_CALL_DUMMY (callers_pc, fp, fp))
914 return fp; /* dummy frame's frame may bear no relation to ours */
916 if (find_pc_partial_function (fi->pc, 0, &fn_start, 0))
917 if (fn_start == entry_point_address ())
918 return 0; /* in _start fn, don't chain further */
920 CORE_ADDR caller_pc, fn_start;
921 struct frame_info caller_fi;
922 int framereg = fi->framereg;
924 if (fi->pc < LOWEST_PC)
927 /* If the caller is the startup code, we're at the end of the chain. */
928 caller_pc = FRAME_SAVED_PC (fi);
929 if (find_pc_partial_function (caller_pc, 0, &fn_start, 0))
930 if (fn_start == entry_point_address ())
933 /* If the caller is Thumb and the caller is ARM, or vice versa,
934 the frame register of the caller is different from ours.
935 So we must scan the prologue of the caller to determine its
936 frame register number. */
937 if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
939 memset (&caller_fi, 0, sizeof (caller_fi));
940 caller_fi.pc = caller_pc;
941 arm_scan_prologue (&caller_fi);
942 framereg = caller_fi.framereg;
945 /* If the caller used a frame register, return its value.
946 Otherwise, return the caller's stack pointer. */
947 if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM)
948 return arm_find_callers_reg (fi, framereg);
950 return fi->frame + fi->framesize;
953 /* This function actually figures out the frame address for a given pc
954 and sp. This is tricky because we sometimes don't use an explicit
955 frame pointer, and the previous stack pointer isn't necessarily
956 recorded on the stack. The only reliable way to get this info is
957 to examine the prologue. FROMLEAF is a little confusing, it means
958 this is the next frame up the chain AFTER a frameless function. If
959 this is true, then the frame value for this frame is still in the
963 arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
968 fi->pc = FRAME_SAVED_PC (fi->next);
970 memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs);
972 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
973 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
975 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
976 by assuming it's always FP. */
977 fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM);
985 arm_scan_prologue (fi);
988 /* this is the innermost frame? */
989 fi->frame = read_register (fi->framereg);
990 else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM)
992 /* not the innermost frame */
993 /* If we have an FP, the callee saved it. */
994 if (fi->next->fsr.regs[fi->framereg] != 0)
996 read_memory_integer (fi->next->fsr.regs[fi->framereg], 4);
998 /* If we were called by a frameless fn. then our frame is
999 still in the frame pointer register on the board... */
1000 fi->frame = read_fp ();
1003 /* Calculate actual addresses of saved registers using offsets
1004 determined by arm_scan_prologue. */
1005 for (reg = 0; reg < NUM_REGS; reg++)
1006 if (fi->fsr.regs[reg] != 0)
1007 fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset;
1012 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1013 is saved in the stack anywhere, otherwise we get it from the
1016 The old definition of this function was a macro:
1017 #define FRAME_SAVED_PC(FRAME) \
1018 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1021 arm_frame_saved_pc (struct frame_info *fi)
1023 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1024 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1025 return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
1029 CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM);
1030 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1034 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1035 Examine the Program Status Register to decide which state we're in. */
1038 arm_target_read_fp (void)
1040 if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
1041 return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
1043 return read_register (FP_REGNUM); /* R11 if ARM */
1046 /* Calculate the frame offsets of the saved registers (ARM version). */
1049 arm_frame_find_saved_regs (struct frame_info *fi,
1050 struct frame_saved_regs *regaddr)
1052 memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs));
1056 arm_push_dummy_frame (void)
1058 CORE_ADDR old_sp = read_register (SP_REGNUM);
1059 CORE_ADDR sp = old_sp;
1060 CORE_ADDR fp, prologue_start;
1063 /* Push the two dummy prologue instructions in reverse order,
1064 so that they'll be in the correct low-to-high order in memory. */
1065 /* sub fp, ip, #4 */
1066 sp = push_word (sp, 0xe24cb004);
1067 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1068 prologue_start = sp = push_word (sp, 0xe92ddfff);
1070 /* Push a pointer to the dummy prologue + 12, because when stm
1071 instruction stores the PC, it stores the address of the stm
1072 instruction itself plus 12. */
1073 fp = sp = push_word (sp, prologue_start + 12);
1074 sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */
1075 sp = push_word (sp, old_sp);
1076 sp = push_word (sp, read_register (FP_REGNUM));
1078 for (regnum = 10; regnum >= 0; regnum--)
1079 sp = push_word (sp, read_register (regnum));
1081 write_register (FP_REGNUM, fp);
1082 write_register (THUMB_FP_REGNUM, fp);
1083 write_register (SP_REGNUM, sp);
1086 /* Fix up the call dummy, based on whether the processor is currently
1087 in Thumb or ARM mode, and whether the target function is Thumb or
1088 ARM. There are three different situations requiring three
1091 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1092 been copied into the dummy parameter to this function.
1093 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1094 "mov pc,r4" instruction patched to be a "bx r4" instead.
1095 * Thumb calling anything: uses the Thumb dummy defined below, which
1096 works for calling both ARM and Thumb functions.
1098 All three call dummies expect to receive the target function
1099 address in R4, with the low bit set if it's a Thumb function. */
1102 arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1103 value_ptr *args, struct type *type, int gcc_p)
1105 static short thumb_dummy[4] =
1107 0xf000, 0xf801, /* bl label */
1108 0xdf18, /* swi 24 */
1109 0x4720, /* label: bx r4 */
1111 static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
1113 /* Set flag indicating whether the current PC is in a Thumb function. */
1114 caller_is_thumb = arm_pc_is_thumb (read_pc ());
1116 /* If the target function is Thumb, set the low bit of the function
1117 address. And if the CPU is currently in ARM mode, patch the
1118 second instruction of call dummy to use a BX instruction to
1119 switch to Thumb mode. */
1120 target_is_thumb = arm_pc_is_thumb (fun);
1121 if (target_is_thumb)
1124 if (!caller_is_thumb)
1125 store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
1128 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1129 instead of the ARM one that's already been copied. This will
1130 work for both Thumb and ARM target functions. */
1131 if (caller_is_thumb)
1135 int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
1137 for (i = 0; i < len; i++)
1139 store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
1140 p += sizeof (thumb_dummy[0]);
1144 /* Put the target address in r4; the call dummy will copy this to
1146 write_register (4, fun);
1149 /* Return the offset in the call dummy of the instruction that needs
1150 to have a breakpoint placed on it. This is the offset of the 'swi
1151 24' instruction, which is no longer actually used, but simply acts
1152 as a place-holder now.
1154 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1157 arm_call_dummy_breakpoint_offset (void)
1159 if (caller_is_thumb)
1167 This function does not support passing parameters using the FPA
1168 variant of the APCS. It passes any floating point arguments in the
1169 general registers and/or on the stack. */
1172 arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp,
1173 int struct_return, CORE_ADDR struct_addr)
1176 int argnum, argreg, nstack_size;
1178 /* Walk through the list of args and determine how large a temporary
1179 stack is required. Need to take care here as structs may be
1180 passed on the stack, and we have to to push them. */
1181 nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
1182 if (struct_return) /* The struct address goes in A1. */
1183 nstack_size += REGISTER_SIZE;
1185 /* Walk through the arguments and add their size to nstack_size. */
1186 for (argnum = 0; argnum < nargs; argnum++)
1189 struct type *arg_type;
1191 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1192 len = TYPE_LENGTH (arg_type);
1194 /* ANSI C code passes float arguments as integers, K&R code
1195 passes float arguments as doubles. Correct for this here. */
1196 if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len)
1197 nstack_size += FP_REGISTER_VIRTUAL_SIZE;
1202 /* Allocate room on the stack, and initialize our stack frame
1205 if (nstack_size > 0)
1211 /* Initialize the integer argument register pointer. */
1214 /* The struct_return pointer occupies the first parameter passing
1217 write_register (argreg++, struct_addr);
1219 /* Process arguments from left to right. Store as many as allowed
1220 in the parameter passing registers (A1-A4), and save the rest on
1221 the temporary stack. */
1222 for (argnum = 0; argnum < nargs; argnum++)
1228 enum type_code typecode;
1229 struct type *arg_type, *target_type;
1231 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1232 target_type = TYPE_TARGET_TYPE (arg_type);
1233 len = TYPE_LENGTH (arg_type);
1234 typecode = TYPE_CODE (arg_type);
1235 val = (char *) VALUE_CONTENTS (args[argnum]);
1237 /* ANSI C code passes float arguments as integers, K&R code
1238 passes float arguments as doubles. The .stabs record for
1239 for ANSI prototype floating point arguments records the
1240 type as FP_INTEGER, while a K&R style (no prototype)
1241 .stabs records the type as FP_FLOAT. In this latter case
1242 the compiler converts the float arguments to double before
1243 calling the function. */
1244 if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
1248 char * bufo = (char *) &d;
1249 char * bufd = (char *) &dbl_arg;
1251 len = sizeof (double);
1253 SWAP_TARGET_AND_HOST (&f, sizeof (float)); /* adjust endianess */
1255 /* We must revert the longwords so they get loaded into the
1256 the right registers. */
1257 memcpy (bufd, bufo + len / 2, len / 2);
1258 SWAP_TARGET_AND_HOST (bufd, len / 2); /* adjust endianess */
1259 memcpy (bufd + len / 2, bufo, len / 2);
1260 SWAP_TARGET_AND_HOST (bufd + len / 2, len / 2); /* adjust endianess */
1261 val = (char *) &dbl_arg;
1264 /* I don't know why this code was disable. The only logical use
1265 for a function pointer is to call that function, so setting
1266 the mode bit is perfectly fine. FN */
1267 /* If the argument is a pointer to a function, and it is a Thumb
1268 function, set the low bit of the pointer. */
1269 if (TYPE_CODE_PTR == typecode
1270 && NULL != target_type
1271 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1273 CORE_ADDR regval = extract_address (val, len);
1274 if (arm_pc_is_thumb (regval))
1275 store_address (val, len, MAKE_THUMB_ADDR (regval));
1278 /* Copy the argument to general registers or the stack in
1279 register-sized pieces. Large arguments are split between
1280 registers and stack. */
1283 int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
1285 if (argreg <= ARM_LAST_ARG_REGNUM)
1287 /* It's an argument being passed in a general register. */
1288 regval = extract_address (val, partial_len);
1289 write_register (argreg++, regval);
1293 /* Push the arguments onto the stack. */
1294 write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
1295 fp += REGISTER_SIZE;
1303 /* Return adjusted stack pointer. */
1308 arm_pop_frame (void)
1311 struct frame_info *frame = get_current_frame ();
1313 if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp()))
1317 old_SP = read_register (frame->framereg);
1318 for (regnum = 0; regnum < NUM_REGS; regnum++)
1319 if (frame->fsr.regs[regnum] != 0)
1320 write_register (regnum,
1321 read_memory_integer (frame->fsr.regs[regnum], 4));
1323 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
1324 write_register (SP_REGNUM, old_SP);
1330 sp = read_register (FP_REGNUM);
1331 sp -= sizeof(CORE_ADDR); /* we don't care about this first word */
1333 write_register (PC_REGNUM, read_memory_integer (sp, 4));
1334 sp -= sizeof(CORE_ADDR);
1335 write_register (SP_REGNUM, read_memory_integer (sp, 4));
1336 sp -= sizeof(CORE_ADDR);
1337 write_register (FP_REGNUM, read_memory_integer (sp, 4));
1338 sp -= sizeof(CORE_ADDR);
1340 for (regnum = 10; regnum >= 0; regnum--)
1342 write_register (regnum, read_memory_integer (sp, 4));
1343 sp -= sizeof(CORE_ADDR);
1347 flush_cached_frames ();
1351 print_fpu_flags (int flags)
1353 if (flags & (1 << 0))
1354 fputs ("IVO ", stdout);
1355 if (flags & (1 << 1))
1356 fputs ("DVZ ", stdout);
1357 if (flags & (1 << 2))
1358 fputs ("OFL ", stdout);
1359 if (flags & (1 << 3))
1360 fputs ("UFL ", stdout);
1361 if (flags & (1 << 4))
1362 fputs ("INX ", stdout);
1367 arm_float_info (void)
1369 register unsigned long status = read_register (FPS_REGNUM);
1372 type = (status >> 24) & 127;
1373 printf ("%s FPU type %d\n",
1374 (status & (1 << 31)) ? "Hardware" : "Software",
1376 fputs ("mask: ", stdout);
1377 print_fpu_flags (status >> 16);
1378 fputs ("flags: ", stdout);
1379 print_fpu_flags (status);
1383 /* FIXME: The generated assembler works but sucks. Instead of using
1384 r0, r1 it pushes them on the stack, then loads them into r3, r4 and
1385 uses those registers. I must be missing something. ScottB */
1388 convert_from_extended (void *ptr, void *dbl)
1394 : "r" (ptr), "r" (dbl));
1398 convert_to_extended (void *dbl, void *ptr)
1404 : "r" (dbl), "r" (ptr));
1408 convert_from_extended (void *ptr, void *dbl)
1410 *(double *) dbl = *(double *) ptr;
1414 convert_to_extended (void *dbl, void *ptr)
1416 *(double *) ptr = *(double *) dbl;
1420 /* Nonzero if register N requires conversion from raw format to
1424 arm_register_convertible (unsigned int regnum)
1426 return ((regnum - F0_REGNUM) < 8);
1429 /* Convert data from raw format for register REGNUM in buffer FROM to
1430 virtual format with type TYPE in buffer TO. */
1433 arm_register_convert_to_virtual (unsigned int regnum, struct type *type,
1434 void *from, void *to)
1438 convert_from_extended (from, &val);
1439 store_floating (to, TYPE_LENGTH (type), val);
1442 /* Convert data from virtual format with type TYPE in buffer FROM to
1443 raw format for register REGNUM in buffer TO. */
1446 arm_register_convert_to_raw (unsigned int regnum, struct type *type,
1447 void *from, void *to)
1449 double val = extract_floating (from, TYPE_LENGTH (type));
1451 convert_to_extended (&val, to);
1455 condition_true (unsigned long cond, unsigned long status_reg)
1457 if (cond == INST_AL || cond == INST_NV)
1463 return ((status_reg & FLAG_Z) != 0);
1465 return ((status_reg & FLAG_Z) == 0);
1467 return ((status_reg & FLAG_C) != 0);
1469 return ((status_reg & FLAG_C) == 0);
1471 return ((status_reg & FLAG_N) != 0);
1473 return ((status_reg & FLAG_N) == 0);
1475 return ((status_reg & FLAG_V) != 0);
1477 return ((status_reg & FLAG_V) == 0);
1479 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1481 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1483 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1485 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1487 return (((status_reg & FLAG_Z) == 0) &&
1488 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1490 return (((status_reg & FLAG_Z) != 0) ||
1491 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1496 #define submask(x) ((1L << ((x) + 1)) - 1)
1497 #define bit(obj,st) (((obj) >> (st)) & 1)
1498 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1499 #define sbits(obj,st,fn) \
1500 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1501 #define BranchDest(addr,instr) \
1502 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1505 static unsigned long
1506 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1507 unsigned long status_reg)
1509 unsigned long res, shift;
1510 int rm = bits (inst, 0, 3);
1511 unsigned long shifttype = bits (inst, 5, 6);
1515 int rs = bits (inst, 8, 11);
1516 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1519 shift = bits (inst, 7, 11);
1522 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1523 + (bit (inst, 4) ? 12 : 8))
1524 : read_register (rm));
1529 res = shift >= 32 ? 0 : res << shift;
1533 res = shift >= 32 ? 0 : res >> shift;
1539 res = ((res & 0x80000000L)
1540 ? ~((~res) >> shift) : res >> shift);
1543 case 3: /* ROR/RRX */
1546 res = (res >> 1) | (carry ? 0x80000000L : 0);
1548 res = (res >> shift) | (res << (32 - shift));
1552 return res & 0xffffffff;
1555 /* Return number of 1-bits in VAL. */
1558 bitcount (unsigned long val)
1561 for (nbits = 0; val != 0; nbits++)
1562 val &= val - 1; /* delete rightmost 1-bit in val */
1567 thumb_get_next_pc (CORE_ADDR pc)
1569 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1570 unsigned short inst1 = read_memory_integer (pc, 2);
1571 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1572 unsigned long offset;
1574 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1578 /* Fetch the saved PC from the stack. It's stored above
1579 all of the other registers. */
1580 offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
1581 sp = read_register (SP_REGNUM);
1582 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1583 nextpc = ADDR_BITS_REMOVE (nextpc);
1585 error ("Infinite loop detected");
1587 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1589 unsigned long status = read_register (PS_REGNUM);
1590 unsigned long cond = bits (inst1, 8, 11);
1591 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1592 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1594 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1596 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1598 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
1600 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1601 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1602 nextpc = pc_val + offset;
1609 arm_get_next_pc (CORE_ADDR pc)
1611 unsigned long pc_val;
1612 unsigned long this_instr;
1613 unsigned long status;
1616 if (arm_pc_is_thumb (pc))
1617 return thumb_get_next_pc (pc);
1619 pc_val = (unsigned long) pc;
1620 this_instr = read_memory_integer (pc, 4);
1621 status = read_register (PS_REGNUM);
1622 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1624 if (condition_true (bits (this_instr, 28, 31), status))
1626 switch (bits (this_instr, 24, 27))
1629 case 0x1: /* data processing */
1633 unsigned long operand1, operand2, result = 0;
1637 if (bits (this_instr, 12, 15) != 15)
1640 if (bits (this_instr, 22, 25) == 0
1641 && bits (this_instr, 4, 7) == 9) /* multiply */
1642 error ("Illegal update to pc in instruction");
1644 /* Multiply into PC */
1645 c = (status & FLAG_C) ? 1 : 0;
1646 rn = bits (this_instr, 16, 19);
1647 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1649 if (bit (this_instr, 25))
1651 unsigned long immval = bits (this_instr, 0, 7);
1652 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1653 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1656 else /* operand 2 is a shifted register */
1657 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1659 switch (bits (this_instr, 21, 24))
1662 result = operand1 & operand2;
1666 result = operand1 ^ operand2;
1670 result = operand1 - operand2;
1674 result = operand2 - operand1;
1678 result = operand1 + operand2;
1682 result = operand1 + operand2 + c;
1686 result = operand1 - operand2 + c;
1690 result = operand2 - operand1 + c;
1696 case 0xb: /* tst, teq, cmp, cmn */
1697 result = (unsigned long) nextpc;
1701 result = operand1 | operand2;
1705 /* Always step into a function. */
1710 result = operand1 & ~operand2;
1717 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1720 error ("Infinite loop detected");
1725 case 0x5: /* data transfer */
1728 if (bit (this_instr, 20))
1731 if (bits (this_instr, 12, 15) == 15)
1737 if (bit (this_instr, 22))
1738 error ("Illegal update to pc in instruction");
1740 /* byte write to PC */
1741 rn = bits (this_instr, 16, 19);
1742 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1743 if (bit (this_instr, 24))
1746 int c = (status & FLAG_C) ? 1 : 0;
1747 unsigned long offset =
1748 (bit (this_instr, 25)
1749 ? shifted_reg_val (this_instr, c, pc_val, status)
1750 : bits (this_instr, 0, 11));
1752 if (bit (this_instr, 23))
1757 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1760 nextpc = ADDR_BITS_REMOVE (nextpc);
1763 error ("Infinite loop detected");
1769 case 0x9: /* block transfer */
1770 if (bit (this_instr, 20))
1773 if (bit (this_instr, 15))
1778 if (bit (this_instr, 23))
1781 unsigned long reglist = bits (this_instr, 0, 14);
1782 offset = bitcount (reglist) * 4;
1783 if (bit (this_instr, 24)) /* pre */
1786 else if (bit (this_instr, 24))
1790 unsigned long rn_val =
1791 read_register (bits (this_instr, 16, 19));
1793 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1797 nextpc = ADDR_BITS_REMOVE (nextpc);
1799 error ("Infinite loop detected");
1804 case 0xb: /* branch & link */
1805 case 0xa: /* branch */
1807 nextpc = BranchDest (pc, this_instr);
1809 nextpc = ADDR_BITS_REMOVE (nextpc);
1811 error ("Infinite loop detected");
1817 case 0xe: /* coproc ops */
1822 fprintf (stderr, "Bad bit-field extraction\n");
1830 #include "bfd-in2.h"
1831 #include "libcoff.h"
1834 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1836 if (arm_pc_is_thumb (memaddr))
1838 static asymbol *asym;
1839 static combined_entry_type ce;
1840 static struct coff_symbol_struct csym;
1841 static struct _bfd fake_bfd;
1842 static bfd_target fake_target;
1844 if (csym.native == NULL)
1846 /* Create a fake symbol vector containing a Thumb symbol. This is
1847 solely so that the code in print_insn_little_arm() and
1848 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1849 of a Thumb symbol and switch to decoding Thumb instructions. */
1851 fake_target.flavour = bfd_target_coff_flavour;
1852 fake_bfd.xvec = &fake_target;
1853 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1855 csym.symbol.the_bfd = &fake_bfd;
1856 csym.symbol.name = "fake";
1857 asym = (asymbol *) & csym;
1860 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1861 info->symbols = &asym;
1864 info->symbols = NULL;
1866 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1867 return print_insn_big_arm (memaddr, info);
1869 return print_insn_little_arm (memaddr, info);
1872 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1873 program counter value to determine whether a 16-bit or 32-bit
1874 breakpoint should be used. It returns a pointer to a string of
1875 bytes that encode a breakpoint instruction, stores the length of
1876 the string to *lenptr, and adjusts the program counter (if
1877 necessary) to point to the actual memory location where the
1878 breakpoint should be inserted. */
1881 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1883 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
1885 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1887 static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT;
1888 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1889 *lenptr = sizeof (thumb_breakpoint);
1890 return thumb_breakpoint;
1894 static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT;
1895 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1896 *lenptr = sizeof (thumb_breakpoint);
1897 return thumb_breakpoint;
1902 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1904 static char arm_breakpoint[] = ARM_BE_BREAKPOINT;
1905 *lenptr = sizeof (arm_breakpoint);
1906 return arm_breakpoint;
1910 static char arm_breakpoint[] = ARM_LE_BREAKPOINT;
1911 *lenptr = sizeof (arm_breakpoint);
1912 return arm_breakpoint;
1917 /* Extract from an array REGBUF containing the (raw) register state a
1918 function return value of type TYPE, and copy that, in virtual
1919 format, into VALBUF. */
1922 arm_extract_return_value (struct type *type,
1923 char regbuf[REGISTER_BYTES],
1926 if (TYPE_CODE_FLT == TYPE_CODE (type))
1927 convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf);
1929 memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type));
1932 /* Return non-zero if the PC is inside a thumb call thunk. */
1935 arm_in_call_stub (CORE_ADDR pc, char *name)
1937 CORE_ADDR start_addr;
1939 /* Find the starting address of the function containing the PC. If
1940 the caller didn't give us a name, look it up at the same time. */
1941 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
1944 return strncmp (name, "_call_via_r", 11) == 0;
1947 /* If PC is in a Thumb call or return stub, return the address of the
1948 target PC, which is in a register. The thunk functions are called
1949 _called_via_xx, where x is the register name. The possible names
1950 are r0-r9, sl, fp, ip, sp, and lr. */
1953 arm_skip_stub (CORE_ADDR pc)
1956 CORE_ADDR start_addr;
1958 /* Find the starting address and name of the function containing the PC. */
1959 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1962 /* Call thunks always start with "_call_via_". */
1963 if (strncmp (name, "_call_via_", 10) == 0)
1965 /* Use the name suffix to determine which register contains the
1967 static char *table[15] =
1968 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1969 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
1973 for (regno = 0; regno <= 14; regno++)
1974 if (strcmp (&name[10], table[regno]) == 0)
1975 return read_register (regno);
1978 return 0; /* not a stub */
1981 /* If the user changes the register disassembly flavor used for info register
1982 and other commands, we have to also switch the flavor used in opcodes
1983 for disassembly output.
1984 This function is run in the set disassembly_flavor command, and does that. */
1987 set_disassembly_flavor_sfunc (char *args, int from_tty,
1988 struct cmd_list_element *c)
1990 set_disassembly_flavor ();
1994 set_disassembly_flavor (void)
1996 const char *setname, *setdesc, **regnames;
1999 /* Find the flavor that the user wants in the opcodes table. */
2001 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2002 while ((disassembly_flavor != setname)
2003 && (current < num_flavor_options))
2004 get_arm_regnames (++current, &setname, &setdesc, ®names);
2005 current_option = current;
2007 /* Fill our copy. */
2008 for (j = 0; j < numregs; j++)
2009 arm_register_names[j] = (char *) regnames[j];
2012 if (isupper (*regnames[PC_REGNUM]))
2014 arm_register_names[FPS_REGNUM] = "FPS";
2015 arm_register_names[PS_REGNUM] = "CPSR";
2019 arm_register_names[FPS_REGNUM] = "fps";
2020 arm_register_names[PS_REGNUM] = "cpsr";
2023 /* Synchronize the disassembler. */
2024 set_arm_regname_option (current);
2027 /* arm_othernames implements the "othernames" command. This is kind
2028 of hacky, and I prefer the set-show disassembly-flavor which is
2029 also used for the x86 gdb. I will keep this around, however, in
2030 case anyone is actually using it. */
2033 arm_othernames (char *names, int n)
2035 /* Circle through the various flavors. */
2036 current_option = (current_option + 1) % num_flavor_options;
2038 disassembly_flavor = valid_flavors[current_option];
2039 set_disassembly_flavor ();
2043 _initialize_arm_tdep (void)
2045 struct ui_file *stb;
2047 struct cmd_list_element *new_cmd;
2048 const char *setname, *setdesc, **regnames;
2050 static char *helptext;
2052 tm_print_insn = gdb_print_insn_arm;
2054 /* Get the number of possible sets of register names defined in opcodes. */
2055 num_flavor_options = get_arm_regname_num_options ();
2057 /* Sync the opcode insn printer with our register viewer: */
2058 parse_arm_disassembler_option ("reg-names-std");
2060 /* Begin creating the help text. */
2061 stb = mem_fileopen ();
2062 fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
2063 The valid values are:\n");
2065 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2066 valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
2067 for (i = 0; i < num_flavor_options; i++)
2069 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2070 valid_flavors[i] = (char *) setname;
2071 fprintf_unfiltered (stb, "%s - %s\n", setname,
2073 /* Copy the default names (if found) and synchronize disassembler. */
2074 if (!strcmp (setname, "std"))
2076 disassembly_flavor = (char *) setname;
2078 for (j = 0; j < numregs; j++)
2079 arm_register_names[j] = (char *) regnames[j];
2080 set_arm_regname_option (i);
2083 /* Mark the end of valid options. */
2084 valid_flavors[num_flavor_options] = NULL;
2086 /* Finish the creation of the help text. */
2087 fprintf_unfiltered (stb, "The default is \"std\".");
2088 helptext = ui_file_xstrdup (stb, &length);
2089 ui_file_delete (stb);
2091 /* Add the disassembly-flavor command */
2092 new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
2094 (char *) &disassembly_flavor,
2097 new_cmd->function.sfunc = set_disassembly_flavor_sfunc;
2098 add_show_from_set (new_cmd, &showlist);
2100 /* ??? Maybe this should be a boolean. */
2101 add_show_from_set (add_set_cmd ("apcs32", no_class,
2102 var_zinteger, (char *) &arm_apcs_32,
2103 "Set usage of ARM 32-bit mode.\n", &setlist),
2106 /* Add the deprecated "othernames" command */
2108 add_com ("othernames", class_obscure, arm_othernames,
2109 "Switch to the next set of register names.");
2112 /* Test whether the coff symbol specific value corresponds to a Thumb
2116 coff_sym_is_thumb (int val)
2118 return (val == C_THUMBEXT ||
2119 val == C_THUMBSTAT ||
2120 val == C_THUMBEXTFUNC ||
2121 val == C_THUMBSTATFUNC ||
2122 val == C_THUMBLABEL);