1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-1989, 1991-1993, 1995-1996, 1998-2012 Free
4 Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include <ctype.h> /* XXX for isupper (). */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "gdb/sim-arm.h"
53 #include "coff/internal.h"
56 #include "gdb_assert.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data *arm_objfile_data_key;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
93 DEF_VEC_O(arm_mapping_symbol_s);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s) **section_maps;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element *setarmcmdlist = NULL;
102 static struct cmd_list_element *showarmcmdlist = NULL;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
118 static const char *current_fp_model = "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
131 static const char *arm_abi_string = "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings[] =
142 static const char *arm_fallback_mode_string = "auto";
143 static const char *arm_force_mode_string = "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode = -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element *);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat *, const void *,
229 static void convert_to_extended (const struct floatformat *, void *,
232 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
233 struct regcache *regcache,
234 int regnum, gdb_byte *buf);
235 static void arm_neon_quad_write (struct gdbarch *gdbarch,
236 struct regcache *regcache,
237 int regnum, const gdb_byte *buf);
239 static int thumb_insn_size (unsigned short inst1);
241 struct arm_prologue_cache
243 /* The stack pointer at the time this frame was created; i.e. the
244 caller's stack pointer when this function was called. It is used
245 to identify this frame. */
248 /* The frame base for this frame is just prev_sp - frame size.
249 FRAMESIZE is the distance from the frame pointer to the
250 initial stack pointer. */
254 /* The register used to hold the frame pointer for this frame. */
257 /* Saved register offsets. */
258 struct trad_frame_saved_reg *saved_regs;
261 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
262 CORE_ADDR prologue_start,
263 CORE_ADDR prologue_end,
264 struct arm_prologue_cache *cache);
266 /* Architecture version for displaced stepping. This effects the behaviour of
267 certain instructions, and really should not be hard-wired. */
269 #define DISPLACED_STEPPING_ARCH_VERSION 5
271 /* Addresses for calling Thumb functions have the bit 0 set.
272 Here are some macros to test, set, or clear bit 0 of addresses. */
273 #define IS_THUMB_ADDR(addr) ((addr) & 1)
274 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
275 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch *gdbarch)
286 if (gdbarch_tdep (gdbarch)->is_m)
292 /* Determine if FRAME is executing in Thumb mode. */
295 arm_frame_is_thumb (struct frame_info *frame)
298 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
300 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
301 directly (from a signal frame or dummy frame) or by interpreting
302 the saved LR (from a prologue or DWARF frame). So consult it and
303 trust the unwinders. */
304 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
306 return (cpsr & t_bit) != 0;
309 /* Callback for VEC_lower_bound. */
312 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
313 const struct arm_mapping_symbol *rhs)
315 return lhs->value < rhs->value;
318 /* Search for the mapping symbol covering MEMADDR. If one is found,
319 return its type. Otherwise, return 0. If START is non-NULL,
320 set *START to the location of the mapping symbol. */
323 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
325 struct obj_section *sec;
327 /* If there are mapping symbols, consult them. */
328 sec = find_pc_section (memaddr);
331 struct arm_per_objfile *data;
332 VEC(arm_mapping_symbol_s) *map;
333 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
337 data = objfile_data (sec->objfile, arm_objfile_data_key);
340 map = data->section_maps[sec->the_bfd_section->index];
341 if (!VEC_empty (arm_mapping_symbol_s, map))
343 struct arm_mapping_symbol *map_sym;
345 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
346 arm_compare_mapping_symbols);
348 /* VEC_lower_bound finds the earliest ordered insertion
349 point. If the following symbol starts at this exact
350 address, we use that; otherwise, the preceding
351 mapping symbol covers this address. */
352 if (idx < VEC_length (arm_mapping_symbol_s, map))
354 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
355 if (map_sym->value == map_key.value)
358 *start = map_sym->value + obj_section_addr (sec);
359 return map_sym->type;
365 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
367 *start = map_sym->value + obj_section_addr (sec);
368 return map_sym->type;
377 /* Determine if the program counter specified in MEMADDR is in a Thumb
378 function. This function should be called for addresses unrelated to
379 any executing frame; otherwise, prefer arm_frame_is_thumb. */
382 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
384 struct minimal_symbol *sym;
386 struct displaced_step_closure* dsc
387 = get_displaced_step_closure_by_addr(memaddr);
389 /* If checking the mode of displaced instruction in copy area, the mode
390 should be determined by instruction on the original address. */
394 fprintf_unfiltered (gdb_stdlog,
395 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (unsigned long) dsc->insn_addr,
397 (unsigned long) memaddr);
398 memaddr = dsc->insn_addr;
401 /* If bit 0 of the address is set, assume this is a Thumb address. */
402 if (IS_THUMB_ADDR (memaddr))
405 /* Respect internal mode override if active. */
406 if (arm_override_mode != -1)
407 return arm_override_mode;
409 /* If the user wants to override the symbol table, let him. */
410 if (strcmp (arm_force_mode_string, "arm") == 0)
412 if (strcmp (arm_force_mode_string, "thumb") == 0)
415 /* ARM v6-M and v7-M are always in Thumb mode. */
416 if (gdbarch_tdep (gdbarch)->is_m)
419 /* If there are mapping symbols, consult them. */
420 type = arm_find_mapping_symbol (memaddr, NULL);
424 /* Thumb functions have a "special" bit set in minimal symbols. */
425 sym = lookup_minimal_symbol_by_pc (memaddr);
427 return (MSYMBOL_IS_SPECIAL (sym));
429 /* If the user wants to override the fallback mode, let them. */
430 if (strcmp (arm_fallback_mode_string, "arm") == 0)
432 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
435 /* If we couldn't find any symbol, but we're talking to a running
436 target, then trust the current value of $cpsr. This lets
437 "display/i $pc" always show the correct mode (though if there is
438 a symbol table we will not reach here, so it still may not be
439 displayed in the mode it will be executed). */
440 if (target_has_registers)
441 return arm_frame_is_thumb (get_current_frame ());
443 /* Otherwise we're out of luck; we assume ARM. */
447 /* Remove useless bits from addresses in a running program. */
449 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
451 /* On M-profile devices, do not strip the low bit from EXC_RETURN
452 (the magic exception return address). */
453 if (gdbarch_tdep (gdbarch)->is_m
454 && (val & 0xfffffff0) == 0xfffffff0)
458 return UNMAKE_THUMB_ADDR (val);
460 return (val & 0x03fffffc);
463 /* When reading symbols, we need to zap the low bit of the address,
464 which may be set to 1 for Thumb functions. */
466 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
471 /* Return 1 if PC is the start of a compiler helper function which
472 can be safely ignored during prologue skipping. IS_THUMB is true
473 if the function is known to be a Thumb function due to the way it
476 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
478 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
479 struct minimal_symbol *msym;
481 msym = lookup_minimal_symbol_by_pc (pc);
483 && SYMBOL_VALUE_ADDRESS (msym) == pc
484 && SYMBOL_LINKAGE_NAME (msym) != NULL)
486 const char *name = SYMBOL_LINKAGE_NAME (msym);
488 /* The GNU linker's Thumb call stub to foo is named
490 if (strstr (name, "_from_thumb") != NULL)
493 /* On soft-float targets, __truncdfsf2 is called to convert promoted
494 arguments to their argument types in non-prototyped
496 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
498 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
501 /* Internal functions related to thread-local storage. */
502 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
504 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
509 /* If we run against a stripped glibc, we may be unable to identify
510 special functions by name. Check for one important case,
511 __aeabi_read_tp, by comparing the *code* against the default
512 implementation (this is hand-written ARM assembler in glibc). */
515 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
516 == 0xe3e00a0f /* mov r0, #0xffff0fff */
517 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
518 == 0xe240f01f) /* sub pc, r0, #31 */
525 /* Support routines for instruction parsing. */
526 #define submask(x) ((1L << ((x) + 1)) - 1)
527 #define bit(obj,st) (((obj) >> (st)) & 1)
528 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
529 #define sbits(obj,st,fn) \
530 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
531 #define BranchDest(addr,instr) \
532 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
534 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
535 the first 16-bit of instruction, and INSN2 is the second 16-bit of
537 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
538 ((bits ((insn1), 0, 3) << 12) \
539 | (bits ((insn1), 10, 10) << 11) \
540 | (bits ((insn2), 12, 14) << 8) \
541 | bits ((insn2), 0, 7))
543 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
544 the 32-bit instruction. */
545 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
546 ((bits ((insn), 16, 19) << 12) \
547 | bits ((insn), 0, 11))
549 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
552 thumb_expand_immediate (unsigned int imm)
554 unsigned int count = imm >> 7;
562 return (imm & 0xff) | ((imm & 0xff) << 16);
564 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
566 return (imm & 0xff) | ((imm & 0xff) << 8)
567 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
570 return (0x80 | (imm & 0x7f)) << (32 - count);
573 /* Return 1 if the 16-bit Thumb instruction INST might change
574 control flow, 0 otherwise. */
577 thumb_instruction_changes_pc (unsigned short inst)
579 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
582 if ((inst & 0xf000) == 0xd000) /* conditional branch */
585 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
588 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
591 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
594 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
600 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
601 might change control flow, 0 otherwise. */
604 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
606 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
608 /* Branches and miscellaneous control instructions. */
610 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
615 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
617 /* SUBS PC, LR, #imm8. */
620 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
622 /* Conditional branch. */
629 if ((inst1 & 0xfe50) == 0xe810)
631 /* Load multiple or RFE. */
633 if (bit (inst1, 7) && !bit (inst1, 8))
639 else if (!bit (inst1, 7) && bit (inst1, 8))
645 else if (bit (inst1, 7) && bit (inst1, 8))
650 else if (!bit (inst1, 7) && !bit (inst1, 8))
659 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
661 /* MOV PC or MOVS PC. */
665 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
668 if (bits (inst1, 0, 3) == 15)
674 if ((inst2 & 0x0fc0) == 0x0000)
680 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
686 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
695 /* Analyze a Thumb prologue, looking for a recognizable stack frame
696 and frame pointer. Scan until we encounter a store that could
697 clobber the stack frame unexpectedly, or an unknown instruction.
698 Return the last address which is definitely safe to skip for an
699 initial breakpoint. */
702 thumb_analyze_prologue (struct gdbarch *gdbarch,
703 CORE_ADDR start, CORE_ADDR limit,
704 struct arm_prologue_cache *cache)
706 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
707 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
710 struct pv_area *stack;
711 struct cleanup *back_to;
713 CORE_ADDR unrecognized_pc = 0;
715 for (i = 0; i < 16; i++)
716 regs[i] = pv_register (i, 0);
717 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
718 back_to = make_cleanup_free_pv_area (stack);
720 while (start < limit)
724 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
726 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
731 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
734 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
735 whether to save LR (R14). */
736 mask = (insn & 0xff) | ((insn & 0x100) << 6);
738 /* Calculate offsets of saved R0-R7 and LR. */
739 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
740 if (mask & (1 << regno))
742 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
744 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
747 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
750 offset = (insn & 0x7f) << 2; /* get scaled offset */
751 if (insn & 0x80) /* Check for SUB. */
752 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
755 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
758 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
759 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
761 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
762 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
763 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
765 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
766 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
767 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
769 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
770 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
771 && pv_is_constant (regs[bits (insn, 3, 5)]))
772 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
773 regs[bits (insn, 6, 8)]);
774 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
775 && pv_is_constant (regs[bits (insn, 3, 6)]))
777 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
778 int rm = bits (insn, 3, 6);
779 regs[rd] = pv_add (regs[rd], regs[rm]);
781 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
783 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
784 int src_reg = (insn & 0x78) >> 3;
785 regs[dst_reg] = regs[src_reg];
787 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
789 /* Handle stores to the stack. Normally pushes are used,
790 but with GCC -mtpcs-frame, there may be other stores
791 in the prologue to create the frame. */
792 int regno = (insn >> 8) & 0x7;
795 offset = (insn & 0xff) << 2;
796 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
798 if (pv_area_store_would_trash (stack, addr))
801 pv_area_store (stack, addr, 4, regs[regno]);
803 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
805 int rd = bits (insn, 0, 2);
806 int rn = bits (insn, 3, 5);
809 offset = bits (insn, 6, 10) << 2;
810 addr = pv_add_constant (regs[rn], offset);
812 if (pv_area_store_would_trash (stack, addr))
815 pv_area_store (stack, addr, 4, regs[rd]);
817 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
818 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
819 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
820 /* Ignore stores of argument registers to the stack. */
822 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
823 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
824 /* Ignore block loads from the stack, potentially copying
825 parameters from memory. */
827 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
828 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
829 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
830 /* Similarly ignore single loads from the stack. */
832 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
833 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
834 /* Skip register copies, i.e. saves to another register
835 instead of the stack. */
837 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
838 /* Recognize constant loads; even with small stacks these are necessary
840 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
841 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
843 /* Constant pool loads, for the same reason. */
844 unsigned int constant;
847 loc = start + 4 + bits (insn, 0, 7) * 4;
848 constant = read_memory_unsigned_integer (loc, 4, byte_order);
849 regs[bits (insn, 8, 10)] = pv_constant (constant);
851 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
853 unsigned short inst2;
855 inst2 = read_memory_unsigned_integer (start + 2, 2,
856 byte_order_for_code);
858 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
860 /* BL, BLX. Allow some special function calls when
861 skipping the prologue; GCC generates these before
862 storing arguments to the stack. */
864 int j1, j2, imm1, imm2;
866 imm1 = sbits (insn, 0, 10);
867 imm2 = bits (inst2, 0, 10);
868 j1 = bit (inst2, 13);
869 j2 = bit (inst2, 11);
871 offset = ((imm1 << 12) + (imm2 << 1));
872 offset ^= ((!j2) << 22) | ((!j1) << 23);
874 nextpc = start + 4 + offset;
875 /* For BLX make sure to clear the low bits. */
876 if (bit (inst2, 12) == 0)
877 nextpc = nextpc & 0xfffffffc;
879 if (!skip_prologue_function (gdbarch, nextpc,
880 bit (inst2, 12) != 0))
884 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
886 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
888 pv_t addr = regs[bits (insn, 0, 3)];
891 if (pv_area_store_would_trash (stack, addr))
894 /* Calculate offsets of saved registers. */
895 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
896 if (inst2 & (1 << regno))
898 addr = pv_add_constant (addr, -4);
899 pv_area_store (stack, addr, 4, regs[regno]);
903 regs[bits (insn, 0, 3)] = addr;
906 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
908 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
910 int regno1 = bits (inst2, 12, 15);
911 int regno2 = bits (inst2, 8, 11);
912 pv_t addr = regs[bits (insn, 0, 3)];
914 offset = inst2 & 0xff;
916 addr = pv_add_constant (addr, offset);
918 addr = pv_add_constant (addr, -offset);
920 if (pv_area_store_would_trash (stack, addr))
923 pv_area_store (stack, addr, 4, regs[regno1]);
924 pv_area_store (stack, pv_add_constant (addr, 4),
928 regs[bits (insn, 0, 3)] = addr;
931 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
932 && (inst2 & 0x0c00) == 0x0c00
933 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
935 int regno = bits (inst2, 12, 15);
936 pv_t addr = regs[bits (insn, 0, 3)];
938 offset = inst2 & 0xff;
940 addr = pv_add_constant (addr, offset);
942 addr = pv_add_constant (addr, -offset);
944 if (pv_area_store_would_trash (stack, addr))
947 pv_area_store (stack, addr, 4, regs[regno]);
950 regs[bits (insn, 0, 3)] = addr;
953 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
954 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
956 int regno = bits (inst2, 12, 15);
959 offset = inst2 & 0xfff;
960 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
962 if (pv_area_store_would_trash (stack, addr))
965 pv_area_store (stack, addr, 4, regs[regno]);
968 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
969 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
970 /* Ignore stores of argument registers to the stack. */
973 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
974 && (inst2 & 0x0d00) == 0x0c00
975 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
976 /* Ignore stores of argument registers to the stack. */
979 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
981 && (inst2 & 0x8000) == 0x0000
982 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
983 /* Ignore block loads from the stack, potentially copying
984 parameters from memory. */
987 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
989 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
990 /* Similarly ignore dual loads from the stack. */
993 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
994 && (inst2 & 0x0d00) == 0x0c00
995 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
996 /* Similarly ignore single loads from the stack. */
999 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1000 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
1001 /* Similarly ignore single loads from the stack. */
1004 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1005 && (inst2 & 0x8000) == 0x0000)
1007 unsigned int imm = ((bits (insn, 10, 10) << 11)
1008 | (bits (inst2, 12, 14) << 8)
1009 | bits (inst2, 0, 7));
1011 regs[bits (inst2, 8, 11)]
1012 = pv_add_constant (regs[bits (insn, 0, 3)],
1013 thumb_expand_immediate (imm));
1016 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1017 && (inst2 & 0x8000) == 0x0000)
1019 unsigned int imm = ((bits (insn, 10, 10) << 11)
1020 | (bits (inst2, 12, 14) << 8)
1021 | bits (inst2, 0, 7));
1023 regs[bits (inst2, 8, 11)]
1024 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1027 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1028 && (inst2 & 0x8000) == 0x0000)
1030 unsigned int imm = ((bits (insn, 10, 10) << 11)
1031 | (bits (inst2, 12, 14) << 8)
1032 | bits (inst2, 0, 7));
1034 regs[bits (inst2, 8, 11)]
1035 = pv_add_constant (regs[bits (insn, 0, 3)],
1036 - (CORE_ADDR) thumb_expand_immediate (imm));
1039 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1040 && (inst2 & 0x8000) == 0x0000)
1042 unsigned int imm = ((bits (insn, 10, 10) << 11)
1043 | (bits (inst2, 12, 14) << 8)
1044 | bits (inst2, 0, 7));
1046 regs[bits (inst2, 8, 11)]
1047 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1050 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1052 unsigned int imm = ((bits (insn, 10, 10) << 11)
1053 | (bits (inst2, 12, 14) << 8)
1054 | bits (inst2, 0, 7));
1056 regs[bits (inst2, 8, 11)]
1057 = pv_constant (thumb_expand_immediate (imm));
1060 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1063 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1065 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1068 else if (insn == 0xea5f /* mov.w Rd,Rm */
1069 && (inst2 & 0xf0f0) == 0)
1071 int dst_reg = (inst2 & 0x0f00) >> 8;
1072 int src_reg = inst2 & 0xf;
1073 regs[dst_reg] = regs[src_reg];
1076 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1078 /* Constant pool loads. */
1079 unsigned int constant;
1082 offset = bits (insn, 0, 11);
1084 loc = start + 4 + offset;
1086 loc = start + 4 - offset;
1088 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1089 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1092 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1094 /* Constant pool loads. */
1095 unsigned int constant;
1098 offset = bits (insn, 0, 7) << 2;
1100 loc = start + 4 + offset;
1102 loc = start + 4 - offset;
1104 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1105 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1107 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1108 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1111 else if (thumb2_instruction_changes_pc (insn, inst2))
1113 /* Don't scan past anything that might change control flow. */
1118 /* The optimizer might shove anything into the prologue,
1119 so we just skip what we don't recognize. */
1120 unrecognized_pc = start;
1125 else if (thumb_instruction_changes_pc (insn))
1127 /* Don't scan past anything that might change control flow. */
1132 /* The optimizer might shove anything into the prologue,
1133 so we just skip what we don't recognize. */
1134 unrecognized_pc = start;
1141 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1142 paddress (gdbarch, start));
1144 if (unrecognized_pc == 0)
1145 unrecognized_pc = start;
1149 do_cleanups (back_to);
1150 return unrecognized_pc;
1153 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1155 /* Frame pointer is fp. Frame size is constant. */
1156 cache->framereg = ARM_FP_REGNUM;
1157 cache->framesize = -regs[ARM_FP_REGNUM].k;
1159 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1161 /* Frame pointer is r7. Frame size is constant. */
1162 cache->framereg = THUMB_FP_REGNUM;
1163 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1167 /* Try the stack pointer... this is a bit desperate. */
1168 cache->framereg = ARM_SP_REGNUM;
1169 cache->framesize = -regs[ARM_SP_REGNUM].k;
1172 for (i = 0; i < 16; i++)
1173 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1174 cache->saved_regs[i].addr = offset;
1176 do_cleanups (back_to);
1177 return unrecognized_pc;
1181 /* Try to analyze the instructions starting from PC, which load symbol
1182 __stack_chk_guard. Return the address of instruction after loading this
1183 symbol, set the dest register number to *BASEREG, and set the size of
1184 instructions for loading symbol in OFFSET. Return 0 if instructions are
1188 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1189 unsigned int *destreg, int *offset)
1191 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1192 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1193 unsigned int low, high, address;
1198 unsigned short insn1
1199 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1201 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1203 *destreg = bits (insn1, 8, 10);
1205 address = bits (insn1, 0, 7);
1207 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1209 unsigned short insn2
1210 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1212 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1215 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1217 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1219 /* movt Rd, #const */
1220 if ((insn1 & 0xfbc0) == 0xf2c0)
1222 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1223 *destreg = bits (insn2, 8, 11);
1225 address = (high << 16 | low);
1232 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1234 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1236 address = bits (insn, 0, 11);
1237 *destreg = bits (insn, 12, 15);
1240 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1242 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1245 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1247 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1249 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1250 *destreg = bits (insn, 12, 15);
1252 address = (high << 16 | low);
1260 /* Try to skip a sequence of instructions used for stack protector. If PC
1261 points to the first instruction of this sequence, return the address of
1262 first instruction after this sequence, otherwise, return original PC.
1264 On arm, this sequence of instructions is composed of mainly three steps,
1265 Step 1: load symbol __stack_chk_guard,
1266 Step 2: load from address of __stack_chk_guard,
1267 Step 3: store it to somewhere else.
1269 Usually, instructions on step 2 and step 3 are the same on various ARM
1270 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1271 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1272 instructions in step 1 vary from different ARM architectures. On ARMv7,
1275 movw Rn, #:lower16:__stack_chk_guard
1276 movt Rn, #:upper16:__stack_chk_guard
1283 .word __stack_chk_guard
1285 Since ldr/str is a very popular instruction, we can't use them as
1286 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1287 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1288 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1291 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1293 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1294 unsigned int basereg;
1295 struct minimal_symbol *stack_chk_guard;
1297 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1300 /* Try to parse the instructions in Step 1. */
1301 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1306 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1307 /* If name of symbol doesn't start with '__stack_chk_guard', this
1308 instruction sequence is not for stack protector. If symbol is
1309 removed, we conservatively think this sequence is for stack protector. */
1311 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
1312 strlen ("__stack_chk_guard")) != 0)
1317 unsigned int destreg;
1319 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1321 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1322 if ((insn & 0xf800) != 0x6800)
1324 if (bits (insn, 3, 5) != basereg)
1326 destreg = bits (insn, 0, 2);
1328 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1329 byte_order_for_code);
1330 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1331 if ((insn & 0xf800) != 0x6000)
1333 if (destreg != bits (insn, 0, 2))
1338 unsigned int destreg;
1340 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1342 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1343 if ((insn & 0x0e500000) != 0x04100000)
1345 if (bits (insn, 16, 19) != basereg)
1347 destreg = bits (insn, 12, 15);
1348 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1349 insn = read_memory_unsigned_integer (pc + offset + 4,
1350 4, byte_order_for_code);
1351 if ((insn & 0x0e500000) != 0x04000000)
1353 if (bits (insn, 12, 15) != destreg)
1356 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1359 return pc + offset + 4;
1361 return pc + offset + 8;
1364 /* Advance the PC across any function entry prologue instructions to
1365 reach some "real" code.
1367 The APCS (ARM Procedure Call Standard) defines the following
1371 [stmfd sp!, {a1,a2,a3,a4}]
1372 stmfd sp!, {...,fp,ip,lr,pc}
1373 [stfe f7, [sp, #-12]!]
1374 [stfe f6, [sp, #-12]!]
1375 [stfe f5, [sp, #-12]!]
1376 [stfe f4, [sp, #-12]!]
1377 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1380 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1382 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1385 CORE_ADDR func_addr, limit_pc;
1387 /* See if we can determine the end of the prologue via the symbol table.
1388 If so, then return either PC, or the PC after the prologue, whichever
1390 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1392 CORE_ADDR post_prologue_pc
1393 = skip_prologue_using_sal (gdbarch, func_addr);
1394 struct symtab *s = find_pc_symtab (func_addr);
1396 if (post_prologue_pc)
1398 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1401 /* GCC always emits a line note before the prologue and another
1402 one after, even if the two are at the same address or on the
1403 same line. Take advantage of this so that we do not need to
1404 know every instruction that might appear in the prologue. We
1405 will have producer information for most binaries; if it is
1406 missing (e.g. for -gstabs), assuming the GNU tools. */
1407 if (post_prologue_pc
1409 || s->producer == NULL
1410 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0
1411 || strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
1412 return post_prologue_pc;
1414 if (post_prologue_pc != 0)
1416 CORE_ADDR analyzed_limit;
1418 /* For non-GCC compilers, make sure the entire line is an
1419 acceptable prologue; GDB will round this function's
1420 return value up to the end of the following line so we
1421 can not skip just part of a line (and we do not want to).
1423 RealView does not treat the prologue specially, but does
1424 associate prologue code with the opening brace; so this
1425 lets us skip the first line if we think it is the opening
1427 if (arm_pc_is_thumb (gdbarch, func_addr))
1428 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1429 post_prologue_pc, NULL);
1431 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1432 post_prologue_pc, NULL);
1434 if (analyzed_limit != post_prologue_pc)
1437 return post_prologue_pc;
1441 /* Can't determine prologue from the symbol table, need to examine
1444 /* Find an upper limit on the function prologue using the debug
1445 information. If the debug information could not be used to provide
1446 that bound, then use an arbitrary large number as the upper bound. */
1447 /* Like arm_scan_prologue, stop no later than pc + 64. */
1448 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1450 limit_pc = pc + 64; /* Magic. */
1453 /* Check if this is Thumb code. */
1454 if (arm_pc_is_thumb (gdbarch, pc))
1455 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1457 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1459 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1461 /* "mov ip, sp" is no longer a required part of the prologue. */
1462 if (inst == 0xe1a0c00d) /* mov ip, sp */
1465 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1468 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1471 /* Some prologues begin with "str lr, [sp, #-4]!". */
1472 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1475 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1478 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1481 /* Any insns after this point may float into the code, if it makes
1482 for better instruction scheduling, so we skip them only if we
1483 find them, but still consider the function to be frame-ful. */
1485 /* We may have either one sfmfd instruction here, or several stfe
1486 insns, depending on the version of floating point code we
1488 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1491 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1494 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1497 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1500 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1501 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1502 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1505 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1506 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1507 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1510 /* Un-recognized instruction; stop scanning. */
1514 return skip_pc; /* End of prologue. */
1518 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1519 This function decodes a Thumb function prologue to determine:
1520 1) the size of the stack frame
1521 2) which registers are saved on it
1522 3) the offsets of saved regs
1523 4) the offset from the stack pointer to the frame pointer
1525 A typical Thumb function prologue would create this stack frame
1526 (offsets relative to FP)
1527 old SP -> 24 stack parameters
1530 R7 -> 0 local variables (16 bytes)
1531 SP -> -12 additional stack space (12 bytes)
1532 The frame size would thus be 36 bytes, and the frame offset would be
1533 12 bytes. The frame register is R7.
1535 The comments for thumb_skip_prolog() describe the algorithm we use
1536 to detect the end of the prolog. */
1540 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1541 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1543 CORE_ADDR prologue_start;
1544 CORE_ADDR prologue_end;
1546 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1549 /* See comment in arm_scan_prologue for an explanation of
1551 if (prologue_end > prologue_start + 64)
1553 prologue_end = prologue_start + 64;
1557 /* We're in the boondocks: we have no idea where the start of the
1561 prologue_end = min (prologue_end, prev_pc);
1563 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1566 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1569 arm_instruction_changes_pc (uint32_t this_instr)
1571 if (bits (this_instr, 28, 31) == INST_NV)
1572 /* Unconditional instructions. */
1573 switch (bits (this_instr, 24, 27))
1577 /* Branch with Link and change to Thumb. */
1582 /* Coprocessor register transfer. */
1583 if (bits (this_instr, 12, 15) == 15)
1584 error (_("Invalid update to pc in instruction"));
1590 switch (bits (this_instr, 25, 27))
1593 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1595 /* Multiplies and extra load/stores. */
1596 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1597 /* Neither multiplies nor extension load/stores are allowed
1601 /* Otherwise, miscellaneous instructions. */
1603 /* BX <reg>, BXJ <reg>, BLX <reg> */
1604 if (bits (this_instr, 4, 27) == 0x12fff1
1605 || bits (this_instr, 4, 27) == 0x12fff2
1606 || bits (this_instr, 4, 27) == 0x12fff3)
1609 /* Other miscellaneous instructions are unpredictable if they
1613 /* Data processing instruction. Fall through. */
1616 if (bits (this_instr, 12, 15) == 15)
1623 /* Media instructions and architecturally undefined instructions. */
1624 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1628 if (bit (this_instr, 20) == 0)
1632 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1638 /* Load/store multiple. */
1639 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1645 /* Branch and branch with link. */
1650 /* Coprocessor transfers or SWIs can not affect PC. */
1654 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1658 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1659 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1660 fill it in. Return the first address not recognized as a prologue
1663 We recognize all the instructions typically found in ARM prologues,
1664 plus harmless instructions which can be skipped (either for analysis
1665 purposes, or a more restrictive set that can be skipped when finding
1666 the end of the prologue). */
1669 arm_analyze_prologue (struct gdbarch *gdbarch,
1670 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1671 struct arm_prologue_cache *cache)
1673 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1674 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1676 CORE_ADDR offset, current_pc;
1677 pv_t regs[ARM_FPS_REGNUM];
1678 struct pv_area *stack;
1679 struct cleanup *back_to;
1680 int framereg, framesize;
1681 CORE_ADDR unrecognized_pc = 0;
1683 /* Search the prologue looking for instructions that set up the
1684 frame pointer, adjust the stack pointer, and save registers.
1686 Be careful, however, and if it doesn't look like a prologue,
1687 don't try to scan it. If, for instance, a frameless function
1688 begins with stmfd sp!, then we will tell ourselves there is
1689 a frame, which will confuse stack traceback, as well as "finish"
1690 and other operations that rely on a knowledge of the stack
1693 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1694 regs[regno] = pv_register (regno, 0);
1695 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1696 back_to = make_cleanup_free_pv_area (stack);
1698 for (current_pc = prologue_start;
1699 current_pc < prologue_end;
1703 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1705 if (insn == 0xe1a0c00d) /* mov ip, sp */
1707 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1710 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1711 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1713 unsigned imm = insn & 0xff; /* immediate value */
1714 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1715 int rd = bits (insn, 12, 15);
1716 imm = (imm >> rot) | (imm << (32 - rot));
1717 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1720 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1721 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1723 unsigned imm = insn & 0xff; /* immediate value */
1724 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1725 int rd = bits (insn, 12, 15);
1726 imm = (imm >> rot) | (imm << (32 - rot));
1727 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1730 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1733 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1735 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1736 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1737 regs[bits (insn, 12, 15)]);
1740 else if ((insn & 0xffff0000) == 0xe92d0000)
1741 /* stmfd sp!, {..., fp, ip, lr, pc}
1743 stmfd sp!, {a1, a2, a3, a4} */
1745 int mask = insn & 0xffff;
1747 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1750 /* Calculate offsets of saved registers. */
1751 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1752 if (mask & (1 << regno))
1755 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1756 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1759 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1760 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1761 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1763 /* No need to add this to saved_regs -- it's just an arg reg. */
1766 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1767 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1768 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1770 /* No need to add this to saved_regs -- it's just an arg reg. */
1773 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1775 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1777 /* No need to add this to saved_regs -- it's just arg regs. */
1780 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1782 unsigned imm = insn & 0xff; /* immediate value */
1783 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1784 imm = (imm >> rot) | (imm << (32 - rot));
1785 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1787 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1789 unsigned imm = insn & 0xff; /* immediate value */
1790 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1791 imm = (imm >> rot) | (imm << (32 - rot));
1792 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1794 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1796 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1798 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1801 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1802 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1803 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1805 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1807 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1809 int n_saved_fp_regs;
1810 unsigned int fp_start_reg, fp_bound_reg;
1812 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1815 if ((insn & 0x800) == 0x800) /* N0 is set */
1817 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1818 n_saved_fp_regs = 3;
1820 n_saved_fp_regs = 1;
1824 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1825 n_saved_fp_regs = 2;
1827 n_saved_fp_regs = 4;
1830 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1831 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1832 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1834 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1835 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1836 regs[fp_start_reg++]);
1839 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1841 /* Allow some special function calls when skipping the
1842 prologue; GCC generates these before storing arguments to
1844 CORE_ADDR dest = BranchDest (current_pc, insn);
1846 if (skip_prologue_function (gdbarch, dest, 0))
1851 else if ((insn & 0xf0000000) != 0xe0000000)
1852 break; /* Condition not true, exit early. */
1853 else if (arm_instruction_changes_pc (insn))
1854 /* Don't scan past anything that might change control flow. */
1856 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1857 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1858 /* Ignore block loads from the stack, potentially copying
1859 parameters from memory. */
1861 else if ((insn & 0xfc500000) == 0xe4100000
1862 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1863 /* Similarly ignore single loads from the stack. */
1865 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1866 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1867 register instead of the stack. */
1871 /* The optimizer might shove anything into the prologue,
1872 so we just skip what we don't recognize. */
1873 unrecognized_pc = current_pc;
1878 if (unrecognized_pc == 0)
1879 unrecognized_pc = current_pc;
1881 /* The frame size is just the distance from the frame register
1882 to the original stack pointer. */
1883 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1885 /* Frame pointer is fp. */
1886 framereg = ARM_FP_REGNUM;
1887 framesize = -regs[ARM_FP_REGNUM].k;
1891 /* Try the stack pointer... this is a bit desperate. */
1892 framereg = ARM_SP_REGNUM;
1893 framesize = -regs[ARM_SP_REGNUM].k;
1898 cache->framereg = framereg;
1899 cache->framesize = framesize;
1901 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1902 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1903 cache->saved_regs[regno].addr = offset;
1907 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1908 paddress (gdbarch, unrecognized_pc));
1910 do_cleanups (back_to);
1911 return unrecognized_pc;
1915 arm_scan_prologue (struct frame_info *this_frame,
1916 struct arm_prologue_cache *cache)
1918 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1919 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1921 CORE_ADDR prologue_start, prologue_end, current_pc;
1922 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1923 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1924 pv_t regs[ARM_FPS_REGNUM];
1925 struct pv_area *stack;
1926 struct cleanup *back_to;
1929 /* Assume there is no frame until proven otherwise. */
1930 cache->framereg = ARM_SP_REGNUM;
1931 cache->framesize = 0;
1933 /* Check for Thumb prologue. */
1934 if (arm_frame_is_thumb (this_frame))
1936 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1940 /* Find the function prologue. If we can't find the function in
1941 the symbol table, peek in the stack frame to find the PC. */
1942 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1945 /* One way to find the end of the prologue (which works well
1946 for unoptimized code) is to do the following:
1948 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1951 prologue_end = prev_pc;
1952 else if (sal.end < prologue_end)
1953 prologue_end = sal.end;
1955 This mechanism is very accurate so long as the optimizer
1956 doesn't move any instructions from the function body into the
1957 prologue. If this happens, sal.end will be the last
1958 instruction in the first hunk of prologue code just before
1959 the first instruction that the scheduler has moved from
1960 the body to the prologue.
1962 In order to make sure that we scan all of the prologue
1963 instructions, we use a slightly less accurate mechanism which
1964 may scan more than necessary. To help compensate for this
1965 lack of accuracy, the prologue scanning loop below contains
1966 several clauses which'll cause the loop to terminate early if
1967 an implausible prologue instruction is encountered.
1973 is a suitable endpoint since it accounts for the largest
1974 possible prologue plus up to five instructions inserted by
1977 if (prologue_end > prologue_start + 64)
1979 prologue_end = prologue_start + 64; /* See above. */
1984 /* We have no symbol information. Our only option is to assume this
1985 function has a standard stack frame and the normal frame register.
1986 Then, we can find the value of our frame pointer on entrance to
1987 the callee (or at the present moment if this is the innermost frame).
1988 The value stored there should be the address of the stmfd + 8. */
1989 CORE_ADDR frame_loc;
1990 LONGEST return_value;
1992 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1993 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1997 prologue_start = gdbarch_addr_bits_remove
1998 (gdbarch, return_value) - 8;
1999 prologue_end = prologue_start + 64; /* See above. */
2003 if (prev_pc < prologue_end)
2004 prologue_end = prev_pc;
2006 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2009 static struct arm_prologue_cache *
2010 arm_make_prologue_cache (struct frame_info *this_frame)
2013 struct arm_prologue_cache *cache;
2014 CORE_ADDR unwound_fp;
2016 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2017 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2019 arm_scan_prologue (this_frame, cache);
2021 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2022 if (unwound_fp == 0)
2025 cache->prev_sp = unwound_fp + cache->framesize;
2027 /* Calculate actual addresses of saved registers using offsets
2028 determined by arm_scan_prologue. */
2029 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2030 if (trad_frame_addr_p (cache->saved_regs, reg))
2031 cache->saved_regs[reg].addr += cache->prev_sp;
2036 /* Our frame ID for a normal frame is the current function's starting PC
2037 and the caller's SP when we were called. */
2040 arm_prologue_this_id (struct frame_info *this_frame,
2042 struct frame_id *this_id)
2044 struct arm_prologue_cache *cache;
2048 if (*this_cache == NULL)
2049 *this_cache = arm_make_prologue_cache (this_frame);
2050 cache = *this_cache;
2052 /* This is meant to halt the backtrace at "_start". */
2053 pc = get_frame_pc (this_frame);
2054 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2057 /* If we've hit a wall, stop. */
2058 if (cache->prev_sp == 0)
2061 /* Use function start address as part of the frame ID. If we cannot
2062 identify the start address (due to missing symbol information),
2063 fall back to just using the current PC. */
2064 func = get_frame_func (this_frame);
2068 id = frame_id_build (cache->prev_sp, func);
2072 static struct value *
2073 arm_prologue_prev_register (struct frame_info *this_frame,
2077 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2078 struct arm_prologue_cache *cache;
2080 if (*this_cache == NULL)
2081 *this_cache = arm_make_prologue_cache (this_frame);
2082 cache = *this_cache;
2084 /* If we are asked to unwind the PC, then we need to return the LR
2085 instead. The prologue may save PC, but it will point into this
2086 frame's prologue, not the next frame's resume location. Also
2087 strip the saved T bit. A valid LR may have the low bit set, but
2088 a valid PC never does. */
2089 if (prev_regnum == ARM_PC_REGNUM)
2093 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2094 return frame_unwind_got_constant (this_frame, prev_regnum,
2095 arm_addr_bits_remove (gdbarch, lr));
2098 /* SP is generally not saved to the stack, but this frame is
2099 identified by the next frame's stack pointer at the time of the call.
2100 The value was already reconstructed into PREV_SP. */
2101 if (prev_regnum == ARM_SP_REGNUM)
2102 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2104 /* The CPSR may have been changed by the call instruction and by the
2105 called function. The only bit we can reconstruct is the T bit,
2106 by checking the low bit of LR as of the call. This is a reliable
2107 indicator of Thumb-ness except for some ARM v4T pre-interworking
2108 Thumb code, which could get away with a clear low bit as long as
2109 the called function did not use bx. Guess that all other
2110 bits are unchanged; the condition flags are presumably lost,
2111 but the processor status is likely valid. */
2112 if (prev_regnum == ARM_PS_REGNUM)
2115 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2117 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2118 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2119 if (IS_THUMB_ADDR (lr))
2123 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2126 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2130 struct frame_unwind arm_prologue_unwind = {
2132 default_frame_unwind_stop_reason,
2133 arm_prologue_this_id,
2134 arm_prologue_prev_register,
2136 default_frame_sniffer
2139 /* Maintain a list of ARM exception table entries per objfile, similar to the
2140 list of mapping symbols. We only cache entries for standard ARM-defined
2141 personality routines; the cache will contain only the frame unwinding
2142 instructions associated with the entry (not the descriptors). */
2144 static const struct objfile_data *arm_exidx_data_key;
2146 struct arm_exidx_entry
2151 typedef struct arm_exidx_entry arm_exidx_entry_s;
2152 DEF_VEC_O(arm_exidx_entry_s);
2154 struct arm_exidx_data
2156 VEC(arm_exidx_entry_s) **section_maps;
2160 arm_exidx_data_free (struct objfile *objfile, void *arg)
2162 struct arm_exidx_data *data = arg;
2165 for (i = 0; i < objfile->obfd->section_count; i++)
2166 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2170 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2171 const struct arm_exidx_entry *rhs)
2173 return lhs->addr < rhs->addr;
2176 static struct obj_section *
2177 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2179 struct obj_section *osect;
2181 ALL_OBJFILE_OSECTIONS (objfile, osect)
2182 if (bfd_get_section_flags (objfile->obfd,
2183 osect->the_bfd_section) & SEC_ALLOC)
2185 bfd_vma start, size;
2186 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2187 size = bfd_get_section_size (osect->the_bfd_section);
2189 if (start <= vma && vma < start + size)
2196 /* Parse contents of exception table and exception index sections
2197 of OBJFILE, and fill in the exception table entry cache.
2199 For each entry that refers to a standard ARM-defined personality
2200 routine, extract the frame unwinding instructions (from either
2201 the index or the table section). The unwinding instructions
2203 - extracting them from the rest of the table data
2204 - converting to host endianness
2205 - appending the implicit 0xb0 ("Finish") code
2207 The extracted and normalized instructions are stored for later
2208 retrieval by the arm_find_exidx_entry routine. */
2211 arm_exidx_new_objfile (struct objfile *objfile)
2213 struct cleanup *cleanups;
2214 struct arm_exidx_data *data;
2215 asection *exidx, *extab;
2216 bfd_vma exidx_vma = 0, extab_vma = 0;
2217 bfd_size_type exidx_size = 0, extab_size = 0;
2218 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2221 /* If we've already touched this file, do nothing. */
2222 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2224 cleanups = make_cleanup (null_cleanup, NULL);
2226 /* Read contents of exception table and index. */
2227 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2230 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2231 exidx_size = bfd_get_section_size (exidx);
2232 exidx_data = xmalloc (exidx_size);
2233 make_cleanup (xfree, exidx_data);
2235 if (!bfd_get_section_contents (objfile->obfd, exidx,
2236 exidx_data, 0, exidx_size))
2238 do_cleanups (cleanups);
2243 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2246 extab_vma = bfd_section_vma (objfile->obfd, extab);
2247 extab_size = bfd_get_section_size (extab);
2248 extab_data = xmalloc (extab_size);
2249 make_cleanup (xfree, extab_data);
2251 if (!bfd_get_section_contents (objfile->obfd, extab,
2252 extab_data, 0, extab_size))
2254 do_cleanups (cleanups);
2259 /* Allocate exception table data structure. */
2260 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2261 set_objfile_data (objfile, arm_exidx_data_key, data);
2262 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2263 objfile->obfd->section_count,
2264 VEC(arm_exidx_entry_s) *);
2266 /* Fill in exception table. */
2267 for (i = 0; i < exidx_size / 8; i++)
2269 struct arm_exidx_entry new_exidx_entry;
2270 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2271 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2272 bfd_vma addr = 0, word = 0;
2273 int n_bytes = 0, n_words = 0;
2274 struct obj_section *sec;
2275 gdb_byte *entry = NULL;
2277 /* Extract address of start of function. */
2278 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2279 idx += exidx_vma + i * 8;
2281 /* Find section containing function and compute section offset. */
2282 sec = arm_obj_section_from_vma (objfile, idx);
2285 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2287 /* Determine address of exception table entry. */
2290 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2292 else if ((val & 0xff000000) == 0x80000000)
2294 /* Exception table entry embedded in .ARM.exidx
2295 -- must be short form. */
2299 else if (!(val & 0x80000000))
2301 /* Exception table entry in .ARM.extab. */
2302 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2303 addr += exidx_vma + i * 8 + 4;
2305 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2307 word = bfd_h_get_32 (objfile->obfd,
2308 extab_data + addr - extab_vma);
2311 if ((word & 0xff000000) == 0x80000000)
2316 else if ((word & 0xff000000) == 0x81000000
2317 || (word & 0xff000000) == 0x82000000)
2321 n_words = ((word >> 16) & 0xff);
2323 else if (!(word & 0x80000000))
2326 struct obj_section *pers_sec;
2327 int gnu_personality = 0;
2329 /* Custom personality routine. */
2330 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2331 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2333 /* Check whether we've got one of the variants of the
2334 GNU personality routines. */
2335 pers_sec = arm_obj_section_from_vma (objfile, pers);
2338 static const char *personality[] =
2340 "__gcc_personality_v0",
2341 "__gxx_personality_v0",
2342 "__gcj_personality_v0",
2343 "__gnu_objc_personality_v0",
2347 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2350 for (k = 0; personality[k]; k++)
2351 if (lookup_minimal_symbol_by_pc_name
2352 (pc, personality[k], objfile))
2354 gnu_personality = 1;
2359 /* If so, the next word contains a word count in the high
2360 byte, followed by the same unwind instructions as the
2361 pre-defined forms. */
2363 && addr + 4 <= extab_vma + extab_size)
2365 word = bfd_h_get_32 (objfile->obfd,
2366 extab_data + addr - extab_vma);
2369 n_words = ((word >> 24) & 0xff);
2375 /* Sanity check address. */
2377 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2378 n_words = n_bytes = 0;
2380 /* The unwind instructions reside in WORD (only the N_BYTES least
2381 significant bytes are valid), followed by N_WORDS words in the
2382 extab section starting at ADDR. */
2383 if (n_bytes || n_words)
2385 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2386 n_bytes + n_words * 4 + 1);
2389 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2393 word = bfd_h_get_32 (objfile->obfd,
2394 extab_data + addr - extab_vma);
2397 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2398 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2399 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2400 *p++ = (gdb_byte) (word & 0xff);
2403 /* Implied "Finish" to terminate the list. */
2407 /* Push entry onto vector. They are guaranteed to always
2408 appear in order of increasing addresses. */
2409 new_exidx_entry.addr = idx;
2410 new_exidx_entry.entry = entry;
2411 VEC_safe_push (arm_exidx_entry_s,
2412 data->section_maps[sec->the_bfd_section->index],
2416 do_cleanups (cleanups);
2419 /* Search for the exception table entry covering MEMADDR. If one is found,
2420 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2421 set *START to the start of the region covered by this entry. */
2424 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2426 struct obj_section *sec;
2428 sec = find_pc_section (memaddr);
2431 struct arm_exidx_data *data;
2432 VEC(arm_exidx_entry_s) *map;
2433 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2436 data = objfile_data (sec->objfile, arm_exidx_data_key);
2439 map = data->section_maps[sec->the_bfd_section->index];
2440 if (!VEC_empty (arm_exidx_entry_s, map))
2442 struct arm_exidx_entry *map_sym;
2444 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2445 arm_compare_exidx_entries);
2447 /* VEC_lower_bound finds the earliest ordered insertion
2448 point. If the following symbol starts at this exact
2449 address, we use that; otherwise, the preceding
2450 exception table entry covers this address. */
2451 if (idx < VEC_length (arm_exidx_entry_s, map))
2453 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2454 if (map_sym->addr == map_key.addr)
2457 *start = map_sym->addr + obj_section_addr (sec);
2458 return map_sym->entry;
2464 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2466 *start = map_sym->addr + obj_section_addr (sec);
2467 return map_sym->entry;
2476 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2477 instruction list from the ARM exception table entry ENTRY, allocate and
2478 return a prologue cache structure describing how to unwind this frame.
2480 Return NULL if the unwinding instruction list contains a "spare",
2481 "reserved" or "refuse to unwind" instruction as defined in section
2482 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2483 for the ARM Architecture" document. */
2485 static struct arm_prologue_cache *
2486 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2491 struct arm_prologue_cache *cache;
2492 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2493 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2499 /* Whenever we reload SP, we actually have to retrieve its
2500 actual value in the current frame. */
2503 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2505 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2506 vsp = get_frame_register_unsigned (this_frame, reg);
2510 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2511 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2517 /* Decode next unwind instruction. */
2520 if ((insn & 0xc0) == 0)
2522 int offset = insn & 0x3f;
2523 vsp += (offset << 2) + 4;
2525 else if ((insn & 0xc0) == 0x40)
2527 int offset = insn & 0x3f;
2528 vsp -= (offset << 2) + 4;
2530 else if ((insn & 0xf0) == 0x80)
2532 int mask = ((insn & 0xf) << 8) | *entry++;
2535 /* The special case of an all-zero mask identifies
2536 "Refuse to unwind". We return NULL to fall back
2537 to the prologue analyzer. */
2541 /* Pop registers r4..r15 under mask. */
2542 for (i = 0; i < 12; i++)
2543 if (mask & (1 << i))
2545 cache->saved_regs[4 + i].addr = vsp;
2549 /* Special-case popping SP -- we need to reload vsp. */
2550 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2553 else if ((insn & 0xf0) == 0x90)
2555 int reg = insn & 0xf;
2557 /* Reserved cases. */
2558 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2561 /* Set SP from another register and mark VSP for reload. */
2562 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2565 else if ((insn & 0xf0) == 0xa0)
2567 int count = insn & 0x7;
2568 int pop_lr = (insn & 0x8) != 0;
2571 /* Pop r4..r[4+count]. */
2572 for (i = 0; i <= count; i++)
2574 cache->saved_regs[4 + i].addr = vsp;
2578 /* If indicated by flag, pop LR as well. */
2581 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2585 else if (insn == 0xb0)
2587 /* We could only have updated PC by popping into it; if so, it
2588 will show up as address. Otherwise, copy LR into PC. */
2589 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2590 cache->saved_regs[ARM_PC_REGNUM]
2591 = cache->saved_regs[ARM_LR_REGNUM];
2596 else if (insn == 0xb1)
2598 int mask = *entry++;
2601 /* All-zero mask and mask >= 16 is "spare". */
2602 if (mask == 0 || mask >= 16)
2605 /* Pop r0..r3 under mask. */
2606 for (i = 0; i < 4; i++)
2607 if (mask & (1 << i))
2609 cache->saved_regs[i].addr = vsp;
2613 else if (insn == 0xb2)
2615 ULONGEST offset = 0;
2620 offset |= (*entry & 0x7f) << shift;
2623 while (*entry++ & 0x80);
2625 vsp += 0x204 + (offset << 2);
2627 else if (insn == 0xb3)
2629 int start = *entry >> 4;
2630 int count = (*entry++) & 0xf;
2633 /* Only registers D0..D15 are valid here. */
2634 if (start + count >= 16)
2637 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2638 for (i = 0; i <= count; i++)
2640 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2644 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2647 else if ((insn & 0xf8) == 0xb8)
2649 int count = insn & 0x7;
2652 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2653 for (i = 0; i <= count; i++)
2655 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2659 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2662 else if (insn == 0xc6)
2664 int start = *entry >> 4;
2665 int count = (*entry++) & 0xf;
2668 /* Only registers WR0..WR15 are valid. */
2669 if (start + count >= 16)
2672 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2673 for (i = 0; i <= count; i++)
2675 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2679 else if (insn == 0xc7)
2681 int mask = *entry++;
2684 /* All-zero mask and mask >= 16 is "spare". */
2685 if (mask == 0 || mask >= 16)
2688 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2689 for (i = 0; i < 4; i++)
2690 if (mask & (1 << i))
2692 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2696 else if ((insn & 0xf8) == 0xc0)
2698 int count = insn & 0x7;
2701 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2702 for (i = 0; i <= count; i++)
2704 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2708 else if (insn == 0xc8)
2710 int start = *entry >> 4;
2711 int count = (*entry++) & 0xf;
2714 /* Only registers D0..D31 are valid. */
2715 if (start + count >= 16)
2718 /* Pop VFP double-precision registers
2719 D[16+start]..D[16+start+count]. */
2720 for (i = 0; i <= count; i++)
2722 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2726 else if (insn == 0xc9)
2728 int start = *entry >> 4;
2729 int count = (*entry++) & 0xf;
2732 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2733 for (i = 0; i <= count; i++)
2735 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2739 else if ((insn & 0xf8) == 0xd0)
2741 int count = insn & 0x7;
2744 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2745 for (i = 0; i <= count; i++)
2747 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2753 /* Everything else is "spare". */
2758 /* If we restore SP from a register, assume this was the frame register.
2759 Otherwise just fall back to SP as frame register. */
2760 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2761 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2763 cache->framereg = ARM_SP_REGNUM;
2765 /* Determine offset to previous frame. */
2767 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2769 /* We already got the previous SP. */
2770 cache->prev_sp = vsp;
2775 /* Unwinding via ARM exception table entries. Note that the sniffer
2776 already computes a filled-in prologue cache, which is then used
2777 with the same arm_prologue_this_id and arm_prologue_prev_register
2778 routines also used for prologue-parsing based unwinding. */
2781 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2782 struct frame_info *this_frame,
2783 void **this_prologue_cache)
2785 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2786 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2787 CORE_ADDR addr_in_block, exidx_region, func_start;
2788 struct arm_prologue_cache *cache;
2791 /* See if we have an ARM exception table entry covering this address. */
2792 addr_in_block = get_frame_address_in_block (this_frame);
2793 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2797 /* The ARM exception table does not describe unwind information
2798 for arbitrary PC values, but is guaranteed to be correct only
2799 at call sites. We have to decide here whether we want to use
2800 ARM exception table information for this frame, or fall back
2801 to using prologue parsing. (Note that if we have DWARF CFI,
2802 this sniffer isn't even called -- CFI is always preferred.)
2804 Before we make this decision, however, we check whether we
2805 actually have *symbol* information for the current frame.
2806 If not, prologue parsing would not work anyway, so we might
2807 as well use the exception table and hope for the best. */
2808 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2812 /* If the next frame is "normal", we are at a call site in this
2813 frame, so exception information is guaranteed to be valid. */
2814 if (get_next_frame (this_frame)
2815 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2818 /* We also assume exception information is valid if we're currently
2819 blocked in a system call. The system library is supposed to
2820 ensure this, so that e.g. pthread cancellation works. */
2821 if (arm_frame_is_thumb (this_frame))
2825 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2826 byte_order_for_code, &insn)
2827 && (insn & 0xff00) == 0xdf00 /* svc */)
2834 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2835 byte_order_for_code, &insn)
2836 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2840 /* Bail out if we don't know that exception information is valid. */
2844 /* The ARM exception index does not mark the *end* of the region
2845 covered by the entry, and some functions will not have any entry.
2846 To correctly recognize the end of the covered region, the linker
2847 should have inserted dummy records with a CANTUNWIND marker.
2849 Unfortunately, current versions of GNU ld do not reliably do
2850 this, and thus we may have found an incorrect entry above.
2851 As a (temporary) sanity check, we only use the entry if it
2852 lies *within* the bounds of the function. Note that this check
2853 might reject perfectly valid entries that just happen to cover
2854 multiple functions; therefore this check ought to be removed
2855 once the linker is fixed. */
2856 if (func_start > exidx_region)
2860 /* Decode the list of unwinding instructions into a prologue cache.
2861 Note that this may fail due to e.g. a "refuse to unwind" code. */
2862 cache = arm_exidx_fill_cache (this_frame, entry);
2866 *this_prologue_cache = cache;
2870 struct frame_unwind arm_exidx_unwind = {
2872 default_frame_unwind_stop_reason,
2873 arm_prologue_this_id,
2874 arm_prologue_prev_register,
2876 arm_exidx_unwind_sniffer
2879 static struct arm_prologue_cache *
2880 arm_make_stub_cache (struct frame_info *this_frame)
2882 struct arm_prologue_cache *cache;
2884 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2885 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2887 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2892 /* Our frame ID for a stub frame is the current SP and LR. */
2895 arm_stub_this_id (struct frame_info *this_frame,
2897 struct frame_id *this_id)
2899 struct arm_prologue_cache *cache;
2901 if (*this_cache == NULL)
2902 *this_cache = arm_make_stub_cache (this_frame);
2903 cache = *this_cache;
2905 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2909 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2910 struct frame_info *this_frame,
2911 void **this_prologue_cache)
2913 CORE_ADDR addr_in_block;
2916 addr_in_block = get_frame_address_in_block (this_frame);
2917 if (in_plt_section (addr_in_block, NULL)
2918 /* We also use the stub winder if the target memory is unreadable
2919 to avoid having the prologue unwinder trying to read it. */
2920 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2926 struct frame_unwind arm_stub_unwind = {
2928 default_frame_unwind_stop_reason,
2930 arm_prologue_prev_register,
2932 arm_stub_unwind_sniffer
2935 /* Put here the code to store, into CACHE->saved_regs, the addresses
2936 of the saved registers of frame described by THIS_FRAME. CACHE is
2939 static struct arm_prologue_cache *
2940 arm_m_exception_cache (struct frame_info *this_frame)
2942 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2943 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2944 struct arm_prologue_cache *cache;
2945 CORE_ADDR unwound_sp;
2948 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2949 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2951 unwound_sp = get_frame_register_unsigned (this_frame,
2954 /* The hardware saves eight 32-bit words, comprising xPSR,
2955 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2956 "B1.5.6 Exception entry behavior" in
2957 "ARMv7-M Architecture Reference Manual". */
2958 cache->saved_regs[0].addr = unwound_sp;
2959 cache->saved_regs[1].addr = unwound_sp + 4;
2960 cache->saved_regs[2].addr = unwound_sp + 8;
2961 cache->saved_regs[3].addr = unwound_sp + 12;
2962 cache->saved_regs[12].addr = unwound_sp + 16;
2963 cache->saved_regs[14].addr = unwound_sp + 20;
2964 cache->saved_regs[15].addr = unwound_sp + 24;
2965 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2967 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2968 aligner between the top of the 32-byte stack frame and the
2969 previous context's stack pointer. */
2970 cache->prev_sp = unwound_sp + 32;
2971 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2972 && (xpsr & (1 << 9)) != 0)
2973 cache->prev_sp += 4;
2978 /* Implementation of function hook 'this_id' in
2979 'struct frame_uwnind'. */
2982 arm_m_exception_this_id (struct frame_info *this_frame,
2984 struct frame_id *this_id)
2986 struct arm_prologue_cache *cache;
2988 if (*this_cache == NULL)
2989 *this_cache = arm_m_exception_cache (this_frame);
2990 cache = *this_cache;
2992 /* Our frame ID for a stub frame is the current SP and LR. */
2993 *this_id = frame_id_build (cache->prev_sp,
2994 get_frame_pc (this_frame));
2997 /* Implementation of function hook 'prev_register' in
2998 'struct frame_uwnind'. */
3000 static struct value *
3001 arm_m_exception_prev_register (struct frame_info *this_frame,
3005 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3006 struct arm_prologue_cache *cache;
3008 if (*this_cache == NULL)
3009 *this_cache = arm_m_exception_cache (this_frame);
3010 cache = *this_cache;
3012 /* The value was already reconstructed into PREV_SP. */
3013 if (prev_regnum == ARM_SP_REGNUM)
3014 return frame_unwind_got_constant (this_frame, prev_regnum,
3017 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3021 /* Implementation of function hook 'sniffer' in
3022 'struct frame_uwnind'. */
3025 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3026 struct frame_info *this_frame,
3027 void **this_prologue_cache)
3029 CORE_ADDR this_pc = get_frame_pc (this_frame);
3031 /* No need to check is_m; this sniffer is only registered for
3032 M-profile architectures. */
3034 /* Exception frames return to one of these magic PCs. Other values
3035 are not defined as of v7-M. See details in "B1.5.8 Exception
3036 return behavior" in "ARMv7-M Architecture Reference Manual". */
3037 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3038 || this_pc == 0xfffffffd)
3044 /* Frame unwinder for M-profile exceptions. */
3046 struct frame_unwind arm_m_exception_unwind =
3049 default_frame_unwind_stop_reason,
3050 arm_m_exception_this_id,
3051 arm_m_exception_prev_register,
3053 arm_m_exception_unwind_sniffer
3057 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3059 struct arm_prologue_cache *cache;
3061 if (*this_cache == NULL)
3062 *this_cache = arm_make_prologue_cache (this_frame);
3063 cache = *this_cache;
3065 return cache->prev_sp - cache->framesize;
3068 struct frame_base arm_normal_base = {
3069 &arm_prologue_unwind,
3070 arm_normal_frame_base,
3071 arm_normal_frame_base,
3072 arm_normal_frame_base
3075 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3076 dummy frame. The frame ID's base needs to match the TOS value
3077 saved by save_dummy_frame_tos() and returned from
3078 arm_push_dummy_call, and the PC needs to match the dummy frame's
3081 static struct frame_id
3082 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3084 return frame_id_build (get_frame_register_unsigned (this_frame,
3086 get_frame_pc (this_frame));
3089 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3090 be used to construct the previous frame's ID, after looking up the
3091 containing function). */
3094 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3097 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3098 return arm_addr_bits_remove (gdbarch, pc);
3102 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3104 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3107 static struct value *
3108 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3111 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3113 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3118 /* The PC is normally copied from the return column, which
3119 describes saves of LR. However, that version may have an
3120 extra bit set to indicate Thumb state. The bit is not
3122 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3123 return frame_unwind_got_constant (this_frame, regnum,
3124 arm_addr_bits_remove (gdbarch, lr));
3127 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3128 cpsr = get_frame_register_unsigned (this_frame, regnum);
3129 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3130 if (IS_THUMB_ADDR (lr))
3134 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3137 internal_error (__FILE__, __LINE__,
3138 _("Unexpected register %d"), regnum);
3143 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3144 struct dwarf2_frame_state_reg *reg,
3145 struct frame_info *this_frame)
3151 reg->how = DWARF2_FRAME_REG_FN;
3152 reg->loc.fn = arm_dwarf2_prev_register;
3155 reg->how = DWARF2_FRAME_REG_CFA;
3160 /* Return true if we are in the function's epilogue, i.e. after the
3161 instruction that destroyed the function's stack frame. */
3164 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3166 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3167 unsigned int insn, insn2;
3168 int found_return = 0, found_stack_adjust = 0;
3169 CORE_ADDR func_start, func_end;
3173 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3176 /* The epilogue is a sequence of instructions along the following lines:
3178 - add stack frame size to SP or FP
3179 - [if frame pointer used] restore SP from FP
3180 - restore registers from SP [may include PC]
3181 - a return-type instruction [if PC wasn't already restored]
3183 In a first pass, we scan forward from the current PC and verify the
3184 instructions we find as compatible with this sequence, ending in a
3187 However, this is not sufficient to distinguish indirect function calls
3188 within a function from indirect tail calls in the epilogue in some cases.
3189 Therefore, if we didn't already find any SP-changing instruction during
3190 forward scan, we add a backward scanning heuristic to ensure we actually
3191 are in the epilogue. */
3194 while (scan_pc < func_end && !found_return)
3196 if (target_read_memory (scan_pc, buf, 2))
3200 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3202 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3204 else if (insn == 0x46f7) /* mov pc, lr */
3206 else if (insn == 0x46bd) /* mov sp, r7 */
3207 found_stack_adjust = 1;
3208 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3209 found_stack_adjust = 1;
3210 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3212 found_stack_adjust = 1;
3213 if (insn & 0x0100) /* <registers> include PC. */
3216 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3218 if (target_read_memory (scan_pc, buf, 2))
3222 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3224 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3226 found_stack_adjust = 1;
3227 if (insn2 & 0x8000) /* <registers> include PC. */
3230 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3231 && (insn2 & 0x0fff) == 0x0b04)
3233 found_stack_adjust = 1;
3234 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3237 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3238 && (insn2 & 0x0e00) == 0x0a00)
3239 found_stack_adjust = 1;
3250 /* Since any instruction in the epilogue sequence, with the possible
3251 exception of return itself, updates the stack pointer, we need to
3252 scan backwards for at most one instruction. Try either a 16-bit or
3253 a 32-bit instruction. This is just a heuristic, so we do not worry
3254 too much about false positives. */
3256 if (!found_stack_adjust)
3258 if (pc - 4 < func_start)
3260 if (target_read_memory (pc - 4, buf, 4))
3263 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3264 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3266 if (insn2 == 0x46bd) /* mov sp, r7 */
3267 found_stack_adjust = 1;
3268 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3269 found_stack_adjust = 1;
3270 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3271 found_stack_adjust = 1;
3272 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3273 found_stack_adjust = 1;
3274 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3275 && (insn2 & 0x0fff) == 0x0b04)
3276 found_stack_adjust = 1;
3277 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3278 && (insn2 & 0x0e00) == 0x0a00)
3279 found_stack_adjust = 1;
3282 return found_stack_adjust;
3285 /* Return true if we are in the function's epilogue, i.e. after the
3286 instruction that destroyed the function's stack frame. */
3289 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3291 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3293 int found_return, found_stack_adjust;
3294 CORE_ADDR func_start, func_end;
3296 if (arm_pc_is_thumb (gdbarch, pc))
3297 return thumb_in_function_epilogue_p (gdbarch, pc);
3299 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3302 /* We are in the epilogue if the previous instruction was a stack
3303 adjustment and the next instruction is a possible return (bx, mov
3304 pc, or pop). We could have to scan backwards to find the stack
3305 adjustment, or forwards to find the return, but this is a decent
3306 approximation. First scan forwards. */
3309 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3310 if (bits (insn, 28, 31) != INST_NV)
3312 if ((insn & 0x0ffffff0) == 0x012fff10)
3315 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3318 else if ((insn & 0x0fff0000) == 0x08bd0000
3319 && (insn & 0x0000c000) != 0)
3320 /* POP (LDMIA), including PC or LR. */
3327 /* Scan backwards. This is just a heuristic, so do not worry about
3328 false positives from mode changes. */
3330 if (pc < func_start + 4)
3333 found_stack_adjust = 0;
3334 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3335 if (bits (insn, 28, 31) != INST_NV)
3337 if ((insn & 0x0df0f000) == 0x0080d000)
3338 /* ADD SP (register or immediate). */
3339 found_stack_adjust = 1;
3340 else if ((insn & 0x0df0f000) == 0x0040d000)
3341 /* SUB SP (register or immediate). */
3342 found_stack_adjust = 1;
3343 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3345 found_stack_adjust = 1;
3346 else if ((insn & 0x0fff0000) == 0x08bd0000)
3348 found_stack_adjust = 1;
3349 else if ((insn & 0x0fff0000) == 0x049d0000)
3350 /* POP of a single register. */
3351 found_stack_adjust = 1;
3354 if (found_stack_adjust)
3361 /* When arguments must be pushed onto the stack, they go on in reverse
3362 order. The code below implements a FILO (stack) to do this. */
3367 struct stack_item *prev;
3371 static struct stack_item *
3372 push_stack_item (struct stack_item *prev, const void *contents, int len)
3374 struct stack_item *si;
3375 si = xmalloc (sizeof (struct stack_item));
3376 si->data = xmalloc (len);
3379 memcpy (si->data, contents, len);
3383 static struct stack_item *
3384 pop_stack_item (struct stack_item *si)
3386 struct stack_item *dead = si;
3394 /* Return the alignment (in bytes) of the given type. */
3397 arm_type_align (struct type *t)
3403 t = check_typedef (t);
3404 switch (TYPE_CODE (t))
3407 /* Should never happen. */
3408 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3412 case TYPE_CODE_ENUM:
3416 case TYPE_CODE_RANGE:
3418 case TYPE_CODE_CHAR:
3419 case TYPE_CODE_BOOL:
3420 return TYPE_LENGTH (t);
3422 case TYPE_CODE_ARRAY:
3423 case TYPE_CODE_COMPLEX:
3424 /* TODO: What about vector types? */
3425 return arm_type_align (TYPE_TARGET_TYPE (t));
3427 case TYPE_CODE_STRUCT:
3428 case TYPE_CODE_UNION:
3430 for (n = 0; n < TYPE_NFIELDS (t); n++)
3432 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3440 /* Possible base types for a candidate for passing and returning in
3443 enum arm_vfp_cprc_base_type
3452 /* The length of one element of base type B. */
3455 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3459 case VFP_CPRC_SINGLE:
3461 case VFP_CPRC_DOUBLE:
3463 case VFP_CPRC_VEC64:
3465 case VFP_CPRC_VEC128:
3468 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3473 /* The character ('s', 'd' or 'q') for the type of VFP register used
3474 for passing base type B. */
3477 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3481 case VFP_CPRC_SINGLE:
3483 case VFP_CPRC_DOUBLE:
3485 case VFP_CPRC_VEC64:
3487 case VFP_CPRC_VEC128:
3490 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3495 /* Determine whether T may be part of a candidate for passing and
3496 returning in VFP registers, ignoring the limit on the total number
3497 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3498 classification of the first valid component found; if it is not
3499 VFP_CPRC_UNKNOWN, all components must have the same classification
3500 as *BASE_TYPE. If it is found that T contains a type not permitted
3501 for passing and returning in VFP registers, a type differently
3502 classified from *BASE_TYPE, or two types differently classified
3503 from each other, return -1, otherwise return the total number of
3504 base-type elements found (possibly 0 in an empty structure or
3505 array). Vectors and complex types are not currently supported,
3506 matching the generic AAPCS support. */
3509 arm_vfp_cprc_sub_candidate (struct type *t,
3510 enum arm_vfp_cprc_base_type *base_type)
3512 t = check_typedef (t);
3513 switch (TYPE_CODE (t))
3516 switch (TYPE_LENGTH (t))
3519 if (*base_type == VFP_CPRC_UNKNOWN)
3520 *base_type = VFP_CPRC_SINGLE;
3521 else if (*base_type != VFP_CPRC_SINGLE)
3526 if (*base_type == VFP_CPRC_UNKNOWN)
3527 *base_type = VFP_CPRC_DOUBLE;
3528 else if (*base_type != VFP_CPRC_DOUBLE)
3537 case TYPE_CODE_ARRAY:
3541 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3544 if (TYPE_LENGTH (t) == 0)
3546 gdb_assert (count == 0);
3549 else if (count == 0)
3551 unitlen = arm_vfp_cprc_unit_length (*base_type);
3552 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3553 return TYPE_LENGTH (t) / unitlen;
3557 case TYPE_CODE_STRUCT:
3562 for (i = 0; i < TYPE_NFIELDS (t); i++)
3564 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3566 if (sub_count == -1)
3570 if (TYPE_LENGTH (t) == 0)
3572 gdb_assert (count == 0);
3575 else if (count == 0)
3577 unitlen = arm_vfp_cprc_unit_length (*base_type);
3578 if (TYPE_LENGTH (t) != unitlen * count)
3583 case TYPE_CODE_UNION:
3588 for (i = 0; i < TYPE_NFIELDS (t); i++)
3590 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3592 if (sub_count == -1)
3594 count = (count > sub_count ? count : sub_count);
3596 if (TYPE_LENGTH (t) == 0)
3598 gdb_assert (count == 0);
3601 else if (count == 0)
3603 unitlen = arm_vfp_cprc_unit_length (*base_type);
3604 if (TYPE_LENGTH (t) != unitlen * count)
3616 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3617 if passed to or returned from a non-variadic function with the VFP
3618 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3619 *BASE_TYPE to the base type for T and *COUNT to the number of
3620 elements of that base type before returning. */
3623 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3626 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3627 int c = arm_vfp_cprc_sub_candidate (t, &b);
3628 if (c <= 0 || c > 4)
3635 /* Return 1 if the VFP ABI should be used for passing arguments to and
3636 returning values from a function of type FUNC_TYPE, 0
3640 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3642 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3643 /* Variadic functions always use the base ABI. Assume that functions
3644 without debug info are not variadic. */
3645 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3647 /* The VFP ABI is only supported as a variant of AAPCS. */
3648 if (tdep->arm_abi != ARM_ABI_AAPCS)
3650 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3653 /* We currently only support passing parameters in integer registers, which
3654 conforms with GCC's default model, and VFP argument passing following
3655 the VFP variant of AAPCS. Several other variants exist and
3656 we should probably support some of them based on the selected ABI. */
3659 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3660 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3661 struct value **args, CORE_ADDR sp, int struct_return,
3662 CORE_ADDR struct_addr)
3664 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3668 struct stack_item *si = NULL;
3671 unsigned vfp_regs_free = (1 << 16) - 1;
3673 /* Determine the type of this function and whether the VFP ABI
3675 ftype = check_typedef (value_type (function));
3676 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3677 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3678 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3680 /* Set the return address. For the ARM, the return breakpoint is
3681 always at BP_ADDR. */
3682 if (arm_pc_is_thumb (gdbarch, bp_addr))
3684 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3686 /* Walk through the list of args and determine how large a temporary
3687 stack is required. Need to take care here as structs may be
3688 passed on the stack, and we have to push them. */
3691 argreg = ARM_A1_REGNUM;
3694 /* The struct_return pointer occupies the first parameter
3695 passing register. */
3699 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3700 gdbarch_register_name (gdbarch, argreg),
3701 paddress (gdbarch, struct_addr));
3702 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3706 for (argnum = 0; argnum < nargs; argnum++)
3709 struct type *arg_type;
3710 struct type *target_type;
3711 enum type_code typecode;
3712 const bfd_byte *val;
3714 enum arm_vfp_cprc_base_type vfp_base_type;
3716 int may_use_core_reg = 1;
3718 arg_type = check_typedef (value_type (args[argnum]));
3719 len = TYPE_LENGTH (arg_type);
3720 target_type = TYPE_TARGET_TYPE (arg_type);
3721 typecode = TYPE_CODE (arg_type);
3722 val = value_contents (args[argnum]);
3724 align = arm_type_align (arg_type);
3725 /* Round alignment up to a whole number of words. */
3726 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3727 /* Different ABIs have different maximum alignments. */
3728 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3730 /* The APCS ABI only requires word alignment. */
3731 align = INT_REGISTER_SIZE;
3735 /* The AAPCS requires at most doubleword alignment. */
3736 if (align > INT_REGISTER_SIZE * 2)
3737 align = INT_REGISTER_SIZE * 2;
3741 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3749 /* Because this is a CPRC it cannot go in a core register or
3750 cause a core register to be skipped for alignment.
3751 Either it goes in VFP registers and the rest of this loop
3752 iteration is skipped for this argument, or it goes on the
3753 stack (and the stack alignment code is correct for this
3755 may_use_core_reg = 0;
3757 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3758 shift = unit_length / 4;
3759 mask = (1 << (shift * vfp_base_count)) - 1;
3760 for (regno = 0; regno < 16; regno += shift)
3761 if (((vfp_regs_free >> regno) & mask) == mask)
3770 vfp_regs_free &= ~(mask << regno);
3771 reg_scaled = regno / shift;
3772 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3773 for (i = 0; i < vfp_base_count; i++)
3777 if (reg_char == 'q')
3778 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3779 val + i * unit_length);
3782 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3783 reg_char, reg_scaled + i);
3784 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3786 regcache_cooked_write (regcache, regnum,
3787 val + i * unit_length);
3794 /* This CPRC could not go in VFP registers, so all VFP
3795 registers are now marked as used. */
3800 /* Push stack padding for dowubleword alignment. */
3801 if (nstack & (align - 1))
3803 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3804 nstack += INT_REGISTER_SIZE;
3807 /* Doubleword aligned quantities must go in even register pairs. */
3808 if (may_use_core_reg
3809 && argreg <= ARM_LAST_ARG_REGNUM
3810 && align > INT_REGISTER_SIZE
3814 /* If the argument is a pointer to a function, and it is a
3815 Thumb function, create a LOCAL copy of the value and set
3816 the THUMB bit in it. */
3817 if (TYPE_CODE_PTR == typecode
3818 && target_type != NULL
3819 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3821 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3822 if (arm_pc_is_thumb (gdbarch, regval))
3824 bfd_byte *copy = alloca (len);
3825 store_unsigned_integer (copy, len, byte_order,
3826 MAKE_THUMB_ADDR (regval));
3831 /* Copy the argument to general registers or the stack in
3832 register-sized pieces. Large arguments are split between
3833 registers and stack. */
3836 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3838 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3840 /* The argument is being passed in a general purpose
3843 = extract_unsigned_integer (val, partial_len, byte_order);
3844 if (byte_order == BFD_ENDIAN_BIG)
3845 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3847 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3849 gdbarch_register_name
3851 phex (regval, INT_REGISTER_SIZE));
3852 regcache_cooked_write_unsigned (regcache, argreg, regval);
3857 /* Push the arguments onto the stack. */
3859 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3861 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3862 nstack += INT_REGISTER_SIZE;
3869 /* If we have an odd number of words to push, then decrement the stack
3870 by one word now, so first stack argument will be dword aligned. */
3877 write_memory (sp, si->data, si->len);
3878 si = pop_stack_item (si);
3881 /* Finally, update teh SP register. */
3882 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3888 /* Always align the frame to an 8-byte boundary. This is required on
3889 some platforms and harmless on the rest. */
3892 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3894 /* Align the stack to eight bytes. */
3895 return sp & ~ (CORE_ADDR) 7;
3899 print_fpu_flags (int flags)
3901 if (flags & (1 << 0))
3902 fputs ("IVO ", stdout);
3903 if (flags & (1 << 1))
3904 fputs ("DVZ ", stdout);
3905 if (flags & (1 << 2))
3906 fputs ("OFL ", stdout);
3907 if (flags & (1 << 3))
3908 fputs ("UFL ", stdout);
3909 if (flags & (1 << 4))
3910 fputs ("INX ", stdout);
3914 /* Print interesting information about the floating point processor
3915 (if present) or emulator. */
3917 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3918 struct frame_info *frame, const char *args)
3920 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3923 type = (status >> 24) & 127;
3924 if (status & (1 << 31))
3925 printf (_("Hardware FPU type %d\n"), type);
3927 printf (_("Software FPU type %d\n"), type);
3928 /* i18n: [floating point unit] mask */
3929 fputs (_("mask: "), stdout);
3930 print_fpu_flags (status >> 16);
3931 /* i18n: [floating point unit] flags */
3932 fputs (_("flags: "), stdout);
3933 print_fpu_flags (status);
3936 /* Construct the ARM extended floating point type. */
3937 static struct type *
3938 arm_ext_type (struct gdbarch *gdbarch)
3940 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3942 if (!tdep->arm_ext_type)
3944 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3945 floatformats_arm_ext);
3947 return tdep->arm_ext_type;
3950 static struct type *
3951 arm_neon_double_type (struct gdbarch *gdbarch)
3953 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3955 if (tdep->neon_double_type == NULL)
3957 struct type *t, *elem;
3959 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3961 elem = builtin_type (gdbarch)->builtin_uint8;
3962 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3963 elem = builtin_type (gdbarch)->builtin_uint16;
3964 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3965 elem = builtin_type (gdbarch)->builtin_uint32;
3966 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3967 elem = builtin_type (gdbarch)->builtin_uint64;
3968 append_composite_type_field (t, "u64", elem);
3969 elem = builtin_type (gdbarch)->builtin_float;
3970 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3971 elem = builtin_type (gdbarch)->builtin_double;
3972 append_composite_type_field (t, "f64", elem);
3974 TYPE_VECTOR (t) = 1;
3975 TYPE_NAME (t) = "neon_d";
3976 tdep->neon_double_type = t;
3979 return tdep->neon_double_type;
3982 /* FIXME: The vector types are not correctly ordered on big-endian
3983 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3984 bits of d0 - regardless of what unit size is being held in d0. So
3985 the offset of the first uint8 in d0 is 7, but the offset of the
3986 first float is 4. This code works as-is for little-endian
3989 static struct type *
3990 arm_neon_quad_type (struct gdbarch *gdbarch)
3992 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3994 if (tdep->neon_quad_type == NULL)
3996 struct type *t, *elem;
3998 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4000 elem = builtin_type (gdbarch)->builtin_uint8;
4001 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4002 elem = builtin_type (gdbarch)->builtin_uint16;
4003 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4004 elem = builtin_type (gdbarch)->builtin_uint32;
4005 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4006 elem = builtin_type (gdbarch)->builtin_uint64;
4007 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4008 elem = builtin_type (gdbarch)->builtin_float;
4009 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4010 elem = builtin_type (gdbarch)->builtin_double;
4011 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4013 TYPE_VECTOR (t) = 1;
4014 TYPE_NAME (t) = "neon_q";
4015 tdep->neon_quad_type = t;
4018 return tdep->neon_quad_type;
4021 /* Return the GDB type object for the "standard" data type of data in
4024 static struct type *
4025 arm_register_type (struct gdbarch *gdbarch, int regnum)
4027 int num_regs = gdbarch_num_regs (gdbarch);
4029 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4030 && regnum >= num_regs && regnum < num_regs + 32)
4031 return builtin_type (gdbarch)->builtin_float;
4033 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4034 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4035 return arm_neon_quad_type (gdbarch);
4037 /* If the target description has register information, we are only
4038 in this function so that we can override the types of
4039 double-precision registers for NEON. */
4040 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4042 struct type *t = tdesc_register_type (gdbarch, regnum);
4044 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4045 && TYPE_CODE (t) == TYPE_CODE_FLT
4046 && gdbarch_tdep (gdbarch)->have_neon)
4047 return arm_neon_double_type (gdbarch);
4052 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4054 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4055 return builtin_type (gdbarch)->builtin_void;
4057 return arm_ext_type (gdbarch);
4059 else if (regnum == ARM_SP_REGNUM)
4060 return builtin_type (gdbarch)->builtin_data_ptr;
4061 else if (regnum == ARM_PC_REGNUM)
4062 return builtin_type (gdbarch)->builtin_func_ptr;
4063 else if (regnum >= ARRAY_SIZE (arm_register_names))
4064 /* These registers are only supported on targets which supply
4065 an XML description. */
4066 return builtin_type (gdbarch)->builtin_int0;
4068 return builtin_type (gdbarch)->builtin_uint32;
4071 /* Map a DWARF register REGNUM onto the appropriate GDB register
4075 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4077 /* Core integer regs. */
4078 if (reg >= 0 && reg <= 15)
4081 /* Legacy FPA encoding. These were once used in a way which
4082 overlapped with VFP register numbering, so their use is
4083 discouraged, but GDB doesn't support the ARM toolchain
4084 which used them for VFP. */
4085 if (reg >= 16 && reg <= 23)
4086 return ARM_F0_REGNUM + reg - 16;
4088 /* New assignments for the FPA registers. */
4089 if (reg >= 96 && reg <= 103)
4090 return ARM_F0_REGNUM + reg - 96;
4092 /* WMMX register assignments. */
4093 if (reg >= 104 && reg <= 111)
4094 return ARM_WCGR0_REGNUM + reg - 104;
4096 if (reg >= 112 && reg <= 127)
4097 return ARM_WR0_REGNUM + reg - 112;
4099 if (reg >= 192 && reg <= 199)
4100 return ARM_WC0_REGNUM + reg - 192;
4102 /* VFP v2 registers. A double precision value is actually
4103 in d1 rather than s2, but the ABI only defines numbering
4104 for the single precision registers. This will "just work"
4105 in GDB for little endian targets (we'll read eight bytes,
4106 starting in s0 and then progressing to s1), but will be
4107 reversed on big endian targets with VFP. This won't
4108 be a problem for the new Neon quad registers; you're supposed
4109 to use DW_OP_piece for those. */
4110 if (reg >= 64 && reg <= 95)
4114 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4115 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4119 /* VFP v3 / Neon registers. This range is also used for VFP v2
4120 registers, except that it now describes d0 instead of s0. */
4121 if (reg >= 256 && reg <= 287)
4125 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4126 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4133 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4135 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4138 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4140 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4141 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4143 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4144 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4146 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4147 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4149 if (reg < NUM_GREGS)
4150 return SIM_ARM_R0_REGNUM + reg;
4153 if (reg < NUM_FREGS)
4154 return SIM_ARM_FP0_REGNUM + reg;
4157 if (reg < NUM_SREGS)
4158 return SIM_ARM_FPS_REGNUM + reg;
4161 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4164 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4165 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4166 It is thought that this is is the floating-point register format on
4167 little-endian systems. */
4170 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4171 void *dbl, int endianess)
4175 if (endianess == BFD_ENDIAN_BIG)
4176 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4178 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4180 floatformat_from_doublest (fmt, &d, dbl);
4184 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4189 floatformat_to_doublest (fmt, ptr, &d);
4190 if (endianess == BFD_ENDIAN_BIG)
4191 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4193 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4198 condition_true (unsigned long cond, unsigned long status_reg)
4200 if (cond == INST_AL || cond == INST_NV)
4206 return ((status_reg & FLAG_Z) != 0);
4208 return ((status_reg & FLAG_Z) == 0);
4210 return ((status_reg & FLAG_C) != 0);
4212 return ((status_reg & FLAG_C) == 0);
4214 return ((status_reg & FLAG_N) != 0);
4216 return ((status_reg & FLAG_N) == 0);
4218 return ((status_reg & FLAG_V) != 0);
4220 return ((status_reg & FLAG_V) == 0);
4222 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4224 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4226 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4228 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4230 return (((status_reg & FLAG_Z) == 0)
4231 && (((status_reg & FLAG_N) == 0)
4232 == ((status_reg & FLAG_V) == 0)));
4234 return (((status_reg & FLAG_Z) != 0)
4235 || (((status_reg & FLAG_N) == 0)
4236 != ((status_reg & FLAG_V) == 0)));
4241 static unsigned long
4242 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4243 unsigned long pc_val, unsigned long status_reg)
4245 unsigned long res, shift;
4246 int rm = bits (inst, 0, 3);
4247 unsigned long shifttype = bits (inst, 5, 6);
4251 int rs = bits (inst, 8, 11);
4252 shift = (rs == 15 ? pc_val + 8
4253 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4256 shift = bits (inst, 7, 11);
4258 res = (rm == ARM_PC_REGNUM
4259 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4260 : get_frame_register_unsigned (frame, rm));
4265 res = shift >= 32 ? 0 : res << shift;
4269 res = shift >= 32 ? 0 : res >> shift;
4275 res = ((res & 0x80000000L)
4276 ? ~((~res) >> shift) : res >> shift);
4279 case 3: /* ROR/RRX */
4282 res = (res >> 1) | (carry ? 0x80000000L : 0);
4284 res = (res >> shift) | (res << (32 - shift));
4288 return res & 0xffffffff;
4291 /* Return number of 1-bits in VAL. */
4294 bitcount (unsigned long val)
4297 for (nbits = 0; val != 0; nbits++)
4298 val &= val - 1; /* Delete rightmost 1-bit in val. */
4302 /* Return the size in bytes of the complete Thumb instruction whose
4303 first halfword is INST1. */
4306 thumb_insn_size (unsigned short inst1)
4308 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4315 thumb_advance_itstate (unsigned int itstate)
4317 /* Preserve IT[7:5], the first three bits of the condition. Shift
4318 the upcoming condition flags left by one bit. */
4319 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4321 /* If we have finished the IT block, clear the state. */
4322 if ((itstate & 0x0f) == 0)
4328 /* Find the next PC after the current instruction executes. In some
4329 cases we can not statically determine the answer (see the IT state
4330 handling in this function); in that case, a breakpoint may be
4331 inserted in addition to the returned PC, which will be used to set
4332 another breakpoint by our caller. */
4335 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4337 struct gdbarch *gdbarch = get_frame_arch (frame);
4338 struct address_space *aspace = get_frame_address_space (frame);
4339 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4340 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4341 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4342 unsigned short inst1;
4343 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4344 unsigned long offset;
4345 ULONGEST status, itstate;
4347 nextpc = MAKE_THUMB_ADDR (nextpc);
4348 pc_val = MAKE_THUMB_ADDR (pc_val);
4350 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4352 /* Thumb-2 conditional execution support. There are eight bits in
4353 the CPSR which describe conditional execution state. Once
4354 reconstructed (they're in a funny order), the low five bits
4355 describe the low bit of the condition for each instruction and
4356 how many instructions remain. The high three bits describe the
4357 base condition. One of the low four bits will be set if an IT
4358 block is active. These bits read as zero on earlier
4360 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4361 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4363 /* If-Then handling. On GNU/Linux, where this routine is used, we
4364 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4365 can disable execution of the undefined instruction. So we might
4366 miss the breakpoint if we set it on a skipped conditional
4367 instruction. Because conditional instructions can change the
4368 flags, affecting the execution of further instructions, we may
4369 need to set two breakpoints. */
4371 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4373 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4375 /* An IT instruction. Because this instruction does not
4376 modify the flags, we can accurately predict the next
4377 executed instruction. */
4378 itstate = inst1 & 0x00ff;
4379 pc += thumb_insn_size (inst1);
4381 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4383 inst1 = read_memory_unsigned_integer (pc, 2,
4384 byte_order_for_code);
4385 pc += thumb_insn_size (inst1);
4386 itstate = thumb_advance_itstate (itstate);
4389 return MAKE_THUMB_ADDR (pc);
4391 else if (itstate != 0)
4393 /* We are in a conditional block. Check the condition. */
4394 if (! condition_true (itstate >> 4, status))
4396 /* Advance to the next executed instruction. */
4397 pc += thumb_insn_size (inst1);
4398 itstate = thumb_advance_itstate (itstate);
4400 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4402 inst1 = read_memory_unsigned_integer (pc, 2,
4403 byte_order_for_code);
4404 pc += thumb_insn_size (inst1);
4405 itstate = thumb_advance_itstate (itstate);
4408 return MAKE_THUMB_ADDR (pc);
4410 else if ((itstate & 0x0f) == 0x08)
4412 /* This is the last instruction of the conditional
4413 block, and it is executed. We can handle it normally
4414 because the following instruction is not conditional,
4415 and we must handle it normally because it is
4416 permitted to branch. Fall through. */
4422 /* There are conditional instructions after this one.
4423 If this instruction modifies the flags, then we can
4424 not predict what the next executed instruction will
4425 be. Fortunately, this instruction is architecturally
4426 forbidden to branch; we know it will fall through.
4427 Start by skipping past it. */
4428 pc += thumb_insn_size (inst1);
4429 itstate = thumb_advance_itstate (itstate);
4431 /* Set a breakpoint on the following instruction. */
4432 gdb_assert ((itstate & 0x0f) != 0);
4433 arm_insert_single_step_breakpoint (gdbarch, aspace,
4434 MAKE_THUMB_ADDR (pc));
4435 cond_negated = (itstate >> 4) & 1;
4437 /* Skip all following instructions with the same
4438 condition. If there is a later instruction in the IT
4439 block with the opposite condition, set the other
4440 breakpoint there. If not, then set a breakpoint on
4441 the instruction after the IT block. */
4444 inst1 = read_memory_unsigned_integer (pc, 2,
4445 byte_order_for_code);
4446 pc += thumb_insn_size (inst1);
4447 itstate = thumb_advance_itstate (itstate);
4449 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4451 return MAKE_THUMB_ADDR (pc);
4455 else if (itstate & 0x0f)
4457 /* We are in a conditional block. Check the condition. */
4458 int cond = itstate >> 4;
4460 if (! condition_true (cond, status))
4461 /* Advance to the next instruction. All the 32-bit
4462 instructions share a common prefix. */
4463 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4465 /* Otherwise, handle the instruction normally. */
4468 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4472 /* Fetch the saved PC from the stack. It's stored above
4473 all of the other registers. */
4474 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4475 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4476 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4478 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4480 unsigned long cond = bits (inst1, 8, 11);
4481 if (cond == 0x0f) /* 0x0f = SWI */
4483 struct gdbarch_tdep *tdep;
4484 tdep = gdbarch_tdep (gdbarch);
4486 if (tdep->syscall_next_pc != NULL)
4487 nextpc = tdep->syscall_next_pc (frame);
4490 else if (cond != 0x0f && condition_true (cond, status))
4491 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4493 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4495 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4497 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4499 unsigned short inst2;
4500 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4502 /* Default to the next instruction. */
4504 nextpc = MAKE_THUMB_ADDR (nextpc);
4506 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4508 /* Branches and miscellaneous control instructions. */
4510 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4513 int j1, j2, imm1, imm2;
4515 imm1 = sbits (inst1, 0, 10);
4516 imm2 = bits (inst2, 0, 10);
4517 j1 = bit (inst2, 13);
4518 j2 = bit (inst2, 11);
4520 offset = ((imm1 << 12) + (imm2 << 1));
4521 offset ^= ((!j2) << 22) | ((!j1) << 23);
4523 nextpc = pc_val + offset;
4524 /* For BLX make sure to clear the low bits. */
4525 if (bit (inst2, 12) == 0)
4526 nextpc = nextpc & 0xfffffffc;
4528 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4530 /* SUBS PC, LR, #imm8. */
4531 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4532 nextpc -= inst2 & 0x00ff;
4534 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4536 /* Conditional branch. */
4537 if (condition_true (bits (inst1, 6, 9), status))
4539 int sign, j1, j2, imm1, imm2;
4541 sign = sbits (inst1, 10, 10);
4542 imm1 = bits (inst1, 0, 5);
4543 imm2 = bits (inst2, 0, 10);
4544 j1 = bit (inst2, 13);
4545 j2 = bit (inst2, 11);
4547 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4548 offset += (imm1 << 12) + (imm2 << 1);
4550 nextpc = pc_val + offset;
4554 else if ((inst1 & 0xfe50) == 0xe810)
4556 /* Load multiple or RFE. */
4557 int rn, offset, load_pc = 1;
4559 rn = bits (inst1, 0, 3);
4560 if (bit (inst1, 7) && !bit (inst1, 8))
4563 if (!bit (inst2, 15))
4565 offset = bitcount (inst2) * 4 - 4;
4567 else if (!bit (inst1, 7) && bit (inst1, 8))
4570 if (!bit (inst2, 15))
4574 else if (bit (inst1, 7) && bit (inst1, 8))
4579 else if (!bit (inst1, 7) && !bit (inst1, 8))
4589 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4590 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4593 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4595 /* MOV PC or MOVS PC. */
4596 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4597 nextpc = MAKE_THUMB_ADDR (nextpc);
4599 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4603 int rn, load_pc = 1;
4605 rn = bits (inst1, 0, 3);
4606 base = get_frame_register_unsigned (frame, rn);
4607 if (rn == ARM_PC_REGNUM)
4609 base = (base + 4) & ~(CORE_ADDR) 0x3;
4611 base += bits (inst2, 0, 11);
4613 base -= bits (inst2, 0, 11);
4615 else if (bit (inst1, 7))
4616 base += bits (inst2, 0, 11);
4617 else if (bit (inst2, 11))
4619 if (bit (inst2, 10))
4622 base += bits (inst2, 0, 7);
4624 base -= bits (inst2, 0, 7);
4627 else if ((inst2 & 0x0fc0) == 0x0000)
4629 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4630 base += get_frame_register_unsigned (frame, rm) << shift;
4637 nextpc = get_frame_memory_unsigned (frame, base, 4);
4639 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4642 CORE_ADDR tbl_reg, table, offset, length;
4644 tbl_reg = bits (inst1, 0, 3);
4645 if (tbl_reg == 0x0f)
4646 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4648 table = get_frame_register_unsigned (frame, tbl_reg);
4650 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4651 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4652 nextpc = pc_val + length;
4654 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4657 CORE_ADDR tbl_reg, table, offset, length;
4659 tbl_reg = bits (inst1, 0, 3);
4660 if (tbl_reg == 0x0f)
4661 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4663 table = get_frame_register_unsigned (frame, tbl_reg);
4665 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4666 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4667 nextpc = pc_val + length;
4670 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4672 if (bits (inst1, 3, 6) == 0x0f)
4673 nextpc = UNMAKE_THUMB_ADDR (pc_val);
4675 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4677 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4679 if (bits (inst1, 3, 6) == 0x0f)
4682 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4684 nextpc = MAKE_THUMB_ADDR (nextpc);
4686 else if ((inst1 & 0xf500) == 0xb100)
4689 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4690 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4692 if (bit (inst1, 11) && reg != 0)
4693 nextpc = pc_val + imm;
4694 else if (!bit (inst1, 11) && reg == 0)
4695 nextpc = pc_val + imm;
4700 /* Get the raw next address. PC is the current program counter, in
4701 FRAME, which is assumed to be executing in ARM mode.
4703 The value returned has the execution state of the next instruction
4704 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4705 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4709 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4711 struct gdbarch *gdbarch = get_frame_arch (frame);
4712 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4713 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4714 unsigned long pc_val;
4715 unsigned long this_instr;
4716 unsigned long status;
4719 pc_val = (unsigned long) pc;
4720 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4722 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4723 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4725 if (bits (this_instr, 28, 31) == INST_NV)
4726 switch (bits (this_instr, 24, 27))
4731 /* Branch with Link and change to Thumb. */
4732 nextpc = BranchDest (pc, this_instr);
4733 nextpc |= bit (this_instr, 24) << 1;
4734 nextpc = MAKE_THUMB_ADDR (nextpc);
4740 /* Coprocessor register transfer. */
4741 if (bits (this_instr, 12, 15) == 15)
4742 error (_("Invalid update to pc in instruction"));
4745 else if (condition_true (bits (this_instr, 28, 31), status))
4747 switch (bits (this_instr, 24, 27))
4750 case 0x1: /* data processing */
4754 unsigned long operand1, operand2, result = 0;
4758 if (bits (this_instr, 12, 15) != 15)
4761 if (bits (this_instr, 22, 25) == 0
4762 && bits (this_instr, 4, 7) == 9) /* multiply */
4763 error (_("Invalid update to pc in instruction"));
4765 /* BX <reg>, BLX <reg> */
4766 if (bits (this_instr, 4, 27) == 0x12fff1
4767 || bits (this_instr, 4, 27) == 0x12fff3)
4769 rn = bits (this_instr, 0, 3);
4770 nextpc = ((rn == ARM_PC_REGNUM)
4772 : get_frame_register_unsigned (frame, rn));
4777 /* Multiply into PC. */
4778 c = (status & FLAG_C) ? 1 : 0;
4779 rn = bits (this_instr, 16, 19);
4780 operand1 = ((rn == ARM_PC_REGNUM)
4782 : get_frame_register_unsigned (frame, rn));
4784 if (bit (this_instr, 25))
4786 unsigned long immval = bits (this_instr, 0, 7);
4787 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4788 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4791 else /* operand 2 is a shifted register. */
4792 operand2 = shifted_reg_val (frame, this_instr, c,
4795 switch (bits (this_instr, 21, 24))
4798 result = operand1 & operand2;
4802 result = operand1 ^ operand2;
4806 result = operand1 - operand2;
4810 result = operand2 - operand1;
4814 result = operand1 + operand2;
4818 result = operand1 + operand2 + c;
4822 result = operand1 - operand2 + c;
4826 result = operand2 - operand1 + c;
4832 case 0xb: /* tst, teq, cmp, cmn */
4833 result = (unsigned long) nextpc;
4837 result = operand1 | operand2;
4841 /* Always step into a function. */
4846 result = operand1 & ~operand2;
4854 /* In 26-bit APCS the bottom two bits of the result are
4855 ignored, and we always end up in ARM state. */
4857 nextpc = arm_addr_bits_remove (gdbarch, result);
4865 case 0x5: /* data transfer */
4868 if (bit (this_instr, 20))
4871 if (bits (this_instr, 12, 15) == 15)
4877 if (bit (this_instr, 22))
4878 error (_("Invalid update to pc in instruction"));
4880 /* byte write to PC */
4881 rn = bits (this_instr, 16, 19);
4882 base = ((rn == ARM_PC_REGNUM)
4884 : get_frame_register_unsigned (frame, rn));
4886 if (bit (this_instr, 24))
4889 int c = (status & FLAG_C) ? 1 : 0;
4890 unsigned long offset =
4891 (bit (this_instr, 25)
4892 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4893 : bits (this_instr, 0, 11));
4895 if (bit (this_instr, 23))
4901 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4908 case 0x9: /* block transfer */
4909 if (bit (this_instr, 20))
4912 if (bit (this_instr, 15))
4916 unsigned long rn_val
4917 = get_frame_register_unsigned (frame,
4918 bits (this_instr, 16, 19));
4920 if (bit (this_instr, 23))
4923 unsigned long reglist = bits (this_instr, 0, 14);
4924 offset = bitcount (reglist) * 4;
4925 if (bit (this_instr, 24)) /* pre */
4928 else if (bit (this_instr, 24))
4932 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
4939 case 0xb: /* branch & link */
4940 case 0xa: /* branch */
4942 nextpc = BranchDest (pc, this_instr);
4948 case 0xe: /* coproc ops */
4952 struct gdbarch_tdep *tdep;
4953 tdep = gdbarch_tdep (gdbarch);
4955 if (tdep->syscall_next_pc != NULL)
4956 nextpc = tdep->syscall_next_pc (frame);
4962 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4970 /* Determine next PC after current instruction executes. Will call either
4971 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4972 loop is detected. */
4975 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4979 if (arm_frame_is_thumb (frame))
4981 nextpc = thumb_get_next_pc_raw (frame, pc);
4982 if (nextpc == MAKE_THUMB_ADDR (pc))
4983 error (_("Infinite loop detected"));
4987 nextpc = arm_get_next_pc_raw (frame, pc);
4989 error (_("Infinite loop detected"));
4995 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4996 of the appropriate mode (as encoded in the PC value), even if this
4997 differs from what would be expected according to the symbol tables. */
5000 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
5001 struct address_space *aspace,
5004 struct cleanup *old_chain
5005 = make_cleanup_restore_integer (&arm_override_mode);
5007 arm_override_mode = IS_THUMB_ADDR (pc);
5008 pc = gdbarch_addr_bits_remove (gdbarch, pc);
5010 insert_single_step_breakpoint (gdbarch, aspace, pc);
5012 do_cleanups (old_chain);
5015 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5016 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5017 is found, attempt to step through it. A breakpoint is placed at the end of
5021 thumb_deal_with_atomic_sequence_raw (struct frame_info *frame)
5023 struct gdbarch *gdbarch = get_frame_arch (frame);
5024 struct address_space *aspace = get_frame_address_space (frame);
5025 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5026 CORE_ADDR pc = get_frame_pc (frame);
5027 CORE_ADDR breaks[2] = {-1, -1};
5029 unsigned short insn1, insn2;
5032 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5033 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5034 ULONGEST status, itstate;
5036 /* We currently do not support atomic sequences within an IT block. */
5037 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
5038 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5042 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5043 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5045 if (thumb_insn_size (insn1) != 4)
5048 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5050 if (!((insn1 & 0xfff0) == 0xe850
5051 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5054 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5056 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5058 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5061 if (thumb_insn_size (insn1) != 4)
5063 /* Assume that there is at most one conditional branch in the
5064 atomic sequence. If a conditional branch is found, put a
5065 breakpoint in its destination address. */
5066 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
5068 if (last_breakpoint > 0)
5069 return 0; /* More than one conditional branch found,
5070 fallback to the standard code. */
5072 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
5076 /* We do not support atomic sequences that use any *other*
5077 instructions but conditional branches to change the PC.
5078 Fall back to standard code to avoid losing control of
5080 else if (thumb_instruction_changes_pc (insn1))
5085 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5088 /* Assume that there is at most one conditional branch in the
5089 atomic sequence. If a conditional branch is found, put a
5090 breakpoint in its destination address. */
5091 if ((insn1 & 0xf800) == 0xf000
5092 && (insn2 & 0xd000) == 0x8000
5093 && (insn1 & 0x0380) != 0x0380)
5095 int sign, j1, j2, imm1, imm2;
5096 unsigned int offset;
5098 sign = sbits (insn1, 10, 10);
5099 imm1 = bits (insn1, 0, 5);
5100 imm2 = bits (insn2, 0, 10);
5101 j1 = bit (insn2, 13);
5102 j2 = bit (insn2, 11);
5104 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5105 offset += (imm1 << 12) + (imm2 << 1);
5107 if (last_breakpoint > 0)
5108 return 0; /* More than one conditional branch found,
5109 fallback to the standard code. */
5111 breaks[1] = loc + offset;
5115 /* We do not support atomic sequences that use any *other*
5116 instructions but conditional branches to change the PC.
5117 Fall back to standard code to avoid losing control of
5119 else if (thumb2_instruction_changes_pc (insn1, insn2))
5122 /* If we find a strex{,b,h,d}, we're done. */
5123 if ((insn1 & 0xfff0) == 0xe840
5124 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5129 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5130 if (insn_count == atomic_sequence_length)
5133 /* Insert a breakpoint right after the end of the atomic sequence. */
5136 /* Check for duplicated breakpoints. Check also for a breakpoint
5137 placed (branch instruction's destination) anywhere in sequence. */
5139 && (breaks[1] == breaks[0]
5140 || (breaks[1] >= pc && breaks[1] < loc)))
5141 last_breakpoint = 0;
5143 /* Effectively inserts the breakpoints. */
5144 for (index = 0; index <= last_breakpoint; index++)
5145 arm_insert_single_step_breakpoint (gdbarch, aspace,
5146 MAKE_THUMB_ADDR (breaks[index]));
5152 arm_deal_with_atomic_sequence_raw (struct frame_info *frame)
5154 struct gdbarch *gdbarch = get_frame_arch (frame);
5155 struct address_space *aspace = get_frame_address_space (frame);
5156 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5157 CORE_ADDR pc = get_frame_pc (frame);
5158 CORE_ADDR breaks[2] = {-1, -1};
5163 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5164 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5166 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5167 Note that we do not currently support conditionally executed atomic
5169 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5171 if ((insn & 0xff9000f0) != 0xe1900090)
5174 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5176 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5178 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5181 /* Assume that there is at most one conditional branch in the atomic
5182 sequence. If a conditional branch is found, put a breakpoint in
5183 its destination address. */
5184 if (bits (insn, 24, 27) == 0xa)
5186 if (last_breakpoint > 0)
5187 return 0; /* More than one conditional branch found, fallback
5188 to the standard single-step code. */
5190 breaks[1] = BranchDest (loc - 4, insn);
5194 /* We do not support atomic sequences that use any *other* instructions
5195 but conditional branches to change the PC. Fall back to standard
5196 code to avoid losing control of execution. */
5197 else if (arm_instruction_changes_pc (insn))
5200 /* If we find a strex{,b,h,d}, we're done. */
5201 if ((insn & 0xff9000f0) == 0xe1800090)
5205 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5206 if (insn_count == atomic_sequence_length)
5209 /* Insert a breakpoint right after the end of the atomic sequence. */
5212 /* Check for duplicated breakpoints. Check also for a breakpoint
5213 placed (branch instruction's destination) anywhere in sequence. */
5215 && (breaks[1] == breaks[0]
5216 || (breaks[1] >= pc && breaks[1] < loc)))
5217 last_breakpoint = 0;
5219 /* Effectively inserts the breakpoints. */
5220 for (index = 0; index <= last_breakpoint; index++)
5221 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5227 arm_deal_with_atomic_sequence (struct frame_info *frame)
5229 if (arm_frame_is_thumb (frame))
5230 return thumb_deal_with_atomic_sequence_raw (frame);
5232 return arm_deal_with_atomic_sequence_raw (frame);
5235 /* single_step() is called just before we want to resume the inferior,
5236 if we want to single-step it but there is no hardware or kernel
5237 single-step support. We find the target of the coming instruction
5238 and breakpoint it. */
5241 arm_software_single_step (struct frame_info *frame)
5243 struct gdbarch *gdbarch = get_frame_arch (frame);
5244 struct address_space *aspace = get_frame_address_space (frame);
5247 if (arm_deal_with_atomic_sequence (frame))
5250 next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
5251 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5256 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5257 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5258 NULL if an error occurs. BUF is freed. */
5261 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5262 int old_len, int new_len)
5265 int bytes_to_read = new_len - old_len;
5267 new_buf = xmalloc (new_len);
5268 memcpy (new_buf + bytes_to_read, buf, old_len);
5270 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5278 /* An IT block is at most the 2-byte IT instruction followed by
5279 four 4-byte instructions. The furthest back we must search to
5280 find an IT block that affects the current instruction is thus
5281 2 + 3 * 4 == 14 bytes. */
5282 #define MAX_IT_BLOCK_PREFIX 14
5284 /* Use a quick scan if there are more than this many bytes of
5286 #define IT_SCAN_THRESHOLD 32
5288 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5289 A breakpoint in an IT block may not be hit, depending on the
5292 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5296 CORE_ADDR boundary, func_start;
5298 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5299 int i, any, last_it, last_it_count;
5301 /* If we are using BKPT breakpoints, none of this is necessary. */
5302 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5305 /* ARM mode does not have this problem. */
5306 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5309 /* We are setting a breakpoint in Thumb code that could potentially
5310 contain an IT block. The first step is to find how much Thumb
5311 code there is; we do not need to read outside of known Thumb
5313 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5315 /* Thumb-2 code must have mapping symbols to have a chance. */
5318 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5320 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5321 && func_start > boundary)
5322 boundary = func_start;
5324 /* Search for a candidate IT instruction. We have to do some fancy
5325 footwork to distinguish a real IT instruction from the second
5326 half of a 32-bit instruction, but there is no need for that if
5327 there's no candidate. */
5328 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5330 /* No room for an IT instruction. */
5333 buf = xmalloc (buf_len);
5334 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5337 for (i = 0; i < buf_len; i += 2)
5339 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5340 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5352 /* OK, the code bytes before this instruction contain at least one
5353 halfword which resembles an IT instruction. We know that it's
5354 Thumb code, but there are still two possibilities. Either the
5355 halfword really is an IT instruction, or it is the second half of
5356 a 32-bit Thumb instruction. The only way we can tell is to
5357 scan forwards from a known instruction boundary. */
5358 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5362 /* There's a lot of code before this instruction. Start with an
5363 optimistic search; it's easy to recognize halfwords that can
5364 not be the start of a 32-bit instruction, and use that to
5365 lock on to the instruction boundaries. */
5366 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5369 buf_len = IT_SCAN_THRESHOLD;
5372 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5374 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5375 if (thumb_insn_size (inst1) == 2)
5382 /* At this point, if DEFINITE, BUF[I] is the first place we
5383 are sure that we know the instruction boundaries, and it is far
5384 enough from BPADDR that we could not miss an IT instruction
5385 affecting BPADDR. If ! DEFINITE, give up - start from a
5389 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5393 buf_len = bpaddr - boundary;
5399 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5402 buf_len = bpaddr - boundary;
5406 /* Scan forwards. Find the last IT instruction before BPADDR. */
5411 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5413 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5418 else if (inst1 & 0x0002)
5420 else if (inst1 & 0x0004)
5425 i += thumb_insn_size (inst1);
5431 /* There wasn't really an IT instruction after all. */
5434 if (last_it_count < 1)
5435 /* It was too far away. */
5438 /* This really is a trouble spot. Move the breakpoint to the IT
5440 return bpaddr - buf_len + last_it;
5443 /* ARM displaced stepping support.
5445 Generally ARM displaced stepping works as follows:
5447 1. When an instruction is to be single-stepped, it is first decoded by
5448 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5449 Depending on the type of instruction, it is then copied to a scratch
5450 location, possibly in a modified form. The copy_* set of functions
5451 performs such modification, as necessary. A breakpoint is placed after
5452 the modified instruction in the scratch space to return control to GDB.
5453 Note in particular that instructions which modify the PC will no longer
5454 do so after modification.
5456 2. The instruction is single-stepped, by setting the PC to the scratch
5457 location address, and resuming. Control returns to GDB when the
5460 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5461 function used for the current instruction. This function's job is to
5462 put the CPU/memory state back to what it would have been if the
5463 instruction had been executed unmodified in its original location. */
5465 /* NOP instruction (mov r0, r0). */
5466 #define ARM_NOP 0xe1a00000
5467 #define THUMB_NOP 0x4600
5469 /* Helper for register reads for displaced stepping. In particular, this
5470 returns the PC as it would be seen by the instruction at its original
5474 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5478 CORE_ADDR from = dsc->insn_addr;
5480 if (regno == ARM_PC_REGNUM)
5482 /* Compute pipeline offset:
5483 - When executing an ARM instruction, PC reads as the address of the
5484 current instruction plus 8.
5485 - When executing a Thumb instruction, PC reads as the address of the
5486 current instruction plus 4. */
5493 if (debug_displaced)
5494 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5495 (unsigned long) from);
5496 return (ULONGEST) from;
5500 regcache_cooked_read_unsigned (regs, regno, &ret);
5501 if (debug_displaced)
5502 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5503 regno, (unsigned long) ret);
5509 displaced_in_arm_mode (struct regcache *regs)
5512 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5514 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5516 return (ps & t_bit) == 0;
5519 /* Write to the PC as from a branch instruction. */
5522 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5526 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5527 architecture versions < 6. */
5528 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5529 val & ~(ULONGEST) 0x3);
5531 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5532 val & ~(ULONGEST) 0x1);
5535 /* Write to the PC as from a branch-exchange instruction. */
5538 bx_write_pc (struct regcache *regs, ULONGEST val)
5541 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5543 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5547 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5548 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5550 else if ((val & 2) == 0)
5552 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5553 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5557 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5558 mode, align dest to 4 bytes). */
5559 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5560 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5561 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5565 /* Write to the PC as if from a load instruction. */
5568 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5571 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5572 bx_write_pc (regs, val);
5574 branch_write_pc (regs, dsc, val);
5577 /* Write to the PC as if from an ALU instruction. */
5580 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5583 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5584 bx_write_pc (regs, val);
5586 branch_write_pc (regs, dsc, val);
5589 /* Helper for writing to registers for displaced stepping. Writing to the PC
5590 has a varying effects depending on the instruction which does the write:
5591 this is controlled by the WRITE_PC argument. */
5594 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5595 int regno, ULONGEST val, enum pc_write_style write_pc)
5597 if (regno == ARM_PC_REGNUM)
5599 if (debug_displaced)
5600 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5601 (unsigned long) val);
5604 case BRANCH_WRITE_PC:
5605 branch_write_pc (regs, dsc, val);
5609 bx_write_pc (regs, val);
5613 load_write_pc (regs, dsc, val);
5617 alu_write_pc (regs, dsc, val);
5620 case CANNOT_WRITE_PC:
5621 warning (_("Instruction wrote to PC in an unexpected way when "
5622 "single-stepping"));
5626 internal_error (__FILE__, __LINE__,
5627 _("Invalid argument to displaced_write_reg"));
5630 dsc->wrote_to_pc = 1;
5634 if (debug_displaced)
5635 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5636 regno, (unsigned long) val);
5637 regcache_cooked_write_unsigned (regs, regno, val);
5641 /* This function is used to concisely determine if an instruction INSN
5642 references PC. Register fields of interest in INSN should have the
5643 corresponding fields of BITMASK set to 0b1111. The function
5644 returns return 1 if any of these fields in INSN reference the PC
5645 (also 0b1111, r15), else it returns 0. */
5648 insn_references_pc (uint32_t insn, uint32_t bitmask)
5650 uint32_t lowbit = 1;
5652 while (bitmask != 0)
5656 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5662 mask = lowbit * 0xf;
5664 if ((insn & mask) == mask)
5673 /* The simplest copy function. Many instructions have the same effect no
5674 matter what address they are executed at: in those cases, use this. */
5677 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5678 const char *iname, struct displaced_step_closure *dsc)
5680 if (debug_displaced)
5681 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5682 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5685 dsc->modinsn[0] = insn;
5691 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5692 uint16_t insn2, const char *iname,
5693 struct displaced_step_closure *dsc)
5695 if (debug_displaced)
5696 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5697 "opcode/class '%s' unmodified\n", insn1, insn2,
5700 dsc->modinsn[0] = insn1;
5701 dsc->modinsn[1] = insn2;
5707 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5710 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5712 struct displaced_step_closure *dsc)
5714 if (debug_displaced)
5715 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5716 "opcode/class '%s' unmodified\n", insn,
5719 dsc->modinsn[0] = insn;
5724 /* Preload instructions with immediate offset. */
5727 cleanup_preload (struct gdbarch *gdbarch,
5728 struct regcache *regs, struct displaced_step_closure *dsc)
5730 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5731 if (!dsc->u.preload.immed)
5732 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5736 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5737 struct displaced_step_closure *dsc, unsigned int rn)
5740 /* Preload instructions:
5742 {pli/pld} [rn, #+/-imm]
5744 {pli/pld} [r0, #+/-imm]. */
5746 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5747 rn_val = displaced_read_reg (regs, dsc, rn);
5748 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5749 dsc->u.preload.immed = 1;
5751 dsc->cleanup = &cleanup_preload;
5755 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5756 struct displaced_step_closure *dsc)
5758 unsigned int rn = bits (insn, 16, 19);
5760 if (!insn_references_pc (insn, 0x000f0000ul))
5761 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5763 if (debug_displaced)
5764 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5765 (unsigned long) insn);
5767 dsc->modinsn[0] = insn & 0xfff0ffff;
5769 install_preload (gdbarch, regs, dsc, rn);
5775 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5776 struct regcache *regs, struct displaced_step_closure *dsc)
5778 unsigned int rn = bits (insn1, 0, 3);
5779 unsigned int u_bit = bit (insn1, 7);
5780 int imm12 = bits (insn2, 0, 11);
5783 if (rn != ARM_PC_REGNUM)
5784 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5786 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5787 PLD (literal) Encoding T1. */
5788 if (debug_displaced)
5789 fprintf_unfiltered (gdb_stdlog,
5790 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5791 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5797 /* Rewrite instruction {pli/pld} PC imm12 into:
5798 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5802 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5804 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5805 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5807 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5809 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5810 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5811 dsc->u.preload.immed = 0;
5813 /* {pli/pld} [r0, r1] */
5814 dsc->modinsn[0] = insn1 & 0xfff0;
5815 dsc->modinsn[1] = 0xf001;
5818 dsc->cleanup = &cleanup_preload;
5822 /* Preload instructions with register offset. */
5825 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5826 struct displaced_step_closure *dsc, unsigned int rn,
5829 ULONGEST rn_val, rm_val;
5831 /* Preload register-offset instructions:
5833 {pli/pld} [rn, rm {, shift}]
5835 {pli/pld} [r0, r1 {, shift}]. */
5837 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5838 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5839 rn_val = displaced_read_reg (regs, dsc, rn);
5840 rm_val = displaced_read_reg (regs, dsc, rm);
5841 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5842 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5843 dsc->u.preload.immed = 0;
5845 dsc->cleanup = &cleanup_preload;
5849 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5850 struct regcache *regs,
5851 struct displaced_step_closure *dsc)
5853 unsigned int rn = bits (insn, 16, 19);
5854 unsigned int rm = bits (insn, 0, 3);
5857 if (!insn_references_pc (insn, 0x000f000ful))
5858 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5860 if (debug_displaced)
5861 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5862 (unsigned long) insn);
5864 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5866 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5870 /* Copy/cleanup coprocessor load and store instructions. */
5873 cleanup_copro_load_store (struct gdbarch *gdbarch,
5874 struct regcache *regs,
5875 struct displaced_step_closure *dsc)
5877 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5879 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5881 if (dsc->u.ldst.writeback)
5882 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5886 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5887 struct displaced_step_closure *dsc,
5888 int writeback, unsigned int rn)
5892 /* Coprocessor load/store instructions:
5894 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5896 {stc/stc2} [r0, #+/-imm].
5898 ldc/ldc2 are handled identically. */
5900 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5901 rn_val = displaced_read_reg (regs, dsc, rn);
5902 /* PC should be 4-byte aligned. */
5903 rn_val = rn_val & 0xfffffffc;
5904 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5906 dsc->u.ldst.writeback = writeback;
5907 dsc->u.ldst.rn = rn;
5909 dsc->cleanup = &cleanup_copro_load_store;
5913 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5914 struct regcache *regs,
5915 struct displaced_step_closure *dsc)
5917 unsigned int rn = bits (insn, 16, 19);
5919 if (!insn_references_pc (insn, 0x000f0000ul))
5920 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5922 if (debug_displaced)
5923 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5924 "load/store insn %.8lx\n", (unsigned long) insn);
5926 dsc->modinsn[0] = insn & 0xfff0ffff;
5928 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5934 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5935 uint16_t insn2, struct regcache *regs,
5936 struct displaced_step_closure *dsc)
5938 unsigned int rn = bits (insn1, 0, 3);
5940 if (rn != ARM_PC_REGNUM)
5941 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5942 "copro load/store", dsc);
5944 if (debug_displaced)
5945 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5946 "load/store insn %.4x%.4x\n", insn1, insn2);
5948 dsc->modinsn[0] = insn1 & 0xfff0;
5949 dsc->modinsn[1] = insn2;
5952 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5953 doesn't support writeback, so pass 0. */
5954 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
5959 /* Clean up branch instructions (actually perform the branch, by setting
5963 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
5964 struct displaced_step_closure *dsc)
5966 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5967 int branch_taken = condition_true (dsc->u.branch.cond, status);
5968 enum pc_write_style write_pc = dsc->u.branch.exchange
5969 ? BX_WRITE_PC : BRANCH_WRITE_PC;
5974 if (dsc->u.branch.link)
5976 /* The value of LR should be the next insn of current one. In order
5977 not to confuse logic hanlding later insn `bx lr', if current insn mode
5978 is Thumb, the bit 0 of LR value should be set to 1. */
5979 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5982 next_insn_addr |= 0x1;
5984 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5988 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5991 /* Copy B/BL/BLX instructions with immediate destinations. */
5994 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
5995 struct displaced_step_closure *dsc,
5996 unsigned int cond, int exchange, int link, long offset)
5998 /* Implement "BL<cond> <label>" as:
6000 Preparation: cond <- instruction condition
6001 Insn: mov r0, r0 (nop)
6002 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6004 B<cond> similar, but don't set r14 in cleanup. */
6006 dsc->u.branch.cond = cond;
6007 dsc->u.branch.link = link;
6008 dsc->u.branch.exchange = exchange;
6010 dsc->u.branch.dest = dsc->insn_addr;
6011 if (link && exchange)
6012 /* For BLX, offset is computed from the Align (PC, 4). */
6013 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6016 dsc->u.branch.dest += 4 + offset;
6018 dsc->u.branch.dest += 8 + offset;
6020 dsc->cleanup = &cleanup_branch;
6023 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
6024 struct regcache *regs, struct displaced_step_closure *dsc)
6026 unsigned int cond = bits (insn, 28, 31);
6027 int exchange = (cond == 0xf);
6028 int link = exchange || bit (insn, 24);
6031 if (debug_displaced)
6032 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
6033 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
6034 (unsigned long) insn);
6036 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6037 then arrange the switch into Thumb mode. */
6038 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
6040 offset = bits (insn, 0, 23) << 2;
6042 if (bit (offset, 25))
6043 offset = offset | ~0x3ffffff;
6045 dsc->modinsn[0] = ARM_NOP;
6047 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6052 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
6053 uint16_t insn2, struct regcache *regs,
6054 struct displaced_step_closure *dsc)
6056 int link = bit (insn2, 14);
6057 int exchange = link && !bit (insn2, 12);
6060 int j1 = bit (insn2, 13);
6061 int j2 = bit (insn2, 11);
6062 int s = sbits (insn1, 10, 10);
6063 int i1 = !(j1 ^ bit (insn1, 10));
6064 int i2 = !(j2 ^ bit (insn1, 10));
6066 if (!link && !exchange) /* B */
6068 offset = (bits (insn2, 0, 10) << 1);
6069 if (bit (insn2, 12)) /* Encoding T4 */
6071 offset |= (bits (insn1, 0, 9) << 12)
6077 else /* Encoding T3 */
6079 offset |= (bits (insn1, 0, 5) << 12)
6083 cond = bits (insn1, 6, 9);
6088 offset = (bits (insn1, 0, 9) << 12);
6089 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6090 offset |= exchange ?
6091 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
6094 if (debug_displaced)
6095 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
6096 "%.4x %.4x with offset %.8lx\n",
6097 link ? (exchange) ? "blx" : "bl" : "b",
6098 insn1, insn2, offset);
6100 dsc->modinsn[0] = THUMB_NOP;
6102 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6106 /* Copy B Thumb instructions. */
6108 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
6109 struct displaced_step_closure *dsc)
6111 unsigned int cond = 0;
6113 unsigned short bit_12_15 = bits (insn, 12, 15);
6114 CORE_ADDR from = dsc->insn_addr;
6116 if (bit_12_15 == 0xd)
6118 /* offset = SignExtend (imm8:0, 32) */
6119 offset = sbits ((insn << 1), 0, 8);
6120 cond = bits (insn, 8, 11);
6122 else if (bit_12_15 == 0xe) /* Encoding T2 */
6124 offset = sbits ((insn << 1), 0, 11);
6128 if (debug_displaced)
6129 fprintf_unfiltered (gdb_stdlog,
6130 "displaced: copying b immediate insn %.4x "
6131 "with offset %d\n", insn, offset);
6133 dsc->u.branch.cond = cond;
6134 dsc->u.branch.link = 0;
6135 dsc->u.branch.exchange = 0;
6136 dsc->u.branch.dest = from + 4 + offset;
6138 dsc->modinsn[0] = THUMB_NOP;
6140 dsc->cleanup = &cleanup_branch;
6145 /* Copy BX/BLX with register-specified destinations. */
6148 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6149 struct displaced_step_closure *dsc, int link,
6150 unsigned int cond, unsigned int rm)
6152 /* Implement {BX,BLX}<cond> <reg>" as:
6154 Preparation: cond <- instruction condition
6155 Insn: mov r0, r0 (nop)
6156 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6158 Don't set r14 in cleanup for BX. */
6160 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6162 dsc->u.branch.cond = cond;
6163 dsc->u.branch.link = link;
6165 dsc->u.branch.exchange = 1;
6167 dsc->cleanup = &cleanup_branch;
6171 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6172 struct regcache *regs, struct displaced_step_closure *dsc)
6174 unsigned int cond = bits (insn, 28, 31);
6177 int link = bit (insn, 5);
6178 unsigned int rm = bits (insn, 0, 3);
6180 if (debug_displaced)
6181 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6182 (unsigned long) insn);
6184 dsc->modinsn[0] = ARM_NOP;
6186 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6191 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6192 struct regcache *regs,
6193 struct displaced_step_closure *dsc)
6195 int link = bit (insn, 7);
6196 unsigned int rm = bits (insn, 3, 6);
6198 if (debug_displaced)
6199 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6200 (unsigned short) insn);
6202 dsc->modinsn[0] = THUMB_NOP;
6204 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6210 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6213 cleanup_alu_imm (struct gdbarch *gdbarch,
6214 struct regcache *regs, struct displaced_step_closure *dsc)
6216 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6217 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6218 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6219 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6223 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6224 struct displaced_step_closure *dsc)
6226 unsigned int rn = bits (insn, 16, 19);
6227 unsigned int rd = bits (insn, 12, 15);
6228 unsigned int op = bits (insn, 21, 24);
6229 int is_mov = (op == 0xd);
6230 ULONGEST rd_val, rn_val;
6232 if (!insn_references_pc (insn, 0x000ff000ul))
6233 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6235 if (debug_displaced)
6236 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6237 "%.8lx\n", is_mov ? "move" : "ALU",
6238 (unsigned long) insn);
6240 /* Instruction is of form:
6242 <op><cond> rd, [rn,] #imm
6246 Preparation: tmp1, tmp2 <- r0, r1;
6248 Insn: <op><cond> r0, r1, #imm
6249 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6252 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6253 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6254 rn_val = displaced_read_reg (regs, dsc, rn);
6255 rd_val = displaced_read_reg (regs, dsc, rd);
6256 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6257 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6261 dsc->modinsn[0] = insn & 0xfff00fff;
6263 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6265 dsc->cleanup = &cleanup_alu_imm;
6271 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6272 uint16_t insn2, struct regcache *regs,
6273 struct displaced_step_closure *dsc)
6275 unsigned int op = bits (insn1, 5, 8);
6276 unsigned int rn, rm, rd;
6277 ULONGEST rd_val, rn_val;
6279 rn = bits (insn1, 0, 3); /* Rn */
6280 rm = bits (insn2, 0, 3); /* Rm */
6281 rd = bits (insn2, 8, 11); /* Rd */
6283 /* This routine is only called for instruction MOV. */
6284 gdb_assert (op == 0x2 && rn == 0xf);
6286 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6287 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6289 if (debug_displaced)
6290 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6291 "ALU", insn1, insn2);
6293 /* Instruction is of form:
6295 <op><cond> rd, [rn,] #imm
6299 Preparation: tmp1, tmp2 <- r0, r1;
6301 Insn: <op><cond> r0, r1, #imm
6302 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6305 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6306 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6307 rn_val = displaced_read_reg (regs, dsc, rn);
6308 rd_val = displaced_read_reg (regs, dsc, rd);
6309 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6310 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6313 dsc->modinsn[0] = insn1;
6314 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6317 dsc->cleanup = &cleanup_alu_imm;
6322 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6325 cleanup_alu_reg (struct gdbarch *gdbarch,
6326 struct regcache *regs, struct displaced_step_closure *dsc)
6331 rd_val = displaced_read_reg (regs, dsc, 0);
6333 for (i = 0; i < 3; i++)
6334 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6336 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6340 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6341 struct displaced_step_closure *dsc,
6342 unsigned int rd, unsigned int rn, unsigned int rm)
6344 ULONGEST rd_val, rn_val, rm_val;
6346 /* Instruction is of form:
6348 <op><cond> rd, [rn,] rm [, <shift>]
6352 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6353 r0, r1, r2 <- rd, rn, rm
6354 Insn: <op><cond> r0, r1, r2 [, <shift>]
6355 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6358 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6359 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6360 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6361 rd_val = displaced_read_reg (regs, dsc, rd);
6362 rn_val = displaced_read_reg (regs, dsc, rn);
6363 rm_val = displaced_read_reg (regs, dsc, rm);
6364 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6365 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6366 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6369 dsc->cleanup = &cleanup_alu_reg;
6373 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6374 struct displaced_step_closure *dsc)
6376 unsigned int op = bits (insn, 21, 24);
6377 int is_mov = (op == 0xd);
6379 if (!insn_references_pc (insn, 0x000ff00ful))
6380 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6382 if (debug_displaced)
6383 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6384 is_mov ? "move" : "ALU", (unsigned long) insn);
6387 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6389 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6391 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6397 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6398 struct regcache *regs,
6399 struct displaced_step_closure *dsc)
6401 unsigned rn, rm, rd;
6403 rd = bits (insn, 3, 6);
6404 rn = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6407 if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6408 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6410 if (debug_displaced)
6411 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n",
6412 "ALU", (unsigned short) insn);
6414 dsc->modinsn[0] = ((insn & 0xff00) | 0x08);
6416 install_alu_reg (gdbarch, regs, dsc, rd, rn, rm);
6421 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6424 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6425 struct regcache *regs,
6426 struct displaced_step_closure *dsc)
6428 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6431 for (i = 0; i < 4; i++)
6432 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6434 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6438 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6439 struct displaced_step_closure *dsc,
6440 unsigned int rd, unsigned int rn, unsigned int rm,
6444 ULONGEST rd_val, rn_val, rm_val, rs_val;
6446 /* Instruction is of form:
6448 <op><cond> rd, [rn,] rm, <shift> rs
6452 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6453 r0, r1, r2, r3 <- rd, rn, rm, rs
6454 Insn: <op><cond> r0, r1, r2, <shift> r3
6456 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6460 for (i = 0; i < 4; i++)
6461 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6463 rd_val = displaced_read_reg (regs, dsc, rd);
6464 rn_val = displaced_read_reg (regs, dsc, rn);
6465 rm_val = displaced_read_reg (regs, dsc, rm);
6466 rs_val = displaced_read_reg (regs, dsc, rs);
6467 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6468 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6469 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6470 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6472 dsc->cleanup = &cleanup_alu_shifted_reg;
6476 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6477 struct regcache *regs,
6478 struct displaced_step_closure *dsc)
6480 unsigned int op = bits (insn, 21, 24);
6481 int is_mov = (op == 0xd);
6482 unsigned int rd, rn, rm, rs;
6484 if (!insn_references_pc (insn, 0x000fff0ful))
6485 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6487 if (debug_displaced)
6488 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6489 "%.8lx\n", is_mov ? "move" : "ALU",
6490 (unsigned long) insn);
6492 rn = bits (insn, 16, 19);
6493 rm = bits (insn, 0, 3);
6494 rs = bits (insn, 8, 11);
6495 rd = bits (insn, 12, 15);
6498 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6500 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6502 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6507 /* Clean up load instructions. */
6510 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6511 struct displaced_step_closure *dsc)
6513 ULONGEST rt_val, rt_val2 = 0, rn_val;
6515 rt_val = displaced_read_reg (regs, dsc, 0);
6516 if (dsc->u.ldst.xfersize == 8)
6517 rt_val2 = displaced_read_reg (regs, dsc, 1);
6518 rn_val = displaced_read_reg (regs, dsc, 2);
6520 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6521 if (dsc->u.ldst.xfersize > 4)
6522 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6523 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6524 if (!dsc->u.ldst.immed)
6525 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6527 /* Handle register writeback. */
6528 if (dsc->u.ldst.writeback)
6529 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6530 /* Put result in right place. */
6531 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6532 if (dsc->u.ldst.xfersize == 8)
6533 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6536 /* Clean up store instructions. */
6539 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6540 struct displaced_step_closure *dsc)
6542 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6544 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6545 if (dsc->u.ldst.xfersize > 4)
6546 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6547 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6548 if (!dsc->u.ldst.immed)
6549 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6550 if (!dsc->u.ldst.restore_r4)
6551 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6554 if (dsc->u.ldst.writeback)
6555 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6558 /* Copy "extra" load/store instructions. These are halfword/doubleword
6559 transfers, which have a different encoding to byte/word transfers. */
6562 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6563 struct regcache *regs, struct displaced_step_closure *dsc)
6565 unsigned int op1 = bits (insn, 20, 24);
6566 unsigned int op2 = bits (insn, 5, 6);
6567 unsigned int rt = bits (insn, 12, 15);
6568 unsigned int rn = bits (insn, 16, 19);
6569 unsigned int rm = bits (insn, 0, 3);
6570 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6571 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6572 int immed = (op1 & 0x4) != 0;
6574 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6576 if (!insn_references_pc (insn, 0x000ff00ful))
6577 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6579 if (debug_displaced)
6580 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6581 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6582 (unsigned long) insn);
6584 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6587 internal_error (__FILE__, __LINE__,
6588 _("copy_extra_ld_st: instruction decode error"));
6590 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6591 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6592 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6594 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6596 rt_val = displaced_read_reg (regs, dsc, rt);
6597 if (bytesize[opcode] == 8)
6598 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6599 rn_val = displaced_read_reg (regs, dsc, rn);
6601 rm_val = displaced_read_reg (regs, dsc, rm);
6603 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6604 if (bytesize[opcode] == 8)
6605 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6606 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6608 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6611 dsc->u.ldst.xfersize = bytesize[opcode];
6612 dsc->u.ldst.rn = rn;
6613 dsc->u.ldst.immed = immed;
6614 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6615 dsc->u.ldst.restore_r4 = 0;
6618 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6620 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6621 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6623 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6625 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6626 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6628 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6633 /* Copy byte/half word/word loads and stores. */
6636 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6637 struct displaced_step_closure *dsc, int load,
6638 int immed, int writeback, int size, int usermode,
6639 int rt, int rm, int rn)
6641 ULONGEST rt_val, rn_val, rm_val = 0;
6643 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6644 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6646 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6648 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6650 rt_val = displaced_read_reg (regs, dsc, rt);
6651 rn_val = displaced_read_reg (regs, dsc, rn);
6653 rm_val = displaced_read_reg (regs, dsc, rm);
6655 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6656 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6658 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6660 dsc->u.ldst.xfersize = size;
6661 dsc->u.ldst.rn = rn;
6662 dsc->u.ldst.immed = immed;
6663 dsc->u.ldst.writeback = writeback;
6665 /* To write PC we can do:
6667 Before this sequence of instructions:
6668 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6669 r2 is the Rn value got from dispalced_read_reg.
6671 Insn1: push {pc} Write address of STR instruction + offset on stack
6672 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6673 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6674 = addr(Insn1) + offset - addr(Insn3) - 8
6676 Insn4: add r4, r4, #8 r4 = offset - 8
6677 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6679 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6681 Otherwise we don't know what value to write for PC, since the offset is
6682 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6683 of this can be found in Section "Saving from r15" in
6684 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6686 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6691 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6692 uint16_t insn2, struct regcache *regs,
6693 struct displaced_step_closure *dsc, int size)
6695 unsigned int u_bit = bit (insn1, 7);
6696 unsigned int rt = bits (insn2, 12, 15);
6697 int imm12 = bits (insn2, 0, 11);
6700 if (debug_displaced)
6701 fprintf_unfiltered (gdb_stdlog,
6702 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6703 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6709 /* Rewrite instruction LDR Rt imm12 into:
6711 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6715 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6718 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6719 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6720 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6722 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6724 pc_val = pc_val & 0xfffffffc;
6726 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6727 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6731 dsc->u.ldst.xfersize = size;
6732 dsc->u.ldst.immed = 0;
6733 dsc->u.ldst.writeback = 0;
6734 dsc->u.ldst.restore_r4 = 0;
6736 /* LDR R0, R2, R3 */
6737 dsc->modinsn[0] = 0xf852;
6738 dsc->modinsn[1] = 0x3;
6741 dsc->cleanup = &cleanup_load;
6747 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6748 uint16_t insn2, struct regcache *regs,
6749 struct displaced_step_closure *dsc,
6750 int writeback, int immed)
6752 unsigned int rt = bits (insn2, 12, 15);
6753 unsigned int rn = bits (insn1, 0, 3);
6754 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6755 /* In LDR (register), there is also a register Rm, which is not allowed to
6756 be PC, so we don't have to check it. */
6758 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6759 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6762 if (debug_displaced)
6763 fprintf_unfiltered (gdb_stdlog,
6764 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6765 rt, rn, insn1, insn2);
6767 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6770 dsc->u.ldst.restore_r4 = 0;
6773 /* ldr[b]<cond> rt, [rn, #imm], etc.
6775 ldr[b]<cond> r0, [r2, #imm]. */
6777 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6778 dsc->modinsn[1] = insn2 & 0x0fff;
6781 /* ldr[b]<cond> rt, [rn, rm], etc.
6783 ldr[b]<cond> r0, [r2, r3]. */
6785 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6786 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6796 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6797 struct regcache *regs,
6798 struct displaced_step_closure *dsc,
6799 int load, int size, int usermode)
6801 int immed = !bit (insn, 25);
6802 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6803 unsigned int rt = bits (insn, 12, 15);
6804 unsigned int rn = bits (insn, 16, 19);
6805 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6807 if (!insn_references_pc (insn, 0x000ff00ful))
6808 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6810 if (debug_displaced)
6811 fprintf_unfiltered (gdb_stdlog,
6812 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6813 load ? (size == 1 ? "ldrb" : "ldr")
6814 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6816 (unsigned long) insn);
6818 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6819 usermode, rt, rm, rn);
6821 if (load || rt != ARM_PC_REGNUM)
6823 dsc->u.ldst.restore_r4 = 0;
6826 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6828 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6829 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6831 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6833 {ldr,str}[b]<cond> r0, [r2, r3]. */
6834 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6838 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6839 dsc->u.ldst.restore_r4 = 1;
6840 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6841 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6842 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6843 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6844 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6848 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6850 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6855 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6860 /* Cleanup LDM instructions with fully-populated register list. This is an
6861 unfortunate corner case: it's impossible to implement correctly by modifying
6862 the instruction. The issue is as follows: we have an instruction,
6866 which we must rewrite to avoid loading PC. A possible solution would be to
6867 do the load in two halves, something like (with suitable cleanup
6871 ldm[id][ab] r8!, {r0-r7}
6873 ldm[id][ab] r8, {r7-r14}
6876 but at present there's no suitable place for <temp>, since the scratch space
6877 is overwritten before the cleanup routine is called. For now, we simply
6878 emulate the instruction. */
6881 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6882 struct displaced_step_closure *dsc)
6884 int inc = dsc->u.block.increment;
6885 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6886 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6887 uint32_t regmask = dsc->u.block.regmask;
6888 int regno = inc ? 0 : 15;
6889 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6890 int exception_return = dsc->u.block.load && dsc->u.block.user
6891 && (regmask & 0x8000) != 0;
6892 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6893 int do_transfer = condition_true (dsc->u.block.cond, status);
6894 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6899 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6900 sensible we can do here. Complain loudly. */
6901 if (exception_return)
6902 error (_("Cannot single-step exception return"));
6904 /* We don't handle any stores here for now. */
6905 gdb_assert (dsc->u.block.load != 0);
6907 if (debug_displaced)
6908 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6909 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6910 dsc->u.block.increment ? "inc" : "dec",
6911 dsc->u.block.before ? "before" : "after");
6918 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6921 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6924 xfer_addr += bump_before;
6926 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6927 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6929 xfer_addr += bump_after;
6931 regmask &= ~(1 << regno);
6934 if (dsc->u.block.writeback)
6935 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6939 /* Clean up an STM which included the PC in the register list. */
6942 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6943 struct displaced_step_closure *dsc)
6945 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6946 int store_executed = condition_true (dsc->u.block.cond, status);
6947 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
6948 CORE_ADDR stm_insn_addr;
6951 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6953 /* If condition code fails, there's nothing else to do. */
6954 if (!store_executed)
6957 if (dsc->u.block.increment)
6959 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6961 if (dsc->u.block.before)
6966 pc_stored_at = dsc->u.block.xfer_addr;
6968 if (dsc->u.block.before)
6972 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
6973 stm_insn_addr = dsc->scratch_base;
6974 offset = pc_val - stm_insn_addr;
6976 if (debug_displaced)
6977 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
6978 "STM instruction\n", offset);
6980 /* Rewrite the stored PC to the proper value for the non-displaced original
6982 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
6983 dsc->insn_addr + offset);
6986 /* Clean up an LDM which includes the PC in the register list. We clumped all
6987 the registers in the transferred list into a contiguous range r0...rX (to
6988 avoid loading PC directly and losing control of the debugged program), so we
6989 must undo that here. */
6992 cleanup_block_load_pc (struct gdbarch *gdbarch,
6993 struct regcache *regs,
6994 struct displaced_step_closure *dsc)
6996 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6997 int load_executed = condition_true (dsc->u.block.cond, status);
6998 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6999 unsigned int regs_loaded = bitcount (mask);
7000 unsigned int num_to_shuffle = regs_loaded, clobbered;
7002 /* The method employed here will fail if the register list is fully populated
7003 (we need to avoid loading PC directly). */
7004 gdb_assert (num_to_shuffle < 16);
7009 clobbered = (1 << num_to_shuffle) - 1;
7011 while (num_to_shuffle > 0)
7013 if ((mask & (1 << write_reg)) != 0)
7015 unsigned int read_reg = num_to_shuffle - 1;
7017 if (read_reg != write_reg)
7019 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
7020 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7021 if (debug_displaced)
7022 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
7023 "loaded register r%d to r%d\n"), read_reg,
7026 else if (debug_displaced)
7027 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
7028 "r%d already in the right place\n"),
7031 clobbered &= ~(1 << write_reg);
7039 /* Restore any registers we scribbled over. */
7040 for (write_reg = 0; clobbered != 0; write_reg++)
7042 if ((clobbered & (1 << write_reg)) != 0)
7044 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7046 if (debug_displaced)
7047 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
7048 "clobbered register r%d\n"), write_reg);
7049 clobbered &= ~(1 << write_reg);
7053 /* Perform register writeback manually. */
7054 if (dsc->u.block.writeback)
7056 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7058 if (dsc->u.block.increment)
7059 new_rn_val += regs_loaded * 4;
7061 new_rn_val -= regs_loaded * 4;
7063 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7068 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7069 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7072 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
7073 struct regcache *regs,
7074 struct displaced_step_closure *dsc)
7076 int load = bit (insn, 20);
7077 int user = bit (insn, 22);
7078 int increment = bit (insn, 23);
7079 int before = bit (insn, 24);
7080 int writeback = bit (insn, 21);
7081 int rn = bits (insn, 16, 19);
7083 /* Block transfers which don't mention PC can be run directly
7085 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
7086 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7088 if (rn == ARM_PC_REGNUM)
7090 warning (_("displaced: Unpredictable LDM or STM with "
7091 "base register r15"));
7092 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7095 if (debug_displaced)
7096 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7097 "%.8lx\n", (unsigned long) insn);
7099 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7100 dsc->u.block.rn = rn;
7102 dsc->u.block.load = load;
7103 dsc->u.block.user = user;
7104 dsc->u.block.increment = increment;
7105 dsc->u.block.before = before;
7106 dsc->u.block.writeback = writeback;
7107 dsc->u.block.cond = bits (insn, 28, 31);
7109 dsc->u.block.regmask = insn & 0xffff;
7113 if ((insn & 0xffff) == 0xffff)
7115 /* LDM with a fully-populated register list. This case is
7116 particularly tricky. Implement for now by fully emulating the
7117 instruction (which might not behave perfectly in all cases, but
7118 these instructions should be rare enough for that not to matter
7120 dsc->modinsn[0] = ARM_NOP;
7122 dsc->cleanup = &cleanup_block_load_all;
7126 /* LDM of a list of registers which includes PC. Implement by
7127 rewriting the list of registers to be transferred into a
7128 contiguous chunk r0...rX before doing the transfer, then shuffling
7129 registers into the correct places in the cleanup routine. */
7130 unsigned int regmask = insn & 0xffff;
7131 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7132 unsigned int to = 0, from = 0, i, new_rn;
7134 for (i = 0; i < num_in_list; i++)
7135 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7137 /* Writeback makes things complicated. We need to avoid clobbering
7138 the base register with one of the registers in our modified
7139 register list, but just using a different register can't work in
7142 ldm r14!, {r0-r13,pc}
7144 which would need to be rewritten as:
7148 but that can't work, because there's no free register for N.
7150 Solve this by turning off the writeback bit, and emulating
7151 writeback manually in the cleanup routine. */
7156 new_regmask = (1 << num_in_list) - 1;
7158 if (debug_displaced)
7159 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7160 "{..., pc}: original reg list %.4x, modified "
7161 "list %.4x\n"), rn, writeback ? "!" : "",
7162 (int) insn & 0xffff, new_regmask);
7164 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7166 dsc->cleanup = &cleanup_block_load_pc;
7171 /* STM of a list of registers which includes PC. Run the instruction
7172 as-is, but out of line: this will store the wrong value for the PC,
7173 so we must manually fix up the memory in the cleanup routine.
7174 Doing things this way has the advantage that we can auto-detect
7175 the offset of the PC write (which is architecture-dependent) in
7176 the cleanup routine. */
7177 dsc->modinsn[0] = insn;
7179 dsc->cleanup = &cleanup_block_store_pc;
7186 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7187 struct regcache *regs,
7188 struct displaced_step_closure *dsc)
7190 int rn = bits (insn1, 0, 3);
7191 int load = bit (insn1, 4);
7192 int writeback = bit (insn1, 5);
7194 /* Block transfers which don't mention PC can be run directly
7196 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7197 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7199 if (rn == ARM_PC_REGNUM)
7201 warning (_("displaced: Unpredictable LDM or STM with "
7202 "base register r15"));
7203 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7204 "unpredictable ldm/stm", dsc);
7207 if (debug_displaced)
7208 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7209 "%.4x%.4x\n", insn1, insn2);
7211 /* Clear bit 13, since it should be always zero. */
7212 dsc->u.block.regmask = (insn2 & 0xdfff);
7213 dsc->u.block.rn = rn;
7215 dsc->u.block.load = load;
7216 dsc->u.block.user = 0;
7217 dsc->u.block.increment = bit (insn1, 7);
7218 dsc->u.block.before = bit (insn1, 8);
7219 dsc->u.block.writeback = writeback;
7220 dsc->u.block.cond = INST_AL;
7221 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7225 if (dsc->u.block.regmask == 0xffff)
7227 /* This branch is impossible to happen. */
7232 unsigned int regmask = dsc->u.block.regmask;
7233 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7234 unsigned int to = 0, from = 0, i, new_rn;
7236 for (i = 0; i < num_in_list; i++)
7237 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7242 new_regmask = (1 << num_in_list) - 1;
7244 if (debug_displaced)
7245 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7246 "{..., pc}: original reg list %.4x, modified "
7247 "list %.4x\n"), rn, writeback ? "!" : "",
7248 (int) dsc->u.block.regmask, new_regmask);
7250 dsc->modinsn[0] = insn1;
7251 dsc->modinsn[1] = (new_regmask & 0xffff);
7254 dsc->cleanup = &cleanup_block_load_pc;
7259 dsc->modinsn[0] = insn1;
7260 dsc->modinsn[1] = insn2;
7262 dsc->cleanup = &cleanup_block_store_pc;
7267 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7268 for Linux, where some SVC instructions must be treated specially. */
7271 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7272 struct displaced_step_closure *dsc)
7274 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7276 if (debug_displaced)
7277 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7278 "%.8lx\n", (unsigned long) resume_addr);
7280 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7284 /* Common copy routine for svc instruciton. */
7287 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7288 struct displaced_step_closure *dsc)
7290 /* Preparation: none.
7291 Insn: unmodified svc.
7292 Cleanup: pc <- insn_addr + insn_size. */
7294 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7296 dsc->wrote_to_pc = 1;
7298 /* Allow OS-specific code to override SVC handling. */
7299 if (dsc->u.svc.copy_svc_os)
7300 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7303 dsc->cleanup = &cleanup_svc;
7309 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7310 struct regcache *regs, struct displaced_step_closure *dsc)
7313 if (debug_displaced)
7314 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7315 (unsigned long) insn);
7317 dsc->modinsn[0] = insn;
7319 return install_svc (gdbarch, regs, dsc);
7323 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7324 struct regcache *regs, struct displaced_step_closure *dsc)
7327 if (debug_displaced)
7328 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7331 dsc->modinsn[0] = insn;
7333 return install_svc (gdbarch, regs, dsc);
7336 /* Copy undefined instructions. */
7339 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7340 struct displaced_step_closure *dsc)
7342 if (debug_displaced)
7343 fprintf_unfiltered (gdb_stdlog,
7344 "displaced: copying undefined insn %.8lx\n",
7345 (unsigned long) insn);
7347 dsc->modinsn[0] = insn;
7353 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7354 struct displaced_step_closure *dsc)
7357 if (debug_displaced)
7358 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7359 "%.4x %.4x\n", (unsigned short) insn1,
7360 (unsigned short) insn2);
7362 dsc->modinsn[0] = insn1;
7363 dsc->modinsn[1] = insn2;
7369 /* Copy unpredictable instructions. */
7372 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7373 struct displaced_step_closure *dsc)
7375 if (debug_displaced)
7376 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7377 "%.8lx\n", (unsigned long) insn);
7379 dsc->modinsn[0] = insn;
7384 /* The decode_* functions are instruction decoding helpers. They mostly follow
7385 the presentation in the ARM ARM. */
7388 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7389 struct regcache *regs,
7390 struct displaced_step_closure *dsc)
7392 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7393 unsigned int rn = bits (insn, 16, 19);
7395 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7396 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7397 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7398 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7399 else if ((op1 & 0x60) == 0x20)
7400 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7401 else if ((op1 & 0x71) == 0x40)
7402 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7404 else if ((op1 & 0x77) == 0x41)
7405 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7406 else if ((op1 & 0x77) == 0x45)
7407 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7408 else if ((op1 & 0x77) == 0x51)
7411 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7413 return arm_copy_unpred (gdbarch, insn, dsc);
7415 else if ((op1 & 0x77) == 0x55)
7416 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7417 else if (op1 == 0x57)
7420 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7421 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7422 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7423 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7424 default: return arm_copy_unpred (gdbarch, insn, dsc);
7426 else if ((op1 & 0x63) == 0x43)
7427 return arm_copy_unpred (gdbarch, insn, dsc);
7428 else if ((op2 & 0x1) == 0x0)
7429 switch (op1 & ~0x80)
7432 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7434 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7435 case 0x71: case 0x75:
7437 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7438 case 0x63: case 0x67: case 0x73: case 0x77:
7439 return arm_copy_unpred (gdbarch, insn, dsc);
7441 return arm_copy_undef (gdbarch, insn, dsc);
7444 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7448 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7449 struct regcache *regs,
7450 struct displaced_step_closure *dsc)
7452 if (bit (insn, 27) == 0)
7453 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7454 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7455 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7458 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7461 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7463 case 0x4: case 0x5: case 0x6: case 0x7:
7464 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7467 switch ((insn & 0xe00000) >> 21)
7469 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7471 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7474 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7477 return arm_copy_undef (gdbarch, insn, dsc);
7482 int rn_f = (bits (insn, 16, 19) == 0xf);
7483 switch ((insn & 0xe00000) >> 21)
7486 /* ldc/ldc2 imm (undefined for rn == pc). */
7487 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7488 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7491 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7493 case 0x4: case 0x5: case 0x6: case 0x7:
7494 /* ldc/ldc2 lit (undefined for rn != pc). */
7495 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7496 : arm_copy_undef (gdbarch, insn, dsc);
7499 return arm_copy_undef (gdbarch, insn, dsc);
7504 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7507 if (bits (insn, 16, 19) == 0xf)
7509 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7511 return arm_copy_undef (gdbarch, insn, dsc);
7515 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7517 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7521 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7523 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7526 return arm_copy_undef (gdbarch, insn, dsc);
7530 /* Decode miscellaneous instructions in dp/misc encoding space. */
7533 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7534 struct regcache *regs,
7535 struct displaced_step_closure *dsc)
7537 unsigned int op2 = bits (insn, 4, 6);
7538 unsigned int op = bits (insn, 21, 22);
7539 unsigned int op1 = bits (insn, 16, 19);
7544 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7547 if (op == 0x1) /* bx. */
7548 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7550 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7552 return arm_copy_undef (gdbarch, insn, dsc);
7556 /* Not really supported. */
7557 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7559 return arm_copy_undef (gdbarch, insn, dsc);
7563 return arm_copy_bx_blx_reg (gdbarch, insn,
7564 regs, dsc); /* blx register. */
7566 return arm_copy_undef (gdbarch, insn, dsc);
7569 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7573 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7575 /* Not really supported. */
7576 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7579 return arm_copy_undef (gdbarch, insn, dsc);
7584 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7585 struct regcache *regs,
7586 struct displaced_step_closure *dsc)
7589 switch (bits (insn, 20, 24))
7592 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7595 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7597 case 0x12: case 0x16:
7598 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7601 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7605 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7607 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7608 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7609 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7610 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7611 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7612 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7613 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7614 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7615 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7616 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7617 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7618 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7619 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7620 /* 2nd arg means "unpriveleged". */
7621 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7625 /* Should be unreachable. */
7630 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7631 struct regcache *regs,
7632 struct displaced_step_closure *dsc)
7634 int a = bit (insn, 25), b = bit (insn, 4);
7635 uint32_t op1 = bits (insn, 20, 24);
7636 int rn_f = bits (insn, 16, 19) == 0xf;
7638 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7639 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7640 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7641 else if ((!a && (op1 & 0x17) == 0x02)
7642 || (a && (op1 & 0x17) == 0x02 && !b))
7643 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7644 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7645 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7646 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7647 else if ((!a && (op1 & 0x17) == 0x03)
7648 || (a && (op1 & 0x17) == 0x03 && !b))
7649 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7650 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7651 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7652 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7653 else if ((!a && (op1 & 0x17) == 0x06)
7654 || (a && (op1 & 0x17) == 0x06 && !b))
7655 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7656 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7657 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7658 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7659 else if ((!a && (op1 & 0x17) == 0x07)
7660 || (a && (op1 & 0x17) == 0x07 && !b))
7661 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7663 /* Should be unreachable. */
7668 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7669 struct displaced_step_closure *dsc)
7671 switch (bits (insn, 20, 24))
7673 case 0x00: case 0x01: case 0x02: case 0x03:
7674 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7676 case 0x04: case 0x05: case 0x06: case 0x07:
7677 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7679 case 0x08: case 0x09: case 0x0a: case 0x0b:
7680 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7681 return arm_copy_unmodified (gdbarch, insn,
7682 "decode/pack/unpack/saturate/reverse", dsc);
7685 if (bits (insn, 5, 7) == 0) /* op2. */
7687 if (bits (insn, 12, 15) == 0xf)
7688 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7690 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7693 return arm_copy_undef (gdbarch, insn, dsc);
7695 case 0x1a: case 0x1b:
7696 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7697 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7699 return arm_copy_undef (gdbarch, insn, dsc);
7701 case 0x1c: case 0x1d:
7702 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7704 if (bits (insn, 0, 3) == 0xf)
7705 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7707 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7710 return arm_copy_undef (gdbarch, insn, dsc);
7712 case 0x1e: case 0x1f:
7713 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7714 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7716 return arm_copy_undef (gdbarch, insn, dsc);
7719 /* Should be unreachable. */
7724 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7725 struct regcache *regs,
7726 struct displaced_step_closure *dsc)
7729 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7731 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7735 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7736 struct regcache *regs,
7737 struct displaced_step_closure *dsc)
7739 unsigned int opcode = bits (insn, 20, 24);
7743 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7744 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7746 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7747 case 0x12: case 0x16:
7748 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7750 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7751 case 0x13: case 0x17:
7752 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7754 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7755 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7756 /* Note: no writeback for these instructions. Bit 25 will always be
7757 zero though (via caller), so the following works OK. */
7758 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7761 /* Should be unreachable. */
7765 /* Decode shifted register instructions. */
7768 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7769 uint16_t insn2, struct regcache *regs,
7770 struct displaced_step_closure *dsc)
7772 /* PC is only allowed to be used in instruction MOV. */
7774 unsigned int op = bits (insn1, 5, 8);
7775 unsigned int rn = bits (insn1, 0, 3);
7777 if (op == 0x2 && rn == 0xf) /* MOV */
7778 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7780 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7781 "dp (shift reg)", dsc);
7785 /* Decode extension register load/store. Exactly the same as
7786 arm_decode_ext_reg_ld_st. */
7789 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7790 uint16_t insn2, struct regcache *regs,
7791 struct displaced_step_closure *dsc)
7793 unsigned int opcode = bits (insn1, 4, 8);
7797 case 0x04: case 0x05:
7798 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7799 "vfp/neon vmov", dsc);
7801 case 0x08: case 0x0c: /* 01x00 */
7802 case 0x0a: case 0x0e: /* 01x10 */
7803 case 0x12: case 0x16: /* 10x10 */
7804 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7805 "vfp/neon vstm/vpush", dsc);
7807 case 0x09: case 0x0d: /* 01x01 */
7808 case 0x0b: case 0x0f: /* 01x11 */
7809 case 0x13: case 0x17: /* 10x11 */
7810 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7811 "vfp/neon vldm/vpop", dsc);
7813 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7814 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7816 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7817 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7820 /* Should be unreachable. */
7825 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7826 struct regcache *regs, struct displaced_step_closure *dsc)
7828 unsigned int op1 = bits (insn, 20, 25);
7829 int op = bit (insn, 4);
7830 unsigned int coproc = bits (insn, 8, 11);
7831 unsigned int rn = bits (insn, 16, 19);
7833 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7834 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7835 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7836 && (coproc & 0xe) != 0xa)
7838 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7839 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7840 && (coproc & 0xe) != 0xa)
7841 /* ldc/ldc2 imm/lit. */
7842 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7843 else if ((op1 & 0x3e) == 0x00)
7844 return arm_copy_undef (gdbarch, insn, dsc);
7845 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7846 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7847 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7848 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7849 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7850 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7851 else if ((op1 & 0x30) == 0x20 && !op)
7853 if ((coproc & 0xe) == 0xa)
7854 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7856 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7858 else if ((op1 & 0x30) == 0x20 && op)
7859 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7860 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7861 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7862 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7863 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7864 else if ((op1 & 0x30) == 0x30)
7865 return arm_copy_svc (gdbarch, insn, regs, dsc);
7867 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7871 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7872 uint16_t insn2, struct regcache *regs,
7873 struct displaced_step_closure *dsc)
7875 unsigned int coproc = bits (insn2, 8, 11);
7876 unsigned int op1 = bits (insn1, 4, 9);
7877 unsigned int bit_5_8 = bits (insn1, 5, 8);
7878 unsigned int bit_9 = bit (insn1, 9);
7879 unsigned int bit_4 = bit (insn1, 4);
7880 unsigned int rn = bits (insn1, 0, 3);
7885 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7886 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7888 else if (bit_5_8 == 0) /* UNDEFINED. */
7889 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7892 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7893 if ((coproc & 0xe) == 0xa)
7894 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7896 else /* coproc is not 101x. */
7898 if (bit_4 == 0) /* STC/STC2. */
7899 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7901 else /* LDC/LDC2 {literal, immeidate}. */
7902 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7908 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7914 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7915 struct displaced_step_closure *dsc, int rd)
7921 Preparation: Rd <- PC
7927 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7928 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7932 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7933 struct displaced_step_closure *dsc,
7934 int rd, unsigned int imm)
7937 /* Encoding T2: ADDS Rd, #imm */
7938 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7940 install_pc_relative (gdbarch, regs, dsc, rd);
7946 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
7947 struct regcache *regs,
7948 struct displaced_step_closure *dsc)
7950 unsigned int rd = bits (insn, 8, 10);
7951 unsigned int imm8 = bits (insn, 0, 7);
7953 if (debug_displaced)
7954 fprintf_unfiltered (gdb_stdlog,
7955 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7958 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7962 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7963 uint16_t insn2, struct regcache *regs,
7964 struct displaced_step_closure *dsc)
7966 unsigned int rd = bits (insn2, 8, 11);
7967 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7968 extract raw immediate encoding rather than computing immediate. When
7969 generating ADD or SUB instruction, we can simply perform OR operation to
7970 set immediate into ADD. */
7971 unsigned int imm_3_8 = insn2 & 0x70ff;
7972 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7974 if (debug_displaced)
7975 fprintf_unfiltered (gdb_stdlog,
7976 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7977 rd, imm_i, imm_3_8, insn1, insn2);
7979 if (bit (insn1, 7)) /* Encoding T2 */
7981 /* Encoding T3: SUB Rd, Rd, #imm */
7982 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7983 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7985 else /* Encoding T3 */
7987 /* Encoding T3: ADD Rd, Rd, #imm */
7988 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7989 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7993 install_pc_relative (gdbarch, regs, dsc, rd);
7999 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
8000 struct regcache *regs,
8001 struct displaced_step_closure *dsc)
8003 unsigned int rt = bits (insn1, 8, 10);
8005 int imm8 = (bits (insn1, 0, 7) << 2);
8006 CORE_ADDR from = dsc->insn_addr;
8012 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8014 Insn: LDR R0, [R2, R3];
8015 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8017 if (debug_displaced)
8018 fprintf_unfiltered (gdb_stdlog,
8019 "displaced: copying thumb ldr r%d [pc #%d]\n"
8022 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8023 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8024 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8025 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8026 /* The assembler calculates the required value of the offset from the
8027 Align(PC,4) value of this instruction to the label. */
8028 pc = pc & 0xfffffffc;
8030 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8031 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8034 dsc->u.ldst.xfersize = 4;
8036 dsc->u.ldst.immed = 0;
8037 dsc->u.ldst.writeback = 0;
8038 dsc->u.ldst.restore_r4 = 0;
8040 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8042 dsc->cleanup = &cleanup_load;
8047 /* Copy Thumb cbnz/cbz insruction. */
8050 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
8051 struct regcache *regs,
8052 struct displaced_step_closure *dsc)
8054 int non_zero = bit (insn1, 11);
8055 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
8056 CORE_ADDR from = dsc->insn_addr;
8057 int rn = bits (insn1, 0, 2);
8058 int rn_val = displaced_read_reg (regs, dsc, rn);
8060 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8061 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8062 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8063 condition is false, let it be, cleanup_branch will do nothing. */
8064 if (dsc->u.branch.cond)
8066 dsc->u.branch.cond = INST_AL;
8067 dsc->u.branch.dest = from + 4 + imm5;
8070 dsc->u.branch.dest = from + 2;
8072 dsc->u.branch.link = 0;
8073 dsc->u.branch.exchange = 0;
8075 if (debug_displaced)
8076 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
8077 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
8078 rn, rn_val, insn1, dsc->u.branch.dest);
8080 dsc->modinsn[0] = THUMB_NOP;
8082 dsc->cleanup = &cleanup_branch;
8086 /* Copy Table Branch Byte/Halfword */
8088 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
8089 uint16_t insn2, struct regcache *regs,
8090 struct displaced_step_closure *dsc)
8092 ULONGEST rn_val, rm_val;
8093 int is_tbh = bit (insn2, 4);
8094 CORE_ADDR halfwords = 0;
8095 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8097 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8098 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8104 target_read_memory (rn_val + 2 * rm_val, buf, 2);
8105 halfwords = extract_unsigned_integer (buf, 2, byte_order);
8111 target_read_memory (rn_val + rm_val, buf, 1);
8112 halfwords = extract_unsigned_integer (buf, 1, byte_order);
8115 if (debug_displaced)
8116 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
8117 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
8118 (unsigned int) rn_val, (unsigned int) rm_val,
8119 (unsigned int) halfwords);
8121 dsc->u.branch.cond = INST_AL;
8122 dsc->u.branch.link = 0;
8123 dsc->u.branch.exchange = 0;
8124 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8126 dsc->cleanup = &cleanup_branch;
8132 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8133 struct displaced_step_closure *dsc)
8136 int val = displaced_read_reg (regs, dsc, 7);
8137 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8140 val = displaced_read_reg (regs, dsc, 8);
8141 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8144 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8149 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8150 struct regcache *regs,
8151 struct displaced_step_closure *dsc)
8153 dsc->u.block.regmask = insn1 & 0x00ff;
8155 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8158 (1) register list is full, that is, r0-r7 are used.
8159 Prepare: tmp[0] <- r8
8161 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8162 MOV r8, r7; Move value of r7 to r8;
8163 POP {r7}; Store PC value into r7.
8165 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8167 (2) register list is not full, supposing there are N registers in
8168 register list (except PC, 0 <= N <= 7).
8169 Prepare: for each i, 0 - N, tmp[i] <- ri.
8171 POP {r0, r1, ...., rN};
8173 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8174 from tmp[] properly.
8176 if (debug_displaced)
8177 fprintf_unfiltered (gdb_stdlog,
8178 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8179 dsc->u.block.regmask, insn1);
8181 if (dsc->u.block.regmask == 0xff)
8183 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8185 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8186 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8187 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8190 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8194 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8195 unsigned int new_regmask, bit = 1;
8196 unsigned int to = 0, from = 0, i, new_rn;
8198 for (i = 0; i < num_in_list + 1; i++)
8199 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8201 new_regmask = (1 << (num_in_list + 1)) - 1;
8203 if (debug_displaced)
8204 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8205 "{..., pc}: original reg list %.4x,"
8206 " modified list %.4x\n"),
8207 (int) dsc->u.block.regmask, new_regmask);
8209 dsc->u.block.regmask |= 0x8000;
8210 dsc->u.block.writeback = 0;
8211 dsc->u.block.cond = INST_AL;
8213 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8215 dsc->cleanup = &cleanup_block_load_pc;
8222 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8223 struct regcache *regs,
8224 struct displaced_step_closure *dsc)
8226 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8227 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8230 /* 16-bit thumb instructions. */
8231 switch (op_bit_12_15)
8233 /* Shift (imme), add, subtract, move and compare. */
8234 case 0: case 1: case 2: case 3:
8235 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8236 "shift/add/sub/mov/cmp",
8240 switch (op_bit_10_11)
8242 case 0: /* Data-processing */
8243 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8247 case 1: /* Special data instructions and branch and exchange. */
8249 unsigned short op = bits (insn1, 7, 9);
8250 if (op == 6 || op == 7) /* BX or BLX */
8251 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8252 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8253 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8255 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8259 default: /* LDR (literal) */
8260 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8263 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8264 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8267 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8268 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8269 else /* Generate SP-relative address */
8270 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8272 case 11: /* Misc 16-bit instructions */
8274 switch (bits (insn1, 8, 11))
8276 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8277 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8279 case 12: case 13: /* POP */
8280 if (bit (insn1, 8)) /* PC is in register list. */
8281 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8283 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8285 case 15: /* If-Then, and hints */
8286 if (bits (insn1, 0, 3))
8287 /* If-Then makes up to four following instructions conditional.
8288 IT instruction itself is not conditional, so handle it as a
8289 common unmodified instruction. */
8290 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8293 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8296 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8301 if (op_bit_10_11 < 2) /* Store multiple registers */
8302 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8303 else /* Load multiple registers */
8304 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8306 case 13: /* Conditional branch and supervisor call */
8307 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8308 err = thumb_copy_b (gdbarch, insn1, dsc);
8310 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8312 case 14: /* Unconditional branch */
8313 err = thumb_copy_b (gdbarch, insn1, dsc);
8320 internal_error (__FILE__, __LINE__,
8321 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8325 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8326 uint16_t insn1, uint16_t insn2,
8327 struct regcache *regs,
8328 struct displaced_step_closure *dsc)
8330 int rt = bits (insn2, 12, 15);
8331 int rn = bits (insn1, 0, 3);
8332 int op1 = bits (insn1, 7, 8);
8335 switch (bits (insn1, 5, 6))
8337 case 0: /* Load byte and memory hints */
8338 if (rt == 0xf) /* PLD/PLI */
8341 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8342 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8344 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8349 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8350 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8353 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8354 "ldrb{reg, immediate}/ldrbt",
8359 case 1: /* Load halfword and memory hints. */
8360 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8361 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8362 "pld/unalloc memhint", dsc);
8366 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8369 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8373 case 2: /* Load word */
8375 int insn2_bit_8_11 = bits (insn2, 8, 11);
8378 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8379 else if (op1 == 0x1) /* Encoding T3 */
8380 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8382 else /* op1 == 0x0 */
8384 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8385 /* LDR (immediate) */
8386 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8387 dsc, bit (insn2, 8), 1);
8388 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8389 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8392 /* LDR (register) */
8393 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8399 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8406 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8407 uint16_t insn2, struct regcache *regs,
8408 struct displaced_step_closure *dsc)
8411 unsigned short op = bit (insn2, 15);
8412 unsigned int op1 = bits (insn1, 11, 12);
8418 switch (bits (insn1, 9, 10))
8423 /* Load/store {dual, execlusive}, table branch. */
8424 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8425 && bits (insn2, 5, 7) == 0)
8426 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8429 /* PC is not allowed to use in load/store {dual, exclusive}
8431 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8432 "load/store dual/ex", dsc);
8434 else /* load/store multiple */
8436 switch (bits (insn1, 7, 8))
8438 case 0: case 3: /* SRS, RFE */
8439 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8442 case 1: case 2: /* LDM/STM/PUSH/POP */
8443 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8450 /* Data-processing (shift register). */
8451 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8454 default: /* Coprocessor instructions. */
8455 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8460 case 2: /* op1 = 2 */
8461 if (op) /* Branch and misc control. */
8463 if (bit (insn2, 14) /* BLX/BL */
8464 || bit (insn2, 12) /* Unconditional branch */
8465 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8466 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8468 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8473 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8475 int op = bits (insn1, 4, 8);
8476 int rn = bits (insn1, 0, 3);
8477 if ((op == 0 || op == 0xa) && rn == 0xf)
8478 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8481 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8484 else /* Data processing (modified immeidate) */
8485 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8489 case 3: /* op1 = 3 */
8490 switch (bits (insn1, 9, 10))
8494 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8496 else /* NEON Load/Store and Store single data item */
8497 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8498 "neon elt/struct load/store",
8501 case 1: /* op1 = 3, bits (9, 10) == 1 */
8502 switch (bits (insn1, 7, 8))
8504 case 0: case 1: /* Data processing (register) */
8505 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8508 case 2: /* Multiply and absolute difference */
8509 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8510 "mul/mua/diff", dsc);
8512 case 3: /* Long multiply and divide */
8513 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8518 default: /* Coprocessor instructions */
8519 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8528 internal_error (__FILE__, __LINE__,
8529 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8534 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8535 CORE_ADDR to, struct regcache *regs,
8536 struct displaced_step_closure *dsc)
8538 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8540 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8542 if (debug_displaced)
8543 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8544 "at %.8lx\n", insn1, (unsigned long) from);
8547 dsc->insn_size = thumb_insn_size (insn1);
8548 if (thumb_insn_size (insn1) == 4)
8551 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8552 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8555 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8559 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8560 CORE_ADDR to, struct regcache *regs,
8561 struct displaced_step_closure *dsc)
8564 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8567 /* Most displaced instructions use a 1-instruction scratch space, so set this
8568 here and override below if/when necessary. */
8570 dsc->insn_addr = from;
8571 dsc->scratch_base = to;
8572 dsc->cleanup = NULL;
8573 dsc->wrote_to_pc = 0;
8575 if (!displaced_in_arm_mode (regs))
8576 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8580 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8581 if (debug_displaced)
8582 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8583 "at %.8lx\n", (unsigned long) insn,
8584 (unsigned long) from);
8586 if ((insn & 0xf0000000) == 0xf0000000)
8587 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8588 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8590 case 0x0: case 0x1: case 0x2: case 0x3:
8591 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8594 case 0x4: case 0x5: case 0x6:
8595 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8599 err = arm_decode_media (gdbarch, insn, dsc);
8602 case 0x8: case 0x9: case 0xa: case 0xb:
8603 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8606 case 0xc: case 0xd: case 0xe: case 0xf:
8607 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8612 internal_error (__FILE__, __LINE__,
8613 _("arm_process_displaced_insn: Instruction decode error"));
8616 /* Actually set up the scratch space for a displaced instruction. */
8619 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8620 CORE_ADDR to, struct displaced_step_closure *dsc)
8622 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8623 unsigned int i, len, offset;
8624 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8625 int size = dsc->is_thumb? 2 : 4;
8626 const unsigned char *bkp_insn;
8629 /* Poke modified instruction(s). */
8630 for (i = 0; i < dsc->numinsns; i++)
8632 if (debug_displaced)
8634 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8636 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8639 fprintf_unfiltered (gdb_stdlog, "%.4x",
8640 (unsigned short)dsc->modinsn[i]);
8642 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8643 (unsigned long) to + offset);
8646 write_memory_unsigned_integer (to + offset, size,
8647 byte_order_for_code,
8652 /* Choose the correct breakpoint instruction. */
8655 bkp_insn = tdep->thumb_breakpoint;
8656 len = tdep->thumb_breakpoint_size;
8660 bkp_insn = tdep->arm_breakpoint;
8661 len = tdep->arm_breakpoint_size;
8664 /* Put breakpoint afterwards. */
8665 write_memory (to + offset, bkp_insn, len);
8667 if (debug_displaced)
8668 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8669 paddress (gdbarch, from), paddress (gdbarch, to));
8672 /* Entry point for copying an instruction into scratch space for displaced
8675 struct displaced_step_closure *
8676 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8677 CORE_ADDR from, CORE_ADDR to,
8678 struct regcache *regs)
8680 struct displaced_step_closure *dsc
8681 = xmalloc (sizeof (struct displaced_step_closure));
8682 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8683 arm_displaced_init_closure (gdbarch, from, to, dsc);
8688 /* Entry point for cleaning things up after a displaced instruction has been
8692 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8693 struct displaced_step_closure *dsc,
8694 CORE_ADDR from, CORE_ADDR to,
8695 struct regcache *regs)
8698 dsc->cleanup (gdbarch, regs, dsc);
8700 if (!dsc->wrote_to_pc)
8701 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8702 dsc->insn_addr + dsc->insn_size);
8706 #include "bfd-in2.h"
8707 #include "libcoff.h"
8710 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8712 struct gdbarch *gdbarch = info->application_data;
8714 if (arm_pc_is_thumb (gdbarch, memaddr))
8716 static asymbol *asym;
8717 static combined_entry_type ce;
8718 static struct coff_symbol_struct csym;
8719 static struct bfd fake_bfd;
8720 static bfd_target fake_target;
8722 if (csym.native == NULL)
8724 /* Create a fake symbol vector containing a Thumb symbol.
8725 This is solely so that the code in print_insn_little_arm()
8726 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8727 the presence of a Thumb symbol and switch to decoding
8728 Thumb instructions. */
8730 fake_target.flavour = bfd_target_coff_flavour;
8731 fake_bfd.xvec = &fake_target;
8732 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8734 csym.symbol.the_bfd = &fake_bfd;
8735 csym.symbol.name = "fake";
8736 asym = (asymbol *) & csym;
8739 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8740 info->symbols = &asym;
8743 info->symbols = NULL;
8745 if (info->endian == BFD_ENDIAN_BIG)
8746 return print_insn_big_arm (memaddr, info);
8748 return print_insn_little_arm (memaddr, info);
8751 /* The following define instruction sequences that will cause ARM
8752 cpu's to take an undefined instruction trap. These are used to
8753 signal a breakpoint to GDB.
8755 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8756 modes. A different instruction is required for each mode. The ARM
8757 cpu's can also be big or little endian. Thus four different
8758 instructions are needed to support all cases.
8760 Note: ARMv4 defines several new instructions that will take the
8761 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8762 not in fact add the new instructions. The new undefined
8763 instructions in ARMv4 are all instructions that had no defined
8764 behaviour in earlier chips. There is no guarantee that they will
8765 raise an exception, but may be treated as NOP's. In practice, it
8766 may only safe to rely on instructions matching:
8768 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8769 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8770 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8772 Even this may only true if the condition predicate is true. The
8773 following use a condition predicate of ALWAYS so it is always TRUE.
8775 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8776 and NetBSD all use a software interrupt rather than an undefined
8777 instruction to force a trap. This can be handled by by the
8778 abi-specific code during establishment of the gdbarch vector. */
8780 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8781 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8782 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8783 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8785 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8786 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8787 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8788 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8790 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8791 the program counter value to determine whether a 16-bit or 32-bit
8792 breakpoint should be used. It returns a pointer to a string of
8793 bytes that encode a breakpoint instruction, stores the length of
8794 the string to *lenptr, and adjusts the program counter (if
8795 necessary) to point to the actual memory location where the
8796 breakpoint should be inserted. */
8798 static const unsigned char *
8799 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8801 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8802 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8804 if (arm_pc_is_thumb (gdbarch, *pcptr))
8806 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8808 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8809 check whether we are replacing a 32-bit instruction. */
8810 if (tdep->thumb2_breakpoint != NULL)
8813 if (target_read_memory (*pcptr, buf, 2) == 0)
8815 unsigned short inst1;
8816 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8817 if (thumb_insn_size (inst1) == 4)
8819 *lenptr = tdep->thumb2_breakpoint_size;
8820 return tdep->thumb2_breakpoint;
8825 *lenptr = tdep->thumb_breakpoint_size;
8826 return tdep->thumb_breakpoint;
8830 *lenptr = tdep->arm_breakpoint_size;
8831 return tdep->arm_breakpoint;
8836 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8839 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8841 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8842 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8843 that this is not confused with a 32-bit ARM breakpoint. */
8847 /* Extract from an array REGBUF containing the (raw) register state a
8848 function return value of type TYPE, and copy that, in virtual
8849 format, into VALBUF. */
8852 arm_extract_return_value (struct type *type, struct regcache *regs,
8855 struct gdbarch *gdbarch = get_regcache_arch (regs);
8856 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8858 if (TYPE_CODE_FLT == TYPE_CODE (type))
8860 switch (gdbarch_tdep (gdbarch)->fp_model)
8864 /* The value is in register F0 in internal format. We need to
8865 extract the raw value and then convert it to the desired
8867 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8869 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8870 convert_from_extended (floatformat_from_type (type), tmpbuf,
8871 valbuf, gdbarch_byte_order (gdbarch));
8875 case ARM_FLOAT_SOFT_FPA:
8876 case ARM_FLOAT_SOFT_VFP:
8877 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8878 not using the VFP ABI code. */
8880 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8881 if (TYPE_LENGTH (type) > 4)
8882 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8883 valbuf + INT_REGISTER_SIZE);
8887 internal_error (__FILE__, __LINE__,
8888 _("arm_extract_return_value: "
8889 "Floating point model not supported"));
8893 else if (TYPE_CODE (type) == TYPE_CODE_INT
8894 || TYPE_CODE (type) == TYPE_CODE_CHAR
8895 || TYPE_CODE (type) == TYPE_CODE_BOOL
8896 || TYPE_CODE (type) == TYPE_CODE_PTR
8897 || TYPE_CODE (type) == TYPE_CODE_REF
8898 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8900 /* If the type is a plain integer, then the access is
8901 straight-forward. Otherwise we have to play around a bit
8903 int len = TYPE_LENGTH (type);
8904 int regno = ARM_A1_REGNUM;
8909 /* By using store_unsigned_integer we avoid having to do
8910 anything special for small big-endian values. */
8911 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8912 store_unsigned_integer (valbuf,
8913 (len > INT_REGISTER_SIZE
8914 ? INT_REGISTER_SIZE : len),
8916 len -= INT_REGISTER_SIZE;
8917 valbuf += INT_REGISTER_SIZE;
8922 /* For a structure or union the behaviour is as if the value had
8923 been stored to word-aligned memory and then loaded into
8924 registers with 32-bit load instruction(s). */
8925 int len = TYPE_LENGTH (type);
8926 int regno = ARM_A1_REGNUM;
8927 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8931 regcache_cooked_read (regs, regno++, tmpbuf);
8932 memcpy (valbuf, tmpbuf,
8933 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8934 len -= INT_REGISTER_SIZE;
8935 valbuf += INT_REGISTER_SIZE;
8941 /* Will a function return an aggregate type in memory or in a
8942 register? Return 0 if an aggregate type can be returned in a
8943 register, 1 if it must be returned in memory. */
8946 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8949 enum type_code code;
8951 CHECK_TYPEDEF (type);
8953 /* In the ARM ABI, "integer" like aggregate types are returned in
8954 registers. For an aggregate type to be integer like, its size
8955 must be less than or equal to INT_REGISTER_SIZE and the
8956 offset of each addressable subfield must be zero. Note that bit
8957 fields are not addressable, and all addressable subfields of
8958 unions always start at offset zero.
8960 This function is based on the behaviour of GCC 2.95.1.
8961 See: gcc/arm.c: arm_return_in_memory() for details.
8963 Note: All versions of GCC before GCC 2.95.2 do not set up the
8964 parameters correctly for a function returning the following
8965 structure: struct { float f;}; This should be returned in memory,
8966 not a register. Richard Earnshaw sent me a patch, but I do not
8967 know of any way to detect if a function like the above has been
8968 compiled with the correct calling convention. */
8970 /* All aggregate types that won't fit in a register must be returned
8972 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8977 /* The AAPCS says all aggregates not larger than a word are returned
8979 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8982 /* The only aggregate types that can be returned in a register are
8983 structs and unions. Arrays must be returned in memory. */
8984 code = TYPE_CODE (type);
8985 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
8990 /* Assume all other aggregate types can be returned in a register.
8991 Run a check for structures, unions and arrays. */
8994 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8997 /* Need to check if this struct/union is "integer" like. For
8998 this to be true, its size must be less than or equal to
8999 INT_REGISTER_SIZE and the offset of each addressable
9000 subfield must be zero. Note that bit fields are not
9001 addressable, and unions always start at offset zero. If any
9002 of the subfields is a floating point type, the struct/union
9003 cannot be an integer type. */
9005 /* For each field in the object, check:
9006 1) Is it FP? --> yes, nRc = 1;
9007 2) Is it addressable (bitpos != 0) and
9008 not packed (bitsize == 0)?
9012 for (i = 0; i < TYPE_NFIELDS (type); i++)
9014 enum type_code field_type_code;
9015 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
9018 /* Is it a floating point type field? */
9019 if (field_type_code == TYPE_CODE_FLT)
9025 /* If bitpos != 0, then we have to care about it. */
9026 if (TYPE_FIELD_BITPOS (type, i) != 0)
9028 /* Bitfields are not addressable. If the field bitsize is
9029 zero, then the field is not packed. Hence it cannot be
9030 a bitfield or any other packed type. */
9031 if (TYPE_FIELD_BITSIZE (type, i) == 0)
9043 /* Write into appropriate registers a function return value of type
9044 TYPE, given in virtual format. */
9047 arm_store_return_value (struct type *type, struct regcache *regs,
9048 const gdb_byte *valbuf)
9050 struct gdbarch *gdbarch = get_regcache_arch (regs);
9051 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9053 if (TYPE_CODE (type) == TYPE_CODE_FLT)
9055 char buf[MAX_REGISTER_SIZE];
9057 switch (gdbarch_tdep (gdbarch)->fp_model)
9061 convert_to_extended (floatformat_from_type (type), buf, valbuf,
9062 gdbarch_byte_order (gdbarch));
9063 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
9066 case ARM_FLOAT_SOFT_FPA:
9067 case ARM_FLOAT_SOFT_VFP:
9068 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9069 not using the VFP ABI code. */
9071 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
9072 if (TYPE_LENGTH (type) > 4)
9073 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
9074 valbuf + INT_REGISTER_SIZE);
9078 internal_error (__FILE__, __LINE__,
9079 _("arm_store_return_value: Floating "
9080 "point model not supported"));
9084 else if (TYPE_CODE (type) == TYPE_CODE_INT
9085 || TYPE_CODE (type) == TYPE_CODE_CHAR
9086 || TYPE_CODE (type) == TYPE_CODE_BOOL
9087 || TYPE_CODE (type) == TYPE_CODE_PTR
9088 || TYPE_CODE (type) == TYPE_CODE_REF
9089 || TYPE_CODE (type) == TYPE_CODE_ENUM)
9091 if (TYPE_LENGTH (type) <= 4)
9093 /* Values of one word or less are zero/sign-extended and
9095 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9096 LONGEST val = unpack_long (type, valbuf);
9098 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
9099 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
9103 /* Integral values greater than one word are stored in consecutive
9104 registers starting with r0. This will always be a multiple of
9105 the regiser size. */
9106 int len = TYPE_LENGTH (type);
9107 int regno = ARM_A1_REGNUM;
9111 regcache_cooked_write (regs, regno++, valbuf);
9112 len -= INT_REGISTER_SIZE;
9113 valbuf += INT_REGISTER_SIZE;
9119 /* For a structure or union the behaviour is as if the value had
9120 been stored to word-aligned memory and then loaded into
9121 registers with 32-bit load instruction(s). */
9122 int len = TYPE_LENGTH (type);
9123 int regno = ARM_A1_REGNUM;
9124 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9128 memcpy (tmpbuf, valbuf,
9129 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9130 regcache_cooked_write (regs, regno++, tmpbuf);
9131 len -= INT_REGISTER_SIZE;
9132 valbuf += INT_REGISTER_SIZE;
9138 /* Handle function return values. */
9140 static enum return_value_convention
9141 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9142 struct type *valtype, struct regcache *regcache,
9143 gdb_byte *readbuf, const gdb_byte *writebuf)
9145 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9146 struct type *func_type = function ? value_type (function) : NULL;
9147 enum arm_vfp_cprc_base_type vfp_base_type;
9150 if (arm_vfp_abi_for_function (gdbarch, func_type)
9151 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9153 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9154 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9156 for (i = 0; i < vfp_base_count; i++)
9158 if (reg_char == 'q')
9161 arm_neon_quad_write (gdbarch, regcache, i,
9162 writebuf + i * unit_length);
9165 arm_neon_quad_read (gdbarch, regcache, i,
9166 readbuf + i * unit_length);
9173 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
9174 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9177 regcache_cooked_write (regcache, regnum,
9178 writebuf + i * unit_length);
9180 regcache_cooked_read (regcache, regnum,
9181 readbuf + i * unit_length);
9184 return RETURN_VALUE_REGISTER_CONVENTION;
9187 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9188 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9189 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9191 if (tdep->struct_return == pcc_struct_return
9192 || arm_return_in_memory (gdbarch, valtype))
9193 return RETURN_VALUE_STRUCT_CONVENTION;
9196 /* AAPCS returns complex types longer than a register in memory. */
9197 if (tdep->arm_abi != ARM_ABI_APCS
9198 && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
9199 && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE)
9200 return RETURN_VALUE_STRUCT_CONVENTION;
9203 arm_store_return_value (valtype, regcache, writebuf);
9206 arm_extract_return_value (valtype, regcache, readbuf);
9208 return RETURN_VALUE_REGISTER_CONVENTION;
9213 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9215 struct gdbarch *gdbarch = get_frame_arch (frame);
9216 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9217 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9219 char buf[INT_REGISTER_SIZE];
9221 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9223 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9227 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9231 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9232 return the target PC. Otherwise return 0. */
9235 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9239 CORE_ADDR start_addr;
9241 /* Find the starting address and name of the function containing the PC. */
9242 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9245 /* If PC is in a Thumb call or return stub, return the address of the
9246 target PC, which is in a register. The thunk functions are called
9247 _call_via_xx, where x is the register name. The possible names
9248 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9249 functions, named __ARM_call_via_r[0-7]. */
9250 if (strncmp (name, "_call_via_", 10) == 0
9251 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9253 /* Use the name suffix to determine which register contains the
9255 static char *table[15] =
9256 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9257 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9260 int offset = strlen (name) - 2;
9262 for (regno = 0; regno <= 14; regno++)
9263 if (strcmp (&name[offset], table[regno]) == 0)
9264 return get_frame_register_unsigned (frame, regno);
9267 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9268 non-interworking calls to foo. We could decode the stubs
9269 to find the target but it's easier to use the symbol table. */
9270 namelen = strlen (name);
9271 if (name[0] == '_' && name[1] == '_'
9272 && ((namelen > 2 + strlen ("_from_thumb")
9273 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
9274 strlen ("_from_thumb")) == 0)
9275 || (namelen > 2 + strlen ("_from_arm")
9276 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
9277 strlen ("_from_arm")) == 0)))
9280 int target_len = namelen - 2;
9281 struct minimal_symbol *minsym;
9282 struct objfile *objfile;
9283 struct obj_section *sec;
9285 if (name[namelen - 1] == 'b')
9286 target_len -= strlen ("_from_thumb");
9288 target_len -= strlen ("_from_arm");
9290 target_name = alloca (target_len + 1);
9291 memcpy (target_name, name + 2, target_len);
9292 target_name[target_len] = '\0';
9294 sec = find_pc_section (pc);
9295 objfile = (sec == NULL) ? NULL : sec->objfile;
9296 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9298 return SYMBOL_VALUE_ADDRESS (minsym);
9303 return 0; /* not a stub */
9307 set_arm_command (char *args, int from_tty)
9309 printf_unfiltered (_("\
9310 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9311 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9315 show_arm_command (char *args, int from_tty)
9317 cmd_show_list (showarmcmdlist, from_tty, "");
9321 arm_update_current_architecture (void)
9323 struct gdbarch_info info;
9325 /* If the current architecture is not ARM, we have nothing to do. */
9326 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
9329 /* Update the architecture. */
9330 gdbarch_info_init (&info);
9332 if (!gdbarch_update_p (info))
9333 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9337 set_fp_model_sfunc (char *args, int from_tty,
9338 struct cmd_list_element *c)
9340 enum arm_float_model fp_model;
9342 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9343 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9345 arm_fp_model = fp_model;
9349 if (fp_model == ARM_FLOAT_LAST)
9350 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9353 arm_update_current_architecture ();
9357 show_fp_model (struct ui_file *file, int from_tty,
9358 struct cmd_list_element *c, const char *value)
9360 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9362 if (arm_fp_model == ARM_FLOAT_AUTO
9363 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9364 fprintf_filtered (file, _("\
9365 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9366 fp_model_strings[tdep->fp_model]);
9368 fprintf_filtered (file, _("\
9369 The current ARM floating point model is \"%s\".\n"),
9370 fp_model_strings[arm_fp_model]);
9374 arm_set_abi (char *args, int from_tty,
9375 struct cmd_list_element *c)
9377 enum arm_abi_kind arm_abi;
9379 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9380 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9382 arm_abi_global = arm_abi;
9386 if (arm_abi == ARM_ABI_LAST)
9387 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9390 arm_update_current_architecture ();
9394 arm_show_abi (struct ui_file *file, int from_tty,
9395 struct cmd_list_element *c, const char *value)
9397 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9399 if (arm_abi_global == ARM_ABI_AUTO
9400 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9401 fprintf_filtered (file, _("\
9402 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9403 arm_abi_strings[tdep->arm_abi]);
9405 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9410 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9411 struct cmd_list_element *c, const char *value)
9413 fprintf_filtered (file,
9414 _("The current execution mode assumed "
9415 "(when symbols are unavailable) is \"%s\".\n"),
9416 arm_fallback_mode_string);
9420 arm_show_force_mode (struct ui_file *file, int from_tty,
9421 struct cmd_list_element *c, const char *value)
9423 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9425 fprintf_filtered (file,
9426 _("The current execution mode assumed "
9427 "(even when symbols are available) is \"%s\".\n"),
9428 arm_force_mode_string);
9431 /* If the user changes the register disassembly style used for info
9432 register and other commands, we have to also switch the style used
9433 in opcodes for disassembly output. This function is run in the "set
9434 arm disassembly" command, and does that. */
9437 set_disassembly_style_sfunc (char *args, int from_tty,
9438 struct cmd_list_element *c)
9440 set_disassembly_style ();
9443 /* Return the ARM register name corresponding to register I. */
9445 arm_register_name (struct gdbarch *gdbarch, int i)
9447 const int num_regs = gdbarch_num_regs (gdbarch);
9449 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9450 && i >= num_regs && i < num_regs + 32)
9452 static const char *const vfp_pseudo_names[] = {
9453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9454 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9455 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9456 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9459 return vfp_pseudo_names[i - num_regs];
9462 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9463 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9465 static const char *const neon_pseudo_names[] = {
9466 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9467 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9470 return neon_pseudo_names[i - num_regs - 32];
9473 if (i >= ARRAY_SIZE (arm_register_names))
9474 /* These registers are only supported on targets which supply
9475 an XML description. */
9478 return arm_register_names[i];
9482 set_disassembly_style (void)
9486 /* Find the style that the user wants. */
9487 for (current = 0; current < num_disassembly_options; current++)
9488 if (disassembly_style == valid_disassembly_styles[current])
9490 gdb_assert (current < num_disassembly_options);
9492 /* Synchronize the disassembler. */
9493 set_arm_regname_option (current);
9496 /* Test whether the coff symbol specific value corresponds to a Thumb
9500 coff_sym_is_thumb (int val)
9502 return (val == C_THUMBEXT
9503 || val == C_THUMBSTAT
9504 || val == C_THUMBEXTFUNC
9505 || val == C_THUMBSTATFUNC
9506 || val == C_THUMBLABEL);
9509 /* arm_coff_make_msymbol_special()
9510 arm_elf_make_msymbol_special()
9512 These functions test whether the COFF or ELF symbol corresponds to
9513 an address in thumb code, and set a "special" bit in a minimal
9514 symbol to indicate that it does. */
9517 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9519 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9520 == ST_BRANCH_TO_THUMB)
9521 MSYMBOL_SET_SPECIAL (msym);
9525 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9527 if (coff_sym_is_thumb (val))
9528 MSYMBOL_SET_SPECIAL (msym);
9532 arm_objfile_data_free (struct objfile *objfile, void *arg)
9534 struct arm_per_objfile *data = arg;
9537 for (i = 0; i < objfile->obfd->section_count; i++)
9538 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9542 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9545 const char *name = bfd_asymbol_name (sym);
9546 struct arm_per_objfile *data;
9547 VEC(arm_mapping_symbol_s) **map_p;
9548 struct arm_mapping_symbol new_map_sym;
9550 gdb_assert (name[0] == '$');
9551 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9554 data = objfile_data (objfile, arm_objfile_data_key);
9557 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9558 struct arm_per_objfile);
9559 set_objfile_data (objfile, arm_objfile_data_key, data);
9560 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9561 objfile->obfd->section_count,
9562 VEC(arm_mapping_symbol_s) *);
9564 map_p = &data->section_maps[bfd_get_section (sym)->index];
9566 new_map_sym.value = sym->value;
9567 new_map_sym.type = name[1];
9569 /* Assume that most mapping symbols appear in order of increasing
9570 value. If they were randomly distributed, it would be faster to
9571 always push here and then sort at first use. */
9572 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9574 struct arm_mapping_symbol *prev_map_sym;
9576 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9577 if (prev_map_sym->value >= sym->value)
9580 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9581 arm_compare_mapping_symbols);
9582 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9587 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9591 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9593 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9594 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9596 /* If necessary, set the T bit. */
9599 ULONGEST val, t_bit;
9600 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9601 t_bit = arm_psr_thumb_bit (gdbarch);
9602 if (arm_pc_is_thumb (gdbarch, pc))
9603 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9606 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9611 /* Read the contents of a NEON quad register, by reading from two
9612 double registers. This is used to implement the quad pseudo
9613 registers, and for argument passing in case the quad registers are
9614 missing; vectors are passed in quad registers when using the VFP
9615 ABI, even if a NEON unit is not present. REGNUM is the index of
9616 the quad register, in [0, 15]. */
9618 static enum register_status
9619 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9620 int regnum, gdb_byte *buf)
9623 gdb_byte reg_buf[8];
9624 int offset, double_regnum;
9625 enum register_status status;
9627 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9628 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9631 /* d0 is always the least significant half of q0. */
9632 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9637 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9638 if (status != REG_VALID)
9640 memcpy (buf + offset, reg_buf, 8);
9642 offset = 8 - offset;
9643 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9644 if (status != REG_VALID)
9646 memcpy (buf + offset, reg_buf, 8);
9651 static enum register_status
9652 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9653 int regnum, gdb_byte *buf)
9655 const int num_regs = gdbarch_num_regs (gdbarch);
9657 gdb_byte reg_buf[8];
9658 int offset, double_regnum;
9660 gdb_assert (regnum >= num_regs);
9663 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9664 /* Quad-precision register. */
9665 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9668 enum register_status status;
9670 /* Single-precision register. */
9671 gdb_assert (regnum < 32);
9673 /* s0 is always the least significant half of d0. */
9674 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9675 offset = (regnum & 1) ? 0 : 4;
9677 offset = (regnum & 1) ? 4 : 0;
9679 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9680 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9683 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9684 if (status == REG_VALID)
9685 memcpy (buf, reg_buf + offset, 4);
9690 /* Store the contents of BUF to a NEON quad register, by writing to
9691 two double registers. This is used to implement the quad pseudo
9692 registers, and for argument passing in case the quad registers are
9693 missing; vectors are passed in quad registers when using the VFP
9694 ABI, even if a NEON unit is not present. REGNUM is the index
9695 of the quad register, in [0, 15]. */
9698 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9699 int regnum, const gdb_byte *buf)
9702 int offset, double_regnum;
9704 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9705 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9708 /* d0 is always the least significant half of q0. */
9709 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9714 regcache_raw_write (regcache, double_regnum, buf + offset);
9715 offset = 8 - offset;
9716 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9720 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9721 int regnum, const gdb_byte *buf)
9723 const int num_regs = gdbarch_num_regs (gdbarch);
9725 gdb_byte reg_buf[8];
9726 int offset, double_regnum;
9728 gdb_assert (regnum >= num_regs);
9731 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9732 /* Quad-precision register. */
9733 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9736 /* Single-precision register. */
9737 gdb_assert (regnum < 32);
9739 /* s0 is always the least significant half of d0. */
9740 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9741 offset = (regnum & 1) ? 0 : 4;
9743 offset = (regnum & 1) ? 4 : 0;
9745 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9746 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9749 regcache_raw_read (regcache, double_regnum, reg_buf);
9750 memcpy (reg_buf + offset, buf, 4);
9751 regcache_raw_write (regcache, double_regnum, reg_buf);
9755 static struct value *
9756 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9758 const int *reg_p = baton;
9759 return value_of_register (*reg_p, frame);
9762 static enum gdb_osabi
9763 arm_elf_osabi_sniffer (bfd *abfd)
9765 unsigned int elfosabi;
9766 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9768 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9770 if (elfosabi == ELFOSABI_ARM)
9771 /* GNU tools use this value. Check note sections in this case,
9773 bfd_map_over_sections (abfd,
9774 generic_elf_osabi_sniff_abi_tag_sections,
9777 /* Anything else will be handled by the generic ELF sniffer. */
9782 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9783 struct reggroup *group)
9785 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9786 this, FPS register belongs to save_regroup, restore_reggroup, and
9787 all_reggroup, of course. */
9788 if (regnum == ARM_FPS_REGNUM)
9789 return (group == float_reggroup
9790 || group == save_reggroup
9791 || group == restore_reggroup
9792 || group == all_reggroup);
9794 return default_register_reggroup_p (gdbarch, regnum, group);
9798 /* For backward-compatibility we allow two 'g' packet lengths with
9799 the remote protocol depending on whether FPA registers are
9800 supplied. M-profile targets do not have FPA registers, but some
9801 stubs already exist in the wild which use a 'g' packet which
9802 supplies them albeit with dummy values. The packet format which
9803 includes FPA registers should be considered deprecated for
9804 M-profile targets. */
9807 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9809 if (gdbarch_tdep (gdbarch)->is_m)
9811 /* If we know from the executable this is an M-profile target,
9812 cater for remote targets whose register set layout is the
9813 same as the FPA layout. */
9814 register_remote_g_packet_guess (gdbarch,
9815 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9816 (16 * INT_REGISTER_SIZE)
9817 + (8 * FP_REGISTER_SIZE)
9818 + (2 * INT_REGISTER_SIZE),
9819 tdesc_arm_with_m_fpa_layout);
9821 /* The regular M-profile layout. */
9822 register_remote_g_packet_guess (gdbarch,
9823 /* r0-r12,sp,lr,pc; xpsr */
9824 (16 * INT_REGISTER_SIZE)
9825 + INT_REGISTER_SIZE,
9828 /* M-profile plus M4F VFP. */
9829 register_remote_g_packet_guess (gdbarch,
9830 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9831 (16 * INT_REGISTER_SIZE)
9832 + (16 * VFP_REGISTER_SIZE)
9833 + (2 * INT_REGISTER_SIZE),
9834 tdesc_arm_with_m_vfp_d16);
9837 /* Otherwise we don't have a useful guess. */
9841 /* Initialize the current architecture based on INFO. If possible,
9842 re-use an architecture from ARCHES, which is a list of
9843 architectures already created during this debugging session.
9845 Called e.g. at program startup, when reading a core file, and when
9846 reading a binary file. */
9848 static struct gdbarch *
9849 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9851 struct gdbarch_tdep *tdep;
9852 struct gdbarch *gdbarch;
9853 struct gdbarch_list *best_arch;
9854 enum arm_abi_kind arm_abi = arm_abi_global;
9855 enum arm_float_model fp_model = arm_fp_model;
9856 struct tdesc_arch_data *tdesc_data = NULL;
9858 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9860 int have_fpa_registers = 1;
9861 const struct target_desc *tdesc = info.target_desc;
9863 /* If we have an object to base this architecture on, try to determine
9866 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9868 int ei_osabi, e_flags;
9870 switch (bfd_get_flavour (info.abfd))
9872 case bfd_target_aout_flavour:
9873 /* Assume it's an old APCS-style ABI. */
9874 arm_abi = ARM_ABI_APCS;
9877 case bfd_target_coff_flavour:
9878 /* Assume it's an old APCS-style ABI. */
9880 arm_abi = ARM_ABI_APCS;
9883 case bfd_target_elf_flavour:
9884 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9885 e_flags = elf_elfheader (info.abfd)->e_flags;
9887 if (ei_osabi == ELFOSABI_ARM)
9889 /* GNU tools used to use this value, but do not for EABI
9890 objects. There's nowhere to tag an EABI version
9891 anyway, so assume APCS. */
9892 arm_abi = ARM_ABI_APCS;
9894 else if (ei_osabi == ELFOSABI_NONE)
9896 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9897 int attr_arch, attr_profile;
9901 case EF_ARM_EABI_UNKNOWN:
9902 /* Assume GNU tools. */
9903 arm_abi = ARM_ABI_APCS;
9906 case EF_ARM_EABI_VER4:
9907 case EF_ARM_EABI_VER5:
9908 arm_abi = ARM_ABI_AAPCS;
9909 /* EABI binaries default to VFP float ordering.
9910 They may also contain build attributes that can
9911 be used to identify if the VFP argument-passing
9913 if (fp_model == ARM_FLOAT_AUTO)
9916 switch (bfd_elf_get_obj_attr_int (info.abfd,
9921 /* "The user intended FP parameter/result
9922 passing to conform to AAPCS, base
9924 fp_model = ARM_FLOAT_SOFT_VFP;
9927 /* "The user intended FP parameter/result
9928 passing to conform to AAPCS, VFP
9930 fp_model = ARM_FLOAT_VFP;
9933 /* "The user intended FP parameter/result
9934 passing to conform to tool chain-specific
9935 conventions" - we don't know any such
9936 conventions, so leave it as "auto". */
9939 /* Attribute value not mentioned in the
9940 October 2008 ABI, so leave it as
9945 fp_model = ARM_FLOAT_SOFT_VFP;
9951 /* Leave it as "auto". */
9952 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9957 /* Detect M-profile programs. This only works if the
9958 executable file includes build attributes; GCC does
9959 copy them to the executable, but e.g. RealView does
9961 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9963 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9965 Tag_CPU_arch_profile);
9966 /* GCC specifies the profile for v6-M; RealView only
9967 specifies the profile for architectures starting with
9968 V7 (as opposed to architectures with a tag
9969 numerically greater than TAG_CPU_ARCH_V7). */
9970 if (!tdesc_has_registers (tdesc)
9971 && (attr_arch == TAG_CPU_ARCH_V6_M
9972 || attr_arch == TAG_CPU_ARCH_V6S_M
9973 || attr_profile == 'M'))
9978 if (fp_model == ARM_FLOAT_AUTO)
9980 int e_flags = elf_elfheader (info.abfd)->e_flags;
9982 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9985 /* Leave it as "auto". Strictly speaking this case
9986 means FPA, but almost nobody uses that now, and
9987 many toolchains fail to set the appropriate bits
9988 for the floating-point model they use. */
9990 case EF_ARM_SOFT_FLOAT:
9991 fp_model = ARM_FLOAT_SOFT_FPA;
9993 case EF_ARM_VFP_FLOAT:
9994 fp_model = ARM_FLOAT_VFP;
9996 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9997 fp_model = ARM_FLOAT_SOFT_VFP;
10002 if (e_flags & EF_ARM_BE8)
10003 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10008 /* Leave it as "auto". */
10013 /* Check any target description for validity. */
10014 if (tdesc_has_registers (tdesc))
10016 /* For most registers we require GDB's default names; but also allow
10017 the numeric names for sp / lr / pc, as a convenience. */
10018 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
10019 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
10020 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
10022 const struct tdesc_feature *feature;
10025 feature = tdesc_find_feature (tdesc,
10026 "org.gnu.gdb.arm.core");
10027 if (feature == NULL)
10029 feature = tdesc_find_feature (tdesc,
10030 "org.gnu.gdb.arm.m-profile");
10031 if (feature == NULL)
10037 tdesc_data = tdesc_data_alloc ();
10040 for (i = 0; i < ARM_SP_REGNUM; i++)
10041 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10042 arm_register_names[i]);
10043 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10046 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10049 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10053 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10054 ARM_PS_REGNUM, "xpsr");
10056 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10057 ARM_PS_REGNUM, "cpsr");
10061 tdesc_data_cleanup (tdesc_data);
10065 feature = tdesc_find_feature (tdesc,
10066 "org.gnu.gdb.arm.fpa");
10067 if (feature != NULL)
10070 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
10071 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10072 arm_register_names[i]);
10075 tdesc_data_cleanup (tdesc_data);
10080 have_fpa_registers = 0;
10082 feature = tdesc_find_feature (tdesc,
10083 "org.gnu.gdb.xscale.iwmmxt");
10084 if (feature != NULL)
10086 static const char *const iwmmxt_names[] = {
10087 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10088 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10089 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10090 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10094 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
10096 &= tdesc_numbered_register (feature, tdesc_data, i,
10097 iwmmxt_names[i - ARM_WR0_REGNUM]);
10099 /* Check for the control registers, but do not fail if they
10101 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
10102 tdesc_numbered_register (feature, tdesc_data, i,
10103 iwmmxt_names[i - ARM_WR0_REGNUM]);
10105 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
10107 &= tdesc_numbered_register (feature, tdesc_data, i,
10108 iwmmxt_names[i - ARM_WR0_REGNUM]);
10112 tdesc_data_cleanup (tdesc_data);
10117 /* If we have a VFP unit, check whether the single precision registers
10118 are present. If not, then we will synthesize them as pseudo
10120 feature = tdesc_find_feature (tdesc,
10121 "org.gnu.gdb.arm.vfp");
10122 if (feature != NULL)
10124 static const char *const vfp_double_names[] = {
10125 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10126 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10127 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10128 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10131 /* Require the double precision registers. There must be either
10134 for (i = 0; i < 32; i++)
10136 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10138 vfp_double_names[i]);
10142 if (!valid_p && i == 16)
10145 /* Also require FPSCR. */
10146 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10147 ARM_FPSCR_REGNUM, "fpscr");
10150 tdesc_data_cleanup (tdesc_data);
10154 if (tdesc_unnumbered_register (feature, "s0") == 0)
10155 have_vfp_pseudos = 1;
10157 have_vfp_registers = 1;
10159 /* If we have VFP, also check for NEON. The architecture allows
10160 NEON without VFP (integer vector operations only), but GDB
10161 does not support that. */
10162 feature = tdesc_find_feature (tdesc,
10163 "org.gnu.gdb.arm.neon");
10164 if (feature != NULL)
10166 /* NEON requires 32 double-precision registers. */
10169 tdesc_data_cleanup (tdesc_data);
10173 /* If there are quad registers defined by the stub, use
10174 their type; otherwise (normally) provide them with
10175 the default type. */
10176 if (tdesc_unnumbered_register (feature, "q0") == 0)
10177 have_neon_pseudos = 1;
10184 /* If there is already a candidate, use it. */
10185 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10187 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10189 if (arm_abi != ARM_ABI_AUTO
10190 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10193 if (fp_model != ARM_FLOAT_AUTO
10194 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10197 /* There are various other properties in tdep that we do not
10198 need to check here: those derived from a target description,
10199 since gdbarches with a different target description are
10200 automatically disqualified. */
10202 /* Do check is_m, though, since it might come from the binary. */
10203 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10206 /* Found a match. */
10210 if (best_arch != NULL)
10212 if (tdesc_data != NULL)
10213 tdesc_data_cleanup (tdesc_data);
10214 return best_arch->gdbarch;
10217 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
10218 gdbarch = gdbarch_alloc (&info, tdep);
10220 /* Record additional information about the architecture we are defining.
10221 These are gdbarch discriminators, like the OSABI. */
10222 tdep->arm_abi = arm_abi;
10223 tdep->fp_model = fp_model;
10225 tdep->have_fpa_registers = have_fpa_registers;
10226 tdep->have_vfp_registers = have_vfp_registers;
10227 tdep->have_vfp_pseudos = have_vfp_pseudos;
10228 tdep->have_neon_pseudos = have_neon_pseudos;
10229 tdep->have_neon = have_neon;
10231 arm_register_g_packet_guesses (gdbarch);
10234 switch (info.byte_order_for_code)
10236 case BFD_ENDIAN_BIG:
10237 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10238 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10239 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10240 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10244 case BFD_ENDIAN_LITTLE:
10245 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10246 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10247 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10248 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10253 internal_error (__FILE__, __LINE__,
10254 _("arm_gdbarch_init: bad byte order for float format"));
10257 /* On ARM targets char defaults to unsigned. */
10258 set_gdbarch_char_signed (gdbarch, 0);
10260 /* Note: for displaced stepping, this includes the breakpoint, and one word
10261 of additional scratch space. This setting isn't used for anything beside
10262 displaced stepping at present. */
10263 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10265 /* This should be low enough for everything. */
10266 tdep->lowest_pc = 0x20;
10267 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10269 /* The default, for both APCS and AAPCS, is to return small
10270 structures in registers. */
10271 tdep->struct_return = reg_struct_return;
10273 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10274 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10276 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10278 /* Frame handling. */
10279 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10280 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10281 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10283 frame_base_set_default (gdbarch, &arm_normal_base);
10285 /* Address manipulation. */
10286 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
10287 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10289 /* Advance PC across function entry code. */
10290 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10292 /* Detect whether PC is in function epilogue. */
10293 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
10295 /* Skip trampolines. */
10296 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10298 /* The stack grows downward. */
10299 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10301 /* Breakpoint manipulation. */
10302 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10303 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10304 arm_remote_breakpoint_from_pc);
10306 /* Information about registers, etc. */
10307 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10308 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10309 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10310 set_gdbarch_register_type (gdbarch, arm_register_type);
10311 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10313 /* This "info float" is FPA-specific. Use the generic version if we
10314 do not have FPA. */
10315 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10316 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10318 /* Internal <-> external register number maps. */
10319 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10320 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10322 set_gdbarch_register_name (gdbarch, arm_register_name);
10324 /* Returning results. */
10325 set_gdbarch_return_value (gdbarch, arm_return_value);
10328 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10330 /* Minsymbol frobbing. */
10331 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10332 set_gdbarch_coff_make_msymbol_special (gdbarch,
10333 arm_coff_make_msymbol_special);
10334 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10336 /* Thumb-2 IT block support. */
10337 set_gdbarch_adjust_breakpoint_address (gdbarch,
10338 arm_adjust_breakpoint_address);
10340 /* Virtual tables. */
10341 set_gdbarch_vbit_in_delta (gdbarch, 1);
10343 /* Hook in the ABI-specific overrides, if they have been registered. */
10344 gdbarch_init_osabi (info, gdbarch);
10346 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10348 /* Add some default predicates. */
10350 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
10351 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10352 dwarf2_append_unwinders (gdbarch);
10353 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10354 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10356 /* Now we have tuned the configuration, set a few final things,
10357 based on what the OS ABI has told us. */
10359 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10360 binaries are always marked. */
10361 if (tdep->arm_abi == ARM_ABI_AUTO)
10362 tdep->arm_abi = ARM_ABI_APCS;
10364 /* Watchpoints are not steppable. */
10365 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10367 /* We used to default to FPA for generic ARM, but almost nobody
10368 uses that now, and we now provide a way for the user to force
10369 the model. So default to the most useful variant. */
10370 if (tdep->fp_model == ARM_FLOAT_AUTO)
10371 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10373 if (tdep->jb_pc >= 0)
10374 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10376 /* Floating point sizes and format. */
10377 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10378 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10380 set_gdbarch_double_format
10381 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10382 set_gdbarch_long_double_format
10383 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10387 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10388 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10391 if (have_vfp_pseudos)
10393 /* NOTE: These are the only pseudo registers used by
10394 the ARM target at the moment. If more are added, a
10395 little more care in numbering will be needed. */
10397 int num_pseudos = 32;
10398 if (have_neon_pseudos)
10400 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10401 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10402 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10407 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10409 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10411 /* Override tdesc_register_type to adjust the types of VFP
10412 registers for NEON. */
10413 set_gdbarch_register_type (gdbarch, arm_register_type);
10416 /* Add standard register aliases. We add aliases even for those
10417 nanes which are used by the current architecture - it's simpler,
10418 and does no harm, since nothing ever lists user registers. */
10419 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10420 user_reg_add (gdbarch, arm_register_aliases[i].name,
10421 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10427 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10429 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10434 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10435 (unsigned long) tdep->lowest_pc);
10438 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10441 _initialize_arm_tdep (void)
10443 struct ui_file *stb;
10445 struct cmd_list_element *new_set, *new_show;
10446 const char *setname;
10447 const char *setdesc;
10448 const char *const *regnames;
10450 static char *helptext;
10451 char regdesc[1024], *rdptr = regdesc;
10452 size_t rest = sizeof (regdesc);
10454 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10456 arm_objfile_data_key
10457 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10459 /* Add ourselves to objfile event chain. */
10460 observer_attach_new_objfile (arm_exidx_new_objfile);
10462 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10464 /* Register an ELF OS ABI sniffer for ARM binaries. */
10465 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10466 bfd_target_elf_flavour,
10467 arm_elf_osabi_sniffer);
10469 /* Initialize the standard target descriptions. */
10470 initialize_tdesc_arm_with_m ();
10471 initialize_tdesc_arm_with_m_fpa_layout ();
10472 initialize_tdesc_arm_with_m_vfp_d16 ();
10473 initialize_tdesc_arm_with_iwmmxt ();
10474 initialize_tdesc_arm_with_vfpv2 ();
10475 initialize_tdesc_arm_with_vfpv3 ();
10476 initialize_tdesc_arm_with_neon ();
10478 /* Get the number of possible sets of register names defined in opcodes. */
10479 num_disassembly_options = get_arm_regname_num_options ();
10481 /* Add root prefix command for all "set arm"/"show arm" commands. */
10482 add_prefix_cmd ("arm", no_class, set_arm_command,
10483 _("Various ARM-specific commands."),
10484 &setarmcmdlist, "set arm ", 0, &setlist);
10486 add_prefix_cmd ("arm", no_class, show_arm_command,
10487 _("Various ARM-specific commands."),
10488 &showarmcmdlist, "show arm ", 0, &showlist);
10490 /* Sync the opcode insn printer with our register viewer. */
10491 parse_arm_disassembler_option ("reg-names-std");
10493 /* Initialize the array that will be passed to
10494 add_setshow_enum_cmd(). */
10495 valid_disassembly_styles
10496 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10497 for (i = 0; i < num_disassembly_options; i++)
10499 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10500 valid_disassembly_styles[i] = setname;
10501 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10504 /* When we find the default names, tell the disassembler to use
10506 if (!strcmp (setname, "std"))
10508 disassembly_style = setname;
10509 set_arm_regname_option (i);
10512 /* Mark the end of valid options. */
10513 valid_disassembly_styles[num_disassembly_options] = NULL;
10515 /* Create the help text. */
10516 stb = mem_fileopen ();
10517 fprintf_unfiltered (stb, "%s%s%s",
10518 _("The valid values are:\n"),
10520 _("The default is \"std\"."));
10521 helptext = ui_file_xstrdup (stb, NULL);
10522 ui_file_delete (stb);
10524 add_setshow_enum_cmd("disassembler", no_class,
10525 valid_disassembly_styles, &disassembly_style,
10526 _("Set the disassembly style."),
10527 _("Show the disassembly style."),
10529 set_disassembly_style_sfunc,
10530 NULL, /* FIXME: i18n: The disassembly style is
10532 &setarmcmdlist, &showarmcmdlist);
10534 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10535 _("Set usage of ARM 32-bit mode."),
10536 _("Show usage of ARM 32-bit mode."),
10537 _("When off, a 26-bit PC will be used."),
10539 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10541 &setarmcmdlist, &showarmcmdlist);
10543 /* Add a command to allow the user to force the FPU model. */
10544 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10545 _("Set the floating point type."),
10546 _("Show the floating point type."),
10547 _("auto - Determine the FP typefrom the OS-ABI.\n\
10548 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10549 fpa - FPA co-processor (GCC compiled).\n\
10550 softvfp - Software FP with pure-endian doubles.\n\
10551 vfp - VFP co-processor."),
10552 set_fp_model_sfunc, show_fp_model,
10553 &setarmcmdlist, &showarmcmdlist);
10555 /* Add a command to allow the user to force the ABI. */
10556 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10558 _("Show the ABI."),
10559 NULL, arm_set_abi, arm_show_abi,
10560 &setarmcmdlist, &showarmcmdlist);
10562 /* Add two commands to allow the user to force the assumed
10564 add_setshow_enum_cmd ("fallback-mode", class_support,
10565 arm_mode_strings, &arm_fallback_mode_string,
10566 _("Set the mode assumed when symbols are unavailable."),
10567 _("Show the mode assumed when symbols are unavailable."),
10568 NULL, NULL, arm_show_fallback_mode,
10569 &setarmcmdlist, &showarmcmdlist);
10570 add_setshow_enum_cmd ("force-mode", class_support,
10571 arm_mode_strings, &arm_force_mode_string,
10572 _("Set the mode assumed even when symbols are available."),
10573 _("Show the mode assumed even when symbols are available."),
10574 NULL, NULL, arm_show_force_mode,
10575 &setarmcmdlist, &showarmcmdlist);
10577 /* Debugging flag. */
10578 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10579 _("Set ARM debugging."),
10580 _("Show ARM debugging."),
10581 _("When on, arm-specific debugging is enabled."),
10583 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10584 &setdebuglist, &showdebuglist);
10587 /* ARM-reversible process record data structures. */
10589 #define ARM_INSN_SIZE_BYTES 4
10590 #define THUMB_INSN_SIZE_BYTES 2
10591 #define THUMB2_INSN_SIZE_BYTES 4
10594 #define INSN_S_L_BIT_NUM 20
10596 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10599 unsigned int reg_len = LENGTH; \
10602 REGS = XNEWVEC (uint32_t, reg_len); \
10603 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10608 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10611 unsigned int mem_len = LENGTH; \
10614 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10615 memcpy(&MEMS->len, &RECORD_BUF[0], \
10616 sizeof(struct arm_mem_r) * LENGTH); \
10621 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10622 #define INSN_RECORDED(ARM_RECORD) \
10623 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10625 /* ARM memory record structure. */
10628 uint32_t len; /* Record length. */
10629 CORE_ADDR addr; /* Memory address. */
10632 /* ARM instruction record contains opcode of current insn
10633 and execution state (before entry to decode_insn()),
10634 contains list of to-be-modified registers and
10635 memory blocks (on return from decode_insn()). */
10637 typedef struct insn_decode_record_t
10639 struct gdbarch *gdbarch;
10640 struct regcache *regcache;
10641 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10642 uint32_t arm_insn; /* Should accommodate thumb. */
10643 uint32_t cond; /* Condition code. */
10644 uint32_t opcode; /* Insn opcode. */
10645 uint32_t decode; /* Insn decode bits. */
10646 uint32_t mem_rec_count; /* No of mem records. */
10647 uint32_t reg_rec_count; /* No of reg records. */
10648 uint32_t *arm_regs; /* Registers to be saved for this record. */
10649 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10650 } insn_decode_record;
10653 /* Checks ARM SBZ and SBO mandatory fields. */
10656 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10658 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10681 } arm_record_strx_t;
10692 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10693 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10696 struct regcache *reg_cache = arm_insn_r->regcache;
10697 ULONGEST u_regval[2]= {0};
10699 uint32_t reg_src1 = 0, reg_src2 = 0;
10700 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10701 uint32_t opcode1 = 0;
10703 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10704 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10705 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10708 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10710 /* 1) Handle misc store, immediate offset. */
10711 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10712 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10713 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10714 regcache_raw_read_unsigned (reg_cache, reg_src1,
10716 if (ARM_PC_REGNUM == reg_src1)
10718 /* If R15 was used as Rn, hence current PC+8. */
10719 u_regval[0] = u_regval[0] + 8;
10721 offset_8 = (immed_high << 4) | immed_low;
10722 /* Calculate target store address. */
10723 if (14 == arm_insn_r->opcode)
10725 tgt_mem_addr = u_regval[0] + offset_8;
10729 tgt_mem_addr = u_regval[0] - offset_8;
10731 if (ARM_RECORD_STRH == str_type)
10733 record_buf_mem[0] = 2;
10734 record_buf_mem[1] = tgt_mem_addr;
10735 arm_insn_r->mem_rec_count = 1;
10737 else if (ARM_RECORD_STRD == str_type)
10739 record_buf_mem[0] = 4;
10740 record_buf_mem[1] = tgt_mem_addr;
10741 record_buf_mem[2] = 4;
10742 record_buf_mem[3] = tgt_mem_addr + 4;
10743 arm_insn_r->mem_rec_count = 2;
10746 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10748 /* 2) Store, register offset. */
10750 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10752 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10753 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10754 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10755 if (15 == reg_src2)
10757 /* If R15 was used as Rn, hence current PC+8. */
10758 u_regval[0] = u_regval[0] + 8;
10760 /* Calculate target store address, Rn +/- Rm, register offset. */
10761 if (12 == arm_insn_r->opcode)
10763 tgt_mem_addr = u_regval[0] + u_regval[1];
10767 tgt_mem_addr = u_regval[1] - u_regval[0];
10769 if (ARM_RECORD_STRH == str_type)
10771 record_buf_mem[0] = 2;
10772 record_buf_mem[1] = tgt_mem_addr;
10773 arm_insn_r->mem_rec_count = 1;
10775 else if (ARM_RECORD_STRD == str_type)
10777 record_buf_mem[0] = 4;
10778 record_buf_mem[1] = tgt_mem_addr;
10779 record_buf_mem[2] = 4;
10780 record_buf_mem[3] = tgt_mem_addr + 4;
10781 arm_insn_r->mem_rec_count = 2;
10784 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10785 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10787 /* 3) Store, immediate pre-indexed. */
10788 /* 5) Store, immediate post-indexed. */
10789 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10790 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10791 offset_8 = (immed_high << 4) | immed_low;
10792 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10793 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10794 /* Calculate target store address, Rn +/- Rm, register offset. */
10795 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10797 tgt_mem_addr = u_regval[0] + offset_8;
10801 tgt_mem_addr = u_regval[0] - offset_8;
10803 if (ARM_RECORD_STRH == str_type)
10805 record_buf_mem[0] = 2;
10806 record_buf_mem[1] = tgt_mem_addr;
10807 arm_insn_r->mem_rec_count = 1;
10809 else if (ARM_RECORD_STRD == str_type)
10811 record_buf_mem[0] = 4;
10812 record_buf_mem[1] = tgt_mem_addr;
10813 record_buf_mem[2] = 4;
10814 record_buf_mem[3] = tgt_mem_addr + 4;
10815 arm_insn_r->mem_rec_count = 2;
10817 /* Record Rn also as it changes. */
10818 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10819 arm_insn_r->reg_rec_count = 1;
10821 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10822 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10824 /* 4) Store, register pre-indexed. */
10825 /* 6) Store, register post -indexed. */
10826 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10827 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10828 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10829 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10830 /* Calculate target store address, Rn +/- Rm, register offset. */
10831 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10833 tgt_mem_addr = u_regval[0] + u_regval[1];
10837 tgt_mem_addr = u_regval[1] - u_regval[0];
10839 if (ARM_RECORD_STRH == str_type)
10841 record_buf_mem[0] = 2;
10842 record_buf_mem[1] = tgt_mem_addr;
10843 arm_insn_r->mem_rec_count = 1;
10845 else if (ARM_RECORD_STRD == str_type)
10847 record_buf_mem[0] = 4;
10848 record_buf_mem[1] = tgt_mem_addr;
10849 record_buf_mem[2] = 4;
10850 record_buf_mem[3] = tgt_mem_addr + 4;
10851 arm_insn_r->mem_rec_count = 2;
10853 /* Record Rn also as it changes. */
10854 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10855 arm_insn_r->reg_rec_count = 1;
10860 /* Handling ARM extension space insns. */
10863 arm_record_extension_space (insn_decode_record *arm_insn_r)
10865 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10866 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10867 uint32_t record_buf[8], record_buf_mem[8];
10868 uint32_t reg_src1 = 0;
10869 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10870 struct regcache *reg_cache = arm_insn_r->regcache;
10871 ULONGEST u_regval = 0;
10873 gdb_assert (!INSN_RECORDED(arm_insn_r));
10874 /* Handle unconditional insn extension space. */
10876 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10877 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10878 if (arm_insn_r->cond)
10880 /* PLD has no affect on architectural state, it just affects
10882 if (5 == ((opcode1 & 0xE0) >> 5))
10885 record_buf[0] = ARM_PS_REGNUM;
10886 record_buf[1] = ARM_LR_REGNUM;
10887 arm_insn_r->reg_rec_count = 2;
10889 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10893 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10894 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10897 /* Undefined instruction on ARM V5; need to handle if later
10898 versions define it. */
10901 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10902 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10903 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10905 /* Handle arithmetic insn extension space. */
10906 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10907 && !INSN_RECORDED(arm_insn_r))
10909 /* Handle MLA(S) and MUL(S). */
10910 if (0 <= insn_op1 && 3 >= insn_op1)
10912 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10913 record_buf[1] = ARM_PS_REGNUM;
10914 arm_insn_r->reg_rec_count = 2;
10916 else if (4 <= insn_op1 && 15 >= insn_op1)
10918 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10919 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10920 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10921 record_buf[2] = ARM_PS_REGNUM;
10922 arm_insn_r->reg_rec_count = 3;
10926 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10927 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10928 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10930 /* Handle control insn extension space. */
10932 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10933 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10935 if (!bit (arm_insn_r->arm_insn,25))
10937 if (!bits (arm_insn_r->arm_insn, 4, 7))
10939 if ((0 == insn_op1) || (2 == insn_op1))
10942 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10943 arm_insn_r->reg_rec_count = 1;
10945 else if (1 == insn_op1)
10947 /* CSPR is going to be changed. */
10948 record_buf[0] = ARM_PS_REGNUM;
10949 arm_insn_r->reg_rec_count = 1;
10951 else if (3 == insn_op1)
10953 /* SPSR is going to be changed. */
10954 /* We need to get SPSR value, which is yet to be done. */
10955 printf_unfiltered (_("Process record does not support "
10956 "instruction 0x%0x at address %s.\n"),
10957 arm_insn_r->arm_insn,
10958 paddress (arm_insn_r->gdbarch,
10959 arm_insn_r->this_addr));
10963 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10968 record_buf[0] = ARM_PS_REGNUM;
10969 arm_insn_r->reg_rec_count = 1;
10971 else if (3 == insn_op1)
10974 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10975 arm_insn_r->reg_rec_count = 1;
10978 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10981 record_buf[0] = ARM_PS_REGNUM;
10982 record_buf[1] = ARM_LR_REGNUM;
10983 arm_insn_r->reg_rec_count = 2;
10985 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10987 /* QADD, QSUB, QDADD, QDSUB */
10988 record_buf[0] = ARM_PS_REGNUM;
10989 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10990 arm_insn_r->reg_rec_count = 2;
10992 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10995 record_buf[0] = ARM_PS_REGNUM;
10996 record_buf[1] = ARM_LR_REGNUM;
10997 arm_insn_r->reg_rec_count = 2;
10999 /* Save SPSR also;how? */
11000 printf_unfiltered (_("Process record does not support "
11001 "instruction 0x%0x at address %s.\n"),
11002 arm_insn_r->arm_insn,
11003 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11006 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
11007 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
11008 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
11009 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
11012 if (0 == insn_op1 || 1 == insn_op1)
11014 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11015 /* We dont do optimization for SMULW<y> where we
11017 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11018 record_buf[1] = ARM_PS_REGNUM;
11019 arm_insn_r->reg_rec_count = 2;
11021 else if (2 == insn_op1)
11024 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11025 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11026 arm_insn_r->reg_rec_count = 2;
11028 else if (3 == insn_op1)
11031 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11032 arm_insn_r->reg_rec_count = 1;
11038 /* MSR : immediate form. */
11041 /* CSPR is going to be changed. */
11042 record_buf[0] = ARM_PS_REGNUM;
11043 arm_insn_r->reg_rec_count = 1;
11045 else if (3 == insn_op1)
11047 /* SPSR is going to be changed. */
11048 /* we need to get SPSR value, which is yet to be done */
11049 printf_unfiltered (_("Process record does not support "
11050 "instruction 0x%0x at address %s.\n"),
11051 arm_insn_r->arm_insn,
11052 paddress (arm_insn_r->gdbarch,
11053 arm_insn_r->this_addr));
11059 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
11060 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
11061 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
11063 /* Handle load/store insn extension space. */
11065 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
11066 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
11067 && !INSN_RECORDED(arm_insn_r))
11072 /* These insn, changes register and memory as well. */
11073 /* SWP or SWPB insn. */
11074 /* Get memory address given by Rn. */
11075 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11076 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11077 /* SWP insn ?, swaps word. */
11078 if (8 == arm_insn_r->opcode)
11080 record_buf_mem[0] = 4;
11084 /* SWPB insn, swaps only byte. */
11085 record_buf_mem[0] = 1;
11087 record_buf_mem[1] = u_regval;
11088 arm_insn_r->mem_rec_count = 1;
11089 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11090 arm_insn_r->reg_rec_count = 1;
11092 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11095 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11098 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11101 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11102 record_buf[1] = record_buf[0] + 1;
11103 arm_insn_r->reg_rec_count = 2;
11105 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11108 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11111 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
11113 /* LDRH, LDRSB, LDRSH. */
11114 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11115 arm_insn_r->reg_rec_count = 1;
11120 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
11121 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
11122 && !INSN_RECORDED(arm_insn_r))
11125 /* Handle coprocessor insn extension space. */
11128 /* To be done for ARMv5 and later; as of now we return -1. */
11130 printf_unfiltered (_("Process record does not support instruction x%0x "
11131 "at address %s.\n"),arm_insn_r->arm_insn,
11132 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11135 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11136 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11141 /* Handling opcode 000 insns. */
11144 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11146 struct regcache *reg_cache = arm_insn_r->regcache;
11147 uint32_t record_buf[8], record_buf_mem[8];
11148 ULONGEST u_regval[2] = {0};
11150 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11151 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11152 uint32_t opcode1 = 0;
11154 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11155 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11156 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11158 /* Data processing insn /multiply insn. */
11159 if (9 == arm_insn_r->decode
11160 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11161 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11163 /* Handle multiply instructions. */
11164 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11165 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11167 /* Handle MLA and MUL. */
11168 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11169 record_buf[1] = ARM_PS_REGNUM;
11170 arm_insn_r->reg_rec_count = 2;
11172 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11174 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11175 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11176 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11177 record_buf[2] = ARM_PS_REGNUM;
11178 arm_insn_r->reg_rec_count = 3;
11181 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11182 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11184 /* Handle misc load insns, as 20th bit (L = 1). */
11185 /* LDR insn has a capability to do branching, if
11186 MOV LR, PC is precceded by LDR insn having Rn as R15
11187 in that case, it emulates branch and link insn, and hence we
11188 need to save CSPR and PC as well. I am not sure this is right
11189 place; as opcode = 010 LDR insn make this happen, if R15 was
11191 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11192 if (15 != reg_dest)
11194 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11195 arm_insn_r->reg_rec_count = 1;
11199 record_buf[0] = reg_dest;
11200 record_buf[1] = ARM_PS_REGNUM;
11201 arm_insn_r->reg_rec_count = 2;
11204 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11205 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11206 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11207 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11209 /* Handle MSR insn. */
11210 if (9 == arm_insn_r->opcode)
11212 /* CSPR is going to be changed. */
11213 record_buf[0] = ARM_PS_REGNUM;
11214 arm_insn_r->reg_rec_count = 1;
11218 /* SPSR is going to be changed. */
11219 /* How to read SPSR value? */
11220 printf_unfiltered (_("Process record does not support instruction "
11221 "0x%0x at address %s.\n"),
11222 arm_insn_r->arm_insn,
11223 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11227 else if (9 == arm_insn_r->decode
11228 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11229 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11231 /* Handling SWP, SWPB. */
11232 /* These insn, changes register and memory as well. */
11233 /* SWP or SWPB insn. */
11235 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11236 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11237 /* SWP insn ?, swaps word. */
11238 if (8 == arm_insn_r->opcode)
11240 record_buf_mem[0] = 4;
11244 /* SWPB insn, swaps only byte. */
11245 record_buf_mem[0] = 1;
11247 record_buf_mem[1] = u_regval[0];
11248 arm_insn_r->mem_rec_count = 1;
11249 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11250 arm_insn_r->reg_rec_count = 1;
11252 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11253 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11255 /* Handle BLX, branch and link/exchange. */
11256 if (9 == arm_insn_r->opcode)
11258 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11259 and R14 stores the return address. */
11260 record_buf[0] = ARM_PS_REGNUM;
11261 record_buf[1] = ARM_LR_REGNUM;
11262 arm_insn_r->reg_rec_count = 2;
11265 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11267 /* Handle enhanced software breakpoint insn, BKPT. */
11268 /* CPSR is changed to be executed in ARM state, disabling normal
11269 interrupts, entering abort mode. */
11270 /* According to high vector configuration PC is set. */
11271 /* user hit breakpoint and type reverse, in
11272 that case, we need to go back with previous CPSR and
11273 Program Counter. */
11274 record_buf[0] = ARM_PS_REGNUM;
11275 record_buf[1] = ARM_LR_REGNUM;
11276 arm_insn_r->reg_rec_count = 2;
11278 /* Save SPSR also; how? */
11279 printf_unfiltered (_("Process record does not support instruction "
11280 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11281 paddress (arm_insn_r->gdbarch,
11282 arm_insn_r->this_addr));
11285 else if (11 == arm_insn_r->decode
11286 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11288 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11290 /* Handle str(x) insn */
11291 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11294 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11295 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11297 /* Handle BX, branch and link/exchange. */
11298 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11299 record_buf[0] = ARM_PS_REGNUM;
11300 arm_insn_r->reg_rec_count = 1;
11302 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11303 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11304 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11306 /* Count leading zeros: CLZ. */
11307 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11308 arm_insn_r->reg_rec_count = 1;
11310 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11311 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11312 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11313 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11316 /* Handle MRS insn. */
11317 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11318 arm_insn_r->reg_rec_count = 1;
11320 else if (arm_insn_r->opcode <= 15)
11322 /* Normal data processing insns. */
11323 /* Out of 11 shifter operands mode, all the insn modifies destination
11324 register, which is specified by 13-16 decode. */
11325 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11326 record_buf[1] = ARM_PS_REGNUM;
11327 arm_insn_r->reg_rec_count = 2;
11334 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11335 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11339 /* Handling opcode 001 insns. */
11342 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11344 uint32_t record_buf[8], record_buf_mem[8];
11346 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11347 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11349 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11350 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11351 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11354 /* Handle MSR insn. */
11355 if (9 == arm_insn_r->opcode)
11357 /* CSPR is going to be changed. */
11358 record_buf[0] = ARM_PS_REGNUM;
11359 arm_insn_r->reg_rec_count = 1;
11363 /* SPSR is going to be changed. */
11366 else if (arm_insn_r->opcode <= 15)
11368 /* Normal data processing insns. */
11369 /* Out of 11 shifter operands mode, all the insn modifies destination
11370 register, which is specified by 13-16 decode. */
11371 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11372 record_buf[1] = ARM_PS_REGNUM;
11373 arm_insn_r->reg_rec_count = 2;
11380 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11381 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11385 /* Handling opcode 010 insns. */
11388 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11390 struct regcache *reg_cache = arm_insn_r->regcache;
11392 uint32_t reg_src1 = 0 , reg_dest = 0;
11393 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11394 uint32_t record_buf[8], record_buf_mem[8];
11396 ULONGEST u_regval = 0;
11398 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11399 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11401 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11403 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11404 /* LDR insn has a capability to do branching, if
11405 MOV LR, PC is precedded by LDR insn having Rn as R15
11406 in that case, it emulates branch and link insn, and hence we
11407 need to save CSPR and PC as well. */
11408 if (ARM_PC_REGNUM != reg_dest)
11410 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11411 arm_insn_r->reg_rec_count = 1;
11415 record_buf[0] = reg_dest;
11416 record_buf[1] = ARM_PS_REGNUM;
11417 arm_insn_r->reg_rec_count = 2;
11422 /* Store, immediate offset, immediate pre-indexed,
11423 immediate post-indexed. */
11424 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11425 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11426 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11428 if (bit (arm_insn_r->arm_insn, 23))
11430 tgt_mem_addr = u_regval + offset_12;
11434 tgt_mem_addr = u_regval - offset_12;
11437 switch (arm_insn_r->opcode)
11451 record_buf_mem[0] = 4;
11466 record_buf_mem[0] = 1;
11470 gdb_assert_not_reached ("no decoding pattern found");
11473 record_buf_mem[1] = tgt_mem_addr;
11474 arm_insn_r->mem_rec_count = 1;
11476 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11477 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11478 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11479 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11480 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11481 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11484 /* We are handling pre-indexed mode; post-indexed mode;
11485 where Rn is going to be changed. */
11486 record_buf[0] = reg_src1;
11487 arm_insn_r->reg_rec_count = 1;
11491 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11492 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11496 /* Handling opcode 011 insns. */
11499 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11501 struct regcache *reg_cache = arm_insn_r->regcache;
11503 uint32_t shift_imm = 0;
11504 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11505 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11506 uint32_t record_buf[8], record_buf_mem[8];
11509 ULONGEST u_regval[2];
11511 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11512 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11514 /* Handle enhanced store insns and LDRD DSP insn,
11515 order begins according to addressing modes for store insns
11519 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11521 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11522 /* LDR insn has a capability to do branching, if
11523 MOV LR, PC is precedded by LDR insn having Rn as R15
11524 in that case, it emulates branch and link insn, and hence we
11525 need to save CSPR and PC as well. */
11526 if (15 != reg_dest)
11528 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11529 arm_insn_r->reg_rec_count = 1;
11533 record_buf[0] = reg_dest;
11534 record_buf[1] = ARM_PS_REGNUM;
11535 arm_insn_r->reg_rec_count = 2;
11540 if (! bits (arm_insn_r->arm_insn, 4, 11))
11542 /* Store insn, register offset and register pre-indexed,
11543 register post-indexed. */
11545 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11547 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11548 regcache_raw_read_unsigned (reg_cache, reg_src1
11550 regcache_raw_read_unsigned (reg_cache, reg_src2
11552 if (15 == reg_src2)
11554 /* If R15 was used as Rn, hence current PC+8. */
11555 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11556 u_regval[0] = u_regval[0] + 8;
11558 /* Calculate target store address, Rn +/- Rm, register offset. */
11560 if (bit (arm_insn_r->arm_insn, 23))
11562 tgt_mem_addr = u_regval[0] + u_regval[1];
11566 tgt_mem_addr = u_regval[1] - u_regval[0];
11569 switch (arm_insn_r->opcode)
11583 record_buf_mem[0] = 4;
11598 record_buf_mem[0] = 1;
11602 gdb_assert_not_reached ("no decoding pattern found");
11605 record_buf_mem[1] = tgt_mem_addr;
11606 arm_insn_r->mem_rec_count = 1;
11608 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11609 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11610 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11611 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11612 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11613 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11616 /* Rn is going to be changed in pre-indexed mode and
11617 post-indexed mode as well. */
11618 record_buf[0] = reg_src2;
11619 arm_insn_r->reg_rec_count = 1;
11624 /* Store insn, scaled register offset; scaled pre-indexed. */
11625 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11627 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11629 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11630 /* Get shift_imm. */
11631 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11632 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11633 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11634 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11635 /* Offset_12 used as shift. */
11639 /* Offset_12 used as index. */
11640 offset_12 = u_regval[0] << shift_imm;
11644 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11650 if (bit (u_regval[0], 31))
11652 offset_12 = 0xFFFFFFFF;
11661 /* This is arithmetic shift. */
11662 offset_12 = s_word >> shift_imm;
11669 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11671 /* Get C flag value and shift it by 31. */
11672 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11673 | (u_regval[0]) >> 1);
11677 offset_12 = (u_regval[0] >> shift_imm) \
11679 (sizeof(uint32_t) - shift_imm));
11684 gdb_assert_not_reached ("no decoding pattern found");
11688 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11690 if (bit (arm_insn_r->arm_insn, 23))
11692 tgt_mem_addr = u_regval[1] + offset_12;
11696 tgt_mem_addr = u_regval[1] - offset_12;
11699 switch (arm_insn_r->opcode)
11713 record_buf_mem[0] = 4;
11728 record_buf_mem[0] = 1;
11732 gdb_assert_not_reached ("no decoding pattern found");
11735 record_buf_mem[1] = tgt_mem_addr;
11736 arm_insn_r->mem_rec_count = 1;
11738 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11739 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11740 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11741 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11742 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11743 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11746 /* Rn is going to be changed in register scaled pre-indexed
11747 mode,and scaled post indexed mode. */
11748 record_buf[0] = reg_src2;
11749 arm_insn_r->reg_rec_count = 1;
11754 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11755 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11759 /* Handling opcode 100 insns. */
11762 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11764 struct regcache *reg_cache = arm_insn_r->regcache;
11766 uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0;
11767 uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0;
11768 uint32_t start_address = 0, index = 0;
11769 uint32_t record_buf[24], record_buf_mem[48];
11771 ULONGEST u_regval[2] = {0};
11773 /* This mode is exclusively for load and store multiple. */
11774 /* Handle incremenrt after/before and decrment after.before mode;
11775 Rn is changing depending on W bit, but as of now we store Rn too
11776 without optimization. */
11778 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11780 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11782 if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22))
11784 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11789 register_bits = bits (arm_insn_r->arm_insn, 0, 14);
11793 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11794 while (register_bits)
11796 if (register_bits & 0x00000001)
11797 register_list[register_count++] = 1;
11798 register_bits = register_bits >> 1;
11801 /* Extra space for Base Register and CPSR; wihtout optimization. */
11802 record_buf[register_count] = reg_src1;
11803 record_buf[register_count + 1] = ARM_PS_REGNUM;
11804 arm_insn_r->reg_rec_count = register_count + 2;
11806 for (register_count = 0; register_count < no_of_regs; register_count++)
11808 if (register_list[register_count])
11810 /* Register_count gives total no of registers
11811 and dually working as reg number. */
11812 record_buf[index] = register_count;
11820 /* It handles both STM(1) and STM(2). */
11821 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11823 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11825 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11826 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11827 while (register_bits)
11829 if (register_bits & 0x00000001)
11831 register_bits = register_bits >> 1;
11836 /* Decrement after. */
11838 start_address = (u_regval[0]) - (register_count * 4) + 4;
11839 arm_insn_r->mem_rec_count = register_count;
11840 while (register_count)
11842 record_buf_mem[(register_count * 2) - 1] = start_address;
11843 record_buf_mem[(register_count * 2) - 2] = 4;
11844 start_address = start_address + 4;
11849 /* Increment after. */
11851 start_address = u_regval[0];
11852 arm_insn_r->mem_rec_count = register_count;
11853 while (register_count)
11855 record_buf_mem[(register_count * 2) - 1] = start_address;
11856 record_buf_mem[(register_count * 2) - 2] = 4;
11857 start_address = start_address + 4;
11862 /* Decrement before. */
11865 start_address = (u_regval[0]) - (register_count * 4);
11866 arm_insn_r->mem_rec_count = register_count;
11867 while (register_count)
11869 record_buf_mem[(register_count * 2) - 1] = start_address;
11870 record_buf_mem[(register_count * 2) - 2] = 4;
11871 start_address = start_address + 4;
11876 /* Increment before. */
11878 start_address = u_regval[0] + 4;
11879 arm_insn_r->mem_rec_count = register_count;
11880 while (register_count)
11882 record_buf_mem[(register_count * 2) - 1] = start_address;
11883 record_buf_mem[(register_count * 2) - 2] = 4;
11884 start_address = start_address + 4;
11890 gdb_assert_not_reached ("no decoding pattern found");
11894 /* Base register also changes; based on condition and W bit. */
11895 /* We save it anyway without optimization. */
11896 record_buf[0] = reg_src1;
11897 arm_insn_r->reg_rec_count = 1;
11900 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11901 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11905 /* Handling opcode 101 insns. */
11908 arm_record_b_bl (insn_decode_record *arm_insn_r)
11910 uint32_t record_buf[8];
11912 /* Handle B, BL, BLX(1) insns. */
11913 /* B simply branches so we do nothing here. */
11914 /* Note: BLX(1) doesnt fall here but instead it falls into
11915 extension space. */
11916 if (bit (arm_insn_r->arm_insn, 24))
11918 record_buf[0] = ARM_LR_REGNUM;
11919 arm_insn_r->reg_rec_count = 1;
11922 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11927 /* Handling opcode 110 insns. */
11930 arm_record_coproc (insn_decode_record *arm_insn_r)
11932 printf_unfiltered (_("Process record does not support instruction "
11933 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11934 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11939 /* Handling opcode 111 insns. */
11942 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11944 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11945 struct regcache *reg_cache = arm_insn_r->regcache;
11946 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
11948 /* Handle SWI insn; system call would be handled over here. */
11950 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11951 if (15 == arm_insn_r->opcode)
11953 /* Handle arm syscall insn. */
11954 if (tdep->arm_swi_record != NULL)
11956 ret = tdep->arm_swi_record(reg_cache);
11960 printf_unfiltered (_("no syscall record support\n"));
11965 printf_unfiltered (_("Process record does not support instruction "
11966 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11967 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11971 /* Handling opcode 000 insns. */
11974 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11976 uint32_t record_buf[8];
11977 uint32_t reg_src1 = 0;
11979 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11981 record_buf[0] = ARM_PS_REGNUM;
11982 record_buf[1] = reg_src1;
11983 thumb_insn_r->reg_rec_count = 2;
11985 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11991 /* Handling opcode 001 insns. */
11994 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11996 uint32_t record_buf[8];
11997 uint32_t reg_src1 = 0;
11999 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12001 record_buf[0] = ARM_PS_REGNUM;
12002 record_buf[1] = reg_src1;
12003 thumb_insn_r->reg_rec_count = 2;
12005 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12010 /* Handling opcode 010 insns. */
12013 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
12015 struct regcache *reg_cache = thumb_insn_r->regcache;
12016 uint32_t record_buf[8], record_buf_mem[8];
12018 uint32_t reg_src1 = 0, reg_src2 = 0;
12019 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12021 ULONGEST u_regval[2] = {0};
12023 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
12025 if (bit (thumb_insn_r->arm_insn, 12))
12027 /* Handle load/store register offset. */
12028 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
12029 if (opcode2 >= 12 && opcode2 <= 15)
12031 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12032 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
12033 record_buf[0] = reg_src1;
12034 thumb_insn_r->reg_rec_count = 1;
12036 else if (opcode2 >= 8 && opcode2 <= 10)
12038 /* STR(2), STRB(2), STRH(2) . */
12039 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12040 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
12041 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
12042 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
12044 record_buf_mem[0] = 4; /* STR (2). */
12045 else if (10 == opcode2)
12046 record_buf_mem[0] = 1; /* STRB (2). */
12047 else if (9 == opcode2)
12048 record_buf_mem[0] = 2; /* STRH (2). */
12049 record_buf_mem[1] = u_regval[0] + u_regval[1];
12050 thumb_insn_r->mem_rec_count = 1;
12053 else if (bit (thumb_insn_r->arm_insn, 11))
12055 /* Handle load from literal pool. */
12057 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12058 record_buf[0] = reg_src1;
12059 thumb_insn_r->reg_rec_count = 1;
12063 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
12064 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
12065 if ((3 == opcode2) && (!opcode3))
12067 /* Branch with exchange. */
12068 record_buf[0] = ARM_PS_REGNUM;
12069 thumb_insn_r->reg_rec_count = 1;
12073 /* Format 8; special data processing insns. */
12074 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12075 record_buf[0] = ARM_PS_REGNUM;
12076 record_buf[1] = reg_src1;
12077 thumb_insn_r->reg_rec_count = 2;
12082 /* Format 5; data processing insns. */
12083 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12084 if (bit (thumb_insn_r->arm_insn, 7))
12086 reg_src1 = reg_src1 + 8;
12088 record_buf[0] = ARM_PS_REGNUM;
12089 record_buf[1] = reg_src1;
12090 thumb_insn_r->reg_rec_count = 2;
12093 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12094 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12100 /* Handling opcode 001 insns. */
12103 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
12105 struct regcache *reg_cache = thumb_insn_r->regcache;
12106 uint32_t record_buf[8], record_buf_mem[8];
12108 uint32_t reg_src1 = 0;
12109 uint32_t opcode = 0, immed_5 = 0;
12111 ULONGEST u_regval = 0;
12113 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12118 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12119 record_buf[0] = reg_src1;
12120 thumb_insn_r->reg_rec_count = 1;
12125 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12126 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12127 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12128 record_buf_mem[0] = 4;
12129 record_buf_mem[1] = u_regval + (immed_5 * 4);
12130 thumb_insn_r->mem_rec_count = 1;
12133 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12134 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12140 /* Handling opcode 100 insns. */
12143 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12145 struct regcache *reg_cache = thumb_insn_r->regcache;
12146 uint32_t record_buf[8], record_buf_mem[8];
12148 uint32_t reg_src1 = 0;
12149 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12151 ULONGEST u_regval = 0;
12153 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12158 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12159 record_buf[0] = reg_src1;
12160 thumb_insn_r->reg_rec_count = 1;
12162 else if (1 == opcode)
12165 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12166 record_buf[0] = reg_src1;
12167 thumb_insn_r->reg_rec_count = 1;
12169 else if (2 == opcode)
12172 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12173 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12174 record_buf_mem[0] = 4;
12175 record_buf_mem[1] = u_regval + (immed_8 * 4);
12176 thumb_insn_r->mem_rec_count = 1;
12178 else if (0 == opcode)
12181 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12182 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12183 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12184 record_buf_mem[0] = 2;
12185 record_buf_mem[1] = u_regval + (immed_5 * 2);
12186 thumb_insn_r->mem_rec_count = 1;
12189 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12190 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12196 /* Handling opcode 101 insns. */
12199 thumb_record_misc (insn_decode_record *thumb_insn_r)
12201 struct regcache *reg_cache = thumb_insn_r->regcache;
12203 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12204 uint32_t register_bits = 0, register_count = 0;
12205 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12206 uint32_t record_buf[24], record_buf_mem[48];
12209 ULONGEST u_regval = 0;
12211 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12212 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12213 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12218 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12219 while (register_bits)
12221 if (register_bits & 0x00000001)
12222 register_list[register_count++] = 1;
12223 register_bits = register_bits >> 1;
12225 record_buf[register_count] = ARM_PS_REGNUM;
12226 record_buf[register_count + 1] = ARM_SP_REGNUM;
12227 thumb_insn_r->reg_rec_count = register_count + 2;
12228 for (register_count = 0; register_count < 8; register_count++)
12230 if (register_list[register_count])
12232 record_buf[index] = register_count;
12237 else if (10 == opcode2)
12240 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12241 regcache_raw_read_unsigned (reg_cache, ARM_PC_REGNUM, &u_regval);
12242 while (register_bits)
12244 if (register_bits & 0x00000001)
12246 register_bits = register_bits >> 1;
12248 start_address = u_regval - \
12249 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12250 thumb_insn_r->mem_rec_count = register_count;
12251 while (register_count)
12253 record_buf_mem[(register_count * 2) - 1] = start_address;
12254 record_buf_mem[(register_count * 2) - 2] = 4;
12255 start_address = start_address + 4;
12258 record_buf[0] = ARM_SP_REGNUM;
12259 thumb_insn_r->reg_rec_count = 1;
12261 else if (0x1E == opcode1)
12264 /* Handle enhanced software breakpoint insn, BKPT. */
12265 /* CPSR is changed to be executed in ARM state, disabling normal
12266 interrupts, entering abort mode. */
12267 /* According to high vector configuration PC is set. */
12268 /* User hits breakpoint and type reverse, in that case, we need to go back with
12269 previous CPSR and Program Counter. */
12270 record_buf[0] = ARM_PS_REGNUM;
12271 record_buf[1] = ARM_LR_REGNUM;
12272 thumb_insn_r->reg_rec_count = 2;
12273 /* We need to save SPSR value, which is not yet done. */
12274 printf_unfiltered (_("Process record does not support instruction "
12275 "0x%0x at address %s.\n"),
12276 thumb_insn_r->arm_insn,
12277 paddress (thumb_insn_r->gdbarch,
12278 thumb_insn_r->this_addr));
12281 else if ((0 == opcode) || (1 == opcode))
12283 /* ADD(5), ADD(6). */
12284 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12285 record_buf[0] = reg_src1;
12286 thumb_insn_r->reg_rec_count = 1;
12288 else if (2 == opcode)
12290 /* ADD(7), SUB(4). */
12291 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12292 record_buf[0] = ARM_SP_REGNUM;
12293 thumb_insn_r->reg_rec_count = 1;
12296 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12297 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12303 /* Handling opcode 110 insns. */
12306 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12308 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12309 struct regcache *reg_cache = thumb_insn_r->regcache;
12311 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12312 uint32_t reg_src1 = 0;
12313 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12314 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12315 uint32_t record_buf[24], record_buf_mem[48];
12317 ULONGEST u_regval = 0;
12319 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12320 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12326 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12328 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12329 while (register_bits)
12331 if (register_bits & 0x00000001)
12332 register_list[register_count++] = 1;
12333 register_bits = register_bits >> 1;
12335 record_buf[register_count] = reg_src1;
12336 thumb_insn_r->reg_rec_count = register_count + 1;
12337 for (register_count = 0; register_count < 8; register_count++)
12339 if (register_list[register_count])
12341 record_buf[index] = register_count;
12346 else if (0 == opcode2)
12348 /* It handles both STMIA. */
12349 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12351 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12352 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12353 while (register_bits)
12355 if (register_bits & 0x00000001)
12357 register_bits = register_bits >> 1;
12359 start_address = u_regval;
12360 thumb_insn_r->mem_rec_count = register_count;
12361 while (register_count)
12363 record_buf_mem[(register_count * 2) - 1] = start_address;
12364 record_buf_mem[(register_count * 2) - 2] = 4;
12365 start_address = start_address + 4;
12369 else if (0x1F == opcode1)
12371 /* Handle arm syscall insn. */
12372 if (tdep->arm_swi_record != NULL)
12374 ret = tdep->arm_swi_record(reg_cache);
12378 printf_unfiltered (_("no syscall record support\n"));
12383 /* B (1), conditional branch is automatically taken care in process_record,
12384 as PC is saved there. */
12386 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12387 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12393 /* Handling opcode 111 insns. */
12396 thumb_record_branch (insn_decode_record *thumb_insn_r)
12398 uint32_t record_buf[8];
12399 uint32_t bits_h = 0;
12401 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12403 if (2 == bits_h || 3 == bits_h)
12406 record_buf[0] = ARM_LR_REGNUM;
12407 thumb_insn_r->reg_rec_count = 1;
12409 else if (1 == bits_h)
12412 record_buf[0] = ARM_PS_REGNUM;
12413 record_buf[1] = ARM_LR_REGNUM;
12414 thumb_insn_r->reg_rec_count = 2;
12417 /* B(2) is automatically taken care in process_record, as PC is
12420 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12426 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12427 and positive val on fauilure. */
12430 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12432 gdb_byte buf[insn_size];
12434 memset (&buf[0], 0, insn_size);
12436 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12438 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12440 gdbarch_byte_order (insn_record->gdbarch));
12444 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12446 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12450 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12451 uint32_t insn_size)
12454 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12455 static const sti_arm_hdl_fp_t const arm_handle_insn[8] =
12457 arm_record_data_proc_misc_ld_str, /* 000. */
12458 arm_record_data_proc_imm, /* 001. */
12459 arm_record_ld_st_imm_offset, /* 010. */
12460 arm_record_ld_st_reg_offset, /* 011. */
12461 arm_record_ld_st_multiple, /* 100. */
12462 arm_record_b_bl, /* 101. */
12463 arm_record_coproc, /* 110. */
12464 arm_record_coproc_data_proc /* 111. */
12467 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12468 static const sti_arm_hdl_fp_t const thumb_handle_insn[8] =
12470 thumb_record_shift_add_sub, /* 000. */
12471 thumb_record_add_sub_cmp_mov, /* 001. */
12472 thumb_record_ld_st_reg_offset, /* 010. */
12473 thumb_record_ld_st_imm_offset, /* 011. */
12474 thumb_record_ld_st_stack, /* 100. */
12475 thumb_record_misc, /* 101. */
12476 thumb_record_ldm_stm_swi, /* 110. */
12477 thumb_record_branch /* 111. */
12480 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12481 uint32_t insn_id = 0;
12483 if (extract_arm_insn (arm_record, insn_size))
12487 printf_unfiltered (_("Process record: error reading memory at "
12488 "addr %s len = %d.\n"),
12489 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
12493 else if (ARM_RECORD == record_type)
12495 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12496 insn_id = bits (arm_record->arm_insn, 25, 27);
12497 ret = arm_record_extension_space (arm_record);
12498 /* If this insn has fallen into extension space
12499 then we need not decode it anymore. */
12500 if (ret != -1 && !INSN_RECORDED(arm_record))
12502 ret = arm_handle_insn[insn_id] (arm_record);
12505 else if (THUMB_RECORD == record_type)
12507 /* As thumb does not have condition codes, we set negative. */
12508 arm_record->cond = -1;
12509 insn_id = bits (arm_record->arm_insn, 13, 15);
12510 ret = thumb_handle_insn[insn_id] (arm_record);
12512 else if (THUMB2_RECORD == record_type)
12514 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12515 "0x%0x at address %s.\n"),arm_record->arm_insn,
12516 paddress (arm_record->gdbarch,
12517 arm_record->this_addr));
12522 /* Throw assertion. */
12523 gdb_assert_not_reached ("not a valid instruction, could not decode");
12530 /* Cleans up local record registers and memory allocations. */
12533 deallocate_reg_mem (insn_decode_record *record)
12535 xfree (record->arm_regs);
12536 xfree (record->arm_mems);
12540 /* Parse the current instruction and record the values of the registers and
12541 memory that will be changed in current instruction to record_arch_list".
12542 Return -1 if something is wrong. */
12545 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
12546 CORE_ADDR insn_addr)
12549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
12550 uint32_t no_of_rec = 0;
12551 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
12552 ULONGEST t_bit = 0, insn_id = 0;
12554 ULONGEST u_regval = 0;
12556 insn_decode_record arm_record;
12558 memset (&arm_record, 0, sizeof (insn_decode_record));
12559 arm_record.regcache = regcache;
12560 arm_record.this_addr = insn_addr;
12561 arm_record.gdbarch = gdbarch;
12564 if (record_debug > 1)
12566 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
12568 paddress (gdbarch, arm_record.this_addr));
12571 if (extract_arm_insn (&arm_record, 2))
12575 printf_unfiltered (_("Process record: error reading memory at "
12576 "addr %s len = %d.\n"),
12577 paddress (arm_record.gdbarch,
12578 arm_record.this_addr), 2);
12583 /* Check the insn, whether it is thumb or arm one. */
12585 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
12586 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
12589 if (!(u_regval & t_bit))
12591 /* We are decoding arm insn. */
12592 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
12596 insn_id = bits (arm_record.arm_insn, 11, 15);
12597 /* is it thumb2 insn? */
12598 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
12600 ret = decode_insn (&arm_record, THUMB2_RECORD,
12601 THUMB2_INSN_SIZE_BYTES);
12605 /* We are decoding thumb insn. */
12606 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
12612 /* Record registers. */
12613 record_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
12614 if (arm_record.arm_regs)
12616 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
12618 if (record_arch_list_add_reg (arm_record.regcache ,
12619 arm_record.arm_regs[no_of_rec]))
12623 /* Record memories. */
12624 if (arm_record.arm_mems)
12626 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
12628 if (record_arch_list_add_mem
12629 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
12630 arm_record.arm_mems[no_of_rec].len))
12635 if (record_arch_list_add_end ())
12640 deallocate_reg_mem (&arm_record);