1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
63 #include "features/arm/arm-with-m.c"
64 #include "features/arm/arm-with-m-fpa-layout.c"
65 #include "features/arm/arm-with-m-vfp-d16.c"
66 #include "features/arm/arm-with-iwmmxt.c"
67 #include "features/arm/arm-with-vfpv2.c"
68 #include "features/arm/arm-with-vfpv3.c"
69 #include "features/arm/arm-with-neon.c"
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose.
77 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
78 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
80 #define MSYMBOL_SET_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym) = 1
83 #define MSYMBOL_IS_SPECIAL(msym) \
84 MSYMBOL_TARGET_FLAG_1 (msym)
86 /* Per-objfile data used for mapping symbols. */
87 static const struct objfile_data *arm_objfile_data_key;
89 struct arm_mapping_symbol
94 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
95 DEF_VEC_O(arm_mapping_symbol_s);
97 struct arm_per_objfile
99 VEC(arm_mapping_symbol_s) **section_maps;
102 /* The list of available "set arm ..." and "show arm ..." commands. */
103 static struct cmd_list_element *setarmcmdlist = NULL;
104 static struct cmd_list_element *showarmcmdlist = NULL;
106 /* The type of floating-point to use. Keep this in sync with enum
107 arm_float_model, and the help string in _initialize_arm_tdep. */
108 static const char *const fp_model_strings[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
120 static const char *current_fp_model = "auto";
122 /* The ABI to use. Keep this in sync with arm_abi_kind. */
123 static const char *const arm_abi_strings[] =
131 /* A variable that can be configured by the user. */
132 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
133 static const char *arm_abi_string = "auto";
135 /* The execution mode to assume. */
136 static const char *const arm_mode_strings[] =
144 static const char *arm_fallback_mode_string = "auto";
145 static const char *arm_force_mode_string = "auto";
147 /* Number of different reg name sets (options). */
148 static int num_disassembly_options;
150 /* The standard register names, and all the valid aliases for them. Note
151 that `fp', `sp' and `pc' are not added in this alias list, because they
152 have been added as builtin user registers in
153 std-regs.c:_initialize_frame_reg. */
158 } arm_register_aliases[] = {
159 /* Basic register numbers. */
176 /* Synonyms (argument and variable registers). */
189 /* Other platform-specific names for r9. */
195 /* Names used by GCC (not listed in the ARM EABI). */
197 /* A special name from the older ATPCS. */
201 static const char *const arm_register_names[] =
202 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
203 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
204 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
205 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
206 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
207 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
208 "fps", "cpsr" }; /* 24 25 */
210 /* Valid register name styles. */
211 static const char **valid_disassembly_styles;
213 /* Disassembly style to use. Default to "std" register names. */
214 static const char *disassembly_style;
216 /* This is used to keep the bfd arch_info in sync with the disassembly
218 static void set_disassembly_style_sfunc(char *, int,
219 struct cmd_list_element *);
220 static void set_disassembly_style (void);
222 static void convert_from_extended (const struct floatformat *, const void *,
224 static void convert_to_extended (const struct floatformat *, void *,
227 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
228 struct regcache *regcache,
229 int regnum, gdb_byte *buf);
230 static void arm_neon_quad_write (struct gdbarch *gdbarch,
231 struct regcache *regcache,
232 int regnum, const gdb_byte *buf);
235 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self);
238 /* get_next_pcs operations. */
239 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = {
240 arm_get_next_pcs_read_memory_unsigned_integer,
241 arm_get_next_pcs_syscall_next_pc,
242 arm_get_next_pcs_addr_bits_remove,
243 arm_get_next_pcs_is_thumb,
247 struct arm_prologue_cache
249 /* The stack pointer at the time this frame was created; i.e. the
250 caller's stack pointer when this function was called. It is used
251 to identify this frame. */
254 /* The frame base for this frame is just prev_sp - frame size.
255 FRAMESIZE is the distance from the frame pointer to the
256 initial stack pointer. */
260 /* The register used to hold the frame pointer for this frame. */
263 /* Saved register offsets. */
264 struct trad_frame_saved_reg *saved_regs;
267 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
268 CORE_ADDR prologue_start,
269 CORE_ADDR prologue_end,
270 struct arm_prologue_cache *cache);
272 /* Architecture version for displaced stepping. This effects the behaviour of
273 certain instructions, and really should not be hard-wired. */
275 #define DISPLACED_STEPPING_ARCH_VERSION 5
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch *gdbarch)
286 if (gdbarch_tdep (gdbarch)->is_m)
292 /* Determine if the processor is currently executing in Thumb mode. */
295 arm_is_thumb (struct regcache *regcache)
298 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
300 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
302 return (cpsr & t_bit) != 0;
305 /* Determine if FRAME is executing in Thumb mode. */
308 arm_frame_is_thumb (struct frame_info *frame)
311 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
313 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
314 directly (from a signal frame or dummy frame) or by interpreting
315 the saved LR (from a prologue or DWARF frame). So consult it and
316 trust the unwinders. */
317 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
319 return (cpsr & t_bit) != 0;
322 /* Callback for VEC_lower_bound. */
325 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
326 const struct arm_mapping_symbol *rhs)
328 return lhs->value < rhs->value;
331 /* Search for the mapping symbol covering MEMADDR. If one is found,
332 return its type. Otherwise, return 0. If START is non-NULL,
333 set *START to the location of the mapping symbol. */
336 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
338 struct obj_section *sec;
340 /* If there are mapping symbols, consult them. */
341 sec = find_pc_section (memaddr);
344 struct arm_per_objfile *data;
345 VEC(arm_mapping_symbol_s) *map;
346 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
350 data = (struct arm_per_objfile *) objfile_data (sec->objfile,
351 arm_objfile_data_key);
354 map = data->section_maps[sec->the_bfd_section->index];
355 if (!VEC_empty (arm_mapping_symbol_s, map))
357 struct arm_mapping_symbol *map_sym;
359 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
360 arm_compare_mapping_symbols);
362 /* VEC_lower_bound finds the earliest ordered insertion
363 point. If the following symbol starts at this exact
364 address, we use that; otherwise, the preceding
365 mapping symbol covers this address. */
366 if (idx < VEC_length (arm_mapping_symbol_s, map))
368 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
369 if (map_sym->value == map_key.value)
372 *start = map_sym->value + obj_section_addr (sec);
373 return map_sym->type;
379 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
381 *start = map_sym->value + obj_section_addr (sec);
382 return map_sym->type;
391 /* Determine if the program counter specified in MEMADDR is in a Thumb
392 function. This function should be called for addresses unrelated to
393 any executing frame; otherwise, prefer arm_frame_is_thumb. */
396 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
398 struct bound_minimal_symbol sym;
400 struct displaced_step_closure* dsc
401 = get_displaced_step_closure_by_addr(memaddr);
403 /* If checking the mode of displaced instruction in copy area, the mode
404 should be determined by instruction on the original address. */
408 fprintf_unfiltered (gdb_stdlog,
409 "displaced: check mode of %.8lx instead of %.8lx\n",
410 (unsigned long) dsc->insn_addr,
411 (unsigned long) memaddr);
412 memaddr = dsc->insn_addr;
415 /* If bit 0 of the address is set, assume this is a Thumb address. */
416 if (IS_THUMB_ADDR (memaddr))
419 /* If the user wants to override the symbol table, let him. */
420 if (strcmp (arm_force_mode_string, "arm") == 0)
422 if (strcmp (arm_force_mode_string, "thumb") == 0)
425 /* ARM v6-M and v7-M are always in Thumb mode. */
426 if (gdbarch_tdep (gdbarch)->is_m)
429 /* If there are mapping symbols, consult them. */
430 type = arm_find_mapping_symbol (memaddr, NULL);
434 /* Thumb functions have a "special" bit set in minimal symbols. */
435 sym = lookup_minimal_symbol_by_pc (memaddr);
437 return (MSYMBOL_IS_SPECIAL (sym.minsym));
439 /* If the user wants to override the fallback mode, let them. */
440 if (strcmp (arm_fallback_mode_string, "arm") == 0)
442 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
445 /* If we couldn't find any symbol, but we're talking to a running
446 target, then trust the current value of $cpsr. This lets
447 "display/i $pc" always show the correct mode (though if there is
448 a symbol table we will not reach here, so it still may not be
449 displayed in the mode it will be executed). */
450 if (target_has_registers)
451 return arm_frame_is_thumb (get_current_frame ());
453 /* Otherwise we're out of luck; we assume ARM. */
457 /* Determine if the address specified equals any of these magic return
458 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
461 From ARMv6-M Reference Manual B1.5.8
462 Table B1-5 Exception return behavior
464 EXC_RETURN Return To Return Stack
465 0xFFFFFFF1 Handler mode Main
466 0xFFFFFFF9 Thread mode Main
467 0xFFFFFFFD Thread mode Process
469 From ARMv7-M Reference Manual B1.5.8
470 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
472 EXC_RETURN Return To Return Stack
473 0xFFFFFFF1 Handler mode Main
474 0xFFFFFFF9 Thread mode Main
475 0xFFFFFFFD Thread mode Process
477 Table B1-9 EXC_RETURN definition of exception return behavior, with
480 EXC_RETURN Return To Return Stack Frame Type
481 0xFFFFFFE1 Handler mode Main Extended
482 0xFFFFFFE9 Thread mode Main Extended
483 0xFFFFFFED Thread mode Process Extended
484 0xFFFFFFF1 Handler mode Main Basic
485 0xFFFFFFF9 Thread mode Main Basic
486 0xFFFFFFFD Thread mode Process Basic
488 For more details see "B1.5.8 Exception return behavior"
489 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
492 arm_m_addr_is_magic (CORE_ADDR addr)
496 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
497 the exception return behavior. */
504 /* Address is magic. */
508 /* Address is not magic. */
513 /* Remove useless bits from addresses in a running program. */
515 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
517 /* On M-profile devices, do not strip the low bit from EXC_RETURN
518 (the magic exception return address). */
519 if (gdbarch_tdep (gdbarch)->is_m
520 && arm_m_addr_is_magic (val))
524 return UNMAKE_THUMB_ADDR (val);
526 return (val & 0x03fffffc);
529 /* Return 1 if PC is the start of a compiler helper function which
530 can be safely ignored during prologue skipping. IS_THUMB is true
531 if the function is known to be a Thumb function due to the way it
534 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
536 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
537 struct bound_minimal_symbol msym;
539 msym = lookup_minimal_symbol_by_pc (pc);
540 if (msym.minsym != NULL
541 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
542 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
544 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
546 /* The GNU linker's Thumb call stub to foo is named
548 if (strstr (name, "_from_thumb") != NULL)
551 /* On soft-float targets, __truncdfsf2 is called to convert promoted
552 arguments to their argument types in non-prototyped
554 if (startswith (name, "__truncdfsf2"))
556 if (startswith (name, "__aeabi_d2f"))
559 /* Internal functions related to thread-local storage. */
560 if (startswith (name, "__tls_get_addr"))
562 if (startswith (name, "__aeabi_read_tp"))
567 /* If we run against a stripped glibc, we may be unable to identify
568 special functions by name. Check for one important case,
569 __aeabi_read_tp, by comparing the *code* against the default
570 implementation (this is hand-written ARM assembler in glibc). */
573 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
574 == 0xe3e00a0f /* mov r0, #0xffff0fff */
575 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
576 == 0xe240f01f) /* sub pc, r0, #31 */
583 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
584 the first 16-bit of instruction, and INSN2 is the second 16-bit of
586 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
587 ((bits ((insn1), 0, 3) << 12) \
588 | (bits ((insn1), 10, 10) << 11) \
589 | (bits ((insn2), 12, 14) << 8) \
590 | bits ((insn2), 0, 7))
592 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
593 the 32-bit instruction. */
594 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
595 ((bits ((insn), 16, 19) << 12) \
596 | bits ((insn), 0, 11))
598 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
601 thumb_expand_immediate (unsigned int imm)
603 unsigned int count = imm >> 7;
611 return (imm & 0xff) | ((imm & 0xff) << 16);
613 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
615 return (imm & 0xff) | ((imm & 0xff) << 8)
616 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
619 return (0x80 | (imm & 0x7f)) << (32 - count);
622 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
623 epilogue, 0 otherwise. */
626 thumb_instruction_restores_sp (unsigned short insn)
628 return (insn == 0x46bd /* mov sp, r7 */
629 || (insn & 0xff80) == 0xb000 /* add sp, imm */
630 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
633 /* Analyze a Thumb prologue, looking for a recognizable stack frame
634 and frame pointer. Scan until we encounter a store that could
635 clobber the stack frame unexpectedly, or an unknown instruction.
636 Return the last address which is definitely safe to skip for an
637 initial breakpoint. */
640 thumb_analyze_prologue (struct gdbarch *gdbarch,
641 CORE_ADDR start, CORE_ADDR limit,
642 struct arm_prologue_cache *cache)
644 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
645 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
648 struct pv_area *stack;
649 struct cleanup *back_to;
651 CORE_ADDR unrecognized_pc = 0;
653 for (i = 0; i < 16; i++)
654 regs[i] = pv_register (i, 0);
655 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
656 back_to = make_cleanup_free_pv_area (stack);
658 while (start < limit)
662 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
664 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
669 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
672 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
673 whether to save LR (R14). */
674 mask = (insn & 0xff) | ((insn & 0x100) << 6);
676 /* Calculate offsets of saved R0-R7 and LR. */
677 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
678 if (mask & (1 << regno))
680 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
682 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
685 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
687 offset = (insn & 0x7f) << 2; /* get scaled offset */
688 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
691 else if (thumb_instruction_restores_sp (insn))
693 /* Don't scan past the epilogue. */
696 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
697 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
699 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
700 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
701 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
703 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
704 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
705 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
707 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
708 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
709 && pv_is_constant (regs[bits (insn, 3, 5)]))
710 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
711 regs[bits (insn, 6, 8)]);
712 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
713 && pv_is_constant (regs[bits (insn, 3, 6)]))
715 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
716 int rm = bits (insn, 3, 6);
717 regs[rd] = pv_add (regs[rd], regs[rm]);
719 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
721 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
722 int src_reg = (insn & 0x78) >> 3;
723 regs[dst_reg] = regs[src_reg];
725 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
727 /* Handle stores to the stack. Normally pushes are used,
728 but with GCC -mtpcs-frame, there may be other stores
729 in the prologue to create the frame. */
730 int regno = (insn >> 8) & 0x7;
733 offset = (insn & 0xff) << 2;
734 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
736 if (pv_area_store_would_trash (stack, addr))
739 pv_area_store (stack, addr, 4, regs[regno]);
741 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
743 int rd = bits (insn, 0, 2);
744 int rn = bits (insn, 3, 5);
747 offset = bits (insn, 6, 10) << 2;
748 addr = pv_add_constant (regs[rn], offset);
750 if (pv_area_store_would_trash (stack, addr))
753 pv_area_store (stack, addr, 4, regs[rd]);
755 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
756 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
757 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
758 /* Ignore stores of argument registers to the stack. */
760 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
761 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
762 /* Ignore block loads from the stack, potentially copying
763 parameters from memory. */
765 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
766 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
767 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
768 /* Similarly ignore single loads from the stack. */
770 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
771 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
772 /* Skip register copies, i.e. saves to another register
773 instead of the stack. */
775 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
776 /* Recognize constant loads; even with small stacks these are necessary
778 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
779 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
781 /* Constant pool loads, for the same reason. */
782 unsigned int constant;
785 loc = start + 4 + bits (insn, 0, 7) * 4;
786 constant = read_memory_unsigned_integer (loc, 4, byte_order);
787 regs[bits (insn, 8, 10)] = pv_constant (constant);
789 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
791 unsigned short inst2;
793 inst2 = read_memory_unsigned_integer (start + 2, 2,
794 byte_order_for_code);
796 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
798 /* BL, BLX. Allow some special function calls when
799 skipping the prologue; GCC generates these before
800 storing arguments to the stack. */
802 int j1, j2, imm1, imm2;
804 imm1 = sbits (insn, 0, 10);
805 imm2 = bits (inst2, 0, 10);
806 j1 = bit (inst2, 13);
807 j2 = bit (inst2, 11);
809 offset = ((imm1 << 12) + (imm2 << 1));
810 offset ^= ((!j2) << 22) | ((!j1) << 23);
812 nextpc = start + 4 + offset;
813 /* For BLX make sure to clear the low bits. */
814 if (bit (inst2, 12) == 0)
815 nextpc = nextpc & 0xfffffffc;
817 if (!skip_prologue_function (gdbarch, nextpc,
818 bit (inst2, 12) != 0))
822 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
824 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
826 pv_t addr = regs[bits (insn, 0, 3)];
829 if (pv_area_store_would_trash (stack, addr))
832 /* Calculate offsets of saved registers. */
833 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
834 if (inst2 & (1 << regno))
836 addr = pv_add_constant (addr, -4);
837 pv_area_store (stack, addr, 4, regs[regno]);
841 regs[bits (insn, 0, 3)] = addr;
844 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
846 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
848 int regno1 = bits (inst2, 12, 15);
849 int regno2 = bits (inst2, 8, 11);
850 pv_t addr = regs[bits (insn, 0, 3)];
852 offset = inst2 & 0xff;
854 addr = pv_add_constant (addr, offset);
856 addr = pv_add_constant (addr, -offset);
858 if (pv_area_store_would_trash (stack, addr))
861 pv_area_store (stack, addr, 4, regs[regno1]);
862 pv_area_store (stack, pv_add_constant (addr, 4),
866 regs[bits (insn, 0, 3)] = addr;
869 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
870 && (inst2 & 0x0c00) == 0x0c00
871 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
873 int regno = bits (inst2, 12, 15);
874 pv_t addr = regs[bits (insn, 0, 3)];
876 offset = inst2 & 0xff;
878 addr = pv_add_constant (addr, offset);
880 addr = pv_add_constant (addr, -offset);
882 if (pv_area_store_would_trash (stack, addr))
885 pv_area_store (stack, addr, 4, regs[regno]);
888 regs[bits (insn, 0, 3)] = addr;
891 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
892 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
894 int regno = bits (inst2, 12, 15);
897 offset = inst2 & 0xfff;
898 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
900 if (pv_area_store_would_trash (stack, addr))
903 pv_area_store (stack, addr, 4, regs[regno]);
906 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
907 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
908 /* Ignore stores of argument registers to the stack. */
911 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
912 && (inst2 & 0x0d00) == 0x0c00
913 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
914 /* Ignore stores of argument registers to the stack. */
917 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
919 && (inst2 & 0x8000) == 0x0000
920 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
921 /* Ignore block loads from the stack, potentially copying
922 parameters from memory. */
925 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
927 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
928 /* Similarly ignore dual loads from the stack. */
931 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
932 && (inst2 & 0x0d00) == 0x0c00
933 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
934 /* Similarly ignore single loads from the stack. */
937 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
938 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
939 /* Similarly ignore single loads from the stack. */
942 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
943 && (inst2 & 0x8000) == 0x0000)
945 unsigned int imm = ((bits (insn, 10, 10) << 11)
946 | (bits (inst2, 12, 14) << 8)
947 | bits (inst2, 0, 7));
949 regs[bits (inst2, 8, 11)]
950 = pv_add_constant (regs[bits (insn, 0, 3)],
951 thumb_expand_immediate (imm));
954 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
955 && (inst2 & 0x8000) == 0x0000)
957 unsigned int imm = ((bits (insn, 10, 10) << 11)
958 | (bits (inst2, 12, 14) << 8)
959 | bits (inst2, 0, 7));
961 regs[bits (inst2, 8, 11)]
962 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
965 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
966 && (inst2 & 0x8000) == 0x0000)
968 unsigned int imm = ((bits (insn, 10, 10) << 11)
969 | (bits (inst2, 12, 14) << 8)
970 | bits (inst2, 0, 7));
972 regs[bits (inst2, 8, 11)]
973 = pv_add_constant (regs[bits (insn, 0, 3)],
974 - (CORE_ADDR) thumb_expand_immediate (imm));
977 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
978 && (inst2 & 0x8000) == 0x0000)
980 unsigned int imm = ((bits (insn, 10, 10) << 11)
981 | (bits (inst2, 12, 14) << 8)
982 | bits (inst2, 0, 7));
984 regs[bits (inst2, 8, 11)]
985 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
988 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
990 unsigned int imm = ((bits (insn, 10, 10) << 11)
991 | (bits (inst2, 12, 14) << 8)
992 | bits (inst2, 0, 7));
994 regs[bits (inst2, 8, 11)]
995 = pv_constant (thumb_expand_immediate (imm));
998 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1001 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1003 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1006 else if (insn == 0xea5f /* mov.w Rd,Rm */
1007 && (inst2 & 0xf0f0) == 0)
1009 int dst_reg = (inst2 & 0x0f00) >> 8;
1010 int src_reg = inst2 & 0xf;
1011 regs[dst_reg] = regs[src_reg];
1014 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1016 /* Constant pool loads. */
1017 unsigned int constant;
1020 offset = bits (inst2, 0, 11);
1022 loc = start + 4 + offset;
1024 loc = start + 4 - offset;
1026 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1027 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1030 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1032 /* Constant pool loads. */
1033 unsigned int constant;
1036 offset = bits (inst2, 0, 7) << 2;
1038 loc = start + 4 + offset;
1040 loc = start + 4 - offset;
1042 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1043 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1045 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1046 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1049 else if (thumb2_instruction_changes_pc (insn, inst2))
1051 /* Don't scan past anything that might change control flow. */
1056 /* The optimizer might shove anything into the prologue,
1057 so we just skip what we don't recognize. */
1058 unrecognized_pc = start;
1063 else if (thumb_instruction_changes_pc (insn))
1065 /* Don't scan past anything that might change control flow. */
1070 /* The optimizer might shove anything into the prologue,
1071 so we just skip what we don't recognize. */
1072 unrecognized_pc = start;
1079 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1080 paddress (gdbarch, start));
1082 if (unrecognized_pc == 0)
1083 unrecognized_pc = start;
1087 do_cleanups (back_to);
1088 return unrecognized_pc;
1091 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1093 /* Frame pointer is fp. Frame size is constant. */
1094 cache->framereg = ARM_FP_REGNUM;
1095 cache->framesize = -regs[ARM_FP_REGNUM].k;
1097 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1099 /* Frame pointer is r7. Frame size is constant. */
1100 cache->framereg = THUMB_FP_REGNUM;
1101 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1105 /* Try the stack pointer... this is a bit desperate. */
1106 cache->framereg = ARM_SP_REGNUM;
1107 cache->framesize = -regs[ARM_SP_REGNUM].k;
1110 for (i = 0; i < 16; i++)
1111 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1112 cache->saved_regs[i].addr = offset;
1114 do_cleanups (back_to);
1115 return unrecognized_pc;
1119 /* Try to analyze the instructions starting from PC, which load symbol
1120 __stack_chk_guard. Return the address of instruction after loading this
1121 symbol, set the dest register number to *BASEREG, and set the size of
1122 instructions for loading symbol in OFFSET. Return 0 if instructions are
1126 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1127 unsigned int *destreg, int *offset)
1129 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1130 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1131 unsigned int low, high, address;
1136 unsigned short insn1
1137 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1139 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1141 *destreg = bits (insn1, 8, 10);
1143 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1144 address = read_memory_unsigned_integer (address, 4,
1145 byte_order_for_code);
1147 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1149 unsigned short insn2
1150 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1152 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1155 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1157 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1159 /* movt Rd, #const */
1160 if ((insn1 & 0xfbc0) == 0xf2c0)
1162 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1163 *destreg = bits (insn2, 8, 11);
1165 address = (high << 16 | low);
1172 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1174 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1176 address = bits (insn, 0, 11) + pc + 8;
1177 address = read_memory_unsigned_integer (address, 4,
1178 byte_order_for_code);
1180 *destreg = bits (insn, 12, 15);
1183 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1185 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1188 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1190 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1192 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1193 *destreg = bits (insn, 12, 15);
1195 address = (high << 16 | low);
1203 /* Try to skip a sequence of instructions used for stack protector. If PC
1204 points to the first instruction of this sequence, return the address of
1205 first instruction after this sequence, otherwise, return original PC.
1207 On arm, this sequence of instructions is composed of mainly three steps,
1208 Step 1: load symbol __stack_chk_guard,
1209 Step 2: load from address of __stack_chk_guard,
1210 Step 3: store it to somewhere else.
1212 Usually, instructions on step 2 and step 3 are the same on various ARM
1213 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1214 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1215 instructions in step 1 vary from different ARM architectures. On ARMv7,
1218 movw Rn, #:lower16:__stack_chk_guard
1219 movt Rn, #:upper16:__stack_chk_guard
1226 .word __stack_chk_guard
1228 Since ldr/str is a very popular instruction, we can't use them as
1229 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1230 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1231 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1234 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1236 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1237 unsigned int basereg;
1238 struct bound_minimal_symbol stack_chk_guard;
1240 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1243 /* Try to parse the instructions in Step 1. */
1244 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1249 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1250 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1251 Otherwise, this sequence cannot be for stack protector. */
1252 if (stack_chk_guard.minsym == NULL
1253 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1258 unsigned int destreg;
1260 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1262 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1263 if ((insn & 0xf800) != 0x6800)
1265 if (bits (insn, 3, 5) != basereg)
1267 destreg = bits (insn, 0, 2);
1269 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1270 byte_order_for_code);
1271 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1272 if ((insn & 0xf800) != 0x6000)
1274 if (destreg != bits (insn, 0, 2))
1279 unsigned int destreg;
1281 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1283 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1284 if ((insn & 0x0e500000) != 0x04100000)
1286 if (bits (insn, 16, 19) != basereg)
1288 destreg = bits (insn, 12, 15);
1289 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1290 insn = read_memory_unsigned_integer (pc + offset + 4,
1291 4, byte_order_for_code);
1292 if ((insn & 0x0e500000) != 0x04000000)
1294 if (bits (insn, 12, 15) != destreg)
1297 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1300 return pc + offset + 4;
1302 return pc + offset + 8;
1305 /* Advance the PC across any function entry prologue instructions to
1306 reach some "real" code.
1308 The APCS (ARM Procedure Call Standard) defines the following
1312 [stmfd sp!, {a1,a2,a3,a4}]
1313 stmfd sp!, {...,fp,ip,lr,pc}
1314 [stfe f7, [sp, #-12]!]
1315 [stfe f6, [sp, #-12]!]
1316 [stfe f5, [sp, #-12]!]
1317 [stfe f4, [sp, #-12]!]
1318 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1321 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1323 CORE_ADDR func_addr, limit_pc;
1325 /* See if we can determine the end of the prologue via the symbol table.
1326 If so, then return either PC, or the PC after the prologue, whichever
1328 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1330 CORE_ADDR post_prologue_pc
1331 = skip_prologue_using_sal (gdbarch, func_addr);
1332 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1334 if (post_prologue_pc)
1336 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1339 /* GCC always emits a line note before the prologue and another
1340 one after, even if the two are at the same address or on the
1341 same line. Take advantage of this so that we do not need to
1342 know every instruction that might appear in the prologue. We
1343 will have producer information for most binaries; if it is
1344 missing (e.g. for -gstabs), assuming the GNU tools. */
1345 if (post_prologue_pc
1347 || COMPUNIT_PRODUCER (cust) == NULL
1348 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1349 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1350 return post_prologue_pc;
1352 if (post_prologue_pc != 0)
1354 CORE_ADDR analyzed_limit;
1356 /* For non-GCC compilers, make sure the entire line is an
1357 acceptable prologue; GDB will round this function's
1358 return value up to the end of the following line so we
1359 can not skip just part of a line (and we do not want to).
1361 RealView does not treat the prologue specially, but does
1362 associate prologue code with the opening brace; so this
1363 lets us skip the first line if we think it is the opening
1365 if (arm_pc_is_thumb (gdbarch, func_addr))
1366 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1367 post_prologue_pc, NULL);
1369 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1370 post_prologue_pc, NULL);
1372 if (analyzed_limit != post_prologue_pc)
1375 return post_prologue_pc;
1379 /* Can't determine prologue from the symbol table, need to examine
1382 /* Find an upper limit on the function prologue using the debug
1383 information. If the debug information could not be used to provide
1384 that bound, then use an arbitrary large number as the upper bound. */
1385 /* Like arm_scan_prologue, stop no later than pc + 64. */
1386 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1388 limit_pc = pc + 64; /* Magic. */
1391 /* Check if this is Thumb code. */
1392 if (arm_pc_is_thumb (gdbarch, pc))
1393 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1395 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1399 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1400 This function decodes a Thumb function prologue to determine:
1401 1) the size of the stack frame
1402 2) which registers are saved on it
1403 3) the offsets of saved regs
1404 4) the offset from the stack pointer to the frame pointer
1406 A typical Thumb function prologue would create this stack frame
1407 (offsets relative to FP)
1408 old SP -> 24 stack parameters
1411 R7 -> 0 local variables (16 bytes)
1412 SP -> -12 additional stack space (12 bytes)
1413 The frame size would thus be 36 bytes, and the frame offset would be
1414 12 bytes. The frame register is R7.
1416 The comments for thumb_skip_prolog() describe the algorithm we use
1417 to detect the end of the prolog. */
1421 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1422 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1424 CORE_ADDR prologue_start;
1425 CORE_ADDR prologue_end;
1427 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1430 /* See comment in arm_scan_prologue for an explanation of
1432 if (prologue_end > prologue_start + 64)
1434 prologue_end = prologue_start + 64;
1438 /* We're in the boondocks: we have no idea where the start of the
1442 prologue_end = std::min (prologue_end, prev_pc);
1444 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1447 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1451 arm_instruction_restores_sp (unsigned int insn)
1453 if (bits (insn, 28, 31) != INST_NV)
1455 if ((insn & 0x0df0f000) == 0x0080d000
1456 /* ADD SP (register or immediate). */
1457 || (insn & 0x0df0f000) == 0x0040d000
1458 /* SUB SP (register or immediate). */
1459 || (insn & 0x0ffffff0) == 0x01a0d000
1461 || (insn & 0x0fff0000) == 0x08bd0000
1463 || (insn & 0x0fff0000) == 0x049d0000)
1464 /* POP of a single register. */
1471 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1472 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1473 fill it in. Return the first address not recognized as a prologue
1476 We recognize all the instructions typically found in ARM prologues,
1477 plus harmless instructions which can be skipped (either for analysis
1478 purposes, or a more restrictive set that can be skipped when finding
1479 the end of the prologue). */
1482 arm_analyze_prologue (struct gdbarch *gdbarch,
1483 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1484 struct arm_prologue_cache *cache)
1486 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1488 CORE_ADDR offset, current_pc;
1489 pv_t regs[ARM_FPS_REGNUM];
1490 struct pv_area *stack;
1491 struct cleanup *back_to;
1492 CORE_ADDR unrecognized_pc = 0;
1494 /* Search the prologue looking for instructions that set up the
1495 frame pointer, adjust the stack pointer, and save registers.
1497 Be careful, however, and if it doesn't look like a prologue,
1498 don't try to scan it. If, for instance, a frameless function
1499 begins with stmfd sp!, then we will tell ourselves there is
1500 a frame, which will confuse stack traceback, as well as "finish"
1501 and other operations that rely on a knowledge of the stack
1504 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1505 regs[regno] = pv_register (regno, 0);
1506 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1507 back_to = make_cleanup_free_pv_area (stack);
1509 for (current_pc = prologue_start;
1510 current_pc < prologue_end;
1514 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1516 if (insn == 0xe1a0c00d) /* mov ip, sp */
1518 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1521 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1522 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1524 unsigned imm = insn & 0xff; /* immediate value */
1525 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1526 int rd = bits (insn, 12, 15);
1527 imm = (imm >> rot) | (imm << (32 - rot));
1528 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1531 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1532 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1534 unsigned imm = insn & 0xff; /* immediate value */
1535 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1536 int rd = bits (insn, 12, 15);
1537 imm = (imm >> rot) | (imm << (32 - rot));
1538 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1541 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1544 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1546 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1547 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1548 regs[bits (insn, 12, 15)]);
1551 else if ((insn & 0xffff0000) == 0xe92d0000)
1552 /* stmfd sp!, {..., fp, ip, lr, pc}
1554 stmfd sp!, {a1, a2, a3, a4} */
1556 int mask = insn & 0xffff;
1558 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1561 /* Calculate offsets of saved registers. */
1562 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1563 if (mask & (1 << regno))
1566 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1567 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1570 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1571 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1572 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1574 /* No need to add this to saved_regs -- it's just an arg reg. */
1577 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1578 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1579 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1581 /* No need to add this to saved_regs -- it's just an arg reg. */
1584 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1586 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1588 /* No need to add this to saved_regs -- it's just arg regs. */
1591 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1593 unsigned imm = insn & 0xff; /* immediate value */
1594 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1595 imm = (imm >> rot) | (imm << (32 - rot));
1596 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1598 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1600 unsigned imm = insn & 0xff; /* immediate value */
1601 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1602 imm = (imm >> rot) | (imm << (32 - rot));
1603 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1605 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1607 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1609 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1612 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1613 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1614 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1616 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1618 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1620 int n_saved_fp_regs;
1621 unsigned int fp_start_reg, fp_bound_reg;
1623 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1626 if ((insn & 0x800) == 0x800) /* N0 is set */
1628 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1629 n_saved_fp_regs = 3;
1631 n_saved_fp_regs = 1;
1635 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1636 n_saved_fp_regs = 2;
1638 n_saved_fp_regs = 4;
1641 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1642 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1643 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1645 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1646 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1647 regs[fp_start_reg++]);
1650 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1652 /* Allow some special function calls when skipping the
1653 prologue; GCC generates these before storing arguments to
1655 CORE_ADDR dest = BranchDest (current_pc, insn);
1657 if (skip_prologue_function (gdbarch, dest, 0))
1662 else if ((insn & 0xf0000000) != 0xe0000000)
1663 break; /* Condition not true, exit early. */
1664 else if (arm_instruction_changes_pc (insn))
1665 /* Don't scan past anything that might change control flow. */
1667 else if (arm_instruction_restores_sp (insn))
1669 /* Don't scan past the epilogue. */
1672 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1673 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1674 /* Ignore block loads from the stack, potentially copying
1675 parameters from memory. */
1677 else if ((insn & 0xfc500000) == 0xe4100000
1678 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1679 /* Similarly ignore single loads from the stack. */
1681 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1682 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1683 register instead of the stack. */
1687 /* The optimizer might shove anything into the prologue, if
1688 we build up cache (cache != NULL) from scanning prologue,
1689 we just skip what we don't recognize and scan further to
1690 make cache as complete as possible. However, if we skip
1691 prologue, we'll stop immediately on unrecognized
1693 unrecognized_pc = current_pc;
1701 if (unrecognized_pc == 0)
1702 unrecognized_pc = current_pc;
1706 int framereg, framesize;
1708 /* The frame size is just the distance from the frame register
1709 to the original stack pointer. */
1710 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1712 /* Frame pointer is fp. */
1713 framereg = ARM_FP_REGNUM;
1714 framesize = -regs[ARM_FP_REGNUM].k;
1718 /* Try the stack pointer... this is a bit desperate. */
1719 framereg = ARM_SP_REGNUM;
1720 framesize = -regs[ARM_SP_REGNUM].k;
1723 cache->framereg = framereg;
1724 cache->framesize = framesize;
1726 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1727 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1728 cache->saved_regs[regno].addr = offset;
1732 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1733 paddress (gdbarch, unrecognized_pc));
1735 do_cleanups (back_to);
1736 return unrecognized_pc;
1740 arm_scan_prologue (struct frame_info *this_frame,
1741 struct arm_prologue_cache *cache)
1743 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1744 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1745 CORE_ADDR prologue_start, prologue_end;
1746 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1747 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1749 /* Assume there is no frame until proven otherwise. */
1750 cache->framereg = ARM_SP_REGNUM;
1751 cache->framesize = 0;
1753 /* Check for Thumb prologue. */
1754 if (arm_frame_is_thumb (this_frame))
1756 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1760 /* Find the function prologue. If we can't find the function in
1761 the symbol table, peek in the stack frame to find the PC. */
1762 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1765 /* One way to find the end of the prologue (which works well
1766 for unoptimized code) is to do the following:
1768 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1771 prologue_end = prev_pc;
1772 else if (sal.end < prologue_end)
1773 prologue_end = sal.end;
1775 This mechanism is very accurate so long as the optimizer
1776 doesn't move any instructions from the function body into the
1777 prologue. If this happens, sal.end will be the last
1778 instruction in the first hunk of prologue code just before
1779 the first instruction that the scheduler has moved from
1780 the body to the prologue.
1782 In order to make sure that we scan all of the prologue
1783 instructions, we use a slightly less accurate mechanism which
1784 may scan more than necessary. To help compensate for this
1785 lack of accuracy, the prologue scanning loop below contains
1786 several clauses which'll cause the loop to terminate early if
1787 an implausible prologue instruction is encountered.
1793 is a suitable endpoint since it accounts for the largest
1794 possible prologue plus up to five instructions inserted by
1797 if (prologue_end > prologue_start + 64)
1799 prologue_end = prologue_start + 64; /* See above. */
1804 /* We have no symbol information. Our only option is to assume this
1805 function has a standard stack frame and the normal frame register.
1806 Then, we can find the value of our frame pointer on entrance to
1807 the callee (or at the present moment if this is the innermost frame).
1808 The value stored there should be the address of the stmfd + 8. */
1809 CORE_ADDR frame_loc;
1810 LONGEST return_value;
1812 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1813 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1817 prologue_start = gdbarch_addr_bits_remove
1818 (gdbarch, return_value) - 8;
1819 prologue_end = prologue_start + 64; /* See above. */
1823 if (prev_pc < prologue_end)
1824 prologue_end = prev_pc;
1826 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1829 static struct arm_prologue_cache *
1830 arm_make_prologue_cache (struct frame_info *this_frame)
1833 struct arm_prologue_cache *cache;
1834 CORE_ADDR unwound_fp;
1836 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1837 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1839 arm_scan_prologue (this_frame, cache);
1841 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1842 if (unwound_fp == 0)
1845 cache->prev_sp = unwound_fp + cache->framesize;
1847 /* Calculate actual addresses of saved registers using offsets
1848 determined by arm_scan_prologue. */
1849 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1850 if (trad_frame_addr_p (cache->saved_regs, reg))
1851 cache->saved_regs[reg].addr += cache->prev_sp;
1856 /* Implementation of the stop_reason hook for arm_prologue frames. */
1858 static enum unwind_stop_reason
1859 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
1862 struct arm_prologue_cache *cache;
1865 if (*this_cache == NULL)
1866 *this_cache = arm_make_prologue_cache (this_frame);
1867 cache = (struct arm_prologue_cache *) *this_cache;
1869 /* This is meant to halt the backtrace at "_start". */
1870 pc = get_frame_pc (this_frame);
1871 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1872 return UNWIND_OUTERMOST;
1874 /* If we've hit a wall, stop. */
1875 if (cache->prev_sp == 0)
1876 return UNWIND_OUTERMOST;
1878 return UNWIND_NO_REASON;
1881 /* Our frame ID for a normal frame is the current function's starting PC
1882 and the caller's SP when we were called. */
1885 arm_prologue_this_id (struct frame_info *this_frame,
1887 struct frame_id *this_id)
1889 struct arm_prologue_cache *cache;
1893 if (*this_cache == NULL)
1894 *this_cache = arm_make_prologue_cache (this_frame);
1895 cache = (struct arm_prologue_cache *) *this_cache;
1897 /* Use function start address as part of the frame ID. If we cannot
1898 identify the start address (due to missing symbol information),
1899 fall back to just using the current PC. */
1900 pc = get_frame_pc (this_frame);
1901 func = get_frame_func (this_frame);
1905 id = frame_id_build (cache->prev_sp, func);
1909 static struct value *
1910 arm_prologue_prev_register (struct frame_info *this_frame,
1914 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1915 struct arm_prologue_cache *cache;
1917 if (*this_cache == NULL)
1918 *this_cache = arm_make_prologue_cache (this_frame);
1919 cache = (struct arm_prologue_cache *) *this_cache;
1921 /* If we are asked to unwind the PC, then we need to return the LR
1922 instead. The prologue may save PC, but it will point into this
1923 frame's prologue, not the next frame's resume location. Also
1924 strip the saved T bit. A valid LR may have the low bit set, but
1925 a valid PC never does. */
1926 if (prev_regnum == ARM_PC_REGNUM)
1930 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1931 return frame_unwind_got_constant (this_frame, prev_regnum,
1932 arm_addr_bits_remove (gdbarch, lr));
1935 /* SP is generally not saved to the stack, but this frame is
1936 identified by the next frame's stack pointer at the time of the call.
1937 The value was already reconstructed into PREV_SP. */
1938 if (prev_regnum == ARM_SP_REGNUM)
1939 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1941 /* The CPSR may have been changed by the call instruction and by the
1942 called function. The only bit we can reconstruct is the T bit,
1943 by checking the low bit of LR as of the call. This is a reliable
1944 indicator of Thumb-ness except for some ARM v4T pre-interworking
1945 Thumb code, which could get away with a clear low bit as long as
1946 the called function did not use bx. Guess that all other
1947 bits are unchanged; the condition flags are presumably lost,
1948 but the processor status is likely valid. */
1949 if (prev_regnum == ARM_PS_REGNUM)
1952 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
1954 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1955 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1956 if (IS_THUMB_ADDR (lr))
1960 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1963 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1967 struct frame_unwind arm_prologue_unwind = {
1969 arm_prologue_unwind_stop_reason,
1970 arm_prologue_this_id,
1971 arm_prologue_prev_register,
1973 default_frame_sniffer
1976 /* Maintain a list of ARM exception table entries per objfile, similar to the
1977 list of mapping symbols. We only cache entries for standard ARM-defined
1978 personality routines; the cache will contain only the frame unwinding
1979 instructions associated with the entry (not the descriptors). */
1981 static const struct objfile_data *arm_exidx_data_key;
1983 struct arm_exidx_entry
1988 typedef struct arm_exidx_entry arm_exidx_entry_s;
1989 DEF_VEC_O(arm_exidx_entry_s);
1991 struct arm_exidx_data
1993 VEC(arm_exidx_entry_s) **section_maps;
1997 arm_exidx_data_free (struct objfile *objfile, void *arg)
1999 struct arm_exidx_data *data = (struct arm_exidx_data *) arg;
2002 for (i = 0; i < objfile->obfd->section_count; i++)
2003 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2007 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2008 const struct arm_exidx_entry *rhs)
2010 return lhs->addr < rhs->addr;
2013 static struct obj_section *
2014 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2016 struct obj_section *osect;
2018 ALL_OBJFILE_OSECTIONS (objfile, osect)
2019 if (bfd_get_section_flags (objfile->obfd,
2020 osect->the_bfd_section) & SEC_ALLOC)
2022 bfd_vma start, size;
2023 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2024 size = bfd_get_section_size (osect->the_bfd_section);
2026 if (start <= vma && vma < start + size)
2033 /* Parse contents of exception table and exception index sections
2034 of OBJFILE, and fill in the exception table entry cache.
2036 For each entry that refers to a standard ARM-defined personality
2037 routine, extract the frame unwinding instructions (from either
2038 the index or the table section). The unwinding instructions
2040 - extracting them from the rest of the table data
2041 - converting to host endianness
2042 - appending the implicit 0xb0 ("Finish") code
2044 The extracted and normalized instructions are stored for later
2045 retrieval by the arm_find_exidx_entry routine. */
2048 arm_exidx_new_objfile (struct objfile *objfile)
2050 struct cleanup *cleanups;
2051 struct arm_exidx_data *data;
2052 asection *exidx, *extab;
2053 bfd_vma exidx_vma = 0, extab_vma = 0;
2054 bfd_size_type exidx_size = 0, extab_size = 0;
2055 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2058 /* If we've already touched this file, do nothing. */
2059 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2061 cleanups = make_cleanup (null_cleanup, NULL);
2063 /* Read contents of exception table and index. */
2064 exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
2067 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2068 exidx_size = bfd_get_section_size (exidx);
2069 exidx_data = (gdb_byte *) xmalloc (exidx_size);
2070 make_cleanup (xfree, exidx_data);
2072 if (!bfd_get_section_contents (objfile->obfd, exidx,
2073 exidx_data, 0, exidx_size))
2075 do_cleanups (cleanups);
2080 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2083 extab_vma = bfd_section_vma (objfile->obfd, extab);
2084 extab_size = bfd_get_section_size (extab);
2085 extab_data = (gdb_byte *) xmalloc (extab_size);
2086 make_cleanup (xfree, extab_data);
2088 if (!bfd_get_section_contents (objfile->obfd, extab,
2089 extab_data, 0, extab_size))
2091 do_cleanups (cleanups);
2096 /* Allocate exception table data structure. */
2097 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2098 set_objfile_data (objfile, arm_exidx_data_key, data);
2099 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2100 objfile->obfd->section_count,
2101 VEC(arm_exidx_entry_s) *);
2103 /* Fill in exception table. */
2104 for (i = 0; i < exidx_size / 8; i++)
2106 struct arm_exidx_entry new_exidx_entry;
2107 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2108 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2109 bfd_vma addr = 0, word = 0;
2110 int n_bytes = 0, n_words = 0;
2111 struct obj_section *sec;
2112 gdb_byte *entry = NULL;
2114 /* Extract address of start of function. */
2115 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2116 idx += exidx_vma + i * 8;
2118 /* Find section containing function and compute section offset. */
2119 sec = arm_obj_section_from_vma (objfile, idx);
2122 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2124 /* Determine address of exception table entry. */
2127 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2129 else if ((val & 0xff000000) == 0x80000000)
2131 /* Exception table entry embedded in .ARM.exidx
2132 -- must be short form. */
2136 else if (!(val & 0x80000000))
2138 /* Exception table entry in .ARM.extab. */
2139 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2140 addr += exidx_vma + i * 8 + 4;
2142 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2144 word = bfd_h_get_32 (objfile->obfd,
2145 extab_data + addr - extab_vma);
2148 if ((word & 0xff000000) == 0x80000000)
2153 else if ((word & 0xff000000) == 0x81000000
2154 || (word & 0xff000000) == 0x82000000)
2158 n_words = ((word >> 16) & 0xff);
2160 else if (!(word & 0x80000000))
2163 struct obj_section *pers_sec;
2164 int gnu_personality = 0;
2166 /* Custom personality routine. */
2167 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2168 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2170 /* Check whether we've got one of the variants of the
2171 GNU personality routines. */
2172 pers_sec = arm_obj_section_from_vma (objfile, pers);
2175 static const char *personality[] =
2177 "__gcc_personality_v0",
2178 "__gxx_personality_v0",
2179 "__gcj_personality_v0",
2180 "__gnu_objc_personality_v0",
2184 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2187 for (k = 0; personality[k]; k++)
2188 if (lookup_minimal_symbol_by_pc_name
2189 (pc, personality[k], objfile))
2191 gnu_personality = 1;
2196 /* If so, the next word contains a word count in the high
2197 byte, followed by the same unwind instructions as the
2198 pre-defined forms. */
2200 && addr + 4 <= extab_vma + extab_size)
2202 word = bfd_h_get_32 (objfile->obfd,
2203 extab_data + addr - extab_vma);
2206 n_words = ((word >> 24) & 0xff);
2212 /* Sanity check address. */
2214 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2215 n_words = n_bytes = 0;
2217 /* The unwind instructions reside in WORD (only the N_BYTES least
2218 significant bytes are valid), followed by N_WORDS words in the
2219 extab section starting at ADDR. */
2220 if (n_bytes || n_words)
2223 = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack,
2224 n_bytes + n_words * 4 + 1);
2227 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2231 word = bfd_h_get_32 (objfile->obfd,
2232 extab_data + addr - extab_vma);
2235 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2236 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2237 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2238 *p++ = (gdb_byte) (word & 0xff);
2241 /* Implied "Finish" to terminate the list. */
2245 /* Push entry onto vector. They are guaranteed to always
2246 appear in order of increasing addresses. */
2247 new_exidx_entry.addr = idx;
2248 new_exidx_entry.entry = entry;
2249 VEC_safe_push (arm_exidx_entry_s,
2250 data->section_maps[sec->the_bfd_section->index],
2254 do_cleanups (cleanups);
2257 /* Search for the exception table entry covering MEMADDR. If one is found,
2258 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2259 set *START to the start of the region covered by this entry. */
2262 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2264 struct obj_section *sec;
2266 sec = find_pc_section (memaddr);
2269 struct arm_exidx_data *data;
2270 VEC(arm_exidx_entry_s) *map;
2271 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2274 data = ((struct arm_exidx_data *)
2275 objfile_data (sec->objfile, arm_exidx_data_key));
2278 map = data->section_maps[sec->the_bfd_section->index];
2279 if (!VEC_empty (arm_exidx_entry_s, map))
2281 struct arm_exidx_entry *map_sym;
2283 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2284 arm_compare_exidx_entries);
2286 /* VEC_lower_bound finds the earliest ordered insertion
2287 point. If the following symbol starts at this exact
2288 address, we use that; otherwise, the preceding
2289 exception table entry covers this address. */
2290 if (idx < VEC_length (arm_exidx_entry_s, map))
2292 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2293 if (map_sym->addr == map_key.addr)
2296 *start = map_sym->addr + obj_section_addr (sec);
2297 return map_sym->entry;
2303 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2305 *start = map_sym->addr + obj_section_addr (sec);
2306 return map_sym->entry;
2315 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2316 instruction list from the ARM exception table entry ENTRY, allocate and
2317 return a prologue cache structure describing how to unwind this frame.
2319 Return NULL if the unwinding instruction list contains a "spare",
2320 "reserved" or "refuse to unwind" instruction as defined in section
2321 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2322 for the ARM Architecture" document. */
2324 static struct arm_prologue_cache *
2325 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2330 struct arm_prologue_cache *cache;
2331 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2332 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2338 /* Whenever we reload SP, we actually have to retrieve its
2339 actual value in the current frame. */
2342 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2344 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2345 vsp = get_frame_register_unsigned (this_frame, reg);
2349 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2350 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2356 /* Decode next unwind instruction. */
2359 if ((insn & 0xc0) == 0)
2361 int offset = insn & 0x3f;
2362 vsp += (offset << 2) + 4;
2364 else if ((insn & 0xc0) == 0x40)
2366 int offset = insn & 0x3f;
2367 vsp -= (offset << 2) + 4;
2369 else if ((insn & 0xf0) == 0x80)
2371 int mask = ((insn & 0xf) << 8) | *entry++;
2374 /* The special case of an all-zero mask identifies
2375 "Refuse to unwind". We return NULL to fall back
2376 to the prologue analyzer. */
2380 /* Pop registers r4..r15 under mask. */
2381 for (i = 0; i < 12; i++)
2382 if (mask & (1 << i))
2384 cache->saved_regs[4 + i].addr = vsp;
2388 /* Special-case popping SP -- we need to reload vsp. */
2389 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2392 else if ((insn & 0xf0) == 0x90)
2394 int reg = insn & 0xf;
2396 /* Reserved cases. */
2397 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2400 /* Set SP from another register and mark VSP for reload. */
2401 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2404 else if ((insn & 0xf0) == 0xa0)
2406 int count = insn & 0x7;
2407 int pop_lr = (insn & 0x8) != 0;
2410 /* Pop r4..r[4+count]. */
2411 for (i = 0; i <= count; i++)
2413 cache->saved_regs[4 + i].addr = vsp;
2417 /* If indicated by flag, pop LR as well. */
2420 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2424 else if (insn == 0xb0)
2426 /* We could only have updated PC by popping into it; if so, it
2427 will show up as address. Otherwise, copy LR into PC. */
2428 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2429 cache->saved_regs[ARM_PC_REGNUM]
2430 = cache->saved_regs[ARM_LR_REGNUM];
2435 else if (insn == 0xb1)
2437 int mask = *entry++;
2440 /* All-zero mask and mask >= 16 is "spare". */
2441 if (mask == 0 || mask >= 16)
2444 /* Pop r0..r3 under mask. */
2445 for (i = 0; i < 4; i++)
2446 if (mask & (1 << i))
2448 cache->saved_regs[i].addr = vsp;
2452 else if (insn == 0xb2)
2454 ULONGEST offset = 0;
2459 offset |= (*entry & 0x7f) << shift;
2462 while (*entry++ & 0x80);
2464 vsp += 0x204 + (offset << 2);
2466 else if (insn == 0xb3)
2468 int start = *entry >> 4;
2469 int count = (*entry++) & 0xf;
2472 /* Only registers D0..D15 are valid here. */
2473 if (start + count >= 16)
2476 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2477 for (i = 0; i <= count; i++)
2479 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2483 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2486 else if ((insn & 0xf8) == 0xb8)
2488 int count = insn & 0x7;
2491 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2492 for (i = 0; i <= count; i++)
2494 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2498 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2501 else if (insn == 0xc6)
2503 int start = *entry >> 4;
2504 int count = (*entry++) & 0xf;
2507 /* Only registers WR0..WR15 are valid. */
2508 if (start + count >= 16)
2511 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2512 for (i = 0; i <= count; i++)
2514 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2518 else if (insn == 0xc7)
2520 int mask = *entry++;
2523 /* All-zero mask and mask >= 16 is "spare". */
2524 if (mask == 0 || mask >= 16)
2527 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2528 for (i = 0; i < 4; i++)
2529 if (mask & (1 << i))
2531 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2535 else if ((insn & 0xf8) == 0xc0)
2537 int count = insn & 0x7;
2540 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2541 for (i = 0; i <= count; i++)
2543 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2547 else if (insn == 0xc8)
2549 int start = *entry >> 4;
2550 int count = (*entry++) & 0xf;
2553 /* Only registers D0..D31 are valid. */
2554 if (start + count >= 16)
2557 /* Pop VFP double-precision registers
2558 D[16+start]..D[16+start+count]. */
2559 for (i = 0; i <= count; i++)
2561 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2565 else if (insn == 0xc9)
2567 int start = *entry >> 4;
2568 int count = (*entry++) & 0xf;
2571 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2572 for (i = 0; i <= count; i++)
2574 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2578 else if ((insn & 0xf8) == 0xd0)
2580 int count = insn & 0x7;
2583 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2584 for (i = 0; i <= count; i++)
2586 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2592 /* Everything else is "spare". */
2597 /* If we restore SP from a register, assume this was the frame register.
2598 Otherwise just fall back to SP as frame register. */
2599 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2600 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2602 cache->framereg = ARM_SP_REGNUM;
2604 /* Determine offset to previous frame. */
2606 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2608 /* We already got the previous SP. */
2609 cache->prev_sp = vsp;
2614 /* Unwinding via ARM exception table entries. Note that the sniffer
2615 already computes a filled-in prologue cache, which is then used
2616 with the same arm_prologue_this_id and arm_prologue_prev_register
2617 routines also used for prologue-parsing based unwinding. */
2620 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2621 struct frame_info *this_frame,
2622 void **this_prologue_cache)
2624 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2625 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2626 CORE_ADDR addr_in_block, exidx_region, func_start;
2627 struct arm_prologue_cache *cache;
2630 /* See if we have an ARM exception table entry covering this address. */
2631 addr_in_block = get_frame_address_in_block (this_frame);
2632 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2636 /* The ARM exception table does not describe unwind information
2637 for arbitrary PC values, but is guaranteed to be correct only
2638 at call sites. We have to decide here whether we want to use
2639 ARM exception table information for this frame, or fall back
2640 to using prologue parsing. (Note that if we have DWARF CFI,
2641 this sniffer isn't even called -- CFI is always preferred.)
2643 Before we make this decision, however, we check whether we
2644 actually have *symbol* information for the current frame.
2645 If not, prologue parsing would not work anyway, so we might
2646 as well use the exception table and hope for the best. */
2647 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2651 /* If the next frame is "normal", we are at a call site in this
2652 frame, so exception information is guaranteed to be valid. */
2653 if (get_next_frame (this_frame)
2654 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2657 /* We also assume exception information is valid if we're currently
2658 blocked in a system call. The system library is supposed to
2659 ensure this, so that e.g. pthread cancellation works. */
2660 if (arm_frame_is_thumb (this_frame))
2664 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2665 byte_order_for_code, &insn)
2666 && (insn & 0xff00) == 0xdf00 /* svc */)
2673 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2674 byte_order_for_code, &insn)
2675 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2679 /* Bail out if we don't know that exception information is valid. */
2683 /* The ARM exception index does not mark the *end* of the region
2684 covered by the entry, and some functions will not have any entry.
2685 To correctly recognize the end of the covered region, the linker
2686 should have inserted dummy records with a CANTUNWIND marker.
2688 Unfortunately, current versions of GNU ld do not reliably do
2689 this, and thus we may have found an incorrect entry above.
2690 As a (temporary) sanity check, we only use the entry if it
2691 lies *within* the bounds of the function. Note that this check
2692 might reject perfectly valid entries that just happen to cover
2693 multiple functions; therefore this check ought to be removed
2694 once the linker is fixed. */
2695 if (func_start > exidx_region)
2699 /* Decode the list of unwinding instructions into a prologue cache.
2700 Note that this may fail due to e.g. a "refuse to unwind" code. */
2701 cache = arm_exidx_fill_cache (this_frame, entry);
2705 *this_prologue_cache = cache;
2709 struct frame_unwind arm_exidx_unwind = {
2711 default_frame_unwind_stop_reason,
2712 arm_prologue_this_id,
2713 arm_prologue_prev_register,
2715 arm_exidx_unwind_sniffer
2718 static struct arm_prologue_cache *
2719 arm_make_epilogue_frame_cache (struct frame_info *this_frame)
2721 struct arm_prologue_cache *cache;
2724 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2725 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2727 /* Still rely on the offset calculated from prologue. */
2728 arm_scan_prologue (this_frame, cache);
2730 /* Since we are in epilogue, the SP has been restored. */
2731 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2733 /* Calculate actual addresses of saved registers using offsets
2734 determined by arm_scan_prologue. */
2735 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2736 if (trad_frame_addr_p (cache->saved_regs, reg))
2737 cache->saved_regs[reg].addr += cache->prev_sp;
2742 /* Implementation of function hook 'this_id' in
2743 'struct frame_uwnind' for epilogue unwinder. */
2746 arm_epilogue_frame_this_id (struct frame_info *this_frame,
2748 struct frame_id *this_id)
2750 struct arm_prologue_cache *cache;
2753 if (*this_cache == NULL)
2754 *this_cache = arm_make_epilogue_frame_cache (this_frame);
2755 cache = (struct arm_prologue_cache *) *this_cache;
2757 /* Use function start address as part of the frame ID. If we cannot
2758 identify the start address (due to missing symbol information),
2759 fall back to just using the current PC. */
2760 pc = get_frame_pc (this_frame);
2761 func = get_frame_func (this_frame);
2765 (*this_id) = frame_id_build (cache->prev_sp, pc);
2768 /* Implementation of function hook 'prev_register' in
2769 'struct frame_uwnind' for epilogue unwinder. */
2771 static struct value *
2772 arm_epilogue_frame_prev_register (struct frame_info *this_frame,
2773 void **this_cache, int regnum)
2775 if (*this_cache == NULL)
2776 *this_cache = arm_make_epilogue_frame_cache (this_frame);
2778 return arm_prologue_prev_register (this_frame, this_cache, regnum);
2781 static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch,
2783 static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch,
2786 /* Implementation of function hook 'sniffer' in
2787 'struct frame_uwnind' for epilogue unwinder. */
2790 arm_epilogue_frame_sniffer (const struct frame_unwind *self,
2791 struct frame_info *this_frame,
2792 void **this_prologue_cache)
2794 if (frame_relative_level (this_frame) == 0)
2796 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2797 CORE_ADDR pc = get_frame_pc (this_frame);
2799 if (arm_frame_is_thumb (this_frame))
2800 return thumb_stack_frame_destroyed_p (gdbarch, pc);
2802 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
2808 /* Frame unwinder from epilogue. */
2810 static const struct frame_unwind arm_epilogue_frame_unwind =
2813 default_frame_unwind_stop_reason,
2814 arm_epilogue_frame_this_id,
2815 arm_epilogue_frame_prev_register,
2817 arm_epilogue_frame_sniffer,
2820 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2821 trampoline, return the target PC. Otherwise return 0.
2823 void call0a (char c, short s, int i, long l) {}
2827 (*pointer_to_call0a) (c, s, i, l);
2830 Instead of calling a stub library function _call_via_xx (xx is
2831 the register name), GCC may inline the trampoline in the object
2832 file as below (register r2 has the address of call0a).
2835 .type main, %function
2844 The trampoline 'bx r2' doesn't belong to main. */
2847 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2849 /* The heuristics of recognizing such trampoline is that FRAME is
2850 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2851 if (arm_frame_is_thumb (frame))
2855 if (target_read_memory (pc, buf, 2) == 0)
2857 struct gdbarch *gdbarch = get_frame_arch (frame);
2858 enum bfd_endian byte_order_for_code
2859 = gdbarch_byte_order_for_code (gdbarch);
2861 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2863 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2866 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2868 /* Clear the LSB so that gdb core sets step-resume
2869 breakpoint at the right address. */
2870 return UNMAKE_THUMB_ADDR (dest);
2878 static struct arm_prologue_cache *
2879 arm_make_stub_cache (struct frame_info *this_frame)
2881 struct arm_prologue_cache *cache;
2883 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2884 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2886 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2891 /* Our frame ID for a stub frame is the current SP and LR. */
2894 arm_stub_this_id (struct frame_info *this_frame,
2896 struct frame_id *this_id)
2898 struct arm_prologue_cache *cache;
2900 if (*this_cache == NULL)
2901 *this_cache = arm_make_stub_cache (this_frame);
2902 cache = (struct arm_prologue_cache *) *this_cache;
2904 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2908 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2909 struct frame_info *this_frame,
2910 void **this_prologue_cache)
2912 CORE_ADDR addr_in_block;
2914 CORE_ADDR pc, start_addr;
2917 addr_in_block = get_frame_address_in_block (this_frame);
2918 pc = get_frame_pc (this_frame);
2919 if (in_plt_section (addr_in_block)
2920 /* We also use the stub winder if the target memory is unreadable
2921 to avoid having the prologue unwinder trying to read it. */
2922 || target_read_memory (pc, dummy, 4) != 0)
2925 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2926 && arm_skip_bx_reg (this_frame, pc) != 0)
2932 struct frame_unwind arm_stub_unwind = {
2934 default_frame_unwind_stop_reason,
2936 arm_prologue_prev_register,
2938 arm_stub_unwind_sniffer
2941 /* Put here the code to store, into CACHE->saved_regs, the addresses
2942 of the saved registers of frame described by THIS_FRAME. CACHE is
2945 static struct arm_prologue_cache *
2946 arm_m_exception_cache (struct frame_info *this_frame)
2948 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2949 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2950 struct arm_prologue_cache *cache;
2951 CORE_ADDR unwound_sp;
2954 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2955 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2957 unwound_sp = get_frame_register_unsigned (this_frame,
2960 /* The hardware saves eight 32-bit words, comprising xPSR,
2961 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2962 "B1.5.6 Exception entry behavior" in
2963 "ARMv7-M Architecture Reference Manual". */
2964 cache->saved_regs[0].addr = unwound_sp;
2965 cache->saved_regs[1].addr = unwound_sp + 4;
2966 cache->saved_regs[2].addr = unwound_sp + 8;
2967 cache->saved_regs[3].addr = unwound_sp + 12;
2968 cache->saved_regs[12].addr = unwound_sp + 16;
2969 cache->saved_regs[14].addr = unwound_sp + 20;
2970 cache->saved_regs[15].addr = unwound_sp + 24;
2971 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2973 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2974 aligner between the top of the 32-byte stack frame and the
2975 previous context's stack pointer. */
2976 cache->prev_sp = unwound_sp + 32;
2977 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2978 && (xpsr & (1 << 9)) != 0)
2979 cache->prev_sp += 4;
2984 /* Implementation of function hook 'this_id' in
2985 'struct frame_uwnind'. */
2988 arm_m_exception_this_id (struct frame_info *this_frame,
2990 struct frame_id *this_id)
2992 struct arm_prologue_cache *cache;
2994 if (*this_cache == NULL)
2995 *this_cache = arm_m_exception_cache (this_frame);
2996 cache = (struct arm_prologue_cache *) *this_cache;
2998 /* Our frame ID for a stub frame is the current SP and LR. */
2999 *this_id = frame_id_build (cache->prev_sp,
3000 get_frame_pc (this_frame));
3003 /* Implementation of function hook 'prev_register' in
3004 'struct frame_uwnind'. */
3006 static struct value *
3007 arm_m_exception_prev_register (struct frame_info *this_frame,
3011 struct arm_prologue_cache *cache;
3013 if (*this_cache == NULL)
3014 *this_cache = arm_m_exception_cache (this_frame);
3015 cache = (struct arm_prologue_cache *) *this_cache;
3017 /* The value was already reconstructed into PREV_SP. */
3018 if (prev_regnum == ARM_SP_REGNUM)
3019 return frame_unwind_got_constant (this_frame, prev_regnum,
3022 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3026 /* Implementation of function hook 'sniffer' in
3027 'struct frame_uwnind'. */
3030 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3031 struct frame_info *this_frame,
3032 void **this_prologue_cache)
3034 CORE_ADDR this_pc = get_frame_pc (this_frame);
3036 /* No need to check is_m; this sniffer is only registered for
3037 M-profile architectures. */
3039 /* Check if exception frame returns to a magic PC value. */
3040 return arm_m_addr_is_magic (this_pc);
3043 /* Frame unwinder for M-profile exceptions. */
3045 struct frame_unwind arm_m_exception_unwind =
3048 default_frame_unwind_stop_reason,
3049 arm_m_exception_this_id,
3050 arm_m_exception_prev_register,
3052 arm_m_exception_unwind_sniffer
3056 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3058 struct arm_prologue_cache *cache;
3060 if (*this_cache == NULL)
3061 *this_cache = arm_make_prologue_cache (this_frame);
3062 cache = (struct arm_prologue_cache *) *this_cache;
3064 return cache->prev_sp - cache->framesize;
3067 struct frame_base arm_normal_base = {
3068 &arm_prologue_unwind,
3069 arm_normal_frame_base,
3070 arm_normal_frame_base,
3071 arm_normal_frame_base
3074 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3075 dummy frame. The frame ID's base needs to match the TOS value
3076 saved by save_dummy_frame_tos() and returned from
3077 arm_push_dummy_call, and the PC needs to match the dummy frame's
3080 static struct frame_id
3081 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3083 return frame_id_build (get_frame_register_unsigned (this_frame,
3085 get_frame_pc (this_frame));
3088 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3089 be used to construct the previous frame's ID, after looking up the
3090 containing function). */
3093 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3096 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3097 return arm_addr_bits_remove (gdbarch, pc);
3101 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3103 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3106 static struct value *
3107 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3110 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3112 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3117 /* The PC is normally copied from the return column, which
3118 describes saves of LR. However, that version may have an
3119 extra bit set to indicate Thumb state. The bit is not
3121 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3122 return frame_unwind_got_constant (this_frame, regnum,
3123 arm_addr_bits_remove (gdbarch, lr));
3126 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3127 cpsr = get_frame_register_unsigned (this_frame, regnum);
3128 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3129 if (IS_THUMB_ADDR (lr))
3133 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3136 internal_error (__FILE__, __LINE__,
3137 _("Unexpected register %d"), regnum);
3142 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3143 struct dwarf2_frame_state_reg *reg,
3144 struct frame_info *this_frame)
3150 reg->how = DWARF2_FRAME_REG_FN;
3151 reg->loc.fn = arm_dwarf2_prev_register;
3154 reg->how = DWARF2_FRAME_REG_CFA;
3159 /* Implement the stack_frame_destroyed_p gdbarch method. */
3162 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3164 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3165 unsigned int insn, insn2;
3166 int found_return = 0, found_stack_adjust = 0;
3167 CORE_ADDR func_start, func_end;
3171 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3174 /* The epilogue is a sequence of instructions along the following lines:
3176 - add stack frame size to SP or FP
3177 - [if frame pointer used] restore SP from FP
3178 - restore registers from SP [may include PC]
3179 - a return-type instruction [if PC wasn't already restored]
3181 In a first pass, we scan forward from the current PC and verify the
3182 instructions we find as compatible with this sequence, ending in a
3185 However, this is not sufficient to distinguish indirect function calls
3186 within a function from indirect tail calls in the epilogue in some cases.
3187 Therefore, if we didn't already find any SP-changing instruction during
3188 forward scan, we add a backward scanning heuristic to ensure we actually
3189 are in the epilogue. */
3192 while (scan_pc < func_end && !found_return)
3194 if (target_read_memory (scan_pc, buf, 2))
3198 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3200 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3202 else if (insn == 0x46f7) /* mov pc, lr */
3204 else if (thumb_instruction_restores_sp (insn))
3206 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3209 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3211 if (target_read_memory (scan_pc, buf, 2))
3215 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3217 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3219 if (insn2 & 0x8000) /* <registers> include PC. */
3222 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3223 && (insn2 & 0x0fff) == 0x0b04)
3225 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3228 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3229 && (insn2 & 0x0e00) == 0x0a00)
3241 /* Since any instruction in the epilogue sequence, with the possible
3242 exception of return itself, updates the stack pointer, we need to
3243 scan backwards for at most one instruction. Try either a 16-bit or
3244 a 32-bit instruction. This is just a heuristic, so we do not worry
3245 too much about false positives. */
3247 if (pc - 4 < func_start)
3249 if (target_read_memory (pc - 4, buf, 4))
3252 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3253 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3255 if (thumb_instruction_restores_sp (insn2))
3256 found_stack_adjust = 1;
3257 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3258 found_stack_adjust = 1;
3259 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3260 && (insn2 & 0x0fff) == 0x0b04)
3261 found_stack_adjust = 1;
3262 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3263 && (insn2 & 0x0e00) == 0x0a00)
3264 found_stack_adjust = 1;
3266 return found_stack_adjust;
3270 arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc)
3272 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3275 CORE_ADDR func_start, func_end;
3277 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3280 /* We are in the epilogue if the previous instruction was a stack
3281 adjustment and the next instruction is a possible return (bx, mov
3282 pc, or pop). We could have to scan backwards to find the stack
3283 adjustment, or forwards to find the return, but this is a decent
3284 approximation. First scan forwards. */
3287 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3288 if (bits (insn, 28, 31) != INST_NV)
3290 if ((insn & 0x0ffffff0) == 0x012fff10)
3293 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3296 else if ((insn & 0x0fff0000) == 0x08bd0000
3297 && (insn & 0x0000c000) != 0)
3298 /* POP (LDMIA), including PC or LR. */
3305 /* Scan backwards. This is just a heuristic, so do not worry about
3306 false positives from mode changes. */
3308 if (pc < func_start + 4)
3311 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3312 if (arm_instruction_restores_sp (insn))
3318 /* Implement the stack_frame_destroyed_p gdbarch method. */
3321 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3323 if (arm_pc_is_thumb (gdbarch, pc))
3324 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3326 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
3329 /* When arguments must be pushed onto the stack, they go on in reverse
3330 order. The code below implements a FILO (stack) to do this. */
3335 struct stack_item *prev;
3339 static struct stack_item *
3340 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
3342 struct stack_item *si;
3343 si = XNEW (struct stack_item);
3344 si->data = (gdb_byte *) xmalloc (len);
3347 memcpy (si->data, contents, len);
3351 static struct stack_item *
3352 pop_stack_item (struct stack_item *si)
3354 struct stack_item *dead = si;
3362 /* Return the alignment (in bytes) of the given type. */
3365 arm_type_align (struct type *t)
3371 t = check_typedef (t);
3372 switch (TYPE_CODE (t))
3375 /* Should never happen. */
3376 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3380 case TYPE_CODE_ENUM:
3384 case TYPE_CODE_RANGE:
3386 case TYPE_CODE_CHAR:
3387 case TYPE_CODE_BOOL:
3388 return TYPE_LENGTH (t);
3390 case TYPE_CODE_ARRAY:
3391 if (TYPE_VECTOR (t))
3393 /* Use the natural alignment for vector types (the same for
3394 scalar type), but the maximum alignment is 64-bit. */
3395 if (TYPE_LENGTH (t) > 8)
3398 return TYPE_LENGTH (t);
3401 return arm_type_align (TYPE_TARGET_TYPE (t));
3402 case TYPE_CODE_COMPLEX:
3403 return arm_type_align (TYPE_TARGET_TYPE (t));
3405 case TYPE_CODE_STRUCT:
3406 case TYPE_CODE_UNION:
3408 for (n = 0; n < TYPE_NFIELDS (t); n++)
3410 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3418 /* Possible base types for a candidate for passing and returning in
3421 enum arm_vfp_cprc_base_type
3430 /* The length of one element of base type B. */
3433 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3437 case VFP_CPRC_SINGLE:
3439 case VFP_CPRC_DOUBLE:
3441 case VFP_CPRC_VEC64:
3443 case VFP_CPRC_VEC128:
3446 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3451 /* The character ('s', 'd' or 'q') for the type of VFP register used
3452 for passing base type B. */
3455 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3459 case VFP_CPRC_SINGLE:
3461 case VFP_CPRC_DOUBLE:
3463 case VFP_CPRC_VEC64:
3465 case VFP_CPRC_VEC128:
3468 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3473 /* Determine whether T may be part of a candidate for passing and
3474 returning in VFP registers, ignoring the limit on the total number
3475 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3476 classification of the first valid component found; if it is not
3477 VFP_CPRC_UNKNOWN, all components must have the same classification
3478 as *BASE_TYPE. If it is found that T contains a type not permitted
3479 for passing and returning in VFP registers, a type differently
3480 classified from *BASE_TYPE, or two types differently classified
3481 from each other, return -1, otherwise return the total number of
3482 base-type elements found (possibly 0 in an empty structure or
3483 array). Vector types are not currently supported, matching the
3484 generic AAPCS support. */
3487 arm_vfp_cprc_sub_candidate (struct type *t,
3488 enum arm_vfp_cprc_base_type *base_type)
3490 t = check_typedef (t);
3491 switch (TYPE_CODE (t))
3494 switch (TYPE_LENGTH (t))
3497 if (*base_type == VFP_CPRC_UNKNOWN)
3498 *base_type = VFP_CPRC_SINGLE;
3499 else if (*base_type != VFP_CPRC_SINGLE)
3504 if (*base_type == VFP_CPRC_UNKNOWN)
3505 *base_type = VFP_CPRC_DOUBLE;
3506 else if (*base_type != VFP_CPRC_DOUBLE)
3515 case TYPE_CODE_COMPLEX:
3516 /* Arguments of complex T where T is one of the types float or
3517 double get treated as if they are implemented as:
3526 switch (TYPE_LENGTH (t))
3529 if (*base_type == VFP_CPRC_UNKNOWN)
3530 *base_type = VFP_CPRC_SINGLE;
3531 else if (*base_type != VFP_CPRC_SINGLE)
3536 if (*base_type == VFP_CPRC_UNKNOWN)
3537 *base_type = VFP_CPRC_DOUBLE;
3538 else if (*base_type != VFP_CPRC_DOUBLE)
3547 case TYPE_CODE_ARRAY:
3549 if (TYPE_VECTOR (t))
3551 /* A 64-bit or 128-bit containerized vector type are VFP
3553 switch (TYPE_LENGTH (t))
3556 if (*base_type == VFP_CPRC_UNKNOWN)
3557 *base_type = VFP_CPRC_VEC64;
3560 if (*base_type == VFP_CPRC_UNKNOWN)
3561 *base_type = VFP_CPRC_VEC128;
3572 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t),
3576 if (TYPE_LENGTH (t) == 0)
3578 gdb_assert (count == 0);
3581 else if (count == 0)
3583 unitlen = arm_vfp_cprc_unit_length (*base_type);
3584 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3585 return TYPE_LENGTH (t) / unitlen;
3590 case TYPE_CODE_STRUCT:
3595 for (i = 0; i < TYPE_NFIELDS (t); i++)
3599 if (!field_is_static (&TYPE_FIELD (t, i)))
3600 sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3602 if (sub_count == -1)
3606 if (TYPE_LENGTH (t) == 0)
3608 gdb_assert (count == 0);
3611 else if (count == 0)
3613 unitlen = arm_vfp_cprc_unit_length (*base_type);
3614 if (TYPE_LENGTH (t) != unitlen * count)
3619 case TYPE_CODE_UNION:
3624 for (i = 0; i < TYPE_NFIELDS (t); i++)
3626 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3628 if (sub_count == -1)
3630 count = (count > sub_count ? count : sub_count);
3632 if (TYPE_LENGTH (t) == 0)
3634 gdb_assert (count == 0);
3637 else if (count == 0)
3639 unitlen = arm_vfp_cprc_unit_length (*base_type);
3640 if (TYPE_LENGTH (t) != unitlen * count)
3652 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3653 if passed to or returned from a non-variadic function with the VFP
3654 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3655 *BASE_TYPE to the base type for T and *COUNT to the number of
3656 elements of that base type before returning. */
3659 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3662 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3663 int c = arm_vfp_cprc_sub_candidate (t, &b);
3664 if (c <= 0 || c > 4)
3671 /* Return 1 if the VFP ABI should be used for passing arguments to and
3672 returning values from a function of type FUNC_TYPE, 0
3676 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3678 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3679 /* Variadic functions always use the base ABI. Assume that functions
3680 without debug info are not variadic. */
3681 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3683 /* The VFP ABI is only supported as a variant of AAPCS. */
3684 if (tdep->arm_abi != ARM_ABI_AAPCS)
3686 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3689 /* We currently only support passing parameters in integer registers, which
3690 conforms with GCC's default model, and VFP argument passing following
3691 the VFP variant of AAPCS. Several other variants exist and
3692 we should probably support some of them based on the selected ABI. */
3695 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3696 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3697 struct value **args, CORE_ADDR sp, int struct_return,
3698 CORE_ADDR struct_addr)
3700 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3704 struct stack_item *si = NULL;
3707 unsigned vfp_regs_free = (1 << 16) - 1;
3709 /* Determine the type of this function and whether the VFP ABI
3711 ftype = check_typedef (value_type (function));
3712 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3713 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3714 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3716 /* Set the return address. For the ARM, the return breakpoint is
3717 always at BP_ADDR. */
3718 if (arm_pc_is_thumb (gdbarch, bp_addr))
3720 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3722 /* Walk through the list of args and determine how large a temporary
3723 stack is required. Need to take care here as structs may be
3724 passed on the stack, and we have to push them. */
3727 argreg = ARM_A1_REGNUM;
3730 /* The struct_return pointer occupies the first parameter
3731 passing register. */
3735 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3736 gdbarch_register_name (gdbarch, argreg),
3737 paddress (gdbarch, struct_addr));
3738 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3742 for (argnum = 0; argnum < nargs; argnum++)
3745 struct type *arg_type;
3746 struct type *target_type;
3747 enum type_code typecode;
3748 const bfd_byte *val;
3750 enum arm_vfp_cprc_base_type vfp_base_type;
3752 int may_use_core_reg = 1;
3754 arg_type = check_typedef (value_type (args[argnum]));
3755 len = TYPE_LENGTH (arg_type);
3756 target_type = TYPE_TARGET_TYPE (arg_type);
3757 typecode = TYPE_CODE (arg_type);
3758 val = value_contents (args[argnum]);
3760 align = arm_type_align (arg_type);
3761 /* Round alignment up to a whole number of words. */
3762 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3763 /* Different ABIs have different maximum alignments. */
3764 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3766 /* The APCS ABI only requires word alignment. */
3767 align = INT_REGISTER_SIZE;
3771 /* The AAPCS requires at most doubleword alignment. */
3772 if (align > INT_REGISTER_SIZE * 2)
3773 align = INT_REGISTER_SIZE * 2;
3777 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3785 /* Because this is a CPRC it cannot go in a core register or
3786 cause a core register to be skipped for alignment.
3787 Either it goes in VFP registers and the rest of this loop
3788 iteration is skipped for this argument, or it goes on the
3789 stack (and the stack alignment code is correct for this
3791 may_use_core_reg = 0;
3793 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3794 shift = unit_length / 4;
3795 mask = (1 << (shift * vfp_base_count)) - 1;
3796 for (regno = 0; regno < 16; regno += shift)
3797 if (((vfp_regs_free >> regno) & mask) == mask)
3806 vfp_regs_free &= ~(mask << regno);
3807 reg_scaled = regno / shift;
3808 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3809 for (i = 0; i < vfp_base_count; i++)
3813 if (reg_char == 'q')
3814 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3815 val + i * unit_length);
3818 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3819 reg_char, reg_scaled + i);
3820 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3822 regcache_cooked_write (regcache, regnum,
3823 val + i * unit_length);
3830 /* This CPRC could not go in VFP registers, so all VFP
3831 registers are now marked as used. */
3836 /* Push stack padding for dowubleword alignment. */
3837 if (nstack & (align - 1))
3839 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3840 nstack += INT_REGISTER_SIZE;
3843 /* Doubleword aligned quantities must go in even register pairs. */
3844 if (may_use_core_reg
3845 && argreg <= ARM_LAST_ARG_REGNUM
3846 && align > INT_REGISTER_SIZE
3850 /* If the argument is a pointer to a function, and it is a
3851 Thumb function, create a LOCAL copy of the value and set
3852 the THUMB bit in it. */
3853 if (TYPE_CODE_PTR == typecode
3854 && target_type != NULL
3855 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3857 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3858 if (arm_pc_is_thumb (gdbarch, regval))
3860 bfd_byte *copy = (bfd_byte *) alloca (len);
3861 store_unsigned_integer (copy, len, byte_order,
3862 MAKE_THUMB_ADDR (regval));
3867 /* Copy the argument to general registers or the stack in
3868 register-sized pieces. Large arguments are split between
3869 registers and stack. */
3872 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3874 = extract_unsigned_integer (val, partial_len, byte_order);
3876 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3878 /* The argument is being passed in a general purpose
3880 if (byte_order == BFD_ENDIAN_BIG)
3881 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3883 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3885 gdbarch_register_name
3887 phex (regval, INT_REGISTER_SIZE));
3888 regcache_cooked_write_unsigned (regcache, argreg, regval);
3893 gdb_byte buf[INT_REGISTER_SIZE];
3895 memset (buf, 0, sizeof (buf));
3896 store_unsigned_integer (buf, partial_len, byte_order, regval);
3898 /* Push the arguments onto the stack. */
3900 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3902 si = push_stack_item (si, buf, INT_REGISTER_SIZE);
3903 nstack += INT_REGISTER_SIZE;
3910 /* If we have an odd number of words to push, then decrement the stack
3911 by one word now, so first stack argument will be dword aligned. */
3918 write_memory (sp, si->data, si->len);
3919 si = pop_stack_item (si);
3922 /* Finally, update teh SP register. */
3923 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3929 /* Always align the frame to an 8-byte boundary. This is required on
3930 some platforms and harmless on the rest. */
3933 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3935 /* Align the stack to eight bytes. */
3936 return sp & ~ (CORE_ADDR) 7;
3940 print_fpu_flags (struct ui_file *file, int flags)
3942 if (flags & (1 << 0))
3943 fputs_filtered ("IVO ", file);
3944 if (flags & (1 << 1))
3945 fputs_filtered ("DVZ ", file);
3946 if (flags & (1 << 2))
3947 fputs_filtered ("OFL ", file);
3948 if (flags & (1 << 3))
3949 fputs_filtered ("UFL ", file);
3950 if (flags & (1 << 4))
3951 fputs_filtered ("INX ", file);
3952 fputc_filtered ('\n', file);
3955 /* Print interesting information about the floating point processor
3956 (if present) or emulator. */
3958 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3959 struct frame_info *frame, const char *args)
3961 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3964 type = (status >> 24) & 127;
3965 if (status & (1 << 31))
3966 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3968 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3969 /* i18n: [floating point unit] mask */
3970 fputs_filtered (_("mask: "), file);
3971 print_fpu_flags (file, status >> 16);
3972 /* i18n: [floating point unit] flags */
3973 fputs_filtered (_("flags: "), file);
3974 print_fpu_flags (file, status);
3977 /* Construct the ARM extended floating point type. */
3978 static struct type *
3979 arm_ext_type (struct gdbarch *gdbarch)
3981 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3983 if (!tdep->arm_ext_type)
3985 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3986 floatformats_arm_ext);
3988 return tdep->arm_ext_type;
3991 static struct type *
3992 arm_neon_double_type (struct gdbarch *gdbarch)
3994 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3996 if (tdep->neon_double_type == NULL)
3998 struct type *t, *elem;
4000 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
4002 elem = builtin_type (gdbarch)->builtin_uint8;
4003 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
4004 elem = builtin_type (gdbarch)->builtin_uint16;
4005 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
4006 elem = builtin_type (gdbarch)->builtin_uint32;
4007 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
4008 elem = builtin_type (gdbarch)->builtin_uint64;
4009 append_composite_type_field (t, "u64", elem);
4010 elem = builtin_type (gdbarch)->builtin_float;
4011 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
4012 elem = builtin_type (gdbarch)->builtin_double;
4013 append_composite_type_field (t, "f64", elem);
4015 TYPE_VECTOR (t) = 1;
4016 TYPE_NAME (t) = "neon_d";
4017 tdep->neon_double_type = t;
4020 return tdep->neon_double_type;
4023 /* FIXME: The vector types are not correctly ordered on big-endian
4024 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4025 bits of d0 - regardless of what unit size is being held in d0. So
4026 the offset of the first uint8 in d0 is 7, but the offset of the
4027 first float is 4. This code works as-is for little-endian
4030 static struct type *
4031 arm_neon_quad_type (struct gdbarch *gdbarch)
4033 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4035 if (tdep->neon_quad_type == NULL)
4037 struct type *t, *elem;
4039 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4041 elem = builtin_type (gdbarch)->builtin_uint8;
4042 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4043 elem = builtin_type (gdbarch)->builtin_uint16;
4044 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4045 elem = builtin_type (gdbarch)->builtin_uint32;
4046 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4047 elem = builtin_type (gdbarch)->builtin_uint64;
4048 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4049 elem = builtin_type (gdbarch)->builtin_float;
4050 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4051 elem = builtin_type (gdbarch)->builtin_double;
4052 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4054 TYPE_VECTOR (t) = 1;
4055 TYPE_NAME (t) = "neon_q";
4056 tdep->neon_quad_type = t;
4059 return tdep->neon_quad_type;
4062 /* Return the GDB type object for the "standard" data type of data in
4065 static struct type *
4066 arm_register_type (struct gdbarch *gdbarch, int regnum)
4068 int num_regs = gdbarch_num_regs (gdbarch);
4070 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4071 && regnum >= num_regs && regnum < num_regs + 32)
4072 return builtin_type (gdbarch)->builtin_float;
4074 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4075 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4076 return arm_neon_quad_type (gdbarch);
4078 /* If the target description has register information, we are only
4079 in this function so that we can override the types of
4080 double-precision registers for NEON. */
4081 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4083 struct type *t = tdesc_register_type (gdbarch, regnum);
4085 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4086 && TYPE_CODE (t) == TYPE_CODE_FLT
4087 && gdbarch_tdep (gdbarch)->have_neon)
4088 return arm_neon_double_type (gdbarch);
4093 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4095 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4096 return builtin_type (gdbarch)->builtin_void;
4098 return arm_ext_type (gdbarch);
4100 else if (regnum == ARM_SP_REGNUM)
4101 return builtin_type (gdbarch)->builtin_data_ptr;
4102 else if (regnum == ARM_PC_REGNUM)
4103 return builtin_type (gdbarch)->builtin_func_ptr;
4104 else if (regnum >= ARRAY_SIZE (arm_register_names))
4105 /* These registers are only supported on targets which supply
4106 an XML description. */
4107 return builtin_type (gdbarch)->builtin_int0;
4109 return builtin_type (gdbarch)->builtin_uint32;
4112 /* Map a DWARF register REGNUM onto the appropriate GDB register
4116 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4118 /* Core integer regs. */
4119 if (reg >= 0 && reg <= 15)
4122 /* Legacy FPA encoding. These were once used in a way which
4123 overlapped with VFP register numbering, so their use is
4124 discouraged, but GDB doesn't support the ARM toolchain
4125 which used them for VFP. */
4126 if (reg >= 16 && reg <= 23)
4127 return ARM_F0_REGNUM + reg - 16;
4129 /* New assignments for the FPA registers. */
4130 if (reg >= 96 && reg <= 103)
4131 return ARM_F0_REGNUM + reg - 96;
4133 /* WMMX register assignments. */
4134 if (reg >= 104 && reg <= 111)
4135 return ARM_WCGR0_REGNUM + reg - 104;
4137 if (reg >= 112 && reg <= 127)
4138 return ARM_WR0_REGNUM + reg - 112;
4140 if (reg >= 192 && reg <= 199)
4141 return ARM_WC0_REGNUM + reg - 192;
4143 /* VFP v2 registers. A double precision value is actually
4144 in d1 rather than s2, but the ABI only defines numbering
4145 for the single precision registers. This will "just work"
4146 in GDB for little endian targets (we'll read eight bytes,
4147 starting in s0 and then progressing to s1), but will be
4148 reversed on big endian targets with VFP. This won't
4149 be a problem for the new Neon quad registers; you're supposed
4150 to use DW_OP_piece for those. */
4151 if (reg >= 64 && reg <= 95)
4155 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4156 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4160 /* VFP v3 / Neon registers. This range is also used for VFP v2
4161 registers, except that it now describes d0 instead of s0. */
4162 if (reg >= 256 && reg <= 287)
4166 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4167 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4174 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4176 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4179 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4181 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4182 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4184 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4185 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4187 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4188 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4190 if (reg < NUM_GREGS)
4191 return SIM_ARM_R0_REGNUM + reg;
4194 if (reg < NUM_FREGS)
4195 return SIM_ARM_FP0_REGNUM + reg;
4198 if (reg < NUM_SREGS)
4199 return SIM_ARM_FPS_REGNUM + reg;
4202 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4205 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4206 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4207 It is thought that this is is the floating-point register format on
4208 little-endian systems. */
4211 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4212 void *dbl, int endianess)
4216 if (endianess == BFD_ENDIAN_BIG)
4217 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4219 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4221 floatformat_from_doublest (fmt, &d, dbl);
4225 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4230 floatformat_to_doublest (fmt, ptr, &d);
4231 if (endianess == BFD_ENDIAN_BIG)
4232 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4234 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4238 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4239 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4240 NULL if an error occurs. BUF is freed. */
4243 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4244 int old_len, int new_len)
4247 int bytes_to_read = new_len - old_len;
4249 new_buf = (gdb_byte *) xmalloc (new_len);
4250 memcpy (new_buf + bytes_to_read, buf, old_len);
4252 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4260 /* An IT block is at most the 2-byte IT instruction followed by
4261 four 4-byte instructions. The furthest back we must search to
4262 find an IT block that affects the current instruction is thus
4263 2 + 3 * 4 == 14 bytes. */
4264 #define MAX_IT_BLOCK_PREFIX 14
4266 /* Use a quick scan if there are more than this many bytes of
4268 #define IT_SCAN_THRESHOLD 32
4270 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4271 A breakpoint in an IT block may not be hit, depending on the
4274 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4278 CORE_ADDR boundary, func_start;
4280 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4281 int i, any, last_it, last_it_count;
4283 /* If we are using BKPT breakpoints, none of this is necessary. */
4284 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4287 /* ARM mode does not have this problem. */
4288 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4291 /* We are setting a breakpoint in Thumb code that could potentially
4292 contain an IT block. The first step is to find how much Thumb
4293 code there is; we do not need to read outside of known Thumb
4295 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4297 /* Thumb-2 code must have mapping symbols to have a chance. */
4300 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4302 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4303 && func_start > boundary)
4304 boundary = func_start;
4306 /* Search for a candidate IT instruction. We have to do some fancy
4307 footwork to distinguish a real IT instruction from the second
4308 half of a 32-bit instruction, but there is no need for that if
4309 there's no candidate. */
4310 buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX);
4312 /* No room for an IT instruction. */
4315 buf = (gdb_byte *) xmalloc (buf_len);
4316 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4319 for (i = 0; i < buf_len; i += 2)
4321 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4322 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4335 /* OK, the code bytes before this instruction contain at least one
4336 halfword which resembles an IT instruction. We know that it's
4337 Thumb code, but there are still two possibilities. Either the
4338 halfword really is an IT instruction, or it is the second half of
4339 a 32-bit Thumb instruction. The only way we can tell is to
4340 scan forwards from a known instruction boundary. */
4341 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
4345 /* There's a lot of code before this instruction. Start with an
4346 optimistic search; it's easy to recognize halfwords that can
4347 not be the start of a 32-bit instruction, and use that to
4348 lock on to the instruction boundaries. */
4349 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
4352 buf_len = IT_SCAN_THRESHOLD;
4355 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
4357 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4358 if (thumb_insn_size (inst1) == 2)
4365 /* At this point, if DEFINITE, BUF[I] is the first place we
4366 are sure that we know the instruction boundaries, and it is far
4367 enough from BPADDR that we could not miss an IT instruction
4368 affecting BPADDR. If ! DEFINITE, give up - start from a
4372 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
4376 buf_len = bpaddr - boundary;
4382 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4385 buf_len = bpaddr - boundary;
4389 /* Scan forwards. Find the last IT instruction before BPADDR. */
4394 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4396 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4401 else if (inst1 & 0x0002)
4403 else if (inst1 & 0x0004)
4408 i += thumb_insn_size (inst1);
4414 /* There wasn't really an IT instruction after all. */
4417 if (last_it_count < 1)
4418 /* It was too far away. */
4421 /* This really is a trouble spot. Move the breakpoint to the IT
4423 return bpaddr - buf_len + last_it;
4426 /* ARM displaced stepping support.
4428 Generally ARM displaced stepping works as follows:
4430 1. When an instruction is to be single-stepped, it is first decoded by
4431 arm_process_displaced_insn. Depending on the type of instruction, it is
4432 then copied to a scratch location, possibly in a modified form. The
4433 copy_* set of functions performs such modification, as necessary. A
4434 breakpoint is placed after the modified instruction in the scratch space
4435 to return control to GDB. Note in particular that instructions which
4436 modify the PC will no longer do so after modification.
4438 2. The instruction is single-stepped, by setting the PC to the scratch
4439 location address, and resuming. Control returns to GDB when the
4442 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4443 function used for the current instruction. This function's job is to
4444 put the CPU/memory state back to what it would have been if the
4445 instruction had been executed unmodified in its original location. */
4447 /* NOP instruction (mov r0, r0). */
4448 #define ARM_NOP 0xe1a00000
4449 #define THUMB_NOP 0x4600
4451 /* Helper for register reads for displaced stepping. In particular, this
4452 returns the PC as it would be seen by the instruction at its original
4456 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4460 CORE_ADDR from = dsc->insn_addr;
4462 if (regno == ARM_PC_REGNUM)
4464 /* Compute pipeline offset:
4465 - When executing an ARM instruction, PC reads as the address of the
4466 current instruction plus 8.
4467 - When executing a Thumb instruction, PC reads as the address of the
4468 current instruction plus 4. */
4475 if (debug_displaced)
4476 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
4477 (unsigned long) from);
4478 return (ULONGEST) from;
4482 regcache_cooked_read_unsigned (regs, regno, &ret);
4483 if (debug_displaced)
4484 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
4485 regno, (unsigned long) ret);
4491 displaced_in_arm_mode (struct regcache *regs)
4494 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4496 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4498 return (ps & t_bit) == 0;
4501 /* Write to the PC as from a branch instruction. */
4504 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4508 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4509 architecture versions < 6. */
4510 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4511 val & ~(ULONGEST) 0x3);
4513 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4514 val & ~(ULONGEST) 0x1);
4517 /* Write to the PC as from a branch-exchange instruction. */
4520 bx_write_pc (struct regcache *regs, ULONGEST val)
4523 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4525 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4529 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
4530 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
4532 else if ((val & 2) == 0)
4534 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4535 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
4539 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4540 mode, align dest to 4 bytes). */
4541 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4542 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4543 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
4547 /* Write to the PC as if from a load instruction. */
4550 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4553 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
4554 bx_write_pc (regs, val);
4556 branch_write_pc (regs, dsc, val);
4559 /* Write to the PC as if from an ALU instruction. */
4562 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4565 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
4566 bx_write_pc (regs, val);
4568 branch_write_pc (regs, dsc, val);
4571 /* Helper for writing to registers for displaced stepping. Writing to the PC
4572 has a varying effects depending on the instruction which does the write:
4573 this is controlled by the WRITE_PC argument. */
4576 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4577 int regno, ULONGEST val, enum pc_write_style write_pc)
4579 if (regno == ARM_PC_REGNUM)
4581 if (debug_displaced)
4582 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
4583 (unsigned long) val);
4586 case BRANCH_WRITE_PC:
4587 branch_write_pc (regs, dsc, val);
4591 bx_write_pc (regs, val);
4595 load_write_pc (regs, dsc, val);
4599 alu_write_pc (regs, dsc, val);
4602 case CANNOT_WRITE_PC:
4603 warning (_("Instruction wrote to PC in an unexpected way when "
4604 "single-stepping"));
4608 internal_error (__FILE__, __LINE__,
4609 _("Invalid argument to displaced_write_reg"));
4612 dsc->wrote_to_pc = 1;
4616 if (debug_displaced)
4617 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
4618 regno, (unsigned long) val);
4619 regcache_cooked_write_unsigned (regs, regno, val);
4623 /* This function is used to concisely determine if an instruction INSN
4624 references PC. Register fields of interest in INSN should have the
4625 corresponding fields of BITMASK set to 0b1111. The function
4626 returns return 1 if any of these fields in INSN reference the PC
4627 (also 0b1111, r15), else it returns 0. */
4630 insn_references_pc (uint32_t insn, uint32_t bitmask)
4632 uint32_t lowbit = 1;
4634 while (bitmask != 0)
4638 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
4644 mask = lowbit * 0xf;
4646 if ((insn & mask) == mask)
4655 /* The simplest copy function. Many instructions have the same effect no
4656 matter what address they are executed at: in those cases, use this. */
4659 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
4660 const char *iname, struct displaced_step_closure *dsc)
4662 if (debug_displaced)
4663 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
4664 "opcode/class '%s' unmodified\n", (unsigned long) insn,
4667 dsc->modinsn[0] = insn;
4673 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
4674 uint16_t insn2, const char *iname,
4675 struct displaced_step_closure *dsc)
4677 if (debug_displaced)
4678 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
4679 "opcode/class '%s' unmodified\n", insn1, insn2,
4682 dsc->modinsn[0] = insn1;
4683 dsc->modinsn[1] = insn2;
4689 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4692 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn,
4694 struct displaced_step_closure *dsc)
4696 if (debug_displaced)
4697 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
4698 "opcode/class '%s' unmodified\n", insn,
4701 dsc->modinsn[0] = insn;
4706 /* Preload instructions with immediate offset. */
4709 cleanup_preload (struct gdbarch *gdbarch,
4710 struct regcache *regs, struct displaced_step_closure *dsc)
4712 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4713 if (!dsc->u.preload.immed)
4714 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4718 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
4719 struct displaced_step_closure *dsc, unsigned int rn)
4722 /* Preload instructions:
4724 {pli/pld} [rn, #+/-imm]
4726 {pli/pld} [r0, #+/-imm]. */
4728 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4729 rn_val = displaced_read_reg (regs, dsc, rn);
4730 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4731 dsc->u.preload.immed = 1;
4733 dsc->cleanup = &cleanup_preload;
4737 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4738 struct displaced_step_closure *dsc)
4740 unsigned int rn = bits (insn, 16, 19);
4742 if (!insn_references_pc (insn, 0x000f0000ul))
4743 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
4745 if (debug_displaced)
4746 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4747 (unsigned long) insn);
4749 dsc->modinsn[0] = insn & 0xfff0ffff;
4751 install_preload (gdbarch, regs, dsc, rn);
4757 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
4758 struct regcache *regs, struct displaced_step_closure *dsc)
4760 unsigned int rn = bits (insn1, 0, 3);
4761 unsigned int u_bit = bit (insn1, 7);
4762 int imm12 = bits (insn2, 0, 11);
4765 if (rn != ARM_PC_REGNUM)
4766 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
4768 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4769 PLD (literal) Encoding T1. */
4770 if (debug_displaced)
4771 fprintf_unfiltered (gdb_stdlog,
4772 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4773 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
4779 /* Rewrite instruction {pli/pld} PC imm12 into:
4780 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4784 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4786 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4787 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4789 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
4791 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
4792 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
4793 dsc->u.preload.immed = 0;
4795 /* {pli/pld} [r0, r1] */
4796 dsc->modinsn[0] = insn1 & 0xfff0;
4797 dsc->modinsn[1] = 0xf001;
4800 dsc->cleanup = &cleanup_preload;
4804 /* Preload instructions with register offset. */
4807 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
4808 struct displaced_step_closure *dsc, unsigned int rn,
4811 ULONGEST rn_val, rm_val;
4813 /* Preload register-offset instructions:
4815 {pli/pld} [rn, rm {, shift}]
4817 {pli/pld} [r0, r1 {, shift}]. */
4819 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4820 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4821 rn_val = displaced_read_reg (regs, dsc, rn);
4822 rm_val = displaced_read_reg (regs, dsc, rm);
4823 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4824 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
4825 dsc->u.preload.immed = 0;
4827 dsc->cleanup = &cleanup_preload;
4831 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
4832 struct regcache *regs,
4833 struct displaced_step_closure *dsc)
4835 unsigned int rn = bits (insn, 16, 19);
4836 unsigned int rm = bits (insn, 0, 3);
4839 if (!insn_references_pc (insn, 0x000f000ful))
4840 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
4842 if (debug_displaced)
4843 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4844 (unsigned long) insn);
4846 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
4848 install_preload_reg (gdbarch, regs, dsc, rn, rm);
4852 /* Copy/cleanup coprocessor load and store instructions. */
4855 cleanup_copro_load_store (struct gdbarch *gdbarch,
4856 struct regcache *regs,
4857 struct displaced_step_closure *dsc)
4859 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
4861 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4863 if (dsc->u.ldst.writeback)
4864 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
4868 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
4869 struct displaced_step_closure *dsc,
4870 int writeback, unsigned int rn)
4874 /* Coprocessor load/store instructions:
4876 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4878 {stc/stc2} [r0, #+/-imm].
4880 ldc/ldc2 are handled identically. */
4882 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4883 rn_val = displaced_read_reg (regs, dsc, rn);
4884 /* PC should be 4-byte aligned. */
4885 rn_val = rn_val & 0xfffffffc;
4886 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4888 dsc->u.ldst.writeback = writeback;
4889 dsc->u.ldst.rn = rn;
4891 dsc->cleanup = &cleanup_copro_load_store;
4895 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
4896 struct regcache *regs,
4897 struct displaced_step_closure *dsc)
4899 unsigned int rn = bits (insn, 16, 19);
4901 if (!insn_references_pc (insn, 0x000f0000ul))
4902 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
4904 if (debug_displaced)
4905 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4906 "load/store insn %.8lx\n", (unsigned long) insn);
4908 dsc->modinsn[0] = insn & 0xfff0ffff;
4910 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
4916 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
4917 uint16_t insn2, struct regcache *regs,
4918 struct displaced_step_closure *dsc)
4920 unsigned int rn = bits (insn1, 0, 3);
4922 if (rn != ARM_PC_REGNUM)
4923 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
4924 "copro load/store", dsc);
4926 if (debug_displaced)
4927 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4928 "load/store insn %.4x%.4x\n", insn1, insn2);
4930 dsc->modinsn[0] = insn1 & 0xfff0;
4931 dsc->modinsn[1] = insn2;
4934 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4935 doesn't support writeback, so pass 0. */
4936 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
4941 /* Clean up branch instructions (actually perform the branch, by setting
4945 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
4946 struct displaced_step_closure *dsc)
4948 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
4949 int branch_taken = condition_true (dsc->u.branch.cond, status);
4950 enum pc_write_style write_pc = dsc->u.branch.exchange
4951 ? BX_WRITE_PC : BRANCH_WRITE_PC;
4956 if (dsc->u.branch.link)
4958 /* The value of LR should be the next insn of current one. In order
4959 not to confuse logic hanlding later insn `bx lr', if current insn mode
4960 is Thumb, the bit 0 of LR value should be set to 1. */
4961 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
4964 next_insn_addr |= 0x1;
4966 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
4970 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
4973 /* Copy B/BL/BLX instructions with immediate destinations. */
4976 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
4977 struct displaced_step_closure *dsc,
4978 unsigned int cond, int exchange, int link, long offset)
4980 /* Implement "BL<cond> <label>" as:
4982 Preparation: cond <- instruction condition
4983 Insn: mov r0, r0 (nop)
4984 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4986 B<cond> similar, but don't set r14 in cleanup. */
4988 dsc->u.branch.cond = cond;
4989 dsc->u.branch.link = link;
4990 dsc->u.branch.exchange = exchange;
4992 dsc->u.branch.dest = dsc->insn_addr;
4993 if (link && exchange)
4994 /* For BLX, offset is computed from the Align (PC, 4). */
4995 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
4998 dsc->u.branch.dest += 4 + offset;
5000 dsc->u.branch.dest += 8 + offset;
5002 dsc->cleanup = &cleanup_branch;
5005 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
5006 struct regcache *regs, struct displaced_step_closure *dsc)
5008 unsigned int cond = bits (insn, 28, 31);
5009 int exchange = (cond == 0xf);
5010 int link = exchange || bit (insn, 24);
5013 if (debug_displaced)
5014 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
5015 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
5016 (unsigned long) insn);
5018 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5019 then arrange the switch into Thumb mode. */
5020 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
5022 offset = bits (insn, 0, 23) << 2;
5024 if (bit (offset, 25))
5025 offset = offset | ~0x3ffffff;
5027 dsc->modinsn[0] = ARM_NOP;
5029 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5034 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
5035 uint16_t insn2, struct regcache *regs,
5036 struct displaced_step_closure *dsc)
5038 int link = bit (insn2, 14);
5039 int exchange = link && !bit (insn2, 12);
5042 int j1 = bit (insn2, 13);
5043 int j2 = bit (insn2, 11);
5044 int s = sbits (insn1, 10, 10);
5045 int i1 = !(j1 ^ bit (insn1, 10));
5046 int i2 = !(j2 ^ bit (insn1, 10));
5048 if (!link && !exchange) /* B */
5050 offset = (bits (insn2, 0, 10) << 1);
5051 if (bit (insn2, 12)) /* Encoding T4 */
5053 offset |= (bits (insn1, 0, 9) << 12)
5059 else /* Encoding T3 */
5061 offset |= (bits (insn1, 0, 5) << 12)
5065 cond = bits (insn1, 6, 9);
5070 offset = (bits (insn1, 0, 9) << 12);
5071 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
5072 offset |= exchange ?
5073 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
5076 if (debug_displaced)
5077 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
5078 "%.4x %.4x with offset %.8lx\n",
5079 link ? (exchange) ? "blx" : "bl" : "b",
5080 insn1, insn2, offset);
5082 dsc->modinsn[0] = THUMB_NOP;
5084 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5088 /* Copy B Thumb instructions. */
5090 thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn,
5091 struct displaced_step_closure *dsc)
5093 unsigned int cond = 0;
5095 unsigned short bit_12_15 = bits (insn, 12, 15);
5096 CORE_ADDR from = dsc->insn_addr;
5098 if (bit_12_15 == 0xd)
5100 /* offset = SignExtend (imm8:0, 32) */
5101 offset = sbits ((insn << 1), 0, 8);
5102 cond = bits (insn, 8, 11);
5104 else if (bit_12_15 == 0xe) /* Encoding T2 */
5106 offset = sbits ((insn << 1), 0, 11);
5110 if (debug_displaced)
5111 fprintf_unfiltered (gdb_stdlog,
5112 "displaced: copying b immediate insn %.4x "
5113 "with offset %d\n", insn, offset);
5115 dsc->u.branch.cond = cond;
5116 dsc->u.branch.link = 0;
5117 dsc->u.branch.exchange = 0;
5118 dsc->u.branch.dest = from + 4 + offset;
5120 dsc->modinsn[0] = THUMB_NOP;
5122 dsc->cleanup = &cleanup_branch;
5127 /* Copy BX/BLX with register-specified destinations. */
5130 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5131 struct displaced_step_closure *dsc, int link,
5132 unsigned int cond, unsigned int rm)
5134 /* Implement {BX,BLX}<cond> <reg>" as:
5136 Preparation: cond <- instruction condition
5137 Insn: mov r0, r0 (nop)
5138 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5140 Don't set r14 in cleanup for BX. */
5142 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5144 dsc->u.branch.cond = cond;
5145 dsc->u.branch.link = link;
5147 dsc->u.branch.exchange = 1;
5149 dsc->cleanup = &cleanup_branch;
5153 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5154 struct regcache *regs, struct displaced_step_closure *dsc)
5156 unsigned int cond = bits (insn, 28, 31);
5159 int link = bit (insn, 5);
5160 unsigned int rm = bits (insn, 0, 3);
5162 if (debug_displaced)
5163 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5164 (unsigned long) insn);
5166 dsc->modinsn[0] = ARM_NOP;
5168 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5173 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
5174 struct regcache *regs,
5175 struct displaced_step_closure *dsc)
5177 int link = bit (insn, 7);
5178 unsigned int rm = bits (insn, 3, 6);
5180 if (debug_displaced)
5181 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
5182 (unsigned short) insn);
5184 dsc->modinsn[0] = THUMB_NOP;
5186 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
5192 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5195 cleanup_alu_imm (struct gdbarch *gdbarch,
5196 struct regcache *regs, struct displaced_step_closure *dsc)
5198 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5199 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5200 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5201 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5205 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5206 struct displaced_step_closure *dsc)
5208 unsigned int rn = bits (insn, 16, 19);
5209 unsigned int rd = bits (insn, 12, 15);
5210 unsigned int op = bits (insn, 21, 24);
5211 int is_mov = (op == 0xd);
5212 ULONGEST rd_val, rn_val;
5214 if (!insn_references_pc (insn, 0x000ff000ul))
5215 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5217 if (debug_displaced)
5218 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5219 "%.8lx\n", is_mov ? "move" : "ALU",
5220 (unsigned long) insn);
5222 /* Instruction is of form:
5224 <op><cond> rd, [rn,] #imm
5228 Preparation: tmp1, tmp2 <- r0, r1;
5230 Insn: <op><cond> r0, r1, #imm
5231 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5234 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5235 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5236 rn_val = displaced_read_reg (regs, dsc, rn);
5237 rd_val = displaced_read_reg (regs, dsc, rd);
5238 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5239 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5243 dsc->modinsn[0] = insn & 0xfff00fff;
5245 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5247 dsc->cleanup = &cleanup_alu_imm;
5253 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
5254 uint16_t insn2, struct regcache *regs,
5255 struct displaced_step_closure *dsc)
5257 unsigned int op = bits (insn1, 5, 8);
5258 unsigned int rn, rm, rd;
5259 ULONGEST rd_val, rn_val;
5261 rn = bits (insn1, 0, 3); /* Rn */
5262 rm = bits (insn2, 0, 3); /* Rm */
5263 rd = bits (insn2, 8, 11); /* Rd */
5265 /* This routine is only called for instruction MOV. */
5266 gdb_assert (op == 0x2 && rn == 0xf);
5268 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
5269 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
5271 if (debug_displaced)
5272 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
5273 "ALU", insn1, insn2);
5275 /* Instruction is of form:
5277 <op><cond> rd, [rn,] #imm
5281 Preparation: tmp1, tmp2 <- r0, r1;
5283 Insn: <op><cond> r0, r1, #imm
5284 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5287 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5288 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5289 rn_val = displaced_read_reg (regs, dsc, rn);
5290 rd_val = displaced_read_reg (regs, dsc, rd);
5291 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5292 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5295 dsc->modinsn[0] = insn1;
5296 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
5299 dsc->cleanup = &cleanup_alu_imm;
5304 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5307 cleanup_alu_reg (struct gdbarch *gdbarch,
5308 struct regcache *regs, struct displaced_step_closure *dsc)
5313 rd_val = displaced_read_reg (regs, dsc, 0);
5315 for (i = 0; i < 3; i++)
5316 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5318 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5322 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
5323 struct displaced_step_closure *dsc,
5324 unsigned int rd, unsigned int rn, unsigned int rm)
5326 ULONGEST rd_val, rn_val, rm_val;
5328 /* Instruction is of form:
5330 <op><cond> rd, [rn,] rm [, <shift>]
5334 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5335 r0, r1, r2 <- rd, rn, rm
5336 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5337 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5340 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5341 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5342 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5343 rd_val = displaced_read_reg (regs, dsc, rd);
5344 rn_val = displaced_read_reg (regs, dsc, rn);
5345 rm_val = displaced_read_reg (regs, dsc, rm);
5346 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5347 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5348 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5351 dsc->cleanup = &cleanup_alu_reg;
5355 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5356 struct displaced_step_closure *dsc)
5358 unsigned int op = bits (insn, 21, 24);
5359 int is_mov = (op == 0xd);
5361 if (!insn_references_pc (insn, 0x000ff00ful))
5362 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
5364 if (debug_displaced)
5365 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
5366 is_mov ? "move" : "ALU", (unsigned long) insn);
5369 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
5371 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
5373 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
5379 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
5380 struct regcache *regs,
5381 struct displaced_step_closure *dsc)
5385 rm = bits (insn, 3, 6);
5386 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
5388 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
5389 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
5391 if (debug_displaced)
5392 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
5393 (unsigned short) insn);
5395 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
5397 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
5402 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5405 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
5406 struct regcache *regs,
5407 struct displaced_step_closure *dsc)
5409 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5412 for (i = 0; i < 4; i++)
5413 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5415 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5419 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
5420 struct displaced_step_closure *dsc,
5421 unsigned int rd, unsigned int rn, unsigned int rm,
5425 ULONGEST rd_val, rn_val, rm_val, rs_val;
5427 /* Instruction is of form:
5429 <op><cond> rd, [rn,] rm, <shift> rs
5433 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5434 r0, r1, r2, r3 <- rd, rn, rm, rs
5435 Insn: <op><cond> r0, r1, r2, <shift> r3
5437 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5441 for (i = 0; i < 4; i++)
5442 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5444 rd_val = displaced_read_reg (regs, dsc, rd);
5445 rn_val = displaced_read_reg (regs, dsc, rn);
5446 rm_val = displaced_read_reg (regs, dsc, rm);
5447 rs_val = displaced_read_reg (regs, dsc, rs);
5448 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5449 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5450 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5451 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
5453 dsc->cleanup = &cleanup_alu_shifted_reg;
5457 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
5458 struct regcache *regs,
5459 struct displaced_step_closure *dsc)
5461 unsigned int op = bits (insn, 21, 24);
5462 int is_mov = (op == 0xd);
5463 unsigned int rd, rn, rm, rs;
5465 if (!insn_references_pc (insn, 0x000fff0ful))
5466 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
5468 if (debug_displaced)
5469 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
5470 "%.8lx\n", is_mov ? "move" : "ALU",
5471 (unsigned long) insn);
5473 rn = bits (insn, 16, 19);
5474 rm = bits (insn, 0, 3);
5475 rs = bits (insn, 8, 11);
5476 rd = bits (insn, 12, 15);
5479 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
5481 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
5483 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
5488 /* Clean up load instructions. */
5491 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
5492 struct displaced_step_closure *dsc)
5494 ULONGEST rt_val, rt_val2 = 0, rn_val;
5496 rt_val = displaced_read_reg (regs, dsc, 0);
5497 if (dsc->u.ldst.xfersize == 8)
5498 rt_val2 = displaced_read_reg (regs, dsc, 1);
5499 rn_val = displaced_read_reg (regs, dsc, 2);
5501 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5502 if (dsc->u.ldst.xfersize > 4)
5503 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5504 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5505 if (!dsc->u.ldst.immed)
5506 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5508 /* Handle register writeback. */
5509 if (dsc->u.ldst.writeback)
5510 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5511 /* Put result in right place. */
5512 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
5513 if (dsc->u.ldst.xfersize == 8)
5514 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5517 /* Clean up store instructions. */
5520 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5521 struct displaced_step_closure *dsc)
5523 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
5525 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5526 if (dsc->u.ldst.xfersize > 4)
5527 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5528 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5529 if (!dsc->u.ldst.immed)
5530 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5531 if (!dsc->u.ldst.restore_r4)
5532 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5535 if (dsc->u.ldst.writeback)
5536 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5539 /* Copy "extra" load/store instructions. These are halfword/doubleword
5540 transfers, which have a different encoding to byte/word transfers. */
5543 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged,
5544 struct regcache *regs, struct displaced_step_closure *dsc)
5546 unsigned int op1 = bits (insn, 20, 24);
5547 unsigned int op2 = bits (insn, 5, 6);
5548 unsigned int rt = bits (insn, 12, 15);
5549 unsigned int rn = bits (insn, 16, 19);
5550 unsigned int rm = bits (insn, 0, 3);
5551 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5552 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5553 int immed = (op1 & 0x4) != 0;
5555 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5557 if (!insn_references_pc (insn, 0x000ff00ful))
5558 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5560 if (debug_displaced)
5561 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5562 "insn %.8lx\n", unprivileged ? "unprivileged " : "",
5563 (unsigned long) insn);
5565 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5568 internal_error (__FILE__, __LINE__,
5569 _("copy_extra_ld_st: instruction decode error"));
5571 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5572 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5573 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5575 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5577 rt_val = displaced_read_reg (regs, dsc, rt);
5578 if (bytesize[opcode] == 8)
5579 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
5580 rn_val = displaced_read_reg (regs, dsc, rn);
5582 rm_val = displaced_read_reg (regs, dsc, rm);
5584 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5585 if (bytesize[opcode] == 8)
5586 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5587 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5589 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5592 dsc->u.ldst.xfersize = bytesize[opcode];
5593 dsc->u.ldst.rn = rn;
5594 dsc->u.ldst.immed = immed;
5595 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5596 dsc->u.ldst.restore_r4 = 0;
5599 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5601 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5602 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5604 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5606 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5607 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5609 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5614 /* Copy byte/half word/word loads and stores. */
5617 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5618 struct displaced_step_closure *dsc, int load,
5619 int immed, int writeback, int size, int usermode,
5620 int rt, int rm, int rn)
5622 ULONGEST rt_val, rn_val, rm_val = 0;
5624 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5625 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5627 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5629 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
5631 rt_val = displaced_read_reg (regs, dsc, rt);
5632 rn_val = displaced_read_reg (regs, dsc, rn);
5634 rm_val = displaced_read_reg (regs, dsc, rm);
5636 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5637 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5639 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5641 dsc->u.ldst.xfersize = size;
5642 dsc->u.ldst.rn = rn;
5643 dsc->u.ldst.immed = immed;
5644 dsc->u.ldst.writeback = writeback;
5646 /* To write PC we can do:
5648 Before this sequence of instructions:
5649 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5650 r2 is the Rn value got from dispalced_read_reg.
5652 Insn1: push {pc} Write address of STR instruction + offset on stack
5653 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5654 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5655 = addr(Insn1) + offset - addr(Insn3) - 8
5657 Insn4: add r4, r4, #8 r4 = offset - 8
5658 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5660 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5662 Otherwise we don't know what value to write for PC, since the offset is
5663 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5664 of this can be found in Section "Saving from r15" in
5665 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5667 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5672 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
5673 uint16_t insn2, struct regcache *regs,
5674 struct displaced_step_closure *dsc, int size)
5676 unsigned int u_bit = bit (insn1, 7);
5677 unsigned int rt = bits (insn2, 12, 15);
5678 int imm12 = bits (insn2, 0, 11);
5681 if (debug_displaced)
5682 fprintf_unfiltered (gdb_stdlog,
5683 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5684 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
5690 /* Rewrite instruction LDR Rt imm12 into:
5692 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5696 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5699 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5700 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5701 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5703 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5705 pc_val = pc_val & 0xfffffffc;
5707 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
5708 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
5712 dsc->u.ldst.xfersize = size;
5713 dsc->u.ldst.immed = 0;
5714 dsc->u.ldst.writeback = 0;
5715 dsc->u.ldst.restore_r4 = 0;
5717 /* LDR R0, R2, R3 */
5718 dsc->modinsn[0] = 0xf852;
5719 dsc->modinsn[1] = 0x3;
5722 dsc->cleanup = &cleanup_load;
5728 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
5729 uint16_t insn2, struct regcache *regs,
5730 struct displaced_step_closure *dsc,
5731 int writeback, int immed)
5733 unsigned int rt = bits (insn2, 12, 15);
5734 unsigned int rn = bits (insn1, 0, 3);
5735 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
5736 /* In LDR (register), there is also a register Rm, which is not allowed to
5737 be PC, so we don't have to check it. */
5739 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
5740 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
5743 if (debug_displaced)
5744 fprintf_unfiltered (gdb_stdlog,
5745 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5746 rt, rn, insn1, insn2);
5748 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
5751 dsc->u.ldst.restore_r4 = 0;
5754 /* ldr[b]<cond> rt, [rn, #imm], etc.
5756 ldr[b]<cond> r0, [r2, #imm]. */
5758 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5759 dsc->modinsn[1] = insn2 & 0x0fff;
5762 /* ldr[b]<cond> rt, [rn, rm], etc.
5764 ldr[b]<cond> r0, [r2, r3]. */
5766 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5767 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
5777 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
5778 struct regcache *regs,
5779 struct displaced_step_closure *dsc,
5780 int load, int size, int usermode)
5782 int immed = !bit (insn, 25);
5783 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
5784 unsigned int rt = bits (insn, 12, 15);
5785 unsigned int rn = bits (insn, 16, 19);
5786 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
5788 if (!insn_references_pc (insn, 0x000ff00ful))
5789 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
5791 if (debug_displaced)
5792 fprintf_unfiltered (gdb_stdlog,
5793 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5794 load ? (size == 1 ? "ldrb" : "ldr")
5795 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
5797 (unsigned long) insn);
5799 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
5800 usermode, rt, rm, rn);
5802 if (load || rt != ARM_PC_REGNUM)
5804 dsc->u.ldst.restore_r4 = 0;
5807 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5809 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5810 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5812 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5814 {ldr,str}[b]<cond> r0, [r2, r3]. */
5815 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5819 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5820 dsc->u.ldst.restore_r4 = 1;
5821 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
5822 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
5823 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
5824 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
5825 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
5829 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
5831 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
5836 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5841 /* Cleanup LDM instructions with fully-populated register list. This is an
5842 unfortunate corner case: it's impossible to implement correctly by modifying
5843 the instruction. The issue is as follows: we have an instruction,
5847 which we must rewrite to avoid loading PC. A possible solution would be to
5848 do the load in two halves, something like (with suitable cleanup
5852 ldm[id][ab] r8!, {r0-r7}
5854 ldm[id][ab] r8, {r7-r14}
5857 but at present there's no suitable place for <temp>, since the scratch space
5858 is overwritten before the cleanup routine is called. For now, we simply
5859 emulate the instruction. */
5862 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
5863 struct displaced_step_closure *dsc)
5865 int inc = dsc->u.block.increment;
5866 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
5867 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
5868 uint32_t regmask = dsc->u.block.regmask;
5869 int regno = inc ? 0 : 15;
5870 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
5871 int exception_return = dsc->u.block.load && dsc->u.block.user
5872 && (regmask & 0x8000) != 0;
5873 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5874 int do_transfer = condition_true (dsc->u.block.cond, status);
5875 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5880 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5881 sensible we can do here. Complain loudly. */
5882 if (exception_return)
5883 error (_("Cannot single-step exception return"));
5885 /* We don't handle any stores here for now. */
5886 gdb_assert (dsc->u.block.load != 0);
5888 if (debug_displaced)
5889 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
5890 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
5891 dsc->u.block.increment ? "inc" : "dec",
5892 dsc->u.block.before ? "before" : "after");
5899 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
5902 while (regno >= 0 && (regmask & (1 << regno)) == 0)
5905 xfer_addr += bump_before;
5907 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
5908 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
5910 xfer_addr += bump_after;
5912 regmask &= ~(1 << regno);
5915 if (dsc->u.block.writeback)
5916 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
5920 /* Clean up an STM which included the PC in the register list. */
5923 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
5924 struct displaced_step_closure *dsc)
5926 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5927 int store_executed = condition_true (dsc->u.block.cond, status);
5928 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
5929 CORE_ADDR stm_insn_addr;
5932 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5934 /* If condition code fails, there's nothing else to do. */
5935 if (!store_executed)
5938 if (dsc->u.block.increment)
5940 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
5942 if (dsc->u.block.before)
5947 pc_stored_at = dsc->u.block.xfer_addr;
5949 if (dsc->u.block.before)
5953 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
5954 stm_insn_addr = dsc->scratch_base;
5955 offset = pc_val - stm_insn_addr;
5957 if (debug_displaced)
5958 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
5959 "STM instruction\n", offset);
5961 /* Rewrite the stored PC to the proper value for the non-displaced original
5963 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
5964 dsc->insn_addr + offset);
5967 /* Clean up an LDM which includes the PC in the register list. We clumped all
5968 the registers in the transferred list into a contiguous range r0...rX (to
5969 avoid loading PC directly and losing control of the debugged program), so we
5970 must undo that here. */
5973 cleanup_block_load_pc (struct gdbarch *gdbarch,
5974 struct regcache *regs,
5975 struct displaced_step_closure *dsc)
5977 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5978 int load_executed = condition_true (dsc->u.block.cond, status);
5979 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
5980 unsigned int regs_loaded = bitcount (mask);
5981 unsigned int num_to_shuffle = regs_loaded, clobbered;
5983 /* The method employed here will fail if the register list is fully populated
5984 (we need to avoid loading PC directly). */
5985 gdb_assert (num_to_shuffle < 16);
5990 clobbered = (1 << num_to_shuffle) - 1;
5992 while (num_to_shuffle > 0)
5994 if ((mask & (1 << write_reg)) != 0)
5996 unsigned int read_reg = num_to_shuffle - 1;
5998 if (read_reg != write_reg)
6000 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6001 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
6002 if (debug_displaced)
6003 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
6004 "loaded register r%d to r%d\n"), read_reg,
6007 else if (debug_displaced)
6008 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
6009 "r%d already in the right place\n"),
6012 clobbered &= ~(1 << write_reg);
6020 /* Restore any registers we scribbled over. */
6021 for (write_reg = 0; clobbered != 0; write_reg++)
6023 if ((clobbered & (1 << write_reg)) != 0)
6025 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
6027 if (debug_displaced)
6028 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
6029 "clobbered register r%d\n"), write_reg);
6030 clobbered &= ~(1 << write_reg);
6034 /* Perform register writeback manually. */
6035 if (dsc->u.block.writeback)
6037 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
6039 if (dsc->u.block.increment)
6040 new_rn_val += regs_loaded * 4;
6042 new_rn_val -= regs_loaded * 4;
6044 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
6049 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6050 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6053 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
6054 struct regcache *regs,
6055 struct displaced_step_closure *dsc)
6057 int load = bit (insn, 20);
6058 int user = bit (insn, 22);
6059 int increment = bit (insn, 23);
6060 int before = bit (insn, 24);
6061 int writeback = bit (insn, 21);
6062 int rn = bits (insn, 16, 19);
6064 /* Block transfers which don't mention PC can be run directly
6066 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
6067 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
6069 if (rn == ARM_PC_REGNUM)
6071 warning (_("displaced: Unpredictable LDM or STM with "
6072 "base register r15"));
6073 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
6076 if (debug_displaced)
6077 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6078 "%.8lx\n", (unsigned long) insn);
6080 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6081 dsc->u.block.rn = rn;
6083 dsc->u.block.load = load;
6084 dsc->u.block.user = user;
6085 dsc->u.block.increment = increment;
6086 dsc->u.block.before = before;
6087 dsc->u.block.writeback = writeback;
6088 dsc->u.block.cond = bits (insn, 28, 31);
6090 dsc->u.block.regmask = insn & 0xffff;
6094 if ((insn & 0xffff) == 0xffff)
6096 /* LDM with a fully-populated register list. This case is
6097 particularly tricky. Implement for now by fully emulating the
6098 instruction (which might not behave perfectly in all cases, but
6099 these instructions should be rare enough for that not to matter
6101 dsc->modinsn[0] = ARM_NOP;
6103 dsc->cleanup = &cleanup_block_load_all;
6107 /* LDM of a list of registers which includes PC. Implement by
6108 rewriting the list of registers to be transferred into a
6109 contiguous chunk r0...rX before doing the transfer, then shuffling
6110 registers into the correct places in the cleanup routine. */
6111 unsigned int regmask = insn & 0xffff;
6112 unsigned int num_in_list = bitcount (regmask), new_regmask;
6115 for (i = 0; i < num_in_list; i++)
6116 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6118 /* Writeback makes things complicated. We need to avoid clobbering
6119 the base register with one of the registers in our modified
6120 register list, but just using a different register can't work in
6123 ldm r14!, {r0-r13,pc}
6125 which would need to be rewritten as:
6129 but that can't work, because there's no free register for N.
6131 Solve this by turning off the writeback bit, and emulating
6132 writeback manually in the cleanup routine. */
6137 new_regmask = (1 << num_in_list) - 1;
6139 if (debug_displaced)
6140 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6141 "{..., pc}: original reg list %.4x, modified "
6142 "list %.4x\n"), rn, writeback ? "!" : "",
6143 (int) insn & 0xffff, new_regmask);
6145 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6147 dsc->cleanup = &cleanup_block_load_pc;
6152 /* STM of a list of registers which includes PC. Run the instruction
6153 as-is, but out of line: this will store the wrong value for the PC,
6154 so we must manually fix up the memory in the cleanup routine.
6155 Doing things this way has the advantage that we can auto-detect
6156 the offset of the PC write (which is architecture-dependent) in
6157 the cleanup routine. */
6158 dsc->modinsn[0] = insn;
6160 dsc->cleanup = &cleanup_block_store_pc;
6167 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6168 struct regcache *regs,
6169 struct displaced_step_closure *dsc)
6171 int rn = bits (insn1, 0, 3);
6172 int load = bit (insn1, 4);
6173 int writeback = bit (insn1, 5);
6175 /* Block transfers which don't mention PC can be run directly
6177 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
6178 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
6180 if (rn == ARM_PC_REGNUM)
6182 warning (_("displaced: Unpredictable LDM or STM with "
6183 "base register r15"));
6184 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6185 "unpredictable ldm/stm", dsc);
6188 if (debug_displaced)
6189 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6190 "%.4x%.4x\n", insn1, insn2);
6192 /* Clear bit 13, since it should be always zero. */
6193 dsc->u.block.regmask = (insn2 & 0xdfff);
6194 dsc->u.block.rn = rn;
6196 dsc->u.block.load = load;
6197 dsc->u.block.user = 0;
6198 dsc->u.block.increment = bit (insn1, 7);
6199 dsc->u.block.before = bit (insn1, 8);
6200 dsc->u.block.writeback = writeback;
6201 dsc->u.block.cond = INST_AL;
6202 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6206 if (dsc->u.block.regmask == 0xffff)
6208 /* This branch is impossible to happen. */
6213 unsigned int regmask = dsc->u.block.regmask;
6214 unsigned int num_in_list = bitcount (regmask), new_regmask;
6217 for (i = 0; i < num_in_list; i++)
6218 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6223 new_regmask = (1 << num_in_list) - 1;
6225 if (debug_displaced)
6226 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6227 "{..., pc}: original reg list %.4x, modified "
6228 "list %.4x\n"), rn, writeback ? "!" : "",
6229 (int) dsc->u.block.regmask, new_regmask);
6231 dsc->modinsn[0] = insn1;
6232 dsc->modinsn[1] = (new_regmask & 0xffff);
6235 dsc->cleanup = &cleanup_block_load_pc;
6240 dsc->modinsn[0] = insn1;
6241 dsc->modinsn[1] = insn2;
6243 dsc->cleanup = &cleanup_block_store_pc;
6248 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6249 This is used to avoid a dependency on BFD's bfd_endian enum. */
6252 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len,
6255 return read_memory_unsigned_integer (memaddr, len,
6256 (enum bfd_endian) byte_order);
6259 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6262 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
6265 return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val);
6268 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6271 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self)
6276 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6279 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self)
6281 return arm_is_thumb (self->regcache);
6284 /* single_step() is called just before we want to resume the inferior,
6285 if we want to single-step it but there is no hardware or kernel
6286 single-step support. We find the target of the coming instructions
6287 and breakpoint them. */
6290 arm_software_single_step (struct frame_info *frame)
6292 struct regcache *regcache = get_current_regcache ();
6293 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6294 struct address_space *aspace = get_regcache_aspace (regcache);
6295 struct arm_get_next_pcs next_pcs_ctx;
6298 VEC (CORE_ADDR) *next_pcs = NULL;
6299 struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
6301 arm_get_next_pcs_ctor (&next_pcs_ctx,
6302 &arm_get_next_pcs_ops,
6303 gdbarch_byte_order (gdbarch),
6304 gdbarch_byte_order_for_code (gdbarch),
6308 next_pcs = arm_get_next_pcs (&next_pcs_ctx);
6310 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
6312 pc = gdbarch_addr_bits_remove (gdbarch, pc);
6313 insert_single_step_breakpoint (gdbarch, aspace, pc);
6316 do_cleanups (old_chain);
6321 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6322 for Linux, where some SVC instructions must be treated specially. */
6325 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6326 struct displaced_step_closure *dsc)
6328 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6330 if (debug_displaced)
6331 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6332 "%.8lx\n", (unsigned long) resume_addr);
6334 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6338 /* Common copy routine for svc instruciton. */
6341 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
6342 struct displaced_step_closure *dsc)
6344 /* Preparation: none.
6345 Insn: unmodified svc.
6346 Cleanup: pc <- insn_addr + insn_size. */
6348 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6350 dsc->wrote_to_pc = 1;
6352 /* Allow OS-specific code to override SVC handling. */
6353 if (dsc->u.svc.copy_svc_os)
6354 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6357 dsc->cleanup = &cleanup_svc;
6363 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6364 struct regcache *regs, struct displaced_step_closure *dsc)
6367 if (debug_displaced)
6368 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6369 (unsigned long) insn);
6371 dsc->modinsn[0] = insn;
6373 return install_svc (gdbarch, regs, dsc);
6377 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
6378 struct regcache *regs, struct displaced_step_closure *dsc)
6381 if (debug_displaced)
6382 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
6385 dsc->modinsn[0] = insn;
6387 return install_svc (gdbarch, regs, dsc);
6390 /* Copy undefined instructions. */
6393 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6394 struct displaced_step_closure *dsc)
6396 if (debug_displaced)
6397 fprintf_unfiltered (gdb_stdlog,
6398 "displaced: copying undefined insn %.8lx\n",
6399 (unsigned long) insn);
6401 dsc->modinsn[0] = insn;
6407 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6408 struct displaced_step_closure *dsc)
6411 if (debug_displaced)
6412 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
6413 "%.4x %.4x\n", (unsigned short) insn1,
6414 (unsigned short) insn2);
6416 dsc->modinsn[0] = insn1;
6417 dsc->modinsn[1] = insn2;
6423 /* Copy unpredictable instructions. */
6426 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
6427 struct displaced_step_closure *dsc)
6429 if (debug_displaced)
6430 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
6431 "%.8lx\n", (unsigned long) insn);
6433 dsc->modinsn[0] = insn;
6438 /* The decode_* functions are instruction decoding helpers. They mostly follow
6439 the presentation in the ARM ARM. */
6442 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
6443 struct regcache *regs,
6444 struct displaced_step_closure *dsc)
6446 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
6447 unsigned int rn = bits (insn, 16, 19);
6449 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
6450 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
6451 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
6452 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
6453 else if ((op1 & 0x60) == 0x20)
6454 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
6455 else if ((op1 & 0x71) == 0x40)
6456 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
6458 else if ((op1 & 0x77) == 0x41)
6459 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6460 else if ((op1 & 0x77) == 0x45)
6461 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
6462 else if ((op1 & 0x77) == 0x51)
6465 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6467 return arm_copy_unpred (gdbarch, insn, dsc);
6469 else if ((op1 & 0x77) == 0x55)
6470 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6471 else if (op1 == 0x57)
6474 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
6475 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
6476 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
6477 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
6478 default: return arm_copy_unpred (gdbarch, insn, dsc);
6480 else if ((op1 & 0x63) == 0x43)
6481 return arm_copy_unpred (gdbarch, insn, dsc);
6482 else if ((op2 & 0x1) == 0x0)
6483 switch (op1 & ~0x80)
6486 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6488 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
6489 case 0x71: case 0x75:
6491 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
6492 case 0x63: case 0x67: case 0x73: case 0x77:
6493 return arm_copy_unpred (gdbarch, insn, dsc);
6495 return arm_copy_undef (gdbarch, insn, dsc);
6498 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
6502 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
6503 struct regcache *regs,
6504 struct displaced_step_closure *dsc)
6506 if (bit (insn, 27) == 0)
6507 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
6508 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6509 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
6512 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
6515 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
6517 case 0x4: case 0x5: case 0x6: case 0x7:
6518 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6521 switch ((insn & 0xe00000) >> 21)
6523 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6525 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6528 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6531 return arm_copy_undef (gdbarch, insn, dsc);
6536 int rn_f = (bits (insn, 16, 19) == 0xf);
6537 switch ((insn & 0xe00000) >> 21)
6540 /* ldc/ldc2 imm (undefined for rn == pc). */
6541 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
6542 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6545 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6547 case 0x4: case 0x5: case 0x6: case 0x7:
6548 /* ldc/ldc2 lit (undefined for rn != pc). */
6549 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
6550 : arm_copy_undef (gdbarch, insn, dsc);
6553 return arm_copy_undef (gdbarch, insn, dsc);
6558 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
6561 if (bits (insn, 16, 19) == 0xf)
6563 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6565 return arm_copy_undef (gdbarch, insn, dsc);
6569 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6571 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6575 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6577 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6580 return arm_copy_undef (gdbarch, insn, dsc);
6584 /* Decode miscellaneous instructions in dp/misc encoding space. */
6587 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
6588 struct regcache *regs,
6589 struct displaced_step_closure *dsc)
6591 unsigned int op2 = bits (insn, 4, 6);
6592 unsigned int op = bits (insn, 21, 22);
6597 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
6600 if (op == 0x1) /* bx. */
6601 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
6603 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
6605 return arm_copy_undef (gdbarch, insn, dsc);
6609 /* Not really supported. */
6610 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
6612 return arm_copy_undef (gdbarch, insn, dsc);
6616 return arm_copy_bx_blx_reg (gdbarch, insn,
6617 regs, dsc); /* blx register. */
6619 return arm_copy_undef (gdbarch, insn, dsc);
6622 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
6626 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
6628 /* Not really supported. */
6629 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
6632 return arm_copy_undef (gdbarch, insn, dsc);
6637 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
6638 struct regcache *regs,
6639 struct displaced_step_closure *dsc)
6642 switch (bits (insn, 20, 24))
6645 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
6648 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
6650 case 0x12: case 0x16:
6651 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
6654 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
6658 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
6660 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
6661 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
6662 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
6663 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
6664 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
6665 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
6666 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
6667 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
6668 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
6669 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
6670 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
6671 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
6672 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
6673 /* 2nd arg means "unprivileged". */
6674 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
6678 /* Should be unreachable. */
6683 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
6684 struct regcache *regs,
6685 struct displaced_step_closure *dsc)
6687 int a = bit (insn, 25), b = bit (insn, 4);
6688 uint32_t op1 = bits (insn, 20, 24);
6690 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
6691 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
6692 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
6693 else if ((!a && (op1 & 0x17) == 0x02)
6694 || (a && (op1 & 0x17) == 0x02 && !b))
6695 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
6696 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
6697 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
6698 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
6699 else if ((!a && (op1 & 0x17) == 0x03)
6700 || (a && (op1 & 0x17) == 0x03 && !b))
6701 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
6702 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
6703 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
6704 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
6705 else if ((!a && (op1 & 0x17) == 0x06)
6706 || (a && (op1 & 0x17) == 0x06 && !b))
6707 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
6708 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
6709 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
6710 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
6711 else if ((!a && (op1 & 0x17) == 0x07)
6712 || (a && (op1 & 0x17) == 0x07 && !b))
6713 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
6715 /* Should be unreachable. */
6720 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
6721 struct displaced_step_closure *dsc)
6723 switch (bits (insn, 20, 24))
6725 case 0x00: case 0x01: case 0x02: case 0x03:
6726 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
6728 case 0x04: case 0x05: case 0x06: case 0x07:
6729 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
6731 case 0x08: case 0x09: case 0x0a: case 0x0b:
6732 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6733 return arm_copy_unmodified (gdbarch, insn,
6734 "decode/pack/unpack/saturate/reverse", dsc);
6737 if (bits (insn, 5, 7) == 0) /* op2. */
6739 if (bits (insn, 12, 15) == 0xf)
6740 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
6742 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
6745 return arm_copy_undef (gdbarch, insn, dsc);
6747 case 0x1a: case 0x1b:
6748 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6749 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
6751 return arm_copy_undef (gdbarch, insn, dsc);
6753 case 0x1c: case 0x1d:
6754 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
6756 if (bits (insn, 0, 3) == 0xf)
6757 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
6759 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
6762 return arm_copy_undef (gdbarch, insn, dsc);
6764 case 0x1e: case 0x1f:
6765 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6766 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
6768 return arm_copy_undef (gdbarch, insn, dsc);
6771 /* Should be unreachable. */
6776 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn,
6777 struct regcache *regs,
6778 struct displaced_step_closure *dsc)
6781 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6783 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
6787 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
6788 struct regcache *regs,
6789 struct displaced_step_closure *dsc)
6791 unsigned int opcode = bits (insn, 20, 24);
6795 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6796 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
6798 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6799 case 0x12: case 0x16:
6800 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
6802 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6803 case 0x13: case 0x17:
6804 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
6806 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6807 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6808 /* Note: no writeback for these instructions. Bit 25 will always be
6809 zero though (via caller), so the following works OK. */
6810 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6813 /* Should be unreachable. */
6817 /* Decode shifted register instructions. */
6820 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
6821 uint16_t insn2, struct regcache *regs,
6822 struct displaced_step_closure *dsc)
6824 /* PC is only allowed to be used in instruction MOV. */
6826 unsigned int op = bits (insn1, 5, 8);
6827 unsigned int rn = bits (insn1, 0, 3);
6829 if (op == 0x2 && rn == 0xf) /* MOV */
6830 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
6832 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6833 "dp (shift reg)", dsc);
6837 /* Decode extension register load/store. Exactly the same as
6838 arm_decode_ext_reg_ld_st. */
6841 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
6842 uint16_t insn2, struct regcache *regs,
6843 struct displaced_step_closure *dsc)
6845 unsigned int opcode = bits (insn1, 4, 8);
6849 case 0x04: case 0x05:
6850 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6851 "vfp/neon vmov", dsc);
6853 case 0x08: case 0x0c: /* 01x00 */
6854 case 0x0a: case 0x0e: /* 01x10 */
6855 case 0x12: case 0x16: /* 10x10 */
6856 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6857 "vfp/neon vstm/vpush", dsc);
6859 case 0x09: case 0x0d: /* 01x01 */
6860 case 0x0b: case 0x0f: /* 01x11 */
6861 case 0x13: case 0x17: /* 10x11 */
6862 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6863 "vfp/neon vldm/vpop", dsc);
6865 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6866 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6868 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6869 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
6872 /* Should be unreachable. */
6877 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn,
6878 struct regcache *regs, struct displaced_step_closure *dsc)
6880 unsigned int op1 = bits (insn, 20, 25);
6881 int op = bit (insn, 4);
6882 unsigned int coproc = bits (insn, 8, 11);
6884 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
6885 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
6886 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
6887 && (coproc & 0xe) != 0xa)
6889 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6890 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
6891 && (coproc & 0xe) != 0xa)
6892 /* ldc/ldc2 imm/lit. */
6893 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6894 else if ((op1 & 0x3e) == 0x00)
6895 return arm_copy_undef (gdbarch, insn, dsc);
6896 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6897 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6898 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6899 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6900 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6901 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6902 else if ((op1 & 0x30) == 0x20 && !op)
6904 if ((coproc & 0xe) == 0xa)
6905 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6907 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6909 else if ((op1 & 0x30) == 0x20 && op)
6910 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6911 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6912 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6913 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6914 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6915 else if ((op1 & 0x30) == 0x30)
6916 return arm_copy_svc (gdbarch, insn, regs, dsc);
6918 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6922 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
6923 uint16_t insn2, struct regcache *regs,
6924 struct displaced_step_closure *dsc)
6926 unsigned int coproc = bits (insn2, 8, 11);
6927 unsigned int bit_5_8 = bits (insn1, 5, 8);
6928 unsigned int bit_9 = bit (insn1, 9);
6929 unsigned int bit_4 = bit (insn1, 4);
6934 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6935 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6937 else if (bit_5_8 == 0) /* UNDEFINED. */
6938 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
6941 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6942 if ((coproc & 0xe) == 0xa)
6943 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
6945 else /* coproc is not 101x. */
6947 if (bit_4 == 0) /* STC/STC2. */
6948 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6950 else /* LDC/LDC2 {literal, immeidate}. */
6951 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
6957 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
6963 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
6964 struct displaced_step_closure *dsc, int rd)
6970 Preparation: Rd <- PC
6976 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6977 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
6981 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
6982 struct displaced_step_closure *dsc,
6983 int rd, unsigned int imm)
6986 /* Encoding T2: ADDS Rd, #imm */
6987 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
6989 install_pc_relative (gdbarch, regs, dsc, rd);
6995 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
6996 struct regcache *regs,
6997 struct displaced_step_closure *dsc)
6999 unsigned int rd = bits (insn, 8, 10);
7000 unsigned int imm8 = bits (insn, 0, 7);
7002 if (debug_displaced)
7003 fprintf_unfiltered (gdb_stdlog,
7004 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7007 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7011 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7012 uint16_t insn2, struct regcache *regs,
7013 struct displaced_step_closure *dsc)
7015 unsigned int rd = bits (insn2, 8, 11);
7016 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7017 extract raw immediate encoding rather than computing immediate. When
7018 generating ADD or SUB instruction, we can simply perform OR operation to
7019 set immediate into ADD. */
7020 unsigned int imm_3_8 = insn2 & 0x70ff;
7021 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7023 if (debug_displaced)
7024 fprintf_unfiltered (gdb_stdlog,
7025 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7026 rd, imm_i, imm_3_8, insn1, insn2);
7028 if (bit (insn1, 7)) /* Encoding T2 */
7030 /* Encoding T3: SUB Rd, Rd, #imm */
7031 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7032 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7034 else /* Encoding T3 */
7036 /* Encoding T3: ADD Rd, Rd, #imm */
7037 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7038 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7042 install_pc_relative (gdbarch, regs, dsc, rd);
7048 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1,
7049 struct regcache *regs,
7050 struct displaced_step_closure *dsc)
7052 unsigned int rt = bits (insn1, 8, 10);
7054 int imm8 = (bits (insn1, 0, 7) << 2);
7060 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7062 Insn: LDR R0, [R2, R3];
7063 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7065 if (debug_displaced)
7066 fprintf_unfiltered (gdb_stdlog,
7067 "displaced: copying thumb ldr r%d [pc #%d]\n"
7070 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
7071 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
7072 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
7073 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7074 /* The assembler calculates the required value of the offset from the
7075 Align(PC,4) value of this instruction to the label. */
7076 pc = pc & 0xfffffffc;
7078 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
7079 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
7082 dsc->u.ldst.xfersize = 4;
7084 dsc->u.ldst.immed = 0;
7085 dsc->u.ldst.writeback = 0;
7086 dsc->u.ldst.restore_r4 = 0;
7088 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7090 dsc->cleanup = &cleanup_load;
7095 /* Copy Thumb cbnz/cbz insruction. */
7098 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
7099 struct regcache *regs,
7100 struct displaced_step_closure *dsc)
7102 int non_zero = bit (insn1, 11);
7103 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
7104 CORE_ADDR from = dsc->insn_addr;
7105 int rn = bits (insn1, 0, 2);
7106 int rn_val = displaced_read_reg (regs, dsc, rn);
7108 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
7109 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7110 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7111 condition is false, let it be, cleanup_branch will do nothing. */
7112 if (dsc->u.branch.cond)
7114 dsc->u.branch.cond = INST_AL;
7115 dsc->u.branch.dest = from + 4 + imm5;
7118 dsc->u.branch.dest = from + 2;
7120 dsc->u.branch.link = 0;
7121 dsc->u.branch.exchange = 0;
7123 if (debug_displaced)
7124 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
7125 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
7126 rn, rn_val, insn1, dsc->u.branch.dest);
7128 dsc->modinsn[0] = THUMB_NOP;
7130 dsc->cleanup = &cleanup_branch;
7134 /* Copy Table Branch Byte/Halfword */
7136 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7137 uint16_t insn2, struct regcache *regs,
7138 struct displaced_step_closure *dsc)
7140 ULONGEST rn_val, rm_val;
7141 int is_tbh = bit (insn2, 4);
7142 CORE_ADDR halfwords = 0;
7143 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7145 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7146 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7152 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7153 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7159 target_read_memory (rn_val + rm_val, buf, 1);
7160 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7163 if (debug_displaced)
7164 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7165 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7166 (unsigned int) rn_val, (unsigned int) rm_val,
7167 (unsigned int) halfwords);
7169 dsc->u.branch.cond = INST_AL;
7170 dsc->u.branch.link = 0;
7171 dsc->u.branch.exchange = 0;
7172 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7174 dsc->cleanup = &cleanup_branch;
7180 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
7181 struct displaced_step_closure *dsc)
7184 int val = displaced_read_reg (regs, dsc, 7);
7185 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
7188 val = displaced_read_reg (regs, dsc, 8);
7189 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
7192 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
7197 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1,
7198 struct regcache *regs,
7199 struct displaced_step_closure *dsc)
7201 dsc->u.block.regmask = insn1 & 0x00ff;
7203 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7206 (1) register list is full, that is, r0-r7 are used.
7207 Prepare: tmp[0] <- r8
7209 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7210 MOV r8, r7; Move value of r7 to r8;
7211 POP {r7}; Store PC value into r7.
7213 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7215 (2) register list is not full, supposing there are N registers in
7216 register list (except PC, 0 <= N <= 7).
7217 Prepare: for each i, 0 - N, tmp[i] <- ri.
7219 POP {r0, r1, ...., rN};
7221 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7222 from tmp[] properly.
7224 if (debug_displaced)
7225 fprintf_unfiltered (gdb_stdlog,
7226 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7227 dsc->u.block.regmask, insn1);
7229 if (dsc->u.block.regmask == 0xff)
7231 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
7233 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
7234 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
7235 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
7238 dsc->cleanup = &cleanup_pop_pc_16bit_all;
7242 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
7244 unsigned int new_regmask;
7246 for (i = 0; i < num_in_list + 1; i++)
7247 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7249 new_regmask = (1 << (num_in_list + 1)) - 1;
7251 if (debug_displaced)
7252 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
7253 "{..., pc}: original reg list %.4x,"
7254 " modified list %.4x\n"),
7255 (int) dsc->u.block.regmask, new_regmask);
7257 dsc->u.block.regmask |= 0x8000;
7258 dsc->u.block.writeback = 0;
7259 dsc->u.block.cond = INST_AL;
7261 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
7263 dsc->cleanup = &cleanup_block_load_pc;
7270 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7271 struct regcache *regs,
7272 struct displaced_step_closure *dsc)
7274 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
7275 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
7278 /* 16-bit thumb instructions. */
7279 switch (op_bit_12_15)
7281 /* Shift (imme), add, subtract, move and compare. */
7282 case 0: case 1: case 2: case 3:
7283 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7284 "shift/add/sub/mov/cmp",
7288 switch (op_bit_10_11)
7290 case 0: /* Data-processing */
7291 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7295 case 1: /* Special data instructions and branch and exchange. */
7297 unsigned short op = bits (insn1, 7, 9);
7298 if (op == 6 || op == 7) /* BX or BLX */
7299 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
7300 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7301 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
7303 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
7307 default: /* LDR (literal) */
7308 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
7311 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7312 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
7315 if (op_bit_10_11 < 2) /* Generate PC-relative address */
7316 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
7317 else /* Generate SP-relative address */
7318 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
7320 case 11: /* Misc 16-bit instructions */
7322 switch (bits (insn1, 8, 11))
7324 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7325 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
7327 case 12: case 13: /* POP */
7328 if (bit (insn1, 8)) /* PC is in register list. */
7329 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
7331 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
7333 case 15: /* If-Then, and hints */
7334 if (bits (insn1, 0, 3))
7335 /* If-Then makes up to four following instructions conditional.
7336 IT instruction itself is not conditional, so handle it as a
7337 common unmodified instruction. */
7338 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
7341 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
7344 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
7349 if (op_bit_10_11 < 2) /* Store multiple registers */
7350 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
7351 else /* Load multiple registers */
7352 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
7354 case 13: /* Conditional branch and supervisor call */
7355 if (bits (insn1, 9, 11) != 7) /* conditional branch */
7356 err = thumb_copy_b (gdbarch, insn1, dsc);
7358 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
7360 case 14: /* Unconditional branch */
7361 err = thumb_copy_b (gdbarch, insn1, dsc);
7368 internal_error (__FILE__, __LINE__,
7369 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7373 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
7374 uint16_t insn1, uint16_t insn2,
7375 struct regcache *regs,
7376 struct displaced_step_closure *dsc)
7378 int rt = bits (insn2, 12, 15);
7379 int rn = bits (insn1, 0, 3);
7380 int op1 = bits (insn1, 7, 8);
7382 switch (bits (insn1, 5, 6))
7384 case 0: /* Load byte and memory hints */
7385 if (rt == 0xf) /* PLD/PLI */
7388 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7389 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
7391 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7396 if (rn == 0xf) /* LDRB/LDRSB (literal) */
7397 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7400 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7401 "ldrb{reg, immediate}/ldrbt",
7406 case 1: /* Load halfword and memory hints. */
7407 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
7408 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7409 "pld/unalloc memhint", dsc);
7413 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7416 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7420 case 2: /* Load word */
7422 int insn2_bit_8_11 = bits (insn2, 8, 11);
7425 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
7426 else if (op1 == 0x1) /* Encoding T3 */
7427 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
7429 else /* op1 == 0x0 */
7431 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
7432 /* LDR (immediate) */
7433 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7434 dsc, bit (insn2, 8), 1);
7435 else if (insn2_bit_8_11 == 0xe) /* LDRT */
7436 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7439 /* LDR (register) */
7440 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7446 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7453 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7454 uint16_t insn2, struct regcache *regs,
7455 struct displaced_step_closure *dsc)
7458 unsigned short op = bit (insn2, 15);
7459 unsigned int op1 = bits (insn1, 11, 12);
7465 switch (bits (insn1, 9, 10))
7470 /* Load/store {dual, execlusive}, table branch. */
7471 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
7472 && bits (insn2, 5, 7) == 0)
7473 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
7476 /* PC is not allowed to use in load/store {dual, exclusive}
7478 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7479 "load/store dual/ex", dsc);
7481 else /* load/store multiple */
7483 switch (bits (insn1, 7, 8))
7485 case 0: case 3: /* SRS, RFE */
7486 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7489 case 1: case 2: /* LDM/STM/PUSH/POP */
7490 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
7497 /* Data-processing (shift register). */
7498 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
7501 default: /* Coprocessor instructions. */
7502 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7507 case 2: /* op1 = 2 */
7508 if (op) /* Branch and misc control. */
7510 if (bit (insn2, 14) /* BLX/BL */
7511 || bit (insn2, 12) /* Unconditional branch */
7512 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
7513 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
7515 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7520 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
7522 int op = bits (insn1, 4, 8);
7523 int rn = bits (insn1, 0, 3);
7524 if ((op == 0 || op == 0xa) && rn == 0xf)
7525 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
7528 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7531 else /* Data processing (modified immeidate) */
7532 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7536 case 3: /* op1 = 3 */
7537 switch (bits (insn1, 9, 10))
7541 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
7543 else /* NEON Load/Store and Store single data item */
7544 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7545 "neon elt/struct load/store",
7548 case 1: /* op1 = 3, bits (9, 10) == 1 */
7549 switch (bits (insn1, 7, 8))
7551 case 0: case 1: /* Data processing (register) */
7552 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7555 case 2: /* Multiply and absolute difference */
7556 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7557 "mul/mua/diff", dsc);
7559 case 3: /* Long multiply and divide */
7560 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7565 default: /* Coprocessor instructions */
7566 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7575 internal_error (__FILE__, __LINE__,
7576 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7581 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7582 struct regcache *regs,
7583 struct displaced_step_closure *dsc)
7585 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7587 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
7589 if (debug_displaced)
7590 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
7591 "at %.8lx\n", insn1, (unsigned long) from);
7594 dsc->insn_size = thumb_insn_size (insn1);
7595 if (thumb_insn_size (insn1) == 4)
7598 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
7599 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
7602 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
7606 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7607 CORE_ADDR to, struct regcache *regs,
7608 struct displaced_step_closure *dsc)
7611 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7614 /* Most displaced instructions use a 1-instruction scratch space, so set this
7615 here and override below if/when necessary. */
7617 dsc->insn_addr = from;
7618 dsc->scratch_base = to;
7619 dsc->cleanup = NULL;
7620 dsc->wrote_to_pc = 0;
7622 if (!displaced_in_arm_mode (regs))
7623 return thumb_process_displaced_insn (gdbarch, from, regs, dsc);
7627 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
7628 if (debug_displaced)
7629 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
7630 "at %.8lx\n", (unsigned long) insn,
7631 (unsigned long) from);
7633 if ((insn & 0xf0000000) == 0xf0000000)
7634 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
7635 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
7637 case 0x0: case 0x1: case 0x2: case 0x3:
7638 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
7641 case 0x4: case 0x5: case 0x6:
7642 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
7646 err = arm_decode_media (gdbarch, insn, dsc);
7649 case 0x8: case 0x9: case 0xa: case 0xb:
7650 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
7653 case 0xc: case 0xd: case 0xe: case 0xf:
7654 err = arm_decode_svc_copro (gdbarch, insn, regs, dsc);
7659 internal_error (__FILE__, __LINE__,
7660 _("arm_process_displaced_insn: Instruction decode error"));
7663 /* Actually set up the scratch space for a displaced instruction. */
7666 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
7667 CORE_ADDR to, struct displaced_step_closure *dsc)
7669 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7670 unsigned int i, len, offset;
7671 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7672 int size = dsc->is_thumb? 2 : 4;
7673 const gdb_byte *bkp_insn;
7676 /* Poke modified instruction(s). */
7677 for (i = 0; i < dsc->numinsns; i++)
7679 if (debug_displaced)
7681 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
7683 fprintf_unfiltered (gdb_stdlog, "%.8lx",
7686 fprintf_unfiltered (gdb_stdlog, "%.4x",
7687 (unsigned short)dsc->modinsn[i]);
7689 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
7690 (unsigned long) to + offset);
7693 write_memory_unsigned_integer (to + offset, size,
7694 byte_order_for_code,
7699 /* Choose the correct breakpoint instruction. */
7702 bkp_insn = tdep->thumb_breakpoint;
7703 len = tdep->thumb_breakpoint_size;
7707 bkp_insn = tdep->arm_breakpoint;
7708 len = tdep->arm_breakpoint_size;
7711 /* Put breakpoint afterwards. */
7712 write_memory (to + offset, bkp_insn, len);
7714 if (debug_displaced)
7715 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
7716 paddress (gdbarch, from), paddress (gdbarch, to));
7719 /* Entry point for cleaning things up after a displaced instruction has been
7723 arm_displaced_step_fixup (struct gdbarch *gdbarch,
7724 struct displaced_step_closure *dsc,
7725 CORE_ADDR from, CORE_ADDR to,
7726 struct regcache *regs)
7729 dsc->cleanup (gdbarch, regs, dsc);
7731 if (!dsc->wrote_to_pc)
7732 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
7733 dsc->insn_addr + dsc->insn_size);
7737 #include "bfd-in2.h"
7738 #include "libcoff.h"
7741 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
7743 struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
7745 if (arm_pc_is_thumb (gdbarch, memaddr))
7747 static asymbol *asym;
7748 static combined_entry_type ce;
7749 static struct coff_symbol_struct csym;
7750 static struct bfd fake_bfd;
7751 static bfd_target fake_target;
7753 if (csym.native == NULL)
7755 /* Create a fake symbol vector containing a Thumb symbol.
7756 This is solely so that the code in print_insn_little_arm()
7757 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7758 the presence of a Thumb symbol and switch to decoding
7759 Thumb instructions. */
7761 fake_target.flavour = bfd_target_coff_flavour;
7762 fake_bfd.xvec = &fake_target;
7763 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
7765 csym.symbol.the_bfd = &fake_bfd;
7766 csym.symbol.name = "fake";
7767 asym = (asymbol *) & csym;
7770 memaddr = UNMAKE_THUMB_ADDR (memaddr);
7771 info->symbols = &asym;
7774 info->symbols = NULL;
7776 if (info->endian == BFD_ENDIAN_BIG)
7777 return print_insn_big_arm (memaddr, info);
7779 return print_insn_little_arm (memaddr, info);
7782 /* The following define instruction sequences that will cause ARM
7783 cpu's to take an undefined instruction trap. These are used to
7784 signal a breakpoint to GDB.
7786 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7787 modes. A different instruction is required for each mode. The ARM
7788 cpu's can also be big or little endian. Thus four different
7789 instructions are needed to support all cases.
7791 Note: ARMv4 defines several new instructions that will take the
7792 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7793 not in fact add the new instructions. The new undefined
7794 instructions in ARMv4 are all instructions that had no defined
7795 behaviour in earlier chips. There is no guarantee that they will
7796 raise an exception, but may be treated as NOP's. In practice, it
7797 may only safe to rely on instructions matching:
7799 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7800 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7801 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7803 Even this may only true if the condition predicate is true. The
7804 following use a condition predicate of ALWAYS so it is always TRUE.
7806 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7807 and NetBSD all use a software interrupt rather than an undefined
7808 instruction to force a trap. This can be handled by by the
7809 abi-specific code during establishment of the gdbarch vector. */
7811 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7812 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7813 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7814 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7816 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
7817 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
7818 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
7819 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
7821 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7824 arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
7826 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7827 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7829 if (arm_pc_is_thumb (gdbarch, *pcptr))
7831 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
7833 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7834 check whether we are replacing a 32-bit instruction. */
7835 if (tdep->thumb2_breakpoint != NULL)
7839 if (target_read_memory (*pcptr, buf, 2) == 0)
7841 unsigned short inst1;
7843 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
7844 if (thumb_insn_size (inst1) == 4)
7845 return ARM_BP_KIND_THUMB2;
7849 return ARM_BP_KIND_THUMB;
7852 return ARM_BP_KIND_ARM;
7856 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7858 static const gdb_byte *
7859 arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
7861 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7865 case ARM_BP_KIND_ARM:
7866 *size = tdep->arm_breakpoint_size;
7867 return tdep->arm_breakpoint;
7868 case ARM_BP_KIND_THUMB:
7869 *size = tdep->thumb_breakpoint_size;
7870 return tdep->thumb_breakpoint;
7871 case ARM_BP_KIND_THUMB2:
7872 *size = tdep->thumb2_breakpoint_size;
7873 return tdep->thumb2_breakpoint;
7875 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7879 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7882 arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
7883 struct regcache *regcache,
7888 /* Check the memory pointed by PC is readable. */
7889 if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
7891 struct arm_get_next_pcs next_pcs_ctx;
7894 VEC (CORE_ADDR) *next_pcs = NULL;
7895 struct cleanup *old_chain
7896 = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
7898 arm_get_next_pcs_ctor (&next_pcs_ctx,
7899 &arm_get_next_pcs_ops,
7900 gdbarch_byte_order (gdbarch),
7901 gdbarch_byte_order_for_code (gdbarch),
7905 next_pcs = arm_get_next_pcs (&next_pcs_ctx);
7907 /* If MEMADDR is the next instruction of current pc, do the
7908 software single step computation, and get the thumb mode by
7909 the destination address. */
7910 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
7912 if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
7914 do_cleanups (old_chain);
7916 if (IS_THUMB_ADDR (pc))
7918 *pcptr = MAKE_THUMB_ADDR (*pcptr);
7919 return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
7922 return ARM_BP_KIND_ARM;
7926 do_cleanups (old_chain);
7929 return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
7932 /* Extract from an array REGBUF containing the (raw) register state a
7933 function return value of type TYPE, and copy that, in virtual
7934 format, into VALBUF. */
7937 arm_extract_return_value (struct type *type, struct regcache *regs,
7940 struct gdbarch *gdbarch = get_regcache_arch (regs);
7941 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7943 if (TYPE_CODE_FLT == TYPE_CODE (type))
7945 switch (gdbarch_tdep (gdbarch)->fp_model)
7949 /* The value is in register F0 in internal format. We need to
7950 extract the raw value and then convert it to the desired
7952 bfd_byte tmpbuf[FP_REGISTER_SIZE];
7954 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
7955 convert_from_extended (floatformat_from_type (type), tmpbuf,
7956 valbuf, gdbarch_byte_order (gdbarch));
7960 case ARM_FLOAT_SOFT_FPA:
7961 case ARM_FLOAT_SOFT_VFP:
7962 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7963 not using the VFP ABI code. */
7965 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
7966 if (TYPE_LENGTH (type) > 4)
7967 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7968 valbuf + INT_REGISTER_SIZE);
7972 internal_error (__FILE__, __LINE__,
7973 _("arm_extract_return_value: "
7974 "Floating point model not supported"));
7978 else if (TYPE_CODE (type) == TYPE_CODE_INT
7979 || TYPE_CODE (type) == TYPE_CODE_CHAR
7980 || TYPE_CODE (type) == TYPE_CODE_BOOL
7981 || TYPE_CODE (type) == TYPE_CODE_PTR
7982 || TYPE_CODE (type) == TYPE_CODE_REF
7983 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7985 /* If the type is a plain integer, then the access is
7986 straight-forward. Otherwise we have to play around a bit
7988 int len = TYPE_LENGTH (type);
7989 int regno = ARM_A1_REGNUM;
7994 /* By using store_unsigned_integer we avoid having to do
7995 anything special for small big-endian values. */
7996 regcache_cooked_read_unsigned (regs, regno++, &tmp);
7997 store_unsigned_integer (valbuf,
7998 (len > INT_REGISTER_SIZE
7999 ? INT_REGISTER_SIZE : len),
8001 len -= INT_REGISTER_SIZE;
8002 valbuf += INT_REGISTER_SIZE;
8007 /* For a structure or union the behaviour is as if the value had
8008 been stored to word-aligned memory and then loaded into
8009 registers with 32-bit load instruction(s). */
8010 int len = TYPE_LENGTH (type);
8011 int regno = ARM_A1_REGNUM;
8012 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8016 regcache_cooked_read (regs, regno++, tmpbuf);
8017 memcpy (valbuf, tmpbuf,
8018 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8019 len -= INT_REGISTER_SIZE;
8020 valbuf += INT_REGISTER_SIZE;
8026 /* Will a function return an aggregate type in memory or in a
8027 register? Return 0 if an aggregate type can be returned in a
8028 register, 1 if it must be returned in memory. */
8031 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8033 enum type_code code;
8035 type = check_typedef (type);
8037 /* Simple, non-aggregate types (ie not including vectors and
8038 complex) are always returned in a register (or registers). */
8039 code = TYPE_CODE (type);
8040 if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code
8041 && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code)
8044 if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type))
8046 /* Vector values should be returned using ARM registers if they
8047 are not over 16 bytes. */
8048 return (TYPE_LENGTH (type) > 16);
8051 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8053 /* The AAPCS says all aggregates not larger than a word are returned
8055 if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
8064 /* All aggregate types that won't fit in a register must be returned
8066 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8069 /* In the ARM ABI, "integer" like aggregate types are returned in
8070 registers. For an aggregate type to be integer like, its size
8071 must be less than or equal to INT_REGISTER_SIZE and the
8072 offset of each addressable subfield must be zero. Note that bit
8073 fields are not addressable, and all addressable subfields of
8074 unions always start at offset zero.
8076 This function is based on the behaviour of GCC 2.95.1.
8077 See: gcc/arm.c: arm_return_in_memory() for details.
8079 Note: All versions of GCC before GCC 2.95.2 do not set up the
8080 parameters correctly for a function returning the following
8081 structure: struct { float f;}; This should be returned in memory,
8082 not a register. Richard Earnshaw sent me a patch, but I do not
8083 know of any way to detect if a function like the above has been
8084 compiled with the correct calling convention. */
8086 /* Assume all other aggregate types can be returned in a register.
8087 Run a check for structures, unions and arrays. */
8090 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8093 /* Need to check if this struct/union is "integer" like. For
8094 this to be true, its size must be less than or equal to
8095 INT_REGISTER_SIZE and the offset of each addressable
8096 subfield must be zero. Note that bit fields are not
8097 addressable, and unions always start at offset zero. If any
8098 of the subfields is a floating point type, the struct/union
8099 cannot be an integer type. */
8101 /* For each field in the object, check:
8102 1) Is it FP? --> yes, nRc = 1;
8103 2) Is it addressable (bitpos != 0) and
8104 not packed (bitsize == 0)?
8108 for (i = 0; i < TYPE_NFIELDS (type); i++)
8110 enum type_code field_type_code;
8113 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
8116 /* Is it a floating point type field? */
8117 if (field_type_code == TYPE_CODE_FLT)
8123 /* If bitpos != 0, then we have to care about it. */
8124 if (TYPE_FIELD_BITPOS (type, i) != 0)
8126 /* Bitfields are not addressable. If the field bitsize is
8127 zero, then the field is not packed. Hence it cannot be
8128 a bitfield or any other packed type. */
8129 if (TYPE_FIELD_BITSIZE (type, i) == 0)
8142 /* Write into appropriate registers a function return value of type
8143 TYPE, given in virtual format. */
8146 arm_store_return_value (struct type *type, struct regcache *regs,
8147 const gdb_byte *valbuf)
8149 struct gdbarch *gdbarch = get_regcache_arch (regs);
8150 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8152 if (TYPE_CODE (type) == TYPE_CODE_FLT)
8154 gdb_byte buf[MAX_REGISTER_SIZE];
8156 switch (gdbarch_tdep (gdbarch)->fp_model)
8160 convert_to_extended (floatformat_from_type (type), buf, valbuf,
8161 gdbarch_byte_order (gdbarch));
8162 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
8165 case ARM_FLOAT_SOFT_FPA:
8166 case ARM_FLOAT_SOFT_VFP:
8167 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8168 not using the VFP ABI code. */
8170 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
8171 if (TYPE_LENGTH (type) > 4)
8172 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
8173 valbuf + INT_REGISTER_SIZE);
8177 internal_error (__FILE__, __LINE__,
8178 _("arm_store_return_value: Floating "
8179 "point model not supported"));
8183 else if (TYPE_CODE (type) == TYPE_CODE_INT
8184 || TYPE_CODE (type) == TYPE_CODE_CHAR
8185 || TYPE_CODE (type) == TYPE_CODE_BOOL
8186 || TYPE_CODE (type) == TYPE_CODE_PTR
8187 || TYPE_CODE (type) == TYPE_CODE_REF
8188 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8190 if (TYPE_LENGTH (type) <= 4)
8192 /* Values of one word or less are zero/sign-extended and
8194 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8195 LONGEST val = unpack_long (type, valbuf);
8197 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8198 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8202 /* Integral values greater than one word are stored in consecutive
8203 registers starting with r0. This will always be a multiple of
8204 the regiser size. */
8205 int len = TYPE_LENGTH (type);
8206 int regno = ARM_A1_REGNUM;
8210 regcache_cooked_write (regs, regno++, valbuf);
8211 len -= INT_REGISTER_SIZE;
8212 valbuf += INT_REGISTER_SIZE;
8218 /* For a structure or union the behaviour is as if the value had
8219 been stored to word-aligned memory and then loaded into
8220 registers with 32-bit load instruction(s). */
8221 int len = TYPE_LENGTH (type);
8222 int regno = ARM_A1_REGNUM;
8223 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8227 memcpy (tmpbuf, valbuf,
8228 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8229 regcache_cooked_write (regs, regno++, tmpbuf);
8230 len -= INT_REGISTER_SIZE;
8231 valbuf += INT_REGISTER_SIZE;
8237 /* Handle function return values. */
8239 static enum return_value_convention
8240 arm_return_value (struct gdbarch *gdbarch, struct value *function,
8241 struct type *valtype, struct regcache *regcache,
8242 gdb_byte *readbuf, const gdb_byte *writebuf)
8244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8245 struct type *func_type = function ? value_type (function) : NULL;
8246 enum arm_vfp_cprc_base_type vfp_base_type;
8249 if (arm_vfp_abi_for_function (gdbarch, func_type)
8250 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
8252 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
8253 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
8255 for (i = 0; i < vfp_base_count; i++)
8257 if (reg_char == 'q')
8260 arm_neon_quad_write (gdbarch, regcache, i,
8261 writebuf + i * unit_length);
8264 arm_neon_quad_read (gdbarch, regcache, i,
8265 readbuf + i * unit_length);
8272 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
8273 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8276 regcache_cooked_write (regcache, regnum,
8277 writebuf + i * unit_length);
8279 regcache_cooked_read (regcache, regnum,
8280 readbuf + i * unit_length);
8283 return RETURN_VALUE_REGISTER_CONVENTION;
8286 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
8287 || TYPE_CODE (valtype) == TYPE_CODE_UNION
8288 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
8290 if (tdep->struct_return == pcc_struct_return
8291 || arm_return_in_memory (gdbarch, valtype))
8292 return RETURN_VALUE_STRUCT_CONVENTION;
8294 else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX)
8296 if (arm_return_in_memory (gdbarch, valtype))
8297 return RETURN_VALUE_STRUCT_CONVENTION;
8301 arm_store_return_value (valtype, regcache, writebuf);
8304 arm_extract_return_value (valtype, regcache, readbuf);
8306 return RETURN_VALUE_REGISTER_CONVENTION;
8311 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
8313 struct gdbarch *gdbarch = get_frame_arch (frame);
8314 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8315 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8317 gdb_byte buf[INT_REGISTER_SIZE];
8319 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
8321 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
8325 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
8329 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8330 return the target PC. Otherwise return 0. */
8333 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
8337 CORE_ADDR start_addr;
8339 /* Find the starting address and name of the function containing the PC. */
8340 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
8342 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8344 start_addr = arm_skip_bx_reg (frame, pc);
8345 if (start_addr != 0)
8351 /* If PC is in a Thumb call or return stub, return the address of the
8352 target PC, which is in a register. The thunk functions are called
8353 _call_via_xx, where x is the register name. The possible names
8354 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8355 functions, named __ARM_call_via_r[0-7]. */
8356 if (startswith (name, "_call_via_")
8357 || startswith (name, "__ARM_call_via_"))
8359 /* Use the name suffix to determine which register contains the
8361 static char *table[15] =
8362 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8363 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8366 int offset = strlen (name) - 2;
8368 for (regno = 0; regno <= 14; regno++)
8369 if (strcmp (&name[offset], table[regno]) == 0)
8370 return get_frame_register_unsigned (frame, regno);
8373 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8374 non-interworking calls to foo. We could decode the stubs
8375 to find the target but it's easier to use the symbol table. */
8376 namelen = strlen (name);
8377 if (name[0] == '_' && name[1] == '_'
8378 && ((namelen > 2 + strlen ("_from_thumb")
8379 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
8380 || (namelen > 2 + strlen ("_from_arm")
8381 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
8384 int target_len = namelen - 2;
8385 struct bound_minimal_symbol minsym;
8386 struct objfile *objfile;
8387 struct obj_section *sec;
8389 if (name[namelen - 1] == 'b')
8390 target_len -= strlen ("_from_thumb");
8392 target_len -= strlen ("_from_arm");
8394 target_name = (char *) alloca (target_len + 1);
8395 memcpy (target_name, name + 2, target_len);
8396 target_name[target_len] = '\0';
8398 sec = find_pc_section (pc);
8399 objfile = (sec == NULL) ? NULL : sec->objfile;
8400 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
8401 if (minsym.minsym != NULL)
8402 return BMSYMBOL_VALUE_ADDRESS (minsym);
8407 return 0; /* not a stub */
8411 set_arm_command (char *args, int from_tty)
8413 printf_unfiltered (_("\
8414 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8415 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
8419 show_arm_command (char *args, int from_tty)
8421 cmd_show_list (showarmcmdlist, from_tty, "");
8425 arm_update_current_architecture (void)
8427 struct gdbarch_info info;
8429 /* If the current architecture is not ARM, we have nothing to do. */
8430 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
8433 /* Update the architecture. */
8434 gdbarch_info_init (&info);
8436 if (!gdbarch_update_p (info))
8437 internal_error (__FILE__, __LINE__, _("could not update architecture"));
8441 set_fp_model_sfunc (char *args, int from_tty,
8442 struct cmd_list_element *c)
8446 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
8447 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
8449 arm_fp_model = (enum arm_float_model) fp_model;
8453 if (fp_model == ARM_FLOAT_LAST)
8454 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
8457 arm_update_current_architecture ();
8461 show_fp_model (struct ui_file *file, int from_tty,
8462 struct cmd_list_element *c, const char *value)
8464 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8466 if (arm_fp_model == ARM_FLOAT_AUTO
8467 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8468 fprintf_filtered (file, _("\
8469 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8470 fp_model_strings[tdep->fp_model]);
8472 fprintf_filtered (file, _("\
8473 The current ARM floating point model is \"%s\".\n"),
8474 fp_model_strings[arm_fp_model]);
8478 arm_set_abi (char *args, int from_tty,
8479 struct cmd_list_element *c)
8483 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
8484 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
8486 arm_abi_global = (enum arm_abi_kind) arm_abi;
8490 if (arm_abi == ARM_ABI_LAST)
8491 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
8494 arm_update_current_architecture ();
8498 arm_show_abi (struct ui_file *file, int from_tty,
8499 struct cmd_list_element *c, const char *value)
8501 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8503 if (arm_abi_global == ARM_ABI_AUTO
8504 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8505 fprintf_filtered (file, _("\
8506 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8507 arm_abi_strings[tdep->arm_abi]);
8509 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
8514 arm_show_fallback_mode (struct ui_file *file, int from_tty,
8515 struct cmd_list_element *c, const char *value)
8517 fprintf_filtered (file,
8518 _("The current execution mode assumed "
8519 "(when symbols are unavailable) is \"%s\".\n"),
8520 arm_fallback_mode_string);
8524 arm_show_force_mode (struct ui_file *file, int from_tty,
8525 struct cmd_list_element *c, const char *value)
8527 fprintf_filtered (file,
8528 _("The current execution mode assumed "
8529 "(even when symbols are available) is \"%s\".\n"),
8530 arm_force_mode_string);
8533 /* If the user changes the register disassembly style used for info
8534 register and other commands, we have to also switch the style used
8535 in opcodes for disassembly output. This function is run in the "set
8536 arm disassembly" command, and does that. */
8539 set_disassembly_style_sfunc (char *args, int from_tty,
8540 struct cmd_list_element *c)
8542 set_disassembly_style ();
8545 /* Return the ARM register name corresponding to register I. */
8547 arm_register_name (struct gdbarch *gdbarch, int i)
8549 const int num_regs = gdbarch_num_regs (gdbarch);
8551 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
8552 && i >= num_regs && i < num_regs + 32)
8554 static const char *const vfp_pseudo_names[] = {
8555 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8556 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8557 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8558 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8561 return vfp_pseudo_names[i - num_regs];
8564 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
8565 && i >= num_regs + 32 && i < num_regs + 32 + 16)
8567 static const char *const neon_pseudo_names[] = {
8568 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8569 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8572 return neon_pseudo_names[i - num_regs - 32];
8575 if (i >= ARRAY_SIZE (arm_register_names))
8576 /* These registers are only supported on targets which supply
8577 an XML description. */
8580 return arm_register_names[i];
8584 set_disassembly_style (void)
8588 /* Find the style that the user wants. */
8589 for (current = 0; current < num_disassembly_options; current++)
8590 if (disassembly_style == valid_disassembly_styles[current])
8592 gdb_assert (current < num_disassembly_options);
8594 /* Synchronize the disassembler. */
8595 set_arm_regname_option (current);
8598 /* Test whether the coff symbol specific value corresponds to a Thumb
8602 coff_sym_is_thumb (int val)
8604 return (val == C_THUMBEXT
8605 || val == C_THUMBSTAT
8606 || val == C_THUMBEXTFUNC
8607 || val == C_THUMBSTATFUNC
8608 || val == C_THUMBLABEL);
8611 /* arm_coff_make_msymbol_special()
8612 arm_elf_make_msymbol_special()
8614 These functions test whether the COFF or ELF symbol corresponds to
8615 an address in thumb code, and set a "special" bit in a minimal
8616 symbol to indicate that it does. */
8619 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
8621 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
8623 if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal)
8624 == ST_BRANCH_TO_THUMB)
8625 MSYMBOL_SET_SPECIAL (msym);
8629 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
8631 if (coff_sym_is_thumb (val))
8632 MSYMBOL_SET_SPECIAL (msym);
8636 arm_objfile_data_free (struct objfile *objfile, void *arg)
8638 struct arm_per_objfile *data = (struct arm_per_objfile *) arg;
8641 for (i = 0; i < objfile->obfd->section_count; i++)
8642 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
8646 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
8649 const char *name = bfd_asymbol_name (sym);
8650 struct arm_per_objfile *data;
8651 VEC(arm_mapping_symbol_s) **map_p;
8652 struct arm_mapping_symbol new_map_sym;
8654 gdb_assert (name[0] == '$');
8655 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
8658 data = (struct arm_per_objfile *) objfile_data (objfile,
8659 arm_objfile_data_key);
8662 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
8663 struct arm_per_objfile);
8664 set_objfile_data (objfile, arm_objfile_data_key, data);
8665 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
8666 objfile->obfd->section_count,
8667 VEC(arm_mapping_symbol_s) *);
8669 map_p = &data->section_maps[bfd_get_section (sym)->index];
8671 new_map_sym.value = sym->value;
8672 new_map_sym.type = name[1];
8674 /* Assume that most mapping symbols appear in order of increasing
8675 value. If they were randomly distributed, it would be faster to
8676 always push here and then sort at first use. */
8677 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
8679 struct arm_mapping_symbol *prev_map_sym;
8681 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
8682 if (prev_map_sym->value >= sym->value)
8685 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
8686 arm_compare_mapping_symbols);
8687 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
8692 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
8696 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
8698 struct gdbarch *gdbarch = get_regcache_arch (regcache);
8699 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
8701 /* If necessary, set the T bit. */
8704 ULONGEST val, t_bit;
8705 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
8706 t_bit = arm_psr_thumb_bit (gdbarch);
8707 if (arm_pc_is_thumb (gdbarch, pc))
8708 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8711 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8716 /* Read the contents of a NEON quad register, by reading from two
8717 double registers. This is used to implement the quad pseudo
8718 registers, and for argument passing in case the quad registers are
8719 missing; vectors are passed in quad registers when using the VFP
8720 ABI, even if a NEON unit is not present. REGNUM is the index of
8721 the quad register, in [0, 15]. */
8723 static enum register_status
8724 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
8725 int regnum, gdb_byte *buf)
8728 gdb_byte reg_buf[8];
8729 int offset, double_regnum;
8730 enum register_status status;
8732 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8733 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8736 /* d0 is always the least significant half of q0. */
8737 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8742 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8743 if (status != REG_VALID)
8745 memcpy (buf + offset, reg_buf, 8);
8747 offset = 8 - offset;
8748 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
8749 if (status != REG_VALID)
8751 memcpy (buf + offset, reg_buf, 8);
8756 static enum register_status
8757 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
8758 int regnum, gdb_byte *buf)
8760 const int num_regs = gdbarch_num_regs (gdbarch);
8762 gdb_byte reg_buf[8];
8763 int offset, double_regnum;
8765 gdb_assert (regnum >= num_regs);
8768 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8769 /* Quad-precision register. */
8770 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
8773 enum register_status status;
8775 /* Single-precision register. */
8776 gdb_assert (regnum < 32);
8778 /* s0 is always the least significant half of d0. */
8779 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8780 offset = (regnum & 1) ? 0 : 4;
8782 offset = (regnum & 1) ? 4 : 0;
8784 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8785 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8788 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8789 if (status == REG_VALID)
8790 memcpy (buf, reg_buf + offset, 4);
8795 /* Store the contents of BUF to a NEON quad register, by writing to
8796 two double registers. This is used to implement the quad pseudo
8797 registers, and for argument passing in case the quad registers are
8798 missing; vectors are passed in quad registers when using the VFP
8799 ABI, even if a NEON unit is not present. REGNUM is the index
8800 of the quad register, in [0, 15]. */
8803 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
8804 int regnum, const gdb_byte *buf)
8807 int offset, double_regnum;
8809 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8810 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8813 /* d0 is always the least significant half of q0. */
8814 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8819 regcache_raw_write (regcache, double_regnum, buf + offset);
8820 offset = 8 - offset;
8821 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
8825 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
8826 int regnum, const gdb_byte *buf)
8828 const int num_regs = gdbarch_num_regs (gdbarch);
8830 gdb_byte reg_buf[8];
8831 int offset, double_regnum;
8833 gdb_assert (regnum >= num_regs);
8836 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8837 /* Quad-precision register. */
8838 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
8841 /* Single-precision register. */
8842 gdb_assert (regnum < 32);
8844 /* s0 is always the least significant half of d0. */
8845 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8846 offset = (regnum & 1) ? 0 : 4;
8848 offset = (regnum & 1) ? 4 : 0;
8850 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8851 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8854 regcache_raw_read (regcache, double_regnum, reg_buf);
8855 memcpy (reg_buf + offset, buf, 4);
8856 regcache_raw_write (regcache, double_regnum, reg_buf);
8860 static struct value *
8861 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
8863 const int *reg_p = (const int *) baton;
8864 return value_of_register (*reg_p, frame);
8867 static enum gdb_osabi
8868 arm_elf_osabi_sniffer (bfd *abfd)
8870 unsigned int elfosabi;
8871 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
8873 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
8875 if (elfosabi == ELFOSABI_ARM)
8876 /* GNU tools use this value. Check note sections in this case,
8878 bfd_map_over_sections (abfd,
8879 generic_elf_osabi_sniff_abi_tag_sections,
8882 /* Anything else will be handled by the generic ELF sniffer. */
8887 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
8888 struct reggroup *group)
8890 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8891 this, FPS register belongs to save_regroup, restore_reggroup, and
8892 all_reggroup, of course. */
8893 if (regnum == ARM_FPS_REGNUM)
8894 return (group == float_reggroup
8895 || group == save_reggroup
8896 || group == restore_reggroup
8897 || group == all_reggroup);
8899 return default_register_reggroup_p (gdbarch, regnum, group);
8903 /* For backward-compatibility we allow two 'g' packet lengths with
8904 the remote protocol depending on whether FPA registers are
8905 supplied. M-profile targets do not have FPA registers, but some
8906 stubs already exist in the wild which use a 'g' packet which
8907 supplies them albeit with dummy values. The packet format which
8908 includes FPA registers should be considered deprecated for
8909 M-profile targets. */
8912 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
8914 if (gdbarch_tdep (gdbarch)->is_m)
8916 /* If we know from the executable this is an M-profile target,
8917 cater for remote targets whose register set layout is the
8918 same as the FPA layout. */
8919 register_remote_g_packet_guess (gdbarch,
8920 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8921 (16 * INT_REGISTER_SIZE)
8922 + (8 * FP_REGISTER_SIZE)
8923 + (2 * INT_REGISTER_SIZE),
8924 tdesc_arm_with_m_fpa_layout);
8926 /* The regular M-profile layout. */
8927 register_remote_g_packet_guess (gdbarch,
8928 /* r0-r12,sp,lr,pc; xpsr */
8929 (16 * INT_REGISTER_SIZE)
8930 + INT_REGISTER_SIZE,
8933 /* M-profile plus M4F VFP. */
8934 register_remote_g_packet_guess (gdbarch,
8935 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8936 (16 * INT_REGISTER_SIZE)
8937 + (16 * VFP_REGISTER_SIZE)
8938 + (2 * INT_REGISTER_SIZE),
8939 tdesc_arm_with_m_vfp_d16);
8942 /* Otherwise we don't have a useful guess. */
8945 /* Implement the code_of_frame_writable gdbarch method. */
8948 arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame)
8950 if (gdbarch_tdep (gdbarch)->is_m
8951 && get_frame_type (frame) == SIGTRAMP_FRAME)
8953 /* M-profile exception frames return to some magic PCs, where
8954 isn't writable at all. */
8962 /* Initialize the current architecture based on INFO. If possible,
8963 re-use an architecture from ARCHES, which is a list of
8964 architectures already created during this debugging session.
8966 Called e.g. at program startup, when reading a core file, and when
8967 reading a binary file. */
8969 static struct gdbarch *
8970 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8972 struct gdbarch_tdep *tdep;
8973 struct gdbarch *gdbarch;
8974 struct gdbarch_list *best_arch;
8975 enum arm_abi_kind arm_abi = arm_abi_global;
8976 enum arm_float_model fp_model = arm_fp_model;
8977 struct tdesc_arch_data *tdesc_data = NULL;
8979 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
8980 int have_wmmx_registers = 0;
8982 int have_fpa_registers = 1;
8983 const struct target_desc *tdesc = info.target_desc;
8985 /* If we have an object to base this architecture on, try to determine
8988 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
8990 int ei_osabi, e_flags;
8992 switch (bfd_get_flavour (info.abfd))
8994 case bfd_target_aout_flavour:
8995 /* Assume it's an old APCS-style ABI. */
8996 arm_abi = ARM_ABI_APCS;
8999 case bfd_target_coff_flavour:
9000 /* Assume it's an old APCS-style ABI. */
9002 arm_abi = ARM_ABI_APCS;
9005 case bfd_target_elf_flavour:
9006 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9007 e_flags = elf_elfheader (info.abfd)->e_flags;
9009 if (ei_osabi == ELFOSABI_ARM)
9011 /* GNU tools used to use this value, but do not for EABI
9012 objects. There's nowhere to tag an EABI version
9013 anyway, so assume APCS. */
9014 arm_abi = ARM_ABI_APCS;
9016 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
9018 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9019 int attr_arch, attr_profile;
9023 case EF_ARM_EABI_UNKNOWN:
9024 /* Assume GNU tools. */
9025 arm_abi = ARM_ABI_APCS;
9028 case EF_ARM_EABI_VER4:
9029 case EF_ARM_EABI_VER5:
9030 arm_abi = ARM_ABI_AAPCS;
9031 /* EABI binaries default to VFP float ordering.
9032 They may also contain build attributes that can
9033 be used to identify if the VFP argument-passing
9035 if (fp_model == ARM_FLOAT_AUTO)
9038 switch (bfd_elf_get_obj_attr_int (info.abfd,
9042 case AEABI_VFP_args_base:
9043 /* "The user intended FP parameter/result
9044 passing to conform to AAPCS, base
9046 fp_model = ARM_FLOAT_SOFT_VFP;
9048 case AEABI_VFP_args_vfp:
9049 /* "The user intended FP parameter/result
9050 passing to conform to AAPCS, VFP
9052 fp_model = ARM_FLOAT_VFP;
9054 case AEABI_VFP_args_toolchain:
9055 /* "The user intended FP parameter/result
9056 passing to conform to tool chain-specific
9057 conventions" - we don't know any such
9058 conventions, so leave it as "auto". */
9060 case AEABI_VFP_args_compatible:
9061 /* "Code is compatible with both the base
9062 and VFP variants; the user did not permit
9063 non-variadic functions to pass FP
9064 parameters/results" - leave it as
9068 /* Attribute value not mentioned in the
9069 November 2012 ABI, so leave it as
9074 fp_model = ARM_FLOAT_SOFT_VFP;
9080 /* Leave it as "auto". */
9081 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9086 /* Detect M-profile programs. This only works if the
9087 executable file includes build attributes; GCC does
9088 copy them to the executable, but e.g. RealView does
9090 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9092 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9094 Tag_CPU_arch_profile);
9095 /* GCC specifies the profile for v6-M; RealView only
9096 specifies the profile for architectures starting with
9097 V7 (as opposed to architectures with a tag
9098 numerically greater than TAG_CPU_ARCH_V7). */
9099 if (!tdesc_has_registers (tdesc)
9100 && (attr_arch == TAG_CPU_ARCH_V6_M
9101 || attr_arch == TAG_CPU_ARCH_V6S_M
9102 || attr_profile == 'M'))
9107 if (fp_model == ARM_FLOAT_AUTO)
9109 int e_flags = elf_elfheader (info.abfd)->e_flags;
9111 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9114 /* Leave it as "auto". Strictly speaking this case
9115 means FPA, but almost nobody uses that now, and
9116 many toolchains fail to set the appropriate bits
9117 for the floating-point model they use. */
9119 case EF_ARM_SOFT_FLOAT:
9120 fp_model = ARM_FLOAT_SOFT_FPA;
9122 case EF_ARM_VFP_FLOAT:
9123 fp_model = ARM_FLOAT_VFP;
9125 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9126 fp_model = ARM_FLOAT_SOFT_VFP;
9131 if (e_flags & EF_ARM_BE8)
9132 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
9137 /* Leave it as "auto". */
9142 /* Check any target description for validity. */
9143 if (tdesc_has_registers (tdesc))
9145 /* For most registers we require GDB's default names; but also allow
9146 the numeric names for sp / lr / pc, as a convenience. */
9147 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
9148 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
9149 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
9151 const struct tdesc_feature *feature;
9154 feature = tdesc_find_feature (tdesc,
9155 "org.gnu.gdb.arm.core");
9156 if (feature == NULL)
9158 feature = tdesc_find_feature (tdesc,
9159 "org.gnu.gdb.arm.m-profile");
9160 if (feature == NULL)
9166 tdesc_data = tdesc_data_alloc ();
9169 for (i = 0; i < ARM_SP_REGNUM; i++)
9170 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9171 arm_register_names[i]);
9172 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9175 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9178 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9182 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9183 ARM_PS_REGNUM, "xpsr");
9185 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9186 ARM_PS_REGNUM, "cpsr");
9190 tdesc_data_cleanup (tdesc_data);
9194 feature = tdesc_find_feature (tdesc,
9195 "org.gnu.gdb.arm.fpa");
9196 if (feature != NULL)
9199 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9200 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9201 arm_register_names[i]);
9204 tdesc_data_cleanup (tdesc_data);
9209 have_fpa_registers = 0;
9211 feature = tdesc_find_feature (tdesc,
9212 "org.gnu.gdb.xscale.iwmmxt");
9213 if (feature != NULL)
9215 static const char *const iwmmxt_names[] = {
9216 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9217 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9218 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9219 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9223 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9225 &= tdesc_numbered_register (feature, tdesc_data, i,
9226 iwmmxt_names[i - ARM_WR0_REGNUM]);
9228 /* Check for the control registers, but do not fail if they
9230 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9231 tdesc_numbered_register (feature, tdesc_data, i,
9232 iwmmxt_names[i - ARM_WR0_REGNUM]);
9234 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9236 &= tdesc_numbered_register (feature, tdesc_data, i,
9237 iwmmxt_names[i - ARM_WR0_REGNUM]);
9241 tdesc_data_cleanup (tdesc_data);
9245 have_wmmx_registers = 1;
9248 /* If we have a VFP unit, check whether the single precision registers
9249 are present. If not, then we will synthesize them as pseudo
9251 feature = tdesc_find_feature (tdesc,
9252 "org.gnu.gdb.arm.vfp");
9253 if (feature != NULL)
9255 static const char *const vfp_double_names[] = {
9256 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9257 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9258 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9259 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9262 /* Require the double precision registers. There must be either
9265 for (i = 0; i < 32; i++)
9267 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9269 vfp_double_names[i]);
9273 if (!valid_p && i == 16)
9276 /* Also require FPSCR. */
9277 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9278 ARM_FPSCR_REGNUM, "fpscr");
9281 tdesc_data_cleanup (tdesc_data);
9285 if (tdesc_unnumbered_register (feature, "s0") == 0)
9286 have_vfp_pseudos = 1;
9288 vfp_register_count = i;
9290 /* If we have VFP, also check for NEON. The architecture allows
9291 NEON without VFP (integer vector operations only), but GDB
9292 does not support that. */
9293 feature = tdesc_find_feature (tdesc,
9294 "org.gnu.gdb.arm.neon");
9295 if (feature != NULL)
9297 /* NEON requires 32 double-precision registers. */
9300 tdesc_data_cleanup (tdesc_data);
9304 /* If there are quad registers defined by the stub, use
9305 their type; otherwise (normally) provide them with
9306 the default type. */
9307 if (tdesc_unnumbered_register (feature, "q0") == 0)
9308 have_neon_pseudos = 1;
9315 /* If there is already a candidate, use it. */
9316 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
9318 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
9320 if (arm_abi != ARM_ABI_AUTO
9321 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
9324 if (fp_model != ARM_FLOAT_AUTO
9325 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
9328 /* There are various other properties in tdep that we do not
9329 need to check here: those derived from a target description,
9330 since gdbarches with a different target description are
9331 automatically disqualified. */
9333 /* Do check is_m, though, since it might come from the binary. */
9334 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
9337 /* Found a match. */
9341 if (best_arch != NULL)
9343 if (tdesc_data != NULL)
9344 tdesc_data_cleanup (tdesc_data);
9345 return best_arch->gdbarch;
9348 tdep = XCNEW (struct gdbarch_tdep);
9349 gdbarch = gdbarch_alloc (&info, tdep);
9351 /* Record additional information about the architecture we are defining.
9352 These are gdbarch discriminators, like the OSABI. */
9353 tdep->arm_abi = arm_abi;
9354 tdep->fp_model = fp_model;
9356 tdep->have_fpa_registers = have_fpa_registers;
9357 tdep->have_wmmx_registers = have_wmmx_registers;
9358 gdb_assert (vfp_register_count == 0
9359 || vfp_register_count == 16
9360 || vfp_register_count == 32);
9361 tdep->vfp_register_count = vfp_register_count;
9362 tdep->have_vfp_pseudos = have_vfp_pseudos;
9363 tdep->have_neon_pseudos = have_neon_pseudos;
9364 tdep->have_neon = have_neon;
9366 arm_register_g_packet_guesses (gdbarch);
9369 switch (info.byte_order_for_code)
9371 case BFD_ENDIAN_BIG:
9372 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
9373 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
9374 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
9375 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
9379 case BFD_ENDIAN_LITTLE:
9380 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
9381 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
9382 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
9383 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
9388 internal_error (__FILE__, __LINE__,
9389 _("arm_gdbarch_init: bad byte order for float format"));
9392 /* On ARM targets char defaults to unsigned. */
9393 set_gdbarch_char_signed (gdbarch, 0);
9395 /* Note: for displaced stepping, this includes the breakpoint, and one word
9396 of additional scratch space. This setting isn't used for anything beside
9397 displaced stepping at present. */
9398 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
9400 /* This should be low enough for everything. */
9401 tdep->lowest_pc = 0x20;
9402 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
9404 /* The default, for both APCS and AAPCS, is to return small
9405 structures in registers. */
9406 tdep->struct_return = reg_struct_return;
9408 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
9409 set_gdbarch_frame_align (gdbarch, arm_frame_align);
9412 set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable);
9414 set_gdbarch_write_pc (gdbarch, arm_write_pc);
9416 /* Frame handling. */
9417 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
9418 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
9419 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
9421 frame_base_set_default (gdbarch, &arm_normal_base);
9423 /* Address manipulation. */
9424 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
9426 /* Advance PC across function entry code. */
9427 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
9429 /* Detect whether PC is at a point where the stack has been destroyed. */
9430 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
9432 /* Skip trampolines. */
9433 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
9435 /* The stack grows downward. */
9436 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
9438 /* Breakpoint manipulation. */
9439 set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc);
9440 set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind);
9441 set_gdbarch_breakpoint_kind_from_current_state (gdbarch,
9442 arm_breakpoint_kind_from_current_state);
9444 /* Information about registers, etc. */
9445 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
9446 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
9447 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
9448 set_gdbarch_register_type (gdbarch, arm_register_type);
9449 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
9451 /* This "info float" is FPA-specific. Use the generic version if we
9453 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
9454 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
9456 /* Internal <-> external register number maps. */
9457 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
9458 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
9460 set_gdbarch_register_name (gdbarch, arm_register_name);
9462 /* Returning results. */
9463 set_gdbarch_return_value (gdbarch, arm_return_value);
9466 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
9468 /* Minsymbol frobbing. */
9469 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
9470 set_gdbarch_coff_make_msymbol_special (gdbarch,
9471 arm_coff_make_msymbol_special);
9472 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
9474 /* Thumb-2 IT block support. */
9475 set_gdbarch_adjust_breakpoint_address (gdbarch,
9476 arm_adjust_breakpoint_address);
9478 /* Virtual tables. */
9479 set_gdbarch_vbit_in_delta (gdbarch, 1);
9481 /* Hook in the ABI-specific overrides, if they have been registered. */
9482 gdbarch_init_osabi (info, gdbarch);
9484 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
9486 /* Add some default predicates. */
9488 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
9489 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
9490 dwarf2_append_unwinders (gdbarch);
9491 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
9492 frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind);
9493 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
9495 /* Now we have tuned the configuration, set a few final things,
9496 based on what the OS ABI has told us. */
9498 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9499 binaries are always marked. */
9500 if (tdep->arm_abi == ARM_ABI_AUTO)
9501 tdep->arm_abi = ARM_ABI_APCS;
9503 /* Watchpoints are not steppable. */
9504 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9506 /* We used to default to FPA for generic ARM, but almost nobody
9507 uses that now, and we now provide a way for the user to force
9508 the model. So default to the most useful variant. */
9509 if (tdep->fp_model == ARM_FLOAT_AUTO)
9510 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
9512 if (tdep->jb_pc >= 0)
9513 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
9515 /* Floating point sizes and format. */
9516 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
9517 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
9519 set_gdbarch_double_format
9520 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9521 set_gdbarch_long_double_format
9522 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9526 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
9527 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
9530 if (have_vfp_pseudos)
9532 /* NOTE: These are the only pseudo registers used by
9533 the ARM target at the moment. If more are added, a
9534 little more care in numbering will be needed. */
9536 int num_pseudos = 32;
9537 if (have_neon_pseudos)
9539 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
9540 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
9541 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
9546 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
9548 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
9550 /* Override tdesc_register_type to adjust the types of VFP
9551 registers for NEON. */
9552 set_gdbarch_register_type (gdbarch, arm_register_type);
9555 /* Add standard register aliases. We add aliases even for those
9556 nanes which are used by the current architecture - it's simpler,
9557 and does no harm, since nothing ever lists user registers. */
9558 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
9559 user_reg_add (gdbarch, arm_register_aliases[i].name,
9560 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
9566 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
9568 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9573 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9574 (unsigned long) tdep->lowest_pc);
9577 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
9580 _initialize_arm_tdep (void)
9582 struct ui_file *stb;
9584 const char *setname;
9585 const char *setdesc;
9586 const char *const *regnames;
9588 static char *helptext;
9589 char regdesc[1024], *rdptr = regdesc;
9590 size_t rest = sizeof (regdesc);
9592 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
9594 arm_objfile_data_key
9595 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
9597 /* Add ourselves to objfile event chain. */
9598 observer_attach_new_objfile (arm_exidx_new_objfile);
9600 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
9602 /* Register an ELF OS ABI sniffer for ARM binaries. */
9603 gdbarch_register_osabi_sniffer (bfd_arch_arm,
9604 bfd_target_elf_flavour,
9605 arm_elf_osabi_sniffer);
9607 /* Initialize the standard target descriptions. */
9608 initialize_tdesc_arm_with_m ();
9609 initialize_tdesc_arm_with_m_fpa_layout ();
9610 initialize_tdesc_arm_with_m_vfp_d16 ();
9611 initialize_tdesc_arm_with_iwmmxt ();
9612 initialize_tdesc_arm_with_vfpv2 ();
9613 initialize_tdesc_arm_with_vfpv3 ();
9614 initialize_tdesc_arm_with_neon ();
9616 /* Get the number of possible sets of register names defined in opcodes. */
9617 num_disassembly_options = get_arm_regname_num_options ();
9619 /* Add root prefix command for all "set arm"/"show arm" commands. */
9620 add_prefix_cmd ("arm", no_class, set_arm_command,
9621 _("Various ARM-specific commands."),
9622 &setarmcmdlist, "set arm ", 0, &setlist);
9624 add_prefix_cmd ("arm", no_class, show_arm_command,
9625 _("Various ARM-specific commands."),
9626 &showarmcmdlist, "show arm ", 0, &showlist);
9628 /* Sync the opcode insn printer with our register viewer. */
9629 parse_arm_disassembler_option ("reg-names-std");
9631 /* Initialize the array that will be passed to
9632 add_setshow_enum_cmd(). */
9633 valid_disassembly_styles = XNEWVEC (const char *,
9634 num_disassembly_options + 1);
9635 for (i = 0; i < num_disassembly_options; i++)
9637 get_arm_regnames (i, &setname, &setdesc, ®names);
9638 valid_disassembly_styles[i] = setname;
9639 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
9642 /* When we find the default names, tell the disassembler to use
9644 if (!strcmp (setname, "std"))
9646 disassembly_style = setname;
9647 set_arm_regname_option (i);
9650 /* Mark the end of valid options. */
9651 valid_disassembly_styles[num_disassembly_options] = NULL;
9653 /* Create the help text. */
9654 stb = mem_fileopen ();
9655 fprintf_unfiltered (stb, "%s%s%s",
9656 _("The valid values are:\n"),
9658 _("The default is \"std\"."));
9659 helptext = ui_file_xstrdup (stb, NULL);
9660 ui_file_delete (stb);
9662 add_setshow_enum_cmd("disassembler", no_class,
9663 valid_disassembly_styles, &disassembly_style,
9664 _("Set the disassembly style."),
9665 _("Show the disassembly style."),
9667 set_disassembly_style_sfunc,
9668 NULL, /* FIXME: i18n: The disassembly style is
9670 &setarmcmdlist, &showarmcmdlist);
9672 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
9673 _("Set usage of ARM 32-bit mode."),
9674 _("Show usage of ARM 32-bit mode."),
9675 _("When off, a 26-bit PC will be used."),
9677 NULL, /* FIXME: i18n: Usage of ARM 32-bit
9679 &setarmcmdlist, &showarmcmdlist);
9681 /* Add a command to allow the user to force the FPU model. */
9682 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
9683 _("Set the floating point type."),
9684 _("Show the floating point type."),
9685 _("auto - Determine the FP typefrom the OS-ABI.\n\
9686 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9687 fpa - FPA co-processor (GCC compiled).\n\
9688 softvfp - Software FP with pure-endian doubles.\n\
9689 vfp - VFP co-processor."),
9690 set_fp_model_sfunc, show_fp_model,
9691 &setarmcmdlist, &showarmcmdlist);
9693 /* Add a command to allow the user to force the ABI. */
9694 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
9697 NULL, arm_set_abi, arm_show_abi,
9698 &setarmcmdlist, &showarmcmdlist);
9700 /* Add two commands to allow the user to force the assumed
9702 add_setshow_enum_cmd ("fallback-mode", class_support,
9703 arm_mode_strings, &arm_fallback_mode_string,
9704 _("Set the mode assumed when symbols are unavailable."),
9705 _("Show the mode assumed when symbols are unavailable."),
9706 NULL, NULL, arm_show_fallback_mode,
9707 &setarmcmdlist, &showarmcmdlist);
9708 add_setshow_enum_cmd ("force-mode", class_support,
9709 arm_mode_strings, &arm_force_mode_string,
9710 _("Set the mode assumed even when symbols are available."),
9711 _("Show the mode assumed even when symbols are available."),
9712 NULL, NULL, arm_show_force_mode,
9713 &setarmcmdlist, &showarmcmdlist);
9715 /* Debugging flag. */
9716 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
9717 _("Set ARM debugging."),
9718 _("Show ARM debugging."),
9719 _("When on, arm-specific debugging is enabled."),
9721 NULL, /* FIXME: i18n: "ARM debugging is %s. */
9722 &setdebuglist, &showdebuglist);
9725 /* ARM-reversible process record data structures. */
9727 #define ARM_INSN_SIZE_BYTES 4
9728 #define THUMB_INSN_SIZE_BYTES 2
9729 #define THUMB2_INSN_SIZE_BYTES 4
9732 /* Position of the bit within a 32-bit ARM instruction
9733 that defines whether the instruction is a load or store. */
9734 #define INSN_S_L_BIT_NUM 20
9736 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9739 unsigned int reg_len = LENGTH; \
9742 REGS = XNEWVEC (uint32_t, reg_len); \
9743 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9748 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9751 unsigned int mem_len = LENGTH; \
9754 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9755 memcpy(&MEMS->len, &RECORD_BUF[0], \
9756 sizeof(struct arm_mem_r) * LENGTH); \
9761 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9762 #define INSN_RECORDED(ARM_RECORD) \
9763 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9765 /* ARM memory record structure. */
9768 uint32_t len; /* Record length. */
9769 uint32_t addr; /* Memory address. */
9772 /* ARM instruction record contains opcode of current insn
9773 and execution state (before entry to decode_insn()),
9774 contains list of to-be-modified registers and
9775 memory blocks (on return from decode_insn()). */
9777 typedef struct insn_decode_record_t
9779 struct gdbarch *gdbarch;
9780 struct regcache *regcache;
9781 CORE_ADDR this_addr; /* Address of the insn being decoded. */
9782 uint32_t arm_insn; /* Should accommodate thumb. */
9783 uint32_t cond; /* Condition code. */
9784 uint32_t opcode; /* Insn opcode. */
9785 uint32_t decode; /* Insn decode bits. */
9786 uint32_t mem_rec_count; /* No of mem records. */
9787 uint32_t reg_rec_count; /* No of reg records. */
9788 uint32_t *arm_regs; /* Registers to be saved for this record. */
9789 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
9790 } insn_decode_record;
9793 /* Checks ARM SBZ and SBO mandatory fields. */
9796 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
9798 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
9817 enum arm_record_result
9819 ARM_RECORD_SUCCESS = 0,
9820 ARM_RECORD_FAILURE = 1
9827 } arm_record_strx_t;
9838 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
9839 uint32_t *record_buf_mem, arm_record_strx_t str_type)
9842 struct regcache *reg_cache = arm_insn_r->regcache;
9843 ULONGEST u_regval[2]= {0};
9845 uint32_t reg_src1 = 0, reg_src2 = 0;
9846 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
9848 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
9849 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
9851 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
9853 /* 1) Handle misc store, immediate offset. */
9854 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9855 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9856 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9857 regcache_raw_read_unsigned (reg_cache, reg_src1,
9859 if (ARM_PC_REGNUM == reg_src1)
9861 /* If R15 was used as Rn, hence current PC+8. */
9862 u_regval[0] = u_regval[0] + 8;
9864 offset_8 = (immed_high << 4) | immed_low;
9865 /* Calculate target store address. */
9866 if (14 == arm_insn_r->opcode)
9868 tgt_mem_addr = u_regval[0] + offset_8;
9872 tgt_mem_addr = u_regval[0] - offset_8;
9874 if (ARM_RECORD_STRH == str_type)
9876 record_buf_mem[0] = 2;
9877 record_buf_mem[1] = tgt_mem_addr;
9878 arm_insn_r->mem_rec_count = 1;
9880 else if (ARM_RECORD_STRD == str_type)
9882 record_buf_mem[0] = 4;
9883 record_buf_mem[1] = tgt_mem_addr;
9884 record_buf_mem[2] = 4;
9885 record_buf_mem[3] = tgt_mem_addr + 4;
9886 arm_insn_r->mem_rec_count = 2;
9889 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
9891 /* 2) Store, register offset. */
9893 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9895 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9896 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9897 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9900 /* If R15 was used as Rn, hence current PC+8. */
9901 u_regval[0] = u_regval[0] + 8;
9903 /* Calculate target store address, Rn +/- Rm, register offset. */
9904 if (12 == arm_insn_r->opcode)
9906 tgt_mem_addr = u_regval[0] + u_regval[1];
9910 tgt_mem_addr = u_regval[1] - u_regval[0];
9912 if (ARM_RECORD_STRH == str_type)
9914 record_buf_mem[0] = 2;
9915 record_buf_mem[1] = tgt_mem_addr;
9916 arm_insn_r->mem_rec_count = 1;
9918 else if (ARM_RECORD_STRD == str_type)
9920 record_buf_mem[0] = 4;
9921 record_buf_mem[1] = tgt_mem_addr;
9922 record_buf_mem[2] = 4;
9923 record_buf_mem[3] = tgt_mem_addr + 4;
9924 arm_insn_r->mem_rec_count = 2;
9927 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
9928 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9930 /* 3) Store, immediate pre-indexed. */
9931 /* 5) Store, immediate post-indexed. */
9932 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9933 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9934 offset_8 = (immed_high << 4) | immed_low;
9935 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9936 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9937 /* Calculate target store address, Rn +/- Rm, register offset. */
9938 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9940 tgt_mem_addr = u_regval[0] + offset_8;
9944 tgt_mem_addr = u_regval[0] - offset_8;
9946 if (ARM_RECORD_STRH == str_type)
9948 record_buf_mem[0] = 2;
9949 record_buf_mem[1] = tgt_mem_addr;
9950 arm_insn_r->mem_rec_count = 1;
9952 else if (ARM_RECORD_STRD == str_type)
9954 record_buf_mem[0] = 4;
9955 record_buf_mem[1] = tgt_mem_addr;
9956 record_buf_mem[2] = 4;
9957 record_buf_mem[3] = tgt_mem_addr + 4;
9958 arm_insn_r->mem_rec_count = 2;
9960 /* Record Rn also as it changes. */
9961 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9962 arm_insn_r->reg_rec_count = 1;
9964 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
9965 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9967 /* 4) Store, register pre-indexed. */
9968 /* 6) Store, register post -indexed. */
9969 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9970 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9971 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9972 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9973 /* Calculate target store address, Rn +/- Rm, register offset. */
9974 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9976 tgt_mem_addr = u_regval[0] + u_regval[1];
9980 tgt_mem_addr = u_regval[1] - u_regval[0];
9982 if (ARM_RECORD_STRH == str_type)
9984 record_buf_mem[0] = 2;
9985 record_buf_mem[1] = tgt_mem_addr;
9986 arm_insn_r->mem_rec_count = 1;
9988 else if (ARM_RECORD_STRD == str_type)
9990 record_buf_mem[0] = 4;
9991 record_buf_mem[1] = tgt_mem_addr;
9992 record_buf_mem[2] = 4;
9993 record_buf_mem[3] = tgt_mem_addr + 4;
9994 arm_insn_r->mem_rec_count = 2;
9996 /* Record Rn also as it changes. */
9997 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9998 arm_insn_r->reg_rec_count = 1;
10003 /* Handling ARM extension space insns. */
10006 arm_record_extension_space (insn_decode_record *arm_insn_r)
10008 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10009 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10010 uint32_t record_buf[8], record_buf_mem[8];
10011 uint32_t reg_src1 = 0;
10012 struct regcache *reg_cache = arm_insn_r->regcache;
10013 ULONGEST u_regval = 0;
10015 gdb_assert (!INSN_RECORDED(arm_insn_r));
10016 /* Handle unconditional insn extension space. */
10018 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10019 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10020 if (arm_insn_r->cond)
10022 /* PLD has no affect on architectural state, it just affects
10024 if (5 == ((opcode1 & 0xE0) >> 5))
10027 record_buf[0] = ARM_PS_REGNUM;
10028 record_buf[1] = ARM_LR_REGNUM;
10029 arm_insn_r->reg_rec_count = 2;
10031 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10035 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10036 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10039 /* Undefined instruction on ARM V5; need to handle if later
10040 versions define it. */
10043 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10044 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10045 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10047 /* Handle arithmetic insn extension space. */
10048 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10049 && !INSN_RECORDED(arm_insn_r))
10051 /* Handle MLA(S) and MUL(S). */
10052 if (0 <= insn_op1 && 3 >= insn_op1)
10054 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10055 record_buf[1] = ARM_PS_REGNUM;
10056 arm_insn_r->reg_rec_count = 2;
10058 else if (4 <= insn_op1 && 15 >= insn_op1)
10060 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10061 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10062 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10063 record_buf[2] = ARM_PS_REGNUM;
10064 arm_insn_r->reg_rec_count = 3;
10068 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10069 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10070 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10072 /* Handle control insn extension space. */
10074 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10075 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10077 if (!bit (arm_insn_r->arm_insn,25))
10079 if (!bits (arm_insn_r->arm_insn, 4, 7))
10081 if ((0 == insn_op1) || (2 == insn_op1))
10084 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10085 arm_insn_r->reg_rec_count = 1;
10087 else if (1 == insn_op1)
10089 /* CSPR is going to be changed. */
10090 record_buf[0] = ARM_PS_REGNUM;
10091 arm_insn_r->reg_rec_count = 1;
10093 else if (3 == insn_op1)
10095 /* SPSR is going to be changed. */
10096 /* We need to get SPSR value, which is yet to be done. */
10100 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10105 record_buf[0] = ARM_PS_REGNUM;
10106 arm_insn_r->reg_rec_count = 1;
10108 else if (3 == insn_op1)
10111 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10112 arm_insn_r->reg_rec_count = 1;
10115 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10118 record_buf[0] = ARM_PS_REGNUM;
10119 record_buf[1] = ARM_LR_REGNUM;
10120 arm_insn_r->reg_rec_count = 2;
10122 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10124 /* QADD, QSUB, QDADD, QDSUB */
10125 record_buf[0] = ARM_PS_REGNUM;
10126 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10127 arm_insn_r->reg_rec_count = 2;
10129 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10132 record_buf[0] = ARM_PS_REGNUM;
10133 record_buf[1] = ARM_LR_REGNUM;
10134 arm_insn_r->reg_rec_count = 2;
10136 /* Save SPSR also;how? */
10139 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
10140 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
10141 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
10142 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
10145 if (0 == insn_op1 || 1 == insn_op1)
10147 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10148 /* We dont do optimization for SMULW<y> where we
10150 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10151 record_buf[1] = ARM_PS_REGNUM;
10152 arm_insn_r->reg_rec_count = 2;
10154 else if (2 == insn_op1)
10157 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10158 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
10159 arm_insn_r->reg_rec_count = 2;
10161 else if (3 == insn_op1)
10164 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10165 arm_insn_r->reg_rec_count = 1;
10171 /* MSR : immediate form. */
10174 /* CSPR is going to be changed. */
10175 record_buf[0] = ARM_PS_REGNUM;
10176 arm_insn_r->reg_rec_count = 1;
10178 else if (3 == insn_op1)
10180 /* SPSR is going to be changed. */
10181 /* we need to get SPSR value, which is yet to be done */
10187 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10188 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
10189 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
10191 /* Handle load/store insn extension space. */
10193 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
10194 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
10195 && !INSN_RECORDED(arm_insn_r))
10200 /* These insn, changes register and memory as well. */
10201 /* SWP or SWPB insn. */
10202 /* Get memory address given by Rn. */
10203 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10204 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
10205 /* SWP insn ?, swaps word. */
10206 if (8 == arm_insn_r->opcode)
10208 record_buf_mem[0] = 4;
10212 /* SWPB insn, swaps only byte. */
10213 record_buf_mem[0] = 1;
10215 record_buf_mem[1] = u_regval;
10216 arm_insn_r->mem_rec_count = 1;
10217 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10218 arm_insn_r->reg_rec_count = 1;
10220 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10223 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10226 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10229 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10230 record_buf[1] = record_buf[0] + 1;
10231 arm_insn_r->reg_rec_count = 2;
10233 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10236 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10239 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
10241 /* LDRH, LDRSB, LDRSH. */
10242 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10243 arm_insn_r->reg_rec_count = 1;
10248 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
10249 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
10250 && !INSN_RECORDED(arm_insn_r))
10253 /* Handle coprocessor insn extension space. */
10256 /* To be done for ARMv5 and later; as of now we return -1. */
10260 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10261 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10266 /* Handling opcode 000 insns. */
10269 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
10271 struct regcache *reg_cache = arm_insn_r->regcache;
10272 uint32_t record_buf[8], record_buf_mem[8];
10273 ULONGEST u_regval[2] = {0};
10275 uint32_t reg_src1 = 0, reg_dest = 0;
10276 uint32_t opcode1 = 0;
10278 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10279 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10280 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10282 /* Data processing insn /multiply insn. */
10283 if (9 == arm_insn_r->decode
10284 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10285 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
10287 /* Handle multiply instructions. */
10288 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10289 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
10291 /* Handle MLA and MUL. */
10292 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10293 record_buf[1] = ARM_PS_REGNUM;
10294 arm_insn_r->reg_rec_count = 2;
10296 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10298 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10299 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10300 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10301 record_buf[2] = ARM_PS_REGNUM;
10302 arm_insn_r->reg_rec_count = 3;
10305 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10306 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
10308 /* Handle misc load insns, as 20th bit (L = 1). */
10309 /* LDR insn has a capability to do branching, if
10310 MOV LR, PC is precceded by LDR insn having Rn as R15
10311 in that case, it emulates branch and link insn, and hence we
10312 need to save CSPR and PC as well. I am not sure this is right
10313 place; as opcode = 010 LDR insn make this happen, if R15 was
10315 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10316 if (15 != reg_dest)
10318 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10319 arm_insn_r->reg_rec_count = 1;
10323 record_buf[0] = reg_dest;
10324 record_buf[1] = ARM_PS_REGNUM;
10325 arm_insn_r->reg_rec_count = 2;
10328 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10329 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
10330 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10331 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
10333 /* Handle MSR insn. */
10334 if (9 == arm_insn_r->opcode)
10336 /* CSPR is going to be changed. */
10337 record_buf[0] = ARM_PS_REGNUM;
10338 arm_insn_r->reg_rec_count = 1;
10342 /* SPSR is going to be changed. */
10343 /* How to read SPSR value? */
10347 else if (9 == arm_insn_r->decode
10348 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10349 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10351 /* Handling SWP, SWPB. */
10352 /* These insn, changes register and memory as well. */
10353 /* SWP or SWPB insn. */
10355 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10356 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10357 /* SWP insn ?, swaps word. */
10358 if (8 == arm_insn_r->opcode)
10360 record_buf_mem[0] = 4;
10364 /* SWPB insn, swaps only byte. */
10365 record_buf_mem[0] = 1;
10367 record_buf_mem[1] = u_regval[0];
10368 arm_insn_r->mem_rec_count = 1;
10369 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10370 arm_insn_r->reg_rec_count = 1;
10372 else if (3 == arm_insn_r->decode && 0x12 == opcode1
10373 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10375 /* Handle BLX, branch and link/exchange. */
10376 if (9 == arm_insn_r->opcode)
10378 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10379 and R14 stores the return address. */
10380 record_buf[0] = ARM_PS_REGNUM;
10381 record_buf[1] = ARM_LR_REGNUM;
10382 arm_insn_r->reg_rec_count = 2;
10385 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
10387 /* Handle enhanced software breakpoint insn, BKPT. */
10388 /* CPSR is changed to be executed in ARM state, disabling normal
10389 interrupts, entering abort mode. */
10390 /* According to high vector configuration PC is set. */
10391 /* user hit breakpoint and type reverse, in
10392 that case, we need to go back with previous CPSR and
10393 Program Counter. */
10394 record_buf[0] = ARM_PS_REGNUM;
10395 record_buf[1] = ARM_LR_REGNUM;
10396 arm_insn_r->reg_rec_count = 2;
10398 /* Save SPSR also; how? */
10401 else if (11 == arm_insn_r->decode
10402 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10404 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10406 /* Handle str(x) insn */
10407 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10410 else if (1 == arm_insn_r->decode && 0x12 == opcode1
10411 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10413 /* Handle BX, branch and link/exchange. */
10414 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10415 record_buf[0] = ARM_PS_REGNUM;
10416 arm_insn_r->reg_rec_count = 1;
10418 else if (1 == arm_insn_r->decode && 0x16 == opcode1
10419 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
10420 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
10422 /* Count leading zeros: CLZ. */
10423 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10424 arm_insn_r->reg_rec_count = 1;
10426 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10427 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10428 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
10429 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
10432 /* Handle MRS insn. */
10433 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10434 arm_insn_r->reg_rec_count = 1;
10436 else if (arm_insn_r->opcode <= 15)
10438 /* Normal data processing insns. */
10439 /* Out of 11 shifter operands mode, all the insn modifies destination
10440 register, which is specified by 13-16 decode. */
10441 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10442 record_buf[1] = ARM_PS_REGNUM;
10443 arm_insn_r->reg_rec_count = 2;
10450 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10451 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10455 /* Handling opcode 001 insns. */
10458 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
10460 uint32_t record_buf[8], record_buf_mem[8];
10462 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10463 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10465 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10466 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
10467 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10470 /* Handle MSR insn. */
10471 if (9 == arm_insn_r->opcode)
10473 /* CSPR is going to be changed. */
10474 record_buf[0] = ARM_PS_REGNUM;
10475 arm_insn_r->reg_rec_count = 1;
10479 /* SPSR is going to be changed. */
10482 else if (arm_insn_r->opcode <= 15)
10484 /* Normal data processing insns. */
10485 /* Out of 11 shifter operands mode, all the insn modifies destination
10486 register, which is specified by 13-16 decode. */
10487 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10488 record_buf[1] = ARM_PS_REGNUM;
10489 arm_insn_r->reg_rec_count = 2;
10496 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10497 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10502 arm_record_media (insn_decode_record *arm_insn_r)
10504 uint32_t record_buf[8];
10506 switch (bits (arm_insn_r->arm_insn, 22, 24))
10509 /* Parallel addition and subtraction, signed */
10511 /* Parallel addition and subtraction, unsigned */
10514 /* Packing, unpacking, saturation and reversal */
10516 int rd = bits (arm_insn_r->arm_insn, 12, 15);
10518 record_buf[arm_insn_r->reg_rec_count++] = rd;
10524 /* Signed multiplies */
10526 int rd = bits (arm_insn_r->arm_insn, 16, 19);
10527 unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22);
10529 record_buf[arm_insn_r->reg_rec_count++] = rd;
10531 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10532 else if (op1 == 0x4)
10533 record_buf[arm_insn_r->reg_rec_count++]
10534 = bits (arm_insn_r->arm_insn, 12, 15);
10540 if (bit (arm_insn_r->arm_insn, 21)
10541 && bits (arm_insn_r->arm_insn, 5, 6) == 0x2)
10544 record_buf[arm_insn_r->reg_rec_count++]
10545 = bits (arm_insn_r->arm_insn, 12, 15);
10547 else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0
10548 && bits (arm_insn_r->arm_insn, 5, 7) == 0x0)
10550 /* USAD8 and USADA8 */
10551 record_buf[arm_insn_r->reg_rec_count++]
10552 = bits (arm_insn_r->arm_insn, 16, 19);
10559 if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3
10560 && bits (arm_insn_r->arm_insn, 5, 7) == 0x7)
10562 /* Permanently UNDEFINED */
10567 /* BFC, BFI and UBFX */
10568 record_buf[arm_insn_r->reg_rec_count++]
10569 = bits (arm_insn_r->arm_insn, 12, 15);
10578 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10583 /* Handle ARM mode instructions with opcode 010. */
10586 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
10588 struct regcache *reg_cache = arm_insn_r->regcache;
10590 uint32_t reg_base , reg_dest;
10591 uint32_t offset_12, tgt_mem_addr;
10592 uint32_t record_buf[8], record_buf_mem[8];
10593 unsigned char wback;
10596 /* Calculate wback. */
10597 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
10598 || (bit (arm_insn_r->arm_insn, 21) == 1);
10600 arm_insn_r->reg_rec_count = 0;
10601 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10603 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10605 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10608 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10609 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
10611 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10612 preceeds a LDR instruction having R15 as reg_base, it
10613 emulates a branch and link instruction, and hence we need to save
10614 CPSR and PC as well. */
10615 if (ARM_PC_REGNUM == reg_dest)
10616 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10618 /* If wback is true, also save the base register, which is going to be
10621 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10625 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10627 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
10628 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10630 /* Handle bit U. */
10631 if (bit (arm_insn_r->arm_insn, 23))
10633 /* U == 1: Add the offset. */
10634 tgt_mem_addr = (uint32_t) u_regval + offset_12;
10638 /* U == 0: subtract the offset. */
10639 tgt_mem_addr = (uint32_t) u_regval - offset_12;
10642 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10644 if (bit (arm_insn_r->arm_insn, 22))
10646 /* STRB and STRBT: 1 byte. */
10647 record_buf_mem[0] = 1;
10651 /* STR and STRT: 4 bytes. */
10652 record_buf_mem[0] = 4;
10655 /* Handle bit P. */
10656 if (bit (arm_insn_r->arm_insn, 24))
10657 record_buf_mem[1] = tgt_mem_addr;
10659 record_buf_mem[1] = (uint32_t) u_regval;
10661 arm_insn_r->mem_rec_count = 1;
10663 /* If wback is true, also save the base register, which is going to be
10666 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10669 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10670 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10674 /* Handling opcode 011 insns. */
10677 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
10679 struct regcache *reg_cache = arm_insn_r->regcache;
10681 uint32_t shift_imm = 0;
10682 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
10683 uint32_t offset_12 = 0, tgt_mem_addr = 0;
10684 uint32_t record_buf[8], record_buf_mem[8];
10687 ULONGEST u_regval[2];
10689 if (bit (arm_insn_r->arm_insn, 4))
10690 return arm_record_media (arm_insn_r);
10692 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10693 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10695 /* Handle enhanced store insns and LDRD DSP insn,
10696 order begins according to addressing modes for store insns
10700 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10702 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10703 /* LDR insn has a capability to do branching, if
10704 MOV LR, PC is precedded by LDR insn having Rn as R15
10705 in that case, it emulates branch and link insn, and hence we
10706 need to save CSPR and PC as well. */
10707 if (15 != reg_dest)
10709 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10710 arm_insn_r->reg_rec_count = 1;
10714 record_buf[0] = reg_dest;
10715 record_buf[1] = ARM_PS_REGNUM;
10716 arm_insn_r->reg_rec_count = 2;
10721 if (! bits (arm_insn_r->arm_insn, 4, 11))
10723 /* Store insn, register offset and register pre-indexed,
10724 register post-indexed. */
10726 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10728 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10729 regcache_raw_read_unsigned (reg_cache, reg_src1
10731 regcache_raw_read_unsigned (reg_cache, reg_src2
10733 if (15 == reg_src2)
10735 /* If R15 was used as Rn, hence current PC+8. */
10736 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10737 u_regval[0] = u_regval[0] + 8;
10739 /* Calculate target store address, Rn +/- Rm, register offset. */
10741 if (bit (arm_insn_r->arm_insn, 23))
10743 tgt_mem_addr = u_regval[0] + u_regval[1];
10747 tgt_mem_addr = u_regval[1] - u_regval[0];
10750 switch (arm_insn_r->opcode)
10764 record_buf_mem[0] = 4;
10779 record_buf_mem[0] = 1;
10783 gdb_assert_not_reached ("no decoding pattern found");
10786 record_buf_mem[1] = tgt_mem_addr;
10787 arm_insn_r->mem_rec_count = 1;
10789 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10790 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10791 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10792 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10793 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10794 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10797 /* Rn is going to be changed in pre-indexed mode and
10798 post-indexed mode as well. */
10799 record_buf[0] = reg_src2;
10800 arm_insn_r->reg_rec_count = 1;
10805 /* Store insn, scaled register offset; scaled pre-indexed. */
10806 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
10808 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10810 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10811 /* Get shift_imm. */
10812 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
10813 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10814 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
10815 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10816 /* Offset_12 used as shift. */
10820 /* Offset_12 used as index. */
10821 offset_12 = u_regval[0] << shift_imm;
10825 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
10831 if (bit (u_regval[0], 31))
10833 offset_12 = 0xFFFFFFFF;
10842 /* This is arithmetic shift. */
10843 offset_12 = s_word >> shift_imm;
10850 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
10852 /* Get C flag value and shift it by 31. */
10853 offset_12 = (((bit (u_regval[1], 29)) << 31) \
10854 | (u_regval[0]) >> 1);
10858 offset_12 = (u_regval[0] >> shift_imm) \
10860 (sizeof(uint32_t) - shift_imm));
10865 gdb_assert_not_reached ("no decoding pattern found");
10869 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10871 if (bit (arm_insn_r->arm_insn, 23))
10873 tgt_mem_addr = u_regval[1] + offset_12;
10877 tgt_mem_addr = u_regval[1] - offset_12;
10880 switch (arm_insn_r->opcode)
10894 record_buf_mem[0] = 4;
10909 record_buf_mem[0] = 1;
10913 gdb_assert_not_reached ("no decoding pattern found");
10916 record_buf_mem[1] = tgt_mem_addr;
10917 arm_insn_r->mem_rec_count = 1;
10919 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10920 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10921 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10922 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10923 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10924 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10927 /* Rn is going to be changed in register scaled pre-indexed
10928 mode,and scaled post indexed mode. */
10929 record_buf[0] = reg_src2;
10930 arm_insn_r->reg_rec_count = 1;
10935 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10936 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10940 /* Handle ARM mode instructions with opcode 100. */
10943 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
10945 struct regcache *reg_cache = arm_insn_r->regcache;
10946 uint32_t register_count = 0, register_bits;
10947 uint32_t reg_base, addr_mode;
10948 uint32_t record_buf[24], record_buf_mem[48];
10952 /* Fetch the list of registers. */
10953 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
10954 arm_insn_r->reg_rec_count = 0;
10956 /* Fetch the base register that contains the address we are loading data
10958 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10960 /* Calculate wback. */
10961 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
10963 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10965 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10967 /* Find out which registers are going to be loaded from memory. */
10968 while (register_bits)
10970 if (register_bits & 0x00000001)
10971 record_buf[arm_insn_r->reg_rec_count++] = register_count;
10972 register_bits = register_bits >> 1;
10977 /* If wback is true, also save the base register, which is going to be
10980 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10982 /* Save the CPSR register. */
10983 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10987 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10989 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
10991 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10993 /* Find out how many registers are going to be stored to memory. */
10994 while (register_bits)
10996 if (register_bits & 0x00000001)
10998 register_bits = register_bits >> 1;
11003 /* STMDA (STMED): Decrement after. */
11005 record_buf_mem[1] = (uint32_t) u_regval
11006 - register_count * INT_REGISTER_SIZE + 4;
11008 /* STM (STMIA, STMEA): Increment after. */
11010 record_buf_mem[1] = (uint32_t) u_regval;
11012 /* STMDB (STMFD): Decrement before. */
11014 record_buf_mem[1] = (uint32_t) u_regval
11015 - register_count * INT_REGISTER_SIZE;
11017 /* STMIB (STMFA): Increment before. */
11019 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
11022 gdb_assert_not_reached ("no decoding pattern found");
11026 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
11027 arm_insn_r->mem_rec_count = 1;
11029 /* If wback is true, also save the base register, which is going to be
11032 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11035 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11036 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11040 /* Handling opcode 101 insns. */
11043 arm_record_b_bl (insn_decode_record *arm_insn_r)
11045 uint32_t record_buf[8];
11047 /* Handle B, BL, BLX(1) insns. */
11048 /* B simply branches so we do nothing here. */
11049 /* Note: BLX(1) doesnt fall here but instead it falls into
11050 extension space. */
11051 if (bit (arm_insn_r->arm_insn, 24))
11053 record_buf[0] = ARM_LR_REGNUM;
11054 arm_insn_r->reg_rec_count = 1;
11057 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11063 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
11065 printf_unfiltered (_("Process record does not support instruction "
11066 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11067 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11072 /* Record handler for vector data transfer instructions. */
11075 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
11077 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
11078 uint32_t record_buf[4];
11080 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
11081 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
11082 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
11083 bit_l = bit (arm_insn_r->arm_insn, 20);
11084 bit_c = bit (arm_insn_r->arm_insn, 8);
11086 /* Handle VMOV instruction. */
11087 if (bit_l && bit_c)
11089 record_buf[0] = reg_t;
11090 arm_insn_r->reg_rec_count = 1;
11092 else if (bit_l && !bit_c)
11094 /* Handle VMOV instruction. */
11095 if (bits_a == 0x00)
11097 record_buf[0] = reg_t;
11098 arm_insn_r->reg_rec_count = 1;
11100 /* Handle VMRS instruction. */
11101 else if (bits_a == 0x07)
11104 reg_t = ARM_PS_REGNUM;
11106 record_buf[0] = reg_t;
11107 arm_insn_r->reg_rec_count = 1;
11110 else if (!bit_l && !bit_c)
11112 /* Handle VMOV instruction. */
11113 if (bits_a == 0x00)
11115 record_buf[0] = ARM_D0_REGNUM + reg_v;
11117 arm_insn_r->reg_rec_count = 1;
11119 /* Handle VMSR instruction. */
11120 else if (bits_a == 0x07)
11122 record_buf[0] = ARM_FPSCR_REGNUM;
11123 arm_insn_r->reg_rec_count = 1;
11126 else if (!bit_l && bit_c)
11128 /* Handle VMOV instruction. */
11129 if (!(bits_a & 0x04))
11131 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
11133 arm_insn_r->reg_rec_count = 1;
11135 /* Handle VDUP instruction. */
11138 if (bit (arm_insn_r->arm_insn, 21))
11140 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
11141 record_buf[0] = reg_v + ARM_D0_REGNUM;
11142 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
11143 arm_insn_r->reg_rec_count = 2;
11147 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
11148 record_buf[0] = reg_v + ARM_D0_REGNUM;
11149 arm_insn_r->reg_rec_count = 1;
11154 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11158 /* Record handler for extension register load/store instructions. */
11161 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
11163 uint32_t opcode, single_reg;
11164 uint8_t op_vldm_vstm;
11165 uint32_t record_buf[8], record_buf_mem[128];
11166 ULONGEST u_regval = 0;
11168 struct regcache *reg_cache = arm_insn_r->regcache;
11170 opcode = bits (arm_insn_r->arm_insn, 20, 24);
11171 single_reg = !bit (arm_insn_r->arm_insn, 8);
11172 op_vldm_vstm = opcode & 0x1b;
11174 /* Handle VMOV instructions. */
11175 if ((opcode & 0x1e) == 0x04)
11177 if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */
11179 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11180 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11181 arm_insn_r->reg_rec_count = 2;
11185 uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3);
11186 uint8_t bit_m = bit (arm_insn_r->arm_insn, 5);
11190 /* The first S register number m is REG_M:M (M is bit 5),
11191 the corresponding D register number is REG_M:M / 2, which
11193 record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m;
11194 /* The second S register number is REG_M:M + 1, the
11195 corresponding D register number is (REG_M:M + 1) / 2.
11196 IOW, if bit M is 1, the first and second S registers
11197 are mapped to different D registers, otherwise, they are
11198 in the same D register. */
11201 record_buf[arm_insn_r->reg_rec_count++]
11202 = ARM_D0_REGNUM + reg_m + 1;
11207 record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM);
11208 arm_insn_r->reg_rec_count = 1;
11212 /* Handle VSTM and VPUSH instructions. */
11213 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
11214 || op_vldm_vstm == 0x12)
11216 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
11217 uint32_t memory_index = 0;
11219 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11220 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11221 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11222 imm_off32 = imm_off8 << 2;
11223 memory_count = imm_off8;
11225 if (bit (arm_insn_r->arm_insn, 23))
11226 start_address = u_regval;
11228 start_address = u_regval - imm_off32;
11230 if (bit (arm_insn_r->arm_insn, 21))
11232 record_buf[0] = reg_rn;
11233 arm_insn_r->reg_rec_count = 1;
11236 while (memory_count > 0)
11240 record_buf_mem[memory_index] = 4;
11241 record_buf_mem[memory_index + 1] = start_address;
11242 start_address = start_address + 4;
11243 memory_index = memory_index + 2;
11247 record_buf_mem[memory_index] = 4;
11248 record_buf_mem[memory_index + 1] = start_address;
11249 record_buf_mem[memory_index + 2] = 4;
11250 record_buf_mem[memory_index + 3] = start_address + 4;
11251 start_address = start_address + 8;
11252 memory_index = memory_index + 4;
11256 arm_insn_r->mem_rec_count = (memory_index >> 1);
11258 /* Handle VLDM instructions. */
11259 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
11260 || op_vldm_vstm == 0x13)
11262 uint32_t reg_count, reg_vd;
11263 uint32_t reg_index = 0;
11264 uint32_t bit_d = bit (arm_insn_r->arm_insn, 22);
11266 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11267 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
11269 /* REG_VD is the first D register number. If the instruction
11270 loads memory to S registers (SINGLE_REG is TRUE), the register
11271 number is (REG_VD << 1 | bit D), so the corresponding D
11272 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11274 reg_vd = reg_vd | (bit_d << 4);
11276 if (bit (arm_insn_r->arm_insn, 21) /* write back */)
11277 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
11279 /* If the instruction loads memory to D register, REG_COUNT should
11280 be divided by 2, according to the ARM Architecture Reference
11281 Manual. If the instruction loads memory to S register, divide by
11282 2 as well because two S registers are mapped to D register. */
11283 reg_count = reg_count / 2;
11284 if (single_reg && bit_d)
11286 /* Increase the register count if S register list starts from
11287 an odd number (bit d is one). */
11291 while (reg_count > 0)
11293 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
11296 arm_insn_r->reg_rec_count = reg_index;
11298 /* VSTR Vector store register. */
11299 else if ((opcode & 0x13) == 0x10)
11301 uint32_t start_address, reg_rn, imm_off32, imm_off8;
11302 uint32_t memory_index = 0;
11304 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11305 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11306 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11307 imm_off32 = imm_off8 << 2;
11309 if (bit (arm_insn_r->arm_insn, 23))
11310 start_address = u_regval + imm_off32;
11312 start_address = u_regval - imm_off32;
11316 record_buf_mem[memory_index] = 4;
11317 record_buf_mem[memory_index + 1] = start_address;
11318 arm_insn_r->mem_rec_count = 1;
11322 record_buf_mem[memory_index] = 4;
11323 record_buf_mem[memory_index + 1] = start_address;
11324 record_buf_mem[memory_index + 2] = 4;
11325 record_buf_mem[memory_index + 3] = start_address + 4;
11326 arm_insn_r->mem_rec_count = 2;
11329 /* VLDR Vector load register. */
11330 else if ((opcode & 0x13) == 0x11)
11332 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11336 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
11337 record_buf[0] = ARM_D0_REGNUM + reg_vd;
11341 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
11342 /* Record register D rather than pseudo register S. */
11343 record_buf[0] = ARM_D0_REGNUM + reg_vd / 2;
11345 arm_insn_r->reg_rec_count = 1;
11348 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11349 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11353 /* Record handler for arm/thumb mode VFP data processing instructions. */
11356 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
11358 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
11359 uint32_t record_buf[4];
11360 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
11361 enum insn_types curr_insn_type = INSN_INV;
11363 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11364 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
11365 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
11366 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
11367 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
11368 bit_d = bit (arm_insn_r->arm_insn, 22);
11369 opc1 = opc1 & 0x04;
11371 /* Handle VMLA, VMLS. */
11374 if (bit (arm_insn_r->arm_insn, 10))
11376 if (bit (arm_insn_r->arm_insn, 6))
11377 curr_insn_type = INSN_T0;
11379 curr_insn_type = INSN_T1;
11384 curr_insn_type = INSN_T1;
11386 curr_insn_type = INSN_T2;
11389 /* Handle VNMLA, VNMLS, VNMUL. */
11390 else if (opc1 == 0x01)
11393 curr_insn_type = INSN_T1;
11395 curr_insn_type = INSN_T2;
11398 else if (opc1 == 0x02 && !(opc3 & 0x01))
11400 if (bit (arm_insn_r->arm_insn, 10))
11402 if (bit (arm_insn_r->arm_insn, 6))
11403 curr_insn_type = INSN_T0;
11405 curr_insn_type = INSN_T1;
11410 curr_insn_type = INSN_T1;
11412 curr_insn_type = INSN_T2;
11415 /* Handle VADD, VSUB. */
11416 else if (opc1 == 0x03)
11418 if (!bit (arm_insn_r->arm_insn, 9))
11420 if (bit (arm_insn_r->arm_insn, 6))
11421 curr_insn_type = INSN_T0;
11423 curr_insn_type = INSN_T1;
11428 curr_insn_type = INSN_T1;
11430 curr_insn_type = INSN_T2;
11434 else if (opc1 == 0x0b)
11437 curr_insn_type = INSN_T1;
11439 curr_insn_type = INSN_T2;
11441 /* Handle all other vfp data processing instructions. */
11442 else if (opc1 == 0x0b)
11445 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
11447 if (bit (arm_insn_r->arm_insn, 4))
11449 if (bit (arm_insn_r->arm_insn, 6))
11450 curr_insn_type = INSN_T0;
11452 curr_insn_type = INSN_T1;
11457 curr_insn_type = INSN_T1;
11459 curr_insn_type = INSN_T2;
11462 /* Handle VNEG and VABS. */
11463 else if ((opc2 == 0x01 && opc3 == 0x01)
11464 || (opc2 == 0x00 && opc3 == 0x03))
11466 if (!bit (arm_insn_r->arm_insn, 11))
11468 if (bit (arm_insn_r->arm_insn, 6))
11469 curr_insn_type = INSN_T0;
11471 curr_insn_type = INSN_T1;
11476 curr_insn_type = INSN_T1;
11478 curr_insn_type = INSN_T2;
11481 /* Handle VSQRT. */
11482 else if (opc2 == 0x01 && opc3 == 0x03)
11485 curr_insn_type = INSN_T1;
11487 curr_insn_type = INSN_T2;
11490 else if (opc2 == 0x07 && opc3 == 0x03)
11493 curr_insn_type = INSN_T1;
11495 curr_insn_type = INSN_T2;
11497 else if (opc3 & 0x01)
11500 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
11502 if (!bit (arm_insn_r->arm_insn, 18))
11503 curr_insn_type = INSN_T2;
11507 curr_insn_type = INSN_T1;
11509 curr_insn_type = INSN_T2;
11513 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
11516 curr_insn_type = INSN_T1;
11518 curr_insn_type = INSN_T2;
11520 /* Handle VCVTB, VCVTT. */
11521 else if ((opc2 & 0x0e) == 0x02)
11522 curr_insn_type = INSN_T2;
11523 /* Handle VCMP, VCMPE. */
11524 else if ((opc2 & 0x0e) == 0x04)
11525 curr_insn_type = INSN_T3;
11529 switch (curr_insn_type)
11532 reg_vd = reg_vd | (bit_d << 4);
11533 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11534 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
11535 arm_insn_r->reg_rec_count = 2;
11539 reg_vd = reg_vd | (bit_d << 4);
11540 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11541 arm_insn_r->reg_rec_count = 1;
11545 reg_vd = (reg_vd << 1) | bit_d;
11546 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11547 arm_insn_r->reg_rec_count = 1;
11551 record_buf[0] = ARM_FPSCR_REGNUM;
11552 arm_insn_r->reg_rec_count = 1;
11556 gdb_assert_not_reached ("no decoding pattern found");
11560 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11564 /* Handling opcode 110 insns. */
11567 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
11569 uint32_t op1, op1_ebit, coproc;
11571 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11572 op1 = bits (arm_insn_r->arm_insn, 20, 25);
11573 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11575 if ((coproc & 0x0e) == 0x0a)
11577 /* Handle extension register ld/st instructions. */
11579 return arm_record_exreg_ld_st_insn (arm_insn_r);
11581 /* 64-bit transfers between arm core and extension registers. */
11582 if ((op1 & 0x3e) == 0x04)
11583 return arm_record_exreg_ld_st_insn (arm_insn_r);
11587 /* Handle coprocessor ld/st instructions. */
11592 return arm_record_unsupported_insn (arm_insn_r);
11595 return arm_record_unsupported_insn (arm_insn_r);
11598 /* Move to coprocessor from two arm core registers. */
11600 return arm_record_unsupported_insn (arm_insn_r);
11602 /* Move to two arm core registers from coprocessor. */
11607 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
11608 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
11609 arm_insn_r->reg_rec_count = 2;
11611 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
11615 return arm_record_unsupported_insn (arm_insn_r);
11618 /* Handling opcode 111 insns. */
11621 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11623 uint32_t op, op1_sbit, op1_ebit, coproc;
11624 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11625 struct regcache *reg_cache = arm_insn_r->regcache;
11627 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11628 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11629 op1_sbit = bit (arm_insn_r->arm_insn, 24);
11630 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11631 op = bit (arm_insn_r->arm_insn, 4);
11633 /* Handle arm SWI/SVC system call instructions. */
11636 if (tdep->arm_syscall_record != NULL)
11638 ULONGEST svc_operand, svc_number;
11640 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
11642 if (svc_operand) /* OABI. */
11643 svc_number = svc_operand - 0x900000;
11645 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
11647 return tdep->arm_syscall_record (reg_cache, svc_number);
11651 printf_unfiltered (_("no syscall record support\n"));
11656 if ((coproc & 0x0e) == 0x0a)
11658 /* VFP data-processing instructions. */
11659 if (!op1_sbit && !op)
11660 return arm_record_vfp_data_proc_insn (arm_insn_r);
11662 /* Advanced SIMD, VFP instructions. */
11663 if (!op1_sbit && op)
11664 return arm_record_vdata_transfer_insn (arm_insn_r);
11668 /* Coprocessor data operations. */
11669 if (!op1_sbit && !op)
11670 return arm_record_unsupported_insn (arm_insn_r);
11672 /* Move to Coprocessor from ARM core register. */
11673 if (!op1_sbit && !op1_ebit && op)
11674 return arm_record_unsupported_insn (arm_insn_r);
11676 /* Move to arm core register from coprocessor. */
11677 if (!op1_sbit && op1_ebit && op)
11679 uint32_t record_buf[1];
11681 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11682 if (record_buf[0] == 15)
11683 record_buf[0] = ARM_PS_REGNUM;
11685 arm_insn_r->reg_rec_count = 1;
11686 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
11692 return arm_record_unsupported_insn (arm_insn_r);
11695 /* Handling opcode 000 insns. */
11698 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11700 uint32_t record_buf[8];
11701 uint32_t reg_src1 = 0;
11703 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11705 record_buf[0] = ARM_PS_REGNUM;
11706 record_buf[1] = reg_src1;
11707 thumb_insn_r->reg_rec_count = 2;
11709 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11715 /* Handling opcode 001 insns. */
11718 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11720 uint32_t record_buf[8];
11721 uint32_t reg_src1 = 0;
11723 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11725 record_buf[0] = ARM_PS_REGNUM;
11726 record_buf[1] = reg_src1;
11727 thumb_insn_r->reg_rec_count = 2;
11729 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11734 /* Handling opcode 010 insns. */
11737 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
11739 struct regcache *reg_cache = thumb_insn_r->regcache;
11740 uint32_t record_buf[8], record_buf_mem[8];
11742 uint32_t reg_src1 = 0, reg_src2 = 0;
11743 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
11745 ULONGEST u_regval[2] = {0};
11747 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
11749 if (bit (thumb_insn_r->arm_insn, 12))
11751 /* Handle load/store register offset. */
11752 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
11753 if (opcode2 >= 12 && opcode2 <= 15)
11755 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11756 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
11757 record_buf[0] = reg_src1;
11758 thumb_insn_r->reg_rec_count = 1;
11760 else if (opcode2 >= 8 && opcode2 <= 10)
11762 /* STR(2), STRB(2), STRH(2) . */
11763 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11764 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
11765 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11766 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11768 record_buf_mem[0] = 4; /* STR (2). */
11769 else if (10 == opcode2)
11770 record_buf_mem[0] = 1; /* STRB (2). */
11771 else if (9 == opcode2)
11772 record_buf_mem[0] = 2; /* STRH (2). */
11773 record_buf_mem[1] = u_regval[0] + u_regval[1];
11774 thumb_insn_r->mem_rec_count = 1;
11777 else if (bit (thumb_insn_r->arm_insn, 11))
11779 /* Handle load from literal pool. */
11781 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11782 record_buf[0] = reg_src1;
11783 thumb_insn_r->reg_rec_count = 1;
11787 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
11788 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
11789 if ((3 == opcode2) && (!opcode3))
11791 /* Branch with exchange. */
11792 record_buf[0] = ARM_PS_REGNUM;
11793 thumb_insn_r->reg_rec_count = 1;
11797 /* Format 8; special data processing insns. */
11798 record_buf[0] = ARM_PS_REGNUM;
11799 record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3
11800 | bits (thumb_insn_r->arm_insn, 0, 2));
11801 thumb_insn_r->reg_rec_count = 2;
11806 /* Format 5; data processing insns. */
11807 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11808 if (bit (thumb_insn_r->arm_insn, 7))
11810 reg_src1 = reg_src1 + 8;
11812 record_buf[0] = ARM_PS_REGNUM;
11813 record_buf[1] = reg_src1;
11814 thumb_insn_r->reg_rec_count = 2;
11817 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11818 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11824 /* Handling opcode 001 insns. */
11827 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
11829 struct regcache *reg_cache = thumb_insn_r->regcache;
11830 uint32_t record_buf[8], record_buf_mem[8];
11832 uint32_t reg_src1 = 0;
11833 uint32_t opcode = 0, immed_5 = 0;
11835 ULONGEST u_regval = 0;
11837 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11842 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11843 record_buf[0] = reg_src1;
11844 thumb_insn_r->reg_rec_count = 1;
11849 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11850 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11851 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11852 record_buf_mem[0] = 4;
11853 record_buf_mem[1] = u_regval + (immed_5 * 4);
11854 thumb_insn_r->mem_rec_count = 1;
11857 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11858 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11864 /* Handling opcode 100 insns. */
11867 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
11869 struct regcache *reg_cache = thumb_insn_r->regcache;
11870 uint32_t record_buf[8], record_buf_mem[8];
11872 uint32_t reg_src1 = 0;
11873 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
11875 ULONGEST u_regval = 0;
11877 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11882 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11883 record_buf[0] = reg_src1;
11884 thumb_insn_r->reg_rec_count = 1;
11886 else if (1 == opcode)
11889 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11890 record_buf[0] = reg_src1;
11891 thumb_insn_r->reg_rec_count = 1;
11893 else if (2 == opcode)
11896 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
11897 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11898 record_buf_mem[0] = 4;
11899 record_buf_mem[1] = u_regval + (immed_8 * 4);
11900 thumb_insn_r->mem_rec_count = 1;
11902 else if (0 == opcode)
11905 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11906 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11907 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11908 record_buf_mem[0] = 2;
11909 record_buf_mem[1] = u_regval + (immed_5 * 2);
11910 thumb_insn_r->mem_rec_count = 1;
11913 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11914 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11920 /* Handling opcode 101 insns. */
11923 thumb_record_misc (insn_decode_record *thumb_insn_r)
11925 struct regcache *reg_cache = thumb_insn_r->regcache;
11927 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
11928 uint32_t register_bits = 0, register_count = 0;
11929 uint32_t index = 0, start_address = 0;
11930 uint32_t record_buf[24], record_buf_mem[48];
11933 ULONGEST u_regval = 0;
11935 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11936 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
11937 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
11942 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11943 while (register_bits)
11945 if (register_bits & 0x00000001)
11946 record_buf[index++] = register_count;
11947 register_bits = register_bits >> 1;
11950 record_buf[index++] = ARM_PS_REGNUM;
11951 record_buf[index++] = ARM_SP_REGNUM;
11952 thumb_insn_r->reg_rec_count = index;
11954 else if (10 == opcode2)
11957 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11958 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11959 while (register_bits)
11961 if (register_bits & 0x00000001)
11963 register_bits = register_bits >> 1;
11965 start_address = u_regval - \
11966 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
11967 thumb_insn_r->mem_rec_count = register_count;
11968 while (register_count)
11970 record_buf_mem[(register_count * 2) - 1] = start_address;
11971 record_buf_mem[(register_count * 2) - 2] = 4;
11972 start_address = start_address + 4;
11975 record_buf[0] = ARM_SP_REGNUM;
11976 thumb_insn_r->reg_rec_count = 1;
11978 else if (0x1E == opcode1)
11981 /* Handle enhanced software breakpoint insn, BKPT. */
11982 /* CPSR is changed to be executed in ARM state, disabling normal
11983 interrupts, entering abort mode. */
11984 /* According to high vector configuration PC is set. */
11985 /* User hits breakpoint and type reverse, in that case, we need to go back with
11986 previous CPSR and Program Counter. */
11987 record_buf[0] = ARM_PS_REGNUM;
11988 record_buf[1] = ARM_LR_REGNUM;
11989 thumb_insn_r->reg_rec_count = 2;
11990 /* We need to save SPSR value, which is not yet done. */
11991 printf_unfiltered (_("Process record does not support instruction "
11992 "0x%0x at address %s.\n"),
11993 thumb_insn_r->arm_insn,
11994 paddress (thumb_insn_r->gdbarch,
11995 thumb_insn_r->this_addr));
11998 else if ((0 == opcode) || (1 == opcode))
12000 /* ADD(5), ADD(6). */
12001 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12002 record_buf[0] = reg_src1;
12003 thumb_insn_r->reg_rec_count = 1;
12005 else if (2 == opcode)
12007 /* ADD(7), SUB(4). */
12008 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12009 record_buf[0] = ARM_SP_REGNUM;
12010 thumb_insn_r->reg_rec_count = 1;
12013 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12014 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12020 /* Handling opcode 110 insns. */
12023 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12025 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12026 struct regcache *reg_cache = thumb_insn_r->regcache;
12028 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12029 uint32_t reg_src1 = 0;
12030 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12031 uint32_t index = 0, start_address = 0;
12032 uint32_t record_buf[24], record_buf_mem[48];
12034 ULONGEST u_regval = 0;
12036 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12037 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12043 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12045 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12046 while (register_bits)
12048 if (register_bits & 0x00000001)
12049 record_buf[index++] = register_count;
12050 register_bits = register_bits >> 1;
12053 record_buf[index++] = reg_src1;
12054 thumb_insn_r->reg_rec_count = index;
12056 else if (0 == opcode2)
12058 /* It handles both STMIA. */
12059 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12061 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12062 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12063 while (register_bits)
12065 if (register_bits & 0x00000001)
12067 register_bits = register_bits >> 1;
12069 start_address = u_regval;
12070 thumb_insn_r->mem_rec_count = register_count;
12071 while (register_count)
12073 record_buf_mem[(register_count * 2) - 1] = start_address;
12074 record_buf_mem[(register_count * 2) - 2] = 4;
12075 start_address = start_address + 4;
12079 else if (0x1F == opcode1)
12081 /* Handle arm syscall insn. */
12082 if (tdep->arm_syscall_record != NULL)
12084 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
12085 ret = tdep->arm_syscall_record (reg_cache, u_regval);
12089 printf_unfiltered (_("no syscall record support\n"));
12094 /* B (1), conditional branch is automatically taken care in process_record,
12095 as PC is saved there. */
12097 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12098 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12104 /* Handling opcode 111 insns. */
12107 thumb_record_branch (insn_decode_record *thumb_insn_r)
12109 uint32_t record_buf[8];
12110 uint32_t bits_h = 0;
12112 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12114 if (2 == bits_h || 3 == bits_h)
12117 record_buf[0] = ARM_LR_REGNUM;
12118 thumb_insn_r->reg_rec_count = 1;
12120 else if (1 == bits_h)
12123 record_buf[0] = ARM_PS_REGNUM;
12124 record_buf[1] = ARM_LR_REGNUM;
12125 thumb_insn_r->reg_rec_count = 2;
12128 /* B(2) is automatically taken care in process_record, as PC is
12131 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12136 /* Handler for thumb2 load/store multiple instructions. */
12139 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
12141 struct regcache *reg_cache = thumb2_insn_r->regcache;
12143 uint32_t reg_rn, op;
12144 uint32_t register_bits = 0, register_count = 0;
12145 uint32_t index = 0, start_address = 0;
12146 uint32_t record_buf[24], record_buf_mem[48];
12148 ULONGEST u_regval = 0;
12150 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12151 op = bits (thumb2_insn_r->arm_insn, 23, 24);
12153 if (0 == op || 3 == op)
12155 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12157 /* Handle RFE instruction. */
12158 record_buf[0] = ARM_PS_REGNUM;
12159 thumb2_insn_r->reg_rec_count = 1;
12163 /* Handle SRS instruction after reading banked SP. */
12164 return arm_record_unsupported_insn (thumb2_insn_r);
12167 else if (1 == op || 2 == op)
12169 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12171 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12172 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12173 while (register_bits)
12175 if (register_bits & 0x00000001)
12176 record_buf[index++] = register_count;
12179 register_bits = register_bits >> 1;
12181 record_buf[index++] = reg_rn;
12182 record_buf[index++] = ARM_PS_REGNUM;
12183 thumb2_insn_r->reg_rec_count = index;
12187 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12188 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12189 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12190 while (register_bits)
12192 if (register_bits & 0x00000001)
12195 register_bits = register_bits >> 1;
12200 /* Start address calculation for LDMDB/LDMEA. */
12201 start_address = u_regval;
12205 /* Start address calculation for LDMDB/LDMEA. */
12206 start_address = u_regval - register_count * 4;
12209 thumb2_insn_r->mem_rec_count = register_count;
12210 while (register_count)
12212 record_buf_mem[register_count * 2 - 1] = start_address;
12213 record_buf_mem[register_count * 2 - 2] = 4;
12214 start_address = start_address + 4;
12217 record_buf[0] = reg_rn;
12218 record_buf[1] = ARM_PS_REGNUM;
12219 thumb2_insn_r->reg_rec_count = 2;
12223 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12225 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12227 return ARM_RECORD_SUCCESS;
12230 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12234 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
12236 struct regcache *reg_cache = thumb2_insn_r->regcache;
12238 uint32_t reg_rd, reg_rn, offset_imm;
12239 uint32_t reg_dest1, reg_dest2;
12240 uint32_t address, offset_addr;
12241 uint32_t record_buf[8], record_buf_mem[8];
12242 uint32_t op1, op2, op3;
12244 ULONGEST u_regval[2];
12246 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
12247 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
12248 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
12250 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12252 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
12254 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
12255 record_buf[0] = reg_dest1;
12256 record_buf[1] = ARM_PS_REGNUM;
12257 thumb2_insn_r->reg_rec_count = 2;
12260 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
12262 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12263 record_buf[2] = reg_dest2;
12264 thumb2_insn_r->reg_rec_count = 3;
12269 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12270 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12272 if (0 == op1 && 0 == op2)
12274 /* Handle STREX. */
12275 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12276 address = u_regval[0] + (offset_imm * 4);
12277 record_buf_mem[0] = 4;
12278 record_buf_mem[1] = address;
12279 thumb2_insn_r->mem_rec_count = 1;
12280 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12281 record_buf[0] = reg_rd;
12282 thumb2_insn_r->reg_rec_count = 1;
12284 else if (1 == op1 && 0 == op2)
12286 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12287 record_buf[0] = reg_rd;
12288 thumb2_insn_r->reg_rec_count = 1;
12289 address = u_regval[0];
12290 record_buf_mem[1] = address;
12294 /* Handle STREXB. */
12295 record_buf_mem[0] = 1;
12296 thumb2_insn_r->mem_rec_count = 1;
12300 /* Handle STREXH. */
12301 record_buf_mem[0] = 2 ;
12302 thumb2_insn_r->mem_rec_count = 1;
12306 /* Handle STREXD. */
12307 address = u_regval[0];
12308 record_buf_mem[0] = 4;
12309 record_buf_mem[2] = 4;
12310 record_buf_mem[3] = address + 4;
12311 thumb2_insn_r->mem_rec_count = 2;
12316 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12318 if (bit (thumb2_insn_r->arm_insn, 24))
12320 if (bit (thumb2_insn_r->arm_insn, 23))
12321 offset_addr = u_regval[0] + (offset_imm * 4);
12323 offset_addr = u_regval[0] - (offset_imm * 4);
12325 address = offset_addr;
12328 address = u_regval[0];
12330 record_buf_mem[0] = 4;
12331 record_buf_mem[1] = address;
12332 record_buf_mem[2] = 4;
12333 record_buf_mem[3] = address + 4;
12334 thumb2_insn_r->mem_rec_count = 2;
12335 record_buf[0] = reg_rn;
12336 thumb2_insn_r->reg_rec_count = 1;
12340 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12342 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12344 return ARM_RECORD_SUCCESS;
12347 /* Handler for thumb2 data processing (shift register and modified immediate)
12351 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
12353 uint32_t reg_rd, op;
12354 uint32_t record_buf[8];
12356 op = bits (thumb2_insn_r->arm_insn, 21, 24);
12357 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12359 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
12361 record_buf[0] = ARM_PS_REGNUM;
12362 thumb2_insn_r->reg_rec_count = 1;
12366 record_buf[0] = reg_rd;
12367 record_buf[1] = ARM_PS_REGNUM;
12368 thumb2_insn_r->reg_rec_count = 2;
12371 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12373 return ARM_RECORD_SUCCESS;
12376 /* Generic handler for thumb2 instructions which effect destination and PS
12380 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
12383 uint32_t record_buf[8];
12385 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12387 record_buf[0] = reg_rd;
12388 record_buf[1] = ARM_PS_REGNUM;
12389 thumb2_insn_r->reg_rec_count = 2;
12391 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12393 return ARM_RECORD_SUCCESS;
12396 /* Handler for thumb2 branch and miscellaneous control instructions. */
12399 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
12401 uint32_t op, op1, op2;
12402 uint32_t record_buf[8];
12404 op = bits (thumb2_insn_r->arm_insn, 20, 26);
12405 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
12406 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12408 /* Handle MSR insn. */
12409 if (!(op1 & 0x2) && 0x38 == op)
12413 /* CPSR is going to be changed. */
12414 record_buf[0] = ARM_PS_REGNUM;
12415 thumb2_insn_r->reg_rec_count = 1;
12419 arm_record_unsupported_insn(thumb2_insn_r);
12423 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
12426 record_buf[0] = ARM_PS_REGNUM;
12427 record_buf[1] = ARM_LR_REGNUM;
12428 thumb2_insn_r->reg_rec_count = 2;
12431 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12433 return ARM_RECORD_SUCCESS;
12436 /* Handler for thumb2 store single data item instructions. */
12439 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
12441 struct regcache *reg_cache = thumb2_insn_r->regcache;
12443 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
12444 uint32_t address, offset_addr;
12445 uint32_t record_buf[8], record_buf_mem[8];
12448 ULONGEST u_regval[2];
12450 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
12451 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
12452 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12453 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12455 if (bit (thumb2_insn_r->arm_insn, 23))
12458 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
12459 offset_addr = u_regval[0] + offset_imm;
12460 address = offset_addr;
12465 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
12467 /* Handle STRB (register). */
12468 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
12469 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
12470 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
12471 offset_addr = u_regval[1] << shift_imm;
12472 address = u_regval[0] + offset_addr;
12476 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12477 if (bit (thumb2_insn_r->arm_insn, 10))
12479 if (bit (thumb2_insn_r->arm_insn, 9))
12480 offset_addr = u_regval[0] + offset_imm;
12482 offset_addr = u_regval[0] - offset_imm;
12484 address = offset_addr;
12487 address = u_regval[0];
12493 /* Store byte instructions. */
12496 record_buf_mem[0] = 1;
12498 /* Store half word instructions. */
12501 record_buf_mem[0] = 2;
12503 /* Store word instructions. */
12506 record_buf_mem[0] = 4;
12510 gdb_assert_not_reached ("no decoding pattern found");
12514 record_buf_mem[1] = address;
12515 thumb2_insn_r->mem_rec_count = 1;
12516 record_buf[0] = reg_rn;
12517 thumb2_insn_r->reg_rec_count = 1;
12519 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12521 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12523 return ARM_RECORD_SUCCESS;
12526 /* Handler for thumb2 load memory hints instructions. */
12529 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
12531 uint32_t record_buf[8];
12532 uint32_t reg_rt, reg_rn;
12534 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
12535 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12537 if (ARM_PC_REGNUM != reg_rt)
12539 record_buf[0] = reg_rt;
12540 record_buf[1] = reg_rn;
12541 record_buf[2] = ARM_PS_REGNUM;
12542 thumb2_insn_r->reg_rec_count = 3;
12544 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12546 return ARM_RECORD_SUCCESS;
12549 return ARM_RECORD_FAILURE;
12552 /* Handler for thumb2 load word instructions. */
12555 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
12557 uint32_t record_buf[8];
12559 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
12560 record_buf[1] = ARM_PS_REGNUM;
12561 thumb2_insn_r->reg_rec_count = 2;
12563 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12565 return ARM_RECORD_SUCCESS;
12568 /* Handler for thumb2 long multiply, long multiply accumulate, and
12569 divide instructions. */
12572 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
12574 uint32_t opcode1 = 0, opcode2 = 0;
12575 uint32_t record_buf[8];
12577 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
12578 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
12580 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
12582 /* Handle SMULL, UMULL, SMULAL. */
12583 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12584 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12585 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12586 record_buf[2] = ARM_PS_REGNUM;
12587 thumb2_insn_r->reg_rec_count = 3;
12589 else if (1 == opcode1 || 3 == opcode2)
12591 /* Handle SDIV and UDIV. */
12592 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12593 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12594 record_buf[2] = ARM_PS_REGNUM;
12595 thumb2_insn_r->reg_rec_count = 3;
12598 return ARM_RECORD_FAILURE;
12600 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12602 return ARM_RECORD_SUCCESS;
12605 /* Record handler for thumb32 coprocessor instructions. */
12608 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
12610 if (bit (thumb2_insn_r->arm_insn, 25))
12611 return arm_record_coproc_data_proc (thumb2_insn_r);
12613 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
12616 /* Record handler for advance SIMD structure load/store instructions. */
12619 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
12621 struct regcache *reg_cache = thumb2_insn_r->regcache;
12622 uint32_t l_bit, a_bit, b_bits;
12623 uint32_t record_buf[128], record_buf_mem[128];
12624 uint32_t reg_rn, reg_vd, address, f_elem;
12625 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
12628 l_bit = bit (thumb2_insn_r->arm_insn, 21);
12629 a_bit = bit (thumb2_insn_r->arm_insn, 23);
12630 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
12631 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12632 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
12633 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
12634 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
12635 f_elem = 8 / f_ebytes;
12639 ULONGEST u_regval = 0;
12640 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12641 address = u_regval;
12646 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12648 if (b_bits == 0x07)
12650 else if (b_bits == 0x0a)
12652 else if (b_bits == 0x06)
12654 else if (b_bits == 0x02)
12659 for (index_r = 0; index_r < bf_regs; index_r++)
12661 for (index_e = 0; index_e < f_elem; index_e++)
12663 record_buf_mem[index_m++] = f_ebytes;
12664 record_buf_mem[index_m++] = address;
12665 address = address + f_ebytes;
12666 thumb2_insn_r->mem_rec_count += 1;
12671 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12673 if (b_bits == 0x09 || b_bits == 0x08)
12675 else if (b_bits == 0x03)
12680 for (index_r = 0; index_r < bf_regs; index_r++)
12681 for (index_e = 0; index_e < f_elem; index_e++)
12683 for (loop_t = 0; loop_t < 2; loop_t++)
12685 record_buf_mem[index_m++] = f_ebytes;
12686 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12687 thumb2_insn_r->mem_rec_count += 1;
12689 address = address + (2 * f_ebytes);
12693 else if ((b_bits & 0x0e) == 0x04)
12695 for (index_e = 0; index_e < f_elem; index_e++)
12697 for (loop_t = 0; loop_t < 3; loop_t++)
12699 record_buf_mem[index_m++] = f_ebytes;
12700 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12701 thumb2_insn_r->mem_rec_count += 1;
12703 address = address + (3 * f_ebytes);
12707 else if (!(b_bits & 0x0e))
12709 for (index_e = 0; index_e < f_elem; index_e++)
12711 for (loop_t = 0; loop_t < 4; loop_t++)
12713 record_buf_mem[index_m++] = f_ebytes;
12714 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12715 thumb2_insn_r->mem_rec_count += 1;
12717 address = address + (4 * f_ebytes);
12723 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
12725 if (bft_size == 0x00)
12727 else if (bft_size == 0x01)
12729 else if (bft_size == 0x02)
12735 if (!(b_bits & 0x0b) || b_bits == 0x08)
12736 thumb2_insn_r->mem_rec_count = 1;
12738 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
12739 thumb2_insn_r->mem_rec_count = 2;
12741 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
12742 thumb2_insn_r->mem_rec_count = 3;
12744 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
12745 thumb2_insn_r->mem_rec_count = 4;
12747 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
12749 record_buf_mem[index_m] = f_ebytes;
12750 record_buf_mem[index_m] = address + (index_m * f_ebytes);
12759 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12760 thumb2_insn_r->reg_rec_count = 1;
12762 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12763 thumb2_insn_r->reg_rec_count = 2;
12765 else if ((b_bits & 0x0e) == 0x04)
12766 thumb2_insn_r->reg_rec_count = 3;
12768 else if (!(b_bits & 0x0e))
12769 thumb2_insn_r->reg_rec_count = 4;
12774 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
12775 thumb2_insn_r->reg_rec_count = 1;
12777 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
12778 thumb2_insn_r->reg_rec_count = 2;
12780 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
12781 thumb2_insn_r->reg_rec_count = 3;
12783 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
12784 thumb2_insn_r->reg_rec_count = 4;
12786 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
12787 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
12791 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
12793 record_buf[index_r] = reg_rn;
12794 thumb2_insn_r->reg_rec_count += 1;
12797 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12799 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12804 /* Decodes thumb2 instruction type and invokes its record handler. */
12806 static unsigned int
12807 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
12809 uint32_t op, op1, op2;
12811 op = bit (thumb2_insn_r->arm_insn, 15);
12812 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
12813 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
12817 if (!(op2 & 0x64 ))
12819 /* Load/store multiple instruction. */
12820 return thumb2_record_ld_st_multiple (thumb2_insn_r);
12822 else if (!((op2 & 0x64) ^ 0x04))
12824 /* Load/store (dual/exclusive) and table branch instruction. */
12825 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
12827 else if (!((op2 & 0x20) ^ 0x20))
12829 /* Data-processing (shifted register). */
12830 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12832 else if (op2 & 0x40)
12834 /* Co-processor instructions. */
12835 return thumb2_record_coproc_insn (thumb2_insn_r);
12838 else if (op1 == 0x02)
12842 /* Branches and miscellaneous control instructions. */
12843 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
12845 else if (op2 & 0x20)
12847 /* Data-processing (plain binary immediate) instruction. */
12848 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12852 /* Data-processing (modified immediate). */
12853 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12856 else if (op1 == 0x03)
12858 if (!(op2 & 0x71 ))
12860 /* Store single data item. */
12861 return thumb2_record_str_single_data (thumb2_insn_r);
12863 else if (!((op2 & 0x71) ^ 0x10))
12865 /* Advanced SIMD or structure load/store instructions. */
12866 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
12868 else if (!((op2 & 0x67) ^ 0x01))
12870 /* Load byte, memory hints instruction. */
12871 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12873 else if (!((op2 & 0x67) ^ 0x03))
12875 /* Load halfword, memory hints instruction. */
12876 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12878 else if (!((op2 & 0x67) ^ 0x05))
12880 /* Load word instruction. */
12881 return thumb2_record_ld_word (thumb2_insn_r);
12883 else if (!((op2 & 0x70) ^ 0x20))
12885 /* Data-processing (register) instruction. */
12886 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12888 else if (!((op2 & 0x78) ^ 0x30))
12890 /* Multiply, multiply accumulate, abs diff instruction. */
12891 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12893 else if (!((op2 & 0x78) ^ 0x38))
12895 /* Long multiply, long multiply accumulate, and divide. */
12896 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
12898 else if (op2 & 0x40)
12900 /* Co-processor instructions. */
12901 return thumb2_record_coproc_insn (thumb2_insn_r);
12908 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12909 and positive val on fauilure. */
12912 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12914 gdb_byte buf[insn_size];
12916 memset (&buf[0], 0, insn_size);
12918 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12920 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12922 gdbarch_byte_order_for_code (insn_record->gdbarch));
12926 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12928 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12932 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12933 uint32_t insn_size)
12936 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12938 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
12940 arm_record_data_proc_misc_ld_str, /* 000. */
12941 arm_record_data_proc_imm, /* 001. */
12942 arm_record_ld_st_imm_offset, /* 010. */
12943 arm_record_ld_st_reg_offset, /* 011. */
12944 arm_record_ld_st_multiple, /* 100. */
12945 arm_record_b_bl, /* 101. */
12946 arm_record_asimd_vfp_coproc, /* 110. */
12947 arm_record_coproc_data_proc /* 111. */
12950 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12952 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
12954 thumb_record_shift_add_sub, /* 000. */
12955 thumb_record_add_sub_cmp_mov, /* 001. */
12956 thumb_record_ld_st_reg_offset, /* 010. */
12957 thumb_record_ld_st_imm_offset, /* 011. */
12958 thumb_record_ld_st_stack, /* 100. */
12959 thumb_record_misc, /* 101. */
12960 thumb_record_ldm_stm_swi, /* 110. */
12961 thumb_record_branch /* 111. */
12964 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12965 uint32_t insn_id = 0;
12967 if (extract_arm_insn (arm_record, insn_size))
12971 printf_unfiltered (_("Process record: error reading memory at "
12972 "addr %s len = %d.\n"),
12973 paddress (arm_record->gdbarch,
12974 arm_record->this_addr), insn_size);
12978 else if (ARM_RECORD == record_type)
12980 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12981 insn_id = bits (arm_record->arm_insn, 25, 27);
12983 if (arm_record->cond == 0xf)
12984 ret = arm_record_extension_space (arm_record);
12987 /* If this insn has fallen into extension space
12988 then we need not decode it anymore. */
12989 ret = arm_handle_insn[insn_id] (arm_record);
12991 if (ret != ARM_RECORD_SUCCESS)
12993 arm_record_unsupported_insn (arm_record);
12997 else if (THUMB_RECORD == record_type)
12999 /* As thumb does not have condition codes, we set negative. */
13000 arm_record->cond = -1;
13001 insn_id = bits (arm_record->arm_insn, 13, 15);
13002 ret = thumb_handle_insn[insn_id] (arm_record);
13003 if (ret != ARM_RECORD_SUCCESS)
13005 arm_record_unsupported_insn (arm_record);
13009 else if (THUMB2_RECORD == record_type)
13011 /* As thumb does not have condition codes, we set negative. */
13012 arm_record->cond = -1;
13014 /* Swap first half of 32bit thumb instruction with second half. */
13015 arm_record->arm_insn
13016 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
13018 ret = thumb2_record_decode_insn_handler (arm_record);
13020 if (ret != ARM_RECORD_SUCCESS)
13022 arm_record_unsupported_insn (arm_record);
13028 /* Throw assertion. */
13029 gdb_assert_not_reached ("not a valid instruction, could not decode");
13036 /* Cleans up local record registers and memory allocations. */
13039 deallocate_reg_mem (insn_decode_record *record)
13041 xfree (record->arm_regs);
13042 xfree (record->arm_mems);
13046 /* Parse the current instruction and record the values of the registers and
13047 memory that will be changed in current instruction to record_arch_list".
13048 Return -1 if something is wrong. */
13051 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
13052 CORE_ADDR insn_addr)
13055 uint32_t no_of_rec = 0;
13056 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
13057 ULONGEST t_bit = 0, insn_id = 0;
13059 ULONGEST u_regval = 0;
13061 insn_decode_record arm_record;
13063 memset (&arm_record, 0, sizeof (insn_decode_record));
13064 arm_record.regcache = regcache;
13065 arm_record.this_addr = insn_addr;
13066 arm_record.gdbarch = gdbarch;
13069 if (record_debug > 1)
13071 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
13073 paddress (gdbarch, arm_record.this_addr));
13076 if (extract_arm_insn (&arm_record, 2))
13080 printf_unfiltered (_("Process record: error reading memory at "
13081 "addr %s len = %d.\n"),
13082 paddress (arm_record.gdbarch,
13083 arm_record.this_addr), 2);
13088 /* Check the insn, whether it is thumb or arm one. */
13090 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
13091 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
13094 if (!(u_regval & t_bit))
13096 /* We are decoding arm insn. */
13097 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
13101 insn_id = bits (arm_record.arm_insn, 11, 15);
13102 /* is it thumb2 insn? */
13103 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13105 ret = decode_insn (&arm_record, THUMB2_RECORD,
13106 THUMB2_INSN_SIZE_BYTES);
13110 /* We are decoding thumb insn. */
13111 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
13117 /* Record registers. */
13118 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
13119 if (arm_record.arm_regs)
13121 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
13123 if (record_full_arch_list_add_reg
13124 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
13128 /* Record memories. */
13129 if (arm_record.arm_mems)
13131 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
13133 if (record_full_arch_list_add_mem
13134 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
13135 arm_record.arm_mems[no_of_rec].len))
13140 if (record_full_arch_list_add_end ())
13145 deallocate_reg_mem (&arm_record);