1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-1989, 1991-1993, 1995-1996, 1998-2012 Free
4 Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include <ctype.h> /* XXX for isupper (). */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data *arm_objfile_data_key;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
92 DEF_VEC_O(arm_mapping_symbol_s);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s) **section_maps;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element *setarmcmdlist = NULL;
101 static struct cmd_list_element *showarmcmdlist = NULL;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
117 static const char *current_fp_model = "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
130 static const char *arm_abi_string = "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings[] =
141 static const char *arm_fallback_mode_string = "auto";
142 static const char *arm_force_mode_string = "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode = -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element *);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat *, const void *,
228 static void convert_to_extended (const struct floatformat *, void *,
231 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
232 struct regcache *regcache,
233 int regnum, gdb_byte *buf);
234 static void arm_neon_quad_write (struct gdbarch *gdbarch,
235 struct regcache *regcache,
236 int regnum, const gdb_byte *buf);
238 static int thumb_insn_size (unsigned short inst1);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg *saved_regs;
260 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
261 CORE_ADDR prologue_start,
262 CORE_ADDR prologue_end,
263 struct arm_prologue_cache *cache);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch *gdbarch)
285 if (gdbarch_tdep (gdbarch)->is_m)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info *frame)
297 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
305 return (cpsr & t_bit) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
312 const struct arm_mapping_symbol *rhs)
314 return lhs->value < rhs->value;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
324 struct obj_section *sec;
326 /* If there are mapping symbols, consult them. */
327 sec = find_pc_section (memaddr);
330 struct arm_per_objfile *data;
331 VEC(arm_mapping_symbol_s) *map;
332 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
336 data = objfile_data (sec->objfile, arm_objfile_data_key);
339 map = data->section_maps[sec->the_bfd_section->index];
340 if (!VEC_empty (arm_mapping_symbol_s, map))
342 struct arm_mapping_symbol *map_sym;
344 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
345 arm_compare_mapping_symbols);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx < VEC_length (arm_mapping_symbol_s, map))
353 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
354 if (map_sym->value == map_key.value)
357 *start = map_sym->value + obj_section_addr (sec);
358 return map_sym->type;
364 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
366 *start = map_sym->value + obj_section_addr (sec);
367 return map_sym->type;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
383 struct minimal_symbol *sym;
385 struct displaced_step_closure* dsc
386 = get_displaced_step_closure_by_addr(memaddr);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc->insn_addr,
396 (unsigned long) memaddr);
397 memaddr = dsc->insn_addr;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode != -1)
406 return arm_override_mode;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string, "arm") == 0)
411 if (strcmp (arm_force_mode_string, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch)->is_m)
418 /* If there are mapping symbols, consult them. */
419 type = arm_find_mapping_symbol (memaddr, NULL);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym = lookup_minimal_symbol_by_pc (memaddr);
426 return (MSYMBOL_IS_SPECIAL (sym));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
451 return UNMAKE_THUMB_ADDR (val);
453 return (val & 0x03fffffc);
456 /* When reading symbols, we need to zap the low bit of the address,
457 which may be set to 1 for Thumb functions. */
459 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
464 /* Return 1 if PC is the start of a compiler helper function which
465 can be safely ignored during prologue skipping. IS_THUMB is true
466 if the function is known to be a Thumb function due to the way it
469 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
471 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
472 struct minimal_symbol *msym;
474 msym = lookup_minimal_symbol_by_pc (pc);
476 && SYMBOL_VALUE_ADDRESS (msym) == pc
477 && SYMBOL_LINKAGE_NAME (msym) != NULL)
479 const char *name = SYMBOL_LINKAGE_NAME (msym);
481 /* The GNU linker's Thumb call stub to foo is named
483 if (strstr (name, "_from_thumb") != NULL)
486 /* On soft-float targets, __truncdfsf2 is called to convert promoted
487 arguments to their argument types in non-prototyped
489 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
491 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
494 /* Internal functions related to thread-local storage. */
495 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
497 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
502 /* If we run against a stripped glibc, we may be unable to identify
503 special functions by name. Check for one important case,
504 __aeabi_read_tp, by comparing the *code* against the default
505 implementation (this is hand-written ARM assembler in glibc). */
508 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
509 == 0xe3e00a0f /* mov r0, #0xffff0fff */
510 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
511 == 0xe240f01f) /* sub pc, r0, #31 */
518 /* Support routines for instruction parsing. */
519 #define submask(x) ((1L << ((x) + 1)) - 1)
520 #define bit(obj,st) (((obj) >> (st)) & 1)
521 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
522 #define sbits(obj,st,fn) \
523 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
524 #define BranchDest(addr,instr) \
525 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
527 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
528 the first 16-bit of instruction, and INSN2 is the second 16-bit of
530 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
531 ((bits ((insn1), 0, 3) << 12) \
532 | (bits ((insn1), 10, 10) << 11) \
533 | (bits ((insn2), 12, 14) << 8) \
534 | bits ((insn2), 0, 7))
536 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
537 the 32-bit instruction. */
538 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
539 ((bits ((insn), 16, 19) << 12) \
540 | bits ((insn), 0, 11))
542 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
545 thumb_expand_immediate (unsigned int imm)
547 unsigned int count = imm >> 7;
555 return (imm & 0xff) | ((imm & 0xff) << 16);
557 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
559 return (imm & 0xff) | ((imm & 0xff) << 8)
560 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
563 return (0x80 | (imm & 0x7f)) << (32 - count);
566 /* Return 1 if the 16-bit Thumb instruction INST might change
567 control flow, 0 otherwise. */
570 thumb_instruction_changes_pc (unsigned short inst)
572 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
575 if ((inst & 0xf000) == 0xd000) /* conditional branch */
578 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
581 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
584 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
587 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
593 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
594 might change control flow, 0 otherwise. */
597 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
599 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
601 /* Branches and miscellaneous control instructions. */
603 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
608 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
610 /* SUBS PC, LR, #imm8. */
613 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
615 /* Conditional branch. */
622 if ((inst1 & 0xfe50) == 0xe810)
624 /* Load multiple or RFE. */
626 if (bit (inst1, 7) && !bit (inst1, 8))
632 else if (!bit (inst1, 7) && bit (inst1, 8))
638 else if (bit (inst1, 7) && bit (inst1, 8))
643 else if (!bit (inst1, 7) && !bit (inst1, 8))
652 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
654 /* MOV PC or MOVS PC. */
658 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
661 if (bits (inst1, 0, 3) == 15)
667 if ((inst2 & 0x0fc0) == 0x0000)
673 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
679 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
688 /* Analyze a Thumb prologue, looking for a recognizable stack frame
689 and frame pointer. Scan until we encounter a store that could
690 clobber the stack frame unexpectedly, or an unknown instruction.
691 Return the last address which is definitely safe to skip for an
692 initial breakpoint. */
695 thumb_analyze_prologue (struct gdbarch *gdbarch,
696 CORE_ADDR start, CORE_ADDR limit,
697 struct arm_prologue_cache *cache)
699 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
700 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
703 struct pv_area *stack;
704 struct cleanup *back_to;
706 CORE_ADDR unrecognized_pc = 0;
708 for (i = 0; i < 16; i++)
709 regs[i] = pv_register (i, 0);
710 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
711 back_to = make_cleanup_free_pv_area (stack);
713 while (start < limit)
717 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
719 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
724 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
727 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
728 whether to save LR (R14). */
729 mask = (insn & 0xff) | ((insn & 0x100) << 6);
731 /* Calculate offsets of saved R0-R7 and LR. */
732 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
733 if (mask & (1 << regno))
735 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
737 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
740 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
743 offset = (insn & 0x7f) << 2; /* get scaled offset */
744 if (insn & 0x80) /* Check for SUB. */
745 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
748 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
751 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
752 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
754 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
755 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
756 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
758 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
759 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
760 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
762 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
763 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
764 && pv_is_constant (regs[bits (insn, 3, 5)]))
765 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
766 regs[bits (insn, 6, 8)]);
767 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
768 && pv_is_constant (regs[bits (insn, 3, 6)]))
770 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
771 int rm = bits (insn, 3, 6);
772 regs[rd] = pv_add (regs[rd], regs[rm]);
774 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
776 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
777 int src_reg = (insn & 0x78) >> 3;
778 regs[dst_reg] = regs[src_reg];
780 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
782 /* Handle stores to the stack. Normally pushes are used,
783 but with GCC -mtpcs-frame, there may be other stores
784 in the prologue to create the frame. */
785 int regno = (insn >> 8) & 0x7;
788 offset = (insn & 0xff) << 2;
789 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
791 if (pv_area_store_would_trash (stack, addr))
794 pv_area_store (stack, addr, 4, regs[regno]);
796 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
798 int rd = bits (insn, 0, 2);
799 int rn = bits (insn, 3, 5);
802 offset = bits (insn, 6, 10) << 2;
803 addr = pv_add_constant (regs[rn], offset);
805 if (pv_area_store_would_trash (stack, addr))
808 pv_area_store (stack, addr, 4, regs[rd]);
810 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
811 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
812 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
813 /* Ignore stores of argument registers to the stack. */
815 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
816 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
817 /* Ignore block loads from the stack, potentially copying
818 parameters from memory. */
820 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
821 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
822 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
823 /* Similarly ignore single loads from the stack. */
825 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
826 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
827 /* Skip register copies, i.e. saves to another register
828 instead of the stack. */
830 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
831 /* Recognize constant loads; even with small stacks these are necessary
833 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
834 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
836 /* Constant pool loads, for the same reason. */
837 unsigned int constant;
840 loc = start + 4 + bits (insn, 0, 7) * 4;
841 constant = read_memory_unsigned_integer (loc, 4, byte_order);
842 regs[bits (insn, 8, 10)] = pv_constant (constant);
844 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
846 unsigned short inst2;
848 inst2 = read_memory_unsigned_integer (start + 2, 2,
849 byte_order_for_code);
851 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
853 /* BL, BLX. Allow some special function calls when
854 skipping the prologue; GCC generates these before
855 storing arguments to the stack. */
857 int j1, j2, imm1, imm2;
859 imm1 = sbits (insn, 0, 10);
860 imm2 = bits (inst2, 0, 10);
861 j1 = bit (inst2, 13);
862 j2 = bit (inst2, 11);
864 offset = ((imm1 << 12) + (imm2 << 1));
865 offset ^= ((!j2) << 22) | ((!j1) << 23);
867 nextpc = start + 4 + offset;
868 /* For BLX make sure to clear the low bits. */
869 if (bit (inst2, 12) == 0)
870 nextpc = nextpc & 0xfffffffc;
872 if (!skip_prologue_function (gdbarch, nextpc,
873 bit (inst2, 12) != 0))
877 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
879 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
881 pv_t addr = regs[bits (insn, 0, 3)];
884 if (pv_area_store_would_trash (stack, addr))
887 /* Calculate offsets of saved registers. */
888 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
889 if (inst2 & (1 << regno))
891 addr = pv_add_constant (addr, -4);
892 pv_area_store (stack, addr, 4, regs[regno]);
896 regs[bits (insn, 0, 3)] = addr;
899 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
901 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
903 int regno1 = bits (inst2, 12, 15);
904 int regno2 = bits (inst2, 8, 11);
905 pv_t addr = regs[bits (insn, 0, 3)];
907 offset = inst2 & 0xff;
909 addr = pv_add_constant (addr, offset);
911 addr = pv_add_constant (addr, -offset);
913 if (pv_area_store_would_trash (stack, addr))
916 pv_area_store (stack, addr, 4, regs[regno1]);
917 pv_area_store (stack, pv_add_constant (addr, 4),
921 regs[bits (insn, 0, 3)] = addr;
924 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
925 && (inst2 & 0x0c00) == 0x0c00
926 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
928 int regno = bits (inst2, 12, 15);
929 pv_t addr = regs[bits (insn, 0, 3)];
931 offset = inst2 & 0xff;
933 addr = pv_add_constant (addr, offset);
935 addr = pv_add_constant (addr, -offset);
937 if (pv_area_store_would_trash (stack, addr))
940 pv_area_store (stack, addr, 4, regs[regno]);
943 regs[bits (insn, 0, 3)] = addr;
946 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
947 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
949 int regno = bits (inst2, 12, 15);
952 offset = inst2 & 0xfff;
953 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
955 if (pv_area_store_would_trash (stack, addr))
958 pv_area_store (stack, addr, 4, regs[regno]);
961 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
962 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
963 /* Ignore stores of argument registers to the stack. */
966 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
967 && (inst2 & 0x0d00) == 0x0c00
968 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
969 /* Ignore stores of argument registers to the stack. */
972 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
974 && (inst2 & 0x8000) == 0x0000
975 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
976 /* Ignore block loads from the stack, potentially copying
977 parameters from memory. */
980 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
982 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
983 /* Similarly ignore dual loads from the stack. */
986 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
987 && (inst2 & 0x0d00) == 0x0c00
988 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
989 /* Similarly ignore single loads from the stack. */
992 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
993 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
994 /* Similarly ignore single loads from the stack. */
997 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
998 && (inst2 & 0x8000) == 0x0000)
1000 unsigned int imm = ((bits (insn, 10, 10) << 11)
1001 | (bits (inst2, 12, 14) << 8)
1002 | bits (inst2, 0, 7));
1004 regs[bits (inst2, 8, 11)]
1005 = pv_add_constant (regs[bits (insn, 0, 3)],
1006 thumb_expand_immediate (imm));
1009 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1010 && (inst2 & 0x8000) == 0x0000)
1012 unsigned int imm = ((bits (insn, 10, 10) << 11)
1013 | (bits (inst2, 12, 14) << 8)
1014 | bits (inst2, 0, 7));
1016 regs[bits (inst2, 8, 11)]
1017 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1020 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1021 && (inst2 & 0x8000) == 0x0000)
1023 unsigned int imm = ((bits (insn, 10, 10) << 11)
1024 | (bits (inst2, 12, 14) << 8)
1025 | bits (inst2, 0, 7));
1027 regs[bits (inst2, 8, 11)]
1028 = pv_add_constant (regs[bits (insn, 0, 3)],
1029 - (CORE_ADDR) thumb_expand_immediate (imm));
1032 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1033 && (inst2 & 0x8000) == 0x0000)
1035 unsigned int imm = ((bits (insn, 10, 10) << 11)
1036 | (bits (inst2, 12, 14) << 8)
1037 | bits (inst2, 0, 7));
1039 regs[bits (inst2, 8, 11)]
1040 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1043 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1045 unsigned int imm = ((bits (insn, 10, 10) << 11)
1046 | (bits (inst2, 12, 14) << 8)
1047 | bits (inst2, 0, 7));
1049 regs[bits (inst2, 8, 11)]
1050 = pv_constant (thumb_expand_immediate (imm));
1053 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1056 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1058 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1061 else if (insn == 0xea5f /* mov.w Rd,Rm */
1062 && (inst2 & 0xf0f0) == 0)
1064 int dst_reg = (inst2 & 0x0f00) >> 8;
1065 int src_reg = inst2 & 0xf;
1066 regs[dst_reg] = regs[src_reg];
1069 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1071 /* Constant pool loads. */
1072 unsigned int constant;
1075 offset = bits (insn, 0, 11);
1077 loc = start + 4 + offset;
1079 loc = start + 4 - offset;
1081 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1082 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1085 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1087 /* Constant pool loads. */
1088 unsigned int constant;
1091 offset = bits (insn, 0, 7) << 2;
1093 loc = start + 4 + offset;
1095 loc = start + 4 - offset;
1097 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1098 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1100 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1101 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1104 else if (thumb2_instruction_changes_pc (insn, inst2))
1106 /* Don't scan past anything that might change control flow. */
1111 /* The optimizer might shove anything into the prologue,
1112 so we just skip what we don't recognize. */
1113 unrecognized_pc = start;
1118 else if (thumb_instruction_changes_pc (insn))
1120 /* Don't scan past anything that might change control flow. */
1125 /* The optimizer might shove anything into the prologue,
1126 so we just skip what we don't recognize. */
1127 unrecognized_pc = start;
1134 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1135 paddress (gdbarch, start));
1137 if (unrecognized_pc == 0)
1138 unrecognized_pc = start;
1142 do_cleanups (back_to);
1143 return unrecognized_pc;
1146 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1148 /* Frame pointer is fp. Frame size is constant. */
1149 cache->framereg = ARM_FP_REGNUM;
1150 cache->framesize = -regs[ARM_FP_REGNUM].k;
1152 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1154 /* Frame pointer is r7. Frame size is constant. */
1155 cache->framereg = THUMB_FP_REGNUM;
1156 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1160 /* Try the stack pointer... this is a bit desperate. */
1161 cache->framereg = ARM_SP_REGNUM;
1162 cache->framesize = -regs[ARM_SP_REGNUM].k;
1165 for (i = 0; i < 16; i++)
1166 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1167 cache->saved_regs[i].addr = offset;
1169 do_cleanups (back_to);
1170 return unrecognized_pc;
1174 /* Try to analyze the instructions starting from PC, which load symbol
1175 __stack_chk_guard. Return the address of instruction after loading this
1176 symbol, set the dest register number to *BASEREG, and set the size of
1177 instructions for loading symbol in OFFSET. Return 0 if instructions are
1181 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1182 unsigned int *destreg, int *offset)
1184 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1185 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1186 unsigned int low, high, address;
1191 unsigned short insn1
1192 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1194 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1196 *destreg = bits (insn1, 8, 10);
1198 address = bits (insn1, 0, 7);
1200 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1202 unsigned short insn2
1203 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1205 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1208 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1210 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1212 /* movt Rd, #const */
1213 if ((insn1 & 0xfbc0) == 0xf2c0)
1215 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1216 *destreg = bits (insn2, 8, 11);
1218 address = (high << 16 | low);
1225 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1227 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1229 address = bits (insn, 0, 11);
1230 *destreg = bits (insn, 12, 15);
1233 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1235 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1238 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1240 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1242 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1243 *destreg = bits (insn, 12, 15);
1245 address = (high << 16 | low);
1253 /* Try to skip a sequence of instructions used for stack protector. If PC
1254 points to the first instruction of this sequence, return the address of
1255 first instruction after this sequence, otherwise, return original PC.
1257 On arm, this sequence of instructions is composed of mainly three steps,
1258 Step 1: load symbol __stack_chk_guard,
1259 Step 2: load from address of __stack_chk_guard,
1260 Step 3: store it to somewhere else.
1262 Usually, instructions on step 2 and step 3 are the same on various ARM
1263 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1264 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1265 instructions in step 1 vary from different ARM architectures. On ARMv7,
1268 movw Rn, #:lower16:__stack_chk_guard
1269 movt Rn, #:upper16:__stack_chk_guard
1276 .word __stack_chk_guard
1278 Since ldr/str is a very popular instruction, we can't use them as
1279 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1280 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1281 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1284 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1286 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1287 unsigned int basereg;
1288 struct minimal_symbol *stack_chk_guard;
1290 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1293 /* Try to parse the instructions in Step 1. */
1294 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1299 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1300 /* If name of symbol doesn't start with '__stack_chk_guard', this
1301 instruction sequence is not for stack protector. If symbol is
1302 removed, we conservatively think this sequence is for stack protector. */
1304 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
1305 strlen ("__stack_chk_guard")) != 0)
1310 unsigned int destreg;
1312 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1314 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1315 if ((insn & 0xf800) != 0x6800)
1317 if (bits (insn, 3, 5) != basereg)
1319 destreg = bits (insn, 0, 2);
1321 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1322 byte_order_for_code);
1323 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1324 if ((insn & 0xf800) != 0x6000)
1326 if (destreg != bits (insn, 0, 2))
1331 unsigned int destreg;
1333 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1335 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1336 if ((insn & 0x0e500000) != 0x04100000)
1338 if (bits (insn, 16, 19) != basereg)
1340 destreg = bits (insn, 12, 15);
1341 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1342 insn = read_memory_unsigned_integer (pc + offset + 4,
1343 4, byte_order_for_code);
1344 if ((insn & 0x0e500000) != 0x04000000)
1346 if (bits (insn, 12, 15) != destreg)
1349 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1352 return pc + offset + 4;
1354 return pc + offset + 8;
1357 /* Advance the PC across any function entry prologue instructions to
1358 reach some "real" code.
1360 The APCS (ARM Procedure Call Standard) defines the following
1364 [stmfd sp!, {a1,a2,a3,a4}]
1365 stmfd sp!, {...,fp,ip,lr,pc}
1366 [stfe f7, [sp, #-12]!]
1367 [stfe f6, [sp, #-12]!]
1368 [stfe f5, [sp, #-12]!]
1369 [stfe f4, [sp, #-12]!]
1370 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1373 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1375 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1378 CORE_ADDR func_addr, limit_pc;
1380 /* See if we can determine the end of the prologue via the symbol table.
1381 If so, then return either PC, or the PC after the prologue, whichever
1383 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1385 CORE_ADDR post_prologue_pc
1386 = skip_prologue_using_sal (gdbarch, func_addr);
1387 struct symtab *s = find_pc_symtab (func_addr);
1389 if (post_prologue_pc)
1391 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1394 /* GCC always emits a line note before the prologue and another
1395 one after, even if the two are at the same address or on the
1396 same line. Take advantage of this so that we do not need to
1397 know every instruction that might appear in the prologue. We
1398 will have producer information for most binaries; if it is
1399 missing (e.g. for -gstabs), assuming the GNU tools. */
1400 if (post_prologue_pc
1402 || s->producer == NULL
1403 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0))
1404 return post_prologue_pc;
1406 if (post_prologue_pc != 0)
1408 CORE_ADDR analyzed_limit;
1410 /* For non-GCC compilers, make sure the entire line is an
1411 acceptable prologue; GDB will round this function's
1412 return value up to the end of the following line so we
1413 can not skip just part of a line (and we do not want to).
1415 RealView does not treat the prologue specially, but does
1416 associate prologue code with the opening brace; so this
1417 lets us skip the first line if we think it is the opening
1419 if (arm_pc_is_thumb (gdbarch, func_addr))
1420 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1421 post_prologue_pc, NULL);
1423 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1424 post_prologue_pc, NULL);
1426 if (analyzed_limit != post_prologue_pc)
1429 return post_prologue_pc;
1433 /* Can't determine prologue from the symbol table, need to examine
1436 /* Find an upper limit on the function prologue using the debug
1437 information. If the debug information could not be used to provide
1438 that bound, then use an arbitrary large number as the upper bound. */
1439 /* Like arm_scan_prologue, stop no later than pc + 64. */
1440 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1442 limit_pc = pc + 64; /* Magic. */
1445 /* Check if this is Thumb code. */
1446 if (arm_pc_is_thumb (gdbarch, pc))
1447 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1449 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1451 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1453 /* "mov ip, sp" is no longer a required part of the prologue. */
1454 if (inst == 0xe1a0c00d) /* mov ip, sp */
1457 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1460 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1463 /* Some prologues begin with "str lr, [sp, #-4]!". */
1464 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1467 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1470 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1473 /* Any insns after this point may float into the code, if it makes
1474 for better instruction scheduling, so we skip them only if we
1475 find them, but still consider the function to be frame-ful. */
1477 /* We may have either one sfmfd instruction here, or several stfe
1478 insns, depending on the version of floating point code we
1480 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1483 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1486 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1489 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1492 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1493 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1494 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1497 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1498 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1499 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1502 /* Un-recognized instruction; stop scanning. */
1506 return skip_pc; /* End of prologue. */
1510 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1511 This function decodes a Thumb function prologue to determine:
1512 1) the size of the stack frame
1513 2) which registers are saved on it
1514 3) the offsets of saved regs
1515 4) the offset from the stack pointer to the frame pointer
1517 A typical Thumb function prologue would create this stack frame
1518 (offsets relative to FP)
1519 old SP -> 24 stack parameters
1522 R7 -> 0 local variables (16 bytes)
1523 SP -> -12 additional stack space (12 bytes)
1524 The frame size would thus be 36 bytes, and the frame offset would be
1525 12 bytes. The frame register is R7.
1527 The comments for thumb_skip_prolog() describe the algorithm we use
1528 to detect the end of the prolog. */
1532 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1533 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1535 CORE_ADDR prologue_start;
1536 CORE_ADDR prologue_end;
1538 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1541 /* See comment in arm_scan_prologue for an explanation of
1543 if (prologue_end > prologue_start + 64)
1545 prologue_end = prologue_start + 64;
1549 /* We're in the boondocks: we have no idea where the start of the
1553 prologue_end = min (prologue_end, prev_pc);
1555 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1558 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1561 arm_instruction_changes_pc (uint32_t this_instr)
1563 if (bits (this_instr, 28, 31) == INST_NV)
1564 /* Unconditional instructions. */
1565 switch (bits (this_instr, 24, 27))
1569 /* Branch with Link and change to Thumb. */
1574 /* Coprocessor register transfer. */
1575 if (bits (this_instr, 12, 15) == 15)
1576 error (_("Invalid update to pc in instruction"));
1582 switch (bits (this_instr, 25, 27))
1585 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1587 /* Multiplies and extra load/stores. */
1588 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1589 /* Neither multiplies nor extension load/stores are allowed
1593 /* Otherwise, miscellaneous instructions. */
1595 /* BX <reg>, BXJ <reg>, BLX <reg> */
1596 if (bits (this_instr, 4, 27) == 0x12fff1
1597 || bits (this_instr, 4, 27) == 0x12fff2
1598 || bits (this_instr, 4, 27) == 0x12fff3)
1601 /* Other miscellaneous instructions are unpredictable if they
1605 /* Data processing instruction. Fall through. */
1608 if (bits (this_instr, 12, 15) == 15)
1615 /* Media instructions and architecturally undefined instructions. */
1616 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1620 if (bit (this_instr, 20) == 0)
1624 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1630 /* Load/store multiple. */
1631 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1637 /* Branch and branch with link. */
1642 /* Coprocessor transfers or SWIs can not affect PC. */
1646 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1650 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1651 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1652 fill it in. Return the first address not recognized as a prologue
1655 We recognize all the instructions typically found in ARM prologues,
1656 plus harmless instructions which can be skipped (either for analysis
1657 purposes, or a more restrictive set that can be skipped when finding
1658 the end of the prologue). */
1661 arm_analyze_prologue (struct gdbarch *gdbarch,
1662 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1663 struct arm_prologue_cache *cache)
1665 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1666 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1668 CORE_ADDR offset, current_pc;
1669 pv_t regs[ARM_FPS_REGNUM];
1670 struct pv_area *stack;
1671 struct cleanup *back_to;
1672 int framereg, framesize;
1673 CORE_ADDR unrecognized_pc = 0;
1675 /* Search the prologue looking for instructions that set up the
1676 frame pointer, adjust the stack pointer, and save registers.
1678 Be careful, however, and if it doesn't look like a prologue,
1679 don't try to scan it. If, for instance, a frameless function
1680 begins with stmfd sp!, then we will tell ourselves there is
1681 a frame, which will confuse stack traceback, as well as "finish"
1682 and other operations that rely on a knowledge of the stack
1685 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1686 regs[regno] = pv_register (regno, 0);
1687 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1688 back_to = make_cleanup_free_pv_area (stack);
1690 for (current_pc = prologue_start;
1691 current_pc < prologue_end;
1695 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1697 if (insn == 0xe1a0c00d) /* mov ip, sp */
1699 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1702 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1703 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1705 unsigned imm = insn & 0xff; /* immediate value */
1706 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1707 int rd = bits (insn, 12, 15);
1708 imm = (imm >> rot) | (imm << (32 - rot));
1709 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1712 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1713 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1715 unsigned imm = insn & 0xff; /* immediate value */
1716 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1717 int rd = bits (insn, 12, 15);
1718 imm = (imm >> rot) | (imm << (32 - rot));
1719 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1722 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1725 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1727 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1728 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1729 regs[bits (insn, 12, 15)]);
1732 else if ((insn & 0xffff0000) == 0xe92d0000)
1733 /* stmfd sp!, {..., fp, ip, lr, pc}
1735 stmfd sp!, {a1, a2, a3, a4} */
1737 int mask = insn & 0xffff;
1739 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1742 /* Calculate offsets of saved registers. */
1743 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1744 if (mask & (1 << regno))
1747 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1748 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1751 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1752 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1753 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1755 /* No need to add this to saved_regs -- it's just an arg reg. */
1758 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1759 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1760 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1762 /* No need to add this to saved_regs -- it's just an arg reg. */
1765 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1767 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1769 /* No need to add this to saved_regs -- it's just arg regs. */
1772 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1774 unsigned imm = insn & 0xff; /* immediate value */
1775 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1776 imm = (imm >> rot) | (imm << (32 - rot));
1777 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1779 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1781 unsigned imm = insn & 0xff; /* immediate value */
1782 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1783 imm = (imm >> rot) | (imm << (32 - rot));
1784 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1786 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1788 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1790 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1793 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1794 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1795 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1797 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1799 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1801 int n_saved_fp_regs;
1802 unsigned int fp_start_reg, fp_bound_reg;
1804 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1807 if ((insn & 0x800) == 0x800) /* N0 is set */
1809 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1810 n_saved_fp_regs = 3;
1812 n_saved_fp_regs = 1;
1816 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1817 n_saved_fp_regs = 2;
1819 n_saved_fp_regs = 4;
1822 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1823 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1824 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1826 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1827 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1828 regs[fp_start_reg++]);
1831 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1833 /* Allow some special function calls when skipping the
1834 prologue; GCC generates these before storing arguments to
1836 CORE_ADDR dest = BranchDest (current_pc, insn);
1838 if (skip_prologue_function (gdbarch, dest, 0))
1843 else if ((insn & 0xf0000000) != 0xe0000000)
1844 break; /* Condition not true, exit early. */
1845 else if (arm_instruction_changes_pc (insn))
1846 /* Don't scan past anything that might change control flow. */
1848 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1849 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1850 /* Ignore block loads from the stack, potentially copying
1851 parameters from memory. */
1853 else if ((insn & 0xfc500000) == 0xe4100000
1854 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1855 /* Similarly ignore single loads from the stack. */
1857 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1858 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1859 register instead of the stack. */
1863 /* The optimizer might shove anything into the prologue,
1864 so we just skip what we don't recognize. */
1865 unrecognized_pc = current_pc;
1870 if (unrecognized_pc == 0)
1871 unrecognized_pc = current_pc;
1873 /* The frame size is just the distance from the frame register
1874 to the original stack pointer. */
1875 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1877 /* Frame pointer is fp. */
1878 framereg = ARM_FP_REGNUM;
1879 framesize = -regs[ARM_FP_REGNUM].k;
1883 /* Try the stack pointer... this is a bit desperate. */
1884 framereg = ARM_SP_REGNUM;
1885 framesize = -regs[ARM_SP_REGNUM].k;
1890 cache->framereg = framereg;
1891 cache->framesize = framesize;
1893 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1894 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1895 cache->saved_regs[regno].addr = offset;
1899 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1900 paddress (gdbarch, unrecognized_pc));
1902 do_cleanups (back_to);
1903 return unrecognized_pc;
1907 arm_scan_prologue (struct frame_info *this_frame,
1908 struct arm_prologue_cache *cache)
1910 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1911 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1913 CORE_ADDR prologue_start, prologue_end, current_pc;
1914 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1915 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1916 pv_t regs[ARM_FPS_REGNUM];
1917 struct pv_area *stack;
1918 struct cleanup *back_to;
1921 /* Assume there is no frame until proven otherwise. */
1922 cache->framereg = ARM_SP_REGNUM;
1923 cache->framesize = 0;
1925 /* Check for Thumb prologue. */
1926 if (arm_frame_is_thumb (this_frame))
1928 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1932 /* Find the function prologue. If we can't find the function in
1933 the symbol table, peek in the stack frame to find the PC. */
1934 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1937 /* One way to find the end of the prologue (which works well
1938 for unoptimized code) is to do the following:
1940 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1943 prologue_end = prev_pc;
1944 else if (sal.end < prologue_end)
1945 prologue_end = sal.end;
1947 This mechanism is very accurate so long as the optimizer
1948 doesn't move any instructions from the function body into the
1949 prologue. If this happens, sal.end will be the last
1950 instruction in the first hunk of prologue code just before
1951 the first instruction that the scheduler has moved from
1952 the body to the prologue.
1954 In order to make sure that we scan all of the prologue
1955 instructions, we use a slightly less accurate mechanism which
1956 may scan more than necessary. To help compensate for this
1957 lack of accuracy, the prologue scanning loop below contains
1958 several clauses which'll cause the loop to terminate early if
1959 an implausible prologue instruction is encountered.
1965 is a suitable endpoint since it accounts for the largest
1966 possible prologue plus up to five instructions inserted by
1969 if (prologue_end > prologue_start + 64)
1971 prologue_end = prologue_start + 64; /* See above. */
1976 /* We have no symbol information. Our only option is to assume this
1977 function has a standard stack frame and the normal frame register.
1978 Then, we can find the value of our frame pointer on entrance to
1979 the callee (or at the present moment if this is the innermost frame).
1980 The value stored there should be the address of the stmfd + 8. */
1981 CORE_ADDR frame_loc;
1982 LONGEST return_value;
1984 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1985 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1989 prologue_start = gdbarch_addr_bits_remove
1990 (gdbarch, return_value) - 8;
1991 prologue_end = prologue_start + 64; /* See above. */
1995 if (prev_pc < prologue_end)
1996 prologue_end = prev_pc;
1998 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2001 static struct arm_prologue_cache *
2002 arm_make_prologue_cache (struct frame_info *this_frame)
2005 struct arm_prologue_cache *cache;
2006 CORE_ADDR unwound_fp;
2008 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2009 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2011 arm_scan_prologue (this_frame, cache);
2013 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2014 if (unwound_fp == 0)
2017 cache->prev_sp = unwound_fp + cache->framesize;
2019 /* Calculate actual addresses of saved registers using offsets
2020 determined by arm_scan_prologue. */
2021 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2022 if (trad_frame_addr_p (cache->saved_regs, reg))
2023 cache->saved_regs[reg].addr += cache->prev_sp;
2028 /* Our frame ID for a normal frame is the current function's starting PC
2029 and the caller's SP when we were called. */
2032 arm_prologue_this_id (struct frame_info *this_frame,
2034 struct frame_id *this_id)
2036 struct arm_prologue_cache *cache;
2040 if (*this_cache == NULL)
2041 *this_cache = arm_make_prologue_cache (this_frame);
2042 cache = *this_cache;
2044 /* This is meant to halt the backtrace at "_start". */
2045 pc = get_frame_pc (this_frame);
2046 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2049 /* If we've hit a wall, stop. */
2050 if (cache->prev_sp == 0)
2053 /* Use function start address as part of the frame ID. If we cannot
2054 identify the start address (due to missing symbol information),
2055 fall back to just using the current PC. */
2056 func = get_frame_func (this_frame);
2060 id = frame_id_build (cache->prev_sp, func);
2064 static struct value *
2065 arm_prologue_prev_register (struct frame_info *this_frame,
2069 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2070 struct arm_prologue_cache *cache;
2072 if (*this_cache == NULL)
2073 *this_cache = arm_make_prologue_cache (this_frame);
2074 cache = *this_cache;
2076 /* If we are asked to unwind the PC, then we need to return the LR
2077 instead. The prologue may save PC, but it will point into this
2078 frame's prologue, not the next frame's resume location. Also
2079 strip the saved T bit. A valid LR may have the low bit set, but
2080 a valid PC never does. */
2081 if (prev_regnum == ARM_PC_REGNUM)
2085 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2086 return frame_unwind_got_constant (this_frame, prev_regnum,
2087 arm_addr_bits_remove (gdbarch, lr));
2090 /* SP is generally not saved to the stack, but this frame is
2091 identified by the next frame's stack pointer at the time of the call.
2092 The value was already reconstructed into PREV_SP. */
2093 if (prev_regnum == ARM_SP_REGNUM)
2094 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2096 /* The CPSR may have been changed by the call instruction and by the
2097 called function. The only bit we can reconstruct is the T bit,
2098 by checking the low bit of LR as of the call. This is a reliable
2099 indicator of Thumb-ness except for some ARM v4T pre-interworking
2100 Thumb code, which could get away with a clear low bit as long as
2101 the called function did not use bx. Guess that all other
2102 bits are unchanged; the condition flags are presumably lost,
2103 but the processor status is likely valid. */
2104 if (prev_regnum == ARM_PS_REGNUM)
2107 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2109 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2110 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2111 if (IS_THUMB_ADDR (lr))
2115 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2118 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2122 struct frame_unwind arm_prologue_unwind = {
2124 default_frame_unwind_stop_reason,
2125 arm_prologue_this_id,
2126 arm_prologue_prev_register,
2128 default_frame_sniffer
2131 /* Maintain a list of ARM exception table entries per objfile, similar to the
2132 list of mapping symbols. We only cache entries for standard ARM-defined
2133 personality routines; the cache will contain only the frame unwinding
2134 instructions associated with the entry (not the descriptors). */
2136 static const struct objfile_data *arm_exidx_data_key;
2138 struct arm_exidx_entry
2143 typedef struct arm_exidx_entry arm_exidx_entry_s;
2144 DEF_VEC_O(arm_exidx_entry_s);
2146 struct arm_exidx_data
2148 VEC(arm_exidx_entry_s) **section_maps;
2152 arm_exidx_data_free (struct objfile *objfile, void *arg)
2154 struct arm_exidx_data *data = arg;
2157 for (i = 0; i < objfile->obfd->section_count; i++)
2158 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2162 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2163 const struct arm_exidx_entry *rhs)
2165 return lhs->addr < rhs->addr;
2168 static struct obj_section *
2169 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2171 struct obj_section *osect;
2173 ALL_OBJFILE_OSECTIONS (objfile, osect)
2174 if (bfd_get_section_flags (objfile->obfd,
2175 osect->the_bfd_section) & SEC_ALLOC)
2177 bfd_vma start, size;
2178 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2179 size = bfd_get_section_size (osect->the_bfd_section);
2181 if (start <= vma && vma < start + size)
2188 /* Parse contents of exception table and exception index sections
2189 of OBJFILE, and fill in the exception table entry cache.
2191 For each entry that refers to a standard ARM-defined personality
2192 routine, extract the frame unwinding instructions (from either
2193 the index or the table section). The unwinding instructions
2195 - extracting them from the rest of the table data
2196 - converting to host endianness
2197 - appending the implicit 0xb0 ("Finish") code
2199 The extracted and normalized instructions are stored for later
2200 retrieval by the arm_find_exidx_entry routine. */
2203 arm_exidx_new_objfile (struct objfile *objfile)
2205 struct cleanup *cleanups;
2206 struct arm_exidx_data *data;
2207 asection *exidx, *extab;
2208 bfd_vma exidx_vma = 0, extab_vma = 0;
2209 bfd_size_type exidx_size = 0, extab_size = 0;
2210 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2213 /* If we've already touched this file, do nothing. */
2214 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2216 cleanups = make_cleanup (null_cleanup, NULL);
2218 /* Read contents of exception table and index. */
2219 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2222 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2223 exidx_size = bfd_get_section_size (exidx);
2224 exidx_data = xmalloc (exidx_size);
2225 make_cleanup (xfree, exidx_data);
2227 if (!bfd_get_section_contents (objfile->obfd, exidx,
2228 exidx_data, 0, exidx_size))
2230 do_cleanups (cleanups);
2235 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2238 extab_vma = bfd_section_vma (objfile->obfd, extab);
2239 extab_size = bfd_get_section_size (extab);
2240 extab_data = xmalloc (extab_size);
2241 make_cleanup (xfree, extab_data);
2243 if (!bfd_get_section_contents (objfile->obfd, extab,
2244 extab_data, 0, extab_size))
2246 do_cleanups (cleanups);
2251 /* Allocate exception table data structure. */
2252 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2253 set_objfile_data (objfile, arm_exidx_data_key, data);
2254 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2255 objfile->obfd->section_count,
2256 VEC(arm_exidx_entry_s) *);
2258 /* Fill in exception table. */
2259 for (i = 0; i < exidx_size / 8; i++)
2261 struct arm_exidx_entry new_exidx_entry;
2262 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2263 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2264 bfd_vma addr = 0, word = 0;
2265 int n_bytes = 0, n_words = 0;
2266 struct obj_section *sec;
2267 gdb_byte *entry = NULL;
2269 /* Extract address of start of function. */
2270 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2271 idx += exidx_vma + i * 8;
2273 /* Find section containing function and compute section offset. */
2274 sec = arm_obj_section_from_vma (objfile, idx);
2277 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2279 /* Determine address of exception table entry. */
2282 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2284 else if ((val & 0xff000000) == 0x80000000)
2286 /* Exception table entry embedded in .ARM.exidx
2287 -- must be short form. */
2291 else if (!(val & 0x80000000))
2293 /* Exception table entry in .ARM.extab. */
2294 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2295 addr += exidx_vma + i * 8 + 4;
2297 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2299 word = bfd_h_get_32 (objfile->obfd,
2300 extab_data + addr - extab_vma);
2303 if ((word & 0xff000000) == 0x80000000)
2308 else if ((word & 0xff000000) == 0x81000000
2309 || (word & 0xff000000) == 0x82000000)
2313 n_words = ((word >> 16) & 0xff);
2315 else if (!(word & 0x80000000))
2318 struct obj_section *pers_sec;
2319 int gnu_personality = 0;
2321 /* Custom personality routine. */
2322 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2323 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2325 /* Check whether we've got one of the variants of the
2326 GNU personality routines. */
2327 pers_sec = arm_obj_section_from_vma (objfile, pers);
2330 static const char *personality[] =
2332 "__gcc_personality_v0",
2333 "__gxx_personality_v0",
2334 "__gcj_personality_v0",
2335 "__gnu_objc_personality_v0",
2339 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2342 for (k = 0; personality[k]; k++)
2343 if (lookup_minimal_symbol_by_pc_name
2344 (pc, personality[k], objfile))
2346 gnu_personality = 1;
2351 /* If so, the next word contains a word count in the high
2352 byte, followed by the same unwind instructions as the
2353 pre-defined forms. */
2355 && addr + 4 <= extab_vma + extab_size)
2357 word = bfd_h_get_32 (objfile->obfd,
2358 extab_data + addr - extab_vma);
2361 n_words = ((word >> 24) & 0xff);
2367 /* Sanity check address. */
2369 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2370 n_words = n_bytes = 0;
2372 /* The unwind instructions reside in WORD (only the N_BYTES least
2373 significant bytes are valid), followed by N_WORDS words in the
2374 extab section starting at ADDR. */
2375 if (n_bytes || n_words)
2377 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2378 n_bytes + n_words * 4 + 1);
2381 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2385 word = bfd_h_get_32 (objfile->obfd,
2386 extab_data + addr - extab_vma);
2389 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2390 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2391 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2392 *p++ = (gdb_byte) (word & 0xff);
2395 /* Implied "Finish" to terminate the list. */
2399 /* Push entry onto vector. They are guaranteed to always
2400 appear in order of increasing addresses. */
2401 new_exidx_entry.addr = idx;
2402 new_exidx_entry.entry = entry;
2403 VEC_safe_push (arm_exidx_entry_s,
2404 data->section_maps[sec->the_bfd_section->index],
2408 do_cleanups (cleanups);
2411 /* Search for the exception table entry covering MEMADDR. If one is found,
2412 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2413 set *START to the start of the region covered by this entry. */
2416 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2418 struct obj_section *sec;
2420 sec = find_pc_section (memaddr);
2423 struct arm_exidx_data *data;
2424 VEC(arm_exidx_entry_s) *map;
2425 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2428 data = objfile_data (sec->objfile, arm_exidx_data_key);
2431 map = data->section_maps[sec->the_bfd_section->index];
2432 if (!VEC_empty (arm_exidx_entry_s, map))
2434 struct arm_exidx_entry *map_sym;
2436 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2437 arm_compare_exidx_entries);
2439 /* VEC_lower_bound finds the earliest ordered insertion
2440 point. If the following symbol starts at this exact
2441 address, we use that; otherwise, the preceding
2442 exception table entry covers this address. */
2443 if (idx < VEC_length (arm_exidx_entry_s, map))
2445 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2446 if (map_sym->addr == map_key.addr)
2449 *start = map_sym->addr + obj_section_addr (sec);
2450 return map_sym->entry;
2456 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2458 *start = map_sym->addr + obj_section_addr (sec);
2459 return map_sym->entry;
2468 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2469 instruction list from the ARM exception table entry ENTRY, allocate and
2470 return a prologue cache structure describing how to unwind this frame.
2472 Return NULL if the unwinding instruction list contains a "spare",
2473 "reserved" or "refuse to unwind" instruction as defined in section
2474 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2475 for the ARM Architecture" document. */
2477 static struct arm_prologue_cache *
2478 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2483 struct arm_prologue_cache *cache;
2484 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2485 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2491 /* Whenever we reload SP, we actually have to retrieve its
2492 actual value in the current frame. */
2495 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2497 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2498 vsp = get_frame_register_unsigned (this_frame, reg);
2502 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2503 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2509 /* Decode next unwind instruction. */
2512 if ((insn & 0xc0) == 0)
2514 int offset = insn & 0x3f;
2515 vsp += (offset << 2) + 4;
2517 else if ((insn & 0xc0) == 0x40)
2519 int offset = insn & 0x3f;
2520 vsp -= (offset << 2) + 4;
2522 else if ((insn & 0xf0) == 0x80)
2524 int mask = ((insn & 0xf) << 8) | *entry++;
2527 /* The special case of an all-zero mask identifies
2528 "Refuse to unwind". We return NULL to fall back
2529 to the prologue analyzer. */
2533 /* Pop registers r4..r15 under mask. */
2534 for (i = 0; i < 12; i++)
2535 if (mask & (1 << i))
2537 cache->saved_regs[4 + i].addr = vsp;
2541 /* Special-case popping SP -- we need to reload vsp. */
2542 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2545 else if ((insn & 0xf0) == 0x90)
2547 int reg = insn & 0xf;
2549 /* Reserved cases. */
2550 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2553 /* Set SP from another register and mark VSP for reload. */
2554 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2557 else if ((insn & 0xf0) == 0xa0)
2559 int count = insn & 0x7;
2560 int pop_lr = (insn & 0x8) != 0;
2563 /* Pop r4..r[4+count]. */
2564 for (i = 0; i <= count; i++)
2566 cache->saved_regs[4 + i].addr = vsp;
2570 /* If indicated by flag, pop LR as well. */
2573 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2577 else if (insn == 0xb0)
2579 /* We could only have updated PC by popping into it; if so, it
2580 will show up as address. Otherwise, copy LR into PC. */
2581 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2582 cache->saved_regs[ARM_PC_REGNUM]
2583 = cache->saved_regs[ARM_LR_REGNUM];
2588 else if (insn == 0xb1)
2590 int mask = *entry++;
2593 /* All-zero mask and mask >= 16 is "spare". */
2594 if (mask == 0 || mask >= 16)
2597 /* Pop r0..r3 under mask. */
2598 for (i = 0; i < 4; i++)
2599 if (mask & (1 << i))
2601 cache->saved_regs[i].addr = vsp;
2605 else if (insn == 0xb2)
2607 ULONGEST offset = 0;
2612 offset |= (*entry & 0x7f) << shift;
2615 while (*entry++ & 0x80);
2617 vsp += 0x204 + (offset << 2);
2619 else if (insn == 0xb3)
2621 int start = *entry >> 4;
2622 int count = (*entry++) & 0xf;
2625 /* Only registers D0..D15 are valid here. */
2626 if (start + count >= 16)
2629 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2630 for (i = 0; i <= count; i++)
2632 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2636 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2639 else if ((insn & 0xf8) == 0xb8)
2641 int count = insn & 0x7;
2644 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2645 for (i = 0; i <= count; i++)
2647 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2651 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2654 else if (insn == 0xc6)
2656 int start = *entry >> 4;
2657 int count = (*entry++) & 0xf;
2660 /* Only registers WR0..WR15 are valid. */
2661 if (start + count >= 16)
2664 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2665 for (i = 0; i <= count; i++)
2667 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2671 else if (insn == 0xc7)
2673 int mask = *entry++;
2676 /* All-zero mask and mask >= 16 is "spare". */
2677 if (mask == 0 || mask >= 16)
2680 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2681 for (i = 0; i < 4; i++)
2682 if (mask & (1 << i))
2684 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2688 else if ((insn & 0xf8) == 0xc0)
2690 int count = insn & 0x7;
2693 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2694 for (i = 0; i <= count; i++)
2696 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2700 else if (insn == 0xc8)
2702 int start = *entry >> 4;
2703 int count = (*entry++) & 0xf;
2706 /* Only registers D0..D31 are valid. */
2707 if (start + count >= 16)
2710 /* Pop VFP double-precision registers
2711 D[16+start]..D[16+start+count]. */
2712 for (i = 0; i <= count; i++)
2714 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2718 else if (insn == 0xc9)
2720 int start = *entry >> 4;
2721 int count = (*entry++) & 0xf;
2724 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2725 for (i = 0; i <= count; i++)
2727 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2731 else if ((insn & 0xf8) == 0xd0)
2733 int count = insn & 0x7;
2736 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2737 for (i = 0; i <= count; i++)
2739 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2745 /* Everything else is "spare". */
2750 /* If we restore SP from a register, assume this was the frame register.
2751 Otherwise just fall back to SP as frame register. */
2752 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2753 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2755 cache->framereg = ARM_SP_REGNUM;
2757 /* Determine offset to previous frame. */
2759 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2761 /* We already got the previous SP. */
2762 cache->prev_sp = vsp;
2767 /* Unwinding via ARM exception table entries. Note that the sniffer
2768 already computes a filled-in prologue cache, which is then used
2769 with the same arm_prologue_this_id and arm_prologue_prev_register
2770 routines also used for prologue-parsing based unwinding. */
2773 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2774 struct frame_info *this_frame,
2775 void **this_prologue_cache)
2777 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2778 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2779 CORE_ADDR addr_in_block, exidx_region, func_start;
2780 struct arm_prologue_cache *cache;
2783 /* See if we have an ARM exception table entry covering this address. */
2784 addr_in_block = get_frame_address_in_block (this_frame);
2785 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2789 /* The ARM exception table does not describe unwind information
2790 for arbitrary PC values, but is guaranteed to be correct only
2791 at call sites. We have to decide here whether we want to use
2792 ARM exception table information for this frame, or fall back
2793 to using prologue parsing. (Note that if we have DWARF CFI,
2794 this sniffer isn't even called -- CFI is always preferred.)
2796 Before we make this decision, however, we check whether we
2797 actually have *symbol* information for the current frame.
2798 If not, prologue parsing would not work anyway, so we might
2799 as well use the exception table and hope for the best. */
2800 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2804 /* If the next frame is "normal", we are at a call site in this
2805 frame, so exception information is guaranteed to be valid. */
2806 if (get_next_frame (this_frame)
2807 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2810 /* We also assume exception information is valid if we're currently
2811 blocked in a system call. The system library is supposed to
2812 ensure this, so that e.g. pthread cancellation works. */
2813 if (arm_frame_is_thumb (this_frame))
2817 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2818 byte_order_for_code, &insn)
2819 && (insn & 0xff00) == 0xdf00 /* svc */)
2826 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2827 byte_order_for_code, &insn)
2828 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2832 /* Bail out if we don't know that exception information is valid. */
2836 /* The ARM exception index does not mark the *end* of the region
2837 covered by the entry, and some functions will not have any entry.
2838 To correctly recognize the end of the covered region, the linker
2839 should have inserted dummy records with a CANTUNWIND marker.
2841 Unfortunately, current versions of GNU ld do not reliably do
2842 this, and thus we may have found an incorrect entry above.
2843 As a (temporary) sanity check, we only use the entry if it
2844 lies *within* the bounds of the function. Note that this check
2845 might reject perfectly valid entries that just happen to cover
2846 multiple functions; therefore this check ought to be removed
2847 once the linker is fixed. */
2848 if (func_start > exidx_region)
2852 /* Decode the list of unwinding instructions into a prologue cache.
2853 Note that this may fail due to e.g. a "refuse to unwind" code. */
2854 cache = arm_exidx_fill_cache (this_frame, entry);
2858 *this_prologue_cache = cache;
2862 struct frame_unwind arm_exidx_unwind = {
2864 default_frame_unwind_stop_reason,
2865 arm_prologue_this_id,
2866 arm_prologue_prev_register,
2868 arm_exidx_unwind_sniffer
2871 static struct arm_prologue_cache *
2872 arm_make_stub_cache (struct frame_info *this_frame)
2874 struct arm_prologue_cache *cache;
2876 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2877 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2879 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2884 /* Our frame ID for a stub frame is the current SP and LR. */
2887 arm_stub_this_id (struct frame_info *this_frame,
2889 struct frame_id *this_id)
2891 struct arm_prologue_cache *cache;
2893 if (*this_cache == NULL)
2894 *this_cache = arm_make_stub_cache (this_frame);
2895 cache = *this_cache;
2897 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2901 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2902 struct frame_info *this_frame,
2903 void **this_prologue_cache)
2905 CORE_ADDR addr_in_block;
2908 addr_in_block = get_frame_address_in_block (this_frame);
2909 if (in_plt_section (addr_in_block, NULL)
2910 /* We also use the stub winder if the target memory is unreadable
2911 to avoid having the prologue unwinder trying to read it. */
2912 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2918 struct frame_unwind arm_stub_unwind = {
2920 default_frame_unwind_stop_reason,
2922 arm_prologue_prev_register,
2924 arm_stub_unwind_sniffer
2928 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
2930 struct arm_prologue_cache *cache;
2932 if (*this_cache == NULL)
2933 *this_cache = arm_make_prologue_cache (this_frame);
2934 cache = *this_cache;
2936 return cache->prev_sp - cache->framesize;
2939 struct frame_base arm_normal_base = {
2940 &arm_prologue_unwind,
2941 arm_normal_frame_base,
2942 arm_normal_frame_base,
2943 arm_normal_frame_base
2946 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2947 dummy frame. The frame ID's base needs to match the TOS value
2948 saved by save_dummy_frame_tos() and returned from
2949 arm_push_dummy_call, and the PC needs to match the dummy frame's
2952 static struct frame_id
2953 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2955 return frame_id_build (get_frame_register_unsigned (this_frame,
2957 get_frame_pc (this_frame));
2960 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2961 be used to construct the previous frame's ID, after looking up the
2962 containing function). */
2965 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
2968 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
2969 return arm_addr_bits_remove (gdbarch, pc);
2973 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
2975 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
2978 static struct value *
2979 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
2982 struct gdbarch * gdbarch = get_frame_arch (this_frame);
2984 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2989 /* The PC is normally copied from the return column, which
2990 describes saves of LR. However, that version may have an
2991 extra bit set to indicate Thumb state. The bit is not
2993 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2994 return frame_unwind_got_constant (this_frame, regnum,
2995 arm_addr_bits_remove (gdbarch, lr));
2998 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
2999 cpsr = get_frame_register_unsigned (this_frame, regnum);
3000 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3001 if (IS_THUMB_ADDR (lr))
3005 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3008 internal_error (__FILE__, __LINE__,
3009 _("Unexpected register %d"), regnum);
3014 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3015 struct dwarf2_frame_state_reg *reg,
3016 struct frame_info *this_frame)
3022 reg->how = DWARF2_FRAME_REG_FN;
3023 reg->loc.fn = arm_dwarf2_prev_register;
3026 reg->how = DWARF2_FRAME_REG_CFA;
3031 /* Return true if we are in the function's epilogue, i.e. after the
3032 instruction that destroyed the function's stack frame. */
3035 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3037 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3038 unsigned int insn, insn2;
3039 int found_return = 0, found_stack_adjust = 0;
3040 CORE_ADDR func_start, func_end;
3044 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3047 /* The epilogue is a sequence of instructions along the following lines:
3049 - add stack frame size to SP or FP
3050 - [if frame pointer used] restore SP from FP
3051 - restore registers from SP [may include PC]
3052 - a return-type instruction [if PC wasn't already restored]
3054 In a first pass, we scan forward from the current PC and verify the
3055 instructions we find as compatible with this sequence, ending in a
3058 However, this is not sufficient to distinguish indirect function calls
3059 within a function from indirect tail calls in the epilogue in some cases.
3060 Therefore, if we didn't already find any SP-changing instruction during
3061 forward scan, we add a backward scanning heuristic to ensure we actually
3062 are in the epilogue. */
3065 while (scan_pc < func_end && !found_return)
3067 if (target_read_memory (scan_pc, buf, 2))
3071 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3073 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3075 else if (insn == 0x46f7) /* mov pc, lr */
3077 else if (insn == 0x46bd) /* mov sp, r7 */
3078 found_stack_adjust = 1;
3079 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3080 found_stack_adjust = 1;
3081 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3083 found_stack_adjust = 1;
3084 if (insn & 0x0100) /* <registers> include PC. */
3087 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3089 if (target_read_memory (scan_pc, buf, 2))
3093 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3095 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3097 found_stack_adjust = 1;
3098 if (insn2 & 0x8000) /* <registers> include PC. */
3101 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3102 && (insn2 & 0x0fff) == 0x0b04)
3104 found_stack_adjust = 1;
3105 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3108 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3109 && (insn2 & 0x0e00) == 0x0a00)
3110 found_stack_adjust = 1;
3121 /* Since any instruction in the epilogue sequence, with the possible
3122 exception of return itself, updates the stack pointer, we need to
3123 scan backwards for at most one instruction. Try either a 16-bit or
3124 a 32-bit instruction. This is just a heuristic, so we do not worry
3125 too much about false positives. */
3127 if (!found_stack_adjust)
3129 if (pc - 4 < func_start)
3131 if (target_read_memory (pc - 4, buf, 4))
3134 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3135 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3137 if (insn2 == 0x46bd) /* mov sp, r7 */
3138 found_stack_adjust = 1;
3139 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3140 found_stack_adjust = 1;
3141 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3142 found_stack_adjust = 1;
3143 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3144 found_stack_adjust = 1;
3145 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3146 && (insn2 & 0x0fff) == 0x0b04)
3147 found_stack_adjust = 1;
3148 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3149 && (insn2 & 0x0e00) == 0x0a00)
3150 found_stack_adjust = 1;
3153 return found_stack_adjust;
3156 /* Return true if we are in the function's epilogue, i.e. after the
3157 instruction that destroyed the function's stack frame. */
3160 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3162 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3164 int found_return, found_stack_adjust;
3165 CORE_ADDR func_start, func_end;
3167 if (arm_pc_is_thumb (gdbarch, pc))
3168 return thumb_in_function_epilogue_p (gdbarch, pc);
3170 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3173 /* We are in the epilogue if the previous instruction was a stack
3174 adjustment and the next instruction is a possible return (bx, mov
3175 pc, or pop). We could have to scan backwards to find the stack
3176 adjustment, or forwards to find the return, but this is a decent
3177 approximation. First scan forwards. */
3180 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3181 if (bits (insn, 28, 31) != INST_NV)
3183 if ((insn & 0x0ffffff0) == 0x012fff10)
3186 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3189 else if ((insn & 0x0fff0000) == 0x08bd0000
3190 && (insn & 0x0000c000) != 0)
3191 /* POP (LDMIA), including PC or LR. */
3198 /* Scan backwards. This is just a heuristic, so do not worry about
3199 false positives from mode changes. */
3201 if (pc < func_start + 4)
3204 found_stack_adjust = 0;
3205 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3206 if (bits (insn, 28, 31) != INST_NV)
3208 if ((insn & 0x0df0f000) == 0x0080d000)
3209 /* ADD SP (register or immediate). */
3210 found_stack_adjust = 1;
3211 else if ((insn & 0x0df0f000) == 0x0040d000)
3212 /* SUB SP (register or immediate). */
3213 found_stack_adjust = 1;
3214 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3216 found_stack_adjust = 1;
3217 else if ((insn & 0x0fff0000) == 0x08bd0000)
3219 found_stack_adjust = 1;
3220 else if ((insn & 0x0fff0000) == 0x049d0000)
3221 /* POP of a single register. */
3222 found_stack_adjust = 1;
3225 if (found_stack_adjust)
3232 /* When arguments must be pushed onto the stack, they go on in reverse
3233 order. The code below implements a FILO (stack) to do this. */
3238 struct stack_item *prev;
3242 static struct stack_item *
3243 push_stack_item (struct stack_item *prev, const void *contents, int len)
3245 struct stack_item *si;
3246 si = xmalloc (sizeof (struct stack_item));
3247 si->data = xmalloc (len);
3250 memcpy (si->data, contents, len);
3254 static struct stack_item *
3255 pop_stack_item (struct stack_item *si)
3257 struct stack_item *dead = si;
3265 /* Return the alignment (in bytes) of the given type. */
3268 arm_type_align (struct type *t)
3274 t = check_typedef (t);
3275 switch (TYPE_CODE (t))
3278 /* Should never happen. */
3279 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3283 case TYPE_CODE_ENUM:
3287 case TYPE_CODE_RANGE:
3289 case TYPE_CODE_CHAR:
3290 case TYPE_CODE_BOOL:
3291 return TYPE_LENGTH (t);
3293 case TYPE_CODE_ARRAY:
3294 case TYPE_CODE_COMPLEX:
3295 /* TODO: What about vector types? */
3296 return arm_type_align (TYPE_TARGET_TYPE (t));
3298 case TYPE_CODE_STRUCT:
3299 case TYPE_CODE_UNION:
3301 for (n = 0; n < TYPE_NFIELDS (t); n++)
3303 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3311 /* Possible base types for a candidate for passing and returning in
3314 enum arm_vfp_cprc_base_type
3323 /* The length of one element of base type B. */
3326 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3330 case VFP_CPRC_SINGLE:
3332 case VFP_CPRC_DOUBLE:
3334 case VFP_CPRC_VEC64:
3336 case VFP_CPRC_VEC128:
3339 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3344 /* The character ('s', 'd' or 'q') for the type of VFP register used
3345 for passing base type B. */
3348 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3352 case VFP_CPRC_SINGLE:
3354 case VFP_CPRC_DOUBLE:
3356 case VFP_CPRC_VEC64:
3358 case VFP_CPRC_VEC128:
3361 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3366 /* Determine whether T may be part of a candidate for passing and
3367 returning in VFP registers, ignoring the limit on the total number
3368 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3369 classification of the first valid component found; if it is not
3370 VFP_CPRC_UNKNOWN, all components must have the same classification
3371 as *BASE_TYPE. If it is found that T contains a type not permitted
3372 for passing and returning in VFP registers, a type differently
3373 classified from *BASE_TYPE, or two types differently classified
3374 from each other, return -1, otherwise return the total number of
3375 base-type elements found (possibly 0 in an empty structure or
3376 array). Vectors and complex types are not currently supported,
3377 matching the generic AAPCS support. */
3380 arm_vfp_cprc_sub_candidate (struct type *t,
3381 enum arm_vfp_cprc_base_type *base_type)
3383 t = check_typedef (t);
3384 switch (TYPE_CODE (t))
3387 switch (TYPE_LENGTH (t))
3390 if (*base_type == VFP_CPRC_UNKNOWN)
3391 *base_type = VFP_CPRC_SINGLE;
3392 else if (*base_type != VFP_CPRC_SINGLE)
3397 if (*base_type == VFP_CPRC_UNKNOWN)
3398 *base_type = VFP_CPRC_DOUBLE;
3399 else if (*base_type != VFP_CPRC_DOUBLE)
3408 case TYPE_CODE_ARRAY:
3412 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3415 if (TYPE_LENGTH (t) == 0)
3417 gdb_assert (count == 0);
3420 else if (count == 0)
3422 unitlen = arm_vfp_cprc_unit_length (*base_type);
3423 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3424 return TYPE_LENGTH (t) / unitlen;
3428 case TYPE_CODE_STRUCT:
3433 for (i = 0; i < TYPE_NFIELDS (t); i++)
3435 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3437 if (sub_count == -1)
3441 if (TYPE_LENGTH (t) == 0)
3443 gdb_assert (count == 0);
3446 else if (count == 0)
3448 unitlen = arm_vfp_cprc_unit_length (*base_type);
3449 if (TYPE_LENGTH (t) != unitlen * count)
3454 case TYPE_CODE_UNION:
3459 for (i = 0; i < TYPE_NFIELDS (t); i++)
3461 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3463 if (sub_count == -1)
3465 count = (count > sub_count ? count : sub_count);
3467 if (TYPE_LENGTH (t) == 0)
3469 gdb_assert (count == 0);
3472 else if (count == 0)
3474 unitlen = arm_vfp_cprc_unit_length (*base_type);
3475 if (TYPE_LENGTH (t) != unitlen * count)
3487 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3488 if passed to or returned from a non-variadic function with the VFP
3489 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3490 *BASE_TYPE to the base type for T and *COUNT to the number of
3491 elements of that base type before returning. */
3494 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3497 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3498 int c = arm_vfp_cprc_sub_candidate (t, &b);
3499 if (c <= 0 || c > 4)
3506 /* Return 1 if the VFP ABI should be used for passing arguments to and
3507 returning values from a function of type FUNC_TYPE, 0
3511 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3514 /* Variadic functions always use the base ABI. Assume that functions
3515 without debug info are not variadic. */
3516 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3518 /* The VFP ABI is only supported as a variant of AAPCS. */
3519 if (tdep->arm_abi != ARM_ABI_AAPCS)
3521 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3524 /* We currently only support passing parameters in integer registers, which
3525 conforms with GCC's default model, and VFP argument passing following
3526 the VFP variant of AAPCS. Several other variants exist and
3527 we should probably support some of them based on the selected ABI. */
3530 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3531 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3532 struct value **args, CORE_ADDR sp, int struct_return,
3533 CORE_ADDR struct_addr)
3535 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3539 struct stack_item *si = NULL;
3542 unsigned vfp_regs_free = (1 << 16) - 1;
3544 /* Determine the type of this function and whether the VFP ABI
3546 ftype = check_typedef (value_type (function));
3547 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3548 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3549 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3551 /* Set the return address. For the ARM, the return breakpoint is
3552 always at BP_ADDR. */
3553 if (arm_pc_is_thumb (gdbarch, bp_addr))
3555 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3557 /* Walk through the list of args and determine how large a temporary
3558 stack is required. Need to take care here as structs may be
3559 passed on the stack, and we have to push them. */
3562 argreg = ARM_A1_REGNUM;
3565 /* The struct_return pointer occupies the first parameter
3566 passing register. */
3570 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3571 gdbarch_register_name (gdbarch, argreg),
3572 paddress (gdbarch, struct_addr));
3573 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3577 for (argnum = 0; argnum < nargs; argnum++)
3580 struct type *arg_type;
3581 struct type *target_type;
3582 enum type_code typecode;
3583 const bfd_byte *val;
3585 enum arm_vfp_cprc_base_type vfp_base_type;
3587 int may_use_core_reg = 1;
3589 arg_type = check_typedef (value_type (args[argnum]));
3590 len = TYPE_LENGTH (arg_type);
3591 target_type = TYPE_TARGET_TYPE (arg_type);
3592 typecode = TYPE_CODE (arg_type);
3593 val = value_contents (args[argnum]);
3595 align = arm_type_align (arg_type);
3596 /* Round alignment up to a whole number of words. */
3597 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3598 /* Different ABIs have different maximum alignments. */
3599 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3601 /* The APCS ABI only requires word alignment. */
3602 align = INT_REGISTER_SIZE;
3606 /* The AAPCS requires at most doubleword alignment. */
3607 if (align > INT_REGISTER_SIZE * 2)
3608 align = INT_REGISTER_SIZE * 2;
3612 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3620 /* Because this is a CPRC it cannot go in a core register or
3621 cause a core register to be skipped for alignment.
3622 Either it goes in VFP registers and the rest of this loop
3623 iteration is skipped for this argument, or it goes on the
3624 stack (and the stack alignment code is correct for this
3626 may_use_core_reg = 0;
3628 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3629 shift = unit_length / 4;
3630 mask = (1 << (shift * vfp_base_count)) - 1;
3631 for (regno = 0; regno < 16; regno += shift)
3632 if (((vfp_regs_free >> regno) & mask) == mask)
3641 vfp_regs_free &= ~(mask << regno);
3642 reg_scaled = regno / shift;
3643 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3644 for (i = 0; i < vfp_base_count; i++)
3648 if (reg_char == 'q')
3649 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3650 val + i * unit_length);
3653 sprintf (name_buf, "%c%d", reg_char, reg_scaled + i);
3654 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3656 regcache_cooked_write (regcache, regnum,
3657 val + i * unit_length);
3664 /* This CPRC could not go in VFP registers, so all VFP
3665 registers are now marked as used. */
3670 /* Push stack padding for dowubleword alignment. */
3671 if (nstack & (align - 1))
3673 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3674 nstack += INT_REGISTER_SIZE;
3677 /* Doubleword aligned quantities must go in even register pairs. */
3678 if (may_use_core_reg
3679 && argreg <= ARM_LAST_ARG_REGNUM
3680 && align > INT_REGISTER_SIZE
3684 /* If the argument is a pointer to a function, and it is a
3685 Thumb function, create a LOCAL copy of the value and set
3686 the THUMB bit in it. */
3687 if (TYPE_CODE_PTR == typecode
3688 && target_type != NULL
3689 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3691 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3692 if (arm_pc_is_thumb (gdbarch, regval))
3694 bfd_byte *copy = alloca (len);
3695 store_unsigned_integer (copy, len, byte_order,
3696 MAKE_THUMB_ADDR (regval));
3701 /* Copy the argument to general registers or the stack in
3702 register-sized pieces. Large arguments are split between
3703 registers and stack. */
3706 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3708 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3710 /* The argument is being passed in a general purpose
3713 = extract_unsigned_integer (val, partial_len, byte_order);
3714 if (byte_order == BFD_ENDIAN_BIG)
3715 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3717 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3719 gdbarch_register_name
3721 phex (regval, INT_REGISTER_SIZE));
3722 regcache_cooked_write_unsigned (regcache, argreg, regval);
3727 /* Push the arguments onto the stack. */
3729 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3731 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3732 nstack += INT_REGISTER_SIZE;
3739 /* If we have an odd number of words to push, then decrement the stack
3740 by one word now, so first stack argument will be dword aligned. */
3747 write_memory (sp, si->data, si->len);
3748 si = pop_stack_item (si);
3751 /* Finally, update teh SP register. */
3752 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3758 /* Always align the frame to an 8-byte boundary. This is required on
3759 some platforms and harmless on the rest. */
3762 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3764 /* Align the stack to eight bytes. */
3765 return sp & ~ (CORE_ADDR) 7;
3769 print_fpu_flags (int flags)
3771 if (flags & (1 << 0))
3772 fputs ("IVO ", stdout);
3773 if (flags & (1 << 1))
3774 fputs ("DVZ ", stdout);
3775 if (flags & (1 << 2))
3776 fputs ("OFL ", stdout);
3777 if (flags & (1 << 3))
3778 fputs ("UFL ", stdout);
3779 if (flags & (1 << 4))
3780 fputs ("INX ", stdout);
3784 /* Print interesting information about the floating point processor
3785 (if present) or emulator. */
3787 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3788 struct frame_info *frame, const char *args)
3790 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3793 type = (status >> 24) & 127;
3794 if (status & (1 << 31))
3795 printf (_("Hardware FPU type %d\n"), type);
3797 printf (_("Software FPU type %d\n"), type);
3798 /* i18n: [floating point unit] mask */
3799 fputs (_("mask: "), stdout);
3800 print_fpu_flags (status >> 16);
3801 /* i18n: [floating point unit] flags */
3802 fputs (_("flags: "), stdout);
3803 print_fpu_flags (status);
3806 /* Construct the ARM extended floating point type. */
3807 static struct type *
3808 arm_ext_type (struct gdbarch *gdbarch)
3810 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3812 if (!tdep->arm_ext_type)
3814 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3815 floatformats_arm_ext);
3817 return tdep->arm_ext_type;
3820 static struct type *
3821 arm_neon_double_type (struct gdbarch *gdbarch)
3823 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3825 if (tdep->neon_double_type == NULL)
3827 struct type *t, *elem;
3829 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3831 elem = builtin_type (gdbarch)->builtin_uint8;
3832 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3833 elem = builtin_type (gdbarch)->builtin_uint16;
3834 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3835 elem = builtin_type (gdbarch)->builtin_uint32;
3836 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3837 elem = builtin_type (gdbarch)->builtin_uint64;
3838 append_composite_type_field (t, "u64", elem);
3839 elem = builtin_type (gdbarch)->builtin_float;
3840 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3841 elem = builtin_type (gdbarch)->builtin_double;
3842 append_composite_type_field (t, "f64", elem);
3844 TYPE_VECTOR (t) = 1;
3845 TYPE_NAME (t) = "neon_d";
3846 tdep->neon_double_type = t;
3849 return tdep->neon_double_type;
3852 /* FIXME: The vector types are not correctly ordered on big-endian
3853 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3854 bits of d0 - regardless of what unit size is being held in d0. So
3855 the offset of the first uint8 in d0 is 7, but the offset of the
3856 first float is 4. This code works as-is for little-endian
3859 static struct type *
3860 arm_neon_quad_type (struct gdbarch *gdbarch)
3862 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3864 if (tdep->neon_quad_type == NULL)
3866 struct type *t, *elem;
3868 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3870 elem = builtin_type (gdbarch)->builtin_uint8;
3871 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3872 elem = builtin_type (gdbarch)->builtin_uint16;
3873 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3874 elem = builtin_type (gdbarch)->builtin_uint32;
3875 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3876 elem = builtin_type (gdbarch)->builtin_uint64;
3877 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
3878 elem = builtin_type (gdbarch)->builtin_float;
3879 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
3880 elem = builtin_type (gdbarch)->builtin_double;
3881 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
3883 TYPE_VECTOR (t) = 1;
3884 TYPE_NAME (t) = "neon_q";
3885 tdep->neon_quad_type = t;
3888 return tdep->neon_quad_type;
3891 /* Return the GDB type object for the "standard" data type of data in
3894 static struct type *
3895 arm_register_type (struct gdbarch *gdbarch, int regnum)
3897 int num_regs = gdbarch_num_regs (gdbarch);
3899 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
3900 && regnum >= num_regs && regnum < num_regs + 32)
3901 return builtin_type (gdbarch)->builtin_float;
3903 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
3904 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
3905 return arm_neon_quad_type (gdbarch);
3907 /* If the target description has register information, we are only
3908 in this function so that we can override the types of
3909 double-precision registers for NEON. */
3910 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
3912 struct type *t = tdesc_register_type (gdbarch, regnum);
3914 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
3915 && TYPE_CODE (t) == TYPE_CODE_FLT
3916 && gdbarch_tdep (gdbarch)->have_neon)
3917 return arm_neon_double_type (gdbarch);
3922 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
3924 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
3925 return builtin_type (gdbarch)->builtin_void;
3927 return arm_ext_type (gdbarch);
3929 else if (regnum == ARM_SP_REGNUM)
3930 return builtin_type (gdbarch)->builtin_data_ptr;
3931 else if (regnum == ARM_PC_REGNUM)
3932 return builtin_type (gdbarch)->builtin_func_ptr;
3933 else if (regnum >= ARRAY_SIZE (arm_register_names))
3934 /* These registers are only supported on targets which supply
3935 an XML description. */
3936 return builtin_type (gdbarch)->builtin_int0;
3938 return builtin_type (gdbarch)->builtin_uint32;
3941 /* Map a DWARF register REGNUM onto the appropriate GDB register
3945 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3947 /* Core integer regs. */
3948 if (reg >= 0 && reg <= 15)
3951 /* Legacy FPA encoding. These were once used in a way which
3952 overlapped with VFP register numbering, so their use is
3953 discouraged, but GDB doesn't support the ARM toolchain
3954 which used them for VFP. */
3955 if (reg >= 16 && reg <= 23)
3956 return ARM_F0_REGNUM + reg - 16;
3958 /* New assignments for the FPA registers. */
3959 if (reg >= 96 && reg <= 103)
3960 return ARM_F0_REGNUM + reg - 96;
3962 /* WMMX register assignments. */
3963 if (reg >= 104 && reg <= 111)
3964 return ARM_WCGR0_REGNUM + reg - 104;
3966 if (reg >= 112 && reg <= 127)
3967 return ARM_WR0_REGNUM + reg - 112;
3969 if (reg >= 192 && reg <= 199)
3970 return ARM_WC0_REGNUM + reg - 192;
3972 /* VFP v2 registers. A double precision value is actually
3973 in d1 rather than s2, but the ABI only defines numbering
3974 for the single precision registers. This will "just work"
3975 in GDB for little endian targets (we'll read eight bytes,
3976 starting in s0 and then progressing to s1), but will be
3977 reversed on big endian targets with VFP. This won't
3978 be a problem for the new Neon quad registers; you're supposed
3979 to use DW_OP_piece for those. */
3980 if (reg >= 64 && reg <= 95)
3984 sprintf (name_buf, "s%d", reg - 64);
3985 return user_reg_map_name_to_regnum (gdbarch, name_buf,
3989 /* VFP v3 / Neon registers. This range is also used for VFP v2
3990 registers, except that it now describes d0 instead of s0. */
3991 if (reg >= 256 && reg <= 287)
3995 sprintf (name_buf, "d%d", reg - 256);
3996 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4003 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4005 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4008 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4010 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4011 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4013 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4014 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4016 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4017 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4019 if (reg < NUM_GREGS)
4020 return SIM_ARM_R0_REGNUM + reg;
4023 if (reg < NUM_FREGS)
4024 return SIM_ARM_FP0_REGNUM + reg;
4027 if (reg < NUM_SREGS)
4028 return SIM_ARM_FPS_REGNUM + reg;
4031 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4034 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4035 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4036 It is thought that this is is the floating-point register format on
4037 little-endian systems. */
4040 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4041 void *dbl, int endianess)
4045 if (endianess == BFD_ENDIAN_BIG)
4046 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4048 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4050 floatformat_from_doublest (fmt, &d, dbl);
4054 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4059 floatformat_to_doublest (fmt, ptr, &d);
4060 if (endianess == BFD_ENDIAN_BIG)
4061 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4063 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4068 condition_true (unsigned long cond, unsigned long status_reg)
4070 if (cond == INST_AL || cond == INST_NV)
4076 return ((status_reg & FLAG_Z) != 0);
4078 return ((status_reg & FLAG_Z) == 0);
4080 return ((status_reg & FLAG_C) != 0);
4082 return ((status_reg & FLAG_C) == 0);
4084 return ((status_reg & FLAG_N) != 0);
4086 return ((status_reg & FLAG_N) == 0);
4088 return ((status_reg & FLAG_V) != 0);
4090 return ((status_reg & FLAG_V) == 0);
4092 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4094 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4096 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4098 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4100 return (((status_reg & FLAG_Z) == 0)
4101 && (((status_reg & FLAG_N) == 0)
4102 == ((status_reg & FLAG_V) == 0)));
4104 return (((status_reg & FLAG_Z) != 0)
4105 || (((status_reg & FLAG_N) == 0)
4106 != ((status_reg & FLAG_V) == 0)));
4111 static unsigned long
4112 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4113 unsigned long pc_val, unsigned long status_reg)
4115 unsigned long res, shift;
4116 int rm = bits (inst, 0, 3);
4117 unsigned long shifttype = bits (inst, 5, 6);
4121 int rs = bits (inst, 8, 11);
4122 shift = (rs == 15 ? pc_val + 8
4123 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4126 shift = bits (inst, 7, 11);
4128 res = (rm == ARM_PC_REGNUM
4129 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4130 : get_frame_register_unsigned (frame, rm));
4135 res = shift >= 32 ? 0 : res << shift;
4139 res = shift >= 32 ? 0 : res >> shift;
4145 res = ((res & 0x80000000L)
4146 ? ~((~res) >> shift) : res >> shift);
4149 case 3: /* ROR/RRX */
4152 res = (res >> 1) | (carry ? 0x80000000L : 0);
4154 res = (res >> shift) | (res << (32 - shift));
4158 return res & 0xffffffff;
4161 /* Return number of 1-bits in VAL. */
4164 bitcount (unsigned long val)
4167 for (nbits = 0; val != 0; nbits++)
4168 val &= val - 1; /* Delete rightmost 1-bit in val. */
4172 /* Return the size in bytes of the complete Thumb instruction whose
4173 first halfword is INST1. */
4176 thumb_insn_size (unsigned short inst1)
4178 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4185 thumb_advance_itstate (unsigned int itstate)
4187 /* Preserve IT[7:5], the first three bits of the condition. Shift
4188 the upcoming condition flags left by one bit. */
4189 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4191 /* If we have finished the IT block, clear the state. */
4192 if ((itstate & 0x0f) == 0)
4198 /* Find the next PC after the current instruction executes. In some
4199 cases we can not statically determine the answer (see the IT state
4200 handling in this function); in that case, a breakpoint may be
4201 inserted in addition to the returned PC, which will be used to set
4202 another breakpoint by our caller. */
4205 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4207 struct gdbarch *gdbarch = get_frame_arch (frame);
4208 struct address_space *aspace = get_frame_address_space (frame);
4209 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4210 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4211 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4212 unsigned short inst1;
4213 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4214 unsigned long offset;
4215 ULONGEST status, itstate;
4217 nextpc = MAKE_THUMB_ADDR (nextpc);
4218 pc_val = MAKE_THUMB_ADDR (pc_val);
4220 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4222 /* Thumb-2 conditional execution support. There are eight bits in
4223 the CPSR which describe conditional execution state. Once
4224 reconstructed (they're in a funny order), the low five bits
4225 describe the low bit of the condition for each instruction and
4226 how many instructions remain. The high three bits describe the
4227 base condition. One of the low four bits will be set if an IT
4228 block is active. These bits read as zero on earlier
4230 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4231 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4233 /* If-Then handling. On GNU/Linux, where this routine is used, we
4234 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4235 can disable execution of the undefined instruction. So we might
4236 miss the breakpoint if we set it on a skipped conditional
4237 instruction. Because conditional instructions can change the
4238 flags, affecting the execution of further instructions, we may
4239 need to set two breakpoints. */
4241 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4243 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4245 /* An IT instruction. Because this instruction does not
4246 modify the flags, we can accurately predict the next
4247 executed instruction. */
4248 itstate = inst1 & 0x00ff;
4249 pc += thumb_insn_size (inst1);
4251 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4253 inst1 = read_memory_unsigned_integer (pc, 2,
4254 byte_order_for_code);
4255 pc += thumb_insn_size (inst1);
4256 itstate = thumb_advance_itstate (itstate);
4259 return MAKE_THUMB_ADDR (pc);
4261 else if (itstate != 0)
4263 /* We are in a conditional block. Check the condition. */
4264 if (! condition_true (itstate >> 4, status))
4266 /* Advance to the next executed instruction. */
4267 pc += thumb_insn_size (inst1);
4268 itstate = thumb_advance_itstate (itstate);
4270 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4272 inst1 = read_memory_unsigned_integer (pc, 2,
4273 byte_order_for_code);
4274 pc += thumb_insn_size (inst1);
4275 itstate = thumb_advance_itstate (itstate);
4278 return MAKE_THUMB_ADDR (pc);
4280 else if ((itstate & 0x0f) == 0x08)
4282 /* This is the last instruction of the conditional
4283 block, and it is executed. We can handle it normally
4284 because the following instruction is not conditional,
4285 and we must handle it normally because it is
4286 permitted to branch. Fall through. */
4292 /* There are conditional instructions after this one.
4293 If this instruction modifies the flags, then we can
4294 not predict what the next executed instruction will
4295 be. Fortunately, this instruction is architecturally
4296 forbidden to branch; we know it will fall through.
4297 Start by skipping past it. */
4298 pc += thumb_insn_size (inst1);
4299 itstate = thumb_advance_itstate (itstate);
4301 /* Set a breakpoint on the following instruction. */
4302 gdb_assert ((itstate & 0x0f) != 0);
4303 arm_insert_single_step_breakpoint (gdbarch, aspace,
4304 MAKE_THUMB_ADDR (pc));
4305 cond_negated = (itstate >> 4) & 1;
4307 /* Skip all following instructions with the same
4308 condition. If there is a later instruction in the IT
4309 block with the opposite condition, set the other
4310 breakpoint there. If not, then set a breakpoint on
4311 the instruction after the IT block. */
4314 inst1 = read_memory_unsigned_integer (pc, 2,
4315 byte_order_for_code);
4316 pc += thumb_insn_size (inst1);
4317 itstate = thumb_advance_itstate (itstate);
4319 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4321 return MAKE_THUMB_ADDR (pc);
4325 else if (itstate & 0x0f)
4327 /* We are in a conditional block. Check the condition. */
4328 int cond = itstate >> 4;
4330 if (! condition_true (cond, status))
4331 /* Advance to the next instruction. All the 32-bit
4332 instructions share a common prefix. */
4333 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4335 /* Otherwise, handle the instruction normally. */
4338 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4342 /* Fetch the saved PC from the stack. It's stored above
4343 all of the other registers. */
4344 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4345 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4346 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4348 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4350 unsigned long cond = bits (inst1, 8, 11);
4351 if (cond == 0x0f) /* 0x0f = SWI */
4353 struct gdbarch_tdep *tdep;
4354 tdep = gdbarch_tdep (gdbarch);
4356 if (tdep->syscall_next_pc != NULL)
4357 nextpc = tdep->syscall_next_pc (frame);
4360 else if (cond != 0x0f && condition_true (cond, status))
4361 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4363 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4365 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4367 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4369 unsigned short inst2;
4370 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4372 /* Default to the next instruction. */
4374 nextpc = MAKE_THUMB_ADDR (nextpc);
4376 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4378 /* Branches and miscellaneous control instructions. */
4380 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4383 int j1, j2, imm1, imm2;
4385 imm1 = sbits (inst1, 0, 10);
4386 imm2 = bits (inst2, 0, 10);
4387 j1 = bit (inst2, 13);
4388 j2 = bit (inst2, 11);
4390 offset = ((imm1 << 12) + (imm2 << 1));
4391 offset ^= ((!j2) << 22) | ((!j1) << 23);
4393 nextpc = pc_val + offset;
4394 /* For BLX make sure to clear the low bits. */
4395 if (bit (inst2, 12) == 0)
4396 nextpc = nextpc & 0xfffffffc;
4398 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4400 /* SUBS PC, LR, #imm8. */
4401 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4402 nextpc -= inst2 & 0x00ff;
4404 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4406 /* Conditional branch. */
4407 if (condition_true (bits (inst1, 6, 9), status))
4409 int sign, j1, j2, imm1, imm2;
4411 sign = sbits (inst1, 10, 10);
4412 imm1 = bits (inst1, 0, 5);
4413 imm2 = bits (inst2, 0, 10);
4414 j1 = bit (inst2, 13);
4415 j2 = bit (inst2, 11);
4417 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4418 offset += (imm1 << 12) + (imm2 << 1);
4420 nextpc = pc_val + offset;
4424 else if ((inst1 & 0xfe50) == 0xe810)
4426 /* Load multiple or RFE. */
4427 int rn, offset, load_pc = 1;
4429 rn = bits (inst1, 0, 3);
4430 if (bit (inst1, 7) && !bit (inst1, 8))
4433 if (!bit (inst2, 15))
4435 offset = bitcount (inst2) * 4 - 4;
4437 else if (!bit (inst1, 7) && bit (inst1, 8))
4440 if (!bit (inst2, 15))
4444 else if (bit (inst1, 7) && bit (inst1, 8))
4449 else if (!bit (inst1, 7) && !bit (inst1, 8))
4459 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4460 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4463 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4465 /* MOV PC or MOVS PC. */
4466 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4467 nextpc = MAKE_THUMB_ADDR (nextpc);
4469 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4473 int rn, load_pc = 1;
4475 rn = bits (inst1, 0, 3);
4476 base = get_frame_register_unsigned (frame, rn);
4477 if (rn == ARM_PC_REGNUM)
4479 base = (base + 4) & ~(CORE_ADDR) 0x3;
4481 base += bits (inst2, 0, 11);
4483 base -= bits (inst2, 0, 11);
4485 else if (bit (inst1, 7))
4486 base += bits (inst2, 0, 11);
4487 else if (bit (inst2, 11))
4489 if (bit (inst2, 10))
4492 base += bits (inst2, 0, 7);
4494 base -= bits (inst2, 0, 7);
4497 else if ((inst2 & 0x0fc0) == 0x0000)
4499 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4500 base += get_frame_register_unsigned (frame, rm) << shift;
4507 nextpc = get_frame_memory_unsigned (frame, base, 4);
4509 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4512 CORE_ADDR tbl_reg, table, offset, length;
4514 tbl_reg = bits (inst1, 0, 3);
4515 if (tbl_reg == 0x0f)
4516 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4518 table = get_frame_register_unsigned (frame, tbl_reg);
4520 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4521 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4522 nextpc = pc_val + length;
4524 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4527 CORE_ADDR tbl_reg, table, offset, length;
4529 tbl_reg = bits (inst1, 0, 3);
4530 if (tbl_reg == 0x0f)
4531 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4533 table = get_frame_register_unsigned (frame, tbl_reg);
4535 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4536 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4537 nextpc = pc_val + length;
4540 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4542 if (bits (inst1, 3, 6) == 0x0f)
4545 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4547 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4549 if (bits (inst1, 3, 6) == 0x0f)
4552 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4554 nextpc = MAKE_THUMB_ADDR (nextpc);
4556 else if ((inst1 & 0xf500) == 0xb100)
4559 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4560 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4562 if (bit (inst1, 11) && reg != 0)
4563 nextpc = pc_val + imm;
4564 else if (!bit (inst1, 11) && reg == 0)
4565 nextpc = pc_val + imm;
4570 /* Get the raw next address. PC is the current program counter, in
4571 FRAME, which is assumed to be executing in ARM mode.
4573 The value returned has the execution state of the next instruction
4574 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4575 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4579 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4581 struct gdbarch *gdbarch = get_frame_arch (frame);
4582 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4583 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4584 unsigned long pc_val;
4585 unsigned long this_instr;
4586 unsigned long status;
4589 pc_val = (unsigned long) pc;
4590 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4592 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4593 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4595 if (bits (this_instr, 28, 31) == INST_NV)
4596 switch (bits (this_instr, 24, 27))
4601 /* Branch with Link and change to Thumb. */
4602 nextpc = BranchDest (pc, this_instr);
4603 nextpc |= bit (this_instr, 24) << 1;
4604 nextpc = MAKE_THUMB_ADDR (nextpc);
4610 /* Coprocessor register transfer. */
4611 if (bits (this_instr, 12, 15) == 15)
4612 error (_("Invalid update to pc in instruction"));
4615 else if (condition_true (bits (this_instr, 28, 31), status))
4617 switch (bits (this_instr, 24, 27))
4620 case 0x1: /* data processing */
4624 unsigned long operand1, operand2, result = 0;
4628 if (bits (this_instr, 12, 15) != 15)
4631 if (bits (this_instr, 22, 25) == 0
4632 && bits (this_instr, 4, 7) == 9) /* multiply */
4633 error (_("Invalid update to pc in instruction"));
4635 /* BX <reg>, BLX <reg> */
4636 if (bits (this_instr, 4, 27) == 0x12fff1
4637 || bits (this_instr, 4, 27) == 0x12fff3)
4639 rn = bits (this_instr, 0, 3);
4640 nextpc = ((rn == ARM_PC_REGNUM)
4642 : get_frame_register_unsigned (frame, rn));
4647 /* Multiply into PC. */
4648 c = (status & FLAG_C) ? 1 : 0;
4649 rn = bits (this_instr, 16, 19);
4650 operand1 = ((rn == ARM_PC_REGNUM)
4652 : get_frame_register_unsigned (frame, rn));
4654 if (bit (this_instr, 25))
4656 unsigned long immval = bits (this_instr, 0, 7);
4657 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4658 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4661 else /* operand 2 is a shifted register. */
4662 operand2 = shifted_reg_val (frame, this_instr, c,
4665 switch (bits (this_instr, 21, 24))
4668 result = operand1 & operand2;
4672 result = operand1 ^ operand2;
4676 result = operand1 - operand2;
4680 result = operand2 - operand1;
4684 result = operand1 + operand2;
4688 result = operand1 + operand2 + c;
4692 result = operand1 - operand2 + c;
4696 result = operand2 - operand1 + c;
4702 case 0xb: /* tst, teq, cmp, cmn */
4703 result = (unsigned long) nextpc;
4707 result = operand1 | operand2;
4711 /* Always step into a function. */
4716 result = operand1 & ~operand2;
4724 /* In 26-bit APCS the bottom two bits of the result are
4725 ignored, and we always end up in ARM state. */
4727 nextpc = arm_addr_bits_remove (gdbarch, result);
4735 case 0x5: /* data transfer */
4738 if (bit (this_instr, 20))
4741 if (bits (this_instr, 12, 15) == 15)
4747 if (bit (this_instr, 22))
4748 error (_("Invalid update to pc in instruction"));
4750 /* byte write to PC */
4751 rn = bits (this_instr, 16, 19);
4752 base = ((rn == ARM_PC_REGNUM)
4754 : get_frame_register_unsigned (frame, rn));
4756 if (bit (this_instr, 24))
4759 int c = (status & FLAG_C) ? 1 : 0;
4760 unsigned long offset =
4761 (bit (this_instr, 25)
4762 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4763 : bits (this_instr, 0, 11));
4765 if (bit (this_instr, 23))
4771 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4778 case 0x9: /* block transfer */
4779 if (bit (this_instr, 20))
4782 if (bit (this_instr, 15))
4786 unsigned long rn_val
4787 = get_frame_register_unsigned (frame,
4788 bits (this_instr, 16, 19));
4790 if (bit (this_instr, 23))
4793 unsigned long reglist = bits (this_instr, 0, 14);
4794 offset = bitcount (reglist) * 4;
4795 if (bit (this_instr, 24)) /* pre */
4798 else if (bit (this_instr, 24))
4802 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
4809 case 0xb: /* branch & link */
4810 case 0xa: /* branch */
4812 nextpc = BranchDest (pc, this_instr);
4818 case 0xe: /* coproc ops */
4822 struct gdbarch_tdep *tdep;
4823 tdep = gdbarch_tdep (gdbarch);
4825 if (tdep->syscall_next_pc != NULL)
4826 nextpc = tdep->syscall_next_pc (frame);
4832 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4840 /* Determine next PC after current instruction executes. Will call either
4841 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4842 loop is detected. */
4845 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4849 if (arm_frame_is_thumb (frame))
4851 nextpc = thumb_get_next_pc_raw (frame, pc);
4852 if (nextpc == MAKE_THUMB_ADDR (pc))
4853 error (_("Infinite loop detected"));
4857 nextpc = arm_get_next_pc_raw (frame, pc);
4859 error (_("Infinite loop detected"));
4865 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4866 of the appropriate mode (as encoded in the PC value), even if this
4867 differs from what would be expected according to the symbol tables. */
4870 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
4871 struct address_space *aspace,
4874 struct cleanup *old_chain
4875 = make_cleanup_restore_integer (&arm_override_mode);
4877 arm_override_mode = IS_THUMB_ADDR (pc);
4878 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4880 insert_single_step_breakpoint (gdbarch, aspace, pc);
4882 do_cleanups (old_chain);
4885 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
4886 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
4887 is found, attempt to step through it. A breakpoint is placed at the end of
4891 thumb_deal_with_atomic_sequence_raw (struct frame_info *frame)
4893 struct gdbarch *gdbarch = get_frame_arch (frame);
4894 struct address_space *aspace = get_frame_address_space (frame);
4895 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4896 CORE_ADDR pc = get_frame_pc (frame);
4897 CORE_ADDR breaks[2] = {-1, -1};
4899 unsigned short insn1, insn2;
4902 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
4903 const int atomic_sequence_length = 16; /* Instruction sequence length. */
4904 ULONGEST status, itstate;
4906 /* We currently do not support atomic sequences within an IT block. */
4907 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4908 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4912 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
4913 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
4915 if (thumb_insn_size (insn1) != 4)
4918 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
4920 if (!((insn1 & 0xfff0) == 0xe850
4921 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
4924 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
4926 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
4928 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
4931 if (thumb_insn_size (insn1) != 4)
4933 /* Assume that there is at most one conditional branch in the
4934 atomic sequence. If a conditional branch is found, put a
4935 breakpoint in its destination address. */
4936 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
4938 if (last_breakpoint > 0)
4939 return 0; /* More than one conditional branch found,
4940 fallback to the standard code. */
4942 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
4946 /* We do not support atomic sequences that use any *other*
4947 instructions but conditional branches to change the PC.
4948 Fall back to standard code to avoid losing control of
4950 else if (thumb_instruction_changes_pc (insn1))
4955 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
4958 /* Assume that there is at most one conditional branch in the
4959 atomic sequence. If a conditional branch is found, put a
4960 breakpoint in its destination address. */
4961 if ((insn1 & 0xf800) == 0xf000
4962 && (insn2 & 0xd000) == 0x8000
4963 && (insn1 & 0x0380) != 0x0380)
4965 int sign, j1, j2, imm1, imm2;
4966 unsigned int offset;
4968 sign = sbits (insn1, 10, 10);
4969 imm1 = bits (insn1, 0, 5);
4970 imm2 = bits (insn2, 0, 10);
4971 j1 = bit (insn2, 13);
4972 j2 = bit (insn2, 11);
4974 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4975 offset += (imm1 << 12) + (imm2 << 1);
4977 if (last_breakpoint > 0)
4978 return 0; /* More than one conditional branch found,
4979 fallback to the standard code. */
4981 breaks[1] = loc + offset;
4985 /* We do not support atomic sequences that use any *other*
4986 instructions but conditional branches to change the PC.
4987 Fall back to standard code to avoid losing control of
4989 else if (thumb2_instruction_changes_pc (insn1, insn2))
4992 /* If we find a strex{,b,h,d}, we're done. */
4993 if ((insn1 & 0xfff0) == 0xe840
4994 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
4999 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5000 if (insn_count == atomic_sequence_length)
5003 /* Insert a breakpoint right after the end of the atomic sequence. */
5006 /* Check for duplicated breakpoints. Check also for a breakpoint
5007 placed (branch instruction's destination) anywhere in sequence. */
5009 && (breaks[1] == breaks[0]
5010 || (breaks[1] >= pc && breaks[1] < loc)))
5011 last_breakpoint = 0;
5013 /* Effectively inserts the breakpoints. */
5014 for (index = 0; index <= last_breakpoint; index++)
5015 arm_insert_single_step_breakpoint (gdbarch, aspace,
5016 MAKE_THUMB_ADDR (breaks[index]));
5022 arm_deal_with_atomic_sequence_raw (struct frame_info *frame)
5024 struct gdbarch *gdbarch = get_frame_arch (frame);
5025 struct address_space *aspace = get_frame_address_space (frame);
5026 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5027 CORE_ADDR pc = get_frame_pc (frame);
5028 CORE_ADDR breaks[2] = {-1, -1};
5033 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5034 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5036 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5037 Note that we do not currently support conditionally executed atomic
5039 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5041 if ((insn & 0xff9000f0) != 0xe1900090)
5044 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5046 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5048 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5051 /* Assume that there is at most one conditional branch in the atomic
5052 sequence. If a conditional branch is found, put a breakpoint in
5053 its destination address. */
5054 if (bits (insn, 24, 27) == 0xa)
5056 if (last_breakpoint > 0)
5057 return 0; /* More than one conditional branch found, fallback
5058 to the standard single-step code. */
5060 breaks[1] = BranchDest (loc - 4, insn);
5064 /* We do not support atomic sequences that use any *other* instructions
5065 but conditional branches to change the PC. Fall back to standard
5066 code to avoid losing control of execution. */
5067 else if (arm_instruction_changes_pc (insn))
5070 /* If we find a strex{,b,h,d}, we're done. */
5071 if ((insn & 0xff9000f0) == 0xe1800090)
5075 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5076 if (insn_count == atomic_sequence_length)
5079 /* Insert a breakpoint right after the end of the atomic sequence. */
5082 /* Check for duplicated breakpoints. Check also for a breakpoint
5083 placed (branch instruction's destination) anywhere in sequence. */
5085 && (breaks[1] == breaks[0]
5086 || (breaks[1] >= pc && breaks[1] < loc)))
5087 last_breakpoint = 0;
5089 /* Effectively inserts the breakpoints. */
5090 for (index = 0; index <= last_breakpoint; index++)
5091 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5097 arm_deal_with_atomic_sequence (struct frame_info *frame)
5099 if (arm_frame_is_thumb (frame))
5100 return thumb_deal_with_atomic_sequence_raw (frame);
5102 return arm_deal_with_atomic_sequence_raw (frame);
5105 /* single_step() is called just before we want to resume the inferior,
5106 if we want to single-step it but there is no hardware or kernel
5107 single-step support. We find the target of the coming instruction
5108 and breakpoint it. */
5111 arm_software_single_step (struct frame_info *frame)
5113 struct gdbarch *gdbarch = get_frame_arch (frame);
5114 struct address_space *aspace = get_frame_address_space (frame);
5117 if (arm_deal_with_atomic_sequence (frame))
5120 next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
5121 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5126 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5127 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5128 NULL if an error occurs. BUF is freed. */
5131 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5132 int old_len, int new_len)
5135 int bytes_to_read = new_len - old_len;
5137 new_buf = xmalloc (new_len);
5138 memcpy (new_buf + bytes_to_read, buf, old_len);
5140 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5148 /* An IT block is at most the 2-byte IT instruction followed by
5149 four 4-byte instructions. The furthest back we must search to
5150 find an IT block that affects the current instruction is thus
5151 2 + 3 * 4 == 14 bytes. */
5152 #define MAX_IT_BLOCK_PREFIX 14
5154 /* Use a quick scan if there are more than this many bytes of
5156 #define IT_SCAN_THRESHOLD 32
5158 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5159 A breakpoint in an IT block may not be hit, depending on the
5162 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5166 CORE_ADDR boundary, func_start;
5168 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5169 int i, any, last_it, last_it_count;
5171 /* If we are using BKPT breakpoints, none of this is necessary. */
5172 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5175 /* ARM mode does not have this problem. */
5176 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5179 /* We are setting a breakpoint in Thumb code that could potentially
5180 contain an IT block. The first step is to find how much Thumb
5181 code there is; we do not need to read outside of known Thumb
5183 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5185 /* Thumb-2 code must have mapping symbols to have a chance. */
5188 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5190 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5191 && func_start > boundary)
5192 boundary = func_start;
5194 /* Search for a candidate IT instruction. We have to do some fancy
5195 footwork to distinguish a real IT instruction from the second
5196 half of a 32-bit instruction, but there is no need for that if
5197 there's no candidate. */
5198 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5200 /* No room for an IT instruction. */
5203 buf = xmalloc (buf_len);
5204 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5207 for (i = 0; i < buf_len; i += 2)
5209 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5210 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5222 /* OK, the code bytes before this instruction contain at least one
5223 halfword which resembles an IT instruction. We know that it's
5224 Thumb code, but there are still two possibilities. Either the
5225 halfword really is an IT instruction, or it is the second half of
5226 a 32-bit Thumb instruction. The only way we can tell is to
5227 scan forwards from a known instruction boundary. */
5228 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5232 /* There's a lot of code before this instruction. Start with an
5233 optimistic search; it's easy to recognize halfwords that can
5234 not be the start of a 32-bit instruction, and use that to
5235 lock on to the instruction boundaries. */
5236 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5239 buf_len = IT_SCAN_THRESHOLD;
5242 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5244 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5245 if (thumb_insn_size (inst1) == 2)
5252 /* At this point, if DEFINITE, BUF[I] is the first place we
5253 are sure that we know the instruction boundaries, and it is far
5254 enough from BPADDR that we could not miss an IT instruction
5255 affecting BPADDR. If ! DEFINITE, give up - start from a
5259 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5263 buf_len = bpaddr - boundary;
5269 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5272 buf_len = bpaddr - boundary;
5276 /* Scan forwards. Find the last IT instruction before BPADDR. */
5281 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5283 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5288 else if (inst1 & 0x0002)
5290 else if (inst1 & 0x0004)
5295 i += thumb_insn_size (inst1);
5301 /* There wasn't really an IT instruction after all. */
5304 if (last_it_count < 1)
5305 /* It was too far away. */
5308 /* This really is a trouble spot. Move the breakpoint to the IT
5310 return bpaddr - buf_len + last_it;
5313 /* ARM displaced stepping support.
5315 Generally ARM displaced stepping works as follows:
5317 1. When an instruction is to be single-stepped, it is first decoded by
5318 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5319 Depending on the type of instruction, it is then copied to a scratch
5320 location, possibly in a modified form. The copy_* set of functions
5321 performs such modification, as necessary. A breakpoint is placed after
5322 the modified instruction in the scratch space to return control to GDB.
5323 Note in particular that instructions which modify the PC will no longer
5324 do so after modification.
5326 2. The instruction is single-stepped, by setting the PC to the scratch
5327 location address, and resuming. Control returns to GDB when the
5330 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5331 function used for the current instruction. This function's job is to
5332 put the CPU/memory state back to what it would have been if the
5333 instruction had been executed unmodified in its original location. */
5335 /* NOP instruction (mov r0, r0). */
5336 #define ARM_NOP 0xe1a00000
5337 #define THUMB_NOP 0x4600
5339 /* Helper for register reads for displaced stepping. In particular, this
5340 returns the PC as it would be seen by the instruction at its original
5344 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5348 CORE_ADDR from = dsc->insn_addr;
5350 if (regno == ARM_PC_REGNUM)
5352 /* Compute pipeline offset:
5353 - When executing an ARM instruction, PC reads as the address of the
5354 current instruction plus 8.
5355 - When executing a Thumb instruction, PC reads as the address of the
5356 current instruction plus 4. */
5363 if (debug_displaced)
5364 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5365 (unsigned long) from);
5366 return (ULONGEST) from;
5370 regcache_cooked_read_unsigned (regs, regno, &ret);
5371 if (debug_displaced)
5372 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5373 regno, (unsigned long) ret);
5379 displaced_in_arm_mode (struct regcache *regs)
5382 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5384 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5386 return (ps & t_bit) == 0;
5389 /* Write to the PC as from a branch instruction. */
5392 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5396 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5397 architecture versions < 6. */
5398 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5399 val & ~(ULONGEST) 0x3);
5401 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5402 val & ~(ULONGEST) 0x1);
5405 /* Write to the PC as from a branch-exchange instruction. */
5408 bx_write_pc (struct regcache *regs, ULONGEST val)
5411 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5413 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5417 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5418 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5420 else if ((val & 2) == 0)
5422 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5423 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5427 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5428 mode, align dest to 4 bytes). */
5429 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5430 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5431 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5435 /* Write to the PC as if from a load instruction. */
5438 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5441 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5442 bx_write_pc (regs, val);
5444 branch_write_pc (regs, dsc, val);
5447 /* Write to the PC as if from an ALU instruction. */
5450 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5453 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5454 bx_write_pc (regs, val);
5456 branch_write_pc (regs, dsc, val);
5459 /* Helper for writing to registers for displaced stepping. Writing to the PC
5460 has a varying effects depending on the instruction which does the write:
5461 this is controlled by the WRITE_PC argument. */
5464 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5465 int regno, ULONGEST val, enum pc_write_style write_pc)
5467 if (regno == ARM_PC_REGNUM)
5469 if (debug_displaced)
5470 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5471 (unsigned long) val);
5474 case BRANCH_WRITE_PC:
5475 branch_write_pc (regs, dsc, val);
5479 bx_write_pc (regs, val);
5483 load_write_pc (regs, dsc, val);
5487 alu_write_pc (regs, dsc, val);
5490 case CANNOT_WRITE_PC:
5491 warning (_("Instruction wrote to PC in an unexpected way when "
5492 "single-stepping"));
5496 internal_error (__FILE__, __LINE__,
5497 _("Invalid argument to displaced_write_reg"));
5500 dsc->wrote_to_pc = 1;
5504 if (debug_displaced)
5505 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5506 regno, (unsigned long) val);
5507 regcache_cooked_write_unsigned (regs, regno, val);
5511 /* This function is used to concisely determine if an instruction INSN
5512 references PC. Register fields of interest in INSN should have the
5513 corresponding fields of BITMASK set to 0b1111. The function
5514 returns return 1 if any of these fields in INSN reference the PC
5515 (also 0b1111, r15), else it returns 0. */
5518 insn_references_pc (uint32_t insn, uint32_t bitmask)
5520 uint32_t lowbit = 1;
5522 while (bitmask != 0)
5526 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5532 mask = lowbit * 0xf;
5534 if ((insn & mask) == mask)
5543 /* The simplest copy function. Many instructions have the same effect no
5544 matter what address they are executed at: in those cases, use this. */
5547 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5548 const char *iname, struct displaced_step_closure *dsc)
5550 if (debug_displaced)
5551 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5552 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5555 dsc->modinsn[0] = insn;
5561 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5562 uint16_t insn2, const char *iname,
5563 struct displaced_step_closure *dsc)
5565 if (debug_displaced)
5566 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5567 "opcode/class '%s' unmodified\n", insn1, insn2,
5570 dsc->modinsn[0] = insn1;
5571 dsc->modinsn[1] = insn2;
5577 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5580 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5582 struct displaced_step_closure *dsc)
5584 if (debug_displaced)
5585 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5586 "opcode/class '%s' unmodified\n", insn,
5589 dsc->modinsn[0] = insn;
5594 /* Preload instructions with immediate offset. */
5597 cleanup_preload (struct gdbarch *gdbarch,
5598 struct regcache *regs, struct displaced_step_closure *dsc)
5600 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5601 if (!dsc->u.preload.immed)
5602 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5606 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5607 struct displaced_step_closure *dsc, unsigned int rn)
5610 /* Preload instructions:
5612 {pli/pld} [rn, #+/-imm]
5614 {pli/pld} [r0, #+/-imm]. */
5616 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5617 rn_val = displaced_read_reg (regs, dsc, rn);
5618 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5619 dsc->u.preload.immed = 1;
5621 dsc->cleanup = &cleanup_preload;
5625 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5626 struct displaced_step_closure *dsc)
5628 unsigned int rn = bits (insn, 16, 19);
5630 if (!insn_references_pc (insn, 0x000f0000ul))
5631 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5633 if (debug_displaced)
5634 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5635 (unsigned long) insn);
5637 dsc->modinsn[0] = insn & 0xfff0ffff;
5639 install_preload (gdbarch, regs, dsc, rn);
5645 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5646 struct regcache *regs, struct displaced_step_closure *dsc)
5648 unsigned int rn = bits (insn1, 0, 3);
5649 unsigned int u_bit = bit (insn1, 7);
5650 int imm12 = bits (insn2, 0, 11);
5653 if (rn != ARM_PC_REGNUM)
5654 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5656 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5657 PLD (literal) Encoding T1. */
5658 if (debug_displaced)
5659 fprintf_unfiltered (gdb_stdlog,
5660 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5661 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5667 /* Rewrite instruction {pli/pld} PC imm12 into:
5668 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5672 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5674 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5675 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5677 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5679 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5680 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5681 dsc->u.preload.immed = 0;
5683 /* {pli/pld} [r0, r1] */
5684 dsc->modinsn[0] = insn1 & 0xfff0;
5685 dsc->modinsn[1] = 0xf001;
5688 dsc->cleanup = &cleanup_preload;
5692 /* Preload instructions with register offset. */
5695 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5696 struct displaced_step_closure *dsc, unsigned int rn,
5699 ULONGEST rn_val, rm_val;
5701 /* Preload register-offset instructions:
5703 {pli/pld} [rn, rm {, shift}]
5705 {pli/pld} [r0, r1 {, shift}]. */
5707 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5708 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5709 rn_val = displaced_read_reg (regs, dsc, rn);
5710 rm_val = displaced_read_reg (regs, dsc, rm);
5711 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5712 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5713 dsc->u.preload.immed = 0;
5715 dsc->cleanup = &cleanup_preload;
5719 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5720 struct regcache *regs,
5721 struct displaced_step_closure *dsc)
5723 unsigned int rn = bits (insn, 16, 19);
5724 unsigned int rm = bits (insn, 0, 3);
5727 if (!insn_references_pc (insn, 0x000f000ful))
5728 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5730 if (debug_displaced)
5731 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5732 (unsigned long) insn);
5734 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5736 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5740 /* Copy/cleanup coprocessor load and store instructions. */
5743 cleanup_copro_load_store (struct gdbarch *gdbarch,
5744 struct regcache *regs,
5745 struct displaced_step_closure *dsc)
5747 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5749 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5751 if (dsc->u.ldst.writeback)
5752 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5756 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5757 struct displaced_step_closure *dsc,
5758 int writeback, unsigned int rn)
5762 /* Coprocessor load/store instructions:
5764 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5766 {stc/stc2} [r0, #+/-imm].
5768 ldc/ldc2 are handled identically. */
5770 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5771 rn_val = displaced_read_reg (regs, dsc, rn);
5772 /* PC should be 4-byte aligned. */
5773 rn_val = rn_val & 0xfffffffc;
5774 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5776 dsc->u.ldst.writeback = writeback;
5777 dsc->u.ldst.rn = rn;
5779 dsc->cleanup = &cleanup_copro_load_store;
5783 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5784 struct regcache *regs,
5785 struct displaced_step_closure *dsc)
5787 unsigned int rn = bits (insn, 16, 19);
5789 if (!insn_references_pc (insn, 0x000f0000ul))
5790 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5792 if (debug_displaced)
5793 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5794 "load/store insn %.8lx\n", (unsigned long) insn);
5796 dsc->modinsn[0] = insn & 0xfff0ffff;
5798 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5804 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5805 uint16_t insn2, struct regcache *regs,
5806 struct displaced_step_closure *dsc)
5808 unsigned int rn = bits (insn1, 0, 3);
5810 if (rn != ARM_PC_REGNUM)
5811 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5812 "copro load/store", dsc);
5814 if (debug_displaced)
5815 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5816 "load/store insn %.4x%.4x\n", insn1, insn2);
5818 dsc->modinsn[0] = insn1 & 0xfff0;
5819 dsc->modinsn[1] = insn2;
5822 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5823 doesn't support writeback, so pass 0. */
5824 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
5829 /* Clean up branch instructions (actually perform the branch, by setting
5833 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
5834 struct displaced_step_closure *dsc)
5836 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5837 int branch_taken = condition_true (dsc->u.branch.cond, status);
5838 enum pc_write_style write_pc = dsc->u.branch.exchange
5839 ? BX_WRITE_PC : BRANCH_WRITE_PC;
5844 if (dsc->u.branch.link)
5846 /* The value of LR should be the next insn of current one. In order
5847 not to confuse logic hanlding later insn `bx lr', if current insn mode
5848 is Thumb, the bit 0 of LR value should be set to 1. */
5849 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5852 next_insn_addr |= 0x1;
5854 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5858 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5861 /* Copy B/BL/BLX instructions with immediate destinations. */
5864 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
5865 struct displaced_step_closure *dsc,
5866 unsigned int cond, int exchange, int link, long offset)
5868 /* Implement "BL<cond> <label>" as:
5870 Preparation: cond <- instruction condition
5871 Insn: mov r0, r0 (nop)
5872 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5874 B<cond> similar, but don't set r14 in cleanup. */
5876 dsc->u.branch.cond = cond;
5877 dsc->u.branch.link = link;
5878 dsc->u.branch.exchange = exchange;
5880 dsc->u.branch.dest = dsc->insn_addr;
5881 if (link && exchange)
5882 /* For BLX, offset is computed from the Align (PC, 4). */
5883 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
5886 dsc->u.branch.dest += 4 + offset;
5888 dsc->u.branch.dest += 8 + offset;
5890 dsc->cleanup = &cleanup_branch;
5893 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
5894 struct regcache *regs, struct displaced_step_closure *dsc)
5896 unsigned int cond = bits (insn, 28, 31);
5897 int exchange = (cond == 0xf);
5898 int link = exchange || bit (insn, 24);
5901 if (debug_displaced)
5902 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
5903 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
5904 (unsigned long) insn);
5906 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5907 then arrange the switch into Thumb mode. */
5908 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
5910 offset = bits (insn, 0, 23) << 2;
5912 if (bit (offset, 25))
5913 offset = offset | ~0x3ffffff;
5915 dsc->modinsn[0] = ARM_NOP;
5917 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5922 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
5923 uint16_t insn2, struct regcache *regs,
5924 struct displaced_step_closure *dsc)
5926 int link = bit (insn2, 14);
5927 int exchange = link && !bit (insn2, 12);
5930 int j1 = bit (insn2, 13);
5931 int j2 = bit (insn2, 11);
5932 int s = sbits (insn1, 10, 10);
5933 int i1 = !(j1 ^ bit (insn1, 10));
5934 int i2 = !(j2 ^ bit (insn1, 10));
5936 if (!link && !exchange) /* B */
5938 offset = (bits (insn2, 0, 10) << 1);
5939 if (bit (insn2, 12)) /* Encoding T4 */
5941 offset |= (bits (insn1, 0, 9) << 12)
5947 else /* Encoding T3 */
5949 offset |= (bits (insn1, 0, 5) << 12)
5953 cond = bits (insn1, 6, 9);
5958 offset = (bits (insn1, 0, 9) << 12);
5959 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
5960 offset |= exchange ?
5961 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
5964 if (debug_displaced)
5965 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
5966 "%.4x %.4x with offset %.8lx\n",
5967 link ? (exchange) ? "blx" : "bl" : "b",
5968 insn1, insn2, offset);
5970 dsc->modinsn[0] = THUMB_NOP;
5972 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5976 /* Copy B Thumb instructions. */
5978 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
5979 struct displaced_step_closure *dsc)
5981 unsigned int cond = 0;
5983 unsigned short bit_12_15 = bits (insn, 12, 15);
5984 CORE_ADDR from = dsc->insn_addr;
5986 if (bit_12_15 == 0xd)
5988 /* offset = SignExtend (imm8:0, 32) */
5989 offset = sbits ((insn << 1), 0, 8);
5990 cond = bits (insn, 8, 11);
5992 else if (bit_12_15 == 0xe) /* Encoding T2 */
5994 offset = sbits ((insn << 1), 0, 11);
5998 if (debug_displaced)
5999 fprintf_unfiltered (gdb_stdlog,
6000 "displaced: copying b immediate insn %.4x "
6001 "with offset %d\n", insn, offset);
6003 dsc->u.branch.cond = cond;
6004 dsc->u.branch.link = 0;
6005 dsc->u.branch.exchange = 0;
6006 dsc->u.branch.dest = from + 4 + offset;
6008 dsc->modinsn[0] = THUMB_NOP;
6010 dsc->cleanup = &cleanup_branch;
6015 /* Copy BX/BLX with register-specified destinations. */
6018 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6019 struct displaced_step_closure *dsc, int link,
6020 unsigned int cond, unsigned int rm)
6022 /* Implement {BX,BLX}<cond> <reg>" as:
6024 Preparation: cond <- instruction condition
6025 Insn: mov r0, r0 (nop)
6026 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6028 Don't set r14 in cleanup for BX. */
6030 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6032 dsc->u.branch.cond = cond;
6033 dsc->u.branch.link = link;
6035 dsc->u.branch.exchange = 1;
6037 dsc->cleanup = &cleanup_branch;
6041 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6042 struct regcache *regs, struct displaced_step_closure *dsc)
6044 unsigned int cond = bits (insn, 28, 31);
6047 int link = bit (insn, 5);
6048 unsigned int rm = bits (insn, 0, 3);
6050 if (debug_displaced)
6051 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6052 (unsigned long) insn);
6054 dsc->modinsn[0] = ARM_NOP;
6056 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6061 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6062 struct regcache *regs,
6063 struct displaced_step_closure *dsc)
6065 int link = bit (insn, 7);
6066 unsigned int rm = bits (insn, 3, 6);
6068 if (debug_displaced)
6069 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6070 (unsigned short) insn);
6072 dsc->modinsn[0] = THUMB_NOP;
6074 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6080 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6083 cleanup_alu_imm (struct gdbarch *gdbarch,
6084 struct regcache *regs, struct displaced_step_closure *dsc)
6086 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6087 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6088 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6089 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6093 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6094 struct displaced_step_closure *dsc)
6096 unsigned int rn = bits (insn, 16, 19);
6097 unsigned int rd = bits (insn, 12, 15);
6098 unsigned int op = bits (insn, 21, 24);
6099 int is_mov = (op == 0xd);
6100 ULONGEST rd_val, rn_val;
6102 if (!insn_references_pc (insn, 0x000ff000ul))
6103 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6105 if (debug_displaced)
6106 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6107 "%.8lx\n", is_mov ? "move" : "ALU",
6108 (unsigned long) insn);
6110 /* Instruction is of form:
6112 <op><cond> rd, [rn,] #imm
6116 Preparation: tmp1, tmp2 <- r0, r1;
6118 Insn: <op><cond> r0, r1, #imm
6119 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6122 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6123 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6124 rn_val = displaced_read_reg (regs, dsc, rn);
6125 rd_val = displaced_read_reg (regs, dsc, rd);
6126 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6127 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6131 dsc->modinsn[0] = insn & 0xfff00fff;
6133 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6135 dsc->cleanup = &cleanup_alu_imm;
6141 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6142 uint16_t insn2, struct regcache *regs,
6143 struct displaced_step_closure *dsc)
6145 unsigned int op = bits (insn1, 5, 8);
6146 unsigned int rn, rm, rd;
6147 ULONGEST rd_val, rn_val;
6149 rn = bits (insn1, 0, 3); /* Rn */
6150 rm = bits (insn2, 0, 3); /* Rm */
6151 rd = bits (insn2, 8, 11); /* Rd */
6153 /* This routine is only called for instruction MOV. */
6154 gdb_assert (op == 0x2 && rn == 0xf);
6156 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6157 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6159 if (debug_displaced)
6160 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6161 "ALU", insn1, insn2);
6163 /* Instruction is of form:
6165 <op><cond> rd, [rn,] #imm
6169 Preparation: tmp1, tmp2 <- r0, r1;
6171 Insn: <op><cond> r0, r1, #imm
6172 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6175 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6176 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6177 rn_val = displaced_read_reg (regs, dsc, rn);
6178 rd_val = displaced_read_reg (regs, dsc, rd);
6179 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6180 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6183 dsc->modinsn[0] = insn1;
6184 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6187 dsc->cleanup = &cleanup_alu_imm;
6192 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6195 cleanup_alu_reg (struct gdbarch *gdbarch,
6196 struct regcache *regs, struct displaced_step_closure *dsc)
6201 rd_val = displaced_read_reg (regs, dsc, 0);
6203 for (i = 0; i < 3; i++)
6204 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6206 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6210 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6211 struct displaced_step_closure *dsc,
6212 unsigned int rd, unsigned int rn, unsigned int rm)
6214 ULONGEST rd_val, rn_val, rm_val;
6216 /* Instruction is of form:
6218 <op><cond> rd, [rn,] rm [, <shift>]
6222 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6223 r0, r1, r2 <- rd, rn, rm
6224 Insn: <op><cond> r0, r1, r2 [, <shift>]
6225 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6228 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6229 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6230 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6231 rd_val = displaced_read_reg (regs, dsc, rd);
6232 rn_val = displaced_read_reg (regs, dsc, rn);
6233 rm_val = displaced_read_reg (regs, dsc, rm);
6234 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6235 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6236 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6239 dsc->cleanup = &cleanup_alu_reg;
6243 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6244 struct displaced_step_closure *dsc)
6246 unsigned int op = bits (insn, 21, 24);
6247 int is_mov = (op == 0xd);
6249 if (!insn_references_pc (insn, 0x000ff00ful))
6250 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6252 if (debug_displaced)
6253 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6254 is_mov ? "move" : "ALU", (unsigned long) insn);
6257 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6259 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6261 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6267 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6268 struct regcache *regs,
6269 struct displaced_step_closure *dsc)
6271 unsigned rn, rm, rd;
6273 rd = bits (insn, 3, 6);
6274 rn = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6277 if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6278 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6280 if (debug_displaced)
6281 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n",
6282 "ALU", (unsigned short) insn);
6284 dsc->modinsn[0] = ((insn & 0xff00) | 0x08);
6286 install_alu_reg (gdbarch, regs, dsc, rd, rn, rm);
6291 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6294 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6295 struct regcache *regs,
6296 struct displaced_step_closure *dsc)
6298 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6301 for (i = 0; i < 4; i++)
6302 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6304 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6308 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6309 struct displaced_step_closure *dsc,
6310 unsigned int rd, unsigned int rn, unsigned int rm,
6314 ULONGEST rd_val, rn_val, rm_val, rs_val;
6316 /* Instruction is of form:
6318 <op><cond> rd, [rn,] rm, <shift> rs
6322 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6323 r0, r1, r2, r3 <- rd, rn, rm, rs
6324 Insn: <op><cond> r0, r1, r2, <shift> r3
6326 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6330 for (i = 0; i < 4; i++)
6331 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6333 rd_val = displaced_read_reg (regs, dsc, rd);
6334 rn_val = displaced_read_reg (regs, dsc, rn);
6335 rm_val = displaced_read_reg (regs, dsc, rm);
6336 rs_val = displaced_read_reg (regs, dsc, rs);
6337 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6338 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6339 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6340 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6342 dsc->cleanup = &cleanup_alu_shifted_reg;
6346 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6347 struct regcache *regs,
6348 struct displaced_step_closure *dsc)
6350 unsigned int op = bits (insn, 21, 24);
6351 int is_mov = (op == 0xd);
6352 unsigned int rd, rn, rm, rs;
6354 if (!insn_references_pc (insn, 0x000fff0ful))
6355 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6357 if (debug_displaced)
6358 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6359 "%.8lx\n", is_mov ? "move" : "ALU",
6360 (unsigned long) insn);
6362 rn = bits (insn, 16, 19);
6363 rm = bits (insn, 0, 3);
6364 rs = bits (insn, 8, 11);
6365 rd = bits (insn, 12, 15);
6368 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6370 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6372 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6377 /* Clean up load instructions. */
6380 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6381 struct displaced_step_closure *dsc)
6383 ULONGEST rt_val, rt_val2 = 0, rn_val;
6385 rt_val = displaced_read_reg (regs, dsc, 0);
6386 if (dsc->u.ldst.xfersize == 8)
6387 rt_val2 = displaced_read_reg (regs, dsc, 1);
6388 rn_val = displaced_read_reg (regs, dsc, 2);
6390 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6391 if (dsc->u.ldst.xfersize > 4)
6392 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6393 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6394 if (!dsc->u.ldst.immed)
6395 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6397 /* Handle register writeback. */
6398 if (dsc->u.ldst.writeback)
6399 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6400 /* Put result in right place. */
6401 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6402 if (dsc->u.ldst.xfersize == 8)
6403 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6406 /* Clean up store instructions. */
6409 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6410 struct displaced_step_closure *dsc)
6412 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6414 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6415 if (dsc->u.ldst.xfersize > 4)
6416 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6417 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6418 if (!dsc->u.ldst.immed)
6419 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6420 if (!dsc->u.ldst.restore_r4)
6421 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6424 if (dsc->u.ldst.writeback)
6425 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6428 /* Copy "extra" load/store instructions. These are halfword/doubleword
6429 transfers, which have a different encoding to byte/word transfers. */
6432 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6433 struct regcache *regs, struct displaced_step_closure *dsc)
6435 unsigned int op1 = bits (insn, 20, 24);
6436 unsigned int op2 = bits (insn, 5, 6);
6437 unsigned int rt = bits (insn, 12, 15);
6438 unsigned int rn = bits (insn, 16, 19);
6439 unsigned int rm = bits (insn, 0, 3);
6440 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6441 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6442 int immed = (op1 & 0x4) != 0;
6444 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6446 if (!insn_references_pc (insn, 0x000ff00ful))
6447 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6449 if (debug_displaced)
6450 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6451 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6452 (unsigned long) insn);
6454 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6457 internal_error (__FILE__, __LINE__,
6458 _("copy_extra_ld_st: instruction decode error"));
6460 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6461 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6462 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6464 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6466 rt_val = displaced_read_reg (regs, dsc, rt);
6467 if (bytesize[opcode] == 8)
6468 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6469 rn_val = displaced_read_reg (regs, dsc, rn);
6471 rm_val = displaced_read_reg (regs, dsc, rm);
6473 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6474 if (bytesize[opcode] == 8)
6475 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6476 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6478 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6481 dsc->u.ldst.xfersize = bytesize[opcode];
6482 dsc->u.ldst.rn = rn;
6483 dsc->u.ldst.immed = immed;
6484 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6485 dsc->u.ldst.restore_r4 = 0;
6488 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6490 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6491 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6493 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6495 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6496 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6498 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6503 /* Copy byte/half word/word loads and stores. */
6506 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6507 struct displaced_step_closure *dsc, int load,
6508 int immed, int writeback, int size, int usermode,
6509 int rt, int rm, int rn)
6511 ULONGEST rt_val, rn_val, rm_val = 0;
6513 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6514 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6516 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6518 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6520 rt_val = displaced_read_reg (regs, dsc, rt);
6521 rn_val = displaced_read_reg (regs, dsc, rn);
6523 rm_val = displaced_read_reg (regs, dsc, rm);
6525 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6526 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6528 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6530 dsc->u.ldst.xfersize = size;
6531 dsc->u.ldst.rn = rn;
6532 dsc->u.ldst.immed = immed;
6533 dsc->u.ldst.writeback = writeback;
6535 /* To write PC we can do:
6537 Before this sequence of instructions:
6538 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6539 r2 is the Rn value got from dispalced_read_reg.
6541 Insn1: push {pc} Write address of STR instruction + offset on stack
6542 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6543 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6544 = addr(Insn1) + offset - addr(Insn3) - 8
6546 Insn4: add r4, r4, #8 r4 = offset - 8
6547 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6549 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6551 Otherwise we don't know what value to write for PC, since the offset is
6552 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6553 of this can be found in Section "Saving from r15" in
6554 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6556 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6561 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6562 uint16_t insn2, struct regcache *regs,
6563 struct displaced_step_closure *dsc, int size)
6565 unsigned int u_bit = bit (insn1, 7);
6566 unsigned int rt = bits (insn2, 12, 15);
6567 int imm12 = bits (insn2, 0, 11);
6570 if (debug_displaced)
6571 fprintf_unfiltered (gdb_stdlog,
6572 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6573 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6579 /* Rewrite instruction LDR Rt imm12 into:
6581 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6585 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6588 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6589 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6590 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6592 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6594 pc_val = pc_val & 0xfffffffc;
6596 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6597 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6601 dsc->u.ldst.xfersize = size;
6602 dsc->u.ldst.immed = 0;
6603 dsc->u.ldst.writeback = 0;
6604 dsc->u.ldst.restore_r4 = 0;
6606 /* LDR R0, R2, R3 */
6607 dsc->modinsn[0] = 0xf852;
6608 dsc->modinsn[1] = 0x3;
6611 dsc->cleanup = &cleanup_load;
6617 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6618 uint16_t insn2, struct regcache *regs,
6619 struct displaced_step_closure *dsc,
6620 int writeback, int immed)
6622 unsigned int rt = bits (insn2, 12, 15);
6623 unsigned int rn = bits (insn1, 0, 3);
6624 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6625 /* In LDR (register), there is also a register Rm, which is not allowed to
6626 be PC, so we don't have to check it. */
6628 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6629 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6632 if (debug_displaced)
6633 fprintf_unfiltered (gdb_stdlog,
6634 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6635 rt, rn, insn1, insn2);
6637 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6640 dsc->u.ldst.restore_r4 = 0;
6643 /* ldr[b]<cond> rt, [rn, #imm], etc.
6645 ldr[b]<cond> r0, [r2, #imm]. */
6647 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6648 dsc->modinsn[1] = insn2 & 0x0fff;
6651 /* ldr[b]<cond> rt, [rn, rm], etc.
6653 ldr[b]<cond> r0, [r2, r3]. */
6655 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6656 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6666 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6667 struct regcache *regs,
6668 struct displaced_step_closure *dsc,
6669 int load, int size, int usermode)
6671 int immed = !bit (insn, 25);
6672 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6673 unsigned int rt = bits (insn, 12, 15);
6674 unsigned int rn = bits (insn, 16, 19);
6675 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6677 if (!insn_references_pc (insn, 0x000ff00ful))
6678 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6680 if (debug_displaced)
6681 fprintf_unfiltered (gdb_stdlog,
6682 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6683 load ? (size == 1 ? "ldrb" : "ldr")
6684 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6686 (unsigned long) insn);
6688 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6689 usermode, rt, rm, rn);
6691 if (load || rt != ARM_PC_REGNUM)
6693 dsc->u.ldst.restore_r4 = 0;
6696 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6698 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6699 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6701 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6703 {ldr,str}[b]<cond> r0, [r2, r3]. */
6704 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6708 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6709 dsc->u.ldst.restore_r4 = 1;
6710 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6711 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6712 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6713 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6714 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6718 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6720 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6725 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6730 /* Cleanup LDM instructions with fully-populated register list. This is an
6731 unfortunate corner case: it's impossible to implement correctly by modifying
6732 the instruction. The issue is as follows: we have an instruction,
6736 which we must rewrite to avoid loading PC. A possible solution would be to
6737 do the load in two halves, something like (with suitable cleanup
6741 ldm[id][ab] r8!, {r0-r7}
6743 ldm[id][ab] r8, {r7-r14}
6746 but at present there's no suitable place for <temp>, since the scratch space
6747 is overwritten before the cleanup routine is called. For now, we simply
6748 emulate the instruction. */
6751 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6752 struct displaced_step_closure *dsc)
6754 int inc = dsc->u.block.increment;
6755 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6756 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6757 uint32_t regmask = dsc->u.block.regmask;
6758 int regno = inc ? 0 : 15;
6759 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6760 int exception_return = dsc->u.block.load && dsc->u.block.user
6761 && (regmask & 0x8000) != 0;
6762 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6763 int do_transfer = condition_true (dsc->u.block.cond, status);
6764 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6769 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6770 sensible we can do here. Complain loudly. */
6771 if (exception_return)
6772 error (_("Cannot single-step exception return"));
6774 /* We don't handle any stores here for now. */
6775 gdb_assert (dsc->u.block.load != 0);
6777 if (debug_displaced)
6778 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6779 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6780 dsc->u.block.increment ? "inc" : "dec",
6781 dsc->u.block.before ? "before" : "after");
6788 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6791 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6794 xfer_addr += bump_before;
6796 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6797 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6799 xfer_addr += bump_after;
6801 regmask &= ~(1 << regno);
6804 if (dsc->u.block.writeback)
6805 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6809 /* Clean up an STM which included the PC in the register list. */
6812 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6813 struct displaced_step_closure *dsc)
6815 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6816 int store_executed = condition_true (dsc->u.block.cond, status);
6817 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
6818 CORE_ADDR stm_insn_addr;
6821 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6823 /* If condition code fails, there's nothing else to do. */
6824 if (!store_executed)
6827 if (dsc->u.block.increment)
6829 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6831 if (dsc->u.block.before)
6836 pc_stored_at = dsc->u.block.xfer_addr;
6838 if (dsc->u.block.before)
6842 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
6843 stm_insn_addr = dsc->scratch_base;
6844 offset = pc_val - stm_insn_addr;
6846 if (debug_displaced)
6847 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
6848 "STM instruction\n", offset);
6850 /* Rewrite the stored PC to the proper value for the non-displaced original
6852 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
6853 dsc->insn_addr + offset);
6856 /* Clean up an LDM which includes the PC in the register list. We clumped all
6857 the registers in the transferred list into a contiguous range r0...rX (to
6858 avoid loading PC directly and losing control of the debugged program), so we
6859 must undo that here. */
6862 cleanup_block_load_pc (struct gdbarch *gdbarch,
6863 struct regcache *regs,
6864 struct displaced_step_closure *dsc)
6866 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6867 int load_executed = condition_true (dsc->u.block.cond, status);
6868 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6869 unsigned int regs_loaded = bitcount (mask);
6870 unsigned int num_to_shuffle = regs_loaded, clobbered;
6872 /* The method employed here will fail if the register list is fully populated
6873 (we need to avoid loading PC directly). */
6874 gdb_assert (num_to_shuffle < 16);
6879 clobbered = (1 << num_to_shuffle) - 1;
6881 while (num_to_shuffle > 0)
6883 if ((mask & (1 << write_reg)) != 0)
6885 unsigned int read_reg = num_to_shuffle - 1;
6887 if (read_reg != write_reg)
6889 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6890 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
6891 if (debug_displaced)
6892 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
6893 "loaded register r%d to r%d\n"), read_reg,
6896 else if (debug_displaced)
6897 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
6898 "r%d already in the right place\n"),
6901 clobbered &= ~(1 << write_reg);
6909 /* Restore any registers we scribbled over. */
6910 for (write_reg = 0; clobbered != 0; write_reg++)
6912 if ((clobbered & (1 << write_reg)) != 0)
6914 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
6916 if (debug_displaced)
6917 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
6918 "clobbered register r%d\n"), write_reg);
6919 clobbered &= ~(1 << write_reg);
6923 /* Perform register writeback manually. */
6924 if (dsc->u.block.writeback)
6926 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
6928 if (dsc->u.block.increment)
6929 new_rn_val += regs_loaded * 4;
6931 new_rn_val -= regs_loaded * 4;
6933 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
6938 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6939 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6942 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
6943 struct regcache *regs,
6944 struct displaced_step_closure *dsc)
6946 int load = bit (insn, 20);
6947 int user = bit (insn, 22);
6948 int increment = bit (insn, 23);
6949 int before = bit (insn, 24);
6950 int writeback = bit (insn, 21);
6951 int rn = bits (insn, 16, 19);
6953 /* Block transfers which don't mention PC can be run directly
6955 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
6956 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
6958 if (rn == ARM_PC_REGNUM)
6960 warning (_("displaced: Unpredictable LDM or STM with "
6961 "base register r15"));
6962 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
6965 if (debug_displaced)
6966 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6967 "%.8lx\n", (unsigned long) insn);
6969 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6970 dsc->u.block.rn = rn;
6972 dsc->u.block.load = load;
6973 dsc->u.block.user = user;
6974 dsc->u.block.increment = increment;
6975 dsc->u.block.before = before;
6976 dsc->u.block.writeback = writeback;
6977 dsc->u.block.cond = bits (insn, 28, 31);
6979 dsc->u.block.regmask = insn & 0xffff;
6983 if ((insn & 0xffff) == 0xffff)
6985 /* LDM with a fully-populated register list. This case is
6986 particularly tricky. Implement for now by fully emulating the
6987 instruction (which might not behave perfectly in all cases, but
6988 these instructions should be rare enough for that not to matter
6990 dsc->modinsn[0] = ARM_NOP;
6992 dsc->cleanup = &cleanup_block_load_all;
6996 /* LDM of a list of registers which includes PC. Implement by
6997 rewriting the list of registers to be transferred into a
6998 contiguous chunk r0...rX before doing the transfer, then shuffling
6999 registers into the correct places in the cleanup routine. */
7000 unsigned int regmask = insn & 0xffff;
7001 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7002 unsigned int to = 0, from = 0, i, new_rn;
7004 for (i = 0; i < num_in_list; i++)
7005 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7007 /* Writeback makes things complicated. We need to avoid clobbering
7008 the base register with one of the registers in our modified
7009 register list, but just using a different register can't work in
7012 ldm r14!, {r0-r13,pc}
7014 which would need to be rewritten as:
7018 but that can't work, because there's no free register for N.
7020 Solve this by turning off the writeback bit, and emulating
7021 writeback manually in the cleanup routine. */
7026 new_regmask = (1 << num_in_list) - 1;
7028 if (debug_displaced)
7029 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7030 "{..., pc}: original reg list %.4x, modified "
7031 "list %.4x\n"), rn, writeback ? "!" : "",
7032 (int) insn & 0xffff, new_regmask);
7034 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7036 dsc->cleanup = &cleanup_block_load_pc;
7041 /* STM of a list of registers which includes PC. Run the instruction
7042 as-is, but out of line: this will store the wrong value for the PC,
7043 so we must manually fix up the memory in the cleanup routine.
7044 Doing things this way has the advantage that we can auto-detect
7045 the offset of the PC write (which is architecture-dependent) in
7046 the cleanup routine. */
7047 dsc->modinsn[0] = insn;
7049 dsc->cleanup = &cleanup_block_store_pc;
7056 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7057 struct regcache *regs,
7058 struct displaced_step_closure *dsc)
7060 int rn = bits (insn1, 0, 3);
7061 int load = bit (insn1, 4);
7062 int writeback = bit (insn1, 5);
7064 /* Block transfers which don't mention PC can be run directly
7066 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7067 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7069 if (rn == ARM_PC_REGNUM)
7071 warning (_("displaced: Unpredictable LDM or STM with "
7072 "base register r15"));
7073 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7074 "unpredictable ldm/stm", dsc);
7077 if (debug_displaced)
7078 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7079 "%.4x%.4x\n", insn1, insn2);
7081 /* Clear bit 13, since it should be always zero. */
7082 dsc->u.block.regmask = (insn2 & 0xdfff);
7083 dsc->u.block.rn = rn;
7085 dsc->u.block.load = load;
7086 dsc->u.block.user = 0;
7087 dsc->u.block.increment = bit (insn1, 7);
7088 dsc->u.block.before = bit (insn1, 8);
7089 dsc->u.block.writeback = writeback;
7090 dsc->u.block.cond = INST_AL;
7091 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7095 if (dsc->u.block.regmask == 0xffff)
7097 /* This branch is impossible to happen. */
7102 unsigned int regmask = dsc->u.block.regmask;
7103 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7104 unsigned int to = 0, from = 0, i, new_rn;
7106 for (i = 0; i < num_in_list; i++)
7107 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7112 new_regmask = (1 << num_in_list) - 1;
7114 if (debug_displaced)
7115 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7116 "{..., pc}: original reg list %.4x, modified "
7117 "list %.4x\n"), rn, writeback ? "!" : "",
7118 (int) dsc->u.block.regmask, new_regmask);
7120 dsc->modinsn[0] = insn1;
7121 dsc->modinsn[1] = (new_regmask & 0xffff);
7124 dsc->cleanup = &cleanup_block_load_pc;
7129 dsc->modinsn[0] = insn1;
7130 dsc->modinsn[1] = insn2;
7132 dsc->cleanup = &cleanup_block_store_pc;
7137 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7138 for Linux, where some SVC instructions must be treated specially. */
7141 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7142 struct displaced_step_closure *dsc)
7144 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7146 if (debug_displaced)
7147 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7148 "%.8lx\n", (unsigned long) resume_addr);
7150 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7154 /* Common copy routine for svc instruciton. */
7157 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7158 struct displaced_step_closure *dsc)
7160 /* Preparation: none.
7161 Insn: unmodified svc.
7162 Cleanup: pc <- insn_addr + insn_size. */
7164 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7166 dsc->wrote_to_pc = 1;
7168 /* Allow OS-specific code to override SVC handling. */
7169 if (dsc->u.svc.copy_svc_os)
7170 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7173 dsc->cleanup = &cleanup_svc;
7179 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7180 struct regcache *regs, struct displaced_step_closure *dsc)
7183 if (debug_displaced)
7184 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7185 (unsigned long) insn);
7187 dsc->modinsn[0] = insn;
7189 return install_svc (gdbarch, regs, dsc);
7193 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7194 struct regcache *regs, struct displaced_step_closure *dsc)
7197 if (debug_displaced)
7198 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7201 dsc->modinsn[0] = insn;
7203 return install_svc (gdbarch, regs, dsc);
7206 /* Copy undefined instructions. */
7209 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7210 struct displaced_step_closure *dsc)
7212 if (debug_displaced)
7213 fprintf_unfiltered (gdb_stdlog,
7214 "displaced: copying undefined insn %.8lx\n",
7215 (unsigned long) insn);
7217 dsc->modinsn[0] = insn;
7223 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7224 struct displaced_step_closure *dsc)
7227 if (debug_displaced)
7228 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7229 "%.4x %.4x\n", (unsigned short) insn1,
7230 (unsigned short) insn2);
7232 dsc->modinsn[0] = insn1;
7233 dsc->modinsn[1] = insn2;
7239 /* Copy unpredictable instructions. */
7242 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7243 struct displaced_step_closure *dsc)
7245 if (debug_displaced)
7246 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7247 "%.8lx\n", (unsigned long) insn);
7249 dsc->modinsn[0] = insn;
7254 /* The decode_* functions are instruction decoding helpers. They mostly follow
7255 the presentation in the ARM ARM. */
7258 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7259 struct regcache *regs,
7260 struct displaced_step_closure *dsc)
7262 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7263 unsigned int rn = bits (insn, 16, 19);
7265 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7266 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7267 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7268 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7269 else if ((op1 & 0x60) == 0x20)
7270 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7271 else if ((op1 & 0x71) == 0x40)
7272 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7274 else if ((op1 & 0x77) == 0x41)
7275 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7276 else if ((op1 & 0x77) == 0x45)
7277 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7278 else if ((op1 & 0x77) == 0x51)
7281 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7283 return arm_copy_unpred (gdbarch, insn, dsc);
7285 else if ((op1 & 0x77) == 0x55)
7286 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7287 else if (op1 == 0x57)
7290 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7291 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7292 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7293 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7294 default: return arm_copy_unpred (gdbarch, insn, dsc);
7296 else if ((op1 & 0x63) == 0x43)
7297 return arm_copy_unpred (gdbarch, insn, dsc);
7298 else if ((op2 & 0x1) == 0x0)
7299 switch (op1 & ~0x80)
7302 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7304 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7305 case 0x71: case 0x75:
7307 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7308 case 0x63: case 0x67: case 0x73: case 0x77:
7309 return arm_copy_unpred (gdbarch, insn, dsc);
7311 return arm_copy_undef (gdbarch, insn, dsc);
7314 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7318 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7319 struct regcache *regs,
7320 struct displaced_step_closure *dsc)
7322 if (bit (insn, 27) == 0)
7323 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7324 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7325 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7328 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7331 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7333 case 0x4: case 0x5: case 0x6: case 0x7:
7334 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7337 switch ((insn & 0xe00000) >> 21)
7339 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7341 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7344 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7347 return arm_copy_undef (gdbarch, insn, dsc);
7352 int rn_f = (bits (insn, 16, 19) == 0xf);
7353 switch ((insn & 0xe00000) >> 21)
7356 /* ldc/ldc2 imm (undefined for rn == pc). */
7357 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7358 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7361 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7363 case 0x4: case 0x5: case 0x6: case 0x7:
7364 /* ldc/ldc2 lit (undefined for rn != pc). */
7365 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7366 : arm_copy_undef (gdbarch, insn, dsc);
7369 return arm_copy_undef (gdbarch, insn, dsc);
7374 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7377 if (bits (insn, 16, 19) == 0xf)
7379 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7381 return arm_copy_undef (gdbarch, insn, dsc);
7385 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7387 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7391 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7393 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7396 return arm_copy_undef (gdbarch, insn, dsc);
7400 /* Decode miscellaneous instructions in dp/misc encoding space. */
7403 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7404 struct regcache *regs,
7405 struct displaced_step_closure *dsc)
7407 unsigned int op2 = bits (insn, 4, 6);
7408 unsigned int op = bits (insn, 21, 22);
7409 unsigned int op1 = bits (insn, 16, 19);
7414 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7417 if (op == 0x1) /* bx. */
7418 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7420 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7422 return arm_copy_undef (gdbarch, insn, dsc);
7426 /* Not really supported. */
7427 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7429 return arm_copy_undef (gdbarch, insn, dsc);
7433 return arm_copy_bx_blx_reg (gdbarch, insn,
7434 regs, dsc); /* blx register. */
7436 return arm_copy_undef (gdbarch, insn, dsc);
7439 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7443 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7445 /* Not really supported. */
7446 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7449 return arm_copy_undef (gdbarch, insn, dsc);
7454 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7455 struct regcache *regs,
7456 struct displaced_step_closure *dsc)
7459 switch (bits (insn, 20, 24))
7462 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7465 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7467 case 0x12: case 0x16:
7468 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7471 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7475 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7477 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7478 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7479 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7480 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7481 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7482 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7483 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7484 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7485 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7486 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7487 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7488 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7489 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7490 /* 2nd arg means "unpriveleged". */
7491 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7495 /* Should be unreachable. */
7500 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7501 struct regcache *regs,
7502 struct displaced_step_closure *dsc)
7504 int a = bit (insn, 25), b = bit (insn, 4);
7505 uint32_t op1 = bits (insn, 20, 24);
7506 int rn_f = bits (insn, 16, 19) == 0xf;
7508 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7509 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7510 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7511 else if ((!a && (op1 & 0x17) == 0x02)
7512 || (a && (op1 & 0x17) == 0x02 && !b))
7513 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7514 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7515 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7516 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7517 else if ((!a && (op1 & 0x17) == 0x03)
7518 || (a && (op1 & 0x17) == 0x03 && !b))
7519 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7520 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7521 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7522 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7523 else if ((!a && (op1 & 0x17) == 0x06)
7524 || (a && (op1 & 0x17) == 0x06 && !b))
7525 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7526 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7527 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7528 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7529 else if ((!a && (op1 & 0x17) == 0x07)
7530 || (a && (op1 & 0x17) == 0x07 && !b))
7531 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7533 /* Should be unreachable. */
7538 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7539 struct displaced_step_closure *dsc)
7541 switch (bits (insn, 20, 24))
7543 case 0x00: case 0x01: case 0x02: case 0x03:
7544 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7546 case 0x04: case 0x05: case 0x06: case 0x07:
7547 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7549 case 0x08: case 0x09: case 0x0a: case 0x0b:
7550 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7551 return arm_copy_unmodified (gdbarch, insn,
7552 "decode/pack/unpack/saturate/reverse", dsc);
7555 if (bits (insn, 5, 7) == 0) /* op2. */
7557 if (bits (insn, 12, 15) == 0xf)
7558 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7560 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7563 return arm_copy_undef (gdbarch, insn, dsc);
7565 case 0x1a: case 0x1b:
7566 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7567 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7569 return arm_copy_undef (gdbarch, insn, dsc);
7571 case 0x1c: case 0x1d:
7572 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7574 if (bits (insn, 0, 3) == 0xf)
7575 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7577 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7580 return arm_copy_undef (gdbarch, insn, dsc);
7582 case 0x1e: case 0x1f:
7583 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7584 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7586 return arm_copy_undef (gdbarch, insn, dsc);
7589 /* Should be unreachable. */
7594 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7595 struct regcache *regs,
7596 struct displaced_step_closure *dsc)
7599 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7601 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7605 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7606 struct regcache *regs,
7607 struct displaced_step_closure *dsc)
7609 unsigned int opcode = bits (insn, 20, 24);
7613 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7614 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7616 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7617 case 0x12: case 0x16:
7618 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7620 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7621 case 0x13: case 0x17:
7622 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7624 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7625 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7626 /* Note: no writeback for these instructions. Bit 25 will always be
7627 zero though (via caller), so the following works OK. */
7628 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7631 /* Should be unreachable. */
7635 /* Decode shifted register instructions. */
7638 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7639 uint16_t insn2, struct regcache *regs,
7640 struct displaced_step_closure *dsc)
7642 /* PC is only allowed to be used in instruction MOV. */
7644 unsigned int op = bits (insn1, 5, 8);
7645 unsigned int rn = bits (insn1, 0, 3);
7647 if (op == 0x2 && rn == 0xf) /* MOV */
7648 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7650 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7651 "dp (shift reg)", dsc);
7655 /* Decode extension register load/store. Exactly the same as
7656 arm_decode_ext_reg_ld_st. */
7659 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7660 uint16_t insn2, struct regcache *regs,
7661 struct displaced_step_closure *dsc)
7663 unsigned int opcode = bits (insn1, 4, 8);
7667 case 0x04: case 0x05:
7668 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7669 "vfp/neon vmov", dsc);
7671 case 0x08: case 0x0c: /* 01x00 */
7672 case 0x0a: case 0x0e: /* 01x10 */
7673 case 0x12: case 0x16: /* 10x10 */
7674 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7675 "vfp/neon vstm/vpush", dsc);
7677 case 0x09: case 0x0d: /* 01x01 */
7678 case 0x0b: case 0x0f: /* 01x11 */
7679 case 0x13: case 0x17: /* 10x11 */
7680 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7681 "vfp/neon vldm/vpop", dsc);
7683 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7684 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7686 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7687 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7690 /* Should be unreachable. */
7695 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7696 struct regcache *regs, struct displaced_step_closure *dsc)
7698 unsigned int op1 = bits (insn, 20, 25);
7699 int op = bit (insn, 4);
7700 unsigned int coproc = bits (insn, 8, 11);
7701 unsigned int rn = bits (insn, 16, 19);
7703 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7704 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7705 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7706 && (coproc & 0xe) != 0xa)
7708 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7709 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7710 && (coproc & 0xe) != 0xa)
7711 /* ldc/ldc2 imm/lit. */
7712 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7713 else if ((op1 & 0x3e) == 0x00)
7714 return arm_copy_undef (gdbarch, insn, dsc);
7715 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7716 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7717 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7718 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7719 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7720 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7721 else if ((op1 & 0x30) == 0x20 && !op)
7723 if ((coproc & 0xe) == 0xa)
7724 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7726 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7728 else if ((op1 & 0x30) == 0x20 && op)
7729 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7730 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7731 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7732 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7733 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7734 else if ((op1 & 0x30) == 0x30)
7735 return arm_copy_svc (gdbarch, insn, regs, dsc);
7737 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7741 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7742 uint16_t insn2, struct regcache *regs,
7743 struct displaced_step_closure *dsc)
7745 unsigned int coproc = bits (insn2, 8, 11);
7746 unsigned int op1 = bits (insn1, 4, 9);
7747 unsigned int bit_5_8 = bits (insn1, 5, 8);
7748 unsigned int bit_9 = bit (insn1, 9);
7749 unsigned int bit_4 = bit (insn1, 4);
7750 unsigned int rn = bits (insn1, 0, 3);
7755 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7756 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7758 else if (bit_5_8 == 0) /* UNDEFINED. */
7759 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7762 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7763 if ((coproc & 0xe) == 0xa)
7764 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7766 else /* coproc is not 101x. */
7768 if (bit_4 == 0) /* STC/STC2. */
7769 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7771 else /* LDC/LDC2 {literal, immeidate}. */
7772 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7778 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7784 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7785 struct displaced_step_closure *dsc, int rd)
7791 Preparation: Rd <- PC
7797 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7798 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7802 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7803 struct displaced_step_closure *dsc,
7804 int rd, unsigned int imm)
7807 /* Encoding T2: ADDS Rd, #imm */
7808 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7810 install_pc_relative (gdbarch, regs, dsc, rd);
7816 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
7817 struct regcache *regs,
7818 struct displaced_step_closure *dsc)
7820 unsigned int rd = bits (insn, 8, 10);
7821 unsigned int imm8 = bits (insn, 0, 7);
7823 if (debug_displaced)
7824 fprintf_unfiltered (gdb_stdlog,
7825 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7828 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7832 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7833 uint16_t insn2, struct regcache *regs,
7834 struct displaced_step_closure *dsc)
7836 unsigned int rd = bits (insn2, 8, 11);
7837 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7838 extract raw immediate encoding rather than computing immediate. When
7839 generating ADD or SUB instruction, we can simply perform OR operation to
7840 set immediate into ADD. */
7841 unsigned int imm_3_8 = insn2 & 0x70ff;
7842 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7844 if (debug_displaced)
7845 fprintf_unfiltered (gdb_stdlog,
7846 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7847 rd, imm_i, imm_3_8, insn1, insn2);
7849 if (bit (insn1, 7)) /* Encoding T2 */
7851 /* Encoding T3: SUB Rd, Rd, #imm */
7852 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7853 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7855 else /* Encoding T3 */
7857 /* Encoding T3: ADD Rd, Rd, #imm */
7858 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7859 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7863 install_pc_relative (gdbarch, regs, dsc, rd);
7869 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
7870 struct regcache *regs,
7871 struct displaced_step_closure *dsc)
7873 unsigned int rt = bits (insn1, 8, 10);
7875 int imm8 = (bits (insn1, 0, 7) << 2);
7876 CORE_ADDR from = dsc->insn_addr;
7882 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7884 Insn: LDR R0, [R2, R3];
7885 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7887 if (debug_displaced)
7888 fprintf_unfiltered (gdb_stdlog,
7889 "displaced: copying thumb ldr r%d [pc #%d]\n"
7892 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
7893 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
7894 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
7895 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7896 /* The assembler calculates the required value of the offset from the
7897 Align(PC,4) value of this instruction to the label. */
7898 pc = pc & 0xfffffffc;
7900 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
7901 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
7904 dsc->u.ldst.xfersize = 4;
7906 dsc->u.ldst.immed = 0;
7907 dsc->u.ldst.writeback = 0;
7908 dsc->u.ldst.restore_r4 = 0;
7910 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7912 dsc->cleanup = &cleanup_load;
7917 /* Copy Thumb cbnz/cbz insruction. */
7920 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
7921 struct regcache *regs,
7922 struct displaced_step_closure *dsc)
7924 int non_zero = bit (insn1, 11);
7925 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
7926 CORE_ADDR from = dsc->insn_addr;
7927 int rn = bits (insn1, 0, 2);
7928 int rn_val = displaced_read_reg (regs, dsc, rn);
7930 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
7931 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7932 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7933 condition is false, let it be, cleanup_branch will do nothing. */
7934 if (dsc->u.branch.cond)
7936 dsc->u.branch.cond = INST_AL;
7937 dsc->u.branch.dest = from + 4 + imm5;
7940 dsc->u.branch.dest = from + 2;
7942 dsc->u.branch.link = 0;
7943 dsc->u.branch.exchange = 0;
7945 if (debug_displaced)
7946 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
7947 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
7948 rn, rn_val, insn1, dsc->u.branch.dest);
7950 dsc->modinsn[0] = THUMB_NOP;
7952 dsc->cleanup = &cleanup_branch;
7956 /* Copy Table Branch Byte/Halfword */
7958 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7959 uint16_t insn2, struct regcache *regs,
7960 struct displaced_step_closure *dsc)
7962 ULONGEST rn_val, rm_val;
7963 int is_tbh = bit (insn2, 4);
7964 CORE_ADDR halfwords = 0;
7965 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7967 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7968 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7974 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7975 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7981 target_read_memory (rn_val + rm_val, buf, 1);
7982 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7985 if (debug_displaced)
7986 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7987 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7988 (unsigned int) rn_val, (unsigned int) rm_val,
7989 (unsigned int) halfwords);
7991 dsc->u.branch.cond = INST_AL;
7992 dsc->u.branch.link = 0;
7993 dsc->u.branch.exchange = 0;
7994 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7996 dsc->cleanup = &cleanup_branch;
8002 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8003 struct displaced_step_closure *dsc)
8006 int val = displaced_read_reg (regs, dsc, 7);
8007 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8010 val = displaced_read_reg (regs, dsc, 8);
8011 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8014 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8019 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8020 struct regcache *regs,
8021 struct displaced_step_closure *dsc)
8023 dsc->u.block.regmask = insn1 & 0x00ff;
8025 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8028 (1) register list is full, that is, r0-r7 are used.
8029 Prepare: tmp[0] <- r8
8031 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8032 MOV r8, r7; Move value of r7 to r8;
8033 POP {r7}; Store PC value into r7.
8035 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8037 (2) register list is not full, supposing there are N registers in
8038 register list (except PC, 0 <= N <= 7).
8039 Prepare: for each i, 0 - N, tmp[i] <- ri.
8041 POP {r0, r1, ...., rN};
8043 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8044 from tmp[] properly.
8046 if (debug_displaced)
8047 fprintf_unfiltered (gdb_stdlog,
8048 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8049 dsc->u.block.regmask, insn1);
8051 if (dsc->u.block.regmask == 0xff)
8053 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8055 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8056 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8057 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8060 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8064 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8065 unsigned int new_regmask, bit = 1;
8066 unsigned int to = 0, from = 0, i, new_rn;
8068 for (i = 0; i < num_in_list + 1; i++)
8069 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8071 new_regmask = (1 << (num_in_list + 1)) - 1;
8073 if (debug_displaced)
8074 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8075 "{..., pc}: original reg list %.4x,"
8076 " modified list %.4x\n"),
8077 (int) dsc->u.block.regmask, new_regmask);
8079 dsc->u.block.regmask |= 0x8000;
8080 dsc->u.block.writeback = 0;
8081 dsc->u.block.cond = INST_AL;
8083 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8085 dsc->cleanup = &cleanup_block_load_pc;
8092 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8093 struct regcache *regs,
8094 struct displaced_step_closure *dsc)
8096 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8097 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8100 /* 16-bit thumb instructions. */
8101 switch (op_bit_12_15)
8103 /* Shift (imme), add, subtract, move and compare. */
8104 case 0: case 1: case 2: case 3:
8105 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8106 "shift/add/sub/mov/cmp",
8110 switch (op_bit_10_11)
8112 case 0: /* Data-processing */
8113 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8117 case 1: /* Special data instructions and branch and exchange. */
8119 unsigned short op = bits (insn1, 7, 9);
8120 if (op == 6 || op == 7) /* BX or BLX */
8121 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8122 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8123 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8125 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8129 default: /* LDR (literal) */
8130 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8133 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8134 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8137 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8138 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8139 else /* Generate SP-relative address */
8140 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8142 case 11: /* Misc 16-bit instructions */
8144 switch (bits (insn1, 8, 11))
8146 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8147 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8149 case 12: case 13: /* POP */
8150 if (bit (insn1, 8)) /* PC is in register list. */
8151 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8153 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8155 case 15: /* If-Then, and hints */
8156 if (bits (insn1, 0, 3))
8157 /* If-Then makes up to four following instructions conditional.
8158 IT instruction itself is not conditional, so handle it as a
8159 common unmodified instruction. */
8160 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8163 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8166 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8171 if (op_bit_10_11 < 2) /* Store multiple registers */
8172 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8173 else /* Load multiple registers */
8174 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8176 case 13: /* Conditional branch and supervisor call */
8177 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8178 err = thumb_copy_b (gdbarch, insn1, dsc);
8180 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8182 case 14: /* Unconditional branch */
8183 err = thumb_copy_b (gdbarch, insn1, dsc);
8190 internal_error (__FILE__, __LINE__,
8191 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8195 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8196 uint16_t insn1, uint16_t insn2,
8197 struct regcache *regs,
8198 struct displaced_step_closure *dsc)
8200 int rt = bits (insn2, 12, 15);
8201 int rn = bits (insn1, 0, 3);
8202 int op1 = bits (insn1, 7, 8);
8205 switch (bits (insn1, 5, 6))
8207 case 0: /* Load byte and memory hints */
8208 if (rt == 0xf) /* PLD/PLI */
8211 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8212 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8214 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8219 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8220 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8223 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8224 "ldrb{reg, immediate}/ldrbt",
8229 case 1: /* Load halfword and memory hints. */
8230 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8231 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8232 "pld/unalloc memhint", dsc);
8236 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8239 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8243 case 2: /* Load word */
8245 int insn2_bit_8_11 = bits (insn2, 8, 11);
8248 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8249 else if (op1 == 0x1) /* Encoding T3 */
8250 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8252 else /* op1 == 0x0 */
8254 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8255 /* LDR (immediate) */
8256 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8257 dsc, bit (insn2, 8), 1);
8258 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8259 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8262 /* LDR (register) */
8263 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8269 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8276 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8277 uint16_t insn2, struct regcache *regs,
8278 struct displaced_step_closure *dsc)
8281 unsigned short op = bit (insn2, 15);
8282 unsigned int op1 = bits (insn1, 11, 12);
8288 switch (bits (insn1, 9, 10))
8293 /* Load/store {dual, execlusive}, table branch. */
8294 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8295 && bits (insn2, 5, 7) == 0)
8296 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8299 /* PC is not allowed to use in load/store {dual, exclusive}
8301 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8302 "load/store dual/ex", dsc);
8304 else /* load/store multiple */
8306 switch (bits (insn1, 7, 8))
8308 case 0: case 3: /* SRS, RFE */
8309 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8312 case 1: case 2: /* LDM/STM/PUSH/POP */
8313 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8320 /* Data-processing (shift register). */
8321 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8324 default: /* Coprocessor instructions. */
8325 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8330 case 2: /* op1 = 2 */
8331 if (op) /* Branch and misc control. */
8333 if (bit (insn2, 14) /* BLX/BL */
8334 || bit (insn2, 12) /* Unconditional branch */
8335 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8336 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8338 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8343 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8345 int op = bits (insn1, 4, 8);
8346 int rn = bits (insn1, 0, 3);
8347 if ((op == 0 || op == 0xa) && rn == 0xf)
8348 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8351 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8354 else /* Data processing (modified immeidate) */
8355 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8359 case 3: /* op1 = 3 */
8360 switch (bits (insn1, 9, 10))
8364 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8366 else /* NEON Load/Store and Store single data item */
8367 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8368 "neon elt/struct load/store",
8371 case 1: /* op1 = 3, bits (9, 10) == 1 */
8372 switch (bits (insn1, 7, 8))
8374 case 0: case 1: /* Data processing (register) */
8375 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8378 case 2: /* Multiply and absolute difference */
8379 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8380 "mul/mua/diff", dsc);
8382 case 3: /* Long multiply and divide */
8383 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8388 default: /* Coprocessor instructions */
8389 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8398 internal_error (__FILE__, __LINE__,
8399 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8404 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8405 CORE_ADDR to, struct regcache *regs,
8406 struct displaced_step_closure *dsc)
8408 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8410 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8412 if (debug_displaced)
8413 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8414 "at %.8lx\n", insn1, (unsigned long) from);
8417 dsc->insn_size = thumb_insn_size (insn1);
8418 if (thumb_insn_size (insn1) == 4)
8421 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8422 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8425 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8429 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8430 CORE_ADDR to, struct regcache *regs,
8431 struct displaced_step_closure *dsc)
8434 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8437 /* Most displaced instructions use a 1-instruction scratch space, so set this
8438 here and override below if/when necessary. */
8440 dsc->insn_addr = from;
8441 dsc->scratch_base = to;
8442 dsc->cleanup = NULL;
8443 dsc->wrote_to_pc = 0;
8445 if (!displaced_in_arm_mode (regs))
8446 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8450 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8451 if (debug_displaced)
8452 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8453 "at %.8lx\n", (unsigned long) insn,
8454 (unsigned long) from);
8456 if ((insn & 0xf0000000) == 0xf0000000)
8457 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8458 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8460 case 0x0: case 0x1: case 0x2: case 0x3:
8461 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8464 case 0x4: case 0x5: case 0x6:
8465 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8469 err = arm_decode_media (gdbarch, insn, dsc);
8472 case 0x8: case 0x9: case 0xa: case 0xb:
8473 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8476 case 0xc: case 0xd: case 0xe: case 0xf:
8477 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8482 internal_error (__FILE__, __LINE__,
8483 _("arm_process_displaced_insn: Instruction decode error"));
8486 /* Actually set up the scratch space for a displaced instruction. */
8489 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8490 CORE_ADDR to, struct displaced_step_closure *dsc)
8492 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8493 unsigned int i, len, offset;
8494 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8495 int size = dsc->is_thumb? 2 : 4;
8496 const unsigned char *bkp_insn;
8499 /* Poke modified instruction(s). */
8500 for (i = 0; i < dsc->numinsns; i++)
8502 if (debug_displaced)
8504 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8506 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8509 fprintf_unfiltered (gdb_stdlog, "%.4x",
8510 (unsigned short)dsc->modinsn[i]);
8512 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8513 (unsigned long) to + offset);
8516 write_memory_unsigned_integer (to + offset, size,
8517 byte_order_for_code,
8522 /* Choose the correct breakpoint instruction. */
8525 bkp_insn = tdep->thumb_breakpoint;
8526 len = tdep->thumb_breakpoint_size;
8530 bkp_insn = tdep->arm_breakpoint;
8531 len = tdep->arm_breakpoint_size;
8534 /* Put breakpoint afterwards. */
8535 write_memory (to + offset, bkp_insn, len);
8537 if (debug_displaced)
8538 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8539 paddress (gdbarch, from), paddress (gdbarch, to));
8542 /* Entry point for copying an instruction into scratch space for displaced
8545 struct displaced_step_closure *
8546 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8547 CORE_ADDR from, CORE_ADDR to,
8548 struct regcache *regs)
8550 struct displaced_step_closure *dsc
8551 = xmalloc (sizeof (struct displaced_step_closure));
8552 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8553 arm_displaced_init_closure (gdbarch, from, to, dsc);
8558 /* Entry point for cleaning things up after a displaced instruction has been
8562 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8563 struct displaced_step_closure *dsc,
8564 CORE_ADDR from, CORE_ADDR to,
8565 struct regcache *regs)
8568 dsc->cleanup (gdbarch, regs, dsc);
8570 if (!dsc->wrote_to_pc)
8571 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8572 dsc->insn_addr + dsc->insn_size);
8576 #include "bfd-in2.h"
8577 #include "libcoff.h"
8580 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8582 struct gdbarch *gdbarch = info->application_data;
8584 if (arm_pc_is_thumb (gdbarch, memaddr))
8586 static asymbol *asym;
8587 static combined_entry_type ce;
8588 static struct coff_symbol_struct csym;
8589 static struct bfd fake_bfd;
8590 static bfd_target fake_target;
8592 if (csym.native == NULL)
8594 /* Create a fake symbol vector containing a Thumb symbol.
8595 This is solely so that the code in print_insn_little_arm()
8596 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8597 the presence of a Thumb symbol and switch to decoding
8598 Thumb instructions. */
8600 fake_target.flavour = bfd_target_coff_flavour;
8601 fake_bfd.xvec = &fake_target;
8602 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8604 csym.symbol.the_bfd = &fake_bfd;
8605 csym.symbol.name = "fake";
8606 asym = (asymbol *) & csym;
8609 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8610 info->symbols = &asym;
8613 info->symbols = NULL;
8615 if (info->endian == BFD_ENDIAN_BIG)
8616 return print_insn_big_arm (memaddr, info);
8618 return print_insn_little_arm (memaddr, info);
8621 /* The following define instruction sequences that will cause ARM
8622 cpu's to take an undefined instruction trap. These are used to
8623 signal a breakpoint to GDB.
8625 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8626 modes. A different instruction is required for each mode. The ARM
8627 cpu's can also be big or little endian. Thus four different
8628 instructions are needed to support all cases.
8630 Note: ARMv4 defines several new instructions that will take the
8631 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8632 not in fact add the new instructions. The new undefined
8633 instructions in ARMv4 are all instructions that had no defined
8634 behaviour in earlier chips. There is no guarantee that they will
8635 raise an exception, but may be treated as NOP's. In practice, it
8636 may only safe to rely on instructions matching:
8638 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8639 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8640 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8642 Even this may only true if the condition predicate is true. The
8643 following use a condition predicate of ALWAYS so it is always TRUE.
8645 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8646 and NetBSD all use a software interrupt rather than an undefined
8647 instruction to force a trap. This can be handled by by the
8648 abi-specific code during establishment of the gdbarch vector. */
8650 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8651 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8652 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8653 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8655 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8656 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8657 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8658 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8660 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8661 the program counter value to determine whether a 16-bit or 32-bit
8662 breakpoint should be used. It returns a pointer to a string of
8663 bytes that encode a breakpoint instruction, stores the length of
8664 the string to *lenptr, and adjusts the program counter (if
8665 necessary) to point to the actual memory location where the
8666 breakpoint should be inserted. */
8668 static const unsigned char *
8669 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8671 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8672 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8674 if (arm_pc_is_thumb (gdbarch, *pcptr))
8676 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8678 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8679 check whether we are replacing a 32-bit instruction. */
8680 if (tdep->thumb2_breakpoint != NULL)
8683 if (target_read_memory (*pcptr, buf, 2) == 0)
8685 unsigned short inst1;
8686 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8687 if (thumb_insn_size (inst1) == 4)
8689 *lenptr = tdep->thumb2_breakpoint_size;
8690 return tdep->thumb2_breakpoint;
8695 *lenptr = tdep->thumb_breakpoint_size;
8696 return tdep->thumb_breakpoint;
8700 *lenptr = tdep->arm_breakpoint_size;
8701 return tdep->arm_breakpoint;
8706 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8709 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8711 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8712 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8713 that this is not confused with a 32-bit ARM breakpoint. */
8717 /* Extract from an array REGBUF containing the (raw) register state a
8718 function return value of type TYPE, and copy that, in virtual
8719 format, into VALBUF. */
8722 arm_extract_return_value (struct type *type, struct regcache *regs,
8725 struct gdbarch *gdbarch = get_regcache_arch (regs);
8726 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8728 if (TYPE_CODE_FLT == TYPE_CODE (type))
8730 switch (gdbarch_tdep (gdbarch)->fp_model)
8734 /* The value is in register F0 in internal format. We need to
8735 extract the raw value and then convert it to the desired
8737 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8739 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8740 convert_from_extended (floatformat_from_type (type), tmpbuf,
8741 valbuf, gdbarch_byte_order (gdbarch));
8745 case ARM_FLOAT_SOFT_FPA:
8746 case ARM_FLOAT_SOFT_VFP:
8747 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8748 not using the VFP ABI code. */
8750 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8751 if (TYPE_LENGTH (type) > 4)
8752 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8753 valbuf + INT_REGISTER_SIZE);
8757 internal_error (__FILE__, __LINE__,
8758 _("arm_extract_return_value: "
8759 "Floating point model not supported"));
8763 else if (TYPE_CODE (type) == TYPE_CODE_INT
8764 || TYPE_CODE (type) == TYPE_CODE_CHAR
8765 || TYPE_CODE (type) == TYPE_CODE_BOOL
8766 || TYPE_CODE (type) == TYPE_CODE_PTR
8767 || TYPE_CODE (type) == TYPE_CODE_REF
8768 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8770 /* If the type is a plain integer, then the access is
8771 straight-forward. Otherwise we have to play around a bit
8773 int len = TYPE_LENGTH (type);
8774 int regno = ARM_A1_REGNUM;
8779 /* By using store_unsigned_integer we avoid having to do
8780 anything special for small big-endian values. */
8781 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8782 store_unsigned_integer (valbuf,
8783 (len > INT_REGISTER_SIZE
8784 ? INT_REGISTER_SIZE : len),
8786 len -= INT_REGISTER_SIZE;
8787 valbuf += INT_REGISTER_SIZE;
8792 /* For a structure or union the behaviour is as if the value had
8793 been stored to word-aligned memory and then loaded into
8794 registers with 32-bit load instruction(s). */
8795 int len = TYPE_LENGTH (type);
8796 int regno = ARM_A1_REGNUM;
8797 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8801 regcache_cooked_read (regs, regno++, tmpbuf);
8802 memcpy (valbuf, tmpbuf,
8803 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8804 len -= INT_REGISTER_SIZE;
8805 valbuf += INT_REGISTER_SIZE;
8811 /* Will a function return an aggregate type in memory or in a
8812 register? Return 0 if an aggregate type can be returned in a
8813 register, 1 if it must be returned in memory. */
8816 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8819 enum type_code code;
8821 CHECK_TYPEDEF (type);
8823 /* In the ARM ABI, "integer" like aggregate types are returned in
8824 registers. For an aggregate type to be integer like, its size
8825 must be less than or equal to INT_REGISTER_SIZE and the
8826 offset of each addressable subfield must be zero. Note that bit
8827 fields are not addressable, and all addressable subfields of
8828 unions always start at offset zero.
8830 This function is based on the behaviour of GCC 2.95.1.
8831 See: gcc/arm.c: arm_return_in_memory() for details.
8833 Note: All versions of GCC before GCC 2.95.2 do not set up the
8834 parameters correctly for a function returning the following
8835 structure: struct { float f;}; This should be returned in memory,
8836 not a register. Richard Earnshaw sent me a patch, but I do not
8837 know of any way to detect if a function like the above has been
8838 compiled with the correct calling convention. */
8840 /* All aggregate types that won't fit in a register must be returned
8842 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8847 /* The AAPCS says all aggregates not larger than a word are returned
8849 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8852 /* The only aggregate types that can be returned in a register are
8853 structs and unions. Arrays must be returned in memory. */
8854 code = TYPE_CODE (type);
8855 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
8860 /* Assume all other aggregate types can be returned in a register.
8861 Run a check for structures, unions and arrays. */
8864 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8867 /* Need to check if this struct/union is "integer" like. For
8868 this to be true, its size must be less than or equal to
8869 INT_REGISTER_SIZE and the offset of each addressable
8870 subfield must be zero. Note that bit fields are not
8871 addressable, and unions always start at offset zero. If any
8872 of the subfields is a floating point type, the struct/union
8873 cannot be an integer type. */
8875 /* For each field in the object, check:
8876 1) Is it FP? --> yes, nRc = 1;
8877 2) Is it addressable (bitpos != 0) and
8878 not packed (bitsize == 0)?
8882 for (i = 0; i < TYPE_NFIELDS (type); i++)
8884 enum type_code field_type_code;
8885 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
8888 /* Is it a floating point type field? */
8889 if (field_type_code == TYPE_CODE_FLT)
8895 /* If bitpos != 0, then we have to care about it. */
8896 if (TYPE_FIELD_BITPOS (type, i) != 0)
8898 /* Bitfields are not addressable. If the field bitsize is
8899 zero, then the field is not packed. Hence it cannot be
8900 a bitfield or any other packed type. */
8901 if (TYPE_FIELD_BITSIZE (type, i) == 0)
8913 /* Write into appropriate registers a function return value of type
8914 TYPE, given in virtual format. */
8917 arm_store_return_value (struct type *type, struct regcache *regs,
8918 const gdb_byte *valbuf)
8920 struct gdbarch *gdbarch = get_regcache_arch (regs);
8921 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8923 if (TYPE_CODE (type) == TYPE_CODE_FLT)
8925 char buf[MAX_REGISTER_SIZE];
8927 switch (gdbarch_tdep (gdbarch)->fp_model)
8931 convert_to_extended (floatformat_from_type (type), buf, valbuf,
8932 gdbarch_byte_order (gdbarch));
8933 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
8936 case ARM_FLOAT_SOFT_FPA:
8937 case ARM_FLOAT_SOFT_VFP:
8938 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8939 not using the VFP ABI code. */
8941 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
8942 if (TYPE_LENGTH (type) > 4)
8943 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
8944 valbuf + INT_REGISTER_SIZE);
8948 internal_error (__FILE__, __LINE__,
8949 _("arm_store_return_value: Floating "
8950 "point model not supported"));
8954 else if (TYPE_CODE (type) == TYPE_CODE_INT
8955 || TYPE_CODE (type) == TYPE_CODE_CHAR
8956 || TYPE_CODE (type) == TYPE_CODE_BOOL
8957 || TYPE_CODE (type) == TYPE_CODE_PTR
8958 || TYPE_CODE (type) == TYPE_CODE_REF
8959 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8961 if (TYPE_LENGTH (type) <= 4)
8963 /* Values of one word or less are zero/sign-extended and
8965 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8966 LONGEST val = unpack_long (type, valbuf);
8968 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8969 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8973 /* Integral values greater than one word are stored in consecutive
8974 registers starting with r0. This will always be a multiple of
8975 the regiser size. */
8976 int len = TYPE_LENGTH (type);
8977 int regno = ARM_A1_REGNUM;
8981 regcache_cooked_write (regs, regno++, valbuf);
8982 len -= INT_REGISTER_SIZE;
8983 valbuf += INT_REGISTER_SIZE;
8989 /* For a structure or union the behaviour is as if the value had
8990 been stored to word-aligned memory and then loaded into
8991 registers with 32-bit load instruction(s). */
8992 int len = TYPE_LENGTH (type);
8993 int regno = ARM_A1_REGNUM;
8994 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8998 memcpy (tmpbuf, valbuf,
8999 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9000 regcache_cooked_write (regs, regno++, tmpbuf);
9001 len -= INT_REGISTER_SIZE;
9002 valbuf += INT_REGISTER_SIZE;
9008 /* Handle function return values. */
9010 static enum return_value_convention
9011 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9012 struct type *valtype, struct regcache *regcache,
9013 gdb_byte *readbuf, const gdb_byte *writebuf)
9015 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9016 struct type *func_type = function ? value_type (function) : NULL;
9017 enum arm_vfp_cprc_base_type vfp_base_type;
9020 if (arm_vfp_abi_for_function (gdbarch, func_type)
9021 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9023 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9024 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9026 for (i = 0; i < vfp_base_count; i++)
9028 if (reg_char == 'q')
9031 arm_neon_quad_write (gdbarch, regcache, i,
9032 writebuf + i * unit_length);
9035 arm_neon_quad_read (gdbarch, regcache, i,
9036 readbuf + i * unit_length);
9043 sprintf (name_buf, "%c%d", reg_char, i);
9044 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9047 regcache_cooked_write (regcache, regnum,
9048 writebuf + i * unit_length);
9050 regcache_cooked_read (regcache, regnum,
9051 readbuf + i * unit_length);
9054 return RETURN_VALUE_REGISTER_CONVENTION;
9057 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9058 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9059 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9061 if (tdep->struct_return == pcc_struct_return
9062 || arm_return_in_memory (gdbarch, valtype))
9063 return RETURN_VALUE_STRUCT_CONVENTION;
9066 /* AAPCS returns complex types longer than a register in memory. */
9067 if (tdep->arm_abi != ARM_ABI_APCS
9068 && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
9069 && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE)
9070 return RETURN_VALUE_STRUCT_CONVENTION;
9073 arm_store_return_value (valtype, regcache, writebuf);
9076 arm_extract_return_value (valtype, regcache, readbuf);
9078 return RETURN_VALUE_REGISTER_CONVENTION;
9083 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9085 struct gdbarch *gdbarch = get_frame_arch (frame);
9086 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9087 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9089 char buf[INT_REGISTER_SIZE];
9091 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9093 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9097 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9101 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9102 return the target PC. Otherwise return 0. */
9105 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9109 CORE_ADDR start_addr;
9111 /* Find the starting address and name of the function containing the PC. */
9112 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9115 /* If PC is in a Thumb call or return stub, return the address of the
9116 target PC, which is in a register. The thunk functions are called
9117 _call_via_xx, where x is the register name. The possible names
9118 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9119 functions, named __ARM_call_via_r[0-7]. */
9120 if (strncmp (name, "_call_via_", 10) == 0
9121 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9123 /* Use the name suffix to determine which register contains the
9125 static char *table[15] =
9126 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9127 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9130 int offset = strlen (name) - 2;
9132 for (regno = 0; regno <= 14; regno++)
9133 if (strcmp (&name[offset], table[regno]) == 0)
9134 return get_frame_register_unsigned (frame, regno);
9137 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9138 non-interworking calls to foo. We could decode the stubs
9139 to find the target but it's easier to use the symbol table. */
9140 namelen = strlen (name);
9141 if (name[0] == '_' && name[1] == '_'
9142 && ((namelen > 2 + strlen ("_from_thumb")
9143 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
9144 strlen ("_from_thumb")) == 0)
9145 || (namelen > 2 + strlen ("_from_arm")
9146 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
9147 strlen ("_from_arm")) == 0)))
9150 int target_len = namelen - 2;
9151 struct minimal_symbol *minsym;
9152 struct objfile *objfile;
9153 struct obj_section *sec;
9155 if (name[namelen - 1] == 'b')
9156 target_len -= strlen ("_from_thumb");
9158 target_len -= strlen ("_from_arm");
9160 target_name = alloca (target_len + 1);
9161 memcpy (target_name, name + 2, target_len);
9162 target_name[target_len] = '\0';
9164 sec = find_pc_section (pc);
9165 objfile = (sec == NULL) ? NULL : sec->objfile;
9166 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9168 return SYMBOL_VALUE_ADDRESS (minsym);
9173 return 0; /* not a stub */
9177 set_arm_command (char *args, int from_tty)
9179 printf_unfiltered (_("\
9180 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9181 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9185 show_arm_command (char *args, int from_tty)
9187 cmd_show_list (showarmcmdlist, from_tty, "");
9191 arm_update_current_architecture (void)
9193 struct gdbarch_info info;
9195 /* If the current architecture is not ARM, we have nothing to do. */
9196 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
9199 /* Update the architecture. */
9200 gdbarch_info_init (&info);
9202 if (!gdbarch_update_p (info))
9203 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9207 set_fp_model_sfunc (char *args, int from_tty,
9208 struct cmd_list_element *c)
9210 enum arm_float_model fp_model;
9212 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9213 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9215 arm_fp_model = fp_model;
9219 if (fp_model == ARM_FLOAT_LAST)
9220 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9223 arm_update_current_architecture ();
9227 show_fp_model (struct ui_file *file, int from_tty,
9228 struct cmd_list_element *c, const char *value)
9230 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9232 if (arm_fp_model == ARM_FLOAT_AUTO
9233 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
9234 fprintf_filtered (file, _("\
9235 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9236 fp_model_strings[tdep->fp_model]);
9238 fprintf_filtered (file, _("\
9239 The current ARM floating point model is \"%s\".\n"),
9240 fp_model_strings[arm_fp_model]);
9244 arm_set_abi (char *args, int from_tty,
9245 struct cmd_list_element *c)
9247 enum arm_abi_kind arm_abi;
9249 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9250 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9252 arm_abi_global = arm_abi;
9256 if (arm_abi == ARM_ABI_LAST)
9257 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9260 arm_update_current_architecture ();
9264 arm_show_abi (struct ui_file *file, int from_tty,
9265 struct cmd_list_element *c, const char *value)
9267 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9269 if (arm_abi_global == ARM_ABI_AUTO
9270 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
9271 fprintf_filtered (file, _("\
9272 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9273 arm_abi_strings[tdep->arm_abi]);
9275 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9280 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9281 struct cmd_list_element *c, const char *value)
9283 fprintf_filtered (file,
9284 _("The current execution mode assumed "
9285 "(when symbols are unavailable) is \"%s\".\n"),
9286 arm_fallback_mode_string);
9290 arm_show_force_mode (struct ui_file *file, int from_tty,
9291 struct cmd_list_element *c, const char *value)
9293 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9295 fprintf_filtered (file,
9296 _("The current execution mode assumed "
9297 "(even when symbols are available) is \"%s\".\n"),
9298 arm_force_mode_string);
9301 /* If the user changes the register disassembly style used for info
9302 register and other commands, we have to also switch the style used
9303 in opcodes for disassembly output. This function is run in the "set
9304 arm disassembly" command, and does that. */
9307 set_disassembly_style_sfunc (char *args, int from_tty,
9308 struct cmd_list_element *c)
9310 set_disassembly_style ();
9313 /* Return the ARM register name corresponding to register I. */
9315 arm_register_name (struct gdbarch *gdbarch, int i)
9317 const int num_regs = gdbarch_num_regs (gdbarch);
9319 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9320 && i >= num_regs && i < num_regs + 32)
9322 static const char *const vfp_pseudo_names[] = {
9323 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9324 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9325 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9326 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9329 return vfp_pseudo_names[i - num_regs];
9332 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9333 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9335 static const char *const neon_pseudo_names[] = {
9336 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9337 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9340 return neon_pseudo_names[i - num_regs - 32];
9343 if (i >= ARRAY_SIZE (arm_register_names))
9344 /* These registers are only supported on targets which supply
9345 an XML description. */
9348 return arm_register_names[i];
9352 set_disassembly_style (void)
9356 /* Find the style that the user wants. */
9357 for (current = 0; current < num_disassembly_options; current++)
9358 if (disassembly_style == valid_disassembly_styles[current])
9360 gdb_assert (current < num_disassembly_options);
9362 /* Synchronize the disassembler. */
9363 set_arm_regname_option (current);
9366 /* Test whether the coff symbol specific value corresponds to a Thumb
9370 coff_sym_is_thumb (int val)
9372 return (val == C_THUMBEXT
9373 || val == C_THUMBSTAT
9374 || val == C_THUMBEXTFUNC
9375 || val == C_THUMBSTATFUNC
9376 || val == C_THUMBLABEL);
9379 /* arm_coff_make_msymbol_special()
9380 arm_elf_make_msymbol_special()
9382 These functions test whether the COFF or ELF symbol corresponds to
9383 an address in thumb code, and set a "special" bit in a minimal
9384 symbol to indicate that it does. */
9387 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9389 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9390 == ST_BRANCH_TO_THUMB)
9391 MSYMBOL_SET_SPECIAL (msym);
9395 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9397 if (coff_sym_is_thumb (val))
9398 MSYMBOL_SET_SPECIAL (msym);
9402 arm_objfile_data_free (struct objfile *objfile, void *arg)
9404 struct arm_per_objfile *data = arg;
9407 for (i = 0; i < objfile->obfd->section_count; i++)
9408 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9412 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9415 const char *name = bfd_asymbol_name (sym);
9416 struct arm_per_objfile *data;
9417 VEC(arm_mapping_symbol_s) **map_p;
9418 struct arm_mapping_symbol new_map_sym;
9420 gdb_assert (name[0] == '$');
9421 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9424 data = objfile_data (objfile, arm_objfile_data_key);
9427 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9428 struct arm_per_objfile);
9429 set_objfile_data (objfile, arm_objfile_data_key, data);
9430 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9431 objfile->obfd->section_count,
9432 VEC(arm_mapping_symbol_s) *);
9434 map_p = &data->section_maps[bfd_get_section (sym)->index];
9436 new_map_sym.value = sym->value;
9437 new_map_sym.type = name[1];
9439 /* Assume that most mapping symbols appear in order of increasing
9440 value. If they were randomly distributed, it would be faster to
9441 always push here and then sort at first use. */
9442 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9444 struct arm_mapping_symbol *prev_map_sym;
9446 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9447 if (prev_map_sym->value >= sym->value)
9450 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9451 arm_compare_mapping_symbols);
9452 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9457 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9461 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9463 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9464 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9466 /* If necessary, set the T bit. */
9469 ULONGEST val, t_bit;
9470 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9471 t_bit = arm_psr_thumb_bit (gdbarch);
9472 if (arm_pc_is_thumb (gdbarch, pc))
9473 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9476 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9481 /* Read the contents of a NEON quad register, by reading from two
9482 double registers. This is used to implement the quad pseudo
9483 registers, and for argument passing in case the quad registers are
9484 missing; vectors are passed in quad registers when using the VFP
9485 ABI, even if a NEON unit is not present. REGNUM is the index of
9486 the quad register, in [0, 15]. */
9488 static enum register_status
9489 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9490 int regnum, gdb_byte *buf)
9493 gdb_byte reg_buf[8];
9494 int offset, double_regnum;
9495 enum register_status status;
9497 sprintf (name_buf, "d%d", regnum << 1);
9498 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9501 /* d0 is always the least significant half of q0. */
9502 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9507 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9508 if (status != REG_VALID)
9510 memcpy (buf + offset, reg_buf, 8);
9512 offset = 8 - offset;
9513 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9514 if (status != REG_VALID)
9516 memcpy (buf + offset, reg_buf, 8);
9521 static enum register_status
9522 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9523 int regnum, gdb_byte *buf)
9525 const int num_regs = gdbarch_num_regs (gdbarch);
9527 gdb_byte reg_buf[8];
9528 int offset, double_regnum;
9530 gdb_assert (regnum >= num_regs);
9533 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9534 /* Quad-precision register. */
9535 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9538 enum register_status status;
9540 /* Single-precision register. */
9541 gdb_assert (regnum < 32);
9543 /* s0 is always the least significant half of d0. */
9544 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9545 offset = (regnum & 1) ? 0 : 4;
9547 offset = (regnum & 1) ? 4 : 0;
9549 sprintf (name_buf, "d%d", regnum >> 1);
9550 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9553 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9554 if (status == REG_VALID)
9555 memcpy (buf, reg_buf + offset, 4);
9560 /* Store the contents of BUF to a NEON quad register, by writing to
9561 two double registers. This is used to implement the quad pseudo
9562 registers, and for argument passing in case the quad registers are
9563 missing; vectors are passed in quad registers when using the VFP
9564 ABI, even if a NEON unit is not present. REGNUM is the index
9565 of the quad register, in [0, 15]. */
9568 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9569 int regnum, const gdb_byte *buf)
9572 int offset, double_regnum;
9574 sprintf (name_buf, "d%d", regnum << 1);
9575 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9578 /* d0 is always the least significant half of q0. */
9579 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9584 regcache_raw_write (regcache, double_regnum, buf + offset);
9585 offset = 8 - offset;
9586 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9590 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9591 int regnum, const gdb_byte *buf)
9593 const int num_regs = gdbarch_num_regs (gdbarch);
9595 gdb_byte reg_buf[8];
9596 int offset, double_regnum;
9598 gdb_assert (regnum >= num_regs);
9601 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9602 /* Quad-precision register. */
9603 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9606 /* Single-precision register. */
9607 gdb_assert (regnum < 32);
9609 /* s0 is always the least significant half of d0. */
9610 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9611 offset = (regnum & 1) ? 0 : 4;
9613 offset = (regnum & 1) ? 4 : 0;
9615 sprintf (name_buf, "d%d", regnum >> 1);
9616 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9619 regcache_raw_read (regcache, double_regnum, reg_buf);
9620 memcpy (reg_buf + offset, buf, 4);
9621 regcache_raw_write (regcache, double_regnum, reg_buf);
9625 static struct value *
9626 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9628 const int *reg_p = baton;
9629 return value_of_register (*reg_p, frame);
9632 static enum gdb_osabi
9633 arm_elf_osabi_sniffer (bfd *abfd)
9635 unsigned int elfosabi;
9636 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9638 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9640 if (elfosabi == ELFOSABI_ARM)
9641 /* GNU tools use this value. Check note sections in this case,
9643 bfd_map_over_sections (abfd,
9644 generic_elf_osabi_sniff_abi_tag_sections,
9647 /* Anything else will be handled by the generic ELF sniffer. */
9652 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9653 struct reggroup *group)
9655 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9656 this, FPS register belongs to save_regroup, restore_reggroup, and
9657 all_reggroup, of course. */
9658 if (regnum == ARM_FPS_REGNUM)
9659 return (group == float_reggroup
9660 || group == save_reggroup
9661 || group == restore_reggroup
9662 || group == all_reggroup);
9664 return default_register_reggroup_p (gdbarch, regnum, group);
9668 /* For backward-compatibility we allow two 'g' packet lengths with
9669 the remote protocol depending on whether FPA registers are
9670 supplied. M-profile targets do not have FPA registers, but some
9671 stubs already exist in the wild which use a 'g' packet which
9672 supplies them albeit with dummy values. The packet format which
9673 includes FPA registers should be considered deprecated for
9674 M-profile targets. */
9677 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9679 if (gdbarch_tdep (gdbarch)->is_m)
9681 /* If we know from the executable this is an M-profile target,
9682 cater for remote targets whose register set layout is the
9683 same as the FPA layout. */
9684 register_remote_g_packet_guess (gdbarch,
9685 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9686 (16 * INT_REGISTER_SIZE)
9687 + (8 * FP_REGISTER_SIZE)
9688 + (2 * INT_REGISTER_SIZE),
9689 tdesc_arm_with_m_fpa_layout);
9691 /* The regular M-profile layout. */
9692 register_remote_g_packet_guess (gdbarch,
9693 /* r0-r12,sp,lr,pc; xpsr */
9694 (16 * INT_REGISTER_SIZE)
9695 + INT_REGISTER_SIZE,
9698 /* M-profile plus M4F VFP. */
9699 register_remote_g_packet_guess (gdbarch,
9700 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9701 (16 * INT_REGISTER_SIZE)
9702 + (16 * VFP_REGISTER_SIZE)
9703 + (2 * INT_REGISTER_SIZE),
9704 tdesc_arm_with_m_vfp_d16);
9707 /* Otherwise we don't have a useful guess. */
9711 /* Initialize the current architecture based on INFO. If possible,
9712 re-use an architecture from ARCHES, which is a list of
9713 architectures already created during this debugging session.
9715 Called e.g. at program startup, when reading a core file, and when
9716 reading a binary file. */
9718 static struct gdbarch *
9719 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9721 struct gdbarch_tdep *tdep;
9722 struct gdbarch *gdbarch;
9723 struct gdbarch_list *best_arch;
9724 enum arm_abi_kind arm_abi = arm_abi_global;
9725 enum arm_float_model fp_model = arm_fp_model;
9726 struct tdesc_arch_data *tdesc_data = NULL;
9728 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9730 int have_fpa_registers = 1;
9731 const struct target_desc *tdesc = info.target_desc;
9733 /* If we have an object to base this architecture on, try to determine
9736 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9738 int ei_osabi, e_flags;
9740 switch (bfd_get_flavour (info.abfd))
9742 case bfd_target_aout_flavour:
9743 /* Assume it's an old APCS-style ABI. */
9744 arm_abi = ARM_ABI_APCS;
9747 case bfd_target_coff_flavour:
9748 /* Assume it's an old APCS-style ABI. */
9750 arm_abi = ARM_ABI_APCS;
9753 case bfd_target_elf_flavour:
9754 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9755 e_flags = elf_elfheader (info.abfd)->e_flags;
9757 if (ei_osabi == ELFOSABI_ARM)
9759 /* GNU tools used to use this value, but do not for EABI
9760 objects. There's nowhere to tag an EABI version
9761 anyway, so assume APCS. */
9762 arm_abi = ARM_ABI_APCS;
9764 else if (ei_osabi == ELFOSABI_NONE)
9766 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9767 int attr_arch, attr_profile;
9771 case EF_ARM_EABI_UNKNOWN:
9772 /* Assume GNU tools. */
9773 arm_abi = ARM_ABI_APCS;
9776 case EF_ARM_EABI_VER4:
9777 case EF_ARM_EABI_VER5:
9778 arm_abi = ARM_ABI_AAPCS;
9779 /* EABI binaries default to VFP float ordering.
9780 They may also contain build attributes that can
9781 be used to identify if the VFP argument-passing
9783 if (fp_model == ARM_FLOAT_AUTO)
9786 switch (bfd_elf_get_obj_attr_int (info.abfd,
9791 /* "The user intended FP parameter/result
9792 passing to conform to AAPCS, base
9794 fp_model = ARM_FLOAT_SOFT_VFP;
9797 /* "The user intended FP parameter/result
9798 passing to conform to AAPCS, VFP
9800 fp_model = ARM_FLOAT_VFP;
9803 /* "The user intended FP parameter/result
9804 passing to conform to tool chain-specific
9805 conventions" - we don't know any such
9806 conventions, so leave it as "auto". */
9809 /* Attribute value not mentioned in the
9810 October 2008 ABI, so leave it as
9815 fp_model = ARM_FLOAT_SOFT_VFP;
9821 /* Leave it as "auto". */
9822 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9827 /* Detect M-profile programs. This only works if the
9828 executable file includes build attributes; GCC does
9829 copy them to the executable, but e.g. RealView does
9831 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9833 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9835 Tag_CPU_arch_profile);
9836 /* GCC specifies the profile for v6-M; RealView only
9837 specifies the profile for architectures starting with
9838 V7 (as opposed to architectures with a tag
9839 numerically greater than TAG_CPU_ARCH_V7). */
9840 if (!tdesc_has_registers (tdesc)
9841 && (attr_arch == TAG_CPU_ARCH_V6_M
9842 || attr_arch == TAG_CPU_ARCH_V6S_M
9843 || attr_profile == 'M'))
9848 if (fp_model == ARM_FLOAT_AUTO)
9850 int e_flags = elf_elfheader (info.abfd)->e_flags;
9852 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9855 /* Leave it as "auto". Strictly speaking this case
9856 means FPA, but almost nobody uses that now, and
9857 many toolchains fail to set the appropriate bits
9858 for the floating-point model they use. */
9860 case EF_ARM_SOFT_FLOAT:
9861 fp_model = ARM_FLOAT_SOFT_FPA;
9863 case EF_ARM_VFP_FLOAT:
9864 fp_model = ARM_FLOAT_VFP;
9866 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9867 fp_model = ARM_FLOAT_SOFT_VFP;
9872 if (e_flags & EF_ARM_BE8)
9873 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
9878 /* Leave it as "auto". */
9883 /* Check any target description for validity. */
9884 if (tdesc_has_registers (tdesc))
9886 /* For most registers we require GDB's default names; but also allow
9887 the numeric names for sp / lr / pc, as a convenience. */
9888 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
9889 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
9890 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
9892 const struct tdesc_feature *feature;
9895 feature = tdesc_find_feature (tdesc,
9896 "org.gnu.gdb.arm.core");
9897 if (feature == NULL)
9899 feature = tdesc_find_feature (tdesc,
9900 "org.gnu.gdb.arm.m-profile");
9901 if (feature == NULL)
9907 tdesc_data = tdesc_data_alloc ();
9910 for (i = 0; i < ARM_SP_REGNUM; i++)
9911 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9912 arm_register_names[i]);
9913 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9916 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9919 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9923 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9924 ARM_PS_REGNUM, "xpsr");
9926 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9927 ARM_PS_REGNUM, "cpsr");
9931 tdesc_data_cleanup (tdesc_data);
9935 feature = tdesc_find_feature (tdesc,
9936 "org.gnu.gdb.arm.fpa");
9937 if (feature != NULL)
9940 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9941 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9942 arm_register_names[i]);
9945 tdesc_data_cleanup (tdesc_data);
9950 have_fpa_registers = 0;
9952 feature = tdesc_find_feature (tdesc,
9953 "org.gnu.gdb.xscale.iwmmxt");
9954 if (feature != NULL)
9956 static const char *const iwmmxt_names[] = {
9957 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9958 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9959 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9960 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9964 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9966 &= tdesc_numbered_register (feature, tdesc_data, i,
9967 iwmmxt_names[i - ARM_WR0_REGNUM]);
9969 /* Check for the control registers, but do not fail if they
9971 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9972 tdesc_numbered_register (feature, tdesc_data, i,
9973 iwmmxt_names[i - ARM_WR0_REGNUM]);
9975 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9977 &= tdesc_numbered_register (feature, tdesc_data, i,
9978 iwmmxt_names[i - ARM_WR0_REGNUM]);
9982 tdesc_data_cleanup (tdesc_data);
9987 /* If we have a VFP unit, check whether the single precision registers
9988 are present. If not, then we will synthesize them as pseudo
9990 feature = tdesc_find_feature (tdesc,
9991 "org.gnu.gdb.arm.vfp");
9992 if (feature != NULL)
9994 static const char *const vfp_double_names[] = {
9995 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9996 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9997 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9998 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10001 /* Require the double precision registers. There must be either
10004 for (i = 0; i < 32; i++)
10006 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10008 vfp_double_names[i]);
10012 if (!valid_p && i == 16)
10015 /* Also require FPSCR. */
10016 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10017 ARM_FPSCR_REGNUM, "fpscr");
10020 tdesc_data_cleanup (tdesc_data);
10024 if (tdesc_unnumbered_register (feature, "s0") == 0)
10025 have_vfp_pseudos = 1;
10027 have_vfp_registers = 1;
10029 /* If we have VFP, also check for NEON. The architecture allows
10030 NEON without VFP (integer vector operations only), but GDB
10031 does not support that. */
10032 feature = tdesc_find_feature (tdesc,
10033 "org.gnu.gdb.arm.neon");
10034 if (feature != NULL)
10036 /* NEON requires 32 double-precision registers. */
10039 tdesc_data_cleanup (tdesc_data);
10043 /* If there are quad registers defined by the stub, use
10044 their type; otherwise (normally) provide them with
10045 the default type. */
10046 if (tdesc_unnumbered_register (feature, "q0") == 0)
10047 have_neon_pseudos = 1;
10054 /* If there is already a candidate, use it. */
10055 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10057 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10059 if (arm_abi != ARM_ABI_AUTO
10060 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10063 if (fp_model != ARM_FLOAT_AUTO
10064 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10067 /* There are various other properties in tdep that we do not
10068 need to check here: those derived from a target description,
10069 since gdbarches with a different target description are
10070 automatically disqualified. */
10072 /* Do check is_m, though, since it might come from the binary. */
10073 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10076 /* Found a match. */
10080 if (best_arch != NULL)
10082 if (tdesc_data != NULL)
10083 tdesc_data_cleanup (tdesc_data);
10084 return best_arch->gdbarch;
10087 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
10088 gdbarch = gdbarch_alloc (&info, tdep);
10090 /* Record additional information about the architecture we are defining.
10091 These are gdbarch discriminators, like the OSABI. */
10092 tdep->arm_abi = arm_abi;
10093 tdep->fp_model = fp_model;
10095 tdep->have_fpa_registers = have_fpa_registers;
10096 tdep->have_vfp_registers = have_vfp_registers;
10097 tdep->have_vfp_pseudos = have_vfp_pseudos;
10098 tdep->have_neon_pseudos = have_neon_pseudos;
10099 tdep->have_neon = have_neon;
10101 arm_register_g_packet_guesses (gdbarch);
10104 switch (info.byte_order_for_code)
10106 case BFD_ENDIAN_BIG:
10107 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10108 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10109 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10110 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10114 case BFD_ENDIAN_LITTLE:
10115 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10116 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10117 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10118 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10123 internal_error (__FILE__, __LINE__,
10124 _("arm_gdbarch_init: bad byte order for float format"));
10127 /* On ARM targets char defaults to unsigned. */
10128 set_gdbarch_char_signed (gdbarch, 0);
10130 /* Note: for displaced stepping, this includes the breakpoint, and one word
10131 of additional scratch space. This setting isn't used for anything beside
10132 displaced stepping at present. */
10133 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10135 /* This should be low enough for everything. */
10136 tdep->lowest_pc = 0x20;
10137 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10139 /* The default, for both APCS and AAPCS, is to return small
10140 structures in registers. */
10141 tdep->struct_return = reg_struct_return;
10143 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10144 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10146 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10148 /* Frame handling. */
10149 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10150 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10151 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10153 frame_base_set_default (gdbarch, &arm_normal_base);
10155 /* Address manipulation. */
10156 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
10157 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10159 /* Advance PC across function entry code. */
10160 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10162 /* Detect whether PC is in function epilogue. */
10163 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
10165 /* Skip trampolines. */
10166 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10168 /* The stack grows downward. */
10169 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10171 /* Breakpoint manipulation. */
10172 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10173 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10174 arm_remote_breakpoint_from_pc);
10176 /* Information about registers, etc. */
10177 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10178 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10179 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10180 set_gdbarch_register_type (gdbarch, arm_register_type);
10181 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10183 /* This "info float" is FPA-specific. Use the generic version if we
10184 do not have FPA. */
10185 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10186 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10188 /* Internal <-> external register number maps. */
10189 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10190 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10192 set_gdbarch_register_name (gdbarch, arm_register_name);
10194 /* Returning results. */
10195 set_gdbarch_return_value (gdbarch, arm_return_value);
10198 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10200 /* Minsymbol frobbing. */
10201 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10202 set_gdbarch_coff_make_msymbol_special (gdbarch,
10203 arm_coff_make_msymbol_special);
10204 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10206 /* Thumb-2 IT block support. */
10207 set_gdbarch_adjust_breakpoint_address (gdbarch,
10208 arm_adjust_breakpoint_address);
10210 /* Virtual tables. */
10211 set_gdbarch_vbit_in_delta (gdbarch, 1);
10213 /* Hook in the ABI-specific overrides, if they have been registered. */
10214 gdbarch_init_osabi (info, gdbarch);
10216 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10218 /* Add some default predicates. */
10219 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10220 dwarf2_append_unwinders (gdbarch);
10221 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10222 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10224 /* Now we have tuned the configuration, set a few final things,
10225 based on what the OS ABI has told us. */
10227 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10228 binaries are always marked. */
10229 if (tdep->arm_abi == ARM_ABI_AUTO)
10230 tdep->arm_abi = ARM_ABI_APCS;
10232 /* Watchpoints are not steppable. */
10233 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10235 /* We used to default to FPA for generic ARM, but almost nobody
10236 uses that now, and we now provide a way for the user to force
10237 the model. So default to the most useful variant. */
10238 if (tdep->fp_model == ARM_FLOAT_AUTO)
10239 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10241 if (tdep->jb_pc >= 0)
10242 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10244 /* Floating point sizes and format. */
10245 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10246 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10248 set_gdbarch_double_format
10249 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10250 set_gdbarch_long_double_format
10251 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10255 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10256 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10259 if (have_vfp_pseudos)
10261 /* NOTE: These are the only pseudo registers used by
10262 the ARM target at the moment. If more are added, a
10263 little more care in numbering will be needed. */
10265 int num_pseudos = 32;
10266 if (have_neon_pseudos)
10268 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10269 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10270 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10275 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10277 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10279 /* Override tdesc_register_type to adjust the types of VFP
10280 registers for NEON. */
10281 set_gdbarch_register_type (gdbarch, arm_register_type);
10284 /* Add standard register aliases. We add aliases even for those
10285 nanes which are used by the current architecture - it's simpler,
10286 and does no harm, since nothing ever lists user registers. */
10287 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10288 user_reg_add (gdbarch, arm_register_aliases[i].name,
10289 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10295 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10302 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10303 (unsigned long) tdep->lowest_pc);
10306 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10309 _initialize_arm_tdep (void)
10311 struct ui_file *stb;
10313 struct cmd_list_element *new_set, *new_show;
10314 const char *setname;
10315 const char *setdesc;
10316 const char *const *regnames;
10318 static char *helptext;
10319 char regdesc[1024], *rdptr = regdesc;
10320 size_t rest = sizeof (regdesc);
10322 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10324 arm_objfile_data_key
10325 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10327 /* Add ourselves to objfile event chain. */
10328 observer_attach_new_objfile (arm_exidx_new_objfile);
10330 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10332 /* Register an ELF OS ABI sniffer for ARM binaries. */
10333 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10334 bfd_target_elf_flavour,
10335 arm_elf_osabi_sniffer);
10337 /* Initialize the standard target descriptions. */
10338 initialize_tdesc_arm_with_m ();
10339 initialize_tdesc_arm_with_m_fpa_layout ();
10340 initialize_tdesc_arm_with_m_vfp_d16 ();
10341 initialize_tdesc_arm_with_iwmmxt ();
10342 initialize_tdesc_arm_with_vfpv2 ();
10343 initialize_tdesc_arm_with_vfpv3 ();
10344 initialize_tdesc_arm_with_neon ();
10346 /* Get the number of possible sets of register names defined in opcodes. */
10347 num_disassembly_options = get_arm_regname_num_options ();
10349 /* Add root prefix command for all "set arm"/"show arm" commands. */
10350 add_prefix_cmd ("arm", no_class, set_arm_command,
10351 _("Various ARM-specific commands."),
10352 &setarmcmdlist, "set arm ", 0, &setlist);
10354 add_prefix_cmd ("arm", no_class, show_arm_command,
10355 _("Various ARM-specific commands."),
10356 &showarmcmdlist, "show arm ", 0, &showlist);
10358 /* Sync the opcode insn printer with our register viewer. */
10359 parse_arm_disassembler_option ("reg-names-std");
10361 /* Initialize the array that will be passed to
10362 add_setshow_enum_cmd(). */
10363 valid_disassembly_styles
10364 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10365 for (i = 0; i < num_disassembly_options; i++)
10367 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10368 valid_disassembly_styles[i] = setname;
10369 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10372 /* When we find the default names, tell the disassembler to use
10374 if (!strcmp (setname, "std"))
10376 disassembly_style = setname;
10377 set_arm_regname_option (i);
10380 /* Mark the end of valid options. */
10381 valid_disassembly_styles[num_disassembly_options] = NULL;
10383 /* Create the help text. */
10384 stb = mem_fileopen ();
10385 fprintf_unfiltered (stb, "%s%s%s",
10386 _("The valid values are:\n"),
10388 _("The default is \"std\"."));
10389 helptext = ui_file_xstrdup (stb, NULL);
10390 ui_file_delete (stb);
10392 add_setshow_enum_cmd("disassembler", no_class,
10393 valid_disassembly_styles, &disassembly_style,
10394 _("Set the disassembly style."),
10395 _("Show the disassembly style."),
10397 set_disassembly_style_sfunc,
10398 NULL, /* FIXME: i18n: The disassembly style is
10400 &setarmcmdlist, &showarmcmdlist);
10402 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10403 _("Set usage of ARM 32-bit mode."),
10404 _("Show usage of ARM 32-bit mode."),
10405 _("When off, a 26-bit PC will be used."),
10407 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10409 &setarmcmdlist, &showarmcmdlist);
10411 /* Add a command to allow the user to force the FPU model. */
10412 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10413 _("Set the floating point type."),
10414 _("Show the floating point type."),
10415 _("auto - Determine the FP typefrom the OS-ABI.\n\
10416 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10417 fpa - FPA co-processor (GCC compiled).\n\
10418 softvfp - Software FP with pure-endian doubles.\n\
10419 vfp - VFP co-processor."),
10420 set_fp_model_sfunc, show_fp_model,
10421 &setarmcmdlist, &showarmcmdlist);
10423 /* Add a command to allow the user to force the ABI. */
10424 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10426 _("Show the ABI."),
10427 NULL, arm_set_abi, arm_show_abi,
10428 &setarmcmdlist, &showarmcmdlist);
10430 /* Add two commands to allow the user to force the assumed
10432 add_setshow_enum_cmd ("fallback-mode", class_support,
10433 arm_mode_strings, &arm_fallback_mode_string,
10434 _("Set the mode assumed when symbols are unavailable."),
10435 _("Show the mode assumed when symbols are unavailable."),
10436 NULL, NULL, arm_show_fallback_mode,
10437 &setarmcmdlist, &showarmcmdlist);
10438 add_setshow_enum_cmd ("force-mode", class_support,
10439 arm_mode_strings, &arm_force_mode_string,
10440 _("Set the mode assumed even when symbols are available."),
10441 _("Show the mode assumed even when symbols are available."),
10442 NULL, NULL, arm_show_force_mode,
10443 &setarmcmdlist, &showarmcmdlist);
10445 /* Debugging flag. */
10446 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10447 _("Set ARM debugging."),
10448 _("Show ARM debugging."),
10449 _("When on, arm-specific debugging is enabled."),
10451 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10452 &setdebuglist, &showdebuglist);
10455 /* ARM-reversible process record data structures. */
10457 #define ARM_INSN_SIZE_BYTES 4
10458 #define THUMB_INSN_SIZE_BYTES 2
10459 #define THUMB2_INSN_SIZE_BYTES 4
10462 #define INSN_S_L_BIT_NUM 20
10464 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10467 unsigned int reg_len = LENGTH; \
10470 REGS = XNEWVEC (uint32_t, reg_len); \
10471 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10476 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10479 unsigned int mem_len = LENGTH; \
10482 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10483 memcpy(&MEMS->len, &RECORD_BUF[0], \
10484 sizeof(struct arm_mem_r) * LENGTH); \
10489 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10490 #define INSN_RECORDED(ARM_RECORD) \
10491 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10493 /* ARM memory record structure. */
10496 uint32_t len; /* Record length. */
10497 CORE_ADDR addr; /* Memory address. */
10500 /* ARM instruction record contains opcode of current insn
10501 and execution state (before entry to decode_insn()),
10502 contains list of to-be-modified registers and
10503 memory blocks (on return from decode_insn()). */
10505 typedef struct insn_decode_record_t
10507 struct gdbarch *gdbarch;
10508 struct regcache *regcache;
10509 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10510 uint32_t arm_insn; /* Should accommodate thumb. */
10511 uint32_t cond; /* Condition code. */
10512 uint32_t opcode; /* Insn opcode. */
10513 uint32_t decode; /* Insn decode bits. */
10514 uint32_t mem_rec_count; /* No of mem records. */
10515 uint32_t reg_rec_count; /* No of reg records. */
10516 uint32_t *arm_regs; /* Registers to be saved for this record. */
10517 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10518 } insn_decode_record;
10521 /* Checks ARM SBZ and SBO mandatory fields. */
10524 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10526 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10549 } arm_record_strx_t;
10560 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10561 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10564 struct regcache *reg_cache = arm_insn_r->regcache;
10565 ULONGEST u_regval[2]= {0};
10567 uint32_t reg_src1 = 0, reg_src2 = 0;
10568 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10569 uint32_t opcode1 = 0;
10571 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10572 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10573 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10576 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10578 /* 1) Handle misc store, immediate offset. */
10579 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10580 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10581 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10582 regcache_raw_read_unsigned (reg_cache, reg_src1,
10584 if (ARM_PC_REGNUM == reg_src1)
10586 /* If R15 was used as Rn, hence current PC+8. */
10587 u_regval[0] = u_regval[0] + 8;
10589 offset_8 = (immed_high << 4) | immed_low;
10590 /* Calculate target store address. */
10591 if (14 == arm_insn_r->opcode)
10593 tgt_mem_addr = u_regval[0] + offset_8;
10597 tgt_mem_addr = u_regval[0] - offset_8;
10599 if (ARM_RECORD_STRH == str_type)
10601 record_buf_mem[0] = 2;
10602 record_buf_mem[1] = tgt_mem_addr;
10603 arm_insn_r->mem_rec_count = 1;
10605 else if (ARM_RECORD_STRD == str_type)
10607 record_buf_mem[0] = 4;
10608 record_buf_mem[1] = tgt_mem_addr;
10609 record_buf_mem[2] = 4;
10610 record_buf_mem[3] = tgt_mem_addr + 4;
10611 arm_insn_r->mem_rec_count = 2;
10614 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10616 /* 2) Store, register offset. */
10618 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10620 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10621 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10622 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10623 if (15 == reg_src2)
10625 /* If R15 was used as Rn, hence current PC+8. */
10626 u_regval[0] = u_regval[0] + 8;
10628 /* Calculate target store address, Rn +/- Rm, register offset. */
10629 if (12 == arm_insn_r->opcode)
10631 tgt_mem_addr = u_regval[0] + u_regval[1];
10635 tgt_mem_addr = u_regval[1] - u_regval[0];
10637 if (ARM_RECORD_STRH == str_type)
10639 record_buf_mem[0] = 2;
10640 record_buf_mem[1] = tgt_mem_addr;
10641 arm_insn_r->mem_rec_count = 1;
10643 else if (ARM_RECORD_STRD == str_type)
10645 record_buf_mem[0] = 4;
10646 record_buf_mem[1] = tgt_mem_addr;
10647 record_buf_mem[2] = 4;
10648 record_buf_mem[3] = tgt_mem_addr + 4;
10649 arm_insn_r->mem_rec_count = 2;
10652 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10653 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10655 /* 3) Store, immediate pre-indexed. */
10656 /* 5) Store, immediate post-indexed. */
10657 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10658 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10659 offset_8 = (immed_high << 4) | immed_low;
10660 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10661 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10662 /* Calculate target store address, Rn +/- Rm, register offset. */
10663 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10665 tgt_mem_addr = u_regval[0] + offset_8;
10669 tgt_mem_addr = u_regval[0] - offset_8;
10671 if (ARM_RECORD_STRH == str_type)
10673 record_buf_mem[0] = 2;
10674 record_buf_mem[1] = tgt_mem_addr;
10675 arm_insn_r->mem_rec_count = 1;
10677 else if (ARM_RECORD_STRD == str_type)
10679 record_buf_mem[0] = 4;
10680 record_buf_mem[1] = tgt_mem_addr;
10681 record_buf_mem[2] = 4;
10682 record_buf_mem[3] = tgt_mem_addr + 4;
10683 arm_insn_r->mem_rec_count = 2;
10685 /* Record Rn also as it changes. */
10686 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10687 arm_insn_r->reg_rec_count = 1;
10689 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10690 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10692 /* 4) Store, register pre-indexed. */
10693 /* 6) Store, register post -indexed. */
10694 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10695 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10696 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10697 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10698 /* Calculate target store address, Rn +/- Rm, register offset. */
10699 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10701 tgt_mem_addr = u_regval[0] + u_regval[1];
10705 tgt_mem_addr = u_regval[1] - u_regval[0];
10707 if (ARM_RECORD_STRH == str_type)
10709 record_buf_mem[0] = 2;
10710 record_buf_mem[1] = tgt_mem_addr;
10711 arm_insn_r->mem_rec_count = 1;
10713 else if (ARM_RECORD_STRD == str_type)
10715 record_buf_mem[0] = 4;
10716 record_buf_mem[1] = tgt_mem_addr;
10717 record_buf_mem[2] = 4;
10718 record_buf_mem[3] = tgt_mem_addr + 4;
10719 arm_insn_r->mem_rec_count = 2;
10721 /* Record Rn also as it changes. */
10722 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10723 arm_insn_r->reg_rec_count = 1;
10728 /* Handling ARM extension space insns. */
10731 arm_record_extension_space (insn_decode_record *arm_insn_r)
10733 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10734 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10735 uint32_t record_buf[8], record_buf_mem[8];
10736 uint32_t reg_src1 = 0;
10737 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10738 struct regcache *reg_cache = arm_insn_r->regcache;
10739 ULONGEST u_regval = 0;
10741 gdb_assert (!INSN_RECORDED(arm_insn_r));
10742 /* Handle unconditional insn extension space. */
10744 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10745 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10746 if (arm_insn_r->cond)
10748 /* PLD has no affect on architectural state, it just affects
10750 if (5 == ((opcode1 & 0xE0) >> 5))
10753 record_buf[0] = ARM_PS_REGNUM;
10754 record_buf[1] = ARM_LR_REGNUM;
10755 arm_insn_r->reg_rec_count = 2;
10757 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10761 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10762 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10765 /* Undefined instruction on ARM V5; need to handle if later
10766 versions define it. */
10769 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10770 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10771 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10773 /* Handle arithmetic insn extension space. */
10774 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10775 && !INSN_RECORDED(arm_insn_r))
10777 /* Handle MLA(S) and MUL(S). */
10778 if (0 <= insn_op1 && 3 >= insn_op1)
10780 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10781 record_buf[1] = ARM_PS_REGNUM;
10782 arm_insn_r->reg_rec_count = 2;
10784 else if (4 <= insn_op1 && 15 >= insn_op1)
10786 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10787 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10788 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10789 record_buf[2] = ARM_PS_REGNUM;
10790 arm_insn_r->reg_rec_count = 3;
10794 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10795 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10796 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10798 /* Handle control insn extension space. */
10800 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10801 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10803 if (!bit (arm_insn_r->arm_insn,25))
10805 if (!bits (arm_insn_r->arm_insn, 4, 7))
10807 if ((0 == insn_op1) || (2 == insn_op1))
10810 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10811 arm_insn_r->reg_rec_count = 1;
10813 else if (1 == insn_op1)
10815 /* CSPR is going to be changed. */
10816 record_buf[0] = ARM_PS_REGNUM;
10817 arm_insn_r->reg_rec_count = 1;
10819 else if (3 == insn_op1)
10821 /* SPSR is going to be changed. */
10822 /* We need to get SPSR value, which is yet to be done. */
10823 printf_unfiltered (_("Process record does not support "
10824 "instruction 0x%0x at address %s.\n"),
10825 arm_insn_r->arm_insn,
10826 paddress (arm_insn_r->gdbarch,
10827 arm_insn_r->this_addr));
10831 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10836 record_buf[0] = ARM_PS_REGNUM;
10837 arm_insn_r->reg_rec_count = 1;
10839 else if (3 == insn_op1)
10842 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10843 arm_insn_r->reg_rec_count = 1;
10846 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10849 record_buf[0] = ARM_PS_REGNUM;
10850 record_buf[1] = ARM_LR_REGNUM;
10851 arm_insn_r->reg_rec_count = 2;
10853 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10855 /* QADD, QSUB, QDADD, QDSUB */
10856 record_buf[0] = ARM_PS_REGNUM;
10857 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10858 arm_insn_r->reg_rec_count = 2;
10860 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10863 record_buf[0] = ARM_PS_REGNUM;
10864 record_buf[1] = ARM_LR_REGNUM;
10865 arm_insn_r->reg_rec_count = 2;
10867 /* Save SPSR also;how? */
10868 printf_unfiltered (_("Process record does not support "
10869 "instruction 0x%0x at address %s.\n"),
10870 arm_insn_r->arm_insn,
10871 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
10874 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
10875 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
10876 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
10877 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
10880 if (0 == insn_op1 || 1 == insn_op1)
10882 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10883 /* We dont do optimization for SMULW<y> where we
10885 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10886 record_buf[1] = ARM_PS_REGNUM;
10887 arm_insn_r->reg_rec_count = 2;
10889 else if (2 == insn_op1)
10892 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10893 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
10894 arm_insn_r->reg_rec_count = 2;
10896 else if (3 == insn_op1)
10899 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10900 arm_insn_r->reg_rec_count = 1;
10906 /* MSR : immediate form. */
10909 /* CSPR is going to be changed. */
10910 record_buf[0] = ARM_PS_REGNUM;
10911 arm_insn_r->reg_rec_count = 1;
10913 else if (3 == insn_op1)
10915 /* SPSR is going to be changed. */
10916 /* we need to get SPSR value, which is yet to be done */
10917 printf_unfiltered (_("Process record does not support "
10918 "instruction 0x%0x at address %s.\n"),
10919 arm_insn_r->arm_insn,
10920 paddress (arm_insn_r->gdbarch,
10921 arm_insn_r->this_addr));
10927 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10928 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
10929 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
10931 /* Handle load/store insn extension space. */
10933 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
10934 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
10935 && !INSN_RECORDED(arm_insn_r))
10940 /* These insn, changes register and memory as well. */
10941 /* SWP or SWPB insn. */
10942 /* Get memory address given by Rn. */
10943 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10944 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
10945 /* SWP insn ?, swaps word. */
10946 if (8 == arm_insn_r->opcode)
10948 record_buf_mem[0] = 4;
10952 /* SWPB insn, swaps only byte. */
10953 record_buf_mem[0] = 1;
10955 record_buf_mem[1] = u_regval;
10956 arm_insn_r->mem_rec_count = 1;
10957 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10958 arm_insn_r->reg_rec_count = 1;
10960 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10963 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10966 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10969 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10970 record_buf[1] = record_buf[0] + 1;
10971 arm_insn_r->reg_rec_count = 2;
10973 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10976 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10979 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
10981 /* LDRH, LDRSB, LDRSH. */
10982 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10983 arm_insn_r->reg_rec_count = 1;
10988 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
10989 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
10990 && !INSN_RECORDED(arm_insn_r))
10993 /* Handle coprocessor insn extension space. */
10996 /* To be done for ARMv5 and later; as of now we return -1. */
10998 printf_unfiltered (_("Process record does not support instruction x%0x "
10999 "at address %s.\n"),arm_insn_r->arm_insn,
11000 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11003 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11004 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11009 /* Handling opcode 000 insns. */
11012 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11014 struct regcache *reg_cache = arm_insn_r->regcache;
11015 uint32_t record_buf[8], record_buf_mem[8];
11016 ULONGEST u_regval[2] = {0};
11018 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11019 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11020 uint32_t opcode1 = 0;
11022 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11023 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11024 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11026 /* Data processing insn /multiply insn. */
11027 if (9 == arm_insn_r->decode
11028 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11029 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11031 /* Handle multiply instructions. */
11032 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11033 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11035 /* Handle MLA and MUL. */
11036 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11037 record_buf[1] = ARM_PS_REGNUM;
11038 arm_insn_r->reg_rec_count = 2;
11040 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11042 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11043 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11044 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11045 record_buf[2] = ARM_PS_REGNUM;
11046 arm_insn_r->reg_rec_count = 3;
11049 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11050 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11052 /* Handle misc load insns, as 20th bit (L = 1). */
11053 /* LDR insn has a capability to do branching, if
11054 MOV LR, PC is precceded by LDR insn having Rn as R15
11055 in that case, it emulates branch and link insn, and hence we
11056 need to save CSPR and PC as well. I am not sure this is right
11057 place; as opcode = 010 LDR insn make this happen, if R15 was
11059 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11060 if (15 != reg_dest)
11062 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11063 arm_insn_r->reg_rec_count = 1;
11067 record_buf[0] = reg_dest;
11068 record_buf[1] = ARM_PS_REGNUM;
11069 arm_insn_r->reg_rec_count = 2;
11072 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11073 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11074 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11075 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11077 /* Handle MSR insn. */
11078 if (9 == arm_insn_r->opcode)
11080 /* CSPR is going to be changed. */
11081 record_buf[0] = ARM_PS_REGNUM;
11082 arm_insn_r->reg_rec_count = 1;
11086 /* SPSR is going to be changed. */
11087 /* How to read SPSR value? */
11088 printf_unfiltered (_("Process record does not support instruction "
11089 "0x%0x at address %s.\n"),
11090 arm_insn_r->arm_insn,
11091 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11095 else if (9 == arm_insn_r->decode
11096 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11097 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11099 /* Handling SWP, SWPB. */
11100 /* These insn, changes register and memory as well. */
11101 /* SWP or SWPB insn. */
11103 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11104 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11105 /* SWP insn ?, swaps word. */
11106 if (8 == arm_insn_r->opcode)
11108 record_buf_mem[0] = 4;
11112 /* SWPB insn, swaps only byte. */
11113 record_buf_mem[0] = 1;
11115 record_buf_mem[1] = u_regval[0];
11116 arm_insn_r->mem_rec_count = 1;
11117 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11118 arm_insn_r->reg_rec_count = 1;
11120 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11121 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11123 /* Handle BLX, branch and link/exchange. */
11124 if (9 == arm_insn_r->opcode)
11126 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11127 and R14 stores the return address. */
11128 record_buf[0] = ARM_PS_REGNUM;
11129 record_buf[1] = ARM_LR_REGNUM;
11130 arm_insn_r->reg_rec_count = 2;
11133 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11135 /* Handle enhanced software breakpoint insn, BKPT. */
11136 /* CPSR is changed to be executed in ARM state, disabling normal
11137 interrupts, entering abort mode. */
11138 /* According to high vector configuration PC is set. */
11139 /* user hit breakpoint and type reverse, in
11140 that case, we need to go back with previous CPSR and
11141 Program Counter. */
11142 record_buf[0] = ARM_PS_REGNUM;
11143 record_buf[1] = ARM_LR_REGNUM;
11144 arm_insn_r->reg_rec_count = 2;
11146 /* Save SPSR also; how? */
11147 printf_unfiltered (_("Process record does not support instruction "
11148 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11149 paddress (arm_insn_r->gdbarch,
11150 arm_insn_r->this_addr));
11153 else if (11 == arm_insn_r->decode
11154 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11156 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11158 /* Handle str(x) insn */
11159 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11162 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11163 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11165 /* Handle BX, branch and link/exchange. */
11166 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11167 record_buf[0] = ARM_PS_REGNUM;
11168 arm_insn_r->reg_rec_count = 1;
11170 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11171 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11172 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11174 /* Count leading zeros: CLZ. */
11175 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11176 arm_insn_r->reg_rec_count = 1;
11178 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11179 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11180 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11181 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11184 /* Handle MRS insn. */
11185 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11186 arm_insn_r->reg_rec_count = 1;
11188 else if (arm_insn_r->opcode <= 15)
11190 /* Normal data processing insns. */
11191 /* Out of 11 shifter operands mode, all the insn modifies destination
11192 register, which is specified by 13-16 decode. */
11193 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11194 record_buf[1] = ARM_PS_REGNUM;
11195 arm_insn_r->reg_rec_count = 2;
11202 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11203 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11207 /* Handling opcode 001 insns. */
11210 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11212 uint32_t record_buf[8], record_buf_mem[8];
11214 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11215 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11217 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11218 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11219 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11222 /* Handle MSR insn. */
11223 if (9 == arm_insn_r->opcode)
11225 /* CSPR is going to be changed. */
11226 record_buf[0] = ARM_PS_REGNUM;
11227 arm_insn_r->reg_rec_count = 1;
11231 /* SPSR is going to be changed. */
11234 else if (arm_insn_r->opcode <= 15)
11236 /* Normal data processing insns. */
11237 /* Out of 11 shifter operands mode, all the insn modifies destination
11238 register, which is specified by 13-16 decode. */
11239 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11240 record_buf[1] = ARM_PS_REGNUM;
11241 arm_insn_r->reg_rec_count = 2;
11248 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11249 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11253 /* Handling opcode 010 insns. */
11256 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11258 struct regcache *reg_cache = arm_insn_r->regcache;
11260 uint32_t reg_src1 = 0 , reg_dest = 0;
11261 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11262 uint32_t record_buf[8], record_buf_mem[8];
11264 ULONGEST u_regval = 0;
11266 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11267 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11269 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11271 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11272 /* LDR insn has a capability to do branching, if
11273 MOV LR, PC is precedded by LDR insn having Rn as R15
11274 in that case, it emulates branch and link insn, and hence we
11275 need to save CSPR and PC as well. */
11276 if (ARM_PC_REGNUM != reg_dest)
11278 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11279 arm_insn_r->reg_rec_count = 1;
11283 record_buf[0] = reg_dest;
11284 record_buf[1] = ARM_PS_REGNUM;
11285 arm_insn_r->reg_rec_count = 2;
11290 /* Store, immediate offset, immediate pre-indexed,
11291 immediate post-indexed. */
11292 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11293 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11294 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11296 if (bit (arm_insn_r->arm_insn, 23))
11298 tgt_mem_addr = u_regval + offset_12;
11302 tgt_mem_addr = u_regval - offset_12;
11305 switch (arm_insn_r->opcode)
11319 record_buf_mem[0] = 4;
11334 record_buf_mem[0] = 1;
11338 gdb_assert_not_reached ("no decoding pattern found");
11341 record_buf_mem[1] = tgt_mem_addr;
11342 arm_insn_r->mem_rec_count = 1;
11344 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11345 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11346 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11347 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11348 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11349 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11352 /* We are handling pre-indexed mode; post-indexed mode;
11353 where Rn is going to be changed. */
11354 record_buf[0] = reg_src1;
11355 arm_insn_r->reg_rec_count = 1;
11359 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11360 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11364 /* Handling opcode 011 insns. */
11367 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11369 struct regcache *reg_cache = arm_insn_r->regcache;
11371 uint32_t shift_imm = 0;
11372 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11373 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11374 uint32_t record_buf[8], record_buf_mem[8];
11377 ULONGEST u_regval[2];
11379 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11380 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11382 /* Handle enhanced store insns and LDRD DSP insn,
11383 order begins according to addressing modes for store insns
11387 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11389 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11390 /* LDR insn has a capability to do branching, if
11391 MOV LR, PC is precedded by LDR insn having Rn as R15
11392 in that case, it emulates branch and link insn, and hence we
11393 need to save CSPR and PC as well. */
11394 if (15 != reg_dest)
11396 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11397 arm_insn_r->reg_rec_count = 1;
11401 record_buf[0] = reg_dest;
11402 record_buf[1] = ARM_PS_REGNUM;
11403 arm_insn_r->reg_rec_count = 2;
11408 if (! bits (arm_insn_r->arm_insn, 4, 11))
11410 /* Store insn, register offset and register pre-indexed,
11411 register post-indexed. */
11413 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11415 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11416 regcache_raw_read_unsigned (reg_cache, reg_src1
11418 regcache_raw_read_unsigned (reg_cache, reg_src2
11420 if (15 == reg_src2)
11422 /* If R15 was used as Rn, hence current PC+8. */
11423 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11424 u_regval[0] = u_regval[0] + 8;
11426 /* Calculate target store address, Rn +/- Rm, register offset. */
11428 if (bit (arm_insn_r->arm_insn, 23))
11430 tgt_mem_addr = u_regval[0] + u_regval[1];
11434 tgt_mem_addr = u_regval[1] - u_regval[0];
11437 switch (arm_insn_r->opcode)
11451 record_buf_mem[0] = 4;
11466 record_buf_mem[0] = 1;
11470 gdb_assert_not_reached ("no decoding pattern found");
11473 record_buf_mem[1] = tgt_mem_addr;
11474 arm_insn_r->mem_rec_count = 1;
11476 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11477 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11478 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11479 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11480 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11481 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11484 /* Rn is going to be changed in pre-indexed mode and
11485 post-indexed mode as well. */
11486 record_buf[0] = reg_src2;
11487 arm_insn_r->reg_rec_count = 1;
11492 /* Store insn, scaled register offset; scaled pre-indexed. */
11493 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11495 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11497 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11498 /* Get shift_imm. */
11499 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11500 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11501 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11502 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11503 /* Offset_12 used as shift. */
11507 /* Offset_12 used as index. */
11508 offset_12 = u_regval[0] << shift_imm;
11512 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11518 if (bit (u_regval[0], 31))
11520 offset_12 = 0xFFFFFFFF;
11529 /* This is arithmetic shift. */
11530 offset_12 = s_word >> shift_imm;
11537 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11539 /* Get C flag value and shift it by 31. */
11540 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11541 | (u_regval[0]) >> 1);
11545 offset_12 = (u_regval[0] >> shift_imm) \
11547 (sizeof(uint32_t) - shift_imm));
11552 gdb_assert_not_reached ("no decoding pattern found");
11556 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11558 if (bit (arm_insn_r->arm_insn, 23))
11560 tgt_mem_addr = u_regval[1] + offset_12;
11564 tgt_mem_addr = u_regval[1] - offset_12;
11567 switch (arm_insn_r->opcode)
11581 record_buf_mem[0] = 4;
11596 record_buf_mem[0] = 1;
11600 gdb_assert_not_reached ("no decoding pattern found");
11603 record_buf_mem[1] = tgt_mem_addr;
11604 arm_insn_r->mem_rec_count = 1;
11606 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11607 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11608 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11609 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11610 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11611 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11614 /* Rn is going to be changed in register scaled pre-indexed
11615 mode,and scaled post indexed mode. */
11616 record_buf[0] = reg_src2;
11617 arm_insn_r->reg_rec_count = 1;
11622 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11623 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11627 /* Handling opcode 100 insns. */
11630 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11632 struct regcache *reg_cache = arm_insn_r->regcache;
11634 uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0;
11635 uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0;
11636 uint32_t start_address = 0, index = 0;
11637 uint32_t record_buf[24], record_buf_mem[48];
11639 ULONGEST u_regval[2] = {0};
11641 /* This mode is exclusively for load and store multiple. */
11642 /* Handle incremenrt after/before and decrment after.before mode;
11643 Rn is changing depending on W bit, but as of now we store Rn too
11644 without optimization. */
11646 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11648 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11650 if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22))
11652 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11657 register_bits = bits (arm_insn_r->arm_insn, 0, 14);
11661 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11662 while (register_bits)
11664 if (register_bits & 0x00000001)
11665 register_list[register_count++] = 1;
11666 register_bits = register_bits >> 1;
11669 /* Extra space for Base Register and CPSR; wihtout optimization. */
11670 record_buf[register_count] = reg_src1;
11671 record_buf[register_count + 1] = ARM_PS_REGNUM;
11672 arm_insn_r->reg_rec_count = register_count + 2;
11674 for (register_count = 0; register_count < no_of_regs; register_count++)
11676 if (register_list[register_count])
11678 /* Register_count gives total no of registers
11679 and dually working as reg number. */
11680 record_buf[index] = register_count;
11688 /* It handles both STM(1) and STM(2). */
11689 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11691 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11693 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11694 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11695 while (register_bits)
11697 if (register_bits & 0x00000001)
11699 register_bits = register_bits >> 1;
11704 /* Decrement after. */
11706 start_address = (u_regval[0]) - (register_count * 4) + 4;
11707 arm_insn_r->mem_rec_count = register_count;
11708 while (register_count)
11710 record_buf_mem[(register_count * 2) - 1] = start_address;
11711 record_buf_mem[(register_count * 2) - 2] = 4;
11712 start_address = start_address + 4;
11717 /* Increment after. */
11719 start_address = u_regval[0];
11720 arm_insn_r->mem_rec_count = register_count;
11721 while (register_count)
11723 record_buf_mem[(register_count * 2) - 1] = start_address;
11724 record_buf_mem[(register_count * 2) - 2] = 4;
11725 start_address = start_address + 4;
11730 /* Decrement before. */
11733 start_address = (u_regval[0]) - (register_count * 4);
11734 arm_insn_r->mem_rec_count = register_count;
11735 while (register_count)
11737 record_buf_mem[(register_count * 2) - 1] = start_address;
11738 record_buf_mem[(register_count * 2) - 2] = 4;
11739 start_address = start_address + 4;
11744 /* Increment before. */
11746 start_address = u_regval[0] + 4;
11747 arm_insn_r->mem_rec_count = register_count;
11748 while (register_count)
11750 record_buf_mem[(register_count * 2) - 1] = start_address;
11751 record_buf_mem[(register_count * 2) - 2] = 4;
11752 start_address = start_address + 4;
11758 gdb_assert_not_reached ("no decoding pattern found");
11762 /* Base register also changes; based on condition and W bit. */
11763 /* We save it anyway without optimization. */
11764 record_buf[0] = reg_src1;
11765 arm_insn_r->reg_rec_count = 1;
11768 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11769 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11773 /* Handling opcode 101 insns. */
11776 arm_record_b_bl (insn_decode_record *arm_insn_r)
11778 uint32_t record_buf[8];
11780 /* Handle B, BL, BLX(1) insns. */
11781 /* B simply branches so we do nothing here. */
11782 /* Note: BLX(1) doesnt fall here but instead it falls into
11783 extension space. */
11784 if (bit (arm_insn_r->arm_insn, 24))
11786 record_buf[0] = ARM_LR_REGNUM;
11787 arm_insn_r->reg_rec_count = 1;
11790 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11795 /* Handling opcode 110 insns. */
11798 arm_record_coproc (insn_decode_record *arm_insn_r)
11800 printf_unfiltered (_("Process record does not support instruction "
11801 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11802 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11807 /* Handling opcode 111 insns. */
11810 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11812 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11813 struct regcache *reg_cache = arm_insn_r->regcache;
11814 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
11816 /* Handle SWI insn; system call would be handled over here. */
11818 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11819 if (15 == arm_insn_r->opcode)
11821 /* Handle arm syscall insn. */
11822 if (tdep->arm_swi_record != NULL)
11824 ret = tdep->arm_swi_record(reg_cache);
11828 printf_unfiltered (_("no syscall record support\n"));
11833 printf_unfiltered (_("Process record does not support instruction "
11834 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11835 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11839 /* Handling opcode 000 insns. */
11842 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11844 uint32_t record_buf[8];
11845 uint32_t reg_src1 = 0;
11847 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11849 record_buf[0] = ARM_PS_REGNUM;
11850 record_buf[1] = reg_src1;
11851 thumb_insn_r->reg_rec_count = 2;
11853 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11859 /* Handling opcode 001 insns. */
11862 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11864 uint32_t record_buf[8];
11865 uint32_t reg_src1 = 0;
11867 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11869 record_buf[0] = ARM_PS_REGNUM;
11870 record_buf[1] = reg_src1;
11871 thumb_insn_r->reg_rec_count = 2;
11873 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11878 /* Handling opcode 010 insns. */
11881 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
11883 struct regcache *reg_cache = thumb_insn_r->regcache;
11884 uint32_t record_buf[8], record_buf_mem[8];
11886 uint32_t reg_src1 = 0, reg_src2 = 0;
11887 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
11889 ULONGEST u_regval[2] = {0};
11891 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
11893 if (bit (thumb_insn_r->arm_insn, 12))
11895 /* Handle load/store register offset. */
11896 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
11897 if (opcode2 >= 12 && opcode2 <= 15)
11899 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11900 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
11901 record_buf[0] = reg_src1;
11902 thumb_insn_r->reg_rec_count = 1;
11904 else if (opcode2 >= 8 && opcode2 <= 10)
11906 /* STR(2), STRB(2), STRH(2) . */
11907 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11908 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
11909 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11910 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11912 record_buf_mem[0] = 4; /* STR (2). */
11913 else if (10 == opcode2)
11914 record_buf_mem[0] = 1; /* STRB (2). */
11915 else if (9 == opcode2)
11916 record_buf_mem[0] = 2; /* STRH (2). */
11917 record_buf_mem[1] = u_regval[0] + u_regval[1];
11918 thumb_insn_r->mem_rec_count = 1;
11921 else if (bit (thumb_insn_r->arm_insn, 11))
11923 /* Handle load from literal pool. */
11925 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11926 record_buf[0] = reg_src1;
11927 thumb_insn_r->reg_rec_count = 1;
11931 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
11932 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
11933 if ((3 == opcode2) && (!opcode3))
11935 /* Branch with exchange. */
11936 record_buf[0] = ARM_PS_REGNUM;
11937 thumb_insn_r->reg_rec_count = 1;
11941 /* Format 8; special data processing insns. */
11942 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11943 record_buf[0] = ARM_PS_REGNUM;
11944 record_buf[1] = reg_src1;
11945 thumb_insn_r->reg_rec_count = 2;
11950 /* Format 5; data processing insns. */
11951 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11952 if (bit (thumb_insn_r->arm_insn, 7))
11954 reg_src1 = reg_src1 + 8;
11956 record_buf[0] = ARM_PS_REGNUM;
11957 record_buf[1] = reg_src1;
11958 thumb_insn_r->reg_rec_count = 2;
11961 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11962 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11968 /* Handling opcode 001 insns. */
11971 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
11973 struct regcache *reg_cache = thumb_insn_r->regcache;
11974 uint32_t record_buf[8], record_buf_mem[8];
11976 uint32_t reg_src1 = 0;
11977 uint32_t opcode = 0, immed_5 = 0;
11979 ULONGEST u_regval = 0;
11981 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11986 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11987 record_buf[0] = reg_src1;
11988 thumb_insn_r->reg_rec_count = 1;
11993 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11994 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11995 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11996 record_buf_mem[0] = 4;
11997 record_buf_mem[1] = u_regval + (immed_5 * 4);
11998 thumb_insn_r->mem_rec_count = 1;
12001 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12002 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12008 /* Handling opcode 100 insns. */
12011 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12013 struct regcache *reg_cache = thumb_insn_r->regcache;
12014 uint32_t record_buf[8], record_buf_mem[8];
12016 uint32_t reg_src1 = 0;
12017 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12019 ULONGEST u_regval = 0;
12021 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12026 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12027 record_buf[0] = reg_src1;
12028 thumb_insn_r->reg_rec_count = 1;
12030 else if (1 == opcode)
12033 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12034 record_buf[0] = reg_src1;
12035 thumb_insn_r->reg_rec_count = 1;
12037 else if (2 == opcode)
12040 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12041 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12042 record_buf_mem[0] = 4;
12043 record_buf_mem[1] = u_regval + (immed_8 * 4);
12044 thumb_insn_r->mem_rec_count = 1;
12046 else if (0 == opcode)
12049 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12050 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12051 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12052 record_buf_mem[0] = 2;
12053 record_buf_mem[1] = u_regval + (immed_5 * 2);
12054 thumb_insn_r->mem_rec_count = 1;
12057 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12058 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12064 /* Handling opcode 101 insns. */
12067 thumb_record_misc (insn_decode_record *thumb_insn_r)
12069 struct regcache *reg_cache = thumb_insn_r->regcache;
12071 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12072 uint32_t register_bits = 0, register_count = 0;
12073 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12074 uint32_t record_buf[24], record_buf_mem[48];
12077 ULONGEST u_regval = 0;
12079 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12080 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12081 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12086 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12087 while (register_bits)
12089 if (register_bits & 0x00000001)
12090 register_list[register_count++] = 1;
12091 register_bits = register_bits >> 1;
12093 record_buf[register_count] = ARM_PS_REGNUM;
12094 record_buf[register_count + 1] = ARM_SP_REGNUM;
12095 thumb_insn_r->reg_rec_count = register_count + 2;
12096 for (register_count = 0; register_count < 8; register_count++)
12098 if (register_list[register_count])
12100 record_buf[index] = register_count;
12105 else if (10 == opcode2)
12108 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12109 regcache_raw_read_unsigned (reg_cache, ARM_PC_REGNUM, &u_regval);
12110 while (register_bits)
12112 if (register_bits & 0x00000001)
12114 register_bits = register_bits >> 1;
12116 start_address = u_regval - \
12117 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12118 thumb_insn_r->mem_rec_count = register_count;
12119 while (register_count)
12121 record_buf_mem[(register_count * 2) - 1] = start_address;
12122 record_buf_mem[(register_count * 2) - 2] = 4;
12123 start_address = start_address + 4;
12126 record_buf[0] = ARM_SP_REGNUM;
12127 thumb_insn_r->reg_rec_count = 1;
12129 else if (0x1E == opcode1)
12132 /* Handle enhanced software breakpoint insn, BKPT. */
12133 /* CPSR is changed to be executed in ARM state, disabling normal
12134 interrupts, entering abort mode. */
12135 /* According to high vector configuration PC is set. */
12136 /* User hits breakpoint and type reverse, in that case, we need to go back with
12137 previous CPSR and Program Counter. */
12138 record_buf[0] = ARM_PS_REGNUM;
12139 record_buf[1] = ARM_LR_REGNUM;
12140 thumb_insn_r->reg_rec_count = 2;
12141 /* We need to save SPSR value, which is not yet done. */
12142 printf_unfiltered (_("Process record does not support instruction "
12143 "0x%0x at address %s.\n"),
12144 thumb_insn_r->arm_insn,
12145 paddress (thumb_insn_r->gdbarch,
12146 thumb_insn_r->this_addr));
12149 else if ((0 == opcode) || (1 == opcode))
12151 /* ADD(5), ADD(6). */
12152 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12153 record_buf[0] = reg_src1;
12154 thumb_insn_r->reg_rec_count = 1;
12156 else if (2 == opcode)
12158 /* ADD(7), SUB(4). */
12159 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12160 record_buf[0] = ARM_SP_REGNUM;
12161 thumb_insn_r->reg_rec_count = 1;
12164 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12165 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12171 /* Handling opcode 110 insns. */
12174 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12176 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12177 struct regcache *reg_cache = thumb_insn_r->regcache;
12179 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12180 uint32_t reg_src1 = 0;
12181 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12182 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12183 uint32_t record_buf[24], record_buf_mem[48];
12185 ULONGEST u_regval = 0;
12187 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12188 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12194 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12196 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12197 while (register_bits)
12199 if (register_bits & 0x00000001)
12200 register_list[register_count++] = 1;
12201 register_bits = register_bits >> 1;
12203 record_buf[register_count] = reg_src1;
12204 thumb_insn_r->reg_rec_count = register_count + 1;
12205 for (register_count = 0; register_count < 8; register_count++)
12207 if (register_list[register_count])
12209 record_buf[index] = register_count;
12214 else if (0 == opcode2)
12216 /* It handles both STMIA. */
12217 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12219 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12220 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12221 while (register_bits)
12223 if (register_bits & 0x00000001)
12225 register_bits = register_bits >> 1;
12227 start_address = u_regval;
12228 thumb_insn_r->mem_rec_count = register_count;
12229 while (register_count)
12231 record_buf_mem[(register_count * 2) - 1] = start_address;
12232 record_buf_mem[(register_count * 2) - 2] = 4;
12233 start_address = start_address + 4;
12237 else if (0x1F == opcode1)
12239 /* Handle arm syscall insn. */
12240 if (tdep->arm_swi_record != NULL)
12242 ret = tdep->arm_swi_record(reg_cache);
12246 printf_unfiltered (_("no syscall record support\n"));
12251 /* B (1), conditional branch is automatically taken care in process_record,
12252 as PC is saved there. */
12254 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12255 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12261 /* Handling opcode 111 insns. */
12264 thumb_record_branch (insn_decode_record *thumb_insn_r)
12266 uint32_t record_buf[8];
12267 uint32_t bits_h = 0;
12269 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12271 if (2 == bits_h || 3 == bits_h)
12274 record_buf[0] = ARM_LR_REGNUM;
12275 thumb_insn_r->reg_rec_count = 1;
12277 else if (1 == bits_h)
12280 record_buf[0] = ARM_PS_REGNUM;
12281 record_buf[1] = ARM_LR_REGNUM;
12282 thumb_insn_r->reg_rec_count = 2;
12285 /* B(2) is automatically taken care in process_record, as PC is
12288 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12294 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12295 and positive val on fauilure. */
12298 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12300 gdb_byte buf[insn_size];
12302 memset (&buf[0], 0, insn_size);
12304 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12306 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12308 gdbarch_byte_order (insn_record->gdbarch));
12312 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12314 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12318 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12319 uint32_t insn_size)
12322 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12323 static const sti_arm_hdl_fp_t const arm_handle_insn[8] =
12325 arm_record_data_proc_misc_ld_str, /* 000. */
12326 arm_record_data_proc_imm, /* 001. */
12327 arm_record_ld_st_imm_offset, /* 010. */
12328 arm_record_ld_st_reg_offset, /* 011. */
12329 arm_record_ld_st_multiple, /* 100. */
12330 arm_record_b_bl, /* 101. */
12331 arm_record_coproc, /* 110. */
12332 arm_record_coproc_data_proc /* 111. */
12335 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12336 static const sti_arm_hdl_fp_t const thumb_handle_insn[8] =
12338 thumb_record_shift_add_sub, /* 000. */
12339 thumb_record_add_sub_cmp_mov, /* 001. */
12340 thumb_record_ld_st_reg_offset, /* 010. */
12341 thumb_record_ld_st_imm_offset, /* 011. */
12342 thumb_record_ld_st_stack, /* 100. */
12343 thumb_record_misc, /* 101. */
12344 thumb_record_ldm_stm_swi, /* 110. */
12345 thumb_record_branch /* 111. */
12348 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12349 uint32_t insn_id = 0;
12351 if (extract_arm_insn (arm_record, insn_size))
12355 printf_unfiltered (_("Process record: error reading memory at "
12356 "addr %s len = %d.\n"),
12357 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
12361 else if (ARM_RECORD == record_type)
12363 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12364 insn_id = bits (arm_record->arm_insn, 25, 27);
12365 ret = arm_record_extension_space (arm_record);
12366 /* If this insn has fallen into extension space
12367 then we need not decode it anymore. */
12368 if (ret != -1 && !INSN_RECORDED(arm_record))
12370 ret = arm_handle_insn[insn_id] (arm_record);
12373 else if (THUMB_RECORD == record_type)
12375 /* As thumb does not have condition codes, we set negative. */
12376 arm_record->cond = -1;
12377 insn_id = bits (arm_record->arm_insn, 13, 15);
12378 ret = thumb_handle_insn[insn_id] (arm_record);
12380 else if (THUMB2_RECORD == record_type)
12382 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12383 "0x%0x at address %s.\n"),arm_record->arm_insn,
12384 paddress (arm_record->gdbarch,
12385 arm_record->this_addr));
12390 /* Throw assertion. */
12391 gdb_assert_not_reached ("not a valid instruction, could not decode");
12398 /* Cleans up local record registers and memory allocations. */
12401 deallocate_reg_mem (insn_decode_record *record)
12403 xfree (record->arm_regs);
12404 xfree (record->arm_mems);
12408 /* Parse the current instruction and record the values of the registers and
12409 memory that will be changed in current instruction to record_arch_list".
12410 Return -1 if something is wrong. */
12413 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
12414 CORE_ADDR insn_addr)
12417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
12418 uint32_t no_of_rec = 0;
12419 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
12420 ULONGEST t_bit = 0, insn_id = 0;
12422 ULONGEST u_regval = 0;
12424 insn_decode_record arm_record;
12426 memset (&arm_record, 0, sizeof (insn_decode_record));
12427 arm_record.regcache = regcache;
12428 arm_record.this_addr = insn_addr;
12429 arm_record.gdbarch = gdbarch;
12432 if (record_debug > 1)
12434 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
12436 paddress (gdbarch, arm_record.this_addr));
12439 if (extract_arm_insn (&arm_record, 2))
12443 printf_unfiltered (_("Process record: error reading memory at "
12444 "addr %s len = %d.\n"),
12445 paddress (arm_record.gdbarch,
12446 arm_record.this_addr), 2);
12451 /* Check the insn, whether it is thumb or arm one. */
12453 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
12454 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
12457 if (!(u_regval & t_bit))
12459 /* We are decoding arm insn. */
12460 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
12464 insn_id = bits (arm_record.arm_insn, 11, 15);
12465 /* is it thumb2 insn? */
12466 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
12468 ret = decode_insn (&arm_record, THUMB2_RECORD,
12469 THUMB2_INSN_SIZE_BYTES);
12473 /* We are decoding thumb insn. */
12474 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
12480 /* Record registers. */
12481 record_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
12482 if (arm_record.arm_regs)
12484 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
12486 if (record_arch_list_add_reg (arm_record.regcache ,
12487 arm_record.arm_regs[no_of_rec]))
12491 /* Record memories. */
12492 if (arm_record.arm_mems)
12494 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
12496 if (record_arch_list_add_mem
12497 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
12498 arm_record.arm_mems[no_of_rec].len))
12503 if (record_arch_list_add_end ())
12508 deallocate_reg_mem (&arm_record);