1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
33 extern void _initialize_arm_tdep (void);
35 /* Number of different reg name sets (options). */
36 static int num_flavor_options;
38 /* We have more registers than the disassembler as gdb can print the value
39 of special registers as well.
40 The general register names are overwritten by whatever is being used by
41 the disassembler at the moment. We also adjust the case of cpsr and fps. */
43 /* Initial value: Register names used in ARM's ISA documentation. */
44 static char * arm_register_name_strings[] =
45 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
46 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
47 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
48 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
49 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
50 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
51 "fps", "cpsr" }; /* 24 25 */
52 char **arm_register_names = arm_register_name_strings;
54 /* Valid register name flavors. */
55 static const char **valid_flavors;
57 /* Disassembly flavor to use. Default to "std" register names. */
58 static const char *disassembly_flavor;
59 static int current_option; /* Index to that option in the opcodes table. */
61 /* This is used to keep the bfd arch_info in sync with the disassembly
63 static void set_disassembly_flavor_sfunc(char *, int,
64 struct cmd_list_element *);
65 static void set_disassembly_flavor (void);
67 static void convert_from_extended (void *ptr, void *dbl);
69 /* Define other aspects of the stack frame. We keep the offsets of
70 all saved registers, 'cause we need 'em a lot! We also keep the
71 current size of the stack frame, and the offset of the frame
72 pointer from the stack pointer (for frameless functions, and when
73 we're still in the prologue of a function with a frame) */
75 struct frame_extra_info
77 struct frame_saved_regs fsr;
83 /* Addresses for calling Thumb functions have the bit 0 set.
84 Here are some macros to test, set, or clear bit 0 of addresses. */
85 #define IS_THUMB_ADDR(addr) ((addr) & 1)
86 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
87 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
89 #define SWAP_TARGET_AND_HOST(buffer,len) \
92 if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
95 char *p = (char *)(buffer); \
96 char *q = ((char *)(buffer)) + len - 1; \
97 for (; p < q; p++, q--) \
107 /* Will a function return an aggregate type in memory or in a
108 register? Return 0 if an aggregate type can be returned in a
109 register, 1 if it must be returned in memory. */
112 arm_use_struct_convention (int gcc_p, struct type *type)
115 register enum type_code code;
117 /* In the ARM ABI, "integer" like aggregate types are returned in
118 registers. For an aggregate type to be integer like, its size
119 must be less than or equal to REGISTER_SIZE and the offset of
120 each addressable subfield must be zero. Note that bit fields are
121 not addressable, and all addressable subfields of unions always
122 start at offset zero.
124 This function is based on the behaviour of GCC 2.95.1.
125 See: gcc/arm.c: arm_return_in_memory() for details.
127 Note: All versions of GCC before GCC 2.95.2 do not set up the
128 parameters correctly for a function returning the following
129 structure: struct { float f;}; This should be returned in memory,
130 not a register. Richard Earnshaw sent me a patch, but I do not
131 know of any way to detect if a function like the above has been
132 compiled with the correct calling convention. */
134 /* All aggregate types that won't fit in a register must be returned
136 if (TYPE_LENGTH (type) > REGISTER_SIZE)
141 /* The only aggregate types that can be returned in a register are
142 structs and unions. Arrays must be returned in memory. */
143 code = TYPE_CODE (type);
144 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
149 /* Assume all other aggregate types can be returned in a register.
150 Run a check for structures, unions and arrays. */
153 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
156 /* Need to check if this struct/union is "integer" like. For
157 this to be true, its size must be less than or equal to
158 REGISTER_SIZE and the offset of each addressable subfield
159 must be zero. Note that bit fields are not addressable, and
160 unions always start at offset zero. If any of the subfields
161 is a floating point type, the struct/union cannot be an
164 /* For each field in the object, check:
165 1) Is it FP? --> yes, nRc = 1;
166 2) Is it addressable (bitpos != 0) and
167 not packed (bitsize == 0)?
171 for (i = 0; i < TYPE_NFIELDS (type); i++)
173 enum type_code field_type_code;
174 field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
176 /* Is it a floating point type field? */
177 if (field_type_code == TYPE_CODE_FLT)
183 /* If bitpos != 0, then we have to care about it. */
184 if (TYPE_FIELD_BITPOS (type, i) != 0)
186 /* Bitfields are not addressable. If the field bitsize is
187 zero, then the field is not packed. Hence it cannot be
188 a bitfield or any other packed type. */
189 if (TYPE_FIELD_BITSIZE (type, i) == 0)
202 arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
204 return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
207 /* Set to true if the 32-bit mode is in use. */
211 /* Flag set by arm_fix_call_dummy that tells whether the target
212 function is a Thumb function. This flag is checked by
213 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
214 its use in valops.c) to pass the function address as an additional
217 static int target_is_thumb;
219 /* Flag set by arm_fix_call_dummy that tells whether the calling
220 function is a Thumb function. This flag is checked by
221 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
223 static int caller_is_thumb;
225 /* Determine if the program counter specified in MEMADDR is in a Thumb
229 arm_pc_is_thumb (bfd_vma memaddr)
231 struct minimal_symbol *sym;
233 /* If bit 0 of the address is set, assume this is a Thumb address. */
234 if (IS_THUMB_ADDR (memaddr))
237 /* Thumb functions have a "special" bit set in minimal symbols. */
238 sym = lookup_minimal_symbol_by_pc (memaddr);
241 return (MSYMBOL_IS_SPECIAL (sym));
249 /* Determine if the program counter specified in MEMADDR is in a call
250 dummy being called from a Thumb function. */
253 arm_pc_is_thumb_dummy (bfd_vma memaddr)
255 CORE_ADDR sp = read_sp ();
257 /* FIXME: Until we switch for the new call dummy macros, this heuristic
258 is the best we can do. We are trying to determine if the pc is on
259 the stack, which (hopefully) will only happen in a call dummy.
260 We hope the current stack pointer is not so far alway from the dummy
261 frame location (true if we have not pushed large data structures or
262 gone too many levels deep) and that our 1024 is not enough to consider
263 code regions as part of the stack (true for most practical purposes) */
264 if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
265 return caller_is_thumb;
271 arm_addr_bits_remove (CORE_ADDR val)
273 if (arm_pc_is_thumb (val))
274 return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
276 return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
280 arm_saved_pc_after_call (struct frame_info *frame)
282 return ADDR_BITS_REMOVE (read_register (LR_REGNUM));
286 arm_frameless_function_invocation (struct frame_info *fi)
288 CORE_ADDR func_start, after_prologue;
291 func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
292 after_prologue = SKIP_PROLOGUE (func_start);
294 /* There are some frameless functions whose first two instructions
295 follow the standard APCS form, in which case after_prologue will
296 be func_start + 8. */
298 frameless = (after_prologue < func_start + 12);
302 /* A typical Thumb prologue looks like this:
306 Sometimes the latter instruction may be replaced by:
314 or, on tpcs, like this:
321 There is always one instruction of three classes:
326 When we have found at least one of each class we are done with the prolog.
327 Note that the "sub sp, #NN" before the push does not count.
331 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
333 CORE_ADDR current_pc;
334 int findmask = 0; /* findmask:
335 bit 0 - push { rlist }
336 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
337 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
340 for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2)
342 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
344 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
346 findmask |= 1; /* push found */
348 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
350 if ((findmask & 1) == 0) /* before push ? */
353 findmask |= 4; /* add/sub sp found */
355 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
357 findmask |= 2; /* setting of r7 found */
359 else if (insn == 0x466f) /* mov r7, sp */
361 findmask |= 2; /* setting of r7 found */
364 continue; /* something in the prolog that we don't care about or some
365 instruction from outside the prolog scheduled here for optimization */
371 /* The APCS (ARM Procedure Call Standard) defines the following
375 [stmfd sp!, {a1,a2,a3,a4}]
376 stmfd sp!, {...,fp,ip,lr,pc}
377 [stfe f7, [sp, #-12]!]
378 [stfe f6, [sp, #-12]!]
379 [stfe f5, [sp, #-12]!]
380 [stfe f4, [sp, #-12]!]
381 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
384 arm_skip_prologue (CORE_ADDR pc)
388 CORE_ADDR func_addr, func_end;
389 struct symtab_and_line sal;
391 /* See what the symbol table says. */
393 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
395 sal = find_pc_line (func_addr, 0);
396 if ((sal.line != 0) && (sal.end < func_end))
400 /* Check if this is Thumb code. */
401 if (arm_pc_is_thumb (pc))
402 return thumb_skip_prologue (pc, func_end);
404 /* Can't find the prologue end in the symbol table, try it the hard way
405 by disassembling the instructions. */
407 inst = read_memory_integer (skip_pc, 4);
408 if (inst != 0xe1a0c00d) /* mov ip, sp */
412 inst = read_memory_integer (skip_pc, 4);
413 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
416 inst = read_memory_integer (skip_pc, 4);
419 if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
423 inst = read_memory_integer (skip_pc, 4);
425 /* Any insns after this point may float into the code, if it makes
426 for better instruction scheduling, so we skip them only if we
427 find them, but still consdier the function to be frame-ful. */
429 /* We may have either one sfmfd instruction here, or several stfe
430 insns, depending on the version of floating point code we
432 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
435 inst = read_memory_integer (skip_pc, 4);
439 while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
442 inst = read_memory_integer (skip_pc, 4);
446 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
452 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
453 This function decodes a Thumb function prologue to determine:
454 1) the size of the stack frame
455 2) which registers are saved on it
456 3) the offsets of saved regs
457 4) the offset from the stack pointer to the frame pointer
458 This information is stored in the "extra" fields of the frame_info.
460 A typical Thumb function prologue would create this stack frame
461 (offsets relative to FP)
462 old SP -> 24 stack parameters
465 R7 -> 0 local variables (16 bytes)
466 SP -> -12 additional stack space (12 bytes)
467 The frame size would thus be 36 bytes, and the frame offset would be
468 12 bytes. The frame register is R7.
470 The comments for thumb_skip_prolog() describe the algorithm we use to detect
471 the end of the prolog */
475 thumb_scan_prologue (struct frame_info *fi)
477 CORE_ADDR prologue_start;
478 CORE_ADDR prologue_end;
479 CORE_ADDR current_pc;
480 int saved_reg[16]; /* which register has been copied to register n? */
481 int findmask = 0; /* findmask:
482 bit 0 - push { rlist }
483 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
484 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
488 if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
490 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
492 if (sal.line == 0) /* no line info, use current PC */
493 prologue_end = fi->pc;
494 else if (sal.end < prologue_end) /* next line begins after fn end */
495 prologue_end = sal.end; /* (probably means no prologue) */
498 prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */
499 /* 16 pushes, an add, and "mv fp,sp" */
501 prologue_end = min (prologue_end, fi->pc);
503 /* Initialize the saved register map. When register H is copied to
504 register L, we will put H in saved_reg[L]. */
505 for (i = 0; i < 16; i++)
508 /* Search the prologue looking for instructions that set up the
509 frame pointer, adjust the stack pointer, and save registers.
510 Do this until all basic prolog instructions are found. */
513 for (current_pc = prologue_start;
514 (current_pc < prologue_end) && ((findmask & 7) != 7);
521 insn = read_memory_unsigned_integer (current_pc, 2);
523 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
526 findmask |= 1; /* push found */
527 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
528 whether to save LR (R14). */
529 mask = (insn & 0xff) | ((insn & 0x100) << 6);
531 /* Calculate offsets of saved R0-R7 and LR. */
532 for (regno = LR_REGNUM; regno >= 0; regno--)
533 if (mask & (1 << regno))
536 fi->fsr.regs[saved_reg[regno]] = -(fi->framesize);
537 saved_reg[regno] = regno; /* reset saved register map */
540 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
542 if ((findmask & 1) == 0) /* before push ? */
545 findmask |= 4; /* add/sub sp found */
547 offset = (insn & 0x7f) << 2; /* get scaled offset */
548 if (insn & 0x80) /* is it signed? (==subtracting) */
550 fi->frameoffset += offset;
553 fi->framesize -= offset;
555 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
557 findmask |= 2; /* setting of r7 found */
558 fi->framereg = THUMB_FP_REGNUM;
559 fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */
561 else if (insn == 0x466f) /* mov r7, sp */
563 findmask |= 2; /* setting of r7 found */
564 fi->framereg = THUMB_FP_REGNUM;
566 saved_reg[THUMB_FP_REGNUM] = SP_REGNUM;
568 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
570 int lo_reg = insn & 7; /* dest. register (r0-r7) */
571 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
572 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
575 continue; /* something in the prolog that we don't care about or some
576 instruction from outside the prolog scheduled here for optimization */
580 /* Check if prologue for this frame's PC has already been scanned. If
581 it has, copy the relevant information about that prologue and
582 return non-zero. Otherwise do not copy anything and return zero.
584 The information saved in the cache includes:
585 * the frame register number;
586 * the size of the stack frame;
587 * the offsets of saved regs (relative to the old SP); and
588 * the offset from the stack pointer to the frame pointer
590 The cache contains only one entry, since this is adequate for the
591 typical sequence of prologue scan requests we get. When performing
592 a backtrace, GDB will usually ask to scan the same function twice
593 in a row (once to get the frame chain, and once to fill in the
594 extra frame information). */
596 static struct frame_info prologue_cache;
599 check_prologue_cache (struct frame_info *fi)
603 if (fi->pc == prologue_cache.pc)
605 fi->framereg = prologue_cache.framereg;
606 fi->framesize = prologue_cache.framesize;
607 fi->frameoffset = prologue_cache.frameoffset;
608 for (i = 0; i <= NUM_REGS; i++)
609 fi->fsr.regs[i] = prologue_cache.fsr.regs[i];
617 /* Copy the prologue information from fi to the prologue cache. */
620 save_prologue_cache (struct frame_info *fi)
624 prologue_cache.pc = fi->pc;
625 prologue_cache.framereg = fi->framereg;
626 prologue_cache.framesize = fi->framesize;
627 prologue_cache.frameoffset = fi->frameoffset;
629 for (i = 0; i <= NUM_REGS; i++)
630 prologue_cache.fsr.regs[i] = fi->fsr.regs[i];
634 /* This function decodes an ARM function prologue to determine:
635 1) the size of the stack frame
636 2) which registers are saved on it
637 3) the offsets of saved regs
638 4) the offset from the stack pointer to the frame pointer
639 This information is stored in the "extra" fields of the frame_info.
641 There are two basic forms for the ARM prologue. The fixed argument
642 function call will look like:
645 stmfd sp!, {fp, ip, lr, pc}
649 Which would create this stack frame (offsets relative to FP):
650 IP -> 4 (caller's stack)
651 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
652 -4 LR (return address in caller)
653 -8 IP (copy of caller's SP)
655 SP -> -28 Local variables
657 The frame size would thus be 32 bytes, and the frame offset would be
658 28 bytes. The stmfd call can also save any of the vN registers it
659 plans to use, which increases the frame size accordingly.
661 Note: The stored PC is 8 off of the STMFD instruction that stored it
662 because the ARM Store instructions always store PC + 8 when you read
665 A variable argument function call will look like:
668 stmfd sp!, {a1, a2, a3, a4}
669 stmfd sp!, {fp, ip, lr, pc}
672 Which would create this stack frame (offsets relative to FP):
673 IP -> 20 (caller's stack)
678 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
679 -4 LR (return address in caller)
680 -8 IP (copy of caller's SP)
682 SP -> -28 Local variables
684 The frame size would thus be 48 bytes, and the frame offset would be
687 There is another potential complication, which is that the optimizer
688 will try to separate the store of fp in the "stmfd" instruction from
689 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
690 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
692 Also, note, the original version of the ARM toolchain claimed that there
695 instruction at the end of the prologue. I have never seen GCC produce
696 this, and the ARM docs don't mention it. We still test for it below in
702 arm_scan_prologue (struct frame_info *fi)
704 int regno, sp_offset, fp_offset;
705 CORE_ADDR prologue_start, prologue_end, current_pc;
707 /* Check if this function is already in the cache of frame information. */
708 if (check_prologue_cache (fi))
711 /* Assume there is no frame until proven otherwise. */
712 fi->framereg = SP_REGNUM;
716 /* Check for Thumb prologue. */
717 if (arm_pc_is_thumb (fi->pc))
719 thumb_scan_prologue (fi);
720 save_prologue_cache (fi);
724 /* Find the function prologue. If we can't find the function in
725 the symbol table, peek in the stack frame to find the PC. */
726 if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
728 /* Assume the prologue is everything between the first instruction
729 in the function and the first source line. */
730 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
732 if (sal.line == 0) /* no line info, use current PC */
733 prologue_end = fi->pc;
734 else if (sal.end < prologue_end) /* next line begins after fn end */
735 prologue_end = sal.end; /* (probably means no prologue) */
739 /* Get address of the stmfd in the prologue of the callee; the saved
740 PC is the address of the stmfd + 8. */
741 prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4))
743 prologue_end = prologue_start + 64; /* This is all the insn's
744 that could be in the prologue,
745 plus room for 5 insn's inserted
749 /* Now search the prologue looking for instructions that set up the
750 frame pointer, adjust the stack pointer, and save registers.
752 Be careful, however, and if it doesn't look like a prologue,
753 don't try to scan it. If, for instance, a frameless function
754 begins with stmfd sp!, then we will tell ourselves there is
755 a frame, which will confuse stack traceback, as well ad"finish"
756 and other operations that rely on a knowledge of the stack
759 In the APCS, the prologue should start with "mov ip, sp" so
760 if we don't see this as the first insn, we will stop. */
762 sp_offset = fp_offset = 0;
764 if (read_memory_unsigned_integer (prologue_start, 4)
765 == 0xe1a0c00d) /* mov ip, sp */
767 for (current_pc = prologue_start + 4; current_pc < prologue_end;
770 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
772 if ((insn & 0xffff0000) == 0xe92d0000)
773 /* stmfd sp!, {..., fp, ip, lr, pc}
775 stmfd sp!, {a1, a2, a3, a4} */
777 int mask = insn & 0xffff;
779 /* Calculate offsets of saved registers. */
780 for (regno = PC_REGNUM; regno >= 0; regno--)
781 if (mask & (1 << regno))
784 fi->fsr.regs[regno] = sp_offset;
787 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
789 unsigned imm = insn & 0xff; /* immediate value */
790 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
791 imm = (imm >> rot) | (imm << (32 - rot));
793 fi->framereg = FP_REGNUM;
795 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
797 unsigned imm = insn & 0xff; /* immediate value */
798 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
799 imm = (imm >> rot) | (imm << (32 - rot));
802 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
805 regno = F0_REGNUM + ((insn >> 12) & 0x07);
806 fi->fsr.regs[regno] = sp_offset;
808 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
811 unsigned int fp_start_reg, fp_bound_reg;
813 if ((insn & 0x800) == 0x800) /* N0 is set */
815 if ((insn & 0x40000) == 0x40000) /* N1 is set */
822 if ((insn & 0x40000) == 0x40000) /* N1 is set */
828 fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7);
829 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
830 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
833 fi->fsr.regs[fp_start_reg++] = sp_offset;
837 /* The optimizer might shove anything into the prologue,
838 so we just skip what we don't recognize. */
843 /* The frame size is just the negative of the offset (from the original SP)
844 of the last thing thing we pushed on the stack. The frame offset is
845 [new FP] - [new SP]. */
846 fi->framesize = -sp_offset;
847 fi->frameoffset = fp_offset - sp_offset;
849 save_prologue_cache (fi);
852 /* Find REGNUM on the stack. Otherwise, it's in an active register.
853 One thing we might want to do here is to check REGNUM against the
854 clobber mask, and somehow flag it as invalid if it isn't saved on
855 the stack somewhere. This would provide a graceful failure mode
856 when trying to get the value of caller-saves registers for an inner
860 arm_find_callers_reg (struct frame_info *fi, int regnum)
862 for (; fi; fi = fi->next)
864 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
865 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
866 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
869 if (fi->fsr.regs[regnum] != 0)
870 return read_memory_integer (fi->fsr.regs[regnum],
871 REGISTER_RAW_SIZE (regnum));
872 return read_register (regnum);
875 /* Function: frame_chain
876 Given a GDB frame, determine the address of the calling function's frame.
877 This will be used to create a new GDB frame struct, and then
878 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
879 For ARM, we save the frame size when we initialize the frame_info.
881 The original definition of this function was a macro in tm-arm.h:
882 { In the case of the ARM, the frame's nominal address is the FP value,
883 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
885 #define FRAME_CHAIN(thisframe) \
886 ((thisframe)->pc >= LOWEST_PC ? \
887 read_memory_integer ((thisframe)->frame - 12, 4) :\
893 arm_frame_chain (struct frame_info *fi)
895 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
896 CORE_ADDR fn_start, callers_pc, fp;
898 /* is this a dummy frame? */
899 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
900 return fi->frame; /* dummy frame same as caller's frame */
902 /* is caller-of-this a dummy frame? */
903 callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */
904 fp = arm_find_callers_reg (fi, FP_REGNUM);
905 if (PC_IN_CALL_DUMMY (callers_pc, fp, fp))
906 return fp; /* dummy frame's frame may bear no relation to ours */
908 if (find_pc_partial_function (fi->pc, 0, &fn_start, 0))
909 if (fn_start == entry_point_address ())
910 return 0; /* in _start fn, don't chain further */
912 CORE_ADDR caller_pc, fn_start;
913 struct frame_info caller_fi;
914 int framereg = fi->framereg;
916 if (fi->pc < LOWEST_PC)
919 /* If the caller is the startup code, we're at the end of the chain. */
920 caller_pc = FRAME_SAVED_PC (fi);
921 if (find_pc_partial_function (caller_pc, 0, &fn_start, 0))
922 if (fn_start == entry_point_address ())
925 /* If the caller is Thumb and the caller is ARM, or vice versa,
926 the frame register of the caller is different from ours.
927 So we must scan the prologue of the caller to determine its
928 frame register number. */
929 if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
931 memset (&caller_fi, 0, sizeof (caller_fi));
932 caller_fi.pc = caller_pc;
933 arm_scan_prologue (&caller_fi);
934 framereg = caller_fi.framereg;
937 /* If the caller used a frame register, return its value.
938 Otherwise, return the caller's stack pointer. */
939 if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM)
940 return arm_find_callers_reg (fi, framereg);
942 return fi->frame + fi->framesize;
945 /* This function actually figures out the frame address for a given pc
946 and sp. This is tricky because we sometimes don't use an explicit
947 frame pointer, and the previous stack pointer isn't necessarily
948 recorded on the stack. The only reliable way to get this info is
949 to examine the prologue. FROMLEAF is a little confusing, it means
950 this is the next frame up the chain AFTER a frameless function. If
951 this is true, then the frame value for this frame is still in the
955 arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
960 fi->pc = FRAME_SAVED_PC (fi->next);
962 memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs);
964 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
965 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
967 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
968 by assuming it's always FP. */
969 fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM);
977 arm_scan_prologue (fi);
980 /* this is the innermost frame? */
981 fi->frame = read_register (fi->framereg);
982 else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM)
984 /* not the innermost frame */
985 /* If we have an FP, the callee saved it. */
986 if (fi->next->fsr.regs[fi->framereg] != 0)
988 read_memory_integer (fi->next->fsr.regs[fi->framereg], 4);
990 /* If we were called by a frameless fn. then our frame is
991 still in the frame pointer register on the board... */
992 fi->frame = read_fp ();
995 /* Calculate actual addresses of saved registers using offsets
996 determined by arm_scan_prologue. */
997 for (reg = 0; reg < NUM_REGS; reg++)
998 if (fi->fsr.regs[reg] != 0)
999 fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset;
1004 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1005 is saved in the stack anywhere, otherwise we get it from the
1008 The old definition of this function was a macro:
1009 #define FRAME_SAVED_PC(FRAME) \
1010 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1013 arm_frame_saved_pc (struct frame_info *fi)
1015 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1016 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1017 return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
1021 CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM);
1022 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1026 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1027 Examine the Program Status Register to decide which state we're in. */
1030 arm_target_read_fp (void)
1032 if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
1033 return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
1035 return read_register (FP_REGNUM); /* R11 if ARM */
1038 /* Calculate the frame offsets of the saved registers (ARM version). */
1041 arm_frame_find_saved_regs (struct frame_info *fi,
1042 struct frame_saved_regs *regaddr)
1044 memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs));
1048 arm_push_dummy_frame (void)
1050 CORE_ADDR old_sp = read_register (SP_REGNUM);
1051 CORE_ADDR sp = old_sp;
1052 CORE_ADDR fp, prologue_start;
1055 /* Push the two dummy prologue instructions in reverse order,
1056 so that they'll be in the correct low-to-high order in memory. */
1057 /* sub fp, ip, #4 */
1058 sp = push_word (sp, 0xe24cb004);
1059 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1060 prologue_start = sp = push_word (sp, 0xe92ddfff);
1062 /* Push a pointer to the dummy prologue + 12, because when stm
1063 instruction stores the PC, it stores the address of the stm
1064 instruction itself plus 12. */
1065 fp = sp = push_word (sp, prologue_start + 12);
1066 sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */
1067 sp = push_word (sp, old_sp);
1068 sp = push_word (sp, read_register (FP_REGNUM));
1070 for (regnum = 10; regnum >= 0; regnum--)
1071 sp = push_word (sp, read_register (regnum));
1073 write_register (FP_REGNUM, fp);
1074 write_register (THUMB_FP_REGNUM, fp);
1075 write_register (SP_REGNUM, sp);
1078 /* Fix up the call dummy, based on whether the processor is currently
1079 in Thumb or ARM mode, and whether the target function is Thumb or
1080 ARM. There are three different situations requiring three
1083 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1084 been copied into the dummy parameter to this function.
1085 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1086 "mov pc,r4" instruction patched to be a "bx r4" instead.
1087 * Thumb calling anything: uses the Thumb dummy defined below, which
1088 works for calling both ARM and Thumb functions.
1090 All three call dummies expect to receive the target function
1091 address in R4, with the low bit set if it's a Thumb function. */
1094 arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1095 value_ptr *args, struct type *type, int gcc_p)
1097 static short thumb_dummy[4] =
1099 0xf000, 0xf801, /* bl label */
1100 0xdf18, /* swi 24 */
1101 0x4720, /* label: bx r4 */
1103 static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
1105 /* Set flag indicating whether the current PC is in a Thumb function. */
1106 caller_is_thumb = arm_pc_is_thumb (read_pc ());
1108 /* If the target function is Thumb, set the low bit of the function
1109 address. And if the CPU is currently in ARM mode, patch the
1110 second instruction of call dummy to use a BX instruction to
1111 switch to Thumb mode. */
1112 target_is_thumb = arm_pc_is_thumb (fun);
1113 if (target_is_thumb)
1116 if (!caller_is_thumb)
1117 store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
1120 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1121 instead of the ARM one that's already been copied. This will
1122 work for both Thumb and ARM target functions. */
1123 if (caller_is_thumb)
1127 int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
1129 for (i = 0; i < len; i++)
1131 store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
1132 p += sizeof (thumb_dummy[0]);
1136 /* Put the target address in r4; the call dummy will copy this to
1138 write_register (4, fun);
1141 /* Return the offset in the call dummy of the instruction that needs
1142 to have a breakpoint placed on it. This is the offset of the 'swi
1143 24' instruction, which is no longer actually used, but simply acts
1144 as a place-holder now.
1146 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1149 arm_call_dummy_breakpoint_offset (void)
1151 if (caller_is_thumb)
1159 This function does not support passing parameters using the FPA
1160 variant of the APCS. It passes any floating point arguments in the
1161 general registers and/or on the stack. */
1164 arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp,
1165 int struct_return, CORE_ADDR struct_addr)
1168 int argnum, argreg, nstack_size;
1170 /* Walk through the list of args and determine how large a temporary
1171 stack is required. Need to take care here as structs may be
1172 passed on the stack, and we have to to push them. */
1173 nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
1174 if (struct_return) /* The struct address goes in A1. */
1175 nstack_size += REGISTER_SIZE;
1177 /* Walk through the arguments and add their size to nstack_size. */
1178 for (argnum = 0; argnum < nargs; argnum++)
1181 struct type *arg_type;
1183 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1184 len = TYPE_LENGTH (arg_type);
1186 /* ANSI C code passes float arguments as integers, K&R code
1187 passes float arguments as doubles. Correct for this here. */
1188 if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len)
1189 nstack_size += FP_REGISTER_VIRTUAL_SIZE;
1194 /* Allocate room on the stack, and initialize our stack frame
1197 if (nstack_size > 0)
1203 /* Initialize the integer argument register pointer. */
1206 /* The struct_return pointer occupies the first parameter passing
1209 write_register (argreg++, struct_addr);
1211 /* Process arguments from left to right. Store as many as allowed
1212 in the parameter passing registers (A1-A4), and save the rest on
1213 the temporary stack. */
1214 for (argnum = 0; argnum < nargs; argnum++)
1220 enum type_code typecode;
1221 struct type *arg_type, *target_type;
1223 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1224 target_type = TYPE_TARGET_TYPE (arg_type);
1225 len = TYPE_LENGTH (arg_type);
1226 typecode = TYPE_CODE (arg_type);
1227 val = (char *) VALUE_CONTENTS (args[argnum]);
1229 /* ANSI C code passes float arguments as integers, K&R code
1230 passes float arguments as doubles. The .stabs record for
1231 for ANSI prototype floating point arguments records the
1232 type as FP_INTEGER, while a K&R style (no prototype)
1233 .stabs records the type as FP_FLOAT. In this latter case
1234 the compiler converts the float arguments to double before
1235 calling the function. */
1236 if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
1240 char * bufo = (char *) &d;
1241 char * bufd = (char *) &dbl_arg;
1243 len = sizeof (double);
1245 SWAP_TARGET_AND_HOST (&f, sizeof (float)); /* adjust endianess */
1247 /* We must revert the longwords so they get loaded into the
1248 the right registers. */
1249 memcpy (bufd, bufo + len / 2, len / 2);
1250 SWAP_TARGET_AND_HOST (bufd, len / 2); /* adjust endianess */
1251 memcpy (bufd + len / 2, bufo, len / 2);
1252 SWAP_TARGET_AND_HOST (bufd + len / 2, len / 2); /* adjust endianess */
1253 val = (char *) &dbl_arg;
1256 /* I don't know why this code was disable. The only logical use
1257 for a function pointer is to call that function, so setting
1258 the mode bit is perfectly fine. FN */
1259 /* If the argument is a pointer to a function, and it is a Thumb
1260 function, set the low bit of the pointer. */
1261 if (TYPE_CODE_PTR == typecode
1262 && NULL != target_type
1263 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1265 CORE_ADDR regval = extract_address (val, len);
1266 if (arm_pc_is_thumb (regval))
1267 store_address (val, len, MAKE_THUMB_ADDR (regval));
1270 /* Copy the argument to general registers or the stack in
1271 register-sized pieces. Large arguments are split between
1272 registers and stack. */
1275 int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
1277 if (argreg <= ARM_LAST_ARG_REGNUM)
1279 /* It's an argument being passed in a general register. */
1280 regval = extract_address (val, partial_len);
1281 write_register (argreg++, regval);
1285 /* Push the arguments onto the stack. */
1286 write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
1287 fp += REGISTER_SIZE;
1295 /* Return adjusted stack pointer. */
1300 arm_pop_frame (void)
1303 struct frame_info *frame = get_current_frame ();
1305 if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp()))
1309 old_SP = read_register (frame->framereg);
1310 for (regnum = 0; regnum < NUM_REGS; regnum++)
1311 if (frame->fsr.regs[regnum] != 0)
1312 write_register (regnum,
1313 read_memory_integer (frame->fsr.regs[regnum], 4));
1315 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
1316 write_register (SP_REGNUM, old_SP);
1322 sp = read_register (FP_REGNUM);
1323 sp -= sizeof(CORE_ADDR); /* we don't care about this first word */
1325 write_register (PC_REGNUM, read_memory_integer (sp, 4));
1326 sp -= sizeof(CORE_ADDR);
1327 write_register (SP_REGNUM, read_memory_integer (sp, 4));
1328 sp -= sizeof(CORE_ADDR);
1329 write_register (FP_REGNUM, read_memory_integer (sp, 4));
1330 sp -= sizeof(CORE_ADDR);
1332 for (regnum = 10; regnum >= 0; regnum--)
1334 write_register (regnum, read_memory_integer (sp, 4));
1335 sp -= sizeof(CORE_ADDR);
1339 flush_cached_frames ();
1343 print_fpu_flags (int flags)
1345 if (flags & (1 << 0))
1346 fputs ("IVO ", stdout);
1347 if (flags & (1 << 1))
1348 fputs ("DVZ ", stdout);
1349 if (flags & (1 << 2))
1350 fputs ("OFL ", stdout);
1351 if (flags & (1 << 3))
1352 fputs ("UFL ", stdout);
1353 if (flags & (1 << 4))
1354 fputs ("INX ", stdout);
1359 arm_float_info (void)
1361 register unsigned long status = read_register (FPS_REGNUM);
1364 type = (status >> 24) & 127;
1365 printf ("%s FPU type %d\n",
1366 (status & (1 << 31)) ? "Hardware" : "Software",
1368 fputs ("mask: ", stdout);
1369 print_fpu_flags (status >> 16);
1370 fputs ("flags: ", stdout);
1371 print_fpu_flags (status);
1375 /* FIXME: The generated assembler works but sucks. Instead of using
1376 r0, r1 it pushes them on the stack, then loads them into r3, r4 and
1377 uses those registers. I must be missing something. ScottB */
1380 convert_from_extended (void *ptr, void *dbl)
1386 : "r" (ptr), "r" (dbl));
1390 convert_to_extended (void *dbl, void *ptr)
1396 : "r" (dbl), "r" (ptr));
1400 convert_from_extended (void *ptr, void *dbl)
1402 *(double *) dbl = *(double *) ptr;
1406 convert_to_extended (void *dbl, void *ptr)
1408 *(double *) ptr = *(double *) dbl;
1412 /* Nonzero if register N requires conversion from raw format to
1416 arm_register_convertible (unsigned int regnum)
1418 return ((regnum - F0_REGNUM) < 8);
1421 /* Convert data from raw format for register REGNUM in buffer FROM to
1422 virtual format with type TYPE in buffer TO. */
1425 arm_register_convert_to_virtual (unsigned int regnum, struct type *type,
1426 void *from, void *to)
1430 convert_from_extended (from, &val);
1431 store_floating (to, TYPE_LENGTH (type), val);
1434 /* Convert data from virtual format with type TYPE in buffer FROM to
1435 raw format for register REGNUM in buffer TO. */
1438 arm_register_convert_to_raw (unsigned int regnum, struct type *type,
1439 void *from, void *to)
1441 double val = extract_floating (from, TYPE_LENGTH (type));
1443 convert_to_extended (&val, to);
1447 condition_true (unsigned long cond, unsigned long status_reg)
1449 if (cond == INST_AL || cond == INST_NV)
1455 return ((status_reg & FLAG_Z) != 0);
1457 return ((status_reg & FLAG_Z) == 0);
1459 return ((status_reg & FLAG_C) != 0);
1461 return ((status_reg & FLAG_C) == 0);
1463 return ((status_reg & FLAG_N) != 0);
1465 return ((status_reg & FLAG_N) == 0);
1467 return ((status_reg & FLAG_V) != 0);
1469 return ((status_reg & FLAG_V) == 0);
1471 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1473 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1475 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1477 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1479 return (((status_reg & FLAG_Z) == 0) &&
1480 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1482 return (((status_reg & FLAG_Z) != 0) ||
1483 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1488 #define submask(x) ((1L << ((x) + 1)) - 1)
1489 #define bit(obj,st) (((obj) >> (st)) & 1)
1490 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1491 #define sbits(obj,st,fn) \
1492 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1493 #define BranchDest(addr,instr) \
1494 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1497 static unsigned long
1498 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1499 unsigned long status_reg)
1501 unsigned long res, shift;
1502 int rm = bits (inst, 0, 3);
1503 unsigned long shifttype = bits (inst, 5, 6);
1507 int rs = bits (inst, 8, 11);
1508 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1511 shift = bits (inst, 7, 11);
1514 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1515 + (bit (inst, 4) ? 12 : 8))
1516 : read_register (rm));
1521 res = shift >= 32 ? 0 : res << shift;
1525 res = shift >= 32 ? 0 : res >> shift;
1531 res = ((res & 0x80000000L)
1532 ? ~((~res) >> shift) : res >> shift);
1535 case 3: /* ROR/RRX */
1538 res = (res >> 1) | (carry ? 0x80000000L : 0);
1540 res = (res >> shift) | (res << (32 - shift));
1544 return res & 0xffffffff;
1547 /* Return number of 1-bits in VAL. */
1550 bitcount (unsigned long val)
1553 for (nbits = 0; val != 0; nbits++)
1554 val &= val - 1; /* delete rightmost 1-bit in val */
1559 thumb_get_next_pc (CORE_ADDR pc)
1561 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1562 unsigned short inst1 = read_memory_integer (pc, 2);
1563 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1564 unsigned long offset;
1566 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1570 /* Fetch the saved PC from the stack. It's stored above
1571 all of the other registers. */
1572 offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
1573 sp = read_register (SP_REGNUM);
1574 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1575 nextpc = ADDR_BITS_REMOVE (nextpc);
1577 error ("Infinite loop detected");
1579 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1581 unsigned long status = read_register (PS_REGNUM);
1582 unsigned long cond = bits (inst1, 8, 11);
1583 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1584 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1586 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1588 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1590 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
1592 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1593 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1594 nextpc = pc_val + offset;
1601 arm_get_next_pc (CORE_ADDR pc)
1603 unsigned long pc_val;
1604 unsigned long this_instr;
1605 unsigned long status;
1608 if (arm_pc_is_thumb (pc))
1609 return thumb_get_next_pc (pc);
1611 pc_val = (unsigned long) pc;
1612 this_instr = read_memory_integer (pc, 4);
1613 status = read_register (PS_REGNUM);
1614 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1616 if (condition_true (bits (this_instr, 28, 31), status))
1618 switch (bits (this_instr, 24, 27))
1621 case 0x1: /* data processing */
1625 unsigned long operand1, operand2, result = 0;
1629 if (bits (this_instr, 12, 15) != 15)
1632 if (bits (this_instr, 22, 25) == 0
1633 && bits (this_instr, 4, 7) == 9) /* multiply */
1634 error ("Illegal update to pc in instruction");
1636 /* Multiply into PC */
1637 c = (status & FLAG_C) ? 1 : 0;
1638 rn = bits (this_instr, 16, 19);
1639 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1641 if (bit (this_instr, 25))
1643 unsigned long immval = bits (this_instr, 0, 7);
1644 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1645 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1648 else /* operand 2 is a shifted register */
1649 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1651 switch (bits (this_instr, 21, 24))
1654 result = operand1 & operand2;
1658 result = operand1 ^ operand2;
1662 result = operand1 - operand2;
1666 result = operand2 - operand1;
1670 result = operand1 + operand2;
1674 result = operand1 + operand2 + c;
1678 result = operand1 - operand2 + c;
1682 result = operand2 - operand1 + c;
1688 case 0xb: /* tst, teq, cmp, cmn */
1689 result = (unsigned long) nextpc;
1693 result = operand1 | operand2;
1697 /* Always step into a function. */
1702 result = operand1 & ~operand2;
1709 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1712 error ("Infinite loop detected");
1717 case 0x5: /* data transfer */
1720 if (bit (this_instr, 20))
1723 if (bits (this_instr, 12, 15) == 15)
1729 if (bit (this_instr, 22))
1730 error ("Illegal update to pc in instruction");
1732 /* byte write to PC */
1733 rn = bits (this_instr, 16, 19);
1734 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1735 if (bit (this_instr, 24))
1738 int c = (status & FLAG_C) ? 1 : 0;
1739 unsigned long offset =
1740 (bit (this_instr, 25)
1741 ? shifted_reg_val (this_instr, c, pc_val, status)
1742 : bits (this_instr, 0, 11));
1744 if (bit (this_instr, 23))
1749 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1752 nextpc = ADDR_BITS_REMOVE (nextpc);
1755 error ("Infinite loop detected");
1761 case 0x9: /* block transfer */
1762 if (bit (this_instr, 20))
1765 if (bit (this_instr, 15))
1770 if (bit (this_instr, 23))
1773 unsigned long reglist = bits (this_instr, 0, 14);
1774 offset = bitcount (reglist) * 4;
1775 if (bit (this_instr, 24)) /* pre */
1778 else if (bit (this_instr, 24))
1782 unsigned long rn_val =
1783 read_register (bits (this_instr, 16, 19));
1785 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1789 nextpc = ADDR_BITS_REMOVE (nextpc);
1791 error ("Infinite loop detected");
1796 case 0xb: /* branch & link */
1797 case 0xa: /* branch */
1799 nextpc = BranchDest (pc, this_instr);
1801 nextpc = ADDR_BITS_REMOVE (nextpc);
1803 error ("Infinite loop detected");
1809 case 0xe: /* coproc ops */
1814 fprintf (stderr, "Bad bit-field extraction\n");
1822 #include "bfd-in2.h"
1823 #include "libcoff.h"
1826 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1828 if (arm_pc_is_thumb (memaddr))
1830 static asymbol *asym;
1831 static combined_entry_type ce;
1832 static struct coff_symbol_struct csym;
1833 static struct _bfd fake_bfd;
1834 static bfd_target fake_target;
1836 if (csym.native == NULL)
1838 /* Create a fake symbol vector containing a Thumb symbol. This is
1839 solely so that the code in print_insn_little_arm() and
1840 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1841 of a Thumb symbol and switch to decoding Thumb instructions. */
1843 fake_target.flavour = bfd_target_coff_flavour;
1844 fake_bfd.xvec = &fake_target;
1845 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1847 csym.symbol.the_bfd = &fake_bfd;
1848 csym.symbol.name = "fake";
1849 asym = (asymbol *) & csym;
1852 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1853 info->symbols = &asym;
1856 info->symbols = NULL;
1858 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1859 return print_insn_big_arm (memaddr, info);
1861 return print_insn_little_arm (memaddr, info);
1864 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1865 program counter value to determine whether a 16-bit or 32-bit
1866 breakpoint should be used. It returns a pointer to a string of
1867 bytes that encode a breakpoint instruction, stores the length of
1868 the string to *lenptr, and adjusts the program counter (if
1869 necessary) to point to the actual memory location where the
1870 breakpoint should be inserted. */
1873 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1875 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
1877 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1879 static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT;
1880 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1881 *lenptr = sizeof (thumb_breakpoint);
1882 return thumb_breakpoint;
1886 static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT;
1887 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1888 *lenptr = sizeof (thumb_breakpoint);
1889 return thumb_breakpoint;
1894 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1896 static char arm_breakpoint[] = ARM_BE_BREAKPOINT;
1897 *lenptr = sizeof (arm_breakpoint);
1898 return arm_breakpoint;
1902 static char arm_breakpoint[] = ARM_LE_BREAKPOINT;
1903 *lenptr = sizeof (arm_breakpoint);
1904 return arm_breakpoint;
1909 /* Extract from an array REGBUF containing the (raw) register state a
1910 function return value of type TYPE, and copy that, in virtual
1911 format, into VALBUF. */
1914 arm_extract_return_value (struct type *type,
1915 char regbuf[REGISTER_BYTES],
1918 if (TYPE_CODE_FLT == TYPE_CODE (type))
1919 convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf);
1921 memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type));
1924 /* Return non-zero if the PC is inside a thumb call thunk. */
1927 arm_in_call_stub (CORE_ADDR pc, char *name)
1929 CORE_ADDR start_addr;
1931 /* Find the starting address of the function containing the PC. If
1932 the caller didn't give us a name, look it up at the same time. */
1933 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
1936 return strncmp (name, "_call_via_r", 11) == 0;
1939 /* If PC is in a Thumb call or return stub, return the address of the
1940 target PC, which is in a register. The thunk functions are called
1941 _called_via_xx, where x is the register name. The possible names
1942 are r0-r9, sl, fp, ip, sp, and lr. */
1945 arm_skip_stub (CORE_ADDR pc)
1948 CORE_ADDR start_addr;
1950 /* Find the starting address and name of the function containing the PC. */
1951 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1954 /* Call thunks always start with "_call_via_". */
1955 if (strncmp (name, "_call_via_", 10) == 0)
1957 /* Use the name suffix to determine which register contains the
1959 static char *table[15] =
1960 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1961 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
1965 for (regno = 0; regno <= 14; regno++)
1966 if (strcmp (&name[10], table[regno]) == 0)
1967 return read_register (regno);
1970 return 0; /* not a stub */
1973 /* If the user changes the register disassembly flavor used for info register
1974 and other commands, we have to also switch the flavor used in opcodes
1975 for disassembly output.
1976 This function is run in the set disassembly_flavor command, and does that. */
1979 set_disassembly_flavor_sfunc (char *args, int from_tty,
1980 struct cmd_list_element *c)
1982 set_disassembly_flavor ();
1986 set_disassembly_flavor (void)
1988 const char *setname, *setdesc, **regnames;
1991 /* Find the flavor that the user wants in the opcodes table. */
1993 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
1994 while ((disassembly_flavor != setname)
1995 && (current < num_flavor_options))
1996 get_arm_regnames (++current, &setname, &setdesc, ®names);
1997 current_option = current;
1999 /* Fill our copy. */
2000 for (j = 0; j < numregs; j++)
2001 arm_register_names[j] = (char *) regnames[j];
2004 if (isupper (*regnames[PC_REGNUM]))
2006 arm_register_names[FPS_REGNUM] = "FPS";
2007 arm_register_names[PS_REGNUM] = "CPSR";
2011 arm_register_names[FPS_REGNUM] = "fps";
2012 arm_register_names[PS_REGNUM] = "cpsr";
2015 /* Synchronize the disassembler. */
2016 set_arm_regname_option (current);
2019 /* arm_othernames implements the "othernames" command. This is kind
2020 of hacky, and I prefer the set-show disassembly-flavor which is
2021 also used for the x86 gdb. I will keep this around, however, in
2022 case anyone is actually using it. */
2025 arm_othernames (char *names, int n)
2027 /* Circle through the various flavors. */
2028 current_option = (current_option + 1) % num_flavor_options;
2030 disassembly_flavor = valid_flavors[current_option];
2031 set_disassembly_flavor ();
2035 _initialize_arm_tdep (void)
2037 struct ui_file *stb;
2039 struct cmd_list_element *new_cmd;
2040 const char *setname;
2041 const char *setdesc;
2042 const char **regnames;
2044 static char *helptext;
2046 tm_print_insn = gdb_print_insn_arm;
2048 /* Get the number of possible sets of register names defined in opcodes. */
2049 num_flavor_options = get_arm_regname_num_options ();
2051 /* Sync the opcode insn printer with our register viewer: */
2052 parse_arm_disassembler_option ("reg-names-std");
2054 /* Begin creating the help text. */
2055 stb = mem_fileopen ();
2056 fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
2057 The valid values are:\n");
2059 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2060 valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
2061 for (i = 0; i < num_flavor_options; i++)
2063 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2064 valid_flavors[i] = setname;
2065 fprintf_unfiltered (stb, "%s - %s\n", setname,
2067 /* Copy the default names (if found) and synchronize disassembler. */
2068 if (!strcmp (setname, "std"))
2070 disassembly_flavor = setname;
2072 for (j = 0; j < numregs; j++)
2073 arm_register_names[j] = (char *) regnames[j];
2074 set_arm_regname_option (i);
2077 /* Mark the end of valid options. */
2078 valid_flavors[num_flavor_options] = NULL;
2080 /* Finish the creation of the help text. */
2081 fprintf_unfiltered (stb, "The default is \"std\".");
2082 helptext = ui_file_xstrdup (stb, &length);
2083 ui_file_delete (stb);
2085 /* Add the disassembly-flavor command */
2086 new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
2088 &disassembly_flavor,
2091 new_cmd->function.sfunc = set_disassembly_flavor_sfunc;
2092 add_show_from_set (new_cmd, &showlist);
2094 /* ??? Maybe this should be a boolean. */
2095 add_show_from_set (add_set_cmd ("apcs32", no_class,
2096 var_zinteger, (char *) &arm_apcs_32,
2097 "Set usage of ARM 32-bit mode.\n", &setlist),
2100 /* Add the deprecated "othernames" command */
2102 add_com ("othernames", class_obscure, arm_othernames,
2103 "Switch to the next set of register names.");
2106 /* Test whether the coff symbol specific value corresponds to a Thumb
2110 coff_sym_is_thumb (int val)
2112 return (val == C_THUMBEXT ||
2113 val == C_THUMBSTAT ||
2114 val == C_THUMBEXTFUNC ||
2115 val == C_THUMBSTATFUNC ||
2116 val == C_THUMBLABEL);