1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
58 #include "features/arm-with-m.c"
59 #include "features/arm-with-iwmmxt.c"
60 #include "features/arm-with-vfpv2.c"
61 #include "features/arm-with-vfpv3.c"
62 #include "features/arm-with-neon.c"
66 /* Macros for setting and testing a bit in a minimal symbol that marks
67 it as Thumb function. The MSB of the minimal symbol's "info" field
68 is used for this purpose.
70 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
71 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
73 #define MSYMBOL_SET_SPECIAL(msym) \
74 MSYMBOL_TARGET_FLAG_1 (msym) = 1
76 #define MSYMBOL_IS_SPECIAL(msym) \
77 MSYMBOL_TARGET_FLAG_1 (msym)
79 /* Per-objfile data used for mapping symbols. */
80 static const struct objfile_data *arm_objfile_data_key;
82 struct arm_mapping_symbol
87 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
88 DEF_VEC_O(arm_mapping_symbol_s);
90 struct arm_per_objfile
92 VEC(arm_mapping_symbol_s) **section_maps;
95 /* The list of available "set arm ..." and "show arm ..." commands. */
96 static struct cmd_list_element *setarmcmdlist = NULL;
97 static struct cmd_list_element *showarmcmdlist = NULL;
99 /* The type of floating-point to use. Keep this in sync with enum
100 arm_float_model, and the help string in _initialize_arm_tdep. */
101 static const char *fp_model_strings[] =
111 /* A variable that can be configured by the user. */
112 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
113 static const char *current_fp_model = "auto";
115 /* The ABI to use. Keep this in sync with arm_abi_kind. */
116 static const char *arm_abi_strings[] =
124 /* A variable that can be configured by the user. */
125 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
126 static const char *arm_abi_string = "auto";
128 /* The execution mode to assume. */
129 static const char *arm_mode_strings[] =
137 static const char *arm_fallback_mode_string = "auto";
138 static const char *arm_force_mode_string = "auto";
140 /* Internal override of the execution mode. -1 means no override,
141 0 means override to ARM mode, 1 means override to Thumb mode.
142 The effect is the same as if arm_force_mode has been set by the
143 user (except the internal override has precedence over a user's
144 arm_force_mode override). */
145 static int arm_override_mode = -1;
147 /* Number of different reg name sets (options). */
148 static int num_disassembly_options;
150 /* The standard register names, and all the valid aliases for them. Note
151 that `fp', `sp' and `pc' are not added in this alias list, because they
152 have been added as builtin user registers in
153 std-regs.c:_initialize_frame_reg. */
158 } arm_register_aliases[] = {
159 /* Basic register numbers. */
176 /* Synonyms (argument and variable registers). */
189 /* Other platform-specific names for r9. */
195 /* Names used by GCC (not listed in the ARM EABI). */
197 /* A special name from the older ATPCS. */
201 static const char *const arm_register_names[] =
202 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
203 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
204 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
205 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
206 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
207 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
208 "fps", "cpsr" }; /* 24 25 */
210 /* Valid register name styles. */
211 static const char **valid_disassembly_styles;
213 /* Disassembly style to use. Default to "std" register names. */
214 static const char *disassembly_style;
216 /* This is used to keep the bfd arch_info in sync with the disassembly
218 static void set_disassembly_style_sfunc(char *, int,
219 struct cmd_list_element *);
220 static void set_disassembly_style (void);
222 static void convert_from_extended (const struct floatformat *, const void *,
224 static void convert_to_extended (const struct floatformat *, void *,
227 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
228 struct regcache *regcache,
229 int regnum, gdb_byte *buf);
230 static void arm_neon_quad_write (struct gdbarch *gdbarch,
231 struct regcache *regcache,
232 int regnum, const gdb_byte *buf);
234 struct arm_prologue_cache
236 /* The stack pointer at the time this frame was created; i.e. the
237 caller's stack pointer when this function was called. It is used
238 to identify this frame. */
241 /* The frame base for this frame is just prev_sp - frame size.
242 FRAMESIZE is the distance from the frame pointer to the
243 initial stack pointer. */
247 /* The register used to hold the frame pointer for this frame. */
250 /* Saved register offsets. */
251 struct trad_frame_saved_reg *saved_regs;
254 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
255 CORE_ADDR prologue_start,
256 CORE_ADDR prologue_end,
257 struct arm_prologue_cache *cache);
259 /* Architecture version for displaced stepping. This effects the behaviour of
260 certain instructions, and really should not be hard-wired. */
262 #define DISPLACED_STEPPING_ARCH_VERSION 5
264 /* Addresses for calling Thumb functions have the bit 0 set.
265 Here are some macros to test, set, or clear bit 0 of addresses. */
266 #define IS_THUMB_ADDR(addr) ((addr) & 1)
267 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
268 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
270 /* Set to true if the 32-bit mode is in use. */
274 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
277 arm_psr_thumb_bit (struct gdbarch *gdbarch)
279 if (gdbarch_tdep (gdbarch)->is_m)
285 /* Determine if FRAME is executing in Thumb mode. */
288 arm_frame_is_thumb (struct frame_info *frame)
291 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
293 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
294 directly (from a signal frame or dummy frame) or by interpreting
295 the saved LR (from a prologue or DWARF frame). So consult it and
296 trust the unwinders. */
297 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
299 return (cpsr & t_bit) != 0;
302 /* Callback for VEC_lower_bound. */
305 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
306 const struct arm_mapping_symbol *rhs)
308 return lhs->value < rhs->value;
311 /* Search for the mapping symbol covering MEMADDR. If one is found,
312 return its type. Otherwise, return 0. If START is non-NULL,
313 set *START to the location of the mapping symbol. */
316 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
318 struct obj_section *sec;
320 /* If there are mapping symbols, consult them. */
321 sec = find_pc_section (memaddr);
324 struct arm_per_objfile *data;
325 VEC(arm_mapping_symbol_s) *map;
326 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
330 data = objfile_data (sec->objfile, arm_objfile_data_key);
333 map = data->section_maps[sec->the_bfd_section->index];
334 if (!VEC_empty (arm_mapping_symbol_s, map))
336 struct arm_mapping_symbol *map_sym;
338 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
339 arm_compare_mapping_symbols);
341 /* VEC_lower_bound finds the earliest ordered insertion
342 point. If the following symbol starts at this exact
343 address, we use that; otherwise, the preceding
344 mapping symbol covers this address. */
345 if (idx < VEC_length (arm_mapping_symbol_s, map))
347 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
348 if (map_sym->value == map_key.value)
351 *start = map_sym->value + obj_section_addr (sec);
352 return map_sym->type;
358 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
360 *start = map_sym->value + obj_section_addr (sec);
361 return map_sym->type;
370 /* Determine if the program counter specified in MEMADDR is in a Thumb
371 function. This function should be called for addresses unrelated to
372 any executing frame; otherwise, prefer arm_frame_is_thumb. */
375 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
377 struct obj_section *sec;
378 struct minimal_symbol *sym;
380 struct displaced_step_closure* dsc
381 = get_displaced_step_closure_by_addr(memaddr);
383 /* If checking the mode of displaced instruction in copy area, the mode
384 should be determined by instruction on the original address. */
388 fprintf_unfiltered (gdb_stdlog,
389 "displaced: check mode of %.8lx instead of %.8lx\n",
390 (unsigned long) dsc->insn_addr,
391 (unsigned long) memaddr);
392 memaddr = dsc->insn_addr;
395 /* If bit 0 of the address is set, assume this is a Thumb address. */
396 if (IS_THUMB_ADDR (memaddr))
399 /* Respect internal mode override if active. */
400 if (arm_override_mode != -1)
401 return arm_override_mode;
403 /* If the user wants to override the symbol table, let him. */
404 if (strcmp (arm_force_mode_string, "arm") == 0)
406 if (strcmp (arm_force_mode_string, "thumb") == 0)
409 /* ARM v6-M and v7-M are always in Thumb mode. */
410 if (gdbarch_tdep (gdbarch)->is_m)
413 /* If there are mapping symbols, consult them. */
414 type = arm_find_mapping_symbol (memaddr, NULL);
418 /* Thumb functions have a "special" bit set in minimal symbols. */
419 sym = lookup_minimal_symbol_by_pc (memaddr);
421 return (MSYMBOL_IS_SPECIAL (sym));
423 /* If the user wants to override the fallback mode, let them. */
424 if (strcmp (arm_fallback_mode_string, "arm") == 0)
426 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
429 /* If we couldn't find any symbol, but we're talking to a running
430 target, then trust the current value of $cpsr. This lets
431 "display/i $pc" always show the correct mode (though if there is
432 a symbol table we will not reach here, so it still may not be
433 displayed in the mode it will be executed). */
434 if (target_has_registers)
435 return arm_frame_is_thumb (get_current_frame ());
437 /* Otherwise we're out of luck; we assume ARM. */
441 /* Remove useless bits from addresses in a running program. */
443 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
446 return UNMAKE_THUMB_ADDR (val);
448 return (val & 0x03fffffc);
451 /* When reading symbols, we need to zap the low bit of the address,
452 which may be set to 1 for Thumb functions. */
454 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
459 /* Return 1 if PC is the start of a compiler helper function which
460 can be safely ignored during prologue skipping. IS_THUMB is true
461 if the function is known to be a Thumb function due to the way it
464 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
466 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
467 struct minimal_symbol *msym;
469 msym = lookup_minimal_symbol_by_pc (pc);
471 && SYMBOL_VALUE_ADDRESS (msym) == pc
472 && SYMBOL_LINKAGE_NAME (msym) != NULL)
474 const char *name = SYMBOL_LINKAGE_NAME (msym);
476 /* The GNU linker's Thumb call stub to foo is named
478 if (strstr (name, "_from_thumb") != NULL)
481 /* On soft-float targets, __truncdfsf2 is called to convert promoted
482 arguments to their argument types in non-prototyped
484 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
486 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
489 /* Internal functions related to thread-local storage. */
490 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
492 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
497 /* If we run against a stripped glibc, we may be unable to identify
498 special functions by name. Check for one important case,
499 __aeabi_read_tp, by comparing the *code* against the default
500 implementation (this is hand-written ARM assembler in glibc). */
503 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
504 == 0xe3e00a0f /* mov r0, #0xffff0fff */
505 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
506 == 0xe240f01f) /* sub pc, r0, #31 */
513 /* Support routines for instruction parsing. */
514 #define submask(x) ((1L << ((x) + 1)) - 1)
515 #define bit(obj,st) (((obj) >> (st)) & 1)
516 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
517 #define sbits(obj,st,fn) \
518 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
519 #define BranchDest(addr,instr) \
520 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
522 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
523 the first 16-bit of instruction, and INSN2 is the second 16-bit of
525 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
526 ((bits ((insn1), 0, 3) << 12) \
527 | (bits ((insn1), 10, 10) << 11) \
528 | (bits ((insn2), 12, 14) << 8) \
529 | bits ((insn2), 0, 7))
531 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
532 the 32-bit instruction. */
533 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
534 ((bits ((insn), 16, 19) << 12) \
535 | bits ((insn), 0, 11))
537 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
540 thumb_expand_immediate (unsigned int imm)
542 unsigned int count = imm >> 7;
550 return (imm & 0xff) | ((imm & 0xff) << 16);
552 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
554 return (imm & 0xff) | ((imm & 0xff) << 8)
555 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
558 return (0x80 | (imm & 0x7f)) << (32 - count);
561 /* Return 1 if the 16-bit Thumb instruction INST might change
562 control flow, 0 otherwise. */
565 thumb_instruction_changes_pc (unsigned short inst)
567 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
570 if ((inst & 0xf000) == 0xd000) /* conditional branch */
573 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
576 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
579 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
582 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
588 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
589 might change control flow, 0 otherwise. */
592 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
594 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
596 /* Branches and miscellaneous control instructions. */
598 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
603 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
605 /* SUBS PC, LR, #imm8. */
608 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
610 /* Conditional branch. */
617 if ((inst1 & 0xfe50) == 0xe810)
619 /* Load multiple or RFE. */
621 if (bit (inst1, 7) && !bit (inst1, 8))
627 else if (!bit (inst1, 7) && bit (inst1, 8))
633 else if (bit (inst1, 7) && bit (inst1, 8))
638 else if (!bit (inst1, 7) && !bit (inst1, 8))
647 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
649 /* MOV PC or MOVS PC. */
653 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
656 if (bits (inst1, 0, 3) == 15)
662 if ((inst2 & 0x0fc0) == 0x0000)
668 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
674 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
683 /* Analyze a Thumb prologue, looking for a recognizable stack frame
684 and frame pointer. Scan until we encounter a store that could
685 clobber the stack frame unexpectedly, or an unknown instruction.
686 Return the last address which is definitely safe to skip for an
687 initial breakpoint. */
690 thumb_analyze_prologue (struct gdbarch *gdbarch,
691 CORE_ADDR start, CORE_ADDR limit,
692 struct arm_prologue_cache *cache)
694 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
695 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
698 struct pv_area *stack;
699 struct cleanup *back_to;
701 CORE_ADDR unrecognized_pc = 0;
703 for (i = 0; i < 16; i++)
704 regs[i] = pv_register (i, 0);
705 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
706 back_to = make_cleanup_free_pv_area (stack);
708 while (start < limit)
712 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
714 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
719 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
722 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
723 whether to save LR (R14). */
724 mask = (insn & 0xff) | ((insn & 0x100) << 6);
726 /* Calculate offsets of saved R0-R7 and LR. */
727 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
728 if (mask & (1 << regno))
730 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
732 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
735 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
738 offset = (insn & 0x7f) << 2; /* get scaled offset */
739 if (insn & 0x80) /* Check for SUB. */
740 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
743 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
746 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
747 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
749 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
750 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
751 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
753 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
754 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
755 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
757 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
758 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
759 && pv_is_constant (regs[bits (insn, 3, 5)]))
760 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
761 regs[bits (insn, 6, 8)]);
762 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
763 && pv_is_constant (regs[bits (insn, 3, 6)]))
765 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
766 int rm = bits (insn, 3, 6);
767 regs[rd] = pv_add (regs[rd], regs[rm]);
769 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
771 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
772 int src_reg = (insn & 0x78) >> 3;
773 regs[dst_reg] = regs[src_reg];
775 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
777 /* Handle stores to the stack. Normally pushes are used,
778 but with GCC -mtpcs-frame, there may be other stores
779 in the prologue to create the frame. */
780 int regno = (insn >> 8) & 0x7;
783 offset = (insn & 0xff) << 2;
784 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
786 if (pv_area_store_would_trash (stack, addr))
789 pv_area_store (stack, addr, 4, regs[regno]);
791 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
793 int rd = bits (insn, 0, 2);
794 int rn = bits (insn, 3, 5);
797 offset = bits (insn, 6, 10) << 2;
798 addr = pv_add_constant (regs[rn], offset);
800 if (pv_area_store_would_trash (stack, addr))
803 pv_area_store (stack, addr, 4, regs[rd]);
805 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
806 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
807 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
808 /* Ignore stores of argument registers to the stack. */
810 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
811 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
812 /* Ignore block loads from the stack, potentially copying
813 parameters from memory. */
815 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
816 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
817 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
818 /* Similarly ignore single loads from the stack. */
820 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
821 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
822 /* Skip register copies, i.e. saves to another register
823 instead of the stack. */
825 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
826 /* Recognize constant loads; even with small stacks these are necessary
828 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
829 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
831 /* Constant pool loads, for the same reason. */
832 unsigned int constant;
835 loc = start + 4 + bits (insn, 0, 7) * 4;
836 constant = read_memory_unsigned_integer (loc, 4, byte_order);
837 regs[bits (insn, 8, 10)] = pv_constant (constant);
839 else if ((insn & 0xe000) == 0xe000)
841 unsigned short inst2;
843 inst2 = read_memory_unsigned_integer (start + 2, 2,
844 byte_order_for_code);
846 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
848 /* BL, BLX. Allow some special function calls when
849 skipping the prologue; GCC generates these before
850 storing arguments to the stack. */
852 int j1, j2, imm1, imm2;
854 imm1 = sbits (insn, 0, 10);
855 imm2 = bits (inst2, 0, 10);
856 j1 = bit (inst2, 13);
857 j2 = bit (inst2, 11);
859 offset = ((imm1 << 12) + (imm2 << 1));
860 offset ^= ((!j2) << 22) | ((!j1) << 23);
862 nextpc = start + 4 + offset;
863 /* For BLX make sure to clear the low bits. */
864 if (bit (inst2, 12) == 0)
865 nextpc = nextpc & 0xfffffffc;
867 if (!skip_prologue_function (gdbarch, nextpc,
868 bit (inst2, 12) != 0))
872 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
874 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
876 pv_t addr = regs[bits (insn, 0, 3)];
879 if (pv_area_store_would_trash (stack, addr))
882 /* Calculate offsets of saved registers. */
883 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
884 if (inst2 & (1 << regno))
886 addr = pv_add_constant (addr, -4);
887 pv_area_store (stack, addr, 4, regs[regno]);
891 regs[bits (insn, 0, 3)] = addr;
894 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
896 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
898 int regno1 = bits (inst2, 12, 15);
899 int regno2 = bits (inst2, 8, 11);
900 pv_t addr = regs[bits (insn, 0, 3)];
902 offset = inst2 & 0xff;
904 addr = pv_add_constant (addr, offset);
906 addr = pv_add_constant (addr, -offset);
908 if (pv_area_store_would_trash (stack, addr))
911 pv_area_store (stack, addr, 4, regs[regno1]);
912 pv_area_store (stack, pv_add_constant (addr, 4),
916 regs[bits (insn, 0, 3)] = addr;
919 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
920 && (inst2 & 0x0c00) == 0x0c00
921 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
923 int regno = bits (inst2, 12, 15);
924 pv_t addr = regs[bits (insn, 0, 3)];
926 offset = inst2 & 0xff;
928 addr = pv_add_constant (addr, offset);
930 addr = pv_add_constant (addr, -offset);
932 if (pv_area_store_would_trash (stack, addr))
935 pv_area_store (stack, addr, 4, regs[regno]);
938 regs[bits (insn, 0, 3)] = addr;
941 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
942 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
944 int regno = bits (inst2, 12, 15);
947 offset = inst2 & 0xfff;
948 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
950 if (pv_area_store_would_trash (stack, addr))
953 pv_area_store (stack, addr, 4, regs[regno]);
956 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
957 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
958 /* Ignore stores of argument registers to the stack. */
961 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
962 && (inst2 & 0x0d00) == 0x0c00
963 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
964 /* Ignore stores of argument registers to the stack. */
967 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
969 && (inst2 & 0x8000) == 0x0000
970 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
971 /* Ignore block loads from the stack, potentially copying
972 parameters from memory. */
975 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
977 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
978 /* Similarly ignore dual loads from the stack. */
981 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
982 && (inst2 & 0x0d00) == 0x0c00
983 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
984 /* Similarly ignore single loads from the stack. */
987 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
988 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
989 /* Similarly ignore single loads from the stack. */
992 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
993 && (inst2 & 0x8000) == 0x0000)
995 unsigned int imm = ((bits (insn, 10, 10) << 11)
996 | (bits (inst2, 12, 14) << 8)
997 | bits (inst2, 0, 7));
999 regs[bits (inst2, 8, 11)]
1000 = pv_add_constant (regs[bits (insn, 0, 3)],
1001 thumb_expand_immediate (imm));
1004 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1005 && (inst2 & 0x8000) == 0x0000)
1007 unsigned int imm = ((bits (insn, 10, 10) << 11)
1008 | (bits (inst2, 12, 14) << 8)
1009 | bits (inst2, 0, 7));
1011 regs[bits (inst2, 8, 11)]
1012 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1015 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1016 && (inst2 & 0x8000) == 0x0000)
1018 unsigned int imm = ((bits (insn, 10, 10) << 11)
1019 | (bits (inst2, 12, 14) << 8)
1020 | bits (inst2, 0, 7));
1022 regs[bits (inst2, 8, 11)]
1023 = pv_add_constant (regs[bits (insn, 0, 3)],
1024 - (CORE_ADDR) thumb_expand_immediate (imm));
1027 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1028 && (inst2 & 0x8000) == 0x0000)
1030 unsigned int imm = ((bits (insn, 10, 10) << 11)
1031 | (bits (inst2, 12, 14) << 8)
1032 | bits (inst2, 0, 7));
1034 regs[bits (inst2, 8, 11)]
1035 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1038 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1040 unsigned int imm = ((bits (insn, 10, 10) << 11)
1041 | (bits (inst2, 12, 14) << 8)
1042 | bits (inst2, 0, 7));
1044 regs[bits (inst2, 8, 11)]
1045 = pv_constant (thumb_expand_immediate (imm));
1048 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1051 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1053 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1056 else if (insn == 0xea5f /* mov.w Rd,Rm */
1057 && (inst2 & 0xf0f0) == 0)
1059 int dst_reg = (inst2 & 0x0f00) >> 8;
1060 int src_reg = inst2 & 0xf;
1061 regs[dst_reg] = regs[src_reg];
1064 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1066 /* Constant pool loads. */
1067 unsigned int constant;
1070 offset = bits (insn, 0, 11);
1072 loc = start + 4 + offset;
1074 loc = start + 4 - offset;
1076 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1077 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1080 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1082 /* Constant pool loads. */
1083 unsigned int constant;
1086 offset = bits (insn, 0, 7) << 2;
1088 loc = start + 4 + offset;
1090 loc = start + 4 - offset;
1092 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1093 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1095 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1096 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1099 else if (thumb2_instruction_changes_pc (insn, inst2))
1101 /* Don't scan past anything that might change control flow. */
1106 /* The optimizer might shove anything into the prologue,
1107 so we just skip what we don't recognize. */
1108 unrecognized_pc = start;
1113 else if (thumb_instruction_changes_pc (insn))
1115 /* Don't scan past anything that might change control flow. */
1120 /* The optimizer might shove anything into the prologue,
1121 so we just skip what we don't recognize. */
1122 unrecognized_pc = start;
1129 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1130 paddress (gdbarch, start));
1132 if (unrecognized_pc == 0)
1133 unrecognized_pc = start;
1137 do_cleanups (back_to);
1138 return unrecognized_pc;
1141 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1143 /* Frame pointer is fp. Frame size is constant. */
1144 cache->framereg = ARM_FP_REGNUM;
1145 cache->framesize = -regs[ARM_FP_REGNUM].k;
1147 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1149 /* Frame pointer is r7. Frame size is constant. */
1150 cache->framereg = THUMB_FP_REGNUM;
1151 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1153 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1155 /* Try the stack pointer... this is a bit desperate. */
1156 cache->framereg = ARM_SP_REGNUM;
1157 cache->framesize = -regs[ARM_SP_REGNUM].k;
1161 /* We're just out of luck. We don't know where the frame is. */
1162 cache->framereg = -1;
1163 cache->framesize = 0;
1166 for (i = 0; i < 16; i++)
1167 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1168 cache->saved_regs[i].addr = offset;
1170 do_cleanups (back_to);
1171 return unrecognized_pc;
1175 /* Try to analyze the instructions starting from PC, which load symbol
1176 __stack_chk_guard. Return the address of instruction after loading this
1177 symbol, set the dest register number to *BASEREG, and set the size of
1178 instructions for loading symbol in OFFSET. Return 0 if instructions are
1182 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1183 unsigned int *destreg, int *offset)
1185 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1186 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1187 unsigned int low, high, address;
1192 unsigned short insn1
1193 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1195 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1197 *destreg = bits (insn1, 8, 10);
1199 address = bits (insn1, 0, 7);
1201 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1203 unsigned short insn2
1204 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1206 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1209 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1211 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1213 /* movt Rd, #const */
1214 if ((insn1 & 0xfbc0) == 0xf2c0)
1216 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1217 *destreg = bits (insn2, 8, 11);
1219 address = (high << 16 | low);
1226 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1228 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1230 address = bits (insn, 0, 11);
1231 *destreg = bits (insn, 12, 15);
1234 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1236 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1239 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1241 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1243 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1244 *destreg = bits (insn, 12, 15);
1246 address = (high << 16 | low);
1254 /* Try to skip a sequence of instructions used for stack protector. If PC
1255 points to the first instruction of this sequence, return the address of
1256 first instruction after this sequence, otherwise, return original PC.
1258 On arm, this sequence of instructions is composed of mainly three steps,
1259 Step 1: load symbol __stack_chk_guard,
1260 Step 2: load from address of __stack_chk_guard,
1261 Step 3: store it to somewhere else.
1263 Usually, instructions on step 2 and step 3 are the same on various ARM
1264 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1265 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1266 instructions in step 1 vary from different ARM architectures. On ARMv7,
1269 movw Rn, #:lower16:__stack_chk_guard
1270 movt Rn, #:upper16:__stack_chk_guard
1277 .word __stack_chk_guard
1279 Since ldr/str is a very popular instruction, we can't use them as
1280 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1281 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1282 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1285 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1287 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1288 unsigned int address, basereg;
1289 struct minimal_symbol *stack_chk_guard;
1291 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1294 /* Try to parse the instructions in Step 1. */
1295 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1300 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1301 /* If name of symbol doesn't start with '__stack_chk_guard', this
1302 instruction sequence is not for stack protector. If symbol is
1303 removed, we conservatively think this sequence is for stack protector. */
1305 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
1306 strlen ("__stack_chk_guard")) != 0)
1311 unsigned int destreg;
1313 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1315 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1316 if ((insn & 0xf800) != 0x6800)
1318 if (bits (insn, 3, 5) != basereg)
1320 destreg = bits (insn, 0, 2);
1322 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1323 byte_order_for_code);
1324 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1325 if ((insn & 0xf800) != 0x6000)
1327 if (destreg != bits (insn, 0, 2))
1332 unsigned int destreg;
1334 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1336 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1337 if ((insn & 0x0e500000) != 0x04100000)
1339 if (bits (insn, 16, 19) != basereg)
1341 destreg = bits (insn, 12, 15);
1342 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1343 insn = read_memory_unsigned_integer (pc + offset + 4,
1344 4, byte_order_for_code);
1345 if ((insn & 0x0e500000) != 0x04000000)
1347 if (bits (insn, 12, 15) != destreg)
1350 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1353 return pc + offset + 4;
1355 return pc + offset + 8;
1358 /* Advance the PC across any function entry prologue instructions to
1359 reach some "real" code.
1361 The APCS (ARM Procedure Call Standard) defines the following
1365 [stmfd sp!, {a1,a2,a3,a4}]
1366 stmfd sp!, {...,fp,ip,lr,pc}
1367 [stfe f7, [sp, #-12]!]
1368 [stfe f6, [sp, #-12]!]
1369 [stfe f5, [sp, #-12]!]
1370 [stfe f4, [sp, #-12]!]
1371 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1374 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1376 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1379 CORE_ADDR func_addr, limit_pc;
1380 struct symtab_and_line sal;
1382 /* See if we can determine the end of the prologue via the symbol table.
1383 If so, then return either PC, or the PC after the prologue, whichever
1385 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1387 CORE_ADDR post_prologue_pc
1388 = skip_prologue_using_sal (gdbarch, func_addr);
1389 struct symtab *s = find_pc_symtab (func_addr);
1391 if (post_prologue_pc)
1393 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1396 /* GCC always emits a line note before the prologue and another
1397 one after, even if the two are at the same address or on the
1398 same line. Take advantage of this so that we do not need to
1399 know every instruction that might appear in the prologue. We
1400 will have producer information for most binaries; if it is
1401 missing (e.g. for -gstabs), assuming the GNU tools. */
1402 if (post_prologue_pc
1404 || s->producer == NULL
1405 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0))
1406 return post_prologue_pc;
1408 if (post_prologue_pc != 0)
1410 CORE_ADDR analyzed_limit;
1412 /* For non-GCC compilers, make sure the entire line is an
1413 acceptable prologue; GDB will round this function's
1414 return value up to the end of the following line so we
1415 can not skip just part of a line (and we do not want to).
1417 RealView does not treat the prologue specially, but does
1418 associate prologue code with the opening brace; so this
1419 lets us skip the first line if we think it is the opening
1421 if (arm_pc_is_thumb (gdbarch, func_addr))
1422 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1423 post_prologue_pc, NULL);
1425 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1426 post_prologue_pc, NULL);
1428 if (analyzed_limit != post_prologue_pc)
1431 return post_prologue_pc;
1435 /* Can't determine prologue from the symbol table, need to examine
1438 /* Find an upper limit on the function prologue using the debug
1439 information. If the debug information could not be used to provide
1440 that bound, then use an arbitrary large number as the upper bound. */
1441 /* Like arm_scan_prologue, stop no later than pc + 64. */
1442 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1444 limit_pc = pc + 64; /* Magic. */
1447 /* Check if this is Thumb code. */
1448 if (arm_pc_is_thumb (gdbarch, pc))
1449 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1451 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1453 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1455 /* "mov ip, sp" is no longer a required part of the prologue. */
1456 if (inst == 0xe1a0c00d) /* mov ip, sp */
1459 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1462 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1465 /* Some prologues begin with "str lr, [sp, #-4]!". */
1466 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1469 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1472 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1475 /* Any insns after this point may float into the code, if it makes
1476 for better instruction scheduling, so we skip them only if we
1477 find them, but still consider the function to be frame-ful. */
1479 /* We may have either one sfmfd instruction here, or several stfe
1480 insns, depending on the version of floating point code we
1482 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1485 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1488 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1491 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1494 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1495 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1496 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1499 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1500 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1501 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1504 /* Un-recognized instruction; stop scanning. */
1508 return skip_pc; /* End of prologue. */
1512 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1513 This function decodes a Thumb function prologue to determine:
1514 1) the size of the stack frame
1515 2) which registers are saved on it
1516 3) the offsets of saved regs
1517 4) the offset from the stack pointer to the frame pointer
1519 A typical Thumb function prologue would create this stack frame
1520 (offsets relative to FP)
1521 old SP -> 24 stack parameters
1524 R7 -> 0 local variables (16 bytes)
1525 SP -> -12 additional stack space (12 bytes)
1526 The frame size would thus be 36 bytes, and the frame offset would be
1527 12 bytes. The frame register is R7.
1529 The comments for thumb_skip_prolog() describe the algorithm we use
1530 to detect the end of the prolog. */
1534 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1535 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1537 CORE_ADDR prologue_start;
1538 CORE_ADDR prologue_end;
1539 CORE_ADDR current_pc;
1541 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1544 /* See comment in arm_scan_prologue for an explanation of
1546 if (prologue_end > prologue_start + 64)
1548 prologue_end = prologue_start + 64;
1552 /* We're in the boondocks: we have no idea where the start of the
1556 prologue_end = min (prologue_end, prev_pc);
1558 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1561 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1564 arm_instruction_changes_pc (uint32_t this_instr)
1566 if (bits (this_instr, 28, 31) == INST_NV)
1567 /* Unconditional instructions. */
1568 switch (bits (this_instr, 24, 27))
1572 /* Branch with Link and change to Thumb. */
1577 /* Coprocessor register transfer. */
1578 if (bits (this_instr, 12, 15) == 15)
1579 error (_("Invalid update to pc in instruction"));
1585 switch (bits (this_instr, 25, 27))
1588 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1590 /* Multiplies and extra load/stores. */
1591 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1592 /* Neither multiplies nor extension load/stores are allowed
1596 /* Otherwise, miscellaneous instructions. */
1598 /* BX <reg>, BXJ <reg>, BLX <reg> */
1599 if (bits (this_instr, 4, 27) == 0x12fff1
1600 || bits (this_instr, 4, 27) == 0x12fff2
1601 || bits (this_instr, 4, 27) == 0x12fff3)
1604 /* Other miscellaneous instructions are unpredictable if they
1608 /* Data processing instruction. Fall through. */
1611 if (bits (this_instr, 12, 15) == 15)
1618 /* Media instructions and architecturally undefined instructions. */
1619 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1623 if (bit (this_instr, 20) == 0)
1627 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1633 /* Load/store multiple. */
1634 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1640 /* Branch and branch with link. */
1645 /* Coprocessor transfers or SWIs can not affect PC. */
1649 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1653 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1654 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1655 fill it in. Return the first address not recognized as a prologue
1658 We recognize all the instructions typically found in ARM prologues,
1659 plus harmless instructions which can be skipped (either for analysis
1660 purposes, or a more restrictive set that can be skipped when finding
1661 the end of the prologue). */
1664 arm_analyze_prologue (struct gdbarch *gdbarch,
1665 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1666 struct arm_prologue_cache *cache)
1668 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1669 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1671 CORE_ADDR offset, current_pc;
1672 pv_t regs[ARM_FPS_REGNUM];
1673 struct pv_area *stack;
1674 struct cleanup *back_to;
1675 int framereg, framesize;
1676 CORE_ADDR unrecognized_pc = 0;
1678 /* Search the prologue looking for instructions that set up the
1679 frame pointer, adjust the stack pointer, and save registers.
1681 Be careful, however, and if it doesn't look like a prologue,
1682 don't try to scan it. If, for instance, a frameless function
1683 begins with stmfd sp!, then we will tell ourselves there is
1684 a frame, which will confuse stack traceback, as well as "finish"
1685 and other operations that rely on a knowledge of the stack
1688 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1689 regs[regno] = pv_register (regno, 0);
1690 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1691 back_to = make_cleanup_free_pv_area (stack);
1693 for (current_pc = prologue_start;
1694 current_pc < prologue_end;
1698 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1700 if (insn == 0xe1a0c00d) /* mov ip, sp */
1702 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1705 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1706 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1708 unsigned imm = insn & 0xff; /* immediate value */
1709 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1710 int rd = bits (insn, 12, 15);
1711 imm = (imm >> rot) | (imm << (32 - rot));
1712 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1715 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1716 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1718 unsigned imm = insn & 0xff; /* immediate value */
1719 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1720 int rd = bits (insn, 12, 15);
1721 imm = (imm >> rot) | (imm << (32 - rot));
1722 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1725 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1728 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1730 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1731 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1732 regs[bits (insn, 12, 15)]);
1735 else if ((insn & 0xffff0000) == 0xe92d0000)
1736 /* stmfd sp!, {..., fp, ip, lr, pc}
1738 stmfd sp!, {a1, a2, a3, a4} */
1740 int mask = insn & 0xffff;
1742 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1745 /* Calculate offsets of saved registers. */
1746 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1747 if (mask & (1 << regno))
1750 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1751 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1754 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1755 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1756 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1758 /* No need to add this to saved_regs -- it's just an arg reg. */
1761 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1762 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1763 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1765 /* No need to add this to saved_regs -- it's just an arg reg. */
1768 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1770 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1772 /* No need to add this to saved_regs -- it's just arg regs. */
1775 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1777 unsigned imm = insn & 0xff; /* immediate value */
1778 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1779 imm = (imm >> rot) | (imm << (32 - rot));
1780 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1782 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1784 unsigned imm = insn & 0xff; /* immediate value */
1785 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1786 imm = (imm >> rot) | (imm << (32 - rot));
1787 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1789 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1791 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1793 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1796 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1797 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1798 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1800 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1802 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1804 int n_saved_fp_regs;
1805 unsigned int fp_start_reg, fp_bound_reg;
1807 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1810 if ((insn & 0x800) == 0x800) /* N0 is set */
1812 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1813 n_saved_fp_regs = 3;
1815 n_saved_fp_regs = 1;
1819 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1820 n_saved_fp_regs = 2;
1822 n_saved_fp_regs = 4;
1825 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1826 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1827 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1829 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1830 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1831 regs[fp_start_reg++]);
1834 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1836 /* Allow some special function calls when skipping the
1837 prologue; GCC generates these before storing arguments to
1839 CORE_ADDR dest = BranchDest (current_pc, insn);
1841 if (skip_prologue_function (gdbarch, dest, 0))
1846 else if ((insn & 0xf0000000) != 0xe0000000)
1847 break; /* Condition not true, exit early. */
1848 else if (arm_instruction_changes_pc (insn))
1849 /* Don't scan past anything that might change control flow. */
1851 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1852 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1853 /* Ignore block loads from the stack, potentially copying
1854 parameters from memory. */
1856 else if ((insn & 0xfc500000) == 0xe4100000
1857 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1858 /* Similarly ignore single loads from the stack. */
1860 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1861 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1862 register instead of the stack. */
1866 /* The optimizer might shove anything into the prologue,
1867 so we just skip what we don't recognize. */
1868 unrecognized_pc = current_pc;
1873 if (unrecognized_pc == 0)
1874 unrecognized_pc = current_pc;
1876 /* The frame size is just the distance from the frame register
1877 to the original stack pointer. */
1878 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1880 /* Frame pointer is fp. */
1881 framereg = ARM_FP_REGNUM;
1882 framesize = -regs[ARM_FP_REGNUM].k;
1884 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1886 /* Try the stack pointer... this is a bit desperate. */
1887 framereg = ARM_SP_REGNUM;
1888 framesize = -regs[ARM_SP_REGNUM].k;
1892 /* We're just out of luck. We don't know where the frame is. */
1899 cache->framereg = framereg;
1900 cache->framesize = framesize;
1902 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1903 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1904 cache->saved_regs[regno].addr = offset;
1908 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1909 paddress (gdbarch, unrecognized_pc));
1911 do_cleanups (back_to);
1912 return unrecognized_pc;
1916 arm_scan_prologue (struct frame_info *this_frame,
1917 struct arm_prologue_cache *cache)
1919 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1920 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1922 CORE_ADDR prologue_start, prologue_end, current_pc;
1923 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1924 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1925 pv_t regs[ARM_FPS_REGNUM];
1926 struct pv_area *stack;
1927 struct cleanup *back_to;
1930 /* Assume there is no frame until proven otherwise. */
1931 cache->framereg = ARM_SP_REGNUM;
1932 cache->framesize = 0;
1934 /* Check for Thumb prologue. */
1935 if (arm_frame_is_thumb (this_frame))
1937 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1941 /* Find the function prologue. If we can't find the function in
1942 the symbol table, peek in the stack frame to find the PC. */
1943 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1946 /* One way to find the end of the prologue (which works well
1947 for unoptimized code) is to do the following:
1949 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1952 prologue_end = prev_pc;
1953 else if (sal.end < prologue_end)
1954 prologue_end = sal.end;
1956 This mechanism is very accurate so long as the optimizer
1957 doesn't move any instructions from the function body into the
1958 prologue. If this happens, sal.end will be the last
1959 instruction in the first hunk of prologue code just before
1960 the first instruction that the scheduler has moved from
1961 the body to the prologue.
1963 In order to make sure that we scan all of the prologue
1964 instructions, we use a slightly less accurate mechanism which
1965 may scan more than necessary. To help compensate for this
1966 lack of accuracy, the prologue scanning loop below contains
1967 several clauses which'll cause the loop to terminate early if
1968 an implausible prologue instruction is encountered.
1974 is a suitable endpoint since it accounts for the largest
1975 possible prologue plus up to five instructions inserted by
1978 if (prologue_end > prologue_start + 64)
1980 prologue_end = prologue_start + 64; /* See above. */
1985 /* We have no symbol information. Our only option is to assume this
1986 function has a standard stack frame and the normal frame register.
1987 Then, we can find the value of our frame pointer on entrance to
1988 the callee (or at the present moment if this is the innermost frame).
1989 The value stored there should be the address of the stmfd + 8. */
1990 CORE_ADDR frame_loc;
1991 LONGEST return_value;
1993 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1994 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1998 prologue_start = gdbarch_addr_bits_remove
1999 (gdbarch, return_value) - 8;
2000 prologue_end = prologue_start + 64; /* See above. */
2004 if (prev_pc < prologue_end)
2005 prologue_end = prev_pc;
2007 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2010 static struct arm_prologue_cache *
2011 arm_make_prologue_cache (struct frame_info *this_frame)
2014 struct arm_prologue_cache *cache;
2015 CORE_ADDR unwound_fp;
2017 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2018 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2020 arm_scan_prologue (this_frame, cache);
2022 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2023 if (unwound_fp == 0)
2026 cache->prev_sp = unwound_fp + cache->framesize;
2028 /* Calculate actual addresses of saved registers using offsets
2029 determined by arm_scan_prologue. */
2030 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2031 if (trad_frame_addr_p (cache->saved_regs, reg))
2032 cache->saved_regs[reg].addr += cache->prev_sp;
2037 /* Our frame ID for a normal frame is the current function's starting PC
2038 and the caller's SP when we were called. */
2041 arm_prologue_this_id (struct frame_info *this_frame,
2043 struct frame_id *this_id)
2045 struct arm_prologue_cache *cache;
2049 if (*this_cache == NULL)
2050 *this_cache = arm_make_prologue_cache (this_frame);
2051 cache = *this_cache;
2053 /* This is meant to halt the backtrace at "_start". */
2054 pc = get_frame_pc (this_frame);
2055 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2058 /* If we've hit a wall, stop. */
2059 if (cache->prev_sp == 0)
2062 /* Use function start address as part of the frame ID. If we cannot
2063 identify the start address (due to missing symbol information),
2064 fall back to just using the current PC. */
2065 func = get_frame_func (this_frame);
2069 id = frame_id_build (cache->prev_sp, func);
2073 static struct value *
2074 arm_prologue_prev_register (struct frame_info *this_frame,
2078 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2079 struct arm_prologue_cache *cache;
2081 if (*this_cache == NULL)
2082 *this_cache = arm_make_prologue_cache (this_frame);
2083 cache = *this_cache;
2085 /* If we are asked to unwind the PC, then we need to return the LR
2086 instead. The prologue may save PC, but it will point into this
2087 frame's prologue, not the next frame's resume location. Also
2088 strip the saved T bit. A valid LR may have the low bit set, but
2089 a valid PC never does. */
2090 if (prev_regnum == ARM_PC_REGNUM)
2094 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2095 return frame_unwind_got_constant (this_frame, prev_regnum,
2096 arm_addr_bits_remove (gdbarch, lr));
2099 /* SP is generally not saved to the stack, but this frame is
2100 identified by the next frame's stack pointer at the time of the call.
2101 The value was already reconstructed into PREV_SP. */
2102 if (prev_regnum == ARM_SP_REGNUM)
2103 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2105 /* The CPSR may have been changed by the call instruction and by the
2106 called function. The only bit we can reconstruct is the T bit,
2107 by checking the low bit of LR as of the call. This is a reliable
2108 indicator of Thumb-ness except for some ARM v4T pre-interworking
2109 Thumb code, which could get away with a clear low bit as long as
2110 the called function did not use bx. Guess that all other
2111 bits are unchanged; the condition flags are presumably lost,
2112 but the processor status is likely valid. */
2113 if (prev_regnum == ARM_PS_REGNUM)
2116 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2118 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2119 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2120 if (IS_THUMB_ADDR (lr))
2124 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2127 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2131 struct frame_unwind arm_prologue_unwind = {
2133 default_frame_unwind_stop_reason,
2134 arm_prologue_this_id,
2135 arm_prologue_prev_register,
2137 default_frame_sniffer
2140 /* Maintain a list of ARM exception table entries per objfile, similar to the
2141 list of mapping symbols. We only cache entries for standard ARM-defined
2142 personality routines; the cache will contain only the frame unwinding
2143 instructions associated with the entry (not the descriptors). */
2145 static const struct objfile_data *arm_exidx_data_key;
2147 struct arm_exidx_entry
2152 typedef struct arm_exidx_entry arm_exidx_entry_s;
2153 DEF_VEC_O(arm_exidx_entry_s);
2155 struct arm_exidx_data
2157 VEC(arm_exidx_entry_s) **section_maps;
2161 arm_exidx_data_free (struct objfile *objfile, void *arg)
2163 struct arm_exidx_data *data = arg;
2166 for (i = 0; i < objfile->obfd->section_count; i++)
2167 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2171 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2172 const struct arm_exidx_entry *rhs)
2174 return lhs->addr < rhs->addr;
2177 static struct obj_section *
2178 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2180 struct obj_section *osect;
2182 ALL_OBJFILE_OSECTIONS (objfile, osect)
2183 if (bfd_get_section_flags (objfile->obfd,
2184 osect->the_bfd_section) & SEC_ALLOC)
2186 bfd_vma start, size;
2187 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2188 size = bfd_get_section_size (osect->the_bfd_section);
2190 if (start <= vma && vma < start + size)
2197 /* Parse contents of exception table and exception index sections
2198 of OBJFILE, and fill in the exception table entry cache.
2200 For each entry that refers to a standard ARM-defined personality
2201 routine, extract the frame unwinding instructions (from either
2202 the index or the table section). The unwinding instructions
2204 - extracting them from the rest of the table data
2205 - converting to host endianness
2206 - appending the implicit 0xb0 ("Finish") code
2208 The extracted and normalized instructions are stored for later
2209 retrieval by the arm_find_exidx_entry routine. */
2212 arm_exidx_new_objfile (struct objfile *objfile)
2214 struct cleanup *cleanups;
2215 struct arm_exidx_data *data;
2216 asection *exidx, *extab;
2217 bfd_vma exidx_vma = 0, extab_vma = 0;
2218 bfd_size_type exidx_size = 0, extab_size = 0;
2219 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2222 /* If we've already touched this file, do nothing. */
2223 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2225 cleanups = make_cleanup (null_cleanup, NULL);
2227 /* Read contents of exception table and index. */
2228 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2231 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2232 exidx_size = bfd_get_section_size (exidx);
2233 exidx_data = xmalloc (exidx_size);
2234 make_cleanup (xfree, exidx_data);
2236 if (!bfd_get_section_contents (objfile->obfd, exidx,
2237 exidx_data, 0, exidx_size))
2239 do_cleanups (cleanups);
2244 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2247 extab_vma = bfd_section_vma (objfile->obfd, extab);
2248 extab_size = bfd_get_section_size (extab);
2249 extab_data = xmalloc (extab_size);
2250 make_cleanup (xfree, extab_data);
2252 if (!bfd_get_section_contents (objfile->obfd, extab,
2253 extab_data, 0, extab_size))
2255 do_cleanups (cleanups);
2260 /* Allocate exception table data structure. */
2261 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2262 set_objfile_data (objfile, arm_exidx_data_key, data);
2263 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2264 objfile->obfd->section_count,
2265 VEC(arm_exidx_entry_s) *);
2267 /* Fill in exception table. */
2268 for (i = 0; i < exidx_size / 8; i++)
2270 struct arm_exidx_entry new_exidx_entry;
2271 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2272 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2273 bfd_vma addr = 0, word = 0;
2274 int n_bytes = 0, n_words = 0;
2275 struct obj_section *sec;
2276 gdb_byte *entry = NULL;
2278 /* Extract address of start of function. */
2279 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2280 idx += exidx_vma + i * 8;
2282 /* Find section containing function and compute section offset. */
2283 sec = arm_obj_section_from_vma (objfile, idx);
2286 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2288 /* Determine address of exception table entry. */
2291 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2293 else if ((val & 0xff000000) == 0x80000000)
2295 /* Exception table entry embedded in .ARM.exidx
2296 -- must be short form. */
2300 else if (!(val & 0x80000000))
2302 /* Exception table entry in .ARM.extab. */
2303 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2304 addr += exidx_vma + i * 8 + 4;
2306 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2308 word = bfd_h_get_32 (objfile->obfd,
2309 extab_data + addr - extab_vma);
2312 if ((word & 0xff000000) == 0x80000000)
2317 else if ((word & 0xff000000) == 0x81000000
2318 || (word & 0xff000000) == 0x82000000)
2322 n_words = ((word >> 16) & 0xff);
2324 else if (!(word & 0x80000000))
2327 struct obj_section *pers_sec;
2328 int gnu_personality = 0;
2330 /* Custom personality routine. */
2331 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2332 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2334 /* Check whether we've got one of the variants of the
2335 GNU personality routines. */
2336 pers_sec = arm_obj_section_from_vma (objfile, pers);
2339 static const char *personality[] =
2341 "__gcc_personality_v0",
2342 "__gxx_personality_v0",
2343 "__gcj_personality_v0",
2344 "__gnu_objc_personality_v0",
2348 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2351 for (k = 0; personality[k]; k++)
2352 if (lookup_minimal_symbol_by_pc_name
2353 (pc, personality[k], objfile))
2355 gnu_personality = 1;
2360 /* If so, the next word contains a word count in the high
2361 byte, followed by the same unwind instructions as the
2362 pre-defined forms. */
2364 && addr + 4 <= extab_vma + extab_size)
2366 word = bfd_h_get_32 (objfile->obfd,
2367 extab_data + addr - extab_vma);
2370 n_words = ((word >> 24) & 0xff);
2376 /* Sanity check address. */
2378 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2379 n_words = n_bytes = 0;
2381 /* The unwind instructions reside in WORD (only the N_BYTES least
2382 significant bytes are valid), followed by N_WORDS words in the
2383 extab section starting at ADDR. */
2384 if (n_bytes || n_words)
2386 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2387 n_bytes + n_words * 4 + 1);
2390 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2394 word = bfd_h_get_32 (objfile->obfd,
2395 extab_data + addr - extab_vma);
2398 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2399 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2400 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2401 *p++ = (gdb_byte) (word & 0xff);
2404 /* Implied "Finish" to terminate the list. */
2408 /* Push entry onto vector. They are guaranteed to always
2409 appear in order of increasing addresses. */
2410 new_exidx_entry.addr = idx;
2411 new_exidx_entry.entry = entry;
2412 VEC_safe_push (arm_exidx_entry_s,
2413 data->section_maps[sec->the_bfd_section->index],
2417 do_cleanups (cleanups);
2420 /* Search for the exception table entry covering MEMADDR. If one is found,
2421 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2422 set *START to the start of the region covered by this entry. */
2425 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2427 struct obj_section *sec;
2429 sec = find_pc_section (memaddr);
2432 struct arm_exidx_data *data;
2433 VEC(arm_exidx_entry_s) *map;
2434 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2437 data = objfile_data (sec->objfile, arm_exidx_data_key);
2440 map = data->section_maps[sec->the_bfd_section->index];
2441 if (!VEC_empty (arm_exidx_entry_s, map))
2443 struct arm_exidx_entry *map_sym;
2445 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2446 arm_compare_exidx_entries);
2448 /* VEC_lower_bound finds the earliest ordered insertion
2449 point. If the following symbol starts at this exact
2450 address, we use that; otherwise, the preceding
2451 exception table entry covers this address. */
2452 if (idx < VEC_length (arm_exidx_entry_s, map))
2454 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2455 if (map_sym->addr == map_key.addr)
2458 *start = map_sym->addr + obj_section_addr (sec);
2459 return map_sym->entry;
2465 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2467 *start = map_sym->addr + obj_section_addr (sec);
2468 return map_sym->entry;
2477 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2478 instruction list from the ARM exception table entry ENTRY, allocate and
2479 return a prologue cache structure describing how to unwind this frame.
2481 Return NULL if the unwinding instruction list contains a "spare",
2482 "reserved" or "refuse to unwind" instruction as defined in section
2483 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2484 for the ARM Architecture" document. */
2486 static struct arm_prologue_cache *
2487 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2492 struct arm_prologue_cache *cache;
2493 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2494 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2500 /* Whenever we reload SP, we actually have to retrieve its
2501 actual value in the current frame. */
2504 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2506 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2507 vsp = get_frame_register_unsigned (this_frame, reg);
2511 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2512 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2518 /* Decode next unwind instruction. */
2521 if ((insn & 0xc0) == 0)
2523 int offset = insn & 0x3f;
2524 vsp += (offset << 2) + 4;
2526 else if ((insn & 0xc0) == 0x40)
2528 int offset = insn & 0x3f;
2529 vsp -= (offset << 2) + 4;
2531 else if ((insn & 0xf0) == 0x80)
2533 int mask = ((insn & 0xf) << 8) | *entry++;
2536 /* The special case of an all-zero mask identifies
2537 "Refuse to unwind". We return NULL to fall back
2538 to the prologue analyzer. */
2542 /* Pop registers r4..r15 under mask. */
2543 for (i = 0; i < 12; i++)
2544 if (mask & (1 << i))
2546 cache->saved_regs[4 + i].addr = vsp;
2550 /* Special-case popping SP -- we need to reload vsp. */
2551 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2554 else if ((insn & 0xf0) == 0x90)
2556 int reg = insn & 0xf;
2558 /* Reserved cases. */
2559 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2562 /* Set SP from another register and mark VSP for reload. */
2563 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2566 else if ((insn & 0xf0) == 0xa0)
2568 int count = insn & 0x7;
2569 int pop_lr = (insn & 0x8) != 0;
2572 /* Pop r4..r[4+count]. */
2573 for (i = 0; i <= count; i++)
2575 cache->saved_regs[4 + i].addr = vsp;
2579 /* If indicated by flag, pop LR as well. */
2582 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2586 else if (insn == 0xb0)
2588 /* We could only have updated PC by popping into it; if so, it
2589 will show up as address. Otherwise, copy LR into PC. */
2590 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2591 cache->saved_regs[ARM_PC_REGNUM]
2592 = cache->saved_regs[ARM_LR_REGNUM];
2597 else if (insn == 0xb1)
2599 int mask = *entry++;
2602 /* All-zero mask and mask >= 16 is "spare". */
2603 if (mask == 0 || mask >= 16)
2606 /* Pop r0..r3 under mask. */
2607 for (i = 0; i < 4; i++)
2608 if (mask & (1 << i))
2610 cache->saved_regs[i].addr = vsp;
2614 else if (insn == 0xb2)
2616 ULONGEST offset = 0;
2621 offset |= (*entry & 0x7f) << shift;
2624 while (*entry++ & 0x80);
2626 vsp += 0x204 + (offset << 2);
2628 else if (insn == 0xb3)
2630 int start = *entry >> 4;
2631 int count = (*entry++) & 0xf;
2634 /* Only registers D0..D15 are valid here. */
2635 if (start + count >= 16)
2638 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2639 for (i = 0; i <= count; i++)
2641 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2645 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2648 else if ((insn & 0xf8) == 0xb8)
2650 int count = insn & 0x7;
2653 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2654 for (i = 0; i <= count; i++)
2656 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2660 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2663 else if (insn == 0xc6)
2665 int start = *entry >> 4;
2666 int count = (*entry++) & 0xf;
2669 /* Only registers WR0..WR15 are valid. */
2670 if (start + count >= 16)
2673 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2674 for (i = 0; i <= count; i++)
2676 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2680 else if (insn == 0xc7)
2682 int mask = *entry++;
2685 /* All-zero mask and mask >= 16 is "spare". */
2686 if (mask == 0 || mask >= 16)
2689 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2690 for (i = 0; i < 4; i++)
2691 if (mask & (1 << i))
2693 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2697 else if ((insn & 0xf8) == 0xc0)
2699 int count = insn & 0x7;
2702 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2703 for (i = 0; i <= count; i++)
2705 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2709 else if (insn == 0xc8)
2711 int start = *entry >> 4;
2712 int count = (*entry++) & 0xf;
2715 /* Only registers D0..D31 are valid. */
2716 if (start + count >= 16)
2719 /* Pop VFP double-precision registers
2720 D[16+start]..D[16+start+count]. */
2721 for (i = 0; i <= count; i++)
2723 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2727 else if (insn == 0xc9)
2729 int start = *entry >> 4;
2730 int count = (*entry++) & 0xf;
2733 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2734 for (i = 0; i <= count; i++)
2736 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2740 else if ((insn & 0xf8) == 0xd0)
2742 int count = insn & 0x7;
2745 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2746 for (i = 0; i <= count; i++)
2748 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2754 /* Everything else is "spare". */
2759 /* If we restore SP from a register, assume this was the frame register.
2760 Otherwise just fall back to SP as frame register. */
2761 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2762 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2764 cache->framereg = ARM_SP_REGNUM;
2766 /* Determine offset to previous frame. */
2768 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2770 /* We already got the previous SP. */
2771 cache->prev_sp = vsp;
2776 /* Unwinding via ARM exception table entries. Note that the sniffer
2777 already computes a filled-in prologue cache, which is then used
2778 with the same arm_prologue_this_id and arm_prologue_prev_register
2779 routines also used for prologue-parsing based unwinding. */
2782 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2783 struct frame_info *this_frame,
2784 void **this_prologue_cache)
2786 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2787 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2788 CORE_ADDR addr_in_block, exidx_region, func_start;
2789 struct arm_prologue_cache *cache;
2792 /* See if we have an ARM exception table entry covering this address. */
2793 addr_in_block = get_frame_address_in_block (this_frame);
2794 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2798 /* The ARM exception table does not describe unwind information
2799 for arbitrary PC values, but is guaranteed to be correct only
2800 at call sites. We have to decide here whether we want to use
2801 ARM exception table information for this frame, or fall back
2802 to using prologue parsing. (Note that if we have DWARF CFI,
2803 this sniffer isn't even called -- CFI is always preferred.)
2805 Before we make this decision, however, we check whether we
2806 actually have *symbol* information for the current frame.
2807 If not, prologue parsing would not work anyway, so we might
2808 as well use the exception table and hope for the best. */
2809 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2813 /* If the next frame is "normal", we are at a call site in this
2814 frame, so exception information is guaranteed to be valid. */
2815 if (get_next_frame (this_frame)
2816 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2819 /* We also assume exception information is valid if we're currently
2820 blocked in a system call. The system library is supposed to
2821 ensure this, so that e.g. pthread cancellation works. */
2822 if (arm_frame_is_thumb (this_frame))
2826 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2827 byte_order_for_code, &insn)
2828 && (insn & 0xff00) == 0xdf00 /* svc */)
2835 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2836 byte_order_for_code, &insn)
2837 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2841 /* Bail out if we don't know that exception information is valid. */
2845 /* The ARM exception index does not mark the *end* of the region
2846 covered by the entry, and some functions will not have any entry.
2847 To correctly recognize the end of the covered region, the linker
2848 should have inserted dummy records with a CANTUNWIND marker.
2850 Unfortunately, current versions of GNU ld do not reliably do
2851 this, and thus we may have found an incorrect entry above.
2852 As a (temporary) sanity check, we only use the entry if it
2853 lies *within* the bounds of the function. Note that this check
2854 might reject perfectly valid entries that just happen to cover
2855 multiple functions; therefore this check ought to be removed
2856 once the linker is fixed. */
2857 if (func_start > exidx_region)
2861 /* Decode the list of unwinding instructions into a prologue cache.
2862 Note that this may fail due to e.g. a "refuse to unwind" code. */
2863 cache = arm_exidx_fill_cache (this_frame, entry);
2867 *this_prologue_cache = cache;
2871 struct frame_unwind arm_exidx_unwind = {
2873 default_frame_unwind_stop_reason,
2874 arm_prologue_this_id,
2875 arm_prologue_prev_register,
2877 arm_exidx_unwind_sniffer
2880 static struct arm_prologue_cache *
2881 arm_make_stub_cache (struct frame_info *this_frame)
2883 struct arm_prologue_cache *cache;
2885 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2886 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2888 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2893 /* Our frame ID for a stub frame is the current SP and LR. */
2896 arm_stub_this_id (struct frame_info *this_frame,
2898 struct frame_id *this_id)
2900 struct arm_prologue_cache *cache;
2902 if (*this_cache == NULL)
2903 *this_cache = arm_make_stub_cache (this_frame);
2904 cache = *this_cache;
2906 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2910 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2911 struct frame_info *this_frame,
2912 void **this_prologue_cache)
2914 CORE_ADDR addr_in_block;
2917 addr_in_block = get_frame_address_in_block (this_frame);
2918 if (in_plt_section (addr_in_block, NULL)
2919 /* We also use the stub winder if the target memory is unreadable
2920 to avoid having the prologue unwinder trying to read it. */
2921 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2927 struct frame_unwind arm_stub_unwind = {
2929 default_frame_unwind_stop_reason,
2931 arm_prologue_prev_register,
2933 arm_stub_unwind_sniffer
2937 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
2939 struct arm_prologue_cache *cache;
2941 if (*this_cache == NULL)
2942 *this_cache = arm_make_prologue_cache (this_frame);
2943 cache = *this_cache;
2945 return cache->prev_sp - cache->framesize;
2948 struct frame_base arm_normal_base = {
2949 &arm_prologue_unwind,
2950 arm_normal_frame_base,
2951 arm_normal_frame_base,
2952 arm_normal_frame_base
2955 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2956 dummy frame. The frame ID's base needs to match the TOS value
2957 saved by save_dummy_frame_tos() and returned from
2958 arm_push_dummy_call, and the PC needs to match the dummy frame's
2961 static struct frame_id
2962 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2964 return frame_id_build (get_frame_register_unsigned (this_frame,
2966 get_frame_pc (this_frame));
2969 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2970 be used to construct the previous frame's ID, after looking up the
2971 containing function). */
2974 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
2977 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
2978 return arm_addr_bits_remove (gdbarch, pc);
2982 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
2984 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
2987 static struct value *
2988 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
2991 struct gdbarch * gdbarch = get_frame_arch (this_frame);
2993 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2998 /* The PC is normally copied from the return column, which
2999 describes saves of LR. However, that version may have an
3000 extra bit set to indicate Thumb state. The bit is not
3002 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3003 return frame_unwind_got_constant (this_frame, regnum,
3004 arm_addr_bits_remove (gdbarch, lr));
3007 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3008 cpsr = get_frame_register_unsigned (this_frame, regnum);
3009 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3010 if (IS_THUMB_ADDR (lr))
3014 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3017 internal_error (__FILE__, __LINE__,
3018 _("Unexpected register %d"), regnum);
3023 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3024 struct dwarf2_frame_state_reg *reg,
3025 struct frame_info *this_frame)
3031 reg->how = DWARF2_FRAME_REG_FN;
3032 reg->loc.fn = arm_dwarf2_prev_register;
3035 reg->how = DWARF2_FRAME_REG_CFA;
3040 /* Return true if we are in the function's epilogue, i.e. after the
3041 instruction that destroyed the function's stack frame. */
3044 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3046 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3047 unsigned int insn, insn2;
3048 int found_return = 0, found_stack_adjust = 0;
3049 CORE_ADDR func_start, func_end;
3053 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3056 /* The epilogue is a sequence of instructions along the following lines:
3058 - add stack frame size to SP or FP
3059 - [if frame pointer used] restore SP from FP
3060 - restore registers from SP [may include PC]
3061 - a return-type instruction [if PC wasn't already restored]
3063 In a first pass, we scan forward from the current PC and verify the
3064 instructions we find as compatible with this sequence, ending in a
3067 However, this is not sufficient to distinguish indirect function calls
3068 within a function from indirect tail calls in the epilogue in some cases.
3069 Therefore, if we didn't already find any SP-changing instruction during
3070 forward scan, we add a backward scanning heuristic to ensure we actually
3071 are in the epilogue. */
3074 while (scan_pc < func_end && !found_return)
3076 if (target_read_memory (scan_pc, buf, 2))
3080 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3082 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3084 else if (insn == 0x46f7) /* mov pc, lr */
3086 else if (insn == 0x46bd) /* mov sp, r7 */
3087 found_stack_adjust = 1;
3088 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3089 found_stack_adjust = 1;
3090 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3092 found_stack_adjust = 1;
3093 if (insn & 0x0100) /* <registers> include PC. */
3096 else if ((insn & 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */
3098 if (target_read_memory (scan_pc, buf, 2))
3102 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3104 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3106 found_stack_adjust = 1;
3107 if (insn2 & 0x8000) /* <registers> include PC. */
3110 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3111 && (insn2 & 0x0fff) == 0x0b04)
3113 found_stack_adjust = 1;
3114 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3117 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3118 && (insn2 & 0x0e00) == 0x0a00)
3119 found_stack_adjust = 1;
3130 /* Since any instruction in the epilogue sequence, with the possible
3131 exception of return itself, updates the stack pointer, we need to
3132 scan backwards for at most one instruction. Try either a 16-bit or
3133 a 32-bit instruction. This is just a heuristic, so we do not worry
3134 too much about false positives. */
3136 if (!found_stack_adjust)
3138 if (pc - 4 < func_start)
3140 if (target_read_memory (pc - 4, buf, 4))
3143 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3144 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3146 if (insn2 == 0x46bd) /* mov sp, r7 */
3147 found_stack_adjust = 1;
3148 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3149 found_stack_adjust = 1;
3150 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3151 found_stack_adjust = 1;
3152 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3153 found_stack_adjust = 1;
3154 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3155 && (insn2 & 0x0fff) == 0x0b04)
3156 found_stack_adjust = 1;
3157 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3158 && (insn2 & 0x0e00) == 0x0a00)
3159 found_stack_adjust = 1;
3162 return found_stack_adjust;
3165 /* Return true if we are in the function's epilogue, i.e. after the
3166 instruction that destroyed the function's stack frame. */
3169 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3171 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3173 int found_return, found_stack_adjust;
3174 CORE_ADDR func_start, func_end;
3176 if (arm_pc_is_thumb (gdbarch, pc))
3177 return thumb_in_function_epilogue_p (gdbarch, pc);
3179 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3182 /* We are in the epilogue if the previous instruction was a stack
3183 adjustment and the next instruction is a possible return (bx, mov
3184 pc, or pop). We could have to scan backwards to find the stack
3185 adjustment, or forwards to find the return, but this is a decent
3186 approximation. First scan forwards. */
3189 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3190 if (bits (insn, 28, 31) != INST_NV)
3192 if ((insn & 0x0ffffff0) == 0x012fff10)
3195 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3198 else if ((insn & 0x0fff0000) == 0x08bd0000
3199 && (insn & 0x0000c000) != 0)
3200 /* POP (LDMIA), including PC or LR. */
3207 /* Scan backwards. This is just a heuristic, so do not worry about
3208 false positives from mode changes. */
3210 if (pc < func_start + 4)
3213 found_stack_adjust = 0;
3214 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3215 if (bits (insn, 28, 31) != INST_NV)
3217 if ((insn & 0x0df0f000) == 0x0080d000)
3218 /* ADD SP (register or immediate). */
3219 found_stack_adjust = 1;
3220 else if ((insn & 0x0df0f000) == 0x0040d000)
3221 /* SUB SP (register or immediate). */
3222 found_stack_adjust = 1;
3223 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3225 found_stack_adjust = 1;
3226 else if ((insn & 0x0fff0000) == 0x08bd0000)
3228 found_stack_adjust = 1;
3231 if (found_stack_adjust)
3238 /* When arguments must be pushed onto the stack, they go on in reverse
3239 order. The code below implements a FILO (stack) to do this. */
3244 struct stack_item *prev;
3248 static struct stack_item *
3249 push_stack_item (struct stack_item *prev, const void *contents, int len)
3251 struct stack_item *si;
3252 si = xmalloc (sizeof (struct stack_item));
3253 si->data = xmalloc (len);
3256 memcpy (si->data, contents, len);
3260 static struct stack_item *
3261 pop_stack_item (struct stack_item *si)
3263 struct stack_item *dead = si;
3271 /* Return the alignment (in bytes) of the given type. */
3274 arm_type_align (struct type *t)
3280 t = check_typedef (t);
3281 switch (TYPE_CODE (t))
3284 /* Should never happen. */
3285 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3289 case TYPE_CODE_ENUM:
3293 case TYPE_CODE_RANGE:
3294 case TYPE_CODE_BITSTRING:
3296 case TYPE_CODE_CHAR:
3297 case TYPE_CODE_BOOL:
3298 return TYPE_LENGTH (t);
3300 case TYPE_CODE_ARRAY:
3301 case TYPE_CODE_COMPLEX:
3302 /* TODO: What about vector types? */
3303 return arm_type_align (TYPE_TARGET_TYPE (t));
3305 case TYPE_CODE_STRUCT:
3306 case TYPE_CODE_UNION:
3308 for (n = 0; n < TYPE_NFIELDS (t); n++)
3310 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3318 /* Possible base types for a candidate for passing and returning in
3321 enum arm_vfp_cprc_base_type
3330 /* The length of one element of base type B. */
3333 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3337 case VFP_CPRC_SINGLE:
3339 case VFP_CPRC_DOUBLE:
3341 case VFP_CPRC_VEC64:
3343 case VFP_CPRC_VEC128:
3346 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3351 /* The character ('s', 'd' or 'q') for the type of VFP register used
3352 for passing base type B. */
3355 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3359 case VFP_CPRC_SINGLE:
3361 case VFP_CPRC_DOUBLE:
3363 case VFP_CPRC_VEC64:
3365 case VFP_CPRC_VEC128:
3368 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3373 /* Determine whether T may be part of a candidate for passing and
3374 returning in VFP registers, ignoring the limit on the total number
3375 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3376 classification of the first valid component found; if it is not
3377 VFP_CPRC_UNKNOWN, all components must have the same classification
3378 as *BASE_TYPE. If it is found that T contains a type not permitted
3379 for passing and returning in VFP registers, a type differently
3380 classified from *BASE_TYPE, or two types differently classified
3381 from each other, return -1, otherwise return the total number of
3382 base-type elements found (possibly 0 in an empty structure or
3383 array). Vectors and complex types are not currently supported,
3384 matching the generic AAPCS support. */
3387 arm_vfp_cprc_sub_candidate (struct type *t,
3388 enum arm_vfp_cprc_base_type *base_type)
3390 t = check_typedef (t);
3391 switch (TYPE_CODE (t))
3394 switch (TYPE_LENGTH (t))
3397 if (*base_type == VFP_CPRC_UNKNOWN)
3398 *base_type = VFP_CPRC_SINGLE;
3399 else if (*base_type != VFP_CPRC_SINGLE)
3404 if (*base_type == VFP_CPRC_UNKNOWN)
3405 *base_type = VFP_CPRC_DOUBLE;
3406 else if (*base_type != VFP_CPRC_DOUBLE)
3415 case TYPE_CODE_ARRAY:
3419 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3422 if (TYPE_LENGTH (t) == 0)
3424 gdb_assert (count == 0);
3427 else if (count == 0)
3429 unitlen = arm_vfp_cprc_unit_length (*base_type);
3430 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3431 return TYPE_LENGTH (t) / unitlen;
3435 case TYPE_CODE_STRUCT:
3440 for (i = 0; i < TYPE_NFIELDS (t); i++)
3442 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3444 if (sub_count == -1)
3448 if (TYPE_LENGTH (t) == 0)
3450 gdb_assert (count == 0);
3453 else if (count == 0)
3455 unitlen = arm_vfp_cprc_unit_length (*base_type);
3456 if (TYPE_LENGTH (t) != unitlen * count)
3461 case TYPE_CODE_UNION:
3466 for (i = 0; i < TYPE_NFIELDS (t); i++)
3468 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3470 if (sub_count == -1)
3472 count = (count > sub_count ? count : sub_count);
3474 if (TYPE_LENGTH (t) == 0)
3476 gdb_assert (count == 0);
3479 else if (count == 0)
3481 unitlen = arm_vfp_cprc_unit_length (*base_type);
3482 if (TYPE_LENGTH (t) != unitlen * count)
3494 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3495 if passed to or returned from a non-variadic function with the VFP
3496 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3497 *BASE_TYPE to the base type for T and *COUNT to the number of
3498 elements of that base type before returning. */
3501 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3504 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3505 int c = arm_vfp_cprc_sub_candidate (t, &b);
3506 if (c <= 0 || c > 4)
3513 /* Return 1 if the VFP ABI should be used for passing arguments to and
3514 returning values from a function of type FUNC_TYPE, 0
3518 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3520 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3521 /* Variadic functions always use the base ABI. Assume that functions
3522 without debug info are not variadic. */
3523 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3525 /* The VFP ABI is only supported as a variant of AAPCS. */
3526 if (tdep->arm_abi != ARM_ABI_AAPCS)
3528 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3531 /* We currently only support passing parameters in integer registers, which
3532 conforms with GCC's default model, and VFP argument passing following
3533 the VFP variant of AAPCS. Several other variants exist and
3534 we should probably support some of them based on the selected ABI. */
3537 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3538 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3539 struct value **args, CORE_ADDR sp, int struct_return,
3540 CORE_ADDR struct_addr)
3542 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3546 struct stack_item *si = NULL;
3549 unsigned vfp_regs_free = (1 << 16) - 1;
3551 /* Determine the type of this function and whether the VFP ABI
3553 ftype = check_typedef (value_type (function));
3554 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3555 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3556 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3558 /* Set the return address. For the ARM, the return breakpoint is
3559 always at BP_ADDR. */
3560 if (arm_pc_is_thumb (gdbarch, bp_addr))
3562 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3564 /* Walk through the list of args and determine how large a temporary
3565 stack is required. Need to take care here as structs may be
3566 passed on the stack, and we have to push them. */
3569 argreg = ARM_A1_REGNUM;
3572 /* The struct_return pointer occupies the first parameter
3573 passing register. */
3577 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3578 gdbarch_register_name (gdbarch, argreg),
3579 paddress (gdbarch, struct_addr));
3580 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3584 for (argnum = 0; argnum < nargs; argnum++)
3587 struct type *arg_type;
3588 struct type *target_type;
3589 enum type_code typecode;
3590 const bfd_byte *val;
3592 enum arm_vfp_cprc_base_type vfp_base_type;
3594 int may_use_core_reg = 1;
3596 arg_type = check_typedef (value_type (args[argnum]));
3597 len = TYPE_LENGTH (arg_type);
3598 target_type = TYPE_TARGET_TYPE (arg_type);
3599 typecode = TYPE_CODE (arg_type);
3600 val = value_contents (args[argnum]);
3602 align = arm_type_align (arg_type);
3603 /* Round alignment up to a whole number of words. */
3604 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3605 /* Different ABIs have different maximum alignments. */
3606 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3608 /* The APCS ABI only requires word alignment. */
3609 align = INT_REGISTER_SIZE;
3613 /* The AAPCS requires at most doubleword alignment. */
3614 if (align > INT_REGISTER_SIZE * 2)
3615 align = INT_REGISTER_SIZE * 2;
3619 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3627 /* Because this is a CPRC it cannot go in a core register or
3628 cause a core register to be skipped for alignment.
3629 Either it goes in VFP registers and the rest of this loop
3630 iteration is skipped for this argument, or it goes on the
3631 stack (and the stack alignment code is correct for this
3633 may_use_core_reg = 0;
3635 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3636 shift = unit_length / 4;
3637 mask = (1 << (shift * vfp_base_count)) - 1;
3638 for (regno = 0; regno < 16; regno += shift)
3639 if (((vfp_regs_free >> regno) & mask) == mask)
3648 vfp_regs_free &= ~(mask << regno);
3649 reg_scaled = regno / shift;
3650 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3651 for (i = 0; i < vfp_base_count; i++)
3655 if (reg_char == 'q')
3656 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3657 val + i * unit_length);
3660 sprintf (name_buf, "%c%d", reg_char, reg_scaled + i);
3661 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3663 regcache_cooked_write (regcache, regnum,
3664 val + i * unit_length);
3671 /* This CPRC could not go in VFP registers, so all VFP
3672 registers are now marked as used. */
3677 /* Push stack padding for dowubleword alignment. */
3678 if (nstack & (align - 1))
3680 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3681 nstack += INT_REGISTER_SIZE;
3684 /* Doubleword aligned quantities must go in even register pairs. */
3685 if (may_use_core_reg
3686 && argreg <= ARM_LAST_ARG_REGNUM
3687 && align > INT_REGISTER_SIZE
3691 /* If the argument is a pointer to a function, and it is a
3692 Thumb function, create a LOCAL copy of the value and set
3693 the THUMB bit in it. */
3694 if (TYPE_CODE_PTR == typecode
3695 && target_type != NULL
3696 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3698 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3699 if (arm_pc_is_thumb (gdbarch, regval))
3701 bfd_byte *copy = alloca (len);
3702 store_unsigned_integer (copy, len, byte_order,
3703 MAKE_THUMB_ADDR (regval));
3708 /* Copy the argument to general registers or the stack in
3709 register-sized pieces. Large arguments are split between
3710 registers and stack. */
3713 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3715 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3717 /* The argument is being passed in a general purpose
3720 = extract_unsigned_integer (val, partial_len, byte_order);
3721 if (byte_order == BFD_ENDIAN_BIG)
3722 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3724 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3726 gdbarch_register_name
3728 phex (regval, INT_REGISTER_SIZE));
3729 regcache_cooked_write_unsigned (regcache, argreg, regval);
3734 /* Push the arguments onto the stack. */
3736 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3738 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3739 nstack += INT_REGISTER_SIZE;
3746 /* If we have an odd number of words to push, then decrement the stack
3747 by one word now, so first stack argument will be dword aligned. */
3754 write_memory (sp, si->data, si->len);
3755 si = pop_stack_item (si);
3758 /* Finally, update teh SP register. */
3759 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3765 /* Always align the frame to an 8-byte boundary. This is required on
3766 some platforms and harmless on the rest. */
3769 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3771 /* Align the stack to eight bytes. */
3772 return sp & ~ (CORE_ADDR) 7;
3776 print_fpu_flags (int flags)
3778 if (flags & (1 << 0))
3779 fputs ("IVO ", stdout);
3780 if (flags & (1 << 1))
3781 fputs ("DVZ ", stdout);
3782 if (flags & (1 << 2))
3783 fputs ("OFL ", stdout);
3784 if (flags & (1 << 3))
3785 fputs ("UFL ", stdout);
3786 if (flags & (1 << 4))
3787 fputs ("INX ", stdout);
3791 /* Print interesting information about the floating point processor
3792 (if present) or emulator. */
3794 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3795 struct frame_info *frame, const char *args)
3797 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3800 type = (status >> 24) & 127;
3801 if (status & (1 << 31))
3802 printf (_("Hardware FPU type %d\n"), type);
3804 printf (_("Software FPU type %d\n"), type);
3805 /* i18n: [floating point unit] mask */
3806 fputs (_("mask: "), stdout);
3807 print_fpu_flags (status >> 16);
3808 /* i18n: [floating point unit] flags */
3809 fputs (_("flags: "), stdout);
3810 print_fpu_flags (status);
3813 /* Construct the ARM extended floating point type. */
3814 static struct type *
3815 arm_ext_type (struct gdbarch *gdbarch)
3817 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3819 if (!tdep->arm_ext_type)
3821 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3822 floatformats_arm_ext);
3824 return tdep->arm_ext_type;
3827 static struct type *
3828 arm_neon_double_type (struct gdbarch *gdbarch)
3830 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3832 if (tdep->neon_double_type == NULL)
3834 struct type *t, *elem;
3836 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3838 elem = builtin_type (gdbarch)->builtin_uint8;
3839 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3840 elem = builtin_type (gdbarch)->builtin_uint16;
3841 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3842 elem = builtin_type (gdbarch)->builtin_uint32;
3843 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3844 elem = builtin_type (gdbarch)->builtin_uint64;
3845 append_composite_type_field (t, "u64", elem);
3846 elem = builtin_type (gdbarch)->builtin_float;
3847 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3848 elem = builtin_type (gdbarch)->builtin_double;
3849 append_composite_type_field (t, "f64", elem);
3851 TYPE_VECTOR (t) = 1;
3852 TYPE_NAME (t) = "neon_d";
3853 tdep->neon_double_type = t;
3856 return tdep->neon_double_type;
3859 /* FIXME: The vector types are not correctly ordered on big-endian
3860 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3861 bits of d0 - regardless of what unit size is being held in d0. So
3862 the offset of the first uint8 in d0 is 7, but the offset of the
3863 first float is 4. This code works as-is for little-endian
3866 static struct type *
3867 arm_neon_quad_type (struct gdbarch *gdbarch)
3869 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3871 if (tdep->neon_quad_type == NULL)
3873 struct type *t, *elem;
3875 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3877 elem = builtin_type (gdbarch)->builtin_uint8;
3878 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3879 elem = builtin_type (gdbarch)->builtin_uint16;
3880 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3881 elem = builtin_type (gdbarch)->builtin_uint32;
3882 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3883 elem = builtin_type (gdbarch)->builtin_uint64;
3884 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
3885 elem = builtin_type (gdbarch)->builtin_float;
3886 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
3887 elem = builtin_type (gdbarch)->builtin_double;
3888 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
3890 TYPE_VECTOR (t) = 1;
3891 TYPE_NAME (t) = "neon_q";
3892 tdep->neon_quad_type = t;
3895 return tdep->neon_quad_type;
3898 /* Return the GDB type object for the "standard" data type of data in
3901 static struct type *
3902 arm_register_type (struct gdbarch *gdbarch, int regnum)
3904 int num_regs = gdbarch_num_regs (gdbarch);
3906 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
3907 && regnum >= num_regs && regnum < num_regs + 32)
3908 return builtin_type (gdbarch)->builtin_float;
3910 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
3911 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
3912 return arm_neon_quad_type (gdbarch);
3914 /* If the target description has register information, we are only
3915 in this function so that we can override the types of
3916 double-precision registers for NEON. */
3917 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
3919 struct type *t = tdesc_register_type (gdbarch, regnum);
3921 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
3922 && TYPE_CODE (t) == TYPE_CODE_FLT
3923 && gdbarch_tdep (gdbarch)->have_neon)
3924 return arm_neon_double_type (gdbarch);
3929 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
3931 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
3932 return builtin_type (gdbarch)->builtin_void;
3934 return arm_ext_type (gdbarch);
3936 else if (regnum == ARM_SP_REGNUM)
3937 return builtin_type (gdbarch)->builtin_data_ptr;
3938 else if (regnum == ARM_PC_REGNUM)
3939 return builtin_type (gdbarch)->builtin_func_ptr;
3940 else if (regnum >= ARRAY_SIZE (arm_register_names))
3941 /* These registers are only supported on targets which supply
3942 an XML description. */
3943 return builtin_type (gdbarch)->builtin_int0;
3945 return builtin_type (gdbarch)->builtin_uint32;
3948 /* Map a DWARF register REGNUM onto the appropriate GDB register
3952 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3954 /* Core integer regs. */
3955 if (reg >= 0 && reg <= 15)
3958 /* Legacy FPA encoding. These were once used in a way which
3959 overlapped with VFP register numbering, so their use is
3960 discouraged, but GDB doesn't support the ARM toolchain
3961 which used them for VFP. */
3962 if (reg >= 16 && reg <= 23)
3963 return ARM_F0_REGNUM + reg - 16;
3965 /* New assignments for the FPA registers. */
3966 if (reg >= 96 && reg <= 103)
3967 return ARM_F0_REGNUM + reg - 96;
3969 /* WMMX register assignments. */
3970 if (reg >= 104 && reg <= 111)
3971 return ARM_WCGR0_REGNUM + reg - 104;
3973 if (reg >= 112 && reg <= 127)
3974 return ARM_WR0_REGNUM + reg - 112;
3976 if (reg >= 192 && reg <= 199)
3977 return ARM_WC0_REGNUM + reg - 192;
3979 /* VFP v2 registers. A double precision value is actually
3980 in d1 rather than s2, but the ABI only defines numbering
3981 for the single precision registers. This will "just work"
3982 in GDB for little endian targets (we'll read eight bytes,
3983 starting in s0 and then progressing to s1), but will be
3984 reversed on big endian targets with VFP. This won't
3985 be a problem for the new Neon quad registers; you're supposed
3986 to use DW_OP_piece for those. */
3987 if (reg >= 64 && reg <= 95)
3991 sprintf (name_buf, "s%d", reg - 64);
3992 return user_reg_map_name_to_regnum (gdbarch, name_buf,
3996 /* VFP v3 / Neon registers. This range is also used for VFP v2
3997 registers, except that it now describes d0 instead of s0. */
3998 if (reg >= 256 && reg <= 287)
4002 sprintf (name_buf, "d%d", reg - 256);
4003 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4010 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4012 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4015 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4017 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4018 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4020 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4021 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4023 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4024 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4026 if (reg < NUM_GREGS)
4027 return SIM_ARM_R0_REGNUM + reg;
4030 if (reg < NUM_FREGS)
4031 return SIM_ARM_FP0_REGNUM + reg;
4034 if (reg < NUM_SREGS)
4035 return SIM_ARM_FPS_REGNUM + reg;
4038 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4041 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4042 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4043 It is thought that this is is the floating-point register format on
4044 little-endian systems. */
4047 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4048 void *dbl, int endianess)
4052 if (endianess == BFD_ENDIAN_BIG)
4053 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4055 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4057 floatformat_from_doublest (fmt, &d, dbl);
4061 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4066 floatformat_to_doublest (fmt, ptr, &d);
4067 if (endianess == BFD_ENDIAN_BIG)
4068 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4070 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4075 condition_true (unsigned long cond, unsigned long status_reg)
4077 if (cond == INST_AL || cond == INST_NV)
4083 return ((status_reg & FLAG_Z) != 0);
4085 return ((status_reg & FLAG_Z) == 0);
4087 return ((status_reg & FLAG_C) != 0);
4089 return ((status_reg & FLAG_C) == 0);
4091 return ((status_reg & FLAG_N) != 0);
4093 return ((status_reg & FLAG_N) == 0);
4095 return ((status_reg & FLAG_V) != 0);
4097 return ((status_reg & FLAG_V) == 0);
4099 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4101 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4103 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4105 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4107 return (((status_reg & FLAG_Z) == 0)
4108 && (((status_reg & FLAG_N) == 0)
4109 == ((status_reg & FLAG_V) == 0)));
4111 return (((status_reg & FLAG_Z) != 0)
4112 || (((status_reg & FLAG_N) == 0)
4113 != ((status_reg & FLAG_V) == 0)));
4118 static unsigned long
4119 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4120 unsigned long pc_val, unsigned long status_reg)
4122 unsigned long res, shift;
4123 int rm = bits (inst, 0, 3);
4124 unsigned long shifttype = bits (inst, 5, 6);
4128 int rs = bits (inst, 8, 11);
4129 shift = (rs == 15 ? pc_val + 8
4130 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4133 shift = bits (inst, 7, 11);
4135 res = (rm == ARM_PC_REGNUM
4136 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4137 : get_frame_register_unsigned (frame, rm));
4142 res = shift >= 32 ? 0 : res << shift;
4146 res = shift >= 32 ? 0 : res >> shift;
4152 res = ((res & 0x80000000L)
4153 ? ~((~res) >> shift) : res >> shift);
4156 case 3: /* ROR/RRX */
4159 res = (res >> 1) | (carry ? 0x80000000L : 0);
4161 res = (res >> shift) | (res << (32 - shift));
4165 return res & 0xffffffff;
4168 /* Return number of 1-bits in VAL. */
4171 bitcount (unsigned long val)
4174 for (nbits = 0; val != 0; nbits++)
4175 val &= val - 1; /* Delete rightmost 1-bit in val. */
4179 /* Return the size in bytes of the complete Thumb instruction whose
4180 first halfword is INST1. */
4183 thumb_insn_size (unsigned short inst1)
4185 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4192 thumb_advance_itstate (unsigned int itstate)
4194 /* Preserve IT[7:5], the first three bits of the condition. Shift
4195 the upcoming condition flags left by one bit. */
4196 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4198 /* If we have finished the IT block, clear the state. */
4199 if ((itstate & 0x0f) == 0)
4205 /* Find the next PC after the current instruction executes. In some
4206 cases we can not statically determine the answer (see the IT state
4207 handling in this function); in that case, a breakpoint may be
4208 inserted in addition to the returned PC, which will be used to set
4209 another breakpoint by our caller. */
4212 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4214 struct gdbarch *gdbarch = get_frame_arch (frame);
4215 struct address_space *aspace = get_frame_address_space (frame);
4216 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4217 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4218 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4219 unsigned short inst1;
4220 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4221 unsigned long offset;
4222 ULONGEST status, itstate;
4224 nextpc = MAKE_THUMB_ADDR (nextpc);
4225 pc_val = MAKE_THUMB_ADDR (pc_val);
4227 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4229 /* Thumb-2 conditional execution support. There are eight bits in
4230 the CPSR which describe conditional execution state. Once
4231 reconstructed (they're in a funny order), the low five bits
4232 describe the low bit of the condition for each instruction and
4233 how many instructions remain. The high three bits describe the
4234 base condition. One of the low four bits will be set if an IT
4235 block is active. These bits read as zero on earlier
4237 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4238 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4240 /* If-Then handling. On GNU/Linux, where this routine is used, we
4241 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4242 can disable execution of the undefined instruction. So we might
4243 miss the breakpoint if we set it on a skipped conditional
4244 instruction. Because conditional instructions can change the
4245 flags, affecting the execution of further instructions, we may
4246 need to set two breakpoints. */
4248 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4250 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4252 /* An IT instruction. Because this instruction does not
4253 modify the flags, we can accurately predict the next
4254 executed instruction. */
4255 itstate = inst1 & 0x00ff;
4256 pc += thumb_insn_size (inst1);
4258 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4260 inst1 = read_memory_unsigned_integer (pc, 2,
4261 byte_order_for_code);
4262 pc += thumb_insn_size (inst1);
4263 itstate = thumb_advance_itstate (itstate);
4266 return MAKE_THUMB_ADDR (pc);
4268 else if (itstate != 0)
4270 /* We are in a conditional block. Check the condition. */
4271 if (! condition_true (itstate >> 4, status))
4273 /* Advance to the next executed instruction. */
4274 pc += thumb_insn_size (inst1);
4275 itstate = thumb_advance_itstate (itstate);
4277 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4279 inst1 = read_memory_unsigned_integer (pc, 2,
4280 byte_order_for_code);
4281 pc += thumb_insn_size (inst1);
4282 itstate = thumb_advance_itstate (itstate);
4285 return MAKE_THUMB_ADDR (pc);
4287 else if ((itstate & 0x0f) == 0x08)
4289 /* This is the last instruction of the conditional
4290 block, and it is executed. We can handle it normally
4291 because the following instruction is not conditional,
4292 and we must handle it normally because it is
4293 permitted to branch. Fall through. */
4299 /* There are conditional instructions after this one.
4300 If this instruction modifies the flags, then we can
4301 not predict what the next executed instruction will
4302 be. Fortunately, this instruction is architecturally
4303 forbidden to branch; we know it will fall through.
4304 Start by skipping past it. */
4305 pc += thumb_insn_size (inst1);
4306 itstate = thumb_advance_itstate (itstate);
4308 /* Set a breakpoint on the following instruction. */
4309 gdb_assert ((itstate & 0x0f) != 0);
4310 arm_insert_single_step_breakpoint (gdbarch, aspace,
4311 MAKE_THUMB_ADDR (pc));
4312 cond_negated = (itstate >> 4) & 1;
4314 /* Skip all following instructions with the same
4315 condition. If there is a later instruction in the IT
4316 block with the opposite condition, set the other
4317 breakpoint there. If not, then set a breakpoint on
4318 the instruction after the IT block. */
4321 inst1 = read_memory_unsigned_integer (pc, 2,
4322 byte_order_for_code);
4323 pc += thumb_insn_size (inst1);
4324 itstate = thumb_advance_itstate (itstate);
4326 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4328 return MAKE_THUMB_ADDR (pc);
4332 else if (itstate & 0x0f)
4334 /* We are in a conditional block. Check the condition. */
4335 int cond = itstate >> 4;
4337 if (! condition_true (cond, status))
4339 /* Advance to the next instruction. All the 32-bit
4340 instructions share a common prefix. */
4341 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4342 return MAKE_THUMB_ADDR (pc + 4);
4344 return MAKE_THUMB_ADDR (pc + 2);
4347 /* Otherwise, handle the instruction normally. */
4350 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4354 /* Fetch the saved PC from the stack. It's stored above
4355 all of the other registers. */
4356 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4357 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4358 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4360 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4362 unsigned long cond = bits (inst1, 8, 11);
4363 if (cond == 0x0f) /* 0x0f = SWI */
4365 struct gdbarch_tdep *tdep;
4366 tdep = gdbarch_tdep (gdbarch);
4368 if (tdep->syscall_next_pc != NULL)
4369 nextpc = tdep->syscall_next_pc (frame);
4372 else if (cond != 0x0f && condition_true (cond, status))
4373 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4375 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4377 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4379 else if ((inst1 & 0xe000) == 0xe000) /* 32-bit instruction */
4381 unsigned short inst2;
4382 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4384 /* Default to the next instruction. */
4386 nextpc = MAKE_THUMB_ADDR (nextpc);
4388 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4390 /* Branches and miscellaneous control instructions. */
4392 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4395 int j1, j2, imm1, imm2;
4397 imm1 = sbits (inst1, 0, 10);
4398 imm2 = bits (inst2, 0, 10);
4399 j1 = bit (inst2, 13);
4400 j2 = bit (inst2, 11);
4402 offset = ((imm1 << 12) + (imm2 << 1));
4403 offset ^= ((!j2) << 22) | ((!j1) << 23);
4405 nextpc = pc_val + offset;
4406 /* For BLX make sure to clear the low bits. */
4407 if (bit (inst2, 12) == 0)
4408 nextpc = nextpc & 0xfffffffc;
4410 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4412 /* SUBS PC, LR, #imm8. */
4413 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4414 nextpc -= inst2 & 0x00ff;
4416 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4418 /* Conditional branch. */
4419 if (condition_true (bits (inst1, 6, 9), status))
4421 int sign, j1, j2, imm1, imm2;
4423 sign = sbits (inst1, 10, 10);
4424 imm1 = bits (inst1, 0, 5);
4425 imm2 = bits (inst2, 0, 10);
4426 j1 = bit (inst2, 13);
4427 j2 = bit (inst2, 11);
4429 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4430 offset += (imm1 << 12) + (imm2 << 1);
4432 nextpc = pc_val + offset;
4436 else if ((inst1 & 0xfe50) == 0xe810)
4438 /* Load multiple or RFE. */
4439 int rn, offset, load_pc = 1;
4441 rn = bits (inst1, 0, 3);
4442 if (bit (inst1, 7) && !bit (inst1, 8))
4445 if (!bit (inst2, 15))
4447 offset = bitcount (inst2) * 4 - 4;
4449 else if (!bit (inst1, 7) && bit (inst1, 8))
4452 if (!bit (inst2, 15))
4456 else if (bit (inst1, 7) && bit (inst1, 8))
4461 else if (!bit (inst1, 7) && !bit (inst1, 8))
4471 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4472 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4475 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4477 /* MOV PC or MOVS PC. */
4478 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4479 nextpc = MAKE_THUMB_ADDR (nextpc);
4481 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4485 int rn, load_pc = 1;
4487 rn = bits (inst1, 0, 3);
4488 base = get_frame_register_unsigned (frame, rn);
4489 if (rn == ARM_PC_REGNUM)
4491 base = (base + 4) & ~(CORE_ADDR) 0x3;
4493 base += bits (inst2, 0, 11);
4495 base -= bits (inst2, 0, 11);
4497 else if (bit (inst1, 7))
4498 base += bits (inst2, 0, 11);
4499 else if (bit (inst2, 11))
4501 if (bit (inst2, 10))
4504 base += bits (inst2, 0, 7);
4506 base -= bits (inst2, 0, 7);
4509 else if ((inst2 & 0x0fc0) == 0x0000)
4511 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4512 base += get_frame_register_unsigned (frame, rm) << shift;
4519 nextpc = get_frame_memory_unsigned (frame, base, 4);
4521 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4524 CORE_ADDR tbl_reg, table, offset, length;
4526 tbl_reg = bits (inst1, 0, 3);
4527 if (tbl_reg == 0x0f)
4528 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4530 table = get_frame_register_unsigned (frame, tbl_reg);
4532 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4533 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4534 nextpc = pc_val + length;
4536 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4539 CORE_ADDR tbl_reg, table, offset, length;
4541 tbl_reg = bits (inst1, 0, 3);
4542 if (tbl_reg == 0x0f)
4543 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4545 table = get_frame_register_unsigned (frame, tbl_reg);
4547 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4548 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4549 nextpc = pc_val + length;
4552 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4554 if (bits (inst1, 3, 6) == 0x0f)
4557 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4559 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4561 if (bits (inst1, 3, 6) == 0x0f)
4564 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4566 nextpc = MAKE_THUMB_ADDR (nextpc);
4568 else if ((inst1 & 0xf500) == 0xb100)
4571 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4572 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4574 if (bit (inst1, 11) && reg != 0)
4575 nextpc = pc_val + imm;
4576 else if (!bit (inst1, 11) && reg == 0)
4577 nextpc = pc_val + imm;
4582 /* Get the raw next address. PC is the current program counter, in
4583 FRAME, which is assumed to be executing in ARM mode.
4585 The value returned has the execution state of the next instruction
4586 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4587 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4591 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4593 struct gdbarch *gdbarch = get_frame_arch (frame);
4594 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4595 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4596 unsigned long pc_val;
4597 unsigned long this_instr;
4598 unsigned long status;
4601 pc_val = (unsigned long) pc;
4602 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4604 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4605 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4607 if (bits (this_instr, 28, 31) == INST_NV)
4608 switch (bits (this_instr, 24, 27))
4613 /* Branch with Link and change to Thumb. */
4614 nextpc = BranchDest (pc, this_instr);
4615 nextpc |= bit (this_instr, 24) << 1;
4616 nextpc = MAKE_THUMB_ADDR (nextpc);
4622 /* Coprocessor register transfer. */
4623 if (bits (this_instr, 12, 15) == 15)
4624 error (_("Invalid update to pc in instruction"));
4627 else if (condition_true (bits (this_instr, 28, 31), status))
4629 switch (bits (this_instr, 24, 27))
4632 case 0x1: /* data processing */
4636 unsigned long operand1, operand2, result = 0;
4640 if (bits (this_instr, 12, 15) != 15)
4643 if (bits (this_instr, 22, 25) == 0
4644 && bits (this_instr, 4, 7) == 9) /* multiply */
4645 error (_("Invalid update to pc in instruction"));
4647 /* BX <reg>, BLX <reg> */
4648 if (bits (this_instr, 4, 27) == 0x12fff1
4649 || bits (this_instr, 4, 27) == 0x12fff3)
4651 rn = bits (this_instr, 0, 3);
4652 nextpc = ((rn == ARM_PC_REGNUM)
4654 : get_frame_register_unsigned (frame, rn));
4659 /* Multiply into PC. */
4660 c = (status & FLAG_C) ? 1 : 0;
4661 rn = bits (this_instr, 16, 19);
4662 operand1 = ((rn == ARM_PC_REGNUM)
4664 : get_frame_register_unsigned (frame, rn));
4666 if (bit (this_instr, 25))
4668 unsigned long immval = bits (this_instr, 0, 7);
4669 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4670 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4673 else /* operand 2 is a shifted register. */
4674 operand2 = shifted_reg_val (frame, this_instr, c,
4677 switch (bits (this_instr, 21, 24))
4680 result = operand1 & operand2;
4684 result = operand1 ^ operand2;
4688 result = operand1 - operand2;
4692 result = operand2 - operand1;
4696 result = operand1 + operand2;
4700 result = operand1 + operand2 + c;
4704 result = operand1 - operand2 + c;
4708 result = operand2 - operand1 + c;
4714 case 0xb: /* tst, teq, cmp, cmn */
4715 result = (unsigned long) nextpc;
4719 result = operand1 | operand2;
4723 /* Always step into a function. */
4728 result = operand1 & ~operand2;
4736 /* In 26-bit APCS the bottom two bits of the result are
4737 ignored, and we always end up in ARM state. */
4739 nextpc = arm_addr_bits_remove (gdbarch, result);
4747 case 0x5: /* data transfer */
4750 if (bit (this_instr, 20))
4753 if (bits (this_instr, 12, 15) == 15)
4759 if (bit (this_instr, 22))
4760 error (_("Invalid update to pc in instruction"));
4762 /* byte write to PC */
4763 rn = bits (this_instr, 16, 19);
4764 base = ((rn == ARM_PC_REGNUM)
4766 : get_frame_register_unsigned (frame, rn));
4768 if (bit (this_instr, 24))
4771 int c = (status & FLAG_C) ? 1 : 0;
4772 unsigned long offset =
4773 (bit (this_instr, 25)
4774 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4775 : bits (this_instr, 0, 11));
4777 if (bit (this_instr, 23))
4782 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
4789 case 0x9: /* block transfer */
4790 if (bit (this_instr, 20))
4793 if (bit (this_instr, 15))
4798 if (bit (this_instr, 23))
4801 unsigned long reglist = bits (this_instr, 0, 14);
4802 offset = bitcount (reglist) * 4;
4803 if (bit (this_instr, 24)) /* pre */
4806 else if (bit (this_instr, 24))
4810 unsigned long rn_val =
4811 get_frame_register_unsigned (frame,
4812 bits (this_instr, 16, 19));
4814 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
4822 case 0xb: /* branch & link */
4823 case 0xa: /* branch */
4825 nextpc = BranchDest (pc, this_instr);
4831 case 0xe: /* coproc ops */
4835 struct gdbarch_tdep *tdep;
4836 tdep = gdbarch_tdep (gdbarch);
4838 if (tdep->syscall_next_pc != NULL)
4839 nextpc = tdep->syscall_next_pc (frame);
4845 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4853 /* Determine next PC after current instruction executes. Will call either
4854 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4855 loop is detected. */
4858 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4862 if (arm_frame_is_thumb (frame))
4864 nextpc = thumb_get_next_pc_raw (frame, pc);
4865 if (nextpc == MAKE_THUMB_ADDR (pc))
4866 error (_("Infinite loop detected"));
4870 nextpc = arm_get_next_pc_raw (frame, pc);
4872 error (_("Infinite loop detected"));
4878 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4879 of the appropriate mode (as encoded in the PC value), even if this
4880 differs from what would be expected according to the symbol tables. */
4883 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
4884 struct address_space *aspace,
4887 struct cleanup *old_chain
4888 = make_cleanup_restore_integer (&arm_override_mode);
4890 arm_override_mode = IS_THUMB_ADDR (pc);
4891 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4893 insert_single_step_breakpoint (gdbarch, aspace, pc);
4895 do_cleanups (old_chain);
4898 /* single_step() is called just before we want to resume the inferior,
4899 if we want to single-step it but there is no hardware or kernel
4900 single-step support. We find the target of the coming instruction
4901 and breakpoint it. */
4904 arm_software_single_step (struct frame_info *frame)
4906 struct gdbarch *gdbarch = get_frame_arch (frame);
4907 struct address_space *aspace = get_frame_address_space (frame);
4908 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
4910 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
4915 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4916 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4917 NULL if an error occurs. BUF is freed. */
4920 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4921 int old_len, int new_len)
4923 gdb_byte *new_buf, *middle;
4924 int bytes_to_read = new_len - old_len;
4926 new_buf = xmalloc (new_len);
4927 memcpy (new_buf + bytes_to_read, buf, old_len);
4929 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4937 /* An IT block is at most the 2-byte IT instruction followed by
4938 four 4-byte instructions. The furthest back we must search to
4939 find an IT block that affects the current instruction is thus
4940 2 + 3 * 4 == 14 bytes. */
4941 #define MAX_IT_BLOCK_PREFIX 14
4943 /* Use a quick scan if there are more than this many bytes of
4945 #define IT_SCAN_THRESHOLD 32
4947 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4948 A breakpoint in an IT block may not be hit, depending on the
4951 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4955 CORE_ADDR boundary, func_start;
4956 int buf_len, buf2_len;
4957 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4958 int i, any, last_it, last_it_count;
4960 /* If we are using BKPT breakpoints, none of this is necessary. */
4961 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4964 /* ARM mode does not have this problem. */
4965 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4968 /* We are setting a breakpoint in Thumb code that could potentially
4969 contain an IT block. The first step is to find how much Thumb
4970 code there is; we do not need to read outside of known Thumb
4972 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4974 /* Thumb-2 code must have mapping symbols to have a chance. */
4977 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4979 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4980 && func_start > boundary)
4981 boundary = func_start;
4983 /* Search for a candidate IT instruction. We have to do some fancy
4984 footwork to distinguish a real IT instruction from the second
4985 half of a 32-bit instruction, but there is no need for that if
4986 there's no candidate. */
4987 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
4989 /* No room for an IT instruction. */
4992 buf = xmalloc (buf_len);
4993 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4996 for (i = 0; i < buf_len; i += 2)
4998 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4999 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5011 /* OK, the code bytes before this instruction contain at least one
5012 halfword which resembles an IT instruction. We know that it's
5013 Thumb code, but there are still two possibilities. Either the
5014 halfword really is an IT instruction, or it is the second half of
5015 a 32-bit Thumb instruction. The only way we can tell is to
5016 scan forwards from a known instruction boundary. */
5017 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5021 /* There's a lot of code before this instruction. Start with an
5022 optimistic search; it's easy to recognize halfwords that can
5023 not be the start of a 32-bit instruction, and use that to
5024 lock on to the instruction boundaries. */
5025 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5028 buf_len = IT_SCAN_THRESHOLD;
5031 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5033 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5034 if (thumb_insn_size (inst1) == 2)
5041 /* At this point, if DEFINITE, BUF[I] is the first place we
5042 are sure that we know the instruction boundaries, and it is far
5043 enough from BPADDR that we could not miss an IT instruction
5044 affecting BPADDR. If ! DEFINITE, give up - start from a
5048 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5052 buf_len = bpaddr - boundary;
5058 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5061 buf_len = bpaddr - boundary;
5065 /* Scan forwards. Find the last IT instruction before BPADDR. */
5070 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5072 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5077 else if (inst1 & 0x0002)
5079 else if (inst1 & 0x0004)
5084 i += thumb_insn_size (inst1);
5090 /* There wasn't really an IT instruction after all. */
5093 if (last_it_count < 1)
5094 /* It was too far away. */
5097 /* This really is a trouble spot. Move the breakpoint to the IT
5099 return bpaddr - buf_len + last_it;
5102 /* ARM displaced stepping support.
5104 Generally ARM displaced stepping works as follows:
5106 1. When an instruction is to be single-stepped, it is first decoded by
5107 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5108 Depending on the type of instruction, it is then copied to a scratch
5109 location, possibly in a modified form. The copy_* set of functions
5110 performs such modification, as necessary. A breakpoint is placed after
5111 the modified instruction in the scratch space to return control to GDB.
5112 Note in particular that instructions which modify the PC will no longer
5113 do so after modification.
5115 2. The instruction is single-stepped, by setting the PC to the scratch
5116 location address, and resuming. Control returns to GDB when the
5119 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5120 function used for the current instruction. This function's job is to
5121 put the CPU/memory state back to what it would have been if the
5122 instruction had been executed unmodified in its original location. */
5124 /* NOP instruction (mov r0, r0). */
5125 #define ARM_NOP 0xe1a00000
5126 #define THUMB_NOP 0x4600
5128 /* Helper for register reads for displaced stepping. In particular, this
5129 returns the PC as it would be seen by the instruction at its original
5133 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5137 CORE_ADDR from = dsc->insn_addr;
5139 if (regno == ARM_PC_REGNUM)
5141 /* Compute pipeline offset:
5142 - When executing an ARM instruction, PC reads as the address of the
5143 current instruction plus 8.
5144 - When executing a Thumb instruction, PC reads as the address of the
5145 current instruction plus 4. */
5152 if (debug_displaced)
5153 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5154 (unsigned long) from);
5155 return (ULONGEST) from;
5159 regcache_cooked_read_unsigned (regs, regno, &ret);
5160 if (debug_displaced)
5161 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5162 regno, (unsigned long) ret);
5168 displaced_in_arm_mode (struct regcache *regs)
5171 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5173 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5175 return (ps & t_bit) == 0;
5178 /* Write to the PC as from a branch instruction. */
5181 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5185 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5186 architecture versions < 6. */
5187 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5188 val & ~(ULONGEST) 0x3);
5190 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5191 val & ~(ULONGEST) 0x1);
5194 /* Write to the PC as from a branch-exchange instruction. */
5197 bx_write_pc (struct regcache *regs, ULONGEST val)
5200 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5202 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5206 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5207 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5209 else if ((val & 2) == 0)
5211 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5212 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5216 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5217 mode, align dest to 4 bytes). */
5218 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5219 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5220 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5224 /* Write to the PC as if from a load instruction. */
5227 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5230 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5231 bx_write_pc (regs, val);
5233 branch_write_pc (regs, dsc, val);
5236 /* Write to the PC as if from an ALU instruction. */
5239 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5242 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5243 bx_write_pc (regs, val);
5245 branch_write_pc (regs, dsc, val);
5248 /* Helper for writing to registers for displaced stepping. Writing to the PC
5249 has a varying effects depending on the instruction which does the write:
5250 this is controlled by the WRITE_PC argument. */
5253 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5254 int regno, ULONGEST val, enum pc_write_style write_pc)
5256 if (regno == ARM_PC_REGNUM)
5258 if (debug_displaced)
5259 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5260 (unsigned long) val);
5263 case BRANCH_WRITE_PC:
5264 branch_write_pc (regs, dsc, val);
5268 bx_write_pc (regs, val);
5272 load_write_pc (regs, dsc, val);
5276 alu_write_pc (regs, dsc, val);
5279 case CANNOT_WRITE_PC:
5280 warning (_("Instruction wrote to PC in an unexpected way when "
5281 "single-stepping"));
5285 internal_error (__FILE__, __LINE__,
5286 _("Invalid argument to displaced_write_reg"));
5289 dsc->wrote_to_pc = 1;
5293 if (debug_displaced)
5294 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5295 regno, (unsigned long) val);
5296 regcache_cooked_write_unsigned (regs, regno, val);
5300 /* This function is used to concisely determine if an instruction INSN
5301 references PC. Register fields of interest in INSN should have the
5302 corresponding fields of BITMASK set to 0b1111. The function
5303 returns return 1 if any of these fields in INSN reference the PC
5304 (also 0b1111, r15), else it returns 0. */
5307 insn_references_pc (uint32_t insn, uint32_t bitmask)
5309 uint32_t lowbit = 1;
5311 while (bitmask != 0)
5315 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5321 mask = lowbit * 0xf;
5323 if ((insn & mask) == mask)
5332 /* The simplest copy function. Many instructions have the same effect no
5333 matter what address they are executed at: in those cases, use this. */
5336 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5337 const char *iname, struct displaced_step_closure *dsc)
5339 if (debug_displaced)
5340 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5341 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5344 dsc->modinsn[0] = insn;
5350 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5351 uint16_t insn2, const char *iname,
5352 struct displaced_step_closure *dsc)
5354 if (debug_displaced)
5355 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5356 "opcode/class '%s' unmodified\n", insn1, insn2,
5359 dsc->modinsn[0] = insn1;
5360 dsc->modinsn[1] = insn2;
5366 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5369 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5371 struct displaced_step_closure *dsc)
5373 if (debug_displaced)
5374 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5375 "opcode/class '%s' unmodified\n", insn,
5378 dsc->modinsn[0] = insn;
5383 /* Preload instructions with immediate offset. */
5386 cleanup_preload (struct gdbarch *gdbarch,
5387 struct regcache *regs, struct displaced_step_closure *dsc)
5389 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5390 if (!dsc->u.preload.immed)
5391 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5395 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5396 struct displaced_step_closure *dsc, unsigned int rn)
5399 /* Preload instructions:
5401 {pli/pld} [rn, #+/-imm]
5403 {pli/pld} [r0, #+/-imm]. */
5405 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5406 rn_val = displaced_read_reg (regs, dsc, rn);
5407 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5408 dsc->u.preload.immed = 1;
5410 dsc->cleanup = &cleanup_preload;
5414 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5415 struct displaced_step_closure *dsc)
5417 unsigned int rn = bits (insn, 16, 19);
5419 if (!insn_references_pc (insn, 0x000f0000ul))
5420 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5422 if (debug_displaced)
5423 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5424 (unsigned long) insn);
5426 dsc->modinsn[0] = insn & 0xfff0ffff;
5428 install_preload (gdbarch, regs, dsc, rn);
5434 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5435 struct regcache *regs, struct displaced_step_closure *dsc)
5437 unsigned int rn = bits (insn1, 0, 3);
5438 unsigned int u_bit = bit (insn1, 7);
5439 int imm12 = bits (insn2, 0, 11);
5442 if (rn != ARM_PC_REGNUM)
5443 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5445 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5446 PLD (literal) Encoding T1. */
5447 if (debug_displaced)
5448 fprintf_unfiltered (gdb_stdlog,
5449 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5450 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5456 /* Rewrite instruction {pli/pld} PC imm12 into:
5457 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5461 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5463 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5464 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5466 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5468 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5469 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5470 dsc->u.preload.immed = 0;
5472 /* {pli/pld} [r0, r1] */
5473 dsc->modinsn[0] = insn1 & 0xfff0;
5474 dsc->modinsn[1] = 0xf001;
5477 dsc->cleanup = &cleanup_preload;
5481 /* Preload instructions with register offset. */
5484 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5485 struct displaced_step_closure *dsc, unsigned int rn,
5488 ULONGEST rn_val, rm_val;
5490 /* Preload register-offset instructions:
5492 {pli/pld} [rn, rm {, shift}]
5494 {pli/pld} [r0, r1 {, shift}]. */
5496 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5497 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5498 rn_val = displaced_read_reg (regs, dsc, rn);
5499 rm_val = displaced_read_reg (regs, dsc, rm);
5500 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5501 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5502 dsc->u.preload.immed = 0;
5504 dsc->cleanup = &cleanup_preload;
5508 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5509 struct regcache *regs,
5510 struct displaced_step_closure *dsc)
5512 unsigned int rn = bits (insn, 16, 19);
5513 unsigned int rm = bits (insn, 0, 3);
5516 if (!insn_references_pc (insn, 0x000f000ful))
5517 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5519 if (debug_displaced)
5520 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5521 (unsigned long) insn);
5523 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5525 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5529 /* Copy/cleanup coprocessor load and store instructions. */
5532 cleanup_copro_load_store (struct gdbarch *gdbarch,
5533 struct regcache *regs,
5534 struct displaced_step_closure *dsc)
5536 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5538 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5540 if (dsc->u.ldst.writeback)
5541 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5545 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5546 struct displaced_step_closure *dsc,
5547 int writeback, unsigned int rn)
5551 /* Coprocessor load/store instructions:
5553 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5555 {stc/stc2} [r0, #+/-imm].
5557 ldc/ldc2 are handled identically. */
5559 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5560 rn_val = displaced_read_reg (regs, dsc, rn);
5561 /* PC should be 4-byte aligned. */
5562 rn_val = rn_val & 0xfffffffc;
5563 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5565 dsc->u.ldst.writeback = writeback;
5566 dsc->u.ldst.rn = rn;
5568 dsc->cleanup = &cleanup_copro_load_store;
5572 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5573 struct regcache *regs,
5574 struct displaced_step_closure *dsc)
5576 unsigned int rn = bits (insn, 16, 19);
5578 if (!insn_references_pc (insn, 0x000f0000ul))
5579 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5581 if (debug_displaced)
5582 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5583 "load/store insn %.8lx\n", (unsigned long) insn);
5585 dsc->modinsn[0] = insn & 0xfff0ffff;
5587 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5593 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5594 uint16_t insn2, struct regcache *regs,
5595 struct displaced_step_closure *dsc)
5597 unsigned int rn = bits (insn1, 0, 3);
5599 if (rn != ARM_PC_REGNUM)
5600 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5601 "copro load/store", dsc);
5603 if (debug_displaced)
5604 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5605 "load/store insn %.4x%.4x\n", insn1, insn2);
5607 dsc->modinsn[0] = insn1 & 0xfff0;
5608 dsc->modinsn[1] = insn2;
5611 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5612 doesn't support writeback, so pass 0. */
5613 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
5618 /* Clean up branch instructions (actually perform the branch, by setting
5622 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
5623 struct displaced_step_closure *dsc)
5625 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5626 int branch_taken = condition_true (dsc->u.branch.cond, status);
5627 enum pc_write_style write_pc = dsc->u.branch.exchange
5628 ? BX_WRITE_PC : BRANCH_WRITE_PC;
5633 if (dsc->u.branch.link)
5635 /* The value of LR should be the next insn of current one. In order
5636 not to confuse logic hanlding later insn `bx lr', if current insn mode
5637 is Thumb, the bit 0 of LR value should be set to 1. */
5638 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5641 next_insn_addr |= 0x1;
5643 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5647 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5650 /* Copy B/BL/BLX instructions with immediate destinations. */
5653 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
5654 struct displaced_step_closure *dsc,
5655 unsigned int cond, int exchange, int link, long offset)
5657 /* Implement "BL<cond> <label>" as:
5659 Preparation: cond <- instruction condition
5660 Insn: mov r0, r0 (nop)
5661 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5663 B<cond> similar, but don't set r14 in cleanup. */
5665 dsc->u.branch.cond = cond;
5666 dsc->u.branch.link = link;
5667 dsc->u.branch.exchange = exchange;
5669 dsc->u.branch.dest = dsc->insn_addr;
5670 if (link && exchange)
5671 /* For BLX, offset is computed from the Align (PC, 4). */
5672 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
5675 dsc->u.branch.dest += 4 + offset;
5677 dsc->u.branch.dest += 8 + offset;
5679 dsc->cleanup = &cleanup_branch;
5682 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
5683 struct regcache *regs, struct displaced_step_closure *dsc)
5685 unsigned int cond = bits (insn, 28, 31);
5686 int exchange = (cond == 0xf);
5687 int link = exchange || bit (insn, 24);
5690 if (debug_displaced)
5691 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
5692 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
5693 (unsigned long) insn);
5695 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5696 then arrange the switch into Thumb mode. */
5697 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
5699 offset = bits (insn, 0, 23) << 2;
5701 if (bit (offset, 25))
5702 offset = offset | ~0x3ffffff;
5704 dsc->modinsn[0] = ARM_NOP;
5706 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5711 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
5712 uint16_t insn2, struct regcache *regs,
5713 struct displaced_step_closure *dsc)
5715 int link = bit (insn2, 14);
5716 int exchange = link && !bit (insn2, 12);
5719 int j1 = bit (insn2, 13);
5720 int j2 = bit (insn2, 11);
5721 int s = sbits (insn1, 10, 10);
5722 int i1 = !(j1 ^ bit (insn1, 10));
5723 int i2 = !(j2 ^ bit (insn1, 10));
5725 if (!link && !exchange) /* B */
5727 offset = (bits (insn2, 0, 10) << 1);
5728 if (bit (insn2, 12)) /* Encoding T4 */
5730 offset |= (bits (insn1, 0, 9) << 12)
5736 else /* Encoding T3 */
5738 offset |= (bits (insn1, 0, 5) << 12)
5742 cond = bits (insn1, 6, 9);
5747 offset = (bits (insn1, 0, 9) << 12);
5748 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
5749 offset |= exchange ?
5750 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
5753 if (debug_displaced)
5754 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
5755 "%.4x %.4x with offset %.8lx\n",
5756 link ? (exchange) ? "blx" : "bl" : "b",
5757 insn1, insn2, offset);
5759 dsc->modinsn[0] = THUMB_NOP;
5761 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5765 /* Copy B Thumb instructions. */
5767 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
5768 struct displaced_step_closure *dsc)
5770 unsigned int cond = 0;
5772 unsigned short bit_12_15 = bits (insn, 12, 15);
5773 CORE_ADDR from = dsc->insn_addr;
5775 if (bit_12_15 == 0xd)
5777 /* offset = SignExtend (imm8:0, 32) */
5778 offset = sbits ((insn << 1), 0, 8);
5779 cond = bits (insn, 8, 11);
5781 else if (bit_12_15 == 0xe) /* Encoding T2 */
5783 offset = sbits ((insn << 1), 0, 11);
5787 if (debug_displaced)
5788 fprintf_unfiltered (gdb_stdlog,
5789 "displaced: copying b immediate insn %.4x "
5790 "with offset %d\n", insn, offset);
5792 dsc->u.branch.cond = cond;
5793 dsc->u.branch.link = 0;
5794 dsc->u.branch.exchange = 0;
5795 dsc->u.branch.dest = from + 4 + offset;
5797 dsc->modinsn[0] = THUMB_NOP;
5799 dsc->cleanup = &cleanup_branch;
5804 /* Copy BX/BLX with register-specified destinations. */
5807 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5808 struct displaced_step_closure *dsc, int link,
5809 unsigned int cond, unsigned int rm)
5811 /* Implement {BX,BLX}<cond> <reg>" as:
5813 Preparation: cond <- instruction condition
5814 Insn: mov r0, r0 (nop)
5815 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5817 Don't set r14 in cleanup for BX. */
5819 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5821 dsc->u.branch.cond = cond;
5822 dsc->u.branch.link = link;
5824 dsc->u.branch.exchange = 1;
5826 dsc->cleanup = &cleanup_branch;
5830 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5831 struct regcache *regs, struct displaced_step_closure *dsc)
5833 unsigned int cond = bits (insn, 28, 31);
5836 int link = bit (insn, 5);
5837 unsigned int rm = bits (insn, 0, 3);
5839 if (debug_displaced)
5840 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5841 (unsigned long) insn);
5843 dsc->modinsn[0] = ARM_NOP;
5845 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5850 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
5851 struct regcache *regs,
5852 struct displaced_step_closure *dsc)
5854 int link = bit (insn, 7);
5855 unsigned int rm = bits (insn, 3, 6);
5857 if (debug_displaced)
5858 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
5859 (unsigned short) insn);
5861 dsc->modinsn[0] = THUMB_NOP;
5863 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
5869 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5872 cleanup_alu_imm (struct gdbarch *gdbarch,
5873 struct regcache *regs, struct displaced_step_closure *dsc)
5875 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5876 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5877 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5878 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5882 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5883 struct displaced_step_closure *dsc)
5885 unsigned int rn = bits (insn, 16, 19);
5886 unsigned int rd = bits (insn, 12, 15);
5887 unsigned int op = bits (insn, 21, 24);
5888 int is_mov = (op == 0xd);
5889 ULONGEST rd_val, rn_val;
5891 if (!insn_references_pc (insn, 0x000ff000ul))
5892 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5894 if (debug_displaced)
5895 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5896 "%.8lx\n", is_mov ? "move" : "ALU",
5897 (unsigned long) insn);
5899 /* Instruction is of form:
5901 <op><cond> rd, [rn,] #imm
5905 Preparation: tmp1, tmp2 <- r0, r1;
5907 Insn: <op><cond> r0, r1, #imm
5908 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5911 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5912 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5913 rn_val = displaced_read_reg (regs, dsc, rn);
5914 rd_val = displaced_read_reg (regs, dsc, rd);
5915 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5916 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5920 dsc->modinsn[0] = insn & 0xfff00fff;
5922 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5924 dsc->cleanup = &cleanup_alu_imm;
5930 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
5931 uint16_t insn2, struct regcache *regs,
5932 struct displaced_step_closure *dsc)
5934 unsigned int op = bits (insn1, 5, 8);
5935 unsigned int rn, rm, rd;
5936 ULONGEST rd_val, rn_val;
5938 rn = bits (insn1, 0, 3); /* Rn */
5939 rm = bits (insn2, 0, 3); /* Rm */
5940 rd = bits (insn2, 8, 11); /* Rd */
5942 /* This routine is only called for instruction MOV. */
5943 gdb_assert (op == 0x2 && rn == 0xf);
5945 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
5946 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
5948 if (debug_displaced)
5949 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
5950 "ALU", insn1, insn2);
5952 /* Instruction is of form:
5954 <op><cond> rd, [rn,] #imm
5958 Preparation: tmp1, tmp2 <- r0, r1;
5960 Insn: <op><cond> r0, r1, #imm
5961 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5964 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5965 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5966 rn_val = displaced_read_reg (regs, dsc, rn);
5967 rd_val = displaced_read_reg (regs, dsc, rd);
5968 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5969 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5972 dsc->modinsn[0] = insn1;
5973 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
5976 dsc->cleanup = &cleanup_alu_imm;
5981 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5984 cleanup_alu_reg (struct gdbarch *gdbarch,
5985 struct regcache *regs, struct displaced_step_closure *dsc)
5990 rd_val = displaced_read_reg (regs, dsc, 0);
5992 for (i = 0; i < 3; i++)
5993 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5995 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5999 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6000 struct displaced_step_closure *dsc,
6001 unsigned int rd, unsigned int rn, unsigned int rm)
6003 ULONGEST rd_val, rn_val, rm_val;
6005 /* Instruction is of form:
6007 <op><cond> rd, [rn,] rm [, <shift>]
6011 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6012 r0, r1, r2 <- rd, rn, rm
6013 Insn: <op><cond> r0, r1, r2 [, <shift>]
6014 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6017 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6018 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6019 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6020 rd_val = displaced_read_reg (regs, dsc, rd);
6021 rn_val = displaced_read_reg (regs, dsc, rn);
6022 rm_val = displaced_read_reg (regs, dsc, rm);
6023 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6024 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6025 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6028 dsc->cleanup = &cleanup_alu_reg;
6032 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6033 struct displaced_step_closure *dsc)
6035 unsigned int op = bits (insn, 21, 24);
6036 int is_mov = (op == 0xd);
6038 if (!insn_references_pc (insn, 0x000ff00ful))
6039 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6041 if (debug_displaced)
6042 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6043 is_mov ? "move" : "ALU", (unsigned long) insn);
6046 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6048 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6050 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6056 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6057 struct regcache *regs,
6058 struct displaced_step_closure *dsc)
6060 unsigned rn, rm, rd;
6062 rd = bits (insn, 3, 6);
6063 rn = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6066 if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6067 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6069 if (debug_displaced)
6070 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n",
6071 "ALU", (unsigned short) insn);
6073 dsc->modinsn[0] = ((insn & 0xff00) | 0x08);
6075 install_alu_reg (gdbarch, regs, dsc, rd, rn, rm);
6080 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6083 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6084 struct regcache *regs,
6085 struct displaced_step_closure *dsc)
6087 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6090 for (i = 0; i < 4; i++)
6091 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6093 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6097 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6098 struct displaced_step_closure *dsc,
6099 unsigned int rd, unsigned int rn, unsigned int rm,
6103 ULONGEST rd_val, rn_val, rm_val, rs_val;
6105 /* Instruction is of form:
6107 <op><cond> rd, [rn,] rm, <shift> rs
6111 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6112 r0, r1, r2, r3 <- rd, rn, rm, rs
6113 Insn: <op><cond> r0, r1, r2, <shift> r3
6115 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6119 for (i = 0; i < 4; i++)
6120 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6122 rd_val = displaced_read_reg (regs, dsc, rd);
6123 rn_val = displaced_read_reg (regs, dsc, rn);
6124 rm_val = displaced_read_reg (regs, dsc, rm);
6125 rs_val = displaced_read_reg (regs, dsc, rs);
6126 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6127 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6128 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6129 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6131 dsc->cleanup = &cleanup_alu_shifted_reg;
6135 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6136 struct regcache *regs,
6137 struct displaced_step_closure *dsc)
6139 unsigned int op = bits (insn, 21, 24);
6140 int is_mov = (op == 0xd);
6141 unsigned int rd, rn, rm, rs;
6143 if (!insn_references_pc (insn, 0x000fff0ful))
6144 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6146 if (debug_displaced)
6147 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6148 "%.8lx\n", is_mov ? "move" : "ALU",
6149 (unsigned long) insn);
6151 rn = bits (insn, 16, 19);
6152 rm = bits (insn, 0, 3);
6153 rs = bits (insn, 8, 11);
6154 rd = bits (insn, 12, 15);
6157 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6159 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6161 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6166 /* Clean up load instructions. */
6169 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6170 struct displaced_step_closure *dsc)
6172 ULONGEST rt_val, rt_val2 = 0, rn_val;
6174 rt_val = displaced_read_reg (regs, dsc, 0);
6175 if (dsc->u.ldst.xfersize == 8)
6176 rt_val2 = displaced_read_reg (regs, dsc, 1);
6177 rn_val = displaced_read_reg (regs, dsc, 2);
6179 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6180 if (dsc->u.ldst.xfersize > 4)
6181 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6182 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6183 if (!dsc->u.ldst.immed)
6184 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6186 /* Handle register writeback. */
6187 if (dsc->u.ldst.writeback)
6188 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6189 /* Put result in right place. */
6190 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6191 if (dsc->u.ldst.xfersize == 8)
6192 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6195 /* Clean up store instructions. */
6198 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6199 struct displaced_step_closure *dsc)
6201 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6203 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6204 if (dsc->u.ldst.xfersize > 4)
6205 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6206 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6207 if (!dsc->u.ldst.immed)
6208 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6209 if (!dsc->u.ldst.restore_r4)
6210 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6213 if (dsc->u.ldst.writeback)
6214 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6217 /* Copy "extra" load/store instructions. These are halfword/doubleword
6218 transfers, which have a different encoding to byte/word transfers. */
6221 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6222 struct regcache *regs, struct displaced_step_closure *dsc)
6224 unsigned int op1 = bits (insn, 20, 24);
6225 unsigned int op2 = bits (insn, 5, 6);
6226 unsigned int rt = bits (insn, 12, 15);
6227 unsigned int rn = bits (insn, 16, 19);
6228 unsigned int rm = bits (insn, 0, 3);
6229 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6230 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6231 int immed = (op1 & 0x4) != 0;
6233 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6235 if (!insn_references_pc (insn, 0x000ff00ful))
6236 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6238 if (debug_displaced)
6239 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6240 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6241 (unsigned long) insn);
6243 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6246 internal_error (__FILE__, __LINE__,
6247 _("copy_extra_ld_st: instruction decode error"));
6249 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6250 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6251 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6253 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6255 rt_val = displaced_read_reg (regs, dsc, rt);
6256 if (bytesize[opcode] == 8)
6257 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6258 rn_val = displaced_read_reg (regs, dsc, rn);
6260 rm_val = displaced_read_reg (regs, dsc, rm);
6262 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6263 if (bytesize[opcode] == 8)
6264 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6265 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6267 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6270 dsc->u.ldst.xfersize = bytesize[opcode];
6271 dsc->u.ldst.rn = rn;
6272 dsc->u.ldst.immed = immed;
6273 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6274 dsc->u.ldst.restore_r4 = 0;
6277 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6279 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6280 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6282 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6284 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6285 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6287 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6292 /* Copy byte/half word/word loads and stores. */
6295 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6296 struct displaced_step_closure *dsc, int load,
6297 int immed, int writeback, int size, int usermode,
6298 int rt, int rm, int rn)
6300 ULONGEST rt_val, rn_val, rm_val = 0;
6302 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6303 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6305 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6307 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6309 rt_val = displaced_read_reg (regs, dsc, rt);
6310 rn_val = displaced_read_reg (regs, dsc, rn);
6312 rm_val = displaced_read_reg (regs, dsc, rm);
6314 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6315 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6317 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6319 dsc->u.ldst.xfersize = size;
6320 dsc->u.ldst.rn = rn;
6321 dsc->u.ldst.immed = immed;
6322 dsc->u.ldst.writeback = writeback;
6324 /* To write PC we can do:
6326 Before this sequence of instructions:
6327 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6328 r2 is the Rn value got from dispalced_read_reg.
6330 Insn1: push {pc} Write address of STR instruction + offset on stack
6331 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6332 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6333 = addr(Insn1) + offset - addr(Insn3) - 8
6335 Insn4: add r4, r4, #8 r4 = offset - 8
6336 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6338 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6340 Otherwise we don't know what value to write for PC, since the offset is
6341 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6342 of this can be found in Section "Saving from r15" in
6343 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6345 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6350 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6351 uint16_t insn2, struct regcache *regs,
6352 struct displaced_step_closure *dsc, int size)
6354 unsigned int u_bit = bit (insn1, 7);
6355 unsigned int rt = bits (insn2, 12, 15);
6356 int imm12 = bits (insn2, 0, 11);
6359 if (debug_displaced)
6360 fprintf_unfiltered (gdb_stdlog,
6361 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6362 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6368 /* Rewrite instruction LDR Rt imm12 into:
6370 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6374 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6377 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6378 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6379 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6381 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6383 pc_val = pc_val & 0xfffffffc;
6385 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6386 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6390 dsc->u.ldst.xfersize = size;
6391 dsc->u.ldst.immed = 0;
6392 dsc->u.ldst.writeback = 0;
6393 dsc->u.ldst.restore_r4 = 0;
6395 /* LDR R0, R2, R3 */
6396 dsc->modinsn[0] = 0xf852;
6397 dsc->modinsn[1] = 0x3;
6400 dsc->cleanup = &cleanup_load;
6406 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6407 uint16_t insn2, struct regcache *regs,
6408 struct displaced_step_closure *dsc,
6409 int writeback, int immed)
6411 unsigned int rt = bits (insn2, 12, 15);
6412 unsigned int rn = bits (insn1, 0, 3);
6413 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6414 /* In LDR (register), there is also a register Rm, which is not allowed to
6415 be PC, so we don't have to check it. */
6417 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6418 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6421 if (debug_displaced)
6422 fprintf_unfiltered (gdb_stdlog,
6423 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6424 rt, rn, insn1, insn2);
6426 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6429 dsc->u.ldst.restore_r4 = 0;
6432 /* ldr[b]<cond> rt, [rn, #imm], etc.
6434 ldr[b]<cond> r0, [r2, #imm]. */
6436 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6437 dsc->modinsn[1] = insn2 & 0x0fff;
6440 /* ldr[b]<cond> rt, [rn, rm], etc.
6442 ldr[b]<cond> r0, [r2, r3]. */
6444 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6445 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6455 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6456 struct regcache *regs,
6457 struct displaced_step_closure *dsc,
6458 int load, int size, int usermode)
6460 int immed = !bit (insn, 25);
6461 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6462 unsigned int rt = bits (insn, 12, 15);
6463 unsigned int rn = bits (insn, 16, 19);
6464 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6466 if (!insn_references_pc (insn, 0x000ff00ful))
6467 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6469 if (debug_displaced)
6470 fprintf_unfiltered (gdb_stdlog,
6471 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6472 load ? (size == 1 ? "ldrb" : "ldr")
6473 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6475 (unsigned long) insn);
6477 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6478 usermode, rt, rm, rn);
6480 if (load || rt != ARM_PC_REGNUM)
6482 dsc->u.ldst.restore_r4 = 0;
6485 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6487 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6488 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6490 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6492 {ldr,str}[b]<cond> r0, [r2, r3]. */
6493 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6497 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6498 dsc->u.ldst.restore_r4 = 1;
6499 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6500 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6501 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6502 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6503 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6507 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6509 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6514 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6519 /* Cleanup LDM instructions with fully-populated register list. This is an
6520 unfortunate corner case: it's impossible to implement correctly by modifying
6521 the instruction. The issue is as follows: we have an instruction,
6525 which we must rewrite to avoid loading PC. A possible solution would be to
6526 do the load in two halves, something like (with suitable cleanup
6530 ldm[id][ab] r8!, {r0-r7}
6532 ldm[id][ab] r8, {r7-r14}
6535 but at present there's no suitable place for <temp>, since the scratch space
6536 is overwritten before the cleanup routine is called. For now, we simply
6537 emulate the instruction. */
6540 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6541 struct displaced_step_closure *dsc)
6543 int inc = dsc->u.block.increment;
6544 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6545 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6546 uint32_t regmask = dsc->u.block.regmask;
6547 int regno = inc ? 0 : 15;
6548 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6549 int exception_return = dsc->u.block.load && dsc->u.block.user
6550 && (regmask & 0x8000) != 0;
6551 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6552 int do_transfer = condition_true (dsc->u.block.cond, status);
6553 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6558 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6559 sensible we can do here. Complain loudly. */
6560 if (exception_return)
6561 error (_("Cannot single-step exception return"));
6563 /* We don't handle any stores here for now. */
6564 gdb_assert (dsc->u.block.load != 0);
6566 if (debug_displaced)
6567 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6568 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6569 dsc->u.block.increment ? "inc" : "dec",
6570 dsc->u.block.before ? "before" : "after");
6577 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6580 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6583 xfer_addr += bump_before;
6585 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6586 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6588 xfer_addr += bump_after;
6590 regmask &= ~(1 << regno);
6593 if (dsc->u.block.writeback)
6594 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6598 /* Clean up an STM which included the PC in the register list. */
6601 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6602 struct displaced_step_closure *dsc)
6604 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6605 int store_executed = condition_true (dsc->u.block.cond, status);
6606 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
6607 CORE_ADDR stm_insn_addr;
6610 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6612 /* If condition code fails, there's nothing else to do. */
6613 if (!store_executed)
6616 if (dsc->u.block.increment)
6618 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6620 if (dsc->u.block.before)
6625 pc_stored_at = dsc->u.block.xfer_addr;
6627 if (dsc->u.block.before)
6631 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
6632 stm_insn_addr = dsc->scratch_base;
6633 offset = pc_val - stm_insn_addr;
6635 if (debug_displaced)
6636 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
6637 "STM instruction\n", offset);
6639 /* Rewrite the stored PC to the proper value for the non-displaced original
6641 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
6642 dsc->insn_addr + offset);
6645 /* Clean up an LDM which includes the PC in the register list. We clumped all
6646 the registers in the transferred list into a contiguous range r0...rX (to
6647 avoid loading PC directly and losing control of the debugged program), so we
6648 must undo that here. */
6651 cleanup_block_load_pc (struct gdbarch *gdbarch,
6652 struct regcache *regs,
6653 struct displaced_step_closure *dsc)
6655 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6656 int load_executed = condition_true (dsc->u.block.cond, status), i;
6657 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6658 unsigned int regs_loaded = bitcount (mask);
6659 unsigned int num_to_shuffle = regs_loaded, clobbered;
6661 /* The method employed here will fail if the register list is fully populated
6662 (we need to avoid loading PC directly). */
6663 gdb_assert (num_to_shuffle < 16);
6668 clobbered = (1 << num_to_shuffle) - 1;
6670 while (num_to_shuffle > 0)
6672 if ((mask & (1 << write_reg)) != 0)
6674 unsigned int read_reg = num_to_shuffle - 1;
6676 if (read_reg != write_reg)
6678 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6679 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
6680 if (debug_displaced)
6681 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
6682 "loaded register r%d to r%d\n"), read_reg,
6685 else if (debug_displaced)
6686 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
6687 "r%d already in the right place\n"),
6690 clobbered &= ~(1 << write_reg);
6698 /* Restore any registers we scribbled over. */
6699 for (write_reg = 0; clobbered != 0; write_reg++)
6701 if ((clobbered & (1 << write_reg)) != 0)
6703 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
6705 if (debug_displaced)
6706 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
6707 "clobbered register r%d\n"), write_reg);
6708 clobbered &= ~(1 << write_reg);
6712 /* Perform register writeback manually. */
6713 if (dsc->u.block.writeback)
6715 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
6717 if (dsc->u.block.increment)
6718 new_rn_val += regs_loaded * 4;
6720 new_rn_val -= regs_loaded * 4;
6722 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
6727 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6728 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6731 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
6732 struct regcache *regs,
6733 struct displaced_step_closure *dsc)
6735 int load = bit (insn, 20);
6736 int user = bit (insn, 22);
6737 int increment = bit (insn, 23);
6738 int before = bit (insn, 24);
6739 int writeback = bit (insn, 21);
6740 int rn = bits (insn, 16, 19);
6742 /* Block transfers which don't mention PC can be run directly
6744 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
6745 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
6747 if (rn == ARM_PC_REGNUM)
6749 warning (_("displaced: Unpredictable LDM or STM with "
6750 "base register r15"));
6751 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
6754 if (debug_displaced)
6755 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6756 "%.8lx\n", (unsigned long) insn);
6758 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6759 dsc->u.block.rn = rn;
6761 dsc->u.block.load = load;
6762 dsc->u.block.user = user;
6763 dsc->u.block.increment = increment;
6764 dsc->u.block.before = before;
6765 dsc->u.block.writeback = writeback;
6766 dsc->u.block.cond = bits (insn, 28, 31);
6768 dsc->u.block.regmask = insn & 0xffff;
6772 if ((insn & 0xffff) == 0xffff)
6774 /* LDM with a fully-populated register list. This case is
6775 particularly tricky. Implement for now by fully emulating the
6776 instruction (which might not behave perfectly in all cases, but
6777 these instructions should be rare enough for that not to matter
6779 dsc->modinsn[0] = ARM_NOP;
6781 dsc->cleanup = &cleanup_block_load_all;
6785 /* LDM of a list of registers which includes PC. Implement by
6786 rewriting the list of registers to be transferred into a
6787 contiguous chunk r0...rX before doing the transfer, then shuffling
6788 registers into the correct places in the cleanup routine. */
6789 unsigned int regmask = insn & 0xffff;
6790 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
6791 unsigned int to = 0, from = 0, i, new_rn;
6793 for (i = 0; i < num_in_list; i++)
6794 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6796 /* Writeback makes things complicated. We need to avoid clobbering
6797 the base register with one of the registers in our modified
6798 register list, but just using a different register can't work in
6801 ldm r14!, {r0-r13,pc}
6803 which would need to be rewritten as:
6807 but that can't work, because there's no free register for N.
6809 Solve this by turning off the writeback bit, and emulating
6810 writeback manually in the cleanup routine. */
6815 new_regmask = (1 << num_in_list) - 1;
6817 if (debug_displaced)
6818 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6819 "{..., pc}: original reg list %.4x, modified "
6820 "list %.4x\n"), rn, writeback ? "!" : "",
6821 (int) insn & 0xffff, new_regmask);
6823 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6825 dsc->cleanup = &cleanup_block_load_pc;
6830 /* STM of a list of registers which includes PC. Run the instruction
6831 as-is, but out of line: this will store the wrong value for the PC,
6832 so we must manually fix up the memory in the cleanup routine.
6833 Doing things this way has the advantage that we can auto-detect
6834 the offset of the PC write (which is architecture-dependent) in
6835 the cleanup routine. */
6836 dsc->modinsn[0] = insn;
6838 dsc->cleanup = &cleanup_block_store_pc;
6845 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6846 struct regcache *regs,
6847 struct displaced_step_closure *dsc)
6849 int rn = bits (insn1, 0, 3);
6850 int load = bit (insn1, 4);
6851 int writeback = bit (insn1, 5);
6853 /* Block transfers which don't mention PC can be run directly
6855 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
6856 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
6858 if (rn == ARM_PC_REGNUM)
6860 warning (_("displaced: Unpredictable LDM or STM with "
6861 "base register r15"));
6862 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6863 "unpredictable ldm/stm", dsc);
6866 if (debug_displaced)
6867 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6868 "%.4x%.4x\n", insn1, insn2);
6870 /* Clear bit 13, since it should be always zero. */
6871 dsc->u.block.regmask = (insn2 & 0xdfff);
6872 dsc->u.block.rn = rn;
6874 dsc->u.block.load = load;
6875 dsc->u.block.user = 0;
6876 dsc->u.block.increment = bit (insn1, 7);
6877 dsc->u.block.before = bit (insn1, 8);
6878 dsc->u.block.writeback = writeback;
6879 dsc->u.block.cond = INST_AL;
6880 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6884 if (dsc->u.block.regmask == 0xffff)
6886 /* This branch is impossible to happen. */
6891 unsigned int regmask = dsc->u.block.regmask;
6892 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
6893 unsigned int to = 0, from = 0, i, new_rn;
6895 for (i = 0; i < num_in_list; i++)
6896 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6901 new_regmask = (1 << num_in_list) - 1;
6903 if (debug_displaced)
6904 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6905 "{..., pc}: original reg list %.4x, modified "
6906 "list %.4x\n"), rn, writeback ? "!" : "",
6907 (int) dsc->u.block.regmask, new_regmask);
6909 dsc->modinsn[0] = insn1;
6910 dsc->modinsn[1] = (new_regmask & 0xffff);
6913 dsc->cleanup = &cleanup_block_load_pc;
6918 dsc->modinsn[0] = insn1;
6919 dsc->modinsn[1] = insn2;
6921 dsc->cleanup = &cleanup_block_store_pc;
6926 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6927 for Linux, where some SVC instructions must be treated specially. */
6930 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6931 struct displaced_step_closure *dsc)
6933 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6935 if (debug_displaced)
6936 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6937 "%.8lx\n", (unsigned long) resume_addr);
6939 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6943 /* Common copy routine for svc instruciton. */
6946 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
6947 struct displaced_step_closure *dsc)
6949 /* Preparation: none.
6950 Insn: unmodified svc.
6951 Cleanup: pc <- insn_addr + insn_size. */
6953 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6955 dsc->wrote_to_pc = 1;
6957 /* Allow OS-specific code to override SVC handling. */
6958 if (dsc->u.svc.copy_svc_os)
6959 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6962 dsc->cleanup = &cleanup_svc;
6968 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6969 struct regcache *regs, struct displaced_step_closure *dsc)
6972 if (debug_displaced)
6973 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6974 (unsigned long) insn);
6976 dsc->modinsn[0] = insn;
6978 return install_svc (gdbarch, regs, dsc);
6982 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
6983 struct regcache *regs, struct displaced_step_closure *dsc)
6986 if (debug_displaced)
6987 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
6990 dsc->modinsn[0] = insn;
6992 return install_svc (gdbarch, regs, dsc);
6995 /* Copy undefined instructions. */
6998 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6999 struct displaced_step_closure *dsc)
7001 if (debug_displaced)
7002 fprintf_unfiltered (gdb_stdlog,
7003 "displaced: copying undefined insn %.8lx\n",
7004 (unsigned long) insn);
7006 dsc->modinsn[0] = insn;
7012 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7013 struct displaced_step_closure *dsc)
7016 if (debug_displaced)
7017 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7018 "%.4x %.4x\n", (unsigned short) insn1,
7019 (unsigned short) insn2);
7021 dsc->modinsn[0] = insn1;
7022 dsc->modinsn[1] = insn2;
7028 /* Copy unpredictable instructions. */
7031 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7032 struct displaced_step_closure *dsc)
7034 if (debug_displaced)
7035 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7036 "%.8lx\n", (unsigned long) insn);
7038 dsc->modinsn[0] = insn;
7043 /* The decode_* functions are instruction decoding helpers. They mostly follow
7044 the presentation in the ARM ARM. */
7047 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7048 struct regcache *regs,
7049 struct displaced_step_closure *dsc)
7051 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7052 unsigned int rn = bits (insn, 16, 19);
7054 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7055 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7056 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7057 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7058 else if ((op1 & 0x60) == 0x20)
7059 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7060 else if ((op1 & 0x71) == 0x40)
7061 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7063 else if ((op1 & 0x77) == 0x41)
7064 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7065 else if ((op1 & 0x77) == 0x45)
7066 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7067 else if ((op1 & 0x77) == 0x51)
7070 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7072 return arm_copy_unpred (gdbarch, insn, dsc);
7074 else if ((op1 & 0x77) == 0x55)
7075 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7076 else if (op1 == 0x57)
7079 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7080 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7081 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7082 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7083 default: return arm_copy_unpred (gdbarch, insn, dsc);
7085 else if ((op1 & 0x63) == 0x43)
7086 return arm_copy_unpred (gdbarch, insn, dsc);
7087 else if ((op2 & 0x1) == 0x0)
7088 switch (op1 & ~0x80)
7091 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7093 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7094 case 0x71: case 0x75:
7096 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7097 case 0x63: case 0x67: case 0x73: case 0x77:
7098 return arm_copy_unpred (gdbarch, insn, dsc);
7100 return arm_copy_undef (gdbarch, insn, dsc);
7103 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7107 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7108 struct regcache *regs,
7109 struct displaced_step_closure *dsc)
7111 if (bit (insn, 27) == 0)
7112 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7113 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7114 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7117 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7120 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7122 case 0x4: case 0x5: case 0x6: case 0x7:
7123 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7126 switch ((insn & 0xe00000) >> 21)
7128 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7130 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7133 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7136 return arm_copy_undef (gdbarch, insn, dsc);
7141 int rn_f = (bits (insn, 16, 19) == 0xf);
7142 switch ((insn & 0xe00000) >> 21)
7145 /* ldc/ldc2 imm (undefined for rn == pc). */
7146 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7147 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7150 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7152 case 0x4: case 0x5: case 0x6: case 0x7:
7153 /* ldc/ldc2 lit (undefined for rn != pc). */
7154 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7155 : arm_copy_undef (gdbarch, insn, dsc);
7158 return arm_copy_undef (gdbarch, insn, dsc);
7163 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7166 if (bits (insn, 16, 19) == 0xf)
7168 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7170 return arm_copy_undef (gdbarch, insn, dsc);
7174 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7176 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7180 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7182 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7185 return arm_copy_undef (gdbarch, insn, dsc);
7189 /* Decode miscellaneous instructions in dp/misc encoding space. */
7192 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7193 struct regcache *regs,
7194 struct displaced_step_closure *dsc)
7196 unsigned int op2 = bits (insn, 4, 6);
7197 unsigned int op = bits (insn, 21, 22);
7198 unsigned int op1 = bits (insn, 16, 19);
7203 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7206 if (op == 0x1) /* bx. */
7207 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7209 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7211 return arm_copy_undef (gdbarch, insn, dsc);
7215 /* Not really supported. */
7216 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7218 return arm_copy_undef (gdbarch, insn, dsc);
7222 return arm_copy_bx_blx_reg (gdbarch, insn,
7223 regs, dsc); /* blx register. */
7225 return arm_copy_undef (gdbarch, insn, dsc);
7228 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7232 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7234 /* Not really supported. */
7235 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7238 return arm_copy_undef (gdbarch, insn, dsc);
7243 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7244 struct regcache *regs,
7245 struct displaced_step_closure *dsc)
7248 switch (bits (insn, 20, 24))
7251 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7254 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7256 case 0x12: case 0x16:
7257 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7260 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7264 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7266 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7267 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7268 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7269 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7270 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7271 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7272 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7273 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7274 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7275 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7276 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7277 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7278 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7279 /* 2nd arg means "unpriveleged". */
7280 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7284 /* Should be unreachable. */
7289 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7290 struct regcache *regs,
7291 struct displaced_step_closure *dsc)
7293 int a = bit (insn, 25), b = bit (insn, 4);
7294 uint32_t op1 = bits (insn, 20, 24);
7295 int rn_f = bits (insn, 16, 19) == 0xf;
7297 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7298 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7299 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7300 else if ((!a && (op1 & 0x17) == 0x02)
7301 || (a && (op1 & 0x17) == 0x02 && !b))
7302 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7303 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7304 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7305 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7306 else if ((!a && (op1 & 0x17) == 0x03)
7307 || (a && (op1 & 0x17) == 0x03 && !b))
7308 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7309 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7310 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7311 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7312 else if ((!a && (op1 & 0x17) == 0x06)
7313 || (a && (op1 & 0x17) == 0x06 && !b))
7314 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7315 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7316 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7317 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7318 else if ((!a && (op1 & 0x17) == 0x07)
7319 || (a && (op1 & 0x17) == 0x07 && !b))
7320 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7322 /* Should be unreachable. */
7327 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7328 struct displaced_step_closure *dsc)
7330 switch (bits (insn, 20, 24))
7332 case 0x00: case 0x01: case 0x02: case 0x03:
7333 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7335 case 0x04: case 0x05: case 0x06: case 0x07:
7336 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7338 case 0x08: case 0x09: case 0x0a: case 0x0b:
7339 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7340 return arm_copy_unmodified (gdbarch, insn,
7341 "decode/pack/unpack/saturate/reverse", dsc);
7344 if (bits (insn, 5, 7) == 0) /* op2. */
7346 if (bits (insn, 12, 15) == 0xf)
7347 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7349 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7352 return arm_copy_undef (gdbarch, insn, dsc);
7354 case 0x1a: case 0x1b:
7355 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7356 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7358 return arm_copy_undef (gdbarch, insn, dsc);
7360 case 0x1c: case 0x1d:
7361 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7363 if (bits (insn, 0, 3) == 0xf)
7364 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7366 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7369 return arm_copy_undef (gdbarch, insn, dsc);
7371 case 0x1e: case 0x1f:
7372 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7373 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7375 return arm_copy_undef (gdbarch, insn, dsc);
7378 /* Should be unreachable. */
7383 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7384 struct regcache *regs,
7385 struct displaced_step_closure *dsc)
7388 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7390 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7394 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7395 struct regcache *regs,
7396 struct displaced_step_closure *dsc)
7398 unsigned int opcode = bits (insn, 20, 24);
7402 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7403 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7405 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7406 case 0x12: case 0x16:
7407 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7409 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7410 case 0x13: case 0x17:
7411 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7413 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7414 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7415 /* Note: no writeback for these instructions. Bit 25 will always be
7416 zero though (via caller), so the following works OK. */
7417 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7420 /* Should be unreachable. */
7424 /* Decode shifted register instructions. */
7427 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7428 uint16_t insn2, struct regcache *regs,
7429 struct displaced_step_closure *dsc)
7431 /* PC is only allowed to be used in instruction MOV. */
7433 unsigned int op = bits (insn1, 5, 8);
7434 unsigned int rn = bits (insn1, 0, 3);
7436 if (op == 0x2 && rn == 0xf) /* MOV */
7437 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7439 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7440 "dp (shift reg)", dsc);
7444 /* Decode extension register load/store. Exactly the same as
7445 arm_decode_ext_reg_ld_st. */
7448 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7449 uint16_t insn2, struct regcache *regs,
7450 struct displaced_step_closure *dsc)
7452 unsigned int opcode = bits (insn1, 4, 8);
7456 case 0x04: case 0x05:
7457 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7458 "vfp/neon vmov", dsc);
7460 case 0x08: case 0x0c: /* 01x00 */
7461 case 0x0a: case 0x0e: /* 01x10 */
7462 case 0x12: case 0x16: /* 10x10 */
7463 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7464 "vfp/neon vstm/vpush", dsc);
7466 case 0x09: case 0x0d: /* 01x01 */
7467 case 0x0b: case 0x0f: /* 01x11 */
7468 case 0x13: case 0x17: /* 10x11 */
7469 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7470 "vfp/neon vldm/vpop", dsc);
7472 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7473 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7475 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7476 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7479 /* Should be unreachable. */
7484 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7485 struct regcache *regs, struct displaced_step_closure *dsc)
7487 unsigned int op1 = bits (insn, 20, 25);
7488 int op = bit (insn, 4);
7489 unsigned int coproc = bits (insn, 8, 11);
7490 unsigned int rn = bits (insn, 16, 19);
7492 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7493 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7494 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7495 && (coproc & 0xe) != 0xa)
7497 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7498 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7499 && (coproc & 0xe) != 0xa)
7500 /* ldc/ldc2 imm/lit. */
7501 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7502 else if ((op1 & 0x3e) == 0x00)
7503 return arm_copy_undef (gdbarch, insn, dsc);
7504 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7505 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7506 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7507 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7508 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7509 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7510 else if ((op1 & 0x30) == 0x20 && !op)
7512 if ((coproc & 0xe) == 0xa)
7513 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7515 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7517 else if ((op1 & 0x30) == 0x20 && op)
7518 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7519 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7520 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7521 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7522 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7523 else if ((op1 & 0x30) == 0x30)
7524 return arm_copy_svc (gdbarch, insn, regs, dsc);
7526 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7530 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7531 uint16_t insn2, struct regcache *regs,
7532 struct displaced_step_closure *dsc)
7534 unsigned int coproc = bits (insn2, 8, 11);
7535 unsigned int op1 = bits (insn1, 4, 9);
7536 unsigned int bit_5_8 = bits (insn1, 5, 8);
7537 unsigned int bit_9 = bit (insn1, 9);
7538 unsigned int bit_4 = bit (insn1, 4);
7539 unsigned int rn = bits (insn1, 0, 3);
7544 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7545 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7547 else if (bit_5_8 == 0) /* UNDEFINED. */
7548 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7551 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7552 if ((coproc & 0xe) == 0xa)
7553 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7555 else /* coproc is not 101x. */
7557 if (bit_4 == 0) /* STC/STC2. */
7558 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7560 else /* LDC/LDC2 {literal, immeidate}. */
7561 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7567 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7573 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7574 struct displaced_step_closure *dsc, int rd)
7580 Preparation: Rd <- PC
7586 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7587 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7591 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7592 struct displaced_step_closure *dsc,
7593 int rd, unsigned int imm)
7596 /* Encoding T2: ADDS Rd, #imm */
7597 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7599 install_pc_relative (gdbarch, regs, dsc, rd);
7605 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
7606 struct regcache *regs,
7607 struct displaced_step_closure *dsc)
7609 unsigned int rd = bits (insn, 8, 10);
7610 unsigned int imm8 = bits (insn, 0, 7);
7612 if (debug_displaced)
7613 fprintf_unfiltered (gdb_stdlog,
7614 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7617 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7621 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7622 uint16_t insn2, struct regcache *regs,
7623 struct displaced_step_closure *dsc)
7625 unsigned int rd = bits (insn2, 8, 11);
7626 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7627 extract raw immediate encoding rather than computing immediate. When
7628 generating ADD or SUB instruction, we can simply perform OR operation to
7629 set immediate into ADD. */
7630 unsigned int imm_3_8 = insn2 & 0x70ff;
7631 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7633 if (debug_displaced)
7634 fprintf_unfiltered (gdb_stdlog,
7635 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7636 rd, imm_i, imm_3_8, insn1, insn2);
7638 if (bit (insn1, 7)) /* Encoding T2 */
7640 /* Encoding T3: SUB Rd, Rd, #imm */
7641 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7642 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7644 else /* Encoding T3 */
7646 /* Encoding T3: ADD Rd, Rd, #imm */
7647 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7648 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7652 install_pc_relative (gdbarch, regs, dsc, rd);
7658 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
7659 struct regcache *regs,
7660 struct displaced_step_closure *dsc)
7662 unsigned int rt = bits (insn1, 8, 10);
7664 int imm8 = (bits (insn1, 0, 7) << 2);
7665 CORE_ADDR from = dsc->insn_addr;
7671 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7673 Insn: LDR R0, [R2, R3];
7674 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7676 if (debug_displaced)
7677 fprintf_unfiltered (gdb_stdlog,
7678 "displaced: copying thumb ldr r%d [pc #%d]\n"
7681 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
7682 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
7683 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
7684 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7685 /* The assembler calculates the required value of the offset from the
7686 Align(PC,4) value of this instruction to the label. */
7687 pc = pc & 0xfffffffc;
7689 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
7690 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
7693 dsc->u.ldst.xfersize = 4;
7695 dsc->u.ldst.immed = 0;
7696 dsc->u.ldst.writeback = 0;
7697 dsc->u.ldst.restore_r4 = 0;
7699 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7701 dsc->cleanup = &cleanup_load;
7706 /* Copy Thumb cbnz/cbz insruction. */
7709 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
7710 struct regcache *regs,
7711 struct displaced_step_closure *dsc)
7713 int non_zero = bit (insn1, 11);
7714 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
7715 CORE_ADDR from = dsc->insn_addr;
7716 int rn = bits (insn1, 0, 2);
7717 int rn_val = displaced_read_reg (regs, dsc, rn);
7719 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
7720 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7721 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7722 condition is false, let it be, cleanup_branch will do nothing. */
7723 if (dsc->u.branch.cond)
7725 dsc->u.branch.cond = INST_AL;
7726 dsc->u.branch.dest = from + 4 + imm5;
7729 dsc->u.branch.dest = from + 2;
7731 dsc->u.branch.link = 0;
7732 dsc->u.branch.exchange = 0;
7734 if (debug_displaced)
7735 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
7736 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
7737 rn, rn_val, insn1, dsc->u.branch.dest);
7739 dsc->modinsn[0] = THUMB_NOP;
7741 dsc->cleanup = &cleanup_branch;
7745 /* Copy Table Branch Byte/Halfword */
7747 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7748 uint16_t insn2, struct regcache *regs,
7749 struct displaced_step_closure *dsc)
7751 ULONGEST rn_val, rm_val;
7752 int is_tbh = bit (insn2, 4);
7753 CORE_ADDR halfwords = 0;
7754 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7756 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7757 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7763 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7764 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7770 target_read_memory (rn_val + rm_val, buf, 1);
7771 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7774 if (debug_displaced)
7775 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7776 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7777 (unsigned int) rn_val, (unsigned int) rm_val,
7778 (unsigned int) halfwords);
7780 dsc->u.branch.cond = INST_AL;
7781 dsc->u.branch.link = 0;
7782 dsc->u.branch.exchange = 0;
7783 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7785 dsc->cleanup = &cleanup_branch;
7791 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
7792 struct displaced_step_closure *dsc)
7795 int val = displaced_read_reg (regs, dsc, 7);
7796 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
7799 val = displaced_read_reg (regs, dsc, 8);
7800 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
7803 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
7808 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
7809 struct regcache *regs,
7810 struct displaced_step_closure *dsc)
7812 dsc->u.block.regmask = insn1 & 0x00ff;
7814 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7817 (1) register list is full, that is, r0-r7 are used.
7818 Prepare: tmp[0] <- r8
7820 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7821 MOV r8, r7; Move value of r7 to r8;
7822 POP {r7}; Store PC value into r7.
7824 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7826 (2) register list is not full, supposing there are N registers in
7827 register list (except PC, 0 <= N <= 7).
7828 Prepare: for each i, 0 - N, tmp[i] <- ri.
7830 POP {r0, r1, ...., rN};
7832 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7833 from tmp[] properly.
7835 if (debug_displaced)
7836 fprintf_unfiltered (gdb_stdlog,
7837 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7838 dsc->u.block.regmask, insn1);
7840 if (dsc->u.block.regmask == 0xff)
7842 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
7844 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
7845 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
7846 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
7849 dsc->cleanup = &cleanup_pop_pc_16bit_all;
7853 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
7854 unsigned int new_regmask, bit = 1;
7855 unsigned int to = 0, from = 0, i, new_rn;
7857 for (i = 0; i < num_in_list + 1; i++)
7858 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7860 new_regmask = (1 << (num_in_list + 1)) - 1;
7862 if (debug_displaced)
7863 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
7864 "{..., pc}: original reg list %.4x,"
7865 " modified list %.4x\n"),
7866 (int) dsc->u.block.regmask, new_regmask);
7868 dsc->u.block.regmask |= 0x8000;
7869 dsc->u.block.writeback = 0;
7870 dsc->u.block.cond = INST_AL;
7872 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
7874 dsc->cleanup = &cleanup_block_load_pc;
7881 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7882 struct regcache *regs,
7883 struct displaced_step_closure *dsc)
7885 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
7886 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
7889 /* 16-bit thumb instructions. */
7890 switch (op_bit_12_15)
7892 /* Shift (imme), add, subtract, move and compare. */
7893 case 0: case 1: case 2: case 3:
7894 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7895 "shift/add/sub/mov/cmp",
7899 switch (op_bit_10_11)
7901 case 0: /* Data-processing */
7902 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7906 case 1: /* Special data instructions and branch and exchange. */
7908 unsigned short op = bits (insn1, 7, 9);
7909 if (op == 6 || op == 7) /* BX or BLX */
7910 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
7911 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7912 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
7914 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
7918 default: /* LDR (literal) */
7919 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
7922 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7923 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
7926 if (op_bit_10_11 < 2) /* Generate PC-relative address */
7927 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
7928 else /* Generate SP-relative address */
7929 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
7931 case 11: /* Misc 16-bit instructions */
7933 switch (bits (insn1, 8, 11))
7935 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7936 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
7938 case 12: case 13: /* POP */
7939 if (bit (insn1, 8)) /* PC is in register list. */
7940 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
7942 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
7944 case 15: /* If-Then, and hints */
7945 if (bits (insn1, 0, 3))
7946 /* If-Then makes up to four following instructions conditional.
7947 IT instruction itself is not conditional, so handle it as a
7948 common unmodified instruction. */
7949 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
7952 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
7955 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
7960 if (op_bit_10_11 < 2) /* Store multiple registers */
7961 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
7962 else /* Load multiple registers */
7963 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
7965 case 13: /* Conditional branch and supervisor call */
7966 if (bits (insn1, 9, 11) != 7) /* conditional branch */
7967 err = thumb_copy_b (gdbarch, insn1, dsc);
7969 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
7971 case 14: /* Unconditional branch */
7972 err = thumb_copy_b (gdbarch, insn1, dsc);
7979 internal_error (__FILE__, __LINE__,
7980 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7984 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
7985 uint16_t insn1, uint16_t insn2,
7986 struct regcache *regs,
7987 struct displaced_step_closure *dsc)
7989 int rt = bits (insn2, 12, 15);
7990 int rn = bits (insn1, 0, 3);
7991 int op1 = bits (insn1, 7, 8);
7994 switch (bits (insn1, 5, 6))
7996 case 0: /* Load byte and memory hints */
7997 if (rt == 0xf) /* PLD/PLI */
8000 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8001 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8003 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8008 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8009 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8012 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8013 "ldrb{reg, immediate}/ldrbt",
8018 case 1: /* Load halfword and memory hints. */
8019 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8020 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8021 "pld/unalloc memhint", dsc);
8025 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8028 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8032 case 2: /* Load word */
8034 int insn2_bit_8_11 = bits (insn2, 8, 11);
8037 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8038 else if (op1 == 0x1) /* Encoding T3 */
8039 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8041 else /* op1 == 0x0 */
8043 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8044 /* LDR (immediate) */
8045 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8046 dsc, bit (insn2, 8), 1);
8047 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8048 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8051 /* LDR (register) */
8052 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8058 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8065 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8066 uint16_t insn2, struct regcache *regs,
8067 struct displaced_step_closure *dsc)
8070 unsigned short op = bit (insn2, 15);
8071 unsigned int op1 = bits (insn1, 11, 12);
8077 switch (bits (insn1, 9, 10))
8082 /* Load/store {dual, execlusive}, table branch. */
8083 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8084 && bits (insn2, 5, 7) == 0)
8085 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8088 /* PC is not allowed to use in load/store {dual, exclusive}
8090 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8091 "load/store dual/ex", dsc);
8093 else /* load/store multiple */
8095 switch (bits (insn1, 7, 8))
8097 case 0: case 3: /* SRS, RFE */
8098 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8101 case 1: case 2: /* LDM/STM/PUSH/POP */
8102 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8109 /* Data-processing (shift register). */
8110 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8113 default: /* Coprocessor instructions. */
8114 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8119 case 2: /* op1 = 2 */
8120 if (op) /* Branch and misc control. */
8122 if (bit (insn2, 14) /* BLX/BL */
8123 || bit (insn2, 12) /* Unconditional branch */
8124 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8125 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8127 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8132 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8134 int op = bits (insn1, 4, 8);
8135 int rn = bits (insn1, 0, 3);
8136 if ((op == 0 || op == 0xa) && rn == 0xf)
8137 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8140 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8143 else /* Data processing (modified immeidate) */
8144 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8148 case 3: /* op1 = 3 */
8149 switch (bits (insn1, 9, 10))
8153 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8155 else /* NEON Load/Store and Store single data item */
8156 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8157 "neon elt/struct load/store",
8160 case 1: /* op1 = 3, bits (9, 10) == 1 */
8161 switch (bits (insn1, 7, 8))
8163 case 0: case 1: /* Data processing (register) */
8164 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8167 case 2: /* Multiply and absolute difference */
8168 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8169 "mul/mua/diff", dsc);
8171 case 3: /* Long multiply and divide */
8172 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8177 default: /* Coprocessor instructions */
8178 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8187 internal_error (__FILE__, __LINE__,
8188 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8193 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8194 CORE_ADDR to, struct regcache *regs,
8195 struct displaced_step_closure *dsc)
8197 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8199 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8201 if (debug_displaced)
8202 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8203 "at %.8lx\n", insn1, (unsigned long) from);
8206 dsc->insn_size = thumb_insn_size (insn1);
8207 if (thumb_insn_size (insn1) == 4)
8210 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8211 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8214 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8218 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8219 CORE_ADDR to, struct regcache *regs,
8220 struct displaced_step_closure *dsc)
8223 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8226 /* Most displaced instructions use a 1-instruction scratch space, so set this
8227 here and override below if/when necessary. */
8229 dsc->insn_addr = from;
8230 dsc->scratch_base = to;
8231 dsc->cleanup = NULL;
8232 dsc->wrote_to_pc = 0;
8234 if (!displaced_in_arm_mode (regs))
8235 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8239 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8240 if (debug_displaced)
8241 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8242 "at %.8lx\n", (unsigned long) insn,
8243 (unsigned long) from);
8245 if ((insn & 0xf0000000) == 0xf0000000)
8246 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8247 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8249 case 0x0: case 0x1: case 0x2: case 0x3:
8250 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8253 case 0x4: case 0x5: case 0x6:
8254 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8258 err = arm_decode_media (gdbarch, insn, dsc);
8261 case 0x8: case 0x9: case 0xa: case 0xb:
8262 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8265 case 0xc: case 0xd: case 0xe: case 0xf:
8266 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8271 internal_error (__FILE__, __LINE__,
8272 _("arm_process_displaced_insn: Instruction decode error"));
8275 /* Actually set up the scratch space for a displaced instruction. */
8278 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8279 CORE_ADDR to, struct displaced_step_closure *dsc)
8281 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8282 unsigned int i, len, offset;
8283 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8284 int size = dsc->is_thumb? 2 : 4;
8285 const unsigned char *bkp_insn;
8288 /* Poke modified instruction(s). */
8289 for (i = 0; i < dsc->numinsns; i++)
8291 if (debug_displaced)
8293 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8295 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8298 fprintf_unfiltered (gdb_stdlog, "%.4x",
8299 (unsigned short)dsc->modinsn[i]);
8301 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8302 (unsigned long) to + offset);
8305 write_memory_unsigned_integer (to + offset, size,
8306 byte_order_for_code,
8311 /* Choose the correct breakpoint instruction. */
8314 bkp_insn = tdep->thumb_breakpoint;
8315 len = tdep->thumb_breakpoint_size;
8319 bkp_insn = tdep->arm_breakpoint;
8320 len = tdep->arm_breakpoint_size;
8323 /* Put breakpoint afterwards. */
8324 write_memory (to + offset, bkp_insn, len);
8326 if (debug_displaced)
8327 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8328 paddress (gdbarch, from), paddress (gdbarch, to));
8331 /* Entry point for copying an instruction into scratch space for displaced
8334 struct displaced_step_closure *
8335 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8336 CORE_ADDR from, CORE_ADDR to,
8337 struct regcache *regs)
8339 struct displaced_step_closure *dsc
8340 = xmalloc (sizeof (struct displaced_step_closure));
8341 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8342 arm_displaced_init_closure (gdbarch, from, to, dsc);
8347 /* Entry point for cleaning things up after a displaced instruction has been
8351 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8352 struct displaced_step_closure *dsc,
8353 CORE_ADDR from, CORE_ADDR to,
8354 struct regcache *regs)
8357 dsc->cleanup (gdbarch, regs, dsc);
8359 if (!dsc->wrote_to_pc)
8360 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8361 dsc->insn_addr + dsc->insn_size);
8365 #include "bfd-in2.h"
8366 #include "libcoff.h"
8369 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8371 struct gdbarch *gdbarch = info->application_data;
8373 if (arm_pc_is_thumb (gdbarch, memaddr))
8375 static asymbol *asym;
8376 static combined_entry_type ce;
8377 static struct coff_symbol_struct csym;
8378 static struct bfd fake_bfd;
8379 static bfd_target fake_target;
8381 if (csym.native == NULL)
8383 /* Create a fake symbol vector containing a Thumb symbol.
8384 This is solely so that the code in print_insn_little_arm()
8385 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8386 the presence of a Thumb symbol and switch to decoding
8387 Thumb instructions. */
8389 fake_target.flavour = bfd_target_coff_flavour;
8390 fake_bfd.xvec = &fake_target;
8391 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8393 csym.symbol.the_bfd = &fake_bfd;
8394 csym.symbol.name = "fake";
8395 asym = (asymbol *) & csym;
8398 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8399 info->symbols = &asym;
8402 info->symbols = NULL;
8404 if (info->endian == BFD_ENDIAN_BIG)
8405 return print_insn_big_arm (memaddr, info);
8407 return print_insn_little_arm (memaddr, info);
8410 /* The following define instruction sequences that will cause ARM
8411 cpu's to take an undefined instruction trap. These are used to
8412 signal a breakpoint to GDB.
8414 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8415 modes. A different instruction is required for each mode. The ARM
8416 cpu's can also be big or little endian. Thus four different
8417 instructions are needed to support all cases.
8419 Note: ARMv4 defines several new instructions that will take the
8420 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8421 not in fact add the new instructions. The new undefined
8422 instructions in ARMv4 are all instructions that had no defined
8423 behaviour in earlier chips. There is no guarantee that they will
8424 raise an exception, but may be treated as NOP's. In practice, it
8425 may only safe to rely on instructions matching:
8427 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8428 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8429 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8431 Even this may only true if the condition predicate is true. The
8432 following use a condition predicate of ALWAYS so it is always TRUE.
8434 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8435 and NetBSD all use a software interrupt rather than an undefined
8436 instruction to force a trap. This can be handled by by the
8437 abi-specific code during establishment of the gdbarch vector. */
8439 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8440 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8441 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8442 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8444 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8445 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8446 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8447 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8449 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8450 the program counter value to determine whether a 16-bit or 32-bit
8451 breakpoint should be used. It returns a pointer to a string of
8452 bytes that encode a breakpoint instruction, stores the length of
8453 the string to *lenptr, and adjusts the program counter (if
8454 necessary) to point to the actual memory location where the
8455 breakpoint should be inserted. */
8457 static const unsigned char *
8458 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8460 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8461 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8463 if (arm_pc_is_thumb (gdbarch, *pcptr))
8465 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8467 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8468 check whether we are replacing a 32-bit instruction. */
8469 if (tdep->thumb2_breakpoint != NULL)
8472 if (target_read_memory (*pcptr, buf, 2) == 0)
8474 unsigned short inst1;
8475 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8476 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
8478 *lenptr = tdep->thumb2_breakpoint_size;
8479 return tdep->thumb2_breakpoint;
8484 *lenptr = tdep->thumb_breakpoint_size;
8485 return tdep->thumb_breakpoint;
8489 *lenptr = tdep->arm_breakpoint_size;
8490 return tdep->arm_breakpoint;
8495 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8498 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8500 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8502 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8503 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8504 that this is not confused with a 32-bit ARM breakpoint. */
8508 /* Extract from an array REGBUF containing the (raw) register state a
8509 function return value of type TYPE, and copy that, in virtual
8510 format, into VALBUF. */
8513 arm_extract_return_value (struct type *type, struct regcache *regs,
8516 struct gdbarch *gdbarch = get_regcache_arch (regs);
8517 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8519 if (TYPE_CODE_FLT == TYPE_CODE (type))
8521 switch (gdbarch_tdep (gdbarch)->fp_model)
8525 /* The value is in register F0 in internal format. We need to
8526 extract the raw value and then convert it to the desired
8528 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8530 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8531 convert_from_extended (floatformat_from_type (type), tmpbuf,
8532 valbuf, gdbarch_byte_order (gdbarch));
8536 case ARM_FLOAT_SOFT_FPA:
8537 case ARM_FLOAT_SOFT_VFP:
8538 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8539 not using the VFP ABI code. */
8541 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8542 if (TYPE_LENGTH (type) > 4)
8543 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8544 valbuf + INT_REGISTER_SIZE);
8548 internal_error (__FILE__, __LINE__,
8549 _("arm_extract_return_value: "
8550 "Floating point model not supported"));
8554 else if (TYPE_CODE (type) == TYPE_CODE_INT
8555 || TYPE_CODE (type) == TYPE_CODE_CHAR
8556 || TYPE_CODE (type) == TYPE_CODE_BOOL
8557 || TYPE_CODE (type) == TYPE_CODE_PTR
8558 || TYPE_CODE (type) == TYPE_CODE_REF
8559 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8561 /* If the type is a plain integer, then the access is
8562 straight-forward. Otherwise we have to play around a bit
8564 int len = TYPE_LENGTH (type);
8565 int regno = ARM_A1_REGNUM;
8570 /* By using store_unsigned_integer we avoid having to do
8571 anything special for small big-endian values. */
8572 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8573 store_unsigned_integer (valbuf,
8574 (len > INT_REGISTER_SIZE
8575 ? INT_REGISTER_SIZE : len),
8577 len -= INT_REGISTER_SIZE;
8578 valbuf += INT_REGISTER_SIZE;
8583 /* For a structure or union the behaviour is as if the value had
8584 been stored to word-aligned memory and then loaded into
8585 registers with 32-bit load instruction(s). */
8586 int len = TYPE_LENGTH (type);
8587 int regno = ARM_A1_REGNUM;
8588 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8592 regcache_cooked_read (regs, regno++, tmpbuf);
8593 memcpy (valbuf, tmpbuf,
8594 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8595 len -= INT_REGISTER_SIZE;
8596 valbuf += INT_REGISTER_SIZE;
8602 /* Will a function return an aggregate type in memory or in a
8603 register? Return 0 if an aggregate type can be returned in a
8604 register, 1 if it must be returned in memory. */
8607 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8610 enum type_code code;
8612 CHECK_TYPEDEF (type);
8614 /* In the ARM ABI, "integer" like aggregate types are returned in
8615 registers. For an aggregate type to be integer like, its size
8616 must be less than or equal to INT_REGISTER_SIZE and the
8617 offset of each addressable subfield must be zero. Note that bit
8618 fields are not addressable, and all addressable subfields of
8619 unions always start at offset zero.
8621 This function is based on the behaviour of GCC 2.95.1.
8622 See: gcc/arm.c: arm_return_in_memory() for details.
8624 Note: All versions of GCC before GCC 2.95.2 do not set up the
8625 parameters correctly for a function returning the following
8626 structure: struct { float f;}; This should be returned in memory,
8627 not a register. Richard Earnshaw sent me a patch, but I do not
8628 know of any way to detect if a function like the above has been
8629 compiled with the correct calling convention. */
8631 /* All aggregate types that won't fit in a register must be returned
8633 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8638 /* The AAPCS says all aggregates not larger than a word are returned
8640 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8643 /* The only aggregate types that can be returned in a register are
8644 structs and unions. Arrays must be returned in memory. */
8645 code = TYPE_CODE (type);
8646 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
8651 /* Assume all other aggregate types can be returned in a register.
8652 Run a check for structures, unions and arrays. */
8655 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8658 /* Need to check if this struct/union is "integer" like. For
8659 this to be true, its size must be less than or equal to
8660 INT_REGISTER_SIZE and the offset of each addressable
8661 subfield must be zero. Note that bit fields are not
8662 addressable, and unions always start at offset zero. If any
8663 of the subfields is a floating point type, the struct/union
8664 cannot be an integer type. */
8666 /* For each field in the object, check:
8667 1) Is it FP? --> yes, nRc = 1;
8668 2) Is it addressable (bitpos != 0) and
8669 not packed (bitsize == 0)?
8673 for (i = 0; i < TYPE_NFIELDS (type); i++)
8675 enum type_code field_type_code;
8676 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
8679 /* Is it a floating point type field? */
8680 if (field_type_code == TYPE_CODE_FLT)
8686 /* If bitpos != 0, then we have to care about it. */
8687 if (TYPE_FIELD_BITPOS (type, i) != 0)
8689 /* Bitfields are not addressable. If the field bitsize is
8690 zero, then the field is not packed. Hence it cannot be
8691 a bitfield or any other packed type. */
8692 if (TYPE_FIELD_BITSIZE (type, i) == 0)
8704 /* Write into appropriate registers a function return value of type
8705 TYPE, given in virtual format. */
8708 arm_store_return_value (struct type *type, struct regcache *regs,
8709 const gdb_byte *valbuf)
8711 struct gdbarch *gdbarch = get_regcache_arch (regs);
8712 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8714 if (TYPE_CODE (type) == TYPE_CODE_FLT)
8716 char buf[MAX_REGISTER_SIZE];
8718 switch (gdbarch_tdep (gdbarch)->fp_model)
8722 convert_to_extended (floatformat_from_type (type), buf, valbuf,
8723 gdbarch_byte_order (gdbarch));
8724 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
8727 case ARM_FLOAT_SOFT_FPA:
8728 case ARM_FLOAT_SOFT_VFP:
8729 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8730 not using the VFP ABI code. */
8732 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
8733 if (TYPE_LENGTH (type) > 4)
8734 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
8735 valbuf + INT_REGISTER_SIZE);
8739 internal_error (__FILE__, __LINE__,
8740 _("arm_store_return_value: Floating "
8741 "point model not supported"));
8745 else if (TYPE_CODE (type) == TYPE_CODE_INT
8746 || TYPE_CODE (type) == TYPE_CODE_CHAR
8747 || TYPE_CODE (type) == TYPE_CODE_BOOL
8748 || TYPE_CODE (type) == TYPE_CODE_PTR
8749 || TYPE_CODE (type) == TYPE_CODE_REF
8750 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8752 if (TYPE_LENGTH (type) <= 4)
8754 /* Values of one word or less are zero/sign-extended and
8756 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8757 LONGEST val = unpack_long (type, valbuf);
8759 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8760 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8764 /* Integral values greater than one word are stored in consecutive
8765 registers starting with r0. This will always be a multiple of
8766 the regiser size. */
8767 int len = TYPE_LENGTH (type);
8768 int regno = ARM_A1_REGNUM;
8772 regcache_cooked_write (regs, regno++, valbuf);
8773 len -= INT_REGISTER_SIZE;
8774 valbuf += INT_REGISTER_SIZE;
8780 /* For a structure or union the behaviour is as if the value had
8781 been stored to word-aligned memory and then loaded into
8782 registers with 32-bit load instruction(s). */
8783 int len = TYPE_LENGTH (type);
8784 int regno = ARM_A1_REGNUM;
8785 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8789 memcpy (tmpbuf, valbuf,
8790 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8791 regcache_cooked_write (regs, regno++, tmpbuf);
8792 len -= INT_REGISTER_SIZE;
8793 valbuf += INT_REGISTER_SIZE;
8799 /* Handle function return values. */
8801 static enum return_value_convention
8802 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
8803 struct type *valtype, struct regcache *regcache,
8804 gdb_byte *readbuf, const gdb_byte *writebuf)
8806 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8807 enum arm_vfp_cprc_base_type vfp_base_type;
8810 if (arm_vfp_abi_for_function (gdbarch, func_type)
8811 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
8813 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
8814 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
8816 for (i = 0; i < vfp_base_count; i++)
8818 if (reg_char == 'q')
8821 arm_neon_quad_write (gdbarch, regcache, i,
8822 writebuf + i * unit_length);
8825 arm_neon_quad_read (gdbarch, regcache, i,
8826 readbuf + i * unit_length);
8833 sprintf (name_buf, "%c%d", reg_char, i);
8834 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8837 regcache_cooked_write (regcache, regnum,
8838 writebuf + i * unit_length);
8840 regcache_cooked_read (regcache, regnum,
8841 readbuf + i * unit_length);
8844 return RETURN_VALUE_REGISTER_CONVENTION;
8847 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
8848 || TYPE_CODE (valtype) == TYPE_CODE_UNION
8849 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
8851 if (tdep->struct_return == pcc_struct_return
8852 || arm_return_in_memory (gdbarch, valtype))
8853 return RETURN_VALUE_STRUCT_CONVENTION;
8857 arm_store_return_value (valtype, regcache, writebuf);
8860 arm_extract_return_value (valtype, regcache, readbuf);
8862 return RETURN_VALUE_REGISTER_CONVENTION;
8867 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
8869 struct gdbarch *gdbarch = get_frame_arch (frame);
8870 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8871 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8873 char buf[INT_REGISTER_SIZE];
8875 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
8877 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
8881 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
8885 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8886 return the target PC. Otherwise return 0. */
8889 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
8893 CORE_ADDR start_addr;
8895 /* Find the starting address and name of the function containing the PC. */
8896 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
8899 /* If PC is in a Thumb call or return stub, return the address of the
8900 target PC, which is in a register. The thunk functions are called
8901 _call_via_xx, where x is the register name. The possible names
8902 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8903 functions, named __ARM_call_via_r[0-7]. */
8904 if (strncmp (name, "_call_via_", 10) == 0
8905 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
8907 /* Use the name suffix to determine which register contains the
8909 static char *table[15] =
8910 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8911 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8914 int offset = strlen (name) - 2;
8916 for (regno = 0; regno <= 14; regno++)
8917 if (strcmp (&name[offset], table[regno]) == 0)
8918 return get_frame_register_unsigned (frame, regno);
8921 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8922 non-interworking calls to foo. We could decode the stubs
8923 to find the target but it's easier to use the symbol table. */
8924 namelen = strlen (name);
8925 if (name[0] == '_' && name[1] == '_'
8926 && ((namelen > 2 + strlen ("_from_thumb")
8927 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
8928 strlen ("_from_thumb")) == 0)
8929 || (namelen > 2 + strlen ("_from_arm")
8930 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
8931 strlen ("_from_arm")) == 0)))
8934 int target_len = namelen - 2;
8935 struct minimal_symbol *minsym;
8936 struct objfile *objfile;
8937 struct obj_section *sec;
8939 if (name[namelen - 1] == 'b')
8940 target_len -= strlen ("_from_thumb");
8942 target_len -= strlen ("_from_arm");
8944 target_name = alloca (target_len + 1);
8945 memcpy (target_name, name + 2, target_len);
8946 target_name[target_len] = '\0';
8948 sec = find_pc_section (pc);
8949 objfile = (sec == NULL) ? NULL : sec->objfile;
8950 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
8952 return SYMBOL_VALUE_ADDRESS (minsym);
8957 return 0; /* not a stub */
8961 set_arm_command (char *args, int from_tty)
8963 printf_unfiltered (_("\
8964 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8965 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
8969 show_arm_command (char *args, int from_tty)
8971 cmd_show_list (showarmcmdlist, from_tty, "");
8975 arm_update_current_architecture (void)
8977 struct gdbarch_info info;
8979 /* If the current architecture is not ARM, we have nothing to do. */
8980 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
8983 /* Update the architecture. */
8984 gdbarch_info_init (&info);
8986 if (!gdbarch_update_p (info))
8987 internal_error (__FILE__, __LINE__, _("could not update architecture"));
8991 set_fp_model_sfunc (char *args, int from_tty,
8992 struct cmd_list_element *c)
8994 enum arm_float_model fp_model;
8996 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
8997 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
8999 arm_fp_model = fp_model;
9003 if (fp_model == ARM_FLOAT_LAST)
9004 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9007 arm_update_current_architecture ();
9011 show_fp_model (struct ui_file *file, int from_tty,
9012 struct cmd_list_element *c, const char *value)
9014 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9016 if (arm_fp_model == ARM_FLOAT_AUTO
9017 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
9018 fprintf_filtered (file, _("\
9019 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9020 fp_model_strings[tdep->fp_model]);
9022 fprintf_filtered (file, _("\
9023 The current ARM floating point model is \"%s\".\n"),
9024 fp_model_strings[arm_fp_model]);
9028 arm_set_abi (char *args, int from_tty,
9029 struct cmd_list_element *c)
9031 enum arm_abi_kind arm_abi;
9033 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9034 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9036 arm_abi_global = arm_abi;
9040 if (arm_abi == ARM_ABI_LAST)
9041 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9044 arm_update_current_architecture ();
9048 arm_show_abi (struct ui_file *file, int from_tty,
9049 struct cmd_list_element *c, const char *value)
9051 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9053 if (arm_abi_global == ARM_ABI_AUTO
9054 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
9055 fprintf_filtered (file, _("\
9056 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9057 arm_abi_strings[tdep->arm_abi]);
9059 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9064 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9065 struct cmd_list_element *c, const char *value)
9067 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9069 fprintf_filtered (file,
9070 _("The current execution mode assumed "
9071 "(when symbols are unavailable) is \"%s\".\n"),
9072 arm_fallback_mode_string);
9076 arm_show_force_mode (struct ui_file *file, int from_tty,
9077 struct cmd_list_element *c, const char *value)
9079 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
9081 fprintf_filtered (file,
9082 _("The current execution mode assumed "
9083 "(even when symbols are available) is \"%s\".\n"),
9084 arm_force_mode_string);
9087 /* If the user changes the register disassembly style used for info
9088 register and other commands, we have to also switch the style used
9089 in opcodes for disassembly output. This function is run in the "set
9090 arm disassembly" command, and does that. */
9093 set_disassembly_style_sfunc (char *args, int from_tty,
9094 struct cmd_list_element *c)
9096 set_disassembly_style ();
9099 /* Return the ARM register name corresponding to register I. */
9101 arm_register_name (struct gdbarch *gdbarch, int i)
9103 const int num_regs = gdbarch_num_regs (gdbarch);
9105 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9106 && i >= num_regs && i < num_regs + 32)
9108 static const char *const vfp_pseudo_names[] = {
9109 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9110 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9111 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9112 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9115 return vfp_pseudo_names[i - num_regs];
9118 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9119 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9121 static const char *const neon_pseudo_names[] = {
9122 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9123 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9126 return neon_pseudo_names[i - num_regs - 32];
9129 if (i >= ARRAY_SIZE (arm_register_names))
9130 /* These registers are only supported on targets which supply
9131 an XML description. */
9134 return arm_register_names[i];
9138 set_disassembly_style (void)
9142 /* Find the style that the user wants. */
9143 for (current = 0; current < num_disassembly_options; current++)
9144 if (disassembly_style == valid_disassembly_styles[current])
9146 gdb_assert (current < num_disassembly_options);
9148 /* Synchronize the disassembler. */
9149 set_arm_regname_option (current);
9152 /* Test whether the coff symbol specific value corresponds to a Thumb
9156 coff_sym_is_thumb (int val)
9158 return (val == C_THUMBEXT
9159 || val == C_THUMBSTAT
9160 || val == C_THUMBEXTFUNC
9161 || val == C_THUMBSTATFUNC
9162 || val == C_THUMBLABEL);
9165 /* arm_coff_make_msymbol_special()
9166 arm_elf_make_msymbol_special()
9168 These functions test whether the COFF or ELF symbol corresponds to
9169 an address in thumb code, and set a "special" bit in a minimal
9170 symbol to indicate that it does. */
9173 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9175 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9176 == ST_BRANCH_TO_THUMB)
9177 MSYMBOL_SET_SPECIAL (msym);
9181 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9183 if (coff_sym_is_thumb (val))
9184 MSYMBOL_SET_SPECIAL (msym);
9188 arm_objfile_data_free (struct objfile *objfile, void *arg)
9190 struct arm_per_objfile *data = arg;
9193 for (i = 0; i < objfile->obfd->section_count; i++)
9194 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9198 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9201 const char *name = bfd_asymbol_name (sym);
9202 struct arm_per_objfile *data;
9203 VEC(arm_mapping_symbol_s) **map_p;
9204 struct arm_mapping_symbol new_map_sym;
9206 gdb_assert (name[0] == '$');
9207 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9210 data = objfile_data (objfile, arm_objfile_data_key);
9213 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9214 struct arm_per_objfile);
9215 set_objfile_data (objfile, arm_objfile_data_key, data);
9216 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9217 objfile->obfd->section_count,
9218 VEC(arm_mapping_symbol_s) *);
9220 map_p = &data->section_maps[bfd_get_section (sym)->index];
9222 new_map_sym.value = sym->value;
9223 new_map_sym.type = name[1];
9225 /* Assume that most mapping symbols appear in order of increasing
9226 value. If they were randomly distributed, it would be faster to
9227 always push here and then sort at first use. */
9228 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9230 struct arm_mapping_symbol *prev_map_sym;
9232 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9233 if (prev_map_sym->value >= sym->value)
9236 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9237 arm_compare_mapping_symbols);
9238 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9243 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9247 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9249 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9250 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9252 /* If necessary, set the T bit. */
9255 ULONGEST val, t_bit;
9256 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9257 t_bit = arm_psr_thumb_bit (gdbarch);
9258 if (arm_pc_is_thumb (gdbarch, pc))
9259 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9262 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9267 /* Read the contents of a NEON quad register, by reading from two
9268 double registers. This is used to implement the quad pseudo
9269 registers, and for argument passing in case the quad registers are
9270 missing; vectors are passed in quad registers when using the VFP
9271 ABI, even if a NEON unit is not present. REGNUM is the index of
9272 the quad register, in [0, 15]. */
9274 static enum register_status
9275 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9276 int regnum, gdb_byte *buf)
9279 gdb_byte reg_buf[8];
9280 int offset, double_regnum;
9281 enum register_status status;
9283 sprintf (name_buf, "d%d", regnum << 1);
9284 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9287 /* d0 is always the least significant half of q0. */
9288 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9293 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9294 if (status != REG_VALID)
9296 memcpy (buf + offset, reg_buf, 8);
9298 offset = 8 - offset;
9299 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9300 if (status != REG_VALID)
9302 memcpy (buf + offset, reg_buf, 8);
9307 static enum register_status
9308 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9309 int regnum, gdb_byte *buf)
9311 const int num_regs = gdbarch_num_regs (gdbarch);
9313 gdb_byte reg_buf[8];
9314 int offset, double_regnum;
9316 gdb_assert (regnum >= num_regs);
9319 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9320 /* Quad-precision register. */
9321 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9324 enum register_status status;
9326 /* Single-precision register. */
9327 gdb_assert (regnum < 32);
9329 /* s0 is always the least significant half of d0. */
9330 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9331 offset = (regnum & 1) ? 0 : 4;
9333 offset = (regnum & 1) ? 4 : 0;
9335 sprintf (name_buf, "d%d", regnum >> 1);
9336 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9339 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9340 if (status == REG_VALID)
9341 memcpy (buf, reg_buf + offset, 4);
9346 /* Store the contents of BUF to a NEON quad register, by writing to
9347 two double registers. This is used to implement the quad pseudo
9348 registers, and for argument passing in case the quad registers are
9349 missing; vectors are passed in quad registers when using the VFP
9350 ABI, even if a NEON unit is not present. REGNUM is the index
9351 of the quad register, in [0, 15]. */
9354 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9355 int regnum, const gdb_byte *buf)
9358 gdb_byte reg_buf[8];
9359 int offset, double_regnum;
9361 sprintf (name_buf, "d%d", regnum << 1);
9362 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9365 /* d0 is always the least significant half of q0. */
9366 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9371 regcache_raw_write (regcache, double_regnum, buf + offset);
9372 offset = 8 - offset;
9373 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9377 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9378 int regnum, const gdb_byte *buf)
9380 const int num_regs = gdbarch_num_regs (gdbarch);
9382 gdb_byte reg_buf[8];
9383 int offset, double_regnum;
9385 gdb_assert (regnum >= num_regs);
9388 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9389 /* Quad-precision register. */
9390 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9393 /* Single-precision register. */
9394 gdb_assert (regnum < 32);
9396 /* s0 is always the least significant half of d0. */
9397 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9398 offset = (regnum & 1) ? 0 : 4;
9400 offset = (regnum & 1) ? 4 : 0;
9402 sprintf (name_buf, "d%d", regnum >> 1);
9403 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9406 regcache_raw_read (regcache, double_regnum, reg_buf);
9407 memcpy (reg_buf + offset, buf, 4);
9408 regcache_raw_write (regcache, double_regnum, reg_buf);
9412 static struct value *
9413 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9415 const int *reg_p = baton;
9416 return value_of_register (*reg_p, frame);
9419 static enum gdb_osabi
9420 arm_elf_osabi_sniffer (bfd *abfd)
9422 unsigned int elfosabi;
9423 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9425 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9427 if (elfosabi == ELFOSABI_ARM)
9428 /* GNU tools use this value. Check note sections in this case,
9430 bfd_map_over_sections (abfd,
9431 generic_elf_osabi_sniff_abi_tag_sections,
9434 /* Anything else will be handled by the generic ELF sniffer. */
9439 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9440 struct reggroup *group)
9442 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9443 this, FPS register belongs to save_regroup, restore_reggroup, and
9444 all_reggroup, of course. */
9445 if (regnum == ARM_FPS_REGNUM)
9446 return (group == float_reggroup
9447 || group == save_reggroup
9448 || group == restore_reggroup
9449 || group == all_reggroup);
9451 return default_register_reggroup_p (gdbarch, regnum, group);
9455 /* Initialize the current architecture based on INFO. If possible,
9456 re-use an architecture from ARCHES, which is a list of
9457 architectures already created during this debugging session.
9459 Called e.g. at program startup, when reading a core file, and when
9460 reading a binary file. */
9462 static struct gdbarch *
9463 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9465 struct gdbarch_tdep *tdep;
9466 struct gdbarch *gdbarch;
9467 struct gdbarch_list *best_arch;
9468 enum arm_abi_kind arm_abi = arm_abi_global;
9469 enum arm_float_model fp_model = arm_fp_model;
9470 struct tdesc_arch_data *tdesc_data = NULL;
9472 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9474 int have_fpa_registers = 1;
9475 const struct target_desc *tdesc = info.target_desc;
9477 /* If we have an object to base this architecture on, try to determine
9480 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9482 int ei_osabi, e_flags;
9484 switch (bfd_get_flavour (info.abfd))
9486 case bfd_target_aout_flavour:
9487 /* Assume it's an old APCS-style ABI. */
9488 arm_abi = ARM_ABI_APCS;
9491 case bfd_target_coff_flavour:
9492 /* Assume it's an old APCS-style ABI. */
9494 arm_abi = ARM_ABI_APCS;
9497 case bfd_target_elf_flavour:
9498 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9499 e_flags = elf_elfheader (info.abfd)->e_flags;
9501 if (ei_osabi == ELFOSABI_ARM)
9503 /* GNU tools used to use this value, but do not for EABI
9504 objects. There's nowhere to tag an EABI version
9505 anyway, so assume APCS. */
9506 arm_abi = ARM_ABI_APCS;
9508 else if (ei_osabi == ELFOSABI_NONE)
9510 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9511 int attr_arch, attr_profile;
9515 case EF_ARM_EABI_UNKNOWN:
9516 /* Assume GNU tools. */
9517 arm_abi = ARM_ABI_APCS;
9520 case EF_ARM_EABI_VER4:
9521 case EF_ARM_EABI_VER5:
9522 arm_abi = ARM_ABI_AAPCS;
9523 /* EABI binaries default to VFP float ordering.
9524 They may also contain build attributes that can
9525 be used to identify if the VFP argument-passing
9527 if (fp_model == ARM_FLOAT_AUTO)
9530 switch (bfd_elf_get_obj_attr_int (info.abfd,
9535 /* "The user intended FP parameter/result
9536 passing to conform to AAPCS, base
9538 fp_model = ARM_FLOAT_SOFT_VFP;
9541 /* "The user intended FP parameter/result
9542 passing to conform to AAPCS, VFP
9544 fp_model = ARM_FLOAT_VFP;
9547 /* "The user intended FP parameter/result
9548 passing to conform to tool chain-specific
9549 conventions" - we don't know any such
9550 conventions, so leave it as "auto". */
9553 /* Attribute value not mentioned in the
9554 October 2008 ABI, so leave it as
9559 fp_model = ARM_FLOAT_SOFT_VFP;
9565 /* Leave it as "auto". */
9566 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9571 /* Detect M-profile programs. This only works if the
9572 executable file includes build attributes; GCC does
9573 copy them to the executable, but e.g. RealView does
9575 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9577 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9579 Tag_CPU_arch_profile);
9580 /* GCC specifies the profile for v6-M; RealView only
9581 specifies the profile for architectures starting with
9582 V7 (as opposed to architectures with a tag
9583 numerically greater than TAG_CPU_ARCH_V7). */
9584 if (!tdesc_has_registers (tdesc)
9585 && (attr_arch == TAG_CPU_ARCH_V6_M
9586 || attr_arch == TAG_CPU_ARCH_V6S_M
9587 || attr_profile == 'M'))
9588 tdesc = tdesc_arm_with_m;
9592 if (fp_model == ARM_FLOAT_AUTO)
9594 int e_flags = elf_elfheader (info.abfd)->e_flags;
9596 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9599 /* Leave it as "auto". Strictly speaking this case
9600 means FPA, but almost nobody uses that now, and
9601 many toolchains fail to set the appropriate bits
9602 for the floating-point model they use. */
9604 case EF_ARM_SOFT_FLOAT:
9605 fp_model = ARM_FLOAT_SOFT_FPA;
9607 case EF_ARM_VFP_FLOAT:
9608 fp_model = ARM_FLOAT_VFP;
9610 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9611 fp_model = ARM_FLOAT_SOFT_VFP;
9616 if (e_flags & EF_ARM_BE8)
9617 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
9622 /* Leave it as "auto". */
9627 /* Check any target description for validity. */
9628 if (tdesc_has_registers (tdesc))
9630 /* For most registers we require GDB's default names; but also allow
9631 the numeric names for sp / lr / pc, as a convenience. */
9632 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
9633 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
9634 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
9636 const struct tdesc_feature *feature;
9639 feature = tdesc_find_feature (tdesc,
9640 "org.gnu.gdb.arm.core");
9641 if (feature == NULL)
9643 feature = tdesc_find_feature (tdesc,
9644 "org.gnu.gdb.arm.m-profile");
9645 if (feature == NULL)
9651 tdesc_data = tdesc_data_alloc ();
9654 for (i = 0; i < ARM_SP_REGNUM; i++)
9655 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9656 arm_register_names[i]);
9657 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9660 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9663 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9667 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9668 ARM_PS_REGNUM, "xpsr");
9670 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9671 ARM_PS_REGNUM, "cpsr");
9675 tdesc_data_cleanup (tdesc_data);
9679 feature = tdesc_find_feature (tdesc,
9680 "org.gnu.gdb.arm.fpa");
9681 if (feature != NULL)
9684 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9685 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9686 arm_register_names[i]);
9689 tdesc_data_cleanup (tdesc_data);
9694 have_fpa_registers = 0;
9696 feature = tdesc_find_feature (tdesc,
9697 "org.gnu.gdb.xscale.iwmmxt");
9698 if (feature != NULL)
9700 static const char *const iwmmxt_names[] = {
9701 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9702 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9703 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9704 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9708 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9710 &= tdesc_numbered_register (feature, tdesc_data, i,
9711 iwmmxt_names[i - ARM_WR0_REGNUM]);
9713 /* Check for the control registers, but do not fail if they
9715 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9716 tdesc_numbered_register (feature, tdesc_data, i,
9717 iwmmxt_names[i - ARM_WR0_REGNUM]);
9719 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9721 &= tdesc_numbered_register (feature, tdesc_data, i,
9722 iwmmxt_names[i - ARM_WR0_REGNUM]);
9726 tdesc_data_cleanup (tdesc_data);
9731 /* If we have a VFP unit, check whether the single precision registers
9732 are present. If not, then we will synthesize them as pseudo
9734 feature = tdesc_find_feature (tdesc,
9735 "org.gnu.gdb.arm.vfp");
9736 if (feature != NULL)
9738 static const char *const vfp_double_names[] = {
9739 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9740 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9741 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9742 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9745 /* Require the double precision registers. There must be either
9748 for (i = 0; i < 32; i++)
9750 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9752 vfp_double_names[i]);
9756 if (!valid_p && i == 16)
9759 /* Also require FPSCR. */
9760 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9761 ARM_FPSCR_REGNUM, "fpscr");
9764 tdesc_data_cleanup (tdesc_data);
9768 if (tdesc_unnumbered_register (feature, "s0") == 0)
9769 have_vfp_pseudos = 1;
9771 have_vfp_registers = 1;
9773 /* If we have VFP, also check for NEON. The architecture allows
9774 NEON without VFP (integer vector operations only), but GDB
9775 does not support that. */
9776 feature = tdesc_find_feature (tdesc,
9777 "org.gnu.gdb.arm.neon");
9778 if (feature != NULL)
9780 /* NEON requires 32 double-precision registers. */
9783 tdesc_data_cleanup (tdesc_data);
9787 /* If there are quad registers defined by the stub, use
9788 their type; otherwise (normally) provide them with
9789 the default type. */
9790 if (tdesc_unnumbered_register (feature, "q0") == 0)
9791 have_neon_pseudos = 1;
9798 /* If there is already a candidate, use it. */
9799 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
9801 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
9803 if (arm_abi != ARM_ABI_AUTO
9804 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
9807 if (fp_model != ARM_FLOAT_AUTO
9808 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
9811 /* There are various other properties in tdep that we do not
9812 need to check here: those derived from a target description,
9813 since gdbarches with a different target description are
9814 automatically disqualified. */
9816 /* Do check is_m, though, since it might come from the binary. */
9817 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
9820 /* Found a match. */
9824 if (best_arch != NULL)
9826 if (tdesc_data != NULL)
9827 tdesc_data_cleanup (tdesc_data);
9828 return best_arch->gdbarch;
9831 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
9832 gdbarch = gdbarch_alloc (&info, tdep);
9834 /* Record additional information about the architecture we are defining.
9835 These are gdbarch discriminators, like the OSABI. */
9836 tdep->arm_abi = arm_abi;
9837 tdep->fp_model = fp_model;
9839 tdep->have_fpa_registers = have_fpa_registers;
9840 tdep->have_vfp_registers = have_vfp_registers;
9841 tdep->have_vfp_pseudos = have_vfp_pseudos;
9842 tdep->have_neon_pseudos = have_neon_pseudos;
9843 tdep->have_neon = have_neon;
9846 switch (info.byte_order_for_code)
9848 case BFD_ENDIAN_BIG:
9849 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
9850 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
9851 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
9852 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
9856 case BFD_ENDIAN_LITTLE:
9857 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
9858 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
9859 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
9860 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
9865 internal_error (__FILE__, __LINE__,
9866 _("arm_gdbarch_init: bad byte order for float format"));
9869 /* On ARM targets char defaults to unsigned. */
9870 set_gdbarch_char_signed (gdbarch, 0);
9872 /* Note: for displaced stepping, this includes the breakpoint, and one word
9873 of additional scratch space. This setting isn't used for anything beside
9874 displaced stepping at present. */
9875 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
9877 /* This should be low enough for everything. */
9878 tdep->lowest_pc = 0x20;
9879 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
9881 /* The default, for both APCS and AAPCS, is to return small
9882 structures in registers. */
9883 tdep->struct_return = reg_struct_return;
9885 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
9886 set_gdbarch_frame_align (gdbarch, arm_frame_align);
9888 set_gdbarch_write_pc (gdbarch, arm_write_pc);
9890 /* Frame handling. */
9891 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
9892 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
9893 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
9895 frame_base_set_default (gdbarch, &arm_normal_base);
9897 /* Address manipulation. */
9898 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
9899 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
9901 /* Advance PC across function entry code. */
9902 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
9904 /* Detect whether PC is in function epilogue. */
9905 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
9907 /* Skip trampolines. */
9908 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
9910 /* The stack grows downward. */
9911 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
9913 /* Breakpoint manipulation. */
9914 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
9915 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
9916 arm_remote_breakpoint_from_pc);
9918 /* Information about registers, etc. */
9919 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
9920 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
9921 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
9922 set_gdbarch_register_type (gdbarch, arm_register_type);
9923 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
9925 /* This "info float" is FPA-specific. Use the generic version if we
9927 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
9928 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
9930 /* Internal <-> external register number maps. */
9931 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
9932 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
9934 set_gdbarch_register_name (gdbarch, arm_register_name);
9936 /* Returning results. */
9937 set_gdbarch_return_value (gdbarch, arm_return_value);
9940 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
9942 /* Minsymbol frobbing. */
9943 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
9944 set_gdbarch_coff_make_msymbol_special (gdbarch,
9945 arm_coff_make_msymbol_special);
9946 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
9948 /* Thumb-2 IT block support. */
9949 set_gdbarch_adjust_breakpoint_address (gdbarch,
9950 arm_adjust_breakpoint_address);
9952 /* Virtual tables. */
9953 set_gdbarch_vbit_in_delta (gdbarch, 1);
9955 /* Hook in the ABI-specific overrides, if they have been registered. */
9956 gdbarch_init_osabi (info, gdbarch);
9958 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
9960 /* Add some default predicates. */
9961 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
9962 dwarf2_append_unwinders (gdbarch);
9963 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
9964 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
9966 /* Now we have tuned the configuration, set a few final things,
9967 based on what the OS ABI has told us. */
9969 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9970 binaries are always marked. */
9971 if (tdep->arm_abi == ARM_ABI_AUTO)
9972 tdep->arm_abi = ARM_ABI_APCS;
9974 /* Watchpoints are not steppable. */
9975 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9977 /* We used to default to FPA for generic ARM, but almost nobody
9978 uses that now, and we now provide a way for the user to force
9979 the model. So default to the most useful variant. */
9980 if (tdep->fp_model == ARM_FLOAT_AUTO)
9981 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
9983 if (tdep->jb_pc >= 0)
9984 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
9986 /* Floating point sizes and format. */
9987 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
9988 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
9990 set_gdbarch_double_format
9991 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9992 set_gdbarch_long_double_format
9993 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9997 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
9998 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10001 if (have_vfp_pseudos)
10003 /* NOTE: These are the only pseudo registers used by
10004 the ARM target at the moment. If more are added, a
10005 little more care in numbering will be needed. */
10007 int num_pseudos = 32;
10008 if (have_neon_pseudos)
10010 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10011 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10012 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10017 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10019 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10021 /* Override tdesc_register_type to adjust the types of VFP
10022 registers for NEON. */
10023 set_gdbarch_register_type (gdbarch, arm_register_type);
10026 /* Add standard register aliases. We add aliases even for those
10027 nanes which are used by the current architecture - it's simpler,
10028 and does no harm, since nothing ever lists user registers. */
10029 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10030 user_reg_add (gdbarch, arm_register_aliases[i].name,
10031 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10037 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10039 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10044 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10045 (unsigned long) tdep->lowest_pc);
10048 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10051 _initialize_arm_tdep (void)
10053 struct ui_file *stb;
10055 struct cmd_list_element *new_set, *new_show;
10056 const char *setname;
10057 const char *setdesc;
10058 const char *const *regnames;
10060 static char *helptext;
10061 char regdesc[1024], *rdptr = regdesc;
10062 size_t rest = sizeof (regdesc);
10064 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10066 arm_objfile_data_key
10067 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10069 /* Add ourselves to objfile event chain. */
10070 observer_attach_new_objfile (arm_exidx_new_objfile);
10072 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10074 /* Register an ELF OS ABI sniffer for ARM binaries. */
10075 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10076 bfd_target_elf_flavour,
10077 arm_elf_osabi_sniffer);
10079 /* Initialize the standard target descriptions. */
10080 initialize_tdesc_arm_with_m ();
10081 initialize_tdesc_arm_with_iwmmxt ();
10082 initialize_tdesc_arm_with_vfpv2 ();
10083 initialize_tdesc_arm_with_vfpv3 ();
10084 initialize_tdesc_arm_with_neon ();
10086 /* Get the number of possible sets of register names defined in opcodes. */
10087 num_disassembly_options = get_arm_regname_num_options ();
10089 /* Add root prefix command for all "set arm"/"show arm" commands. */
10090 add_prefix_cmd ("arm", no_class, set_arm_command,
10091 _("Various ARM-specific commands."),
10092 &setarmcmdlist, "set arm ", 0, &setlist);
10094 add_prefix_cmd ("arm", no_class, show_arm_command,
10095 _("Various ARM-specific commands."),
10096 &showarmcmdlist, "show arm ", 0, &showlist);
10098 /* Sync the opcode insn printer with our register viewer. */
10099 parse_arm_disassembler_option ("reg-names-std");
10101 /* Initialize the array that will be passed to
10102 add_setshow_enum_cmd(). */
10103 valid_disassembly_styles
10104 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10105 for (i = 0; i < num_disassembly_options; i++)
10107 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10108 valid_disassembly_styles[i] = setname;
10109 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10112 /* When we find the default names, tell the disassembler to use
10114 if (!strcmp (setname, "std"))
10116 disassembly_style = setname;
10117 set_arm_regname_option (i);
10120 /* Mark the end of valid options. */
10121 valid_disassembly_styles[num_disassembly_options] = NULL;
10123 /* Create the help text. */
10124 stb = mem_fileopen ();
10125 fprintf_unfiltered (stb, "%s%s%s",
10126 _("The valid values are:\n"),
10128 _("The default is \"std\"."));
10129 helptext = ui_file_xstrdup (stb, NULL);
10130 ui_file_delete (stb);
10132 add_setshow_enum_cmd("disassembler", no_class,
10133 valid_disassembly_styles, &disassembly_style,
10134 _("Set the disassembly style."),
10135 _("Show the disassembly style."),
10137 set_disassembly_style_sfunc,
10138 NULL, /* FIXME: i18n: The disassembly style is
10140 &setarmcmdlist, &showarmcmdlist);
10142 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10143 _("Set usage of ARM 32-bit mode."),
10144 _("Show usage of ARM 32-bit mode."),
10145 _("When off, a 26-bit PC will be used."),
10147 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10149 &setarmcmdlist, &showarmcmdlist);
10151 /* Add a command to allow the user to force the FPU model. */
10152 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10153 _("Set the floating point type."),
10154 _("Show the floating point type."),
10155 _("auto - Determine the FP typefrom the OS-ABI.\n\
10156 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10157 fpa - FPA co-processor (GCC compiled).\n\
10158 softvfp - Software FP with pure-endian doubles.\n\
10159 vfp - VFP co-processor."),
10160 set_fp_model_sfunc, show_fp_model,
10161 &setarmcmdlist, &showarmcmdlist);
10163 /* Add a command to allow the user to force the ABI. */
10164 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10166 _("Show the ABI."),
10167 NULL, arm_set_abi, arm_show_abi,
10168 &setarmcmdlist, &showarmcmdlist);
10170 /* Add two commands to allow the user to force the assumed
10172 add_setshow_enum_cmd ("fallback-mode", class_support,
10173 arm_mode_strings, &arm_fallback_mode_string,
10174 _("Set the mode assumed when symbols are unavailable."),
10175 _("Show the mode assumed when symbols are unavailable."),
10176 NULL, NULL, arm_show_fallback_mode,
10177 &setarmcmdlist, &showarmcmdlist);
10178 add_setshow_enum_cmd ("force-mode", class_support,
10179 arm_mode_strings, &arm_force_mode_string,
10180 _("Set the mode assumed even when symbols are available."),
10181 _("Show the mode assumed even when symbols are available."),
10182 NULL, NULL, arm_show_force_mode,
10183 &setarmcmdlist, &showarmcmdlist);
10185 /* Debugging flag. */
10186 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10187 _("Set ARM debugging."),
10188 _("Show ARM debugging."),
10189 _("When on, arm-specific debugging is enabled."),
10191 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10192 &setdebuglist, &showdebuglist);