1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
62 #include "features/arm-with-m.c"
63 #include "features/arm-with-m-fpa-layout.c"
64 #include "features/arm-with-m-vfp-d16.c"
65 #include "features/arm-with-iwmmxt.c"
66 #include "features/arm-with-vfpv2.c"
67 #include "features/arm-with-vfpv3.c"
68 #include "features/arm-with-neon.c"
72 /* Macros for setting and testing a bit in a minimal symbol that marks
73 it as Thumb function. The MSB of the minimal symbol's "info" field
74 is used for this purpose.
76 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
77 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
79 #define MSYMBOL_SET_SPECIAL(msym) \
80 MSYMBOL_TARGET_FLAG_1 (msym) = 1
82 #define MSYMBOL_IS_SPECIAL(msym) \
83 MSYMBOL_TARGET_FLAG_1 (msym)
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data *arm_objfile_data_key;
88 struct arm_mapping_symbol
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
94 DEF_VEC_O(arm_mapping_symbol_s);
96 struct arm_per_objfile
98 VEC(arm_mapping_symbol_s) **section_maps;
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element *setarmcmdlist = NULL;
103 static struct cmd_list_element *showarmcmdlist = NULL;
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *const fp_model_strings[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
119 static const char *current_fp_model = "auto";
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *const arm_abi_strings[] =
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
132 static const char *arm_abi_string = "auto";
134 /* The execution mode to assume. */
135 static const char *const arm_mode_strings[] =
143 static const char *arm_fallback_mode_string = "auto";
144 static const char *arm_force_mode_string = "auto";
146 /* Internal override of the execution mode. -1 means no override,
147 0 means override to ARM mode, 1 means override to Thumb mode.
148 The effect is the same as if arm_force_mode has been set by the
149 user (except the internal override has precedence over a user's
150 arm_force_mode override). */
151 static int arm_override_mode = -1;
153 /* Number of different reg name sets (options). */
154 static int num_disassembly_options;
156 /* The standard register names, and all the valid aliases for them. Note
157 that `fp', `sp' and `pc' are not added in this alias list, because they
158 have been added as builtin user registers in
159 std-regs.c:_initialize_frame_reg. */
164 } arm_register_aliases[] = {
165 /* Basic register numbers. */
182 /* Synonyms (argument and variable registers). */
195 /* Other platform-specific names for r9. */
201 /* Names used by GCC (not listed in the ARM EABI). */
203 /* A special name from the older ATPCS. */
207 static const char *const arm_register_names[] =
208 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
209 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
210 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
211 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
212 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
213 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
214 "fps", "cpsr" }; /* 24 25 */
216 /* Valid register name styles. */
217 static const char **valid_disassembly_styles;
219 /* Disassembly style to use. Default to "std" register names. */
220 static const char *disassembly_style;
222 /* This is used to keep the bfd arch_info in sync with the disassembly
224 static void set_disassembly_style_sfunc(char *, int,
225 struct cmd_list_element *);
226 static void set_disassembly_style (void);
228 static void convert_from_extended (const struct floatformat *, const void *,
230 static void convert_to_extended (const struct floatformat *, void *,
233 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
234 struct regcache *regcache,
235 int regnum, gdb_byte *buf);
236 static void arm_neon_quad_write (struct gdbarch *gdbarch,
237 struct regcache *regcache,
238 int regnum, const gdb_byte *buf);
241 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self,
245 /* get_next_pcs operations. */
246 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = {
247 arm_get_next_pcs_read_memory_unsigned_integer,
248 arm_get_next_pcs_syscall_next_pc,
249 arm_get_next_pcs_addr_bits_remove,
250 arm_get_next_pcs_is_thumb
253 struct arm_prologue_cache
255 /* The stack pointer at the time this frame was created; i.e. the
256 caller's stack pointer when this function was called. It is used
257 to identify this frame. */
260 /* The frame base for this frame is just prev_sp - frame size.
261 FRAMESIZE is the distance from the frame pointer to the
262 initial stack pointer. */
266 /* The register used to hold the frame pointer for this frame. */
269 /* Saved register offsets. */
270 struct trad_frame_saved_reg *saved_regs;
273 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
274 CORE_ADDR prologue_start,
275 CORE_ADDR prologue_end,
276 struct arm_prologue_cache *cache);
278 /* Architecture version for displaced stepping. This effects the behaviour of
279 certain instructions, and really should not be hard-wired. */
281 #define DISPLACED_STEPPING_ARCH_VERSION 5
283 /* Set to true if the 32-bit mode is in use. */
287 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
290 arm_psr_thumb_bit (struct gdbarch *gdbarch)
292 if (gdbarch_tdep (gdbarch)->is_m)
298 /* Determine if the processor is currently executing in Thumb mode. */
301 arm_is_thumb (struct regcache *regcache)
304 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
306 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
308 return (cpsr & t_bit) != 0;
311 /* Determine if FRAME is executing in Thumb mode. */
314 arm_frame_is_thumb (struct frame_info *frame)
317 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
319 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
320 directly (from a signal frame or dummy frame) or by interpreting
321 the saved LR (from a prologue or DWARF frame). So consult it and
322 trust the unwinders. */
323 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
325 return (cpsr & t_bit) != 0;
328 /* Callback for VEC_lower_bound. */
331 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
332 const struct arm_mapping_symbol *rhs)
334 return lhs->value < rhs->value;
337 /* Search for the mapping symbol covering MEMADDR. If one is found,
338 return its type. Otherwise, return 0. If START is non-NULL,
339 set *START to the location of the mapping symbol. */
342 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
344 struct obj_section *sec;
346 /* If there are mapping symbols, consult them. */
347 sec = find_pc_section (memaddr);
350 struct arm_per_objfile *data;
351 VEC(arm_mapping_symbol_s) *map;
352 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
356 data = (struct arm_per_objfile *) objfile_data (sec->objfile,
357 arm_objfile_data_key);
360 map = data->section_maps[sec->the_bfd_section->index];
361 if (!VEC_empty (arm_mapping_symbol_s, map))
363 struct arm_mapping_symbol *map_sym;
365 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
366 arm_compare_mapping_symbols);
368 /* VEC_lower_bound finds the earliest ordered insertion
369 point. If the following symbol starts at this exact
370 address, we use that; otherwise, the preceding
371 mapping symbol covers this address. */
372 if (idx < VEC_length (arm_mapping_symbol_s, map))
374 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
375 if (map_sym->value == map_key.value)
378 *start = map_sym->value + obj_section_addr (sec);
379 return map_sym->type;
385 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
387 *start = map_sym->value + obj_section_addr (sec);
388 return map_sym->type;
397 /* Determine if the program counter specified in MEMADDR is in a Thumb
398 function. This function should be called for addresses unrelated to
399 any executing frame; otherwise, prefer arm_frame_is_thumb. */
402 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
404 struct bound_minimal_symbol sym;
406 struct displaced_step_closure* dsc
407 = get_displaced_step_closure_by_addr(memaddr);
409 /* If checking the mode of displaced instruction in copy area, the mode
410 should be determined by instruction on the original address. */
414 fprintf_unfiltered (gdb_stdlog,
415 "displaced: check mode of %.8lx instead of %.8lx\n",
416 (unsigned long) dsc->insn_addr,
417 (unsigned long) memaddr);
418 memaddr = dsc->insn_addr;
421 /* If bit 0 of the address is set, assume this is a Thumb address. */
422 if (IS_THUMB_ADDR (memaddr))
425 /* Respect internal mode override if active. */
426 if (arm_override_mode != -1)
427 return arm_override_mode;
429 /* If the user wants to override the symbol table, let him. */
430 if (strcmp (arm_force_mode_string, "arm") == 0)
432 if (strcmp (arm_force_mode_string, "thumb") == 0)
435 /* ARM v6-M and v7-M are always in Thumb mode. */
436 if (gdbarch_tdep (gdbarch)->is_m)
439 /* If there are mapping symbols, consult them. */
440 type = arm_find_mapping_symbol (memaddr, NULL);
444 /* Thumb functions have a "special" bit set in minimal symbols. */
445 sym = lookup_minimal_symbol_by_pc (memaddr);
447 return (MSYMBOL_IS_SPECIAL (sym.minsym));
449 /* If the user wants to override the fallback mode, let them. */
450 if (strcmp (arm_fallback_mode_string, "arm") == 0)
452 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
455 /* If we couldn't find any symbol, but we're talking to a running
456 target, then trust the current value of $cpsr. This lets
457 "display/i $pc" always show the correct mode (though if there is
458 a symbol table we will not reach here, so it still may not be
459 displayed in the mode it will be executed). */
460 if (target_has_registers)
461 return arm_frame_is_thumb (get_current_frame ());
463 /* Otherwise we're out of luck; we assume ARM. */
467 /* Remove useless bits from addresses in a running program. */
469 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
471 /* On M-profile devices, do not strip the low bit from EXC_RETURN
472 (the magic exception return address). */
473 if (gdbarch_tdep (gdbarch)->is_m
474 && (val & 0xfffffff0) == 0xfffffff0)
478 return UNMAKE_THUMB_ADDR (val);
480 return (val & 0x03fffffc);
483 /* Return 1 if PC is the start of a compiler helper function which
484 can be safely ignored during prologue skipping. IS_THUMB is true
485 if the function is known to be a Thumb function due to the way it
488 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
490 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
491 struct bound_minimal_symbol msym;
493 msym = lookup_minimal_symbol_by_pc (pc);
494 if (msym.minsym != NULL
495 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
496 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
498 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
500 /* The GNU linker's Thumb call stub to foo is named
502 if (strstr (name, "_from_thumb") != NULL)
505 /* On soft-float targets, __truncdfsf2 is called to convert promoted
506 arguments to their argument types in non-prototyped
508 if (startswith (name, "__truncdfsf2"))
510 if (startswith (name, "__aeabi_d2f"))
513 /* Internal functions related to thread-local storage. */
514 if (startswith (name, "__tls_get_addr"))
516 if (startswith (name, "__aeabi_read_tp"))
521 /* If we run against a stripped glibc, we may be unable to identify
522 special functions by name. Check for one important case,
523 __aeabi_read_tp, by comparing the *code* against the default
524 implementation (this is hand-written ARM assembler in glibc). */
527 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
528 == 0xe3e00a0f /* mov r0, #0xffff0fff */
529 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
530 == 0xe240f01f) /* sub pc, r0, #31 */
537 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
538 the first 16-bit of instruction, and INSN2 is the second 16-bit of
540 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
541 ((bits ((insn1), 0, 3) << 12) \
542 | (bits ((insn1), 10, 10) << 11) \
543 | (bits ((insn2), 12, 14) << 8) \
544 | bits ((insn2), 0, 7))
546 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
547 the 32-bit instruction. */
548 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
549 ((bits ((insn), 16, 19) << 12) \
550 | bits ((insn), 0, 11))
552 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
555 thumb_expand_immediate (unsigned int imm)
557 unsigned int count = imm >> 7;
565 return (imm & 0xff) | ((imm & 0xff) << 16);
567 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
569 return (imm & 0xff) | ((imm & 0xff) << 8)
570 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
573 return (0x80 | (imm & 0x7f)) << (32 - count);
576 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
577 epilogue, 0 otherwise. */
580 thumb_instruction_restores_sp (unsigned short insn)
582 return (insn == 0x46bd /* mov sp, r7 */
583 || (insn & 0xff80) == 0xb000 /* add sp, imm */
584 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
587 /* Analyze a Thumb prologue, looking for a recognizable stack frame
588 and frame pointer. Scan until we encounter a store that could
589 clobber the stack frame unexpectedly, or an unknown instruction.
590 Return the last address which is definitely safe to skip for an
591 initial breakpoint. */
594 thumb_analyze_prologue (struct gdbarch *gdbarch,
595 CORE_ADDR start, CORE_ADDR limit,
596 struct arm_prologue_cache *cache)
598 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
599 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
602 struct pv_area *stack;
603 struct cleanup *back_to;
605 CORE_ADDR unrecognized_pc = 0;
607 for (i = 0; i < 16; i++)
608 regs[i] = pv_register (i, 0);
609 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
610 back_to = make_cleanup_free_pv_area (stack);
612 while (start < limit)
616 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
618 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
623 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
626 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
627 whether to save LR (R14). */
628 mask = (insn & 0xff) | ((insn & 0x100) << 6);
630 /* Calculate offsets of saved R0-R7 and LR. */
631 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
632 if (mask & (1 << regno))
634 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
636 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
639 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
641 offset = (insn & 0x7f) << 2; /* get scaled offset */
642 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
645 else if (thumb_instruction_restores_sp (insn))
647 /* Don't scan past the epilogue. */
650 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
651 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
653 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
654 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
655 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
657 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
658 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
659 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
661 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
662 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
663 && pv_is_constant (regs[bits (insn, 3, 5)]))
664 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
665 regs[bits (insn, 6, 8)]);
666 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
667 && pv_is_constant (regs[bits (insn, 3, 6)]))
669 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
670 int rm = bits (insn, 3, 6);
671 regs[rd] = pv_add (regs[rd], regs[rm]);
673 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
675 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
676 int src_reg = (insn & 0x78) >> 3;
677 regs[dst_reg] = regs[src_reg];
679 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
681 /* Handle stores to the stack. Normally pushes are used,
682 but with GCC -mtpcs-frame, there may be other stores
683 in the prologue to create the frame. */
684 int regno = (insn >> 8) & 0x7;
687 offset = (insn & 0xff) << 2;
688 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
690 if (pv_area_store_would_trash (stack, addr))
693 pv_area_store (stack, addr, 4, regs[regno]);
695 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
697 int rd = bits (insn, 0, 2);
698 int rn = bits (insn, 3, 5);
701 offset = bits (insn, 6, 10) << 2;
702 addr = pv_add_constant (regs[rn], offset);
704 if (pv_area_store_would_trash (stack, addr))
707 pv_area_store (stack, addr, 4, regs[rd]);
709 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
710 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
711 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
712 /* Ignore stores of argument registers to the stack. */
714 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
715 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
716 /* Ignore block loads from the stack, potentially copying
717 parameters from memory. */
719 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
720 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
721 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
722 /* Similarly ignore single loads from the stack. */
724 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
725 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
726 /* Skip register copies, i.e. saves to another register
727 instead of the stack. */
729 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
730 /* Recognize constant loads; even with small stacks these are necessary
732 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
733 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
735 /* Constant pool loads, for the same reason. */
736 unsigned int constant;
739 loc = start + 4 + bits (insn, 0, 7) * 4;
740 constant = read_memory_unsigned_integer (loc, 4, byte_order);
741 regs[bits (insn, 8, 10)] = pv_constant (constant);
743 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
745 unsigned short inst2;
747 inst2 = read_memory_unsigned_integer (start + 2, 2,
748 byte_order_for_code);
750 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
752 /* BL, BLX. Allow some special function calls when
753 skipping the prologue; GCC generates these before
754 storing arguments to the stack. */
756 int j1, j2, imm1, imm2;
758 imm1 = sbits (insn, 0, 10);
759 imm2 = bits (inst2, 0, 10);
760 j1 = bit (inst2, 13);
761 j2 = bit (inst2, 11);
763 offset = ((imm1 << 12) + (imm2 << 1));
764 offset ^= ((!j2) << 22) | ((!j1) << 23);
766 nextpc = start + 4 + offset;
767 /* For BLX make sure to clear the low bits. */
768 if (bit (inst2, 12) == 0)
769 nextpc = nextpc & 0xfffffffc;
771 if (!skip_prologue_function (gdbarch, nextpc,
772 bit (inst2, 12) != 0))
776 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
778 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
780 pv_t addr = regs[bits (insn, 0, 3)];
783 if (pv_area_store_would_trash (stack, addr))
786 /* Calculate offsets of saved registers. */
787 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
788 if (inst2 & (1 << regno))
790 addr = pv_add_constant (addr, -4);
791 pv_area_store (stack, addr, 4, regs[regno]);
795 regs[bits (insn, 0, 3)] = addr;
798 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
800 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
802 int regno1 = bits (inst2, 12, 15);
803 int regno2 = bits (inst2, 8, 11);
804 pv_t addr = regs[bits (insn, 0, 3)];
806 offset = inst2 & 0xff;
808 addr = pv_add_constant (addr, offset);
810 addr = pv_add_constant (addr, -offset);
812 if (pv_area_store_would_trash (stack, addr))
815 pv_area_store (stack, addr, 4, regs[regno1]);
816 pv_area_store (stack, pv_add_constant (addr, 4),
820 regs[bits (insn, 0, 3)] = addr;
823 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
824 && (inst2 & 0x0c00) == 0x0c00
825 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
827 int regno = bits (inst2, 12, 15);
828 pv_t addr = regs[bits (insn, 0, 3)];
830 offset = inst2 & 0xff;
832 addr = pv_add_constant (addr, offset);
834 addr = pv_add_constant (addr, -offset);
836 if (pv_area_store_would_trash (stack, addr))
839 pv_area_store (stack, addr, 4, regs[regno]);
842 regs[bits (insn, 0, 3)] = addr;
845 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
846 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
848 int regno = bits (inst2, 12, 15);
851 offset = inst2 & 0xfff;
852 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
854 if (pv_area_store_would_trash (stack, addr))
857 pv_area_store (stack, addr, 4, regs[regno]);
860 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
861 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
862 /* Ignore stores of argument registers to the stack. */
865 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
866 && (inst2 & 0x0d00) == 0x0c00
867 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
868 /* Ignore stores of argument registers to the stack. */
871 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
873 && (inst2 & 0x8000) == 0x0000
874 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
875 /* Ignore block loads from the stack, potentially copying
876 parameters from memory. */
879 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
881 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
882 /* Similarly ignore dual loads from the stack. */
885 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
886 && (inst2 & 0x0d00) == 0x0c00
887 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
888 /* Similarly ignore single loads from the stack. */
891 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
892 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
893 /* Similarly ignore single loads from the stack. */
896 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
897 && (inst2 & 0x8000) == 0x0000)
899 unsigned int imm = ((bits (insn, 10, 10) << 11)
900 | (bits (inst2, 12, 14) << 8)
901 | bits (inst2, 0, 7));
903 regs[bits (inst2, 8, 11)]
904 = pv_add_constant (regs[bits (insn, 0, 3)],
905 thumb_expand_immediate (imm));
908 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
909 && (inst2 & 0x8000) == 0x0000)
911 unsigned int imm = ((bits (insn, 10, 10) << 11)
912 | (bits (inst2, 12, 14) << 8)
913 | bits (inst2, 0, 7));
915 regs[bits (inst2, 8, 11)]
916 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
919 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
920 && (inst2 & 0x8000) == 0x0000)
922 unsigned int imm = ((bits (insn, 10, 10) << 11)
923 | (bits (inst2, 12, 14) << 8)
924 | bits (inst2, 0, 7));
926 regs[bits (inst2, 8, 11)]
927 = pv_add_constant (regs[bits (insn, 0, 3)],
928 - (CORE_ADDR) thumb_expand_immediate (imm));
931 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
932 && (inst2 & 0x8000) == 0x0000)
934 unsigned int imm = ((bits (insn, 10, 10) << 11)
935 | (bits (inst2, 12, 14) << 8)
936 | bits (inst2, 0, 7));
938 regs[bits (inst2, 8, 11)]
939 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
942 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
944 unsigned int imm = ((bits (insn, 10, 10) << 11)
945 | (bits (inst2, 12, 14) << 8)
946 | bits (inst2, 0, 7));
948 regs[bits (inst2, 8, 11)]
949 = pv_constant (thumb_expand_immediate (imm));
952 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
955 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
957 regs[bits (inst2, 8, 11)] = pv_constant (imm);
960 else if (insn == 0xea5f /* mov.w Rd,Rm */
961 && (inst2 & 0xf0f0) == 0)
963 int dst_reg = (inst2 & 0x0f00) >> 8;
964 int src_reg = inst2 & 0xf;
965 regs[dst_reg] = regs[src_reg];
968 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
970 /* Constant pool loads. */
971 unsigned int constant;
974 offset = bits (inst2, 0, 11);
976 loc = start + 4 + offset;
978 loc = start + 4 - offset;
980 constant = read_memory_unsigned_integer (loc, 4, byte_order);
981 regs[bits (inst2, 12, 15)] = pv_constant (constant);
984 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
986 /* Constant pool loads. */
987 unsigned int constant;
990 offset = bits (inst2, 0, 7) << 2;
992 loc = start + 4 + offset;
994 loc = start + 4 - offset;
996 constant = read_memory_unsigned_integer (loc, 4, byte_order);
997 regs[bits (inst2, 12, 15)] = pv_constant (constant);
999 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1000 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1003 else if (thumb2_instruction_changes_pc (insn, inst2))
1005 /* Don't scan past anything that might change control flow. */
1010 /* The optimizer might shove anything into the prologue,
1011 so we just skip what we don't recognize. */
1012 unrecognized_pc = start;
1017 else if (thumb_instruction_changes_pc (insn))
1019 /* Don't scan past anything that might change control flow. */
1024 /* The optimizer might shove anything into the prologue,
1025 so we just skip what we don't recognize. */
1026 unrecognized_pc = start;
1033 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1034 paddress (gdbarch, start));
1036 if (unrecognized_pc == 0)
1037 unrecognized_pc = start;
1041 do_cleanups (back_to);
1042 return unrecognized_pc;
1045 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1047 /* Frame pointer is fp. Frame size is constant. */
1048 cache->framereg = ARM_FP_REGNUM;
1049 cache->framesize = -regs[ARM_FP_REGNUM].k;
1051 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1053 /* Frame pointer is r7. Frame size is constant. */
1054 cache->framereg = THUMB_FP_REGNUM;
1055 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1059 /* Try the stack pointer... this is a bit desperate. */
1060 cache->framereg = ARM_SP_REGNUM;
1061 cache->framesize = -regs[ARM_SP_REGNUM].k;
1064 for (i = 0; i < 16; i++)
1065 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1066 cache->saved_regs[i].addr = offset;
1068 do_cleanups (back_to);
1069 return unrecognized_pc;
1073 /* Try to analyze the instructions starting from PC, which load symbol
1074 __stack_chk_guard. Return the address of instruction after loading this
1075 symbol, set the dest register number to *BASEREG, and set the size of
1076 instructions for loading symbol in OFFSET. Return 0 if instructions are
1080 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1081 unsigned int *destreg, int *offset)
1083 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1084 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1085 unsigned int low, high, address;
1090 unsigned short insn1
1091 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1093 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1095 *destreg = bits (insn1, 8, 10);
1097 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1098 address = read_memory_unsigned_integer (address, 4,
1099 byte_order_for_code);
1101 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1103 unsigned short insn2
1104 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1106 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1109 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1111 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1113 /* movt Rd, #const */
1114 if ((insn1 & 0xfbc0) == 0xf2c0)
1116 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1117 *destreg = bits (insn2, 8, 11);
1119 address = (high << 16 | low);
1126 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1128 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1130 address = bits (insn, 0, 11) + pc + 8;
1131 address = read_memory_unsigned_integer (address, 4,
1132 byte_order_for_code);
1134 *destreg = bits (insn, 12, 15);
1137 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1139 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1142 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1144 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1146 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1147 *destreg = bits (insn, 12, 15);
1149 address = (high << 16 | low);
1157 /* Try to skip a sequence of instructions used for stack protector. If PC
1158 points to the first instruction of this sequence, return the address of
1159 first instruction after this sequence, otherwise, return original PC.
1161 On arm, this sequence of instructions is composed of mainly three steps,
1162 Step 1: load symbol __stack_chk_guard,
1163 Step 2: load from address of __stack_chk_guard,
1164 Step 3: store it to somewhere else.
1166 Usually, instructions on step 2 and step 3 are the same on various ARM
1167 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1168 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1169 instructions in step 1 vary from different ARM architectures. On ARMv7,
1172 movw Rn, #:lower16:__stack_chk_guard
1173 movt Rn, #:upper16:__stack_chk_guard
1180 .word __stack_chk_guard
1182 Since ldr/str is a very popular instruction, we can't use them as
1183 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1184 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1185 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1188 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1190 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1191 unsigned int basereg;
1192 struct bound_minimal_symbol stack_chk_guard;
1194 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1197 /* Try to parse the instructions in Step 1. */
1198 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1203 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1204 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1205 Otherwise, this sequence cannot be for stack protector. */
1206 if (stack_chk_guard.minsym == NULL
1207 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1212 unsigned int destreg;
1214 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1216 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1217 if ((insn & 0xf800) != 0x6800)
1219 if (bits (insn, 3, 5) != basereg)
1221 destreg = bits (insn, 0, 2);
1223 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1224 byte_order_for_code);
1225 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1226 if ((insn & 0xf800) != 0x6000)
1228 if (destreg != bits (insn, 0, 2))
1233 unsigned int destreg;
1235 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1237 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1238 if ((insn & 0x0e500000) != 0x04100000)
1240 if (bits (insn, 16, 19) != basereg)
1242 destreg = bits (insn, 12, 15);
1243 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1244 insn = read_memory_unsigned_integer (pc + offset + 4,
1245 4, byte_order_for_code);
1246 if ((insn & 0x0e500000) != 0x04000000)
1248 if (bits (insn, 12, 15) != destreg)
1251 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1254 return pc + offset + 4;
1256 return pc + offset + 8;
1259 /* Advance the PC across any function entry prologue instructions to
1260 reach some "real" code.
1262 The APCS (ARM Procedure Call Standard) defines the following
1266 [stmfd sp!, {a1,a2,a3,a4}]
1267 stmfd sp!, {...,fp,ip,lr,pc}
1268 [stfe f7, [sp, #-12]!]
1269 [stfe f6, [sp, #-12]!]
1270 [stfe f5, [sp, #-12]!]
1271 [stfe f4, [sp, #-12]!]
1272 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1275 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1277 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1279 CORE_ADDR func_addr, limit_pc;
1281 /* See if we can determine the end of the prologue via the symbol table.
1282 If so, then return either PC, or the PC after the prologue, whichever
1284 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1286 CORE_ADDR post_prologue_pc
1287 = skip_prologue_using_sal (gdbarch, func_addr);
1288 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1290 if (post_prologue_pc)
1292 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1295 /* GCC always emits a line note before the prologue and another
1296 one after, even if the two are at the same address or on the
1297 same line. Take advantage of this so that we do not need to
1298 know every instruction that might appear in the prologue. We
1299 will have producer information for most binaries; if it is
1300 missing (e.g. for -gstabs), assuming the GNU tools. */
1301 if (post_prologue_pc
1303 || COMPUNIT_PRODUCER (cust) == NULL
1304 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1305 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1306 return post_prologue_pc;
1308 if (post_prologue_pc != 0)
1310 CORE_ADDR analyzed_limit;
1312 /* For non-GCC compilers, make sure the entire line is an
1313 acceptable prologue; GDB will round this function's
1314 return value up to the end of the following line so we
1315 can not skip just part of a line (and we do not want to).
1317 RealView does not treat the prologue specially, but does
1318 associate prologue code with the opening brace; so this
1319 lets us skip the first line if we think it is the opening
1321 if (arm_pc_is_thumb (gdbarch, func_addr))
1322 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1323 post_prologue_pc, NULL);
1325 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1326 post_prologue_pc, NULL);
1328 if (analyzed_limit != post_prologue_pc)
1331 return post_prologue_pc;
1335 /* Can't determine prologue from the symbol table, need to examine
1338 /* Find an upper limit on the function prologue using the debug
1339 information. If the debug information could not be used to provide
1340 that bound, then use an arbitrary large number as the upper bound. */
1341 /* Like arm_scan_prologue, stop no later than pc + 64. */
1342 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1344 limit_pc = pc + 64; /* Magic. */
1347 /* Check if this is Thumb code. */
1348 if (arm_pc_is_thumb (gdbarch, pc))
1349 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1351 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1355 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1356 This function decodes a Thumb function prologue to determine:
1357 1) the size of the stack frame
1358 2) which registers are saved on it
1359 3) the offsets of saved regs
1360 4) the offset from the stack pointer to the frame pointer
1362 A typical Thumb function prologue would create this stack frame
1363 (offsets relative to FP)
1364 old SP -> 24 stack parameters
1367 R7 -> 0 local variables (16 bytes)
1368 SP -> -12 additional stack space (12 bytes)
1369 The frame size would thus be 36 bytes, and the frame offset would be
1370 12 bytes. The frame register is R7.
1372 The comments for thumb_skip_prolog() describe the algorithm we use
1373 to detect the end of the prolog. */
1377 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1378 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1380 CORE_ADDR prologue_start;
1381 CORE_ADDR prologue_end;
1383 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1386 /* See comment in arm_scan_prologue for an explanation of
1388 if (prologue_end > prologue_start + 64)
1390 prologue_end = prologue_start + 64;
1394 /* We're in the boondocks: we have no idea where the start of the
1398 prologue_end = min (prologue_end, prev_pc);
1400 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1403 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1407 arm_instruction_restores_sp (unsigned int insn)
1409 if (bits (insn, 28, 31) != INST_NV)
1411 if ((insn & 0x0df0f000) == 0x0080d000
1412 /* ADD SP (register or immediate). */
1413 || (insn & 0x0df0f000) == 0x0040d000
1414 /* SUB SP (register or immediate). */
1415 || (insn & 0x0ffffff0) == 0x01a0d000
1417 || (insn & 0x0fff0000) == 0x08bd0000
1419 || (insn & 0x0fff0000) == 0x049d0000)
1420 /* POP of a single register. */
1427 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1428 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1429 fill it in. Return the first address not recognized as a prologue
1432 We recognize all the instructions typically found in ARM prologues,
1433 plus harmless instructions which can be skipped (either for analysis
1434 purposes, or a more restrictive set that can be skipped when finding
1435 the end of the prologue). */
1438 arm_analyze_prologue (struct gdbarch *gdbarch,
1439 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1440 struct arm_prologue_cache *cache)
1442 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1443 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1445 CORE_ADDR offset, current_pc;
1446 pv_t regs[ARM_FPS_REGNUM];
1447 struct pv_area *stack;
1448 struct cleanup *back_to;
1449 CORE_ADDR unrecognized_pc = 0;
1451 /* Search the prologue looking for instructions that set up the
1452 frame pointer, adjust the stack pointer, and save registers.
1454 Be careful, however, and if it doesn't look like a prologue,
1455 don't try to scan it. If, for instance, a frameless function
1456 begins with stmfd sp!, then we will tell ourselves there is
1457 a frame, which will confuse stack traceback, as well as "finish"
1458 and other operations that rely on a knowledge of the stack
1461 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1462 regs[regno] = pv_register (regno, 0);
1463 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1464 back_to = make_cleanup_free_pv_area (stack);
1466 for (current_pc = prologue_start;
1467 current_pc < prologue_end;
1471 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1473 if (insn == 0xe1a0c00d) /* mov ip, sp */
1475 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1478 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1479 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1481 unsigned imm = insn & 0xff; /* immediate value */
1482 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1483 int rd = bits (insn, 12, 15);
1484 imm = (imm >> rot) | (imm << (32 - rot));
1485 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1488 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1489 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1491 unsigned imm = insn & 0xff; /* immediate value */
1492 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1493 int rd = bits (insn, 12, 15);
1494 imm = (imm >> rot) | (imm << (32 - rot));
1495 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1498 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1501 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1503 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1504 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1505 regs[bits (insn, 12, 15)]);
1508 else if ((insn & 0xffff0000) == 0xe92d0000)
1509 /* stmfd sp!, {..., fp, ip, lr, pc}
1511 stmfd sp!, {a1, a2, a3, a4} */
1513 int mask = insn & 0xffff;
1515 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1518 /* Calculate offsets of saved registers. */
1519 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1520 if (mask & (1 << regno))
1523 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1524 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1527 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1528 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1529 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1531 /* No need to add this to saved_regs -- it's just an arg reg. */
1534 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1535 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1536 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1538 /* No need to add this to saved_regs -- it's just an arg reg. */
1541 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1543 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1545 /* No need to add this to saved_regs -- it's just arg regs. */
1548 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1550 unsigned imm = insn & 0xff; /* immediate value */
1551 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1552 imm = (imm >> rot) | (imm << (32 - rot));
1553 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1555 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1557 unsigned imm = insn & 0xff; /* immediate value */
1558 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1559 imm = (imm >> rot) | (imm << (32 - rot));
1560 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1562 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1564 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1566 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1569 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1570 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1571 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1573 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1575 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1577 int n_saved_fp_regs;
1578 unsigned int fp_start_reg, fp_bound_reg;
1580 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1583 if ((insn & 0x800) == 0x800) /* N0 is set */
1585 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1586 n_saved_fp_regs = 3;
1588 n_saved_fp_regs = 1;
1592 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1593 n_saved_fp_regs = 2;
1595 n_saved_fp_regs = 4;
1598 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1599 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1600 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1602 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1603 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1604 regs[fp_start_reg++]);
1607 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1609 /* Allow some special function calls when skipping the
1610 prologue; GCC generates these before storing arguments to
1612 CORE_ADDR dest = BranchDest (current_pc, insn);
1614 if (skip_prologue_function (gdbarch, dest, 0))
1619 else if ((insn & 0xf0000000) != 0xe0000000)
1620 break; /* Condition not true, exit early. */
1621 else if (arm_instruction_changes_pc (insn))
1622 /* Don't scan past anything that might change control flow. */
1624 else if (arm_instruction_restores_sp (insn))
1626 /* Don't scan past the epilogue. */
1629 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1630 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1631 /* Ignore block loads from the stack, potentially copying
1632 parameters from memory. */
1634 else if ((insn & 0xfc500000) == 0xe4100000
1635 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1636 /* Similarly ignore single loads from the stack. */
1638 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1639 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1640 register instead of the stack. */
1644 /* The optimizer might shove anything into the prologue, if
1645 we build up cache (cache != NULL) from scanning prologue,
1646 we just skip what we don't recognize and scan further to
1647 make cache as complete as possible. However, if we skip
1648 prologue, we'll stop immediately on unrecognized
1650 unrecognized_pc = current_pc;
1658 if (unrecognized_pc == 0)
1659 unrecognized_pc = current_pc;
1663 int framereg, framesize;
1665 /* The frame size is just the distance from the frame register
1666 to the original stack pointer. */
1667 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1669 /* Frame pointer is fp. */
1670 framereg = ARM_FP_REGNUM;
1671 framesize = -regs[ARM_FP_REGNUM].k;
1675 /* Try the stack pointer... this is a bit desperate. */
1676 framereg = ARM_SP_REGNUM;
1677 framesize = -regs[ARM_SP_REGNUM].k;
1680 cache->framereg = framereg;
1681 cache->framesize = framesize;
1683 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1684 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1685 cache->saved_regs[regno].addr = offset;
1689 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1690 paddress (gdbarch, unrecognized_pc));
1692 do_cleanups (back_to);
1693 return unrecognized_pc;
1697 arm_scan_prologue (struct frame_info *this_frame,
1698 struct arm_prologue_cache *cache)
1700 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1701 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1703 CORE_ADDR prologue_start, prologue_end, current_pc;
1704 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1705 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1706 pv_t regs[ARM_FPS_REGNUM];
1707 struct pv_area *stack;
1708 struct cleanup *back_to;
1711 /* Assume there is no frame until proven otherwise. */
1712 cache->framereg = ARM_SP_REGNUM;
1713 cache->framesize = 0;
1715 /* Check for Thumb prologue. */
1716 if (arm_frame_is_thumb (this_frame))
1718 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1722 /* Find the function prologue. If we can't find the function in
1723 the symbol table, peek in the stack frame to find the PC. */
1724 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1727 /* One way to find the end of the prologue (which works well
1728 for unoptimized code) is to do the following:
1730 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1733 prologue_end = prev_pc;
1734 else if (sal.end < prologue_end)
1735 prologue_end = sal.end;
1737 This mechanism is very accurate so long as the optimizer
1738 doesn't move any instructions from the function body into the
1739 prologue. If this happens, sal.end will be the last
1740 instruction in the first hunk of prologue code just before
1741 the first instruction that the scheduler has moved from
1742 the body to the prologue.
1744 In order to make sure that we scan all of the prologue
1745 instructions, we use a slightly less accurate mechanism which
1746 may scan more than necessary. To help compensate for this
1747 lack of accuracy, the prologue scanning loop below contains
1748 several clauses which'll cause the loop to terminate early if
1749 an implausible prologue instruction is encountered.
1755 is a suitable endpoint since it accounts for the largest
1756 possible prologue plus up to five instructions inserted by
1759 if (prologue_end > prologue_start + 64)
1761 prologue_end = prologue_start + 64; /* See above. */
1766 /* We have no symbol information. Our only option is to assume this
1767 function has a standard stack frame and the normal frame register.
1768 Then, we can find the value of our frame pointer on entrance to
1769 the callee (or at the present moment if this is the innermost frame).
1770 The value stored there should be the address of the stmfd + 8. */
1771 CORE_ADDR frame_loc;
1772 LONGEST return_value;
1774 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1775 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1779 prologue_start = gdbarch_addr_bits_remove
1780 (gdbarch, return_value) - 8;
1781 prologue_end = prologue_start + 64; /* See above. */
1785 if (prev_pc < prologue_end)
1786 prologue_end = prev_pc;
1788 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1791 static struct arm_prologue_cache *
1792 arm_make_prologue_cache (struct frame_info *this_frame)
1795 struct arm_prologue_cache *cache;
1796 CORE_ADDR unwound_fp;
1798 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1799 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1801 arm_scan_prologue (this_frame, cache);
1803 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1804 if (unwound_fp == 0)
1807 cache->prev_sp = unwound_fp + cache->framesize;
1809 /* Calculate actual addresses of saved registers using offsets
1810 determined by arm_scan_prologue. */
1811 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1812 if (trad_frame_addr_p (cache->saved_regs, reg))
1813 cache->saved_regs[reg].addr += cache->prev_sp;
1818 /* Implementation of the stop_reason hook for arm_prologue frames. */
1820 static enum unwind_stop_reason
1821 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
1824 struct arm_prologue_cache *cache;
1827 if (*this_cache == NULL)
1828 *this_cache = arm_make_prologue_cache (this_frame);
1829 cache = (struct arm_prologue_cache *) *this_cache;
1831 /* This is meant to halt the backtrace at "_start". */
1832 pc = get_frame_pc (this_frame);
1833 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1834 return UNWIND_OUTERMOST;
1836 /* If we've hit a wall, stop. */
1837 if (cache->prev_sp == 0)
1838 return UNWIND_OUTERMOST;
1840 return UNWIND_NO_REASON;
1843 /* Our frame ID for a normal frame is the current function's starting PC
1844 and the caller's SP when we were called. */
1847 arm_prologue_this_id (struct frame_info *this_frame,
1849 struct frame_id *this_id)
1851 struct arm_prologue_cache *cache;
1855 if (*this_cache == NULL)
1856 *this_cache = arm_make_prologue_cache (this_frame);
1857 cache = (struct arm_prologue_cache *) *this_cache;
1859 /* Use function start address as part of the frame ID. If we cannot
1860 identify the start address (due to missing symbol information),
1861 fall back to just using the current PC. */
1862 pc = get_frame_pc (this_frame);
1863 func = get_frame_func (this_frame);
1867 id = frame_id_build (cache->prev_sp, func);
1871 static struct value *
1872 arm_prologue_prev_register (struct frame_info *this_frame,
1876 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1877 struct arm_prologue_cache *cache;
1879 if (*this_cache == NULL)
1880 *this_cache = arm_make_prologue_cache (this_frame);
1881 cache = (struct arm_prologue_cache *) *this_cache;
1883 /* If we are asked to unwind the PC, then we need to return the LR
1884 instead. The prologue may save PC, but it will point into this
1885 frame's prologue, not the next frame's resume location. Also
1886 strip the saved T bit. A valid LR may have the low bit set, but
1887 a valid PC never does. */
1888 if (prev_regnum == ARM_PC_REGNUM)
1892 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1893 return frame_unwind_got_constant (this_frame, prev_regnum,
1894 arm_addr_bits_remove (gdbarch, lr));
1897 /* SP is generally not saved to the stack, but this frame is
1898 identified by the next frame's stack pointer at the time of the call.
1899 The value was already reconstructed into PREV_SP. */
1900 if (prev_regnum == ARM_SP_REGNUM)
1901 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1903 /* The CPSR may have been changed by the call instruction and by the
1904 called function. The only bit we can reconstruct is the T bit,
1905 by checking the low bit of LR as of the call. This is a reliable
1906 indicator of Thumb-ness except for some ARM v4T pre-interworking
1907 Thumb code, which could get away with a clear low bit as long as
1908 the called function did not use bx. Guess that all other
1909 bits are unchanged; the condition flags are presumably lost,
1910 but the processor status is likely valid. */
1911 if (prev_regnum == ARM_PS_REGNUM)
1914 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
1916 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1917 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1918 if (IS_THUMB_ADDR (lr))
1922 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1925 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1929 struct frame_unwind arm_prologue_unwind = {
1931 arm_prologue_unwind_stop_reason,
1932 arm_prologue_this_id,
1933 arm_prologue_prev_register,
1935 default_frame_sniffer
1938 /* Maintain a list of ARM exception table entries per objfile, similar to the
1939 list of mapping symbols. We only cache entries for standard ARM-defined
1940 personality routines; the cache will contain only the frame unwinding
1941 instructions associated with the entry (not the descriptors). */
1943 static const struct objfile_data *arm_exidx_data_key;
1945 struct arm_exidx_entry
1950 typedef struct arm_exidx_entry arm_exidx_entry_s;
1951 DEF_VEC_O(arm_exidx_entry_s);
1953 struct arm_exidx_data
1955 VEC(arm_exidx_entry_s) **section_maps;
1959 arm_exidx_data_free (struct objfile *objfile, void *arg)
1961 struct arm_exidx_data *data = (struct arm_exidx_data *) arg;
1964 for (i = 0; i < objfile->obfd->section_count; i++)
1965 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
1969 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
1970 const struct arm_exidx_entry *rhs)
1972 return lhs->addr < rhs->addr;
1975 static struct obj_section *
1976 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
1978 struct obj_section *osect;
1980 ALL_OBJFILE_OSECTIONS (objfile, osect)
1981 if (bfd_get_section_flags (objfile->obfd,
1982 osect->the_bfd_section) & SEC_ALLOC)
1984 bfd_vma start, size;
1985 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
1986 size = bfd_get_section_size (osect->the_bfd_section);
1988 if (start <= vma && vma < start + size)
1995 /* Parse contents of exception table and exception index sections
1996 of OBJFILE, and fill in the exception table entry cache.
1998 For each entry that refers to a standard ARM-defined personality
1999 routine, extract the frame unwinding instructions (from either
2000 the index or the table section). The unwinding instructions
2002 - extracting them from the rest of the table data
2003 - converting to host endianness
2004 - appending the implicit 0xb0 ("Finish") code
2006 The extracted and normalized instructions are stored for later
2007 retrieval by the arm_find_exidx_entry routine. */
2010 arm_exidx_new_objfile (struct objfile *objfile)
2012 struct cleanup *cleanups;
2013 struct arm_exidx_data *data;
2014 asection *exidx, *extab;
2015 bfd_vma exidx_vma = 0, extab_vma = 0;
2016 bfd_size_type exidx_size = 0, extab_size = 0;
2017 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2020 /* If we've already touched this file, do nothing. */
2021 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2023 cleanups = make_cleanup (null_cleanup, NULL);
2025 /* Read contents of exception table and index. */
2026 exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
2029 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2030 exidx_size = bfd_get_section_size (exidx);
2031 exidx_data = (gdb_byte *) xmalloc (exidx_size);
2032 make_cleanup (xfree, exidx_data);
2034 if (!bfd_get_section_contents (objfile->obfd, exidx,
2035 exidx_data, 0, exidx_size))
2037 do_cleanups (cleanups);
2042 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2045 extab_vma = bfd_section_vma (objfile->obfd, extab);
2046 extab_size = bfd_get_section_size (extab);
2047 extab_data = (gdb_byte *) xmalloc (extab_size);
2048 make_cleanup (xfree, extab_data);
2050 if (!bfd_get_section_contents (objfile->obfd, extab,
2051 extab_data, 0, extab_size))
2053 do_cleanups (cleanups);
2058 /* Allocate exception table data structure. */
2059 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2060 set_objfile_data (objfile, arm_exidx_data_key, data);
2061 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2062 objfile->obfd->section_count,
2063 VEC(arm_exidx_entry_s) *);
2065 /* Fill in exception table. */
2066 for (i = 0; i < exidx_size / 8; i++)
2068 struct arm_exidx_entry new_exidx_entry;
2069 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2070 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2071 bfd_vma addr = 0, word = 0;
2072 int n_bytes = 0, n_words = 0;
2073 struct obj_section *sec;
2074 gdb_byte *entry = NULL;
2076 /* Extract address of start of function. */
2077 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2078 idx += exidx_vma + i * 8;
2080 /* Find section containing function and compute section offset. */
2081 sec = arm_obj_section_from_vma (objfile, idx);
2084 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2086 /* Determine address of exception table entry. */
2089 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2091 else if ((val & 0xff000000) == 0x80000000)
2093 /* Exception table entry embedded in .ARM.exidx
2094 -- must be short form. */
2098 else if (!(val & 0x80000000))
2100 /* Exception table entry in .ARM.extab. */
2101 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2102 addr += exidx_vma + i * 8 + 4;
2104 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2106 word = bfd_h_get_32 (objfile->obfd,
2107 extab_data + addr - extab_vma);
2110 if ((word & 0xff000000) == 0x80000000)
2115 else if ((word & 0xff000000) == 0x81000000
2116 || (word & 0xff000000) == 0x82000000)
2120 n_words = ((word >> 16) & 0xff);
2122 else if (!(word & 0x80000000))
2125 struct obj_section *pers_sec;
2126 int gnu_personality = 0;
2128 /* Custom personality routine. */
2129 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2130 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2132 /* Check whether we've got one of the variants of the
2133 GNU personality routines. */
2134 pers_sec = arm_obj_section_from_vma (objfile, pers);
2137 static const char *personality[] =
2139 "__gcc_personality_v0",
2140 "__gxx_personality_v0",
2141 "__gcj_personality_v0",
2142 "__gnu_objc_personality_v0",
2146 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2149 for (k = 0; personality[k]; k++)
2150 if (lookup_minimal_symbol_by_pc_name
2151 (pc, personality[k], objfile))
2153 gnu_personality = 1;
2158 /* If so, the next word contains a word count in the high
2159 byte, followed by the same unwind instructions as the
2160 pre-defined forms. */
2162 && addr + 4 <= extab_vma + extab_size)
2164 word = bfd_h_get_32 (objfile->obfd,
2165 extab_data + addr - extab_vma);
2168 n_words = ((word >> 24) & 0xff);
2174 /* Sanity check address. */
2176 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2177 n_words = n_bytes = 0;
2179 /* The unwind instructions reside in WORD (only the N_BYTES least
2180 significant bytes are valid), followed by N_WORDS words in the
2181 extab section starting at ADDR. */
2182 if (n_bytes || n_words)
2185 = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack,
2186 n_bytes + n_words * 4 + 1);
2189 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2193 word = bfd_h_get_32 (objfile->obfd,
2194 extab_data + addr - extab_vma);
2197 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2198 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2199 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2200 *p++ = (gdb_byte) (word & 0xff);
2203 /* Implied "Finish" to terminate the list. */
2207 /* Push entry onto vector. They are guaranteed to always
2208 appear in order of increasing addresses. */
2209 new_exidx_entry.addr = idx;
2210 new_exidx_entry.entry = entry;
2211 VEC_safe_push (arm_exidx_entry_s,
2212 data->section_maps[sec->the_bfd_section->index],
2216 do_cleanups (cleanups);
2219 /* Search for the exception table entry covering MEMADDR. If one is found,
2220 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2221 set *START to the start of the region covered by this entry. */
2224 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2226 struct obj_section *sec;
2228 sec = find_pc_section (memaddr);
2231 struct arm_exidx_data *data;
2232 VEC(arm_exidx_entry_s) *map;
2233 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2236 data = ((struct arm_exidx_data *)
2237 objfile_data (sec->objfile, arm_exidx_data_key));
2240 map = data->section_maps[sec->the_bfd_section->index];
2241 if (!VEC_empty (arm_exidx_entry_s, map))
2243 struct arm_exidx_entry *map_sym;
2245 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2246 arm_compare_exidx_entries);
2248 /* VEC_lower_bound finds the earliest ordered insertion
2249 point. If the following symbol starts at this exact
2250 address, we use that; otherwise, the preceding
2251 exception table entry covers this address. */
2252 if (idx < VEC_length (arm_exidx_entry_s, map))
2254 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2255 if (map_sym->addr == map_key.addr)
2258 *start = map_sym->addr + obj_section_addr (sec);
2259 return map_sym->entry;
2265 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2267 *start = map_sym->addr + obj_section_addr (sec);
2268 return map_sym->entry;
2277 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2278 instruction list from the ARM exception table entry ENTRY, allocate and
2279 return a prologue cache structure describing how to unwind this frame.
2281 Return NULL if the unwinding instruction list contains a "spare",
2282 "reserved" or "refuse to unwind" instruction as defined in section
2283 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2284 for the ARM Architecture" document. */
2286 static struct arm_prologue_cache *
2287 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2292 struct arm_prologue_cache *cache;
2293 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2294 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2300 /* Whenever we reload SP, we actually have to retrieve its
2301 actual value in the current frame. */
2304 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2306 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2307 vsp = get_frame_register_unsigned (this_frame, reg);
2311 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2312 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2318 /* Decode next unwind instruction. */
2321 if ((insn & 0xc0) == 0)
2323 int offset = insn & 0x3f;
2324 vsp += (offset << 2) + 4;
2326 else if ((insn & 0xc0) == 0x40)
2328 int offset = insn & 0x3f;
2329 vsp -= (offset << 2) + 4;
2331 else if ((insn & 0xf0) == 0x80)
2333 int mask = ((insn & 0xf) << 8) | *entry++;
2336 /* The special case of an all-zero mask identifies
2337 "Refuse to unwind". We return NULL to fall back
2338 to the prologue analyzer. */
2342 /* Pop registers r4..r15 under mask. */
2343 for (i = 0; i < 12; i++)
2344 if (mask & (1 << i))
2346 cache->saved_regs[4 + i].addr = vsp;
2350 /* Special-case popping SP -- we need to reload vsp. */
2351 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2354 else if ((insn & 0xf0) == 0x90)
2356 int reg = insn & 0xf;
2358 /* Reserved cases. */
2359 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2362 /* Set SP from another register and mark VSP for reload. */
2363 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2366 else if ((insn & 0xf0) == 0xa0)
2368 int count = insn & 0x7;
2369 int pop_lr = (insn & 0x8) != 0;
2372 /* Pop r4..r[4+count]. */
2373 for (i = 0; i <= count; i++)
2375 cache->saved_regs[4 + i].addr = vsp;
2379 /* If indicated by flag, pop LR as well. */
2382 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2386 else if (insn == 0xb0)
2388 /* We could only have updated PC by popping into it; if so, it
2389 will show up as address. Otherwise, copy LR into PC. */
2390 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2391 cache->saved_regs[ARM_PC_REGNUM]
2392 = cache->saved_regs[ARM_LR_REGNUM];
2397 else if (insn == 0xb1)
2399 int mask = *entry++;
2402 /* All-zero mask and mask >= 16 is "spare". */
2403 if (mask == 0 || mask >= 16)
2406 /* Pop r0..r3 under mask. */
2407 for (i = 0; i < 4; i++)
2408 if (mask & (1 << i))
2410 cache->saved_regs[i].addr = vsp;
2414 else if (insn == 0xb2)
2416 ULONGEST offset = 0;
2421 offset |= (*entry & 0x7f) << shift;
2424 while (*entry++ & 0x80);
2426 vsp += 0x204 + (offset << 2);
2428 else if (insn == 0xb3)
2430 int start = *entry >> 4;
2431 int count = (*entry++) & 0xf;
2434 /* Only registers D0..D15 are valid here. */
2435 if (start + count >= 16)
2438 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2439 for (i = 0; i <= count; i++)
2441 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2445 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2448 else if ((insn & 0xf8) == 0xb8)
2450 int count = insn & 0x7;
2453 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2454 for (i = 0; i <= count; i++)
2456 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2460 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2463 else if (insn == 0xc6)
2465 int start = *entry >> 4;
2466 int count = (*entry++) & 0xf;
2469 /* Only registers WR0..WR15 are valid. */
2470 if (start + count >= 16)
2473 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2474 for (i = 0; i <= count; i++)
2476 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2480 else if (insn == 0xc7)
2482 int mask = *entry++;
2485 /* All-zero mask and mask >= 16 is "spare". */
2486 if (mask == 0 || mask >= 16)
2489 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2490 for (i = 0; i < 4; i++)
2491 if (mask & (1 << i))
2493 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2497 else if ((insn & 0xf8) == 0xc0)
2499 int count = insn & 0x7;
2502 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2503 for (i = 0; i <= count; i++)
2505 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2509 else if (insn == 0xc8)
2511 int start = *entry >> 4;
2512 int count = (*entry++) & 0xf;
2515 /* Only registers D0..D31 are valid. */
2516 if (start + count >= 16)
2519 /* Pop VFP double-precision registers
2520 D[16+start]..D[16+start+count]. */
2521 for (i = 0; i <= count; i++)
2523 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2527 else if (insn == 0xc9)
2529 int start = *entry >> 4;
2530 int count = (*entry++) & 0xf;
2533 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2534 for (i = 0; i <= count; i++)
2536 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2540 else if ((insn & 0xf8) == 0xd0)
2542 int count = insn & 0x7;
2545 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2546 for (i = 0; i <= count; i++)
2548 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2554 /* Everything else is "spare". */
2559 /* If we restore SP from a register, assume this was the frame register.
2560 Otherwise just fall back to SP as frame register. */
2561 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2562 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2564 cache->framereg = ARM_SP_REGNUM;
2566 /* Determine offset to previous frame. */
2568 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2570 /* We already got the previous SP. */
2571 cache->prev_sp = vsp;
2576 /* Unwinding via ARM exception table entries. Note that the sniffer
2577 already computes a filled-in prologue cache, which is then used
2578 with the same arm_prologue_this_id and arm_prologue_prev_register
2579 routines also used for prologue-parsing based unwinding. */
2582 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2583 struct frame_info *this_frame,
2584 void **this_prologue_cache)
2586 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2587 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2588 CORE_ADDR addr_in_block, exidx_region, func_start;
2589 struct arm_prologue_cache *cache;
2592 /* See if we have an ARM exception table entry covering this address. */
2593 addr_in_block = get_frame_address_in_block (this_frame);
2594 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2598 /* The ARM exception table does not describe unwind information
2599 for arbitrary PC values, but is guaranteed to be correct only
2600 at call sites. We have to decide here whether we want to use
2601 ARM exception table information for this frame, or fall back
2602 to using prologue parsing. (Note that if we have DWARF CFI,
2603 this sniffer isn't even called -- CFI is always preferred.)
2605 Before we make this decision, however, we check whether we
2606 actually have *symbol* information for the current frame.
2607 If not, prologue parsing would not work anyway, so we might
2608 as well use the exception table and hope for the best. */
2609 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2613 /* If the next frame is "normal", we are at a call site in this
2614 frame, so exception information is guaranteed to be valid. */
2615 if (get_next_frame (this_frame)
2616 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2619 /* We also assume exception information is valid if we're currently
2620 blocked in a system call. The system library is supposed to
2621 ensure this, so that e.g. pthread cancellation works. */
2622 if (arm_frame_is_thumb (this_frame))
2626 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2627 byte_order_for_code, &insn)
2628 && (insn & 0xff00) == 0xdf00 /* svc */)
2635 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2636 byte_order_for_code, &insn)
2637 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2641 /* Bail out if we don't know that exception information is valid. */
2645 /* The ARM exception index does not mark the *end* of the region
2646 covered by the entry, and some functions will not have any entry.
2647 To correctly recognize the end of the covered region, the linker
2648 should have inserted dummy records with a CANTUNWIND marker.
2650 Unfortunately, current versions of GNU ld do not reliably do
2651 this, and thus we may have found an incorrect entry above.
2652 As a (temporary) sanity check, we only use the entry if it
2653 lies *within* the bounds of the function. Note that this check
2654 might reject perfectly valid entries that just happen to cover
2655 multiple functions; therefore this check ought to be removed
2656 once the linker is fixed. */
2657 if (func_start > exidx_region)
2661 /* Decode the list of unwinding instructions into a prologue cache.
2662 Note that this may fail due to e.g. a "refuse to unwind" code. */
2663 cache = arm_exidx_fill_cache (this_frame, entry);
2667 *this_prologue_cache = cache;
2671 struct frame_unwind arm_exidx_unwind = {
2673 default_frame_unwind_stop_reason,
2674 arm_prologue_this_id,
2675 arm_prologue_prev_register,
2677 arm_exidx_unwind_sniffer
2680 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2681 trampoline, return the target PC. Otherwise return 0.
2683 void call0a (char c, short s, int i, long l) {}
2687 (*pointer_to_call0a) (c, s, i, l);
2690 Instead of calling a stub library function _call_via_xx (xx is
2691 the register name), GCC may inline the trampoline in the object
2692 file as below (register r2 has the address of call0a).
2695 .type main, %function
2704 The trampoline 'bx r2' doesn't belong to main. */
2707 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2709 /* The heuristics of recognizing such trampoline is that FRAME is
2710 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2711 if (arm_frame_is_thumb (frame))
2715 if (target_read_memory (pc, buf, 2) == 0)
2717 struct gdbarch *gdbarch = get_frame_arch (frame);
2718 enum bfd_endian byte_order_for_code
2719 = gdbarch_byte_order_for_code (gdbarch);
2721 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2723 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2726 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2728 /* Clear the LSB so that gdb core sets step-resume
2729 breakpoint at the right address. */
2730 return UNMAKE_THUMB_ADDR (dest);
2738 static struct arm_prologue_cache *
2739 arm_make_stub_cache (struct frame_info *this_frame)
2741 struct arm_prologue_cache *cache;
2743 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2744 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2746 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2751 /* Our frame ID for a stub frame is the current SP and LR. */
2754 arm_stub_this_id (struct frame_info *this_frame,
2756 struct frame_id *this_id)
2758 struct arm_prologue_cache *cache;
2760 if (*this_cache == NULL)
2761 *this_cache = arm_make_stub_cache (this_frame);
2762 cache = (struct arm_prologue_cache *) *this_cache;
2764 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2768 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2769 struct frame_info *this_frame,
2770 void **this_prologue_cache)
2772 CORE_ADDR addr_in_block;
2774 CORE_ADDR pc, start_addr;
2777 addr_in_block = get_frame_address_in_block (this_frame);
2778 pc = get_frame_pc (this_frame);
2779 if (in_plt_section (addr_in_block)
2780 /* We also use the stub winder if the target memory is unreadable
2781 to avoid having the prologue unwinder trying to read it. */
2782 || target_read_memory (pc, dummy, 4) != 0)
2785 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2786 && arm_skip_bx_reg (this_frame, pc) != 0)
2792 struct frame_unwind arm_stub_unwind = {
2794 default_frame_unwind_stop_reason,
2796 arm_prologue_prev_register,
2798 arm_stub_unwind_sniffer
2801 /* Put here the code to store, into CACHE->saved_regs, the addresses
2802 of the saved registers of frame described by THIS_FRAME. CACHE is
2805 static struct arm_prologue_cache *
2806 arm_m_exception_cache (struct frame_info *this_frame)
2808 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2809 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2810 struct arm_prologue_cache *cache;
2811 CORE_ADDR unwound_sp;
2814 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2815 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2817 unwound_sp = get_frame_register_unsigned (this_frame,
2820 /* The hardware saves eight 32-bit words, comprising xPSR,
2821 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2822 "B1.5.6 Exception entry behavior" in
2823 "ARMv7-M Architecture Reference Manual". */
2824 cache->saved_regs[0].addr = unwound_sp;
2825 cache->saved_regs[1].addr = unwound_sp + 4;
2826 cache->saved_regs[2].addr = unwound_sp + 8;
2827 cache->saved_regs[3].addr = unwound_sp + 12;
2828 cache->saved_regs[12].addr = unwound_sp + 16;
2829 cache->saved_regs[14].addr = unwound_sp + 20;
2830 cache->saved_regs[15].addr = unwound_sp + 24;
2831 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2833 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2834 aligner between the top of the 32-byte stack frame and the
2835 previous context's stack pointer. */
2836 cache->prev_sp = unwound_sp + 32;
2837 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2838 && (xpsr & (1 << 9)) != 0)
2839 cache->prev_sp += 4;
2844 /* Implementation of function hook 'this_id' in
2845 'struct frame_uwnind'. */
2848 arm_m_exception_this_id (struct frame_info *this_frame,
2850 struct frame_id *this_id)
2852 struct arm_prologue_cache *cache;
2854 if (*this_cache == NULL)
2855 *this_cache = arm_m_exception_cache (this_frame);
2856 cache = (struct arm_prologue_cache *) *this_cache;
2858 /* Our frame ID for a stub frame is the current SP and LR. */
2859 *this_id = frame_id_build (cache->prev_sp,
2860 get_frame_pc (this_frame));
2863 /* Implementation of function hook 'prev_register' in
2864 'struct frame_uwnind'. */
2866 static struct value *
2867 arm_m_exception_prev_register (struct frame_info *this_frame,
2871 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2872 struct arm_prologue_cache *cache;
2874 if (*this_cache == NULL)
2875 *this_cache = arm_m_exception_cache (this_frame);
2876 cache = (struct arm_prologue_cache *) *this_cache;
2878 /* The value was already reconstructed into PREV_SP. */
2879 if (prev_regnum == ARM_SP_REGNUM)
2880 return frame_unwind_got_constant (this_frame, prev_regnum,
2883 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2887 /* Implementation of function hook 'sniffer' in
2888 'struct frame_uwnind'. */
2891 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
2892 struct frame_info *this_frame,
2893 void **this_prologue_cache)
2895 CORE_ADDR this_pc = get_frame_pc (this_frame);
2897 /* No need to check is_m; this sniffer is only registered for
2898 M-profile architectures. */
2900 /* Exception frames return to one of these magic PCs. Other values
2901 are not defined as of v7-M. See details in "B1.5.8 Exception
2902 return behavior" in "ARMv7-M Architecture Reference Manual". */
2903 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
2904 || this_pc == 0xfffffffd)
2910 /* Frame unwinder for M-profile exceptions. */
2912 struct frame_unwind arm_m_exception_unwind =
2915 default_frame_unwind_stop_reason,
2916 arm_m_exception_this_id,
2917 arm_m_exception_prev_register,
2919 arm_m_exception_unwind_sniffer
2923 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
2925 struct arm_prologue_cache *cache;
2927 if (*this_cache == NULL)
2928 *this_cache = arm_make_prologue_cache (this_frame);
2929 cache = (struct arm_prologue_cache *) *this_cache;
2931 return cache->prev_sp - cache->framesize;
2934 struct frame_base arm_normal_base = {
2935 &arm_prologue_unwind,
2936 arm_normal_frame_base,
2937 arm_normal_frame_base,
2938 arm_normal_frame_base
2941 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2942 dummy frame. The frame ID's base needs to match the TOS value
2943 saved by save_dummy_frame_tos() and returned from
2944 arm_push_dummy_call, and the PC needs to match the dummy frame's
2947 static struct frame_id
2948 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2950 return frame_id_build (get_frame_register_unsigned (this_frame,
2952 get_frame_pc (this_frame));
2955 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2956 be used to construct the previous frame's ID, after looking up the
2957 containing function). */
2960 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
2963 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
2964 return arm_addr_bits_remove (gdbarch, pc);
2968 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
2970 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
2973 static struct value *
2974 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
2977 struct gdbarch * gdbarch = get_frame_arch (this_frame);
2979 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2984 /* The PC is normally copied from the return column, which
2985 describes saves of LR. However, that version may have an
2986 extra bit set to indicate Thumb state. The bit is not
2988 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2989 return frame_unwind_got_constant (this_frame, regnum,
2990 arm_addr_bits_remove (gdbarch, lr));
2993 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
2994 cpsr = get_frame_register_unsigned (this_frame, regnum);
2995 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2996 if (IS_THUMB_ADDR (lr))
3000 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3003 internal_error (__FILE__, __LINE__,
3004 _("Unexpected register %d"), regnum);
3009 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3010 struct dwarf2_frame_state_reg *reg,
3011 struct frame_info *this_frame)
3017 reg->how = DWARF2_FRAME_REG_FN;
3018 reg->loc.fn = arm_dwarf2_prev_register;
3021 reg->how = DWARF2_FRAME_REG_CFA;
3026 /* Implement the stack_frame_destroyed_p gdbarch method. */
3029 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3031 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3032 unsigned int insn, insn2;
3033 int found_return = 0, found_stack_adjust = 0;
3034 CORE_ADDR func_start, func_end;
3038 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3041 /* The epilogue is a sequence of instructions along the following lines:
3043 - add stack frame size to SP or FP
3044 - [if frame pointer used] restore SP from FP
3045 - restore registers from SP [may include PC]
3046 - a return-type instruction [if PC wasn't already restored]
3048 In a first pass, we scan forward from the current PC and verify the
3049 instructions we find as compatible with this sequence, ending in a
3052 However, this is not sufficient to distinguish indirect function calls
3053 within a function from indirect tail calls in the epilogue in some cases.
3054 Therefore, if we didn't already find any SP-changing instruction during
3055 forward scan, we add a backward scanning heuristic to ensure we actually
3056 are in the epilogue. */
3059 while (scan_pc < func_end && !found_return)
3061 if (target_read_memory (scan_pc, buf, 2))
3065 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3067 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3069 else if (insn == 0x46f7) /* mov pc, lr */
3071 else if (thumb_instruction_restores_sp (insn))
3073 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3076 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3078 if (target_read_memory (scan_pc, buf, 2))
3082 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3084 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3086 if (insn2 & 0x8000) /* <registers> include PC. */
3089 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3090 && (insn2 & 0x0fff) == 0x0b04)
3092 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3095 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3096 && (insn2 & 0x0e00) == 0x0a00)
3108 /* Since any instruction in the epilogue sequence, with the possible
3109 exception of return itself, updates the stack pointer, we need to
3110 scan backwards for at most one instruction. Try either a 16-bit or
3111 a 32-bit instruction. This is just a heuristic, so we do not worry
3112 too much about false positives. */
3114 if (pc - 4 < func_start)
3116 if (target_read_memory (pc - 4, buf, 4))
3119 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3120 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3122 if (thumb_instruction_restores_sp (insn2))
3123 found_stack_adjust = 1;
3124 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3125 found_stack_adjust = 1;
3126 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3127 && (insn2 & 0x0fff) == 0x0b04)
3128 found_stack_adjust = 1;
3129 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3130 && (insn2 & 0x0e00) == 0x0a00)
3131 found_stack_adjust = 1;
3133 return found_stack_adjust;
3136 /* Implement the stack_frame_destroyed_p gdbarch method. */
3139 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3141 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3144 CORE_ADDR func_start, func_end;
3146 if (arm_pc_is_thumb (gdbarch, pc))
3147 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3149 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3152 /* We are in the epilogue if the previous instruction was a stack
3153 adjustment and the next instruction is a possible return (bx, mov
3154 pc, or pop). We could have to scan backwards to find the stack
3155 adjustment, or forwards to find the return, but this is a decent
3156 approximation. First scan forwards. */
3159 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3160 if (bits (insn, 28, 31) != INST_NV)
3162 if ((insn & 0x0ffffff0) == 0x012fff10)
3165 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3168 else if ((insn & 0x0fff0000) == 0x08bd0000
3169 && (insn & 0x0000c000) != 0)
3170 /* POP (LDMIA), including PC or LR. */
3177 /* Scan backwards. This is just a heuristic, so do not worry about
3178 false positives from mode changes. */
3180 if (pc < func_start + 4)
3183 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3184 if (arm_instruction_restores_sp (insn))
3191 /* When arguments must be pushed onto the stack, they go on in reverse
3192 order. The code below implements a FILO (stack) to do this. */
3197 struct stack_item *prev;
3201 static struct stack_item *
3202 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
3204 struct stack_item *si;
3205 si = XNEW (struct stack_item);
3206 si->data = (gdb_byte *) xmalloc (len);
3209 memcpy (si->data, contents, len);
3213 static struct stack_item *
3214 pop_stack_item (struct stack_item *si)
3216 struct stack_item *dead = si;
3224 /* Return the alignment (in bytes) of the given type. */
3227 arm_type_align (struct type *t)
3233 t = check_typedef (t);
3234 switch (TYPE_CODE (t))
3237 /* Should never happen. */
3238 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3242 case TYPE_CODE_ENUM:
3246 case TYPE_CODE_RANGE:
3248 case TYPE_CODE_CHAR:
3249 case TYPE_CODE_BOOL:
3250 return TYPE_LENGTH (t);
3252 case TYPE_CODE_ARRAY:
3253 if (TYPE_VECTOR (t))
3255 /* Use the natural alignment for vector types (the same for
3256 scalar type), but the maximum alignment is 64-bit. */
3257 if (TYPE_LENGTH (t) > 8)
3260 return TYPE_LENGTH (t);
3263 return arm_type_align (TYPE_TARGET_TYPE (t));
3264 case TYPE_CODE_COMPLEX:
3265 return arm_type_align (TYPE_TARGET_TYPE (t));
3267 case TYPE_CODE_STRUCT:
3268 case TYPE_CODE_UNION:
3270 for (n = 0; n < TYPE_NFIELDS (t); n++)
3272 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3280 /* Possible base types for a candidate for passing and returning in
3283 enum arm_vfp_cprc_base_type
3292 /* The length of one element of base type B. */
3295 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3299 case VFP_CPRC_SINGLE:
3301 case VFP_CPRC_DOUBLE:
3303 case VFP_CPRC_VEC64:
3305 case VFP_CPRC_VEC128:
3308 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3313 /* The character ('s', 'd' or 'q') for the type of VFP register used
3314 for passing base type B. */
3317 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3321 case VFP_CPRC_SINGLE:
3323 case VFP_CPRC_DOUBLE:
3325 case VFP_CPRC_VEC64:
3327 case VFP_CPRC_VEC128:
3330 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3335 /* Determine whether T may be part of a candidate for passing and
3336 returning in VFP registers, ignoring the limit on the total number
3337 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3338 classification of the first valid component found; if it is not
3339 VFP_CPRC_UNKNOWN, all components must have the same classification
3340 as *BASE_TYPE. If it is found that T contains a type not permitted
3341 for passing and returning in VFP registers, a type differently
3342 classified from *BASE_TYPE, or two types differently classified
3343 from each other, return -1, otherwise return the total number of
3344 base-type elements found (possibly 0 in an empty structure or
3345 array). Vector types are not currently supported, matching the
3346 generic AAPCS support. */
3349 arm_vfp_cprc_sub_candidate (struct type *t,
3350 enum arm_vfp_cprc_base_type *base_type)
3352 t = check_typedef (t);
3353 switch (TYPE_CODE (t))
3356 switch (TYPE_LENGTH (t))
3359 if (*base_type == VFP_CPRC_UNKNOWN)
3360 *base_type = VFP_CPRC_SINGLE;
3361 else if (*base_type != VFP_CPRC_SINGLE)
3366 if (*base_type == VFP_CPRC_UNKNOWN)
3367 *base_type = VFP_CPRC_DOUBLE;
3368 else if (*base_type != VFP_CPRC_DOUBLE)
3377 case TYPE_CODE_COMPLEX:
3378 /* Arguments of complex T where T is one of the types float or
3379 double get treated as if they are implemented as:
3388 switch (TYPE_LENGTH (t))
3391 if (*base_type == VFP_CPRC_UNKNOWN)
3392 *base_type = VFP_CPRC_SINGLE;
3393 else if (*base_type != VFP_CPRC_SINGLE)
3398 if (*base_type == VFP_CPRC_UNKNOWN)
3399 *base_type = VFP_CPRC_DOUBLE;
3400 else if (*base_type != VFP_CPRC_DOUBLE)
3409 case TYPE_CODE_ARRAY:
3411 if (TYPE_VECTOR (t))
3413 /* A 64-bit or 128-bit containerized vector type are VFP
3415 switch (TYPE_LENGTH (t))
3418 if (*base_type == VFP_CPRC_UNKNOWN)
3419 *base_type = VFP_CPRC_VEC64;
3422 if (*base_type == VFP_CPRC_UNKNOWN)
3423 *base_type = VFP_CPRC_VEC128;
3434 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t),
3438 if (TYPE_LENGTH (t) == 0)
3440 gdb_assert (count == 0);
3443 else if (count == 0)
3445 unitlen = arm_vfp_cprc_unit_length (*base_type);
3446 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3447 return TYPE_LENGTH (t) / unitlen;
3452 case TYPE_CODE_STRUCT:
3457 for (i = 0; i < TYPE_NFIELDS (t); i++)
3459 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3461 if (sub_count == -1)
3465 if (TYPE_LENGTH (t) == 0)
3467 gdb_assert (count == 0);
3470 else if (count == 0)
3472 unitlen = arm_vfp_cprc_unit_length (*base_type);
3473 if (TYPE_LENGTH (t) != unitlen * count)
3478 case TYPE_CODE_UNION:
3483 for (i = 0; i < TYPE_NFIELDS (t); i++)
3485 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3487 if (sub_count == -1)
3489 count = (count > sub_count ? count : sub_count);
3491 if (TYPE_LENGTH (t) == 0)
3493 gdb_assert (count == 0);
3496 else if (count == 0)
3498 unitlen = arm_vfp_cprc_unit_length (*base_type);
3499 if (TYPE_LENGTH (t) != unitlen * count)
3511 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3512 if passed to or returned from a non-variadic function with the VFP
3513 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3514 *BASE_TYPE to the base type for T and *COUNT to the number of
3515 elements of that base type before returning. */
3518 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3521 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3522 int c = arm_vfp_cprc_sub_candidate (t, &b);
3523 if (c <= 0 || c > 4)
3530 /* Return 1 if the VFP ABI should be used for passing arguments to and
3531 returning values from a function of type FUNC_TYPE, 0
3535 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3537 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3538 /* Variadic functions always use the base ABI. Assume that functions
3539 without debug info are not variadic. */
3540 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3542 /* The VFP ABI is only supported as a variant of AAPCS. */
3543 if (tdep->arm_abi != ARM_ABI_AAPCS)
3545 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3548 /* We currently only support passing parameters in integer registers, which
3549 conforms with GCC's default model, and VFP argument passing following
3550 the VFP variant of AAPCS. Several other variants exist and
3551 we should probably support some of them based on the selected ABI. */
3554 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3555 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3556 struct value **args, CORE_ADDR sp, int struct_return,
3557 CORE_ADDR struct_addr)
3559 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3563 struct stack_item *si = NULL;
3566 unsigned vfp_regs_free = (1 << 16) - 1;
3568 /* Determine the type of this function and whether the VFP ABI
3570 ftype = check_typedef (value_type (function));
3571 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3572 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3573 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3575 /* Set the return address. For the ARM, the return breakpoint is
3576 always at BP_ADDR. */
3577 if (arm_pc_is_thumb (gdbarch, bp_addr))
3579 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3581 /* Walk through the list of args and determine how large a temporary
3582 stack is required. Need to take care here as structs may be
3583 passed on the stack, and we have to push them. */
3586 argreg = ARM_A1_REGNUM;
3589 /* The struct_return pointer occupies the first parameter
3590 passing register. */
3594 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3595 gdbarch_register_name (gdbarch, argreg),
3596 paddress (gdbarch, struct_addr));
3597 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3601 for (argnum = 0; argnum < nargs; argnum++)
3604 struct type *arg_type;
3605 struct type *target_type;
3606 enum type_code typecode;
3607 const bfd_byte *val;
3609 enum arm_vfp_cprc_base_type vfp_base_type;
3611 int may_use_core_reg = 1;
3613 arg_type = check_typedef (value_type (args[argnum]));
3614 len = TYPE_LENGTH (arg_type);
3615 target_type = TYPE_TARGET_TYPE (arg_type);
3616 typecode = TYPE_CODE (arg_type);
3617 val = value_contents (args[argnum]);
3619 align = arm_type_align (arg_type);
3620 /* Round alignment up to a whole number of words. */
3621 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3622 /* Different ABIs have different maximum alignments. */
3623 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3625 /* The APCS ABI only requires word alignment. */
3626 align = INT_REGISTER_SIZE;
3630 /* The AAPCS requires at most doubleword alignment. */
3631 if (align > INT_REGISTER_SIZE * 2)
3632 align = INT_REGISTER_SIZE * 2;
3636 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3644 /* Because this is a CPRC it cannot go in a core register or
3645 cause a core register to be skipped for alignment.
3646 Either it goes in VFP registers and the rest of this loop
3647 iteration is skipped for this argument, or it goes on the
3648 stack (and the stack alignment code is correct for this
3650 may_use_core_reg = 0;
3652 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3653 shift = unit_length / 4;
3654 mask = (1 << (shift * vfp_base_count)) - 1;
3655 for (regno = 0; regno < 16; regno += shift)
3656 if (((vfp_regs_free >> regno) & mask) == mask)
3665 vfp_regs_free &= ~(mask << regno);
3666 reg_scaled = regno / shift;
3667 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3668 for (i = 0; i < vfp_base_count; i++)
3672 if (reg_char == 'q')
3673 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3674 val + i * unit_length);
3677 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3678 reg_char, reg_scaled + i);
3679 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3681 regcache_cooked_write (regcache, regnum,
3682 val + i * unit_length);
3689 /* This CPRC could not go in VFP registers, so all VFP
3690 registers are now marked as used. */
3695 /* Push stack padding for dowubleword alignment. */
3696 if (nstack & (align - 1))
3698 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3699 nstack += INT_REGISTER_SIZE;
3702 /* Doubleword aligned quantities must go in even register pairs. */
3703 if (may_use_core_reg
3704 && argreg <= ARM_LAST_ARG_REGNUM
3705 && align > INT_REGISTER_SIZE
3709 /* If the argument is a pointer to a function, and it is a
3710 Thumb function, create a LOCAL copy of the value and set
3711 the THUMB bit in it. */
3712 if (TYPE_CODE_PTR == typecode
3713 && target_type != NULL
3714 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3716 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3717 if (arm_pc_is_thumb (gdbarch, regval))
3719 bfd_byte *copy = (bfd_byte *) alloca (len);
3720 store_unsigned_integer (copy, len, byte_order,
3721 MAKE_THUMB_ADDR (regval));
3726 /* Copy the argument to general registers or the stack in
3727 register-sized pieces. Large arguments are split between
3728 registers and stack. */
3731 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3733 = extract_unsigned_integer (val, partial_len, byte_order);
3735 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3737 /* The argument is being passed in a general purpose
3739 if (byte_order == BFD_ENDIAN_BIG)
3740 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3742 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3744 gdbarch_register_name
3746 phex (regval, INT_REGISTER_SIZE));
3747 regcache_cooked_write_unsigned (regcache, argreg, regval);
3752 gdb_byte buf[INT_REGISTER_SIZE];
3754 memset (buf, 0, sizeof (buf));
3755 store_unsigned_integer (buf, partial_len, byte_order, regval);
3757 /* Push the arguments onto the stack. */
3759 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3761 si = push_stack_item (si, buf, INT_REGISTER_SIZE);
3762 nstack += INT_REGISTER_SIZE;
3769 /* If we have an odd number of words to push, then decrement the stack
3770 by one word now, so first stack argument will be dword aligned. */
3777 write_memory (sp, si->data, si->len);
3778 si = pop_stack_item (si);
3781 /* Finally, update teh SP register. */
3782 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3788 /* Always align the frame to an 8-byte boundary. This is required on
3789 some platforms and harmless on the rest. */
3792 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3794 /* Align the stack to eight bytes. */
3795 return sp & ~ (CORE_ADDR) 7;
3799 print_fpu_flags (struct ui_file *file, int flags)
3801 if (flags & (1 << 0))
3802 fputs_filtered ("IVO ", file);
3803 if (flags & (1 << 1))
3804 fputs_filtered ("DVZ ", file);
3805 if (flags & (1 << 2))
3806 fputs_filtered ("OFL ", file);
3807 if (flags & (1 << 3))
3808 fputs_filtered ("UFL ", file);
3809 if (flags & (1 << 4))
3810 fputs_filtered ("INX ", file);
3811 fputc_filtered ('\n', file);
3814 /* Print interesting information about the floating point processor
3815 (if present) or emulator. */
3817 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3818 struct frame_info *frame, const char *args)
3820 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3823 type = (status >> 24) & 127;
3824 if (status & (1 << 31))
3825 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3827 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3828 /* i18n: [floating point unit] mask */
3829 fputs_filtered (_("mask: "), file);
3830 print_fpu_flags (file, status >> 16);
3831 /* i18n: [floating point unit] flags */
3832 fputs_filtered (_("flags: "), file);
3833 print_fpu_flags (file, status);
3836 /* Construct the ARM extended floating point type. */
3837 static struct type *
3838 arm_ext_type (struct gdbarch *gdbarch)
3840 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3842 if (!tdep->arm_ext_type)
3844 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3845 floatformats_arm_ext);
3847 return tdep->arm_ext_type;
3850 static struct type *
3851 arm_neon_double_type (struct gdbarch *gdbarch)
3853 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3855 if (tdep->neon_double_type == NULL)
3857 struct type *t, *elem;
3859 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3861 elem = builtin_type (gdbarch)->builtin_uint8;
3862 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3863 elem = builtin_type (gdbarch)->builtin_uint16;
3864 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3865 elem = builtin_type (gdbarch)->builtin_uint32;
3866 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3867 elem = builtin_type (gdbarch)->builtin_uint64;
3868 append_composite_type_field (t, "u64", elem);
3869 elem = builtin_type (gdbarch)->builtin_float;
3870 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3871 elem = builtin_type (gdbarch)->builtin_double;
3872 append_composite_type_field (t, "f64", elem);
3874 TYPE_VECTOR (t) = 1;
3875 TYPE_NAME (t) = "neon_d";
3876 tdep->neon_double_type = t;
3879 return tdep->neon_double_type;
3882 /* FIXME: The vector types are not correctly ordered on big-endian
3883 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3884 bits of d0 - regardless of what unit size is being held in d0. So
3885 the offset of the first uint8 in d0 is 7, but the offset of the
3886 first float is 4. This code works as-is for little-endian
3889 static struct type *
3890 arm_neon_quad_type (struct gdbarch *gdbarch)
3892 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3894 if (tdep->neon_quad_type == NULL)
3896 struct type *t, *elem;
3898 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3900 elem = builtin_type (gdbarch)->builtin_uint8;
3901 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3902 elem = builtin_type (gdbarch)->builtin_uint16;
3903 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3904 elem = builtin_type (gdbarch)->builtin_uint32;
3905 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3906 elem = builtin_type (gdbarch)->builtin_uint64;
3907 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
3908 elem = builtin_type (gdbarch)->builtin_float;
3909 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
3910 elem = builtin_type (gdbarch)->builtin_double;
3911 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
3913 TYPE_VECTOR (t) = 1;
3914 TYPE_NAME (t) = "neon_q";
3915 tdep->neon_quad_type = t;
3918 return tdep->neon_quad_type;
3921 /* Return the GDB type object for the "standard" data type of data in
3924 static struct type *
3925 arm_register_type (struct gdbarch *gdbarch, int regnum)
3927 int num_regs = gdbarch_num_regs (gdbarch);
3929 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
3930 && regnum >= num_regs && regnum < num_regs + 32)
3931 return builtin_type (gdbarch)->builtin_float;
3933 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
3934 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
3935 return arm_neon_quad_type (gdbarch);
3937 /* If the target description has register information, we are only
3938 in this function so that we can override the types of
3939 double-precision registers for NEON. */
3940 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
3942 struct type *t = tdesc_register_type (gdbarch, regnum);
3944 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
3945 && TYPE_CODE (t) == TYPE_CODE_FLT
3946 && gdbarch_tdep (gdbarch)->have_neon)
3947 return arm_neon_double_type (gdbarch);
3952 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
3954 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
3955 return builtin_type (gdbarch)->builtin_void;
3957 return arm_ext_type (gdbarch);
3959 else if (regnum == ARM_SP_REGNUM)
3960 return builtin_type (gdbarch)->builtin_data_ptr;
3961 else if (regnum == ARM_PC_REGNUM)
3962 return builtin_type (gdbarch)->builtin_func_ptr;
3963 else if (regnum >= ARRAY_SIZE (arm_register_names))
3964 /* These registers are only supported on targets which supply
3965 an XML description. */
3966 return builtin_type (gdbarch)->builtin_int0;
3968 return builtin_type (gdbarch)->builtin_uint32;
3971 /* Map a DWARF register REGNUM onto the appropriate GDB register
3975 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3977 /* Core integer regs. */
3978 if (reg >= 0 && reg <= 15)
3981 /* Legacy FPA encoding. These were once used in a way which
3982 overlapped with VFP register numbering, so their use is
3983 discouraged, but GDB doesn't support the ARM toolchain
3984 which used them for VFP. */
3985 if (reg >= 16 && reg <= 23)
3986 return ARM_F0_REGNUM + reg - 16;
3988 /* New assignments for the FPA registers. */
3989 if (reg >= 96 && reg <= 103)
3990 return ARM_F0_REGNUM + reg - 96;
3992 /* WMMX register assignments. */
3993 if (reg >= 104 && reg <= 111)
3994 return ARM_WCGR0_REGNUM + reg - 104;
3996 if (reg >= 112 && reg <= 127)
3997 return ARM_WR0_REGNUM + reg - 112;
3999 if (reg >= 192 && reg <= 199)
4000 return ARM_WC0_REGNUM + reg - 192;
4002 /* VFP v2 registers. A double precision value is actually
4003 in d1 rather than s2, but the ABI only defines numbering
4004 for the single precision registers. This will "just work"
4005 in GDB for little endian targets (we'll read eight bytes,
4006 starting in s0 and then progressing to s1), but will be
4007 reversed on big endian targets with VFP. This won't
4008 be a problem for the new Neon quad registers; you're supposed
4009 to use DW_OP_piece for those. */
4010 if (reg >= 64 && reg <= 95)
4014 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4015 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4019 /* VFP v3 / Neon registers. This range is also used for VFP v2
4020 registers, except that it now describes d0 instead of s0. */
4021 if (reg >= 256 && reg <= 287)
4025 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4026 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4033 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4035 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4038 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4040 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4041 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4043 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4044 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4046 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4047 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4049 if (reg < NUM_GREGS)
4050 return SIM_ARM_R0_REGNUM + reg;
4053 if (reg < NUM_FREGS)
4054 return SIM_ARM_FP0_REGNUM + reg;
4057 if (reg < NUM_SREGS)
4058 return SIM_ARM_FPS_REGNUM + reg;
4061 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4064 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4065 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4066 It is thought that this is is the floating-point register format on
4067 little-endian systems. */
4070 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4071 void *dbl, int endianess)
4075 if (endianess == BFD_ENDIAN_BIG)
4076 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4078 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4080 floatformat_from_doublest (fmt, &d, dbl);
4084 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4089 floatformat_to_doublest (fmt, ptr, &d);
4090 if (endianess == BFD_ENDIAN_BIG)
4091 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4093 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4097 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4098 of the appropriate mode (as encoded in the PC value), even if this
4099 differs from what would be expected according to the symbol tables. */
4102 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
4103 struct address_space *aspace,
4106 struct cleanup *old_chain
4107 = make_cleanup_restore_integer (&arm_override_mode);
4109 arm_override_mode = IS_THUMB_ADDR (pc);
4110 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4112 insert_single_step_breakpoint (gdbarch, aspace, pc);
4114 do_cleanups (old_chain);
4117 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4118 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4119 NULL if an error occurs. BUF is freed. */
4122 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4123 int old_len, int new_len)
4126 int bytes_to_read = new_len - old_len;
4128 new_buf = (gdb_byte *) xmalloc (new_len);
4129 memcpy (new_buf + bytes_to_read, buf, old_len);
4131 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4139 /* An IT block is at most the 2-byte IT instruction followed by
4140 four 4-byte instructions. The furthest back we must search to
4141 find an IT block that affects the current instruction is thus
4142 2 + 3 * 4 == 14 bytes. */
4143 #define MAX_IT_BLOCK_PREFIX 14
4145 /* Use a quick scan if there are more than this many bytes of
4147 #define IT_SCAN_THRESHOLD 32
4149 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4150 A breakpoint in an IT block may not be hit, depending on the
4153 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4157 CORE_ADDR boundary, func_start;
4159 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4160 int i, any, last_it, last_it_count;
4162 /* If we are using BKPT breakpoints, none of this is necessary. */
4163 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4166 /* ARM mode does not have this problem. */
4167 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4170 /* We are setting a breakpoint in Thumb code that could potentially
4171 contain an IT block. The first step is to find how much Thumb
4172 code there is; we do not need to read outside of known Thumb
4174 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4176 /* Thumb-2 code must have mapping symbols to have a chance. */
4179 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4181 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4182 && func_start > boundary)
4183 boundary = func_start;
4185 /* Search for a candidate IT instruction. We have to do some fancy
4186 footwork to distinguish a real IT instruction from the second
4187 half of a 32-bit instruction, but there is no need for that if
4188 there's no candidate. */
4189 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
4191 /* No room for an IT instruction. */
4194 buf = (gdb_byte *) xmalloc (buf_len);
4195 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4198 for (i = 0; i < buf_len; i += 2)
4200 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4201 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4214 /* OK, the code bytes before this instruction contain at least one
4215 halfword which resembles an IT instruction. We know that it's
4216 Thumb code, but there are still two possibilities. Either the
4217 halfword really is an IT instruction, or it is the second half of
4218 a 32-bit Thumb instruction. The only way we can tell is to
4219 scan forwards from a known instruction boundary. */
4220 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
4224 /* There's a lot of code before this instruction. Start with an
4225 optimistic search; it's easy to recognize halfwords that can
4226 not be the start of a 32-bit instruction, and use that to
4227 lock on to the instruction boundaries. */
4228 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
4231 buf_len = IT_SCAN_THRESHOLD;
4234 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
4236 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4237 if (thumb_insn_size (inst1) == 2)
4244 /* At this point, if DEFINITE, BUF[I] is the first place we
4245 are sure that we know the instruction boundaries, and it is far
4246 enough from BPADDR that we could not miss an IT instruction
4247 affecting BPADDR. If ! DEFINITE, give up - start from a
4251 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
4255 buf_len = bpaddr - boundary;
4261 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4264 buf_len = bpaddr - boundary;
4268 /* Scan forwards. Find the last IT instruction before BPADDR. */
4273 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4275 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4280 else if (inst1 & 0x0002)
4282 else if (inst1 & 0x0004)
4287 i += thumb_insn_size (inst1);
4293 /* There wasn't really an IT instruction after all. */
4296 if (last_it_count < 1)
4297 /* It was too far away. */
4300 /* This really is a trouble spot. Move the breakpoint to the IT
4302 return bpaddr - buf_len + last_it;
4305 /* ARM displaced stepping support.
4307 Generally ARM displaced stepping works as follows:
4309 1. When an instruction is to be single-stepped, it is first decoded by
4310 arm_process_displaced_insn. Depending on the type of instruction, it is
4311 then copied to a scratch location, possibly in a modified form. The
4312 copy_* set of functions performs such modification, as necessary. A
4313 breakpoint is placed after the modified instruction in the scratch space
4314 to return control to GDB. Note in particular that instructions which
4315 modify the PC will no longer do so after modification.
4317 2. The instruction is single-stepped, by setting the PC to the scratch
4318 location address, and resuming. Control returns to GDB when the
4321 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4322 function used for the current instruction. This function's job is to
4323 put the CPU/memory state back to what it would have been if the
4324 instruction had been executed unmodified in its original location. */
4326 /* NOP instruction (mov r0, r0). */
4327 #define ARM_NOP 0xe1a00000
4328 #define THUMB_NOP 0x4600
4330 /* Helper for register reads for displaced stepping. In particular, this
4331 returns the PC as it would be seen by the instruction at its original
4335 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4339 CORE_ADDR from = dsc->insn_addr;
4341 if (regno == ARM_PC_REGNUM)
4343 /* Compute pipeline offset:
4344 - When executing an ARM instruction, PC reads as the address of the
4345 current instruction plus 8.
4346 - When executing a Thumb instruction, PC reads as the address of the
4347 current instruction plus 4. */
4354 if (debug_displaced)
4355 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
4356 (unsigned long) from);
4357 return (ULONGEST) from;
4361 regcache_cooked_read_unsigned (regs, regno, &ret);
4362 if (debug_displaced)
4363 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
4364 regno, (unsigned long) ret);
4370 displaced_in_arm_mode (struct regcache *regs)
4373 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4375 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4377 return (ps & t_bit) == 0;
4380 /* Write to the PC as from a branch instruction. */
4383 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4387 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4388 architecture versions < 6. */
4389 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4390 val & ~(ULONGEST) 0x3);
4392 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4393 val & ~(ULONGEST) 0x1);
4396 /* Write to the PC as from a branch-exchange instruction. */
4399 bx_write_pc (struct regcache *regs, ULONGEST val)
4402 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4404 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4408 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
4409 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
4411 else if ((val & 2) == 0)
4413 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4414 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
4418 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4419 mode, align dest to 4 bytes). */
4420 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4421 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4422 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
4426 /* Write to the PC as if from a load instruction. */
4429 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4432 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
4433 bx_write_pc (regs, val);
4435 branch_write_pc (regs, dsc, val);
4438 /* Write to the PC as if from an ALU instruction. */
4441 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4444 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
4445 bx_write_pc (regs, val);
4447 branch_write_pc (regs, dsc, val);
4450 /* Helper for writing to registers for displaced stepping. Writing to the PC
4451 has a varying effects depending on the instruction which does the write:
4452 this is controlled by the WRITE_PC argument. */
4455 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4456 int regno, ULONGEST val, enum pc_write_style write_pc)
4458 if (regno == ARM_PC_REGNUM)
4460 if (debug_displaced)
4461 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
4462 (unsigned long) val);
4465 case BRANCH_WRITE_PC:
4466 branch_write_pc (regs, dsc, val);
4470 bx_write_pc (regs, val);
4474 load_write_pc (regs, dsc, val);
4478 alu_write_pc (regs, dsc, val);
4481 case CANNOT_WRITE_PC:
4482 warning (_("Instruction wrote to PC in an unexpected way when "
4483 "single-stepping"));
4487 internal_error (__FILE__, __LINE__,
4488 _("Invalid argument to displaced_write_reg"));
4491 dsc->wrote_to_pc = 1;
4495 if (debug_displaced)
4496 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
4497 regno, (unsigned long) val);
4498 regcache_cooked_write_unsigned (regs, regno, val);
4502 /* This function is used to concisely determine if an instruction INSN
4503 references PC. Register fields of interest in INSN should have the
4504 corresponding fields of BITMASK set to 0b1111. The function
4505 returns return 1 if any of these fields in INSN reference the PC
4506 (also 0b1111, r15), else it returns 0. */
4509 insn_references_pc (uint32_t insn, uint32_t bitmask)
4511 uint32_t lowbit = 1;
4513 while (bitmask != 0)
4517 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
4523 mask = lowbit * 0xf;
4525 if ((insn & mask) == mask)
4534 /* The simplest copy function. Many instructions have the same effect no
4535 matter what address they are executed at: in those cases, use this. */
4538 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
4539 const char *iname, struct displaced_step_closure *dsc)
4541 if (debug_displaced)
4542 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
4543 "opcode/class '%s' unmodified\n", (unsigned long) insn,
4546 dsc->modinsn[0] = insn;
4552 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
4553 uint16_t insn2, const char *iname,
4554 struct displaced_step_closure *dsc)
4556 if (debug_displaced)
4557 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
4558 "opcode/class '%s' unmodified\n", insn1, insn2,
4561 dsc->modinsn[0] = insn1;
4562 dsc->modinsn[1] = insn2;
4568 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4571 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn,
4573 struct displaced_step_closure *dsc)
4575 if (debug_displaced)
4576 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
4577 "opcode/class '%s' unmodified\n", insn,
4580 dsc->modinsn[0] = insn;
4585 /* Preload instructions with immediate offset. */
4588 cleanup_preload (struct gdbarch *gdbarch,
4589 struct regcache *regs, struct displaced_step_closure *dsc)
4591 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4592 if (!dsc->u.preload.immed)
4593 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4597 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
4598 struct displaced_step_closure *dsc, unsigned int rn)
4601 /* Preload instructions:
4603 {pli/pld} [rn, #+/-imm]
4605 {pli/pld} [r0, #+/-imm]. */
4607 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4608 rn_val = displaced_read_reg (regs, dsc, rn);
4609 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4610 dsc->u.preload.immed = 1;
4612 dsc->cleanup = &cleanup_preload;
4616 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4617 struct displaced_step_closure *dsc)
4619 unsigned int rn = bits (insn, 16, 19);
4621 if (!insn_references_pc (insn, 0x000f0000ul))
4622 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
4624 if (debug_displaced)
4625 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4626 (unsigned long) insn);
4628 dsc->modinsn[0] = insn & 0xfff0ffff;
4630 install_preload (gdbarch, regs, dsc, rn);
4636 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
4637 struct regcache *regs, struct displaced_step_closure *dsc)
4639 unsigned int rn = bits (insn1, 0, 3);
4640 unsigned int u_bit = bit (insn1, 7);
4641 int imm12 = bits (insn2, 0, 11);
4644 if (rn != ARM_PC_REGNUM)
4645 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
4647 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4648 PLD (literal) Encoding T1. */
4649 if (debug_displaced)
4650 fprintf_unfiltered (gdb_stdlog,
4651 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4652 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
4658 /* Rewrite instruction {pli/pld} PC imm12 into:
4659 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4663 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4665 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4666 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4668 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
4670 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
4671 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
4672 dsc->u.preload.immed = 0;
4674 /* {pli/pld} [r0, r1] */
4675 dsc->modinsn[0] = insn1 & 0xfff0;
4676 dsc->modinsn[1] = 0xf001;
4679 dsc->cleanup = &cleanup_preload;
4683 /* Preload instructions with register offset. */
4686 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
4687 struct displaced_step_closure *dsc, unsigned int rn,
4690 ULONGEST rn_val, rm_val;
4692 /* Preload register-offset instructions:
4694 {pli/pld} [rn, rm {, shift}]
4696 {pli/pld} [r0, r1 {, shift}]. */
4698 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4699 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4700 rn_val = displaced_read_reg (regs, dsc, rn);
4701 rm_val = displaced_read_reg (regs, dsc, rm);
4702 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4703 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
4704 dsc->u.preload.immed = 0;
4706 dsc->cleanup = &cleanup_preload;
4710 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
4711 struct regcache *regs,
4712 struct displaced_step_closure *dsc)
4714 unsigned int rn = bits (insn, 16, 19);
4715 unsigned int rm = bits (insn, 0, 3);
4718 if (!insn_references_pc (insn, 0x000f000ful))
4719 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
4721 if (debug_displaced)
4722 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4723 (unsigned long) insn);
4725 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
4727 install_preload_reg (gdbarch, regs, dsc, rn, rm);
4731 /* Copy/cleanup coprocessor load and store instructions. */
4734 cleanup_copro_load_store (struct gdbarch *gdbarch,
4735 struct regcache *regs,
4736 struct displaced_step_closure *dsc)
4738 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
4740 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4742 if (dsc->u.ldst.writeback)
4743 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
4747 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
4748 struct displaced_step_closure *dsc,
4749 int writeback, unsigned int rn)
4753 /* Coprocessor load/store instructions:
4755 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4757 {stc/stc2} [r0, #+/-imm].
4759 ldc/ldc2 are handled identically. */
4761 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4762 rn_val = displaced_read_reg (regs, dsc, rn);
4763 /* PC should be 4-byte aligned. */
4764 rn_val = rn_val & 0xfffffffc;
4765 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4767 dsc->u.ldst.writeback = writeback;
4768 dsc->u.ldst.rn = rn;
4770 dsc->cleanup = &cleanup_copro_load_store;
4774 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
4775 struct regcache *regs,
4776 struct displaced_step_closure *dsc)
4778 unsigned int rn = bits (insn, 16, 19);
4780 if (!insn_references_pc (insn, 0x000f0000ul))
4781 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
4783 if (debug_displaced)
4784 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4785 "load/store insn %.8lx\n", (unsigned long) insn);
4787 dsc->modinsn[0] = insn & 0xfff0ffff;
4789 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
4795 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
4796 uint16_t insn2, struct regcache *regs,
4797 struct displaced_step_closure *dsc)
4799 unsigned int rn = bits (insn1, 0, 3);
4801 if (rn != ARM_PC_REGNUM)
4802 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
4803 "copro load/store", dsc);
4805 if (debug_displaced)
4806 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4807 "load/store insn %.4x%.4x\n", insn1, insn2);
4809 dsc->modinsn[0] = insn1 & 0xfff0;
4810 dsc->modinsn[1] = insn2;
4813 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4814 doesn't support writeback, so pass 0. */
4815 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
4820 /* Clean up branch instructions (actually perform the branch, by setting
4824 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
4825 struct displaced_step_closure *dsc)
4827 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
4828 int branch_taken = condition_true (dsc->u.branch.cond, status);
4829 enum pc_write_style write_pc = dsc->u.branch.exchange
4830 ? BX_WRITE_PC : BRANCH_WRITE_PC;
4835 if (dsc->u.branch.link)
4837 /* The value of LR should be the next insn of current one. In order
4838 not to confuse logic hanlding later insn `bx lr', if current insn mode
4839 is Thumb, the bit 0 of LR value should be set to 1. */
4840 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
4843 next_insn_addr |= 0x1;
4845 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
4849 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
4852 /* Copy B/BL/BLX instructions with immediate destinations. */
4855 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
4856 struct displaced_step_closure *dsc,
4857 unsigned int cond, int exchange, int link, long offset)
4859 /* Implement "BL<cond> <label>" as:
4861 Preparation: cond <- instruction condition
4862 Insn: mov r0, r0 (nop)
4863 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4865 B<cond> similar, but don't set r14 in cleanup. */
4867 dsc->u.branch.cond = cond;
4868 dsc->u.branch.link = link;
4869 dsc->u.branch.exchange = exchange;
4871 dsc->u.branch.dest = dsc->insn_addr;
4872 if (link && exchange)
4873 /* For BLX, offset is computed from the Align (PC, 4). */
4874 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
4877 dsc->u.branch.dest += 4 + offset;
4879 dsc->u.branch.dest += 8 + offset;
4881 dsc->cleanup = &cleanup_branch;
4884 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
4885 struct regcache *regs, struct displaced_step_closure *dsc)
4887 unsigned int cond = bits (insn, 28, 31);
4888 int exchange = (cond == 0xf);
4889 int link = exchange || bit (insn, 24);
4892 if (debug_displaced)
4893 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
4894 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
4895 (unsigned long) insn);
4897 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4898 then arrange the switch into Thumb mode. */
4899 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
4901 offset = bits (insn, 0, 23) << 2;
4903 if (bit (offset, 25))
4904 offset = offset | ~0x3ffffff;
4906 dsc->modinsn[0] = ARM_NOP;
4908 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
4913 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
4914 uint16_t insn2, struct regcache *regs,
4915 struct displaced_step_closure *dsc)
4917 int link = bit (insn2, 14);
4918 int exchange = link && !bit (insn2, 12);
4921 int j1 = bit (insn2, 13);
4922 int j2 = bit (insn2, 11);
4923 int s = sbits (insn1, 10, 10);
4924 int i1 = !(j1 ^ bit (insn1, 10));
4925 int i2 = !(j2 ^ bit (insn1, 10));
4927 if (!link && !exchange) /* B */
4929 offset = (bits (insn2, 0, 10) << 1);
4930 if (bit (insn2, 12)) /* Encoding T4 */
4932 offset |= (bits (insn1, 0, 9) << 12)
4938 else /* Encoding T3 */
4940 offset |= (bits (insn1, 0, 5) << 12)
4944 cond = bits (insn1, 6, 9);
4949 offset = (bits (insn1, 0, 9) << 12);
4950 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
4951 offset |= exchange ?
4952 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
4955 if (debug_displaced)
4956 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
4957 "%.4x %.4x with offset %.8lx\n",
4958 link ? (exchange) ? "blx" : "bl" : "b",
4959 insn1, insn2, offset);
4961 dsc->modinsn[0] = THUMB_NOP;
4963 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
4967 /* Copy B Thumb instructions. */
4969 thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn,
4970 struct displaced_step_closure *dsc)
4972 unsigned int cond = 0;
4974 unsigned short bit_12_15 = bits (insn, 12, 15);
4975 CORE_ADDR from = dsc->insn_addr;
4977 if (bit_12_15 == 0xd)
4979 /* offset = SignExtend (imm8:0, 32) */
4980 offset = sbits ((insn << 1), 0, 8);
4981 cond = bits (insn, 8, 11);
4983 else if (bit_12_15 == 0xe) /* Encoding T2 */
4985 offset = sbits ((insn << 1), 0, 11);
4989 if (debug_displaced)
4990 fprintf_unfiltered (gdb_stdlog,
4991 "displaced: copying b immediate insn %.4x "
4992 "with offset %d\n", insn, offset);
4994 dsc->u.branch.cond = cond;
4995 dsc->u.branch.link = 0;
4996 dsc->u.branch.exchange = 0;
4997 dsc->u.branch.dest = from + 4 + offset;
4999 dsc->modinsn[0] = THUMB_NOP;
5001 dsc->cleanup = &cleanup_branch;
5006 /* Copy BX/BLX with register-specified destinations. */
5009 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5010 struct displaced_step_closure *dsc, int link,
5011 unsigned int cond, unsigned int rm)
5013 /* Implement {BX,BLX}<cond> <reg>" as:
5015 Preparation: cond <- instruction condition
5016 Insn: mov r0, r0 (nop)
5017 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5019 Don't set r14 in cleanup for BX. */
5021 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5023 dsc->u.branch.cond = cond;
5024 dsc->u.branch.link = link;
5026 dsc->u.branch.exchange = 1;
5028 dsc->cleanup = &cleanup_branch;
5032 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5033 struct regcache *regs, struct displaced_step_closure *dsc)
5035 unsigned int cond = bits (insn, 28, 31);
5038 int link = bit (insn, 5);
5039 unsigned int rm = bits (insn, 0, 3);
5041 if (debug_displaced)
5042 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5043 (unsigned long) insn);
5045 dsc->modinsn[0] = ARM_NOP;
5047 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5052 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
5053 struct regcache *regs,
5054 struct displaced_step_closure *dsc)
5056 int link = bit (insn, 7);
5057 unsigned int rm = bits (insn, 3, 6);
5059 if (debug_displaced)
5060 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
5061 (unsigned short) insn);
5063 dsc->modinsn[0] = THUMB_NOP;
5065 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
5071 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5074 cleanup_alu_imm (struct gdbarch *gdbarch,
5075 struct regcache *regs, struct displaced_step_closure *dsc)
5077 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5078 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5079 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5080 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5084 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5085 struct displaced_step_closure *dsc)
5087 unsigned int rn = bits (insn, 16, 19);
5088 unsigned int rd = bits (insn, 12, 15);
5089 unsigned int op = bits (insn, 21, 24);
5090 int is_mov = (op == 0xd);
5091 ULONGEST rd_val, rn_val;
5093 if (!insn_references_pc (insn, 0x000ff000ul))
5094 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5096 if (debug_displaced)
5097 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5098 "%.8lx\n", is_mov ? "move" : "ALU",
5099 (unsigned long) insn);
5101 /* Instruction is of form:
5103 <op><cond> rd, [rn,] #imm
5107 Preparation: tmp1, tmp2 <- r0, r1;
5109 Insn: <op><cond> r0, r1, #imm
5110 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5113 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5114 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5115 rn_val = displaced_read_reg (regs, dsc, rn);
5116 rd_val = displaced_read_reg (regs, dsc, rd);
5117 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5118 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5122 dsc->modinsn[0] = insn & 0xfff00fff;
5124 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5126 dsc->cleanup = &cleanup_alu_imm;
5132 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
5133 uint16_t insn2, struct regcache *regs,
5134 struct displaced_step_closure *dsc)
5136 unsigned int op = bits (insn1, 5, 8);
5137 unsigned int rn, rm, rd;
5138 ULONGEST rd_val, rn_val;
5140 rn = bits (insn1, 0, 3); /* Rn */
5141 rm = bits (insn2, 0, 3); /* Rm */
5142 rd = bits (insn2, 8, 11); /* Rd */
5144 /* This routine is only called for instruction MOV. */
5145 gdb_assert (op == 0x2 && rn == 0xf);
5147 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
5148 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
5150 if (debug_displaced)
5151 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
5152 "ALU", insn1, insn2);
5154 /* Instruction is of form:
5156 <op><cond> rd, [rn,] #imm
5160 Preparation: tmp1, tmp2 <- r0, r1;
5162 Insn: <op><cond> r0, r1, #imm
5163 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5166 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5167 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5168 rn_val = displaced_read_reg (regs, dsc, rn);
5169 rd_val = displaced_read_reg (regs, dsc, rd);
5170 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5171 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5174 dsc->modinsn[0] = insn1;
5175 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
5178 dsc->cleanup = &cleanup_alu_imm;
5183 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5186 cleanup_alu_reg (struct gdbarch *gdbarch,
5187 struct regcache *regs, struct displaced_step_closure *dsc)
5192 rd_val = displaced_read_reg (regs, dsc, 0);
5194 for (i = 0; i < 3; i++)
5195 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5197 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5201 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
5202 struct displaced_step_closure *dsc,
5203 unsigned int rd, unsigned int rn, unsigned int rm)
5205 ULONGEST rd_val, rn_val, rm_val;
5207 /* Instruction is of form:
5209 <op><cond> rd, [rn,] rm [, <shift>]
5213 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5214 r0, r1, r2 <- rd, rn, rm
5215 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5216 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5219 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5220 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5221 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5222 rd_val = displaced_read_reg (regs, dsc, rd);
5223 rn_val = displaced_read_reg (regs, dsc, rn);
5224 rm_val = displaced_read_reg (regs, dsc, rm);
5225 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5226 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5227 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5230 dsc->cleanup = &cleanup_alu_reg;
5234 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5235 struct displaced_step_closure *dsc)
5237 unsigned int op = bits (insn, 21, 24);
5238 int is_mov = (op == 0xd);
5240 if (!insn_references_pc (insn, 0x000ff00ful))
5241 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
5243 if (debug_displaced)
5244 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
5245 is_mov ? "move" : "ALU", (unsigned long) insn);
5248 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
5250 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
5252 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
5258 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
5259 struct regcache *regs,
5260 struct displaced_step_closure *dsc)
5264 rm = bits (insn, 3, 6);
5265 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
5267 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
5268 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
5270 if (debug_displaced)
5271 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
5272 (unsigned short) insn);
5274 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
5276 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
5281 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5284 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
5285 struct regcache *regs,
5286 struct displaced_step_closure *dsc)
5288 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5291 for (i = 0; i < 4; i++)
5292 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5294 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5298 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
5299 struct displaced_step_closure *dsc,
5300 unsigned int rd, unsigned int rn, unsigned int rm,
5304 ULONGEST rd_val, rn_val, rm_val, rs_val;
5306 /* Instruction is of form:
5308 <op><cond> rd, [rn,] rm, <shift> rs
5312 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5313 r0, r1, r2, r3 <- rd, rn, rm, rs
5314 Insn: <op><cond> r0, r1, r2, <shift> r3
5316 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5320 for (i = 0; i < 4; i++)
5321 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5323 rd_val = displaced_read_reg (regs, dsc, rd);
5324 rn_val = displaced_read_reg (regs, dsc, rn);
5325 rm_val = displaced_read_reg (regs, dsc, rm);
5326 rs_val = displaced_read_reg (regs, dsc, rs);
5327 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5328 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5329 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5330 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
5332 dsc->cleanup = &cleanup_alu_shifted_reg;
5336 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
5337 struct regcache *regs,
5338 struct displaced_step_closure *dsc)
5340 unsigned int op = bits (insn, 21, 24);
5341 int is_mov = (op == 0xd);
5342 unsigned int rd, rn, rm, rs;
5344 if (!insn_references_pc (insn, 0x000fff0ful))
5345 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
5347 if (debug_displaced)
5348 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
5349 "%.8lx\n", is_mov ? "move" : "ALU",
5350 (unsigned long) insn);
5352 rn = bits (insn, 16, 19);
5353 rm = bits (insn, 0, 3);
5354 rs = bits (insn, 8, 11);
5355 rd = bits (insn, 12, 15);
5358 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
5360 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
5362 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
5367 /* Clean up load instructions. */
5370 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
5371 struct displaced_step_closure *dsc)
5373 ULONGEST rt_val, rt_val2 = 0, rn_val;
5375 rt_val = displaced_read_reg (regs, dsc, 0);
5376 if (dsc->u.ldst.xfersize == 8)
5377 rt_val2 = displaced_read_reg (regs, dsc, 1);
5378 rn_val = displaced_read_reg (regs, dsc, 2);
5380 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5381 if (dsc->u.ldst.xfersize > 4)
5382 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5383 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5384 if (!dsc->u.ldst.immed)
5385 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5387 /* Handle register writeback. */
5388 if (dsc->u.ldst.writeback)
5389 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5390 /* Put result in right place. */
5391 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
5392 if (dsc->u.ldst.xfersize == 8)
5393 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5396 /* Clean up store instructions. */
5399 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5400 struct displaced_step_closure *dsc)
5402 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
5404 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5405 if (dsc->u.ldst.xfersize > 4)
5406 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5407 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5408 if (!dsc->u.ldst.immed)
5409 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5410 if (!dsc->u.ldst.restore_r4)
5411 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5414 if (dsc->u.ldst.writeback)
5415 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5418 /* Copy "extra" load/store instructions. These are halfword/doubleword
5419 transfers, which have a different encoding to byte/word transfers. */
5422 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged,
5423 struct regcache *regs, struct displaced_step_closure *dsc)
5425 unsigned int op1 = bits (insn, 20, 24);
5426 unsigned int op2 = bits (insn, 5, 6);
5427 unsigned int rt = bits (insn, 12, 15);
5428 unsigned int rn = bits (insn, 16, 19);
5429 unsigned int rm = bits (insn, 0, 3);
5430 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5431 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5432 int immed = (op1 & 0x4) != 0;
5434 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5436 if (!insn_references_pc (insn, 0x000ff00ful))
5437 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5439 if (debug_displaced)
5440 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5441 "insn %.8lx\n", unprivileged ? "unprivileged " : "",
5442 (unsigned long) insn);
5444 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5447 internal_error (__FILE__, __LINE__,
5448 _("copy_extra_ld_st: instruction decode error"));
5450 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5451 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5452 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5454 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5456 rt_val = displaced_read_reg (regs, dsc, rt);
5457 if (bytesize[opcode] == 8)
5458 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
5459 rn_val = displaced_read_reg (regs, dsc, rn);
5461 rm_val = displaced_read_reg (regs, dsc, rm);
5463 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5464 if (bytesize[opcode] == 8)
5465 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5466 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5468 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5471 dsc->u.ldst.xfersize = bytesize[opcode];
5472 dsc->u.ldst.rn = rn;
5473 dsc->u.ldst.immed = immed;
5474 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5475 dsc->u.ldst.restore_r4 = 0;
5478 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5480 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5481 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5483 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5485 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5486 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5488 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5493 /* Copy byte/half word/word loads and stores. */
5496 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5497 struct displaced_step_closure *dsc, int load,
5498 int immed, int writeback, int size, int usermode,
5499 int rt, int rm, int rn)
5501 ULONGEST rt_val, rn_val, rm_val = 0;
5503 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5504 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5506 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5508 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
5510 rt_val = displaced_read_reg (regs, dsc, rt);
5511 rn_val = displaced_read_reg (regs, dsc, rn);
5513 rm_val = displaced_read_reg (regs, dsc, rm);
5515 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5516 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5518 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5520 dsc->u.ldst.xfersize = size;
5521 dsc->u.ldst.rn = rn;
5522 dsc->u.ldst.immed = immed;
5523 dsc->u.ldst.writeback = writeback;
5525 /* To write PC we can do:
5527 Before this sequence of instructions:
5528 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5529 r2 is the Rn value got from dispalced_read_reg.
5531 Insn1: push {pc} Write address of STR instruction + offset on stack
5532 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5533 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5534 = addr(Insn1) + offset - addr(Insn3) - 8
5536 Insn4: add r4, r4, #8 r4 = offset - 8
5537 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5539 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5541 Otherwise we don't know what value to write for PC, since the offset is
5542 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5543 of this can be found in Section "Saving from r15" in
5544 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5546 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5551 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
5552 uint16_t insn2, struct regcache *regs,
5553 struct displaced_step_closure *dsc, int size)
5555 unsigned int u_bit = bit (insn1, 7);
5556 unsigned int rt = bits (insn2, 12, 15);
5557 int imm12 = bits (insn2, 0, 11);
5560 if (debug_displaced)
5561 fprintf_unfiltered (gdb_stdlog,
5562 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5563 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
5569 /* Rewrite instruction LDR Rt imm12 into:
5571 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5575 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5578 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5579 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5580 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5582 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5584 pc_val = pc_val & 0xfffffffc;
5586 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
5587 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
5591 dsc->u.ldst.xfersize = size;
5592 dsc->u.ldst.immed = 0;
5593 dsc->u.ldst.writeback = 0;
5594 dsc->u.ldst.restore_r4 = 0;
5596 /* LDR R0, R2, R3 */
5597 dsc->modinsn[0] = 0xf852;
5598 dsc->modinsn[1] = 0x3;
5601 dsc->cleanup = &cleanup_load;
5607 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
5608 uint16_t insn2, struct regcache *regs,
5609 struct displaced_step_closure *dsc,
5610 int writeback, int immed)
5612 unsigned int rt = bits (insn2, 12, 15);
5613 unsigned int rn = bits (insn1, 0, 3);
5614 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
5615 /* In LDR (register), there is also a register Rm, which is not allowed to
5616 be PC, so we don't have to check it. */
5618 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
5619 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
5622 if (debug_displaced)
5623 fprintf_unfiltered (gdb_stdlog,
5624 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5625 rt, rn, insn1, insn2);
5627 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
5630 dsc->u.ldst.restore_r4 = 0;
5633 /* ldr[b]<cond> rt, [rn, #imm], etc.
5635 ldr[b]<cond> r0, [r2, #imm]. */
5637 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5638 dsc->modinsn[1] = insn2 & 0x0fff;
5641 /* ldr[b]<cond> rt, [rn, rm], etc.
5643 ldr[b]<cond> r0, [r2, r3]. */
5645 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5646 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
5656 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
5657 struct regcache *regs,
5658 struct displaced_step_closure *dsc,
5659 int load, int size, int usermode)
5661 int immed = !bit (insn, 25);
5662 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
5663 unsigned int rt = bits (insn, 12, 15);
5664 unsigned int rn = bits (insn, 16, 19);
5665 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
5667 if (!insn_references_pc (insn, 0x000ff00ful))
5668 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
5670 if (debug_displaced)
5671 fprintf_unfiltered (gdb_stdlog,
5672 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5673 load ? (size == 1 ? "ldrb" : "ldr")
5674 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
5676 (unsigned long) insn);
5678 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
5679 usermode, rt, rm, rn);
5681 if (load || rt != ARM_PC_REGNUM)
5683 dsc->u.ldst.restore_r4 = 0;
5686 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5688 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5689 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5691 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5693 {ldr,str}[b]<cond> r0, [r2, r3]. */
5694 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5698 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5699 dsc->u.ldst.restore_r4 = 1;
5700 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
5701 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
5702 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
5703 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
5704 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
5708 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
5710 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
5715 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5720 /* Cleanup LDM instructions with fully-populated register list. This is an
5721 unfortunate corner case: it's impossible to implement correctly by modifying
5722 the instruction. The issue is as follows: we have an instruction,
5726 which we must rewrite to avoid loading PC. A possible solution would be to
5727 do the load in two halves, something like (with suitable cleanup
5731 ldm[id][ab] r8!, {r0-r7}
5733 ldm[id][ab] r8, {r7-r14}
5736 but at present there's no suitable place for <temp>, since the scratch space
5737 is overwritten before the cleanup routine is called. For now, we simply
5738 emulate the instruction. */
5741 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
5742 struct displaced_step_closure *dsc)
5744 int inc = dsc->u.block.increment;
5745 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
5746 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
5747 uint32_t regmask = dsc->u.block.regmask;
5748 int regno = inc ? 0 : 15;
5749 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
5750 int exception_return = dsc->u.block.load && dsc->u.block.user
5751 && (regmask & 0x8000) != 0;
5752 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5753 int do_transfer = condition_true (dsc->u.block.cond, status);
5754 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5759 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5760 sensible we can do here. Complain loudly. */
5761 if (exception_return)
5762 error (_("Cannot single-step exception return"));
5764 /* We don't handle any stores here for now. */
5765 gdb_assert (dsc->u.block.load != 0);
5767 if (debug_displaced)
5768 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
5769 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
5770 dsc->u.block.increment ? "inc" : "dec",
5771 dsc->u.block.before ? "before" : "after");
5778 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
5781 while (regno >= 0 && (regmask & (1 << regno)) == 0)
5784 xfer_addr += bump_before;
5786 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
5787 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
5789 xfer_addr += bump_after;
5791 regmask &= ~(1 << regno);
5794 if (dsc->u.block.writeback)
5795 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
5799 /* Clean up an STM which included the PC in the register list. */
5802 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
5803 struct displaced_step_closure *dsc)
5805 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5806 int store_executed = condition_true (dsc->u.block.cond, status);
5807 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
5808 CORE_ADDR stm_insn_addr;
5811 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5813 /* If condition code fails, there's nothing else to do. */
5814 if (!store_executed)
5817 if (dsc->u.block.increment)
5819 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
5821 if (dsc->u.block.before)
5826 pc_stored_at = dsc->u.block.xfer_addr;
5828 if (dsc->u.block.before)
5832 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
5833 stm_insn_addr = dsc->scratch_base;
5834 offset = pc_val - stm_insn_addr;
5836 if (debug_displaced)
5837 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
5838 "STM instruction\n", offset);
5840 /* Rewrite the stored PC to the proper value for the non-displaced original
5842 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
5843 dsc->insn_addr + offset);
5846 /* Clean up an LDM which includes the PC in the register list. We clumped all
5847 the registers in the transferred list into a contiguous range r0...rX (to
5848 avoid loading PC directly and losing control of the debugged program), so we
5849 must undo that here. */
5852 cleanup_block_load_pc (struct gdbarch *gdbarch,
5853 struct regcache *regs,
5854 struct displaced_step_closure *dsc)
5856 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5857 int load_executed = condition_true (dsc->u.block.cond, status);
5858 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
5859 unsigned int regs_loaded = bitcount (mask);
5860 unsigned int num_to_shuffle = regs_loaded, clobbered;
5862 /* The method employed here will fail if the register list is fully populated
5863 (we need to avoid loading PC directly). */
5864 gdb_assert (num_to_shuffle < 16);
5869 clobbered = (1 << num_to_shuffle) - 1;
5871 while (num_to_shuffle > 0)
5873 if ((mask & (1 << write_reg)) != 0)
5875 unsigned int read_reg = num_to_shuffle - 1;
5877 if (read_reg != write_reg)
5879 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
5880 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
5881 if (debug_displaced)
5882 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
5883 "loaded register r%d to r%d\n"), read_reg,
5886 else if (debug_displaced)
5887 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
5888 "r%d already in the right place\n"),
5891 clobbered &= ~(1 << write_reg);
5899 /* Restore any registers we scribbled over. */
5900 for (write_reg = 0; clobbered != 0; write_reg++)
5902 if ((clobbered & (1 << write_reg)) != 0)
5904 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
5906 if (debug_displaced)
5907 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
5908 "clobbered register r%d\n"), write_reg);
5909 clobbered &= ~(1 << write_reg);
5913 /* Perform register writeback manually. */
5914 if (dsc->u.block.writeback)
5916 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
5918 if (dsc->u.block.increment)
5919 new_rn_val += regs_loaded * 4;
5921 new_rn_val -= regs_loaded * 4;
5923 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
5928 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
5929 in user-level code (in particular exception return, ldm rn, {...pc}^). */
5932 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
5933 struct regcache *regs,
5934 struct displaced_step_closure *dsc)
5936 int load = bit (insn, 20);
5937 int user = bit (insn, 22);
5938 int increment = bit (insn, 23);
5939 int before = bit (insn, 24);
5940 int writeback = bit (insn, 21);
5941 int rn = bits (insn, 16, 19);
5943 /* Block transfers which don't mention PC can be run directly
5945 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
5946 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
5948 if (rn == ARM_PC_REGNUM)
5950 warning (_("displaced: Unpredictable LDM or STM with "
5951 "base register r15"));
5952 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
5955 if (debug_displaced)
5956 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
5957 "%.8lx\n", (unsigned long) insn);
5959 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
5960 dsc->u.block.rn = rn;
5962 dsc->u.block.load = load;
5963 dsc->u.block.user = user;
5964 dsc->u.block.increment = increment;
5965 dsc->u.block.before = before;
5966 dsc->u.block.writeback = writeback;
5967 dsc->u.block.cond = bits (insn, 28, 31);
5969 dsc->u.block.regmask = insn & 0xffff;
5973 if ((insn & 0xffff) == 0xffff)
5975 /* LDM with a fully-populated register list. This case is
5976 particularly tricky. Implement for now by fully emulating the
5977 instruction (which might not behave perfectly in all cases, but
5978 these instructions should be rare enough for that not to matter
5980 dsc->modinsn[0] = ARM_NOP;
5982 dsc->cleanup = &cleanup_block_load_all;
5986 /* LDM of a list of registers which includes PC. Implement by
5987 rewriting the list of registers to be transferred into a
5988 contiguous chunk r0...rX before doing the transfer, then shuffling
5989 registers into the correct places in the cleanup routine. */
5990 unsigned int regmask = insn & 0xffff;
5991 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
5992 unsigned int to = 0, from = 0, i, new_rn;
5994 for (i = 0; i < num_in_list; i++)
5995 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5997 /* Writeback makes things complicated. We need to avoid clobbering
5998 the base register with one of the registers in our modified
5999 register list, but just using a different register can't work in
6002 ldm r14!, {r0-r13,pc}
6004 which would need to be rewritten as:
6008 but that can't work, because there's no free register for N.
6010 Solve this by turning off the writeback bit, and emulating
6011 writeback manually in the cleanup routine. */
6016 new_regmask = (1 << num_in_list) - 1;
6018 if (debug_displaced)
6019 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6020 "{..., pc}: original reg list %.4x, modified "
6021 "list %.4x\n"), rn, writeback ? "!" : "",
6022 (int) insn & 0xffff, new_regmask);
6024 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6026 dsc->cleanup = &cleanup_block_load_pc;
6031 /* STM of a list of registers which includes PC. Run the instruction
6032 as-is, but out of line: this will store the wrong value for the PC,
6033 so we must manually fix up the memory in the cleanup routine.
6034 Doing things this way has the advantage that we can auto-detect
6035 the offset of the PC write (which is architecture-dependent) in
6036 the cleanup routine. */
6037 dsc->modinsn[0] = insn;
6039 dsc->cleanup = &cleanup_block_store_pc;
6046 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6047 struct regcache *regs,
6048 struct displaced_step_closure *dsc)
6050 int rn = bits (insn1, 0, 3);
6051 int load = bit (insn1, 4);
6052 int writeback = bit (insn1, 5);
6054 /* Block transfers which don't mention PC can be run directly
6056 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
6057 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
6059 if (rn == ARM_PC_REGNUM)
6061 warning (_("displaced: Unpredictable LDM or STM with "
6062 "base register r15"));
6063 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6064 "unpredictable ldm/stm", dsc);
6067 if (debug_displaced)
6068 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6069 "%.4x%.4x\n", insn1, insn2);
6071 /* Clear bit 13, since it should be always zero. */
6072 dsc->u.block.regmask = (insn2 & 0xdfff);
6073 dsc->u.block.rn = rn;
6075 dsc->u.block.load = load;
6076 dsc->u.block.user = 0;
6077 dsc->u.block.increment = bit (insn1, 7);
6078 dsc->u.block.before = bit (insn1, 8);
6079 dsc->u.block.writeback = writeback;
6080 dsc->u.block.cond = INST_AL;
6081 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6085 if (dsc->u.block.regmask == 0xffff)
6087 /* This branch is impossible to happen. */
6092 unsigned int regmask = dsc->u.block.regmask;
6093 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
6094 unsigned int to = 0, from = 0, i, new_rn;
6096 for (i = 0; i < num_in_list; i++)
6097 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6102 new_regmask = (1 << num_in_list) - 1;
6104 if (debug_displaced)
6105 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6106 "{..., pc}: original reg list %.4x, modified "
6107 "list %.4x\n"), rn, writeback ? "!" : "",
6108 (int) dsc->u.block.regmask, new_regmask);
6110 dsc->modinsn[0] = insn1;
6111 dsc->modinsn[1] = (new_regmask & 0xffff);
6114 dsc->cleanup = &cleanup_block_load_pc;
6119 dsc->modinsn[0] = insn1;
6120 dsc->modinsn[1] = insn2;
6122 dsc->cleanup = &cleanup_block_store_pc;
6127 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6128 This is used to avoid a dependency on BFD's bfd_endian enum. */
6131 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len,
6134 return read_memory_unsigned_integer (memaddr, len,
6135 (enum bfd_endian) byte_order);
6138 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6141 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
6144 return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val);
6147 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6150 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self,
6156 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6159 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self)
6161 return arm_is_thumb (self->regcache);
6164 /* single_step() is called just before we want to resume the inferior,
6165 if we want to single-step it but there is no hardware or kernel
6166 single-step support. We find the target of the coming instructions
6167 and breakpoint them. */
6170 arm_software_single_step (struct frame_info *frame)
6172 struct regcache *regcache = get_current_regcache ();
6173 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6174 struct address_space *aspace = get_regcache_aspace (regcache);
6175 struct arm_get_next_pcs next_pcs_ctx;
6178 VEC (CORE_ADDR) *next_pcs = NULL;
6179 struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
6181 arm_get_next_pcs_ctor (&next_pcs_ctx,
6182 &arm_get_next_pcs_ops,
6183 gdbarch_byte_order (gdbarch),
6184 gdbarch_byte_order_for_code (gdbarch),
6188 next_pcs = arm_get_next_pcs (&next_pcs_ctx);
6190 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
6191 arm_insert_single_step_breakpoint (gdbarch, aspace, pc);
6193 do_cleanups (old_chain);
6198 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6199 for Linux, where some SVC instructions must be treated specially. */
6202 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6203 struct displaced_step_closure *dsc)
6205 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6207 if (debug_displaced)
6208 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6209 "%.8lx\n", (unsigned long) resume_addr);
6211 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6215 /* Common copy routine for svc instruciton. */
6218 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
6219 struct displaced_step_closure *dsc)
6221 /* Preparation: none.
6222 Insn: unmodified svc.
6223 Cleanup: pc <- insn_addr + insn_size. */
6225 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6227 dsc->wrote_to_pc = 1;
6229 /* Allow OS-specific code to override SVC handling. */
6230 if (dsc->u.svc.copy_svc_os)
6231 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6234 dsc->cleanup = &cleanup_svc;
6240 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6241 struct regcache *regs, struct displaced_step_closure *dsc)
6244 if (debug_displaced)
6245 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6246 (unsigned long) insn);
6248 dsc->modinsn[0] = insn;
6250 return install_svc (gdbarch, regs, dsc);
6254 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
6255 struct regcache *regs, struct displaced_step_closure *dsc)
6258 if (debug_displaced)
6259 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
6262 dsc->modinsn[0] = insn;
6264 return install_svc (gdbarch, regs, dsc);
6267 /* Copy undefined instructions. */
6270 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6271 struct displaced_step_closure *dsc)
6273 if (debug_displaced)
6274 fprintf_unfiltered (gdb_stdlog,
6275 "displaced: copying undefined insn %.8lx\n",
6276 (unsigned long) insn);
6278 dsc->modinsn[0] = insn;
6284 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6285 struct displaced_step_closure *dsc)
6288 if (debug_displaced)
6289 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
6290 "%.4x %.4x\n", (unsigned short) insn1,
6291 (unsigned short) insn2);
6293 dsc->modinsn[0] = insn1;
6294 dsc->modinsn[1] = insn2;
6300 /* Copy unpredictable instructions. */
6303 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
6304 struct displaced_step_closure *dsc)
6306 if (debug_displaced)
6307 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
6308 "%.8lx\n", (unsigned long) insn);
6310 dsc->modinsn[0] = insn;
6315 /* The decode_* functions are instruction decoding helpers. They mostly follow
6316 the presentation in the ARM ARM. */
6319 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
6320 struct regcache *regs,
6321 struct displaced_step_closure *dsc)
6323 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
6324 unsigned int rn = bits (insn, 16, 19);
6326 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
6327 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
6328 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
6329 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
6330 else if ((op1 & 0x60) == 0x20)
6331 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
6332 else if ((op1 & 0x71) == 0x40)
6333 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
6335 else if ((op1 & 0x77) == 0x41)
6336 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6337 else if ((op1 & 0x77) == 0x45)
6338 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
6339 else if ((op1 & 0x77) == 0x51)
6342 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6344 return arm_copy_unpred (gdbarch, insn, dsc);
6346 else if ((op1 & 0x77) == 0x55)
6347 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6348 else if (op1 == 0x57)
6351 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
6352 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
6353 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
6354 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
6355 default: return arm_copy_unpred (gdbarch, insn, dsc);
6357 else if ((op1 & 0x63) == 0x43)
6358 return arm_copy_unpred (gdbarch, insn, dsc);
6359 else if ((op2 & 0x1) == 0x0)
6360 switch (op1 & ~0x80)
6363 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6365 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
6366 case 0x71: case 0x75:
6368 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
6369 case 0x63: case 0x67: case 0x73: case 0x77:
6370 return arm_copy_unpred (gdbarch, insn, dsc);
6372 return arm_copy_undef (gdbarch, insn, dsc);
6375 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
6379 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
6380 struct regcache *regs,
6381 struct displaced_step_closure *dsc)
6383 if (bit (insn, 27) == 0)
6384 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
6385 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6386 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
6389 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
6392 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
6394 case 0x4: case 0x5: case 0x6: case 0x7:
6395 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6398 switch ((insn & 0xe00000) >> 21)
6400 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6402 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6405 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6408 return arm_copy_undef (gdbarch, insn, dsc);
6413 int rn_f = (bits (insn, 16, 19) == 0xf);
6414 switch ((insn & 0xe00000) >> 21)
6417 /* ldc/ldc2 imm (undefined for rn == pc). */
6418 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
6419 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6422 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6424 case 0x4: case 0x5: case 0x6: case 0x7:
6425 /* ldc/ldc2 lit (undefined for rn != pc). */
6426 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
6427 : arm_copy_undef (gdbarch, insn, dsc);
6430 return arm_copy_undef (gdbarch, insn, dsc);
6435 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
6438 if (bits (insn, 16, 19) == 0xf)
6440 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6442 return arm_copy_undef (gdbarch, insn, dsc);
6446 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6448 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6452 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6454 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6457 return arm_copy_undef (gdbarch, insn, dsc);
6461 /* Decode miscellaneous instructions in dp/misc encoding space. */
6464 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
6465 struct regcache *regs,
6466 struct displaced_step_closure *dsc)
6468 unsigned int op2 = bits (insn, 4, 6);
6469 unsigned int op = bits (insn, 21, 22);
6470 unsigned int op1 = bits (insn, 16, 19);
6475 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
6478 if (op == 0x1) /* bx. */
6479 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
6481 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
6483 return arm_copy_undef (gdbarch, insn, dsc);
6487 /* Not really supported. */
6488 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
6490 return arm_copy_undef (gdbarch, insn, dsc);
6494 return arm_copy_bx_blx_reg (gdbarch, insn,
6495 regs, dsc); /* blx register. */
6497 return arm_copy_undef (gdbarch, insn, dsc);
6500 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
6504 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
6506 /* Not really supported. */
6507 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
6510 return arm_copy_undef (gdbarch, insn, dsc);
6515 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
6516 struct regcache *regs,
6517 struct displaced_step_closure *dsc)
6520 switch (bits (insn, 20, 24))
6523 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
6526 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
6528 case 0x12: case 0x16:
6529 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
6532 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
6536 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
6538 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
6539 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
6540 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
6541 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
6542 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
6543 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
6544 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
6545 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
6546 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
6547 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
6548 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
6549 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
6550 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
6551 /* 2nd arg means "unprivileged". */
6552 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
6556 /* Should be unreachable. */
6561 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
6562 struct regcache *regs,
6563 struct displaced_step_closure *dsc)
6565 int a = bit (insn, 25), b = bit (insn, 4);
6566 uint32_t op1 = bits (insn, 20, 24);
6567 int rn_f = bits (insn, 16, 19) == 0xf;
6569 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
6570 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
6571 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
6572 else if ((!a && (op1 & 0x17) == 0x02)
6573 || (a && (op1 & 0x17) == 0x02 && !b))
6574 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
6575 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
6576 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
6577 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
6578 else if ((!a && (op1 & 0x17) == 0x03)
6579 || (a && (op1 & 0x17) == 0x03 && !b))
6580 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
6581 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
6582 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
6583 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
6584 else if ((!a && (op1 & 0x17) == 0x06)
6585 || (a && (op1 & 0x17) == 0x06 && !b))
6586 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
6587 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
6588 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
6589 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
6590 else if ((!a && (op1 & 0x17) == 0x07)
6591 || (a && (op1 & 0x17) == 0x07 && !b))
6592 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
6594 /* Should be unreachable. */
6599 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
6600 struct displaced_step_closure *dsc)
6602 switch (bits (insn, 20, 24))
6604 case 0x00: case 0x01: case 0x02: case 0x03:
6605 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
6607 case 0x04: case 0x05: case 0x06: case 0x07:
6608 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
6610 case 0x08: case 0x09: case 0x0a: case 0x0b:
6611 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6612 return arm_copy_unmodified (gdbarch, insn,
6613 "decode/pack/unpack/saturate/reverse", dsc);
6616 if (bits (insn, 5, 7) == 0) /* op2. */
6618 if (bits (insn, 12, 15) == 0xf)
6619 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
6621 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
6624 return arm_copy_undef (gdbarch, insn, dsc);
6626 case 0x1a: case 0x1b:
6627 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6628 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
6630 return arm_copy_undef (gdbarch, insn, dsc);
6632 case 0x1c: case 0x1d:
6633 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
6635 if (bits (insn, 0, 3) == 0xf)
6636 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
6638 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
6641 return arm_copy_undef (gdbarch, insn, dsc);
6643 case 0x1e: case 0x1f:
6644 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6645 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
6647 return arm_copy_undef (gdbarch, insn, dsc);
6650 /* Should be unreachable. */
6655 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn,
6656 struct regcache *regs,
6657 struct displaced_step_closure *dsc)
6660 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6662 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
6666 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
6667 struct regcache *regs,
6668 struct displaced_step_closure *dsc)
6670 unsigned int opcode = bits (insn, 20, 24);
6674 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6675 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
6677 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6678 case 0x12: case 0x16:
6679 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
6681 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6682 case 0x13: case 0x17:
6683 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
6685 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6686 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6687 /* Note: no writeback for these instructions. Bit 25 will always be
6688 zero though (via caller), so the following works OK. */
6689 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6692 /* Should be unreachable. */
6696 /* Decode shifted register instructions. */
6699 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
6700 uint16_t insn2, struct regcache *regs,
6701 struct displaced_step_closure *dsc)
6703 /* PC is only allowed to be used in instruction MOV. */
6705 unsigned int op = bits (insn1, 5, 8);
6706 unsigned int rn = bits (insn1, 0, 3);
6708 if (op == 0x2 && rn == 0xf) /* MOV */
6709 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
6711 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6712 "dp (shift reg)", dsc);
6716 /* Decode extension register load/store. Exactly the same as
6717 arm_decode_ext_reg_ld_st. */
6720 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
6721 uint16_t insn2, struct regcache *regs,
6722 struct displaced_step_closure *dsc)
6724 unsigned int opcode = bits (insn1, 4, 8);
6728 case 0x04: case 0x05:
6729 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6730 "vfp/neon vmov", dsc);
6732 case 0x08: case 0x0c: /* 01x00 */
6733 case 0x0a: case 0x0e: /* 01x10 */
6734 case 0x12: case 0x16: /* 10x10 */
6735 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6736 "vfp/neon vstm/vpush", dsc);
6738 case 0x09: case 0x0d: /* 01x01 */
6739 case 0x0b: case 0x0f: /* 01x11 */
6740 case 0x13: case 0x17: /* 10x11 */
6741 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6742 "vfp/neon vldm/vpop", dsc);
6744 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6745 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6747 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6748 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
6751 /* Should be unreachable. */
6756 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
6757 struct regcache *regs, struct displaced_step_closure *dsc)
6759 unsigned int op1 = bits (insn, 20, 25);
6760 int op = bit (insn, 4);
6761 unsigned int coproc = bits (insn, 8, 11);
6762 unsigned int rn = bits (insn, 16, 19);
6764 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
6765 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
6766 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
6767 && (coproc & 0xe) != 0xa)
6769 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6770 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
6771 && (coproc & 0xe) != 0xa)
6772 /* ldc/ldc2 imm/lit. */
6773 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6774 else if ((op1 & 0x3e) == 0x00)
6775 return arm_copy_undef (gdbarch, insn, dsc);
6776 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6777 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6778 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6779 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6780 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6781 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6782 else if ((op1 & 0x30) == 0x20 && !op)
6784 if ((coproc & 0xe) == 0xa)
6785 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6787 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6789 else if ((op1 & 0x30) == 0x20 && op)
6790 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6791 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6792 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6793 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6794 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6795 else if ((op1 & 0x30) == 0x30)
6796 return arm_copy_svc (gdbarch, insn, regs, dsc);
6798 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6802 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
6803 uint16_t insn2, struct regcache *regs,
6804 struct displaced_step_closure *dsc)
6806 unsigned int coproc = bits (insn2, 8, 11);
6807 unsigned int op1 = bits (insn1, 4, 9);
6808 unsigned int bit_5_8 = bits (insn1, 5, 8);
6809 unsigned int bit_9 = bit (insn1, 9);
6810 unsigned int bit_4 = bit (insn1, 4);
6811 unsigned int rn = bits (insn1, 0, 3);
6816 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6817 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6819 else if (bit_5_8 == 0) /* UNDEFINED. */
6820 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
6823 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6824 if ((coproc & 0xe) == 0xa)
6825 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
6827 else /* coproc is not 101x. */
6829 if (bit_4 == 0) /* STC/STC2. */
6830 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6832 else /* LDC/LDC2 {literal, immeidate}. */
6833 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
6839 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
6845 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
6846 struct displaced_step_closure *dsc, int rd)
6852 Preparation: Rd <- PC
6858 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6859 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
6863 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
6864 struct displaced_step_closure *dsc,
6865 int rd, unsigned int imm)
6868 /* Encoding T2: ADDS Rd, #imm */
6869 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
6871 install_pc_relative (gdbarch, regs, dsc, rd);
6877 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
6878 struct regcache *regs,
6879 struct displaced_step_closure *dsc)
6881 unsigned int rd = bits (insn, 8, 10);
6882 unsigned int imm8 = bits (insn, 0, 7);
6884 if (debug_displaced)
6885 fprintf_unfiltered (gdb_stdlog,
6886 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6889 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
6893 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
6894 uint16_t insn2, struct regcache *regs,
6895 struct displaced_step_closure *dsc)
6897 unsigned int rd = bits (insn2, 8, 11);
6898 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6899 extract raw immediate encoding rather than computing immediate. When
6900 generating ADD or SUB instruction, we can simply perform OR operation to
6901 set immediate into ADD. */
6902 unsigned int imm_3_8 = insn2 & 0x70ff;
6903 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
6905 if (debug_displaced)
6906 fprintf_unfiltered (gdb_stdlog,
6907 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
6908 rd, imm_i, imm_3_8, insn1, insn2);
6910 if (bit (insn1, 7)) /* Encoding T2 */
6912 /* Encoding T3: SUB Rd, Rd, #imm */
6913 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
6914 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
6916 else /* Encoding T3 */
6918 /* Encoding T3: ADD Rd, Rd, #imm */
6919 dsc->modinsn[0] = (0xf100 | rd | imm_i);
6920 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
6924 install_pc_relative (gdbarch, regs, dsc, rd);
6930 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1,
6931 struct regcache *regs,
6932 struct displaced_step_closure *dsc)
6934 unsigned int rt = bits (insn1, 8, 10);
6936 int imm8 = (bits (insn1, 0, 7) << 2);
6937 CORE_ADDR from = dsc->insn_addr;
6943 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
6945 Insn: LDR R0, [R2, R3];
6946 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
6948 if (debug_displaced)
6949 fprintf_unfiltered (gdb_stdlog,
6950 "displaced: copying thumb ldr r%d [pc #%d]\n"
6953 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6954 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6955 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6956 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6957 /* The assembler calculates the required value of the offset from the
6958 Align(PC,4) value of this instruction to the label. */
6959 pc = pc & 0xfffffffc;
6961 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
6962 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
6965 dsc->u.ldst.xfersize = 4;
6967 dsc->u.ldst.immed = 0;
6968 dsc->u.ldst.writeback = 0;
6969 dsc->u.ldst.restore_r4 = 0;
6971 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
6973 dsc->cleanup = &cleanup_load;
6978 /* Copy Thumb cbnz/cbz insruction. */
6981 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
6982 struct regcache *regs,
6983 struct displaced_step_closure *dsc)
6985 int non_zero = bit (insn1, 11);
6986 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
6987 CORE_ADDR from = dsc->insn_addr;
6988 int rn = bits (insn1, 0, 2);
6989 int rn_val = displaced_read_reg (regs, dsc, rn);
6991 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
6992 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
6993 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
6994 condition is false, let it be, cleanup_branch will do nothing. */
6995 if (dsc->u.branch.cond)
6997 dsc->u.branch.cond = INST_AL;
6998 dsc->u.branch.dest = from + 4 + imm5;
7001 dsc->u.branch.dest = from + 2;
7003 dsc->u.branch.link = 0;
7004 dsc->u.branch.exchange = 0;
7006 if (debug_displaced)
7007 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
7008 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
7009 rn, rn_val, insn1, dsc->u.branch.dest);
7011 dsc->modinsn[0] = THUMB_NOP;
7013 dsc->cleanup = &cleanup_branch;
7017 /* Copy Table Branch Byte/Halfword */
7019 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7020 uint16_t insn2, struct regcache *regs,
7021 struct displaced_step_closure *dsc)
7023 ULONGEST rn_val, rm_val;
7024 int is_tbh = bit (insn2, 4);
7025 CORE_ADDR halfwords = 0;
7026 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7028 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7029 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7035 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7036 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7042 target_read_memory (rn_val + rm_val, buf, 1);
7043 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7046 if (debug_displaced)
7047 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7048 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7049 (unsigned int) rn_val, (unsigned int) rm_val,
7050 (unsigned int) halfwords);
7052 dsc->u.branch.cond = INST_AL;
7053 dsc->u.branch.link = 0;
7054 dsc->u.branch.exchange = 0;
7055 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7057 dsc->cleanup = &cleanup_branch;
7063 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
7064 struct displaced_step_closure *dsc)
7067 int val = displaced_read_reg (regs, dsc, 7);
7068 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
7071 val = displaced_read_reg (regs, dsc, 8);
7072 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
7075 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
7080 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1,
7081 struct regcache *regs,
7082 struct displaced_step_closure *dsc)
7084 dsc->u.block.regmask = insn1 & 0x00ff;
7086 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7089 (1) register list is full, that is, r0-r7 are used.
7090 Prepare: tmp[0] <- r8
7092 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7093 MOV r8, r7; Move value of r7 to r8;
7094 POP {r7}; Store PC value into r7.
7096 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7098 (2) register list is not full, supposing there are N registers in
7099 register list (except PC, 0 <= N <= 7).
7100 Prepare: for each i, 0 - N, tmp[i] <- ri.
7102 POP {r0, r1, ...., rN};
7104 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7105 from tmp[] properly.
7107 if (debug_displaced)
7108 fprintf_unfiltered (gdb_stdlog,
7109 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7110 dsc->u.block.regmask, insn1);
7112 if (dsc->u.block.regmask == 0xff)
7114 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
7116 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
7117 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
7118 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
7121 dsc->cleanup = &cleanup_pop_pc_16bit_all;
7125 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
7126 unsigned int new_regmask, bit = 1;
7127 unsigned int to = 0, from = 0, i, new_rn;
7129 for (i = 0; i < num_in_list + 1; i++)
7130 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7132 new_regmask = (1 << (num_in_list + 1)) - 1;
7134 if (debug_displaced)
7135 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
7136 "{..., pc}: original reg list %.4x,"
7137 " modified list %.4x\n"),
7138 (int) dsc->u.block.regmask, new_regmask);
7140 dsc->u.block.regmask |= 0x8000;
7141 dsc->u.block.writeback = 0;
7142 dsc->u.block.cond = INST_AL;
7144 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
7146 dsc->cleanup = &cleanup_block_load_pc;
7153 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7154 struct regcache *regs,
7155 struct displaced_step_closure *dsc)
7157 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
7158 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
7161 /* 16-bit thumb instructions. */
7162 switch (op_bit_12_15)
7164 /* Shift (imme), add, subtract, move and compare. */
7165 case 0: case 1: case 2: case 3:
7166 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7167 "shift/add/sub/mov/cmp",
7171 switch (op_bit_10_11)
7173 case 0: /* Data-processing */
7174 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7178 case 1: /* Special data instructions and branch and exchange. */
7180 unsigned short op = bits (insn1, 7, 9);
7181 if (op == 6 || op == 7) /* BX or BLX */
7182 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
7183 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7184 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
7186 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
7190 default: /* LDR (literal) */
7191 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
7194 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7195 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
7198 if (op_bit_10_11 < 2) /* Generate PC-relative address */
7199 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
7200 else /* Generate SP-relative address */
7201 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
7203 case 11: /* Misc 16-bit instructions */
7205 switch (bits (insn1, 8, 11))
7207 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7208 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
7210 case 12: case 13: /* POP */
7211 if (bit (insn1, 8)) /* PC is in register list. */
7212 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
7214 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
7216 case 15: /* If-Then, and hints */
7217 if (bits (insn1, 0, 3))
7218 /* If-Then makes up to four following instructions conditional.
7219 IT instruction itself is not conditional, so handle it as a
7220 common unmodified instruction. */
7221 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
7224 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
7227 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
7232 if (op_bit_10_11 < 2) /* Store multiple registers */
7233 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
7234 else /* Load multiple registers */
7235 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
7237 case 13: /* Conditional branch and supervisor call */
7238 if (bits (insn1, 9, 11) != 7) /* conditional branch */
7239 err = thumb_copy_b (gdbarch, insn1, dsc);
7241 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
7243 case 14: /* Unconditional branch */
7244 err = thumb_copy_b (gdbarch, insn1, dsc);
7251 internal_error (__FILE__, __LINE__,
7252 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7256 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
7257 uint16_t insn1, uint16_t insn2,
7258 struct regcache *regs,
7259 struct displaced_step_closure *dsc)
7261 int rt = bits (insn2, 12, 15);
7262 int rn = bits (insn1, 0, 3);
7263 int op1 = bits (insn1, 7, 8);
7266 switch (bits (insn1, 5, 6))
7268 case 0: /* Load byte and memory hints */
7269 if (rt == 0xf) /* PLD/PLI */
7272 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7273 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
7275 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7280 if (rn == 0xf) /* LDRB/LDRSB (literal) */
7281 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7284 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7285 "ldrb{reg, immediate}/ldrbt",
7290 case 1: /* Load halfword and memory hints. */
7291 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
7292 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7293 "pld/unalloc memhint", dsc);
7297 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7300 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7304 case 2: /* Load word */
7306 int insn2_bit_8_11 = bits (insn2, 8, 11);
7309 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
7310 else if (op1 == 0x1) /* Encoding T3 */
7311 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
7313 else /* op1 == 0x0 */
7315 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
7316 /* LDR (immediate) */
7317 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7318 dsc, bit (insn2, 8), 1);
7319 else if (insn2_bit_8_11 == 0xe) /* LDRT */
7320 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7323 /* LDR (register) */
7324 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7330 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7337 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7338 uint16_t insn2, struct regcache *regs,
7339 struct displaced_step_closure *dsc)
7342 unsigned short op = bit (insn2, 15);
7343 unsigned int op1 = bits (insn1, 11, 12);
7349 switch (bits (insn1, 9, 10))
7354 /* Load/store {dual, execlusive}, table branch. */
7355 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
7356 && bits (insn2, 5, 7) == 0)
7357 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
7360 /* PC is not allowed to use in load/store {dual, exclusive}
7362 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7363 "load/store dual/ex", dsc);
7365 else /* load/store multiple */
7367 switch (bits (insn1, 7, 8))
7369 case 0: case 3: /* SRS, RFE */
7370 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7373 case 1: case 2: /* LDM/STM/PUSH/POP */
7374 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
7381 /* Data-processing (shift register). */
7382 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
7385 default: /* Coprocessor instructions. */
7386 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7391 case 2: /* op1 = 2 */
7392 if (op) /* Branch and misc control. */
7394 if (bit (insn2, 14) /* BLX/BL */
7395 || bit (insn2, 12) /* Unconditional branch */
7396 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
7397 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
7399 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7404 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
7406 int op = bits (insn1, 4, 8);
7407 int rn = bits (insn1, 0, 3);
7408 if ((op == 0 || op == 0xa) && rn == 0xf)
7409 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
7412 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7415 else /* Data processing (modified immeidate) */
7416 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7420 case 3: /* op1 = 3 */
7421 switch (bits (insn1, 9, 10))
7425 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
7427 else /* NEON Load/Store and Store single data item */
7428 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7429 "neon elt/struct load/store",
7432 case 1: /* op1 = 3, bits (9, 10) == 1 */
7433 switch (bits (insn1, 7, 8))
7435 case 0: case 1: /* Data processing (register) */
7436 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7439 case 2: /* Multiply and absolute difference */
7440 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7441 "mul/mua/diff", dsc);
7443 case 3: /* Long multiply and divide */
7444 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7449 default: /* Coprocessor instructions */
7450 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7459 internal_error (__FILE__, __LINE__,
7460 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7465 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7466 CORE_ADDR to, struct regcache *regs,
7467 struct displaced_step_closure *dsc)
7469 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7471 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
7473 if (debug_displaced)
7474 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
7475 "at %.8lx\n", insn1, (unsigned long) from);
7478 dsc->insn_size = thumb_insn_size (insn1);
7479 if (thumb_insn_size (insn1) == 4)
7482 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
7483 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
7486 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
7490 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7491 CORE_ADDR to, struct regcache *regs,
7492 struct displaced_step_closure *dsc)
7495 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7498 /* Most displaced instructions use a 1-instruction scratch space, so set this
7499 here and override below if/when necessary. */
7501 dsc->insn_addr = from;
7502 dsc->scratch_base = to;
7503 dsc->cleanup = NULL;
7504 dsc->wrote_to_pc = 0;
7506 if (!displaced_in_arm_mode (regs))
7507 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
7511 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
7512 if (debug_displaced)
7513 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
7514 "at %.8lx\n", (unsigned long) insn,
7515 (unsigned long) from);
7517 if ((insn & 0xf0000000) == 0xf0000000)
7518 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
7519 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
7521 case 0x0: case 0x1: case 0x2: case 0x3:
7522 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
7525 case 0x4: case 0x5: case 0x6:
7526 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
7530 err = arm_decode_media (gdbarch, insn, dsc);
7533 case 0x8: case 0x9: case 0xa: case 0xb:
7534 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
7537 case 0xc: case 0xd: case 0xe: case 0xf:
7538 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
7543 internal_error (__FILE__, __LINE__,
7544 _("arm_process_displaced_insn: Instruction decode error"));
7547 /* Actually set up the scratch space for a displaced instruction. */
7550 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
7551 CORE_ADDR to, struct displaced_step_closure *dsc)
7553 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7554 unsigned int i, len, offset;
7555 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7556 int size = dsc->is_thumb? 2 : 4;
7557 const gdb_byte *bkp_insn;
7560 /* Poke modified instruction(s). */
7561 for (i = 0; i < dsc->numinsns; i++)
7563 if (debug_displaced)
7565 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
7567 fprintf_unfiltered (gdb_stdlog, "%.8lx",
7570 fprintf_unfiltered (gdb_stdlog, "%.4x",
7571 (unsigned short)dsc->modinsn[i]);
7573 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
7574 (unsigned long) to + offset);
7577 write_memory_unsigned_integer (to + offset, size,
7578 byte_order_for_code,
7583 /* Choose the correct breakpoint instruction. */
7586 bkp_insn = tdep->thumb_breakpoint;
7587 len = tdep->thumb_breakpoint_size;
7591 bkp_insn = tdep->arm_breakpoint;
7592 len = tdep->arm_breakpoint_size;
7595 /* Put breakpoint afterwards. */
7596 write_memory (to + offset, bkp_insn, len);
7598 if (debug_displaced)
7599 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
7600 paddress (gdbarch, from), paddress (gdbarch, to));
7603 /* Entry point for cleaning things up after a displaced instruction has been
7607 arm_displaced_step_fixup (struct gdbarch *gdbarch,
7608 struct displaced_step_closure *dsc,
7609 CORE_ADDR from, CORE_ADDR to,
7610 struct regcache *regs)
7613 dsc->cleanup (gdbarch, regs, dsc);
7615 if (!dsc->wrote_to_pc)
7616 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
7617 dsc->insn_addr + dsc->insn_size);
7621 #include "bfd-in2.h"
7622 #include "libcoff.h"
7625 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
7627 struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
7629 if (arm_pc_is_thumb (gdbarch, memaddr))
7631 static asymbol *asym;
7632 static combined_entry_type ce;
7633 static struct coff_symbol_struct csym;
7634 static struct bfd fake_bfd;
7635 static bfd_target fake_target;
7637 if (csym.native == NULL)
7639 /* Create a fake symbol vector containing a Thumb symbol.
7640 This is solely so that the code in print_insn_little_arm()
7641 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7642 the presence of a Thumb symbol and switch to decoding
7643 Thumb instructions. */
7645 fake_target.flavour = bfd_target_coff_flavour;
7646 fake_bfd.xvec = &fake_target;
7647 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
7649 csym.symbol.the_bfd = &fake_bfd;
7650 csym.symbol.name = "fake";
7651 asym = (asymbol *) & csym;
7654 memaddr = UNMAKE_THUMB_ADDR (memaddr);
7655 info->symbols = &asym;
7658 info->symbols = NULL;
7660 if (info->endian == BFD_ENDIAN_BIG)
7661 return print_insn_big_arm (memaddr, info);
7663 return print_insn_little_arm (memaddr, info);
7666 /* The following define instruction sequences that will cause ARM
7667 cpu's to take an undefined instruction trap. These are used to
7668 signal a breakpoint to GDB.
7670 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7671 modes. A different instruction is required for each mode. The ARM
7672 cpu's can also be big or little endian. Thus four different
7673 instructions are needed to support all cases.
7675 Note: ARMv4 defines several new instructions that will take the
7676 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7677 not in fact add the new instructions. The new undefined
7678 instructions in ARMv4 are all instructions that had no defined
7679 behaviour in earlier chips. There is no guarantee that they will
7680 raise an exception, but may be treated as NOP's. In practice, it
7681 may only safe to rely on instructions matching:
7683 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7684 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7685 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7687 Even this may only true if the condition predicate is true. The
7688 following use a condition predicate of ALWAYS so it is always TRUE.
7690 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7691 and NetBSD all use a software interrupt rather than an undefined
7692 instruction to force a trap. This can be handled by by the
7693 abi-specific code during establishment of the gdbarch vector. */
7695 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7696 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7697 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7698 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7700 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
7701 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
7702 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
7703 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
7705 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7706 the program counter value to determine whether a 16-bit or 32-bit
7707 breakpoint should be used. It returns a pointer to a string of
7708 bytes that encode a breakpoint instruction, stores the length of
7709 the string to *lenptr, and adjusts the program counter (if
7710 necessary) to point to the actual memory location where the
7711 breakpoint should be inserted. */
7713 static const unsigned char *
7714 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
7716 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7717 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7719 if (arm_pc_is_thumb (gdbarch, *pcptr))
7721 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
7723 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7724 check whether we are replacing a 32-bit instruction. */
7725 if (tdep->thumb2_breakpoint != NULL)
7728 if (target_read_memory (*pcptr, buf, 2) == 0)
7730 unsigned short inst1;
7731 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
7732 if (thumb_insn_size (inst1) == 4)
7734 *lenptr = tdep->thumb2_breakpoint_size;
7735 return tdep->thumb2_breakpoint;
7740 *lenptr = tdep->thumb_breakpoint_size;
7741 return tdep->thumb_breakpoint;
7745 *lenptr = tdep->arm_breakpoint_size;
7746 return tdep->arm_breakpoint;
7751 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
7754 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
7756 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
7757 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7758 that this is not confused with a 32-bit ARM breakpoint. */
7762 /* Extract from an array REGBUF containing the (raw) register state a
7763 function return value of type TYPE, and copy that, in virtual
7764 format, into VALBUF. */
7767 arm_extract_return_value (struct type *type, struct regcache *regs,
7770 struct gdbarch *gdbarch = get_regcache_arch (regs);
7771 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7773 if (TYPE_CODE_FLT == TYPE_CODE (type))
7775 switch (gdbarch_tdep (gdbarch)->fp_model)
7779 /* The value is in register F0 in internal format. We need to
7780 extract the raw value and then convert it to the desired
7782 bfd_byte tmpbuf[FP_REGISTER_SIZE];
7784 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
7785 convert_from_extended (floatformat_from_type (type), tmpbuf,
7786 valbuf, gdbarch_byte_order (gdbarch));
7790 case ARM_FLOAT_SOFT_FPA:
7791 case ARM_FLOAT_SOFT_VFP:
7792 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7793 not using the VFP ABI code. */
7795 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
7796 if (TYPE_LENGTH (type) > 4)
7797 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7798 valbuf + INT_REGISTER_SIZE);
7802 internal_error (__FILE__, __LINE__,
7803 _("arm_extract_return_value: "
7804 "Floating point model not supported"));
7808 else if (TYPE_CODE (type) == TYPE_CODE_INT
7809 || TYPE_CODE (type) == TYPE_CODE_CHAR
7810 || TYPE_CODE (type) == TYPE_CODE_BOOL
7811 || TYPE_CODE (type) == TYPE_CODE_PTR
7812 || TYPE_CODE (type) == TYPE_CODE_REF
7813 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7815 /* If the type is a plain integer, then the access is
7816 straight-forward. Otherwise we have to play around a bit
7818 int len = TYPE_LENGTH (type);
7819 int regno = ARM_A1_REGNUM;
7824 /* By using store_unsigned_integer we avoid having to do
7825 anything special for small big-endian values. */
7826 regcache_cooked_read_unsigned (regs, regno++, &tmp);
7827 store_unsigned_integer (valbuf,
7828 (len > INT_REGISTER_SIZE
7829 ? INT_REGISTER_SIZE : len),
7831 len -= INT_REGISTER_SIZE;
7832 valbuf += INT_REGISTER_SIZE;
7837 /* For a structure or union the behaviour is as if the value had
7838 been stored to word-aligned memory and then loaded into
7839 registers with 32-bit load instruction(s). */
7840 int len = TYPE_LENGTH (type);
7841 int regno = ARM_A1_REGNUM;
7842 bfd_byte tmpbuf[INT_REGISTER_SIZE];
7846 regcache_cooked_read (regs, regno++, tmpbuf);
7847 memcpy (valbuf, tmpbuf,
7848 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
7849 len -= INT_REGISTER_SIZE;
7850 valbuf += INT_REGISTER_SIZE;
7856 /* Will a function return an aggregate type in memory or in a
7857 register? Return 0 if an aggregate type can be returned in a
7858 register, 1 if it must be returned in memory. */
7861 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
7863 enum type_code code;
7865 type = check_typedef (type);
7867 /* Simple, non-aggregate types (ie not including vectors and
7868 complex) are always returned in a register (or registers). */
7869 code = TYPE_CODE (type);
7870 if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code
7871 && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code)
7874 if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type))
7876 /* Vector values should be returned using ARM registers if they
7877 are not over 16 bytes. */
7878 return (TYPE_LENGTH (type) > 16);
7881 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
7883 /* The AAPCS says all aggregates not larger than a word are returned
7885 if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
7894 /* All aggregate types that won't fit in a register must be returned
7896 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
7899 /* In the ARM ABI, "integer" like aggregate types are returned in
7900 registers. For an aggregate type to be integer like, its size
7901 must be less than or equal to INT_REGISTER_SIZE and the
7902 offset of each addressable subfield must be zero. Note that bit
7903 fields are not addressable, and all addressable subfields of
7904 unions always start at offset zero.
7906 This function is based on the behaviour of GCC 2.95.1.
7907 See: gcc/arm.c: arm_return_in_memory() for details.
7909 Note: All versions of GCC before GCC 2.95.2 do not set up the
7910 parameters correctly for a function returning the following
7911 structure: struct { float f;}; This should be returned in memory,
7912 not a register. Richard Earnshaw sent me a patch, but I do not
7913 know of any way to detect if a function like the above has been
7914 compiled with the correct calling convention. */
7916 /* Assume all other aggregate types can be returned in a register.
7917 Run a check for structures, unions and arrays. */
7920 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
7923 /* Need to check if this struct/union is "integer" like. For
7924 this to be true, its size must be less than or equal to
7925 INT_REGISTER_SIZE and the offset of each addressable
7926 subfield must be zero. Note that bit fields are not
7927 addressable, and unions always start at offset zero. If any
7928 of the subfields is a floating point type, the struct/union
7929 cannot be an integer type. */
7931 /* For each field in the object, check:
7932 1) Is it FP? --> yes, nRc = 1;
7933 2) Is it addressable (bitpos != 0) and
7934 not packed (bitsize == 0)?
7938 for (i = 0; i < TYPE_NFIELDS (type); i++)
7940 enum type_code field_type_code;
7943 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
7946 /* Is it a floating point type field? */
7947 if (field_type_code == TYPE_CODE_FLT)
7953 /* If bitpos != 0, then we have to care about it. */
7954 if (TYPE_FIELD_BITPOS (type, i) != 0)
7956 /* Bitfields are not addressable. If the field bitsize is
7957 zero, then the field is not packed. Hence it cannot be
7958 a bitfield or any other packed type. */
7959 if (TYPE_FIELD_BITSIZE (type, i) == 0)
7972 /* Write into appropriate registers a function return value of type
7973 TYPE, given in virtual format. */
7976 arm_store_return_value (struct type *type, struct regcache *regs,
7977 const gdb_byte *valbuf)
7979 struct gdbarch *gdbarch = get_regcache_arch (regs);
7980 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7982 if (TYPE_CODE (type) == TYPE_CODE_FLT)
7984 gdb_byte buf[MAX_REGISTER_SIZE];
7986 switch (gdbarch_tdep (gdbarch)->fp_model)
7990 convert_to_extended (floatformat_from_type (type), buf, valbuf,
7991 gdbarch_byte_order (gdbarch));
7992 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
7995 case ARM_FLOAT_SOFT_FPA:
7996 case ARM_FLOAT_SOFT_VFP:
7997 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7998 not using the VFP ABI code. */
8000 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
8001 if (TYPE_LENGTH (type) > 4)
8002 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
8003 valbuf + INT_REGISTER_SIZE);
8007 internal_error (__FILE__, __LINE__,
8008 _("arm_store_return_value: Floating "
8009 "point model not supported"));
8013 else if (TYPE_CODE (type) == TYPE_CODE_INT
8014 || TYPE_CODE (type) == TYPE_CODE_CHAR
8015 || TYPE_CODE (type) == TYPE_CODE_BOOL
8016 || TYPE_CODE (type) == TYPE_CODE_PTR
8017 || TYPE_CODE (type) == TYPE_CODE_REF
8018 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8020 if (TYPE_LENGTH (type) <= 4)
8022 /* Values of one word or less are zero/sign-extended and
8024 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8025 LONGEST val = unpack_long (type, valbuf);
8027 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8028 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8032 /* Integral values greater than one word are stored in consecutive
8033 registers starting with r0. This will always be a multiple of
8034 the regiser size. */
8035 int len = TYPE_LENGTH (type);
8036 int regno = ARM_A1_REGNUM;
8040 regcache_cooked_write (regs, regno++, valbuf);
8041 len -= INT_REGISTER_SIZE;
8042 valbuf += INT_REGISTER_SIZE;
8048 /* For a structure or union the behaviour is as if the value had
8049 been stored to word-aligned memory and then loaded into
8050 registers with 32-bit load instruction(s). */
8051 int len = TYPE_LENGTH (type);
8052 int regno = ARM_A1_REGNUM;
8053 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8057 memcpy (tmpbuf, valbuf,
8058 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8059 regcache_cooked_write (regs, regno++, tmpbuf);
8060 len -= INT_REGISTER_SIZE;
8061 valbuf += INT_REGISTER_SIZE;
8067 /* Handle function return values. */
8069 static enum return_value_convention
8070 arm_return_value (struct gdbarch *gdbarch, struct value *function,
8071 struct type *valtype, struct regcache *regcache,
8072 gdb_byte *readbuf, const gdb_byte *writebuf)
8074 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8075 struct type *func_type = function ? value_type (function) : NULL;
8076 enum arm_vfp_cprc_base_type vfp_base_type;
8079 if (arm_vfp_abi_for_function (gdbarch, func_type)
8080 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
8082 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
8083 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
8085 for (i = 0; i < vfp_base_count; i++)
8087 if (reg_char == 'q')
8090 arm_neon_quad_write (gdbarch, regcache, i,
8091 writebuf + i * unit_length);
8094 arm_neon_quad_read (gdbarch, regcache, i,
8095 readbuf + i * unit_length);
8102 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
8103 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8106 regcache_cooked_write (regcache, regnum,
8107 writebuf + i * unit_length);
8109 regcache_cooked_read (regcache, regnum,
8110 readbuf + i * unit_length);
8113 return RETURN_VALUE_REGISTER_CONVENTION;
8116 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
8117 || TYPE_CODE (valtype) == TYPE_CODE_UNION
8118 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
8120 if (tdep->struct_return == pcc_struct_return
8121 || arm_return_in_memory (gdbarch, valtype))
8122 return RETURN_VALUE_STRUCT_CONVENTION;
8124 else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX)
8126 if (arm_return_in_memory (gdbarch, valtype))
8127 return RETURN_VALUE_STRUCT_CONVENTION;
8131 arm_store_return_value (valtype, regcache, writebuf);
8134 arm_extract_return_value (valtype, regcache, readbuf);
8136 return RETURN_VALUE_REGISTER_CONVENTION;
8141 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
8143 struct gdbarch *gdbarch = get_frame_arch (frame);
8144 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8145 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8147 gdb_byte buf[INT_REGISTER_SIZE];
8149 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
8151 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
8155 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
8159 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8160 return the target PC. Otherwise return 0. */
8163 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
8167 CORE_ADDR start_addr;
8169 /* Find the starting address and name of the function containing the PC. */
8170 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
8172 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8174 start_addr = arm_skip_bx_reg (frame, pc);
8175 if (start_addr != 0)
8181 /* If PC is in a Thumb call or return stub, return the address of the
8182 target PC, which is in a register. The thunk functions are called
8183 _call_via_xx, where x is the register name. The possible names
8184 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8185 functions, named __ARM_call_via_r[0-7]. */
8186 if (startswith (name, "_call_via_")
8187 || startswith (name, "__ARM_call_via_"))
8189 /* Use the name suffix to determine which register contains the
8191 static char *table[15] =
8192 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8193 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8196 int offset = strlen (name) - 2;
8198 for (regno = 0; regno <= 14; regno++)
8199 if (strcmp (&name[offset], table[regno]) == 0)
8200 return get_frame_register_unsigned (frame, regno);
8203 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8204 non-interworking calls to foo. We could decode the stubs
8205 to find the target but it's easier to use the symbol table. */
8206 namelen = strlen (name);
8207 if (name[0] == '_' && name[1] == '_'
8208 && ((namelen > 2 + strlen ("_from_thumb")
8209 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
8210 || (namelen > 2 + strlen ("_from_arm")
8211 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
8214 int target_len = namelen - 2;
8215 struct bound_minimal_symbol minsym;
8216 struct objfile *objfile;
8217 struct obj_section *sec;
8219 if (name[namelen - 1] == 'b')
8220 target_len -= strlen ("_from_thumb");
8222 target_len -= strlen ("_from_arm");
8224 target_name = (char *) alloca (target_len + 1);
8225 memcpy (target_name, name + 2, target_len);
8226 target_name[target_len] = '\0';
8228 sec = find_pc_section (pc);
8229 objfile = (sec == NULL) ? NULL : sec->objfile;
8230 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
8231 if (minsym.minsym != NULL)
8232 return BMSYMBOL_VALUE_ADDRESS (minsym);
8237 return 0; /* not a stub */
8241 set_arm_command (char *args, int from_tty)
8243 printf_unfiltered (_("\
8244 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8245 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
8249 show_arm_command (char *args, int from_tty)
8251 cmd_show_list (showarmcmdlist, from_tty, "");
8255 arm_update_current_architecture (void)
8257 struct gdbarch_info info;
8259 /* If the current architecture is not ARM, we have nothing to do. */
8260 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
8263 /* Update the architecture. */
8264 gdbarch_info_init (&info);
8266 if (!gdbarch_update_p (info))
8267 internal_error (__FILE__, __LINE__, _("could not update architecture"));
8271 set_fp_model_sfunc (char *args, int from_tty,
8272 struct cmd_list_element *c)
8276 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
8277 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
8279 arm_fp_model = (enum arm_float_model) fp_model;
8283 if (fp_model == ARM_FLOAT_LAST)
8284 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
8287 arm_update_current_architecture ();
8291 show_fp_model (struct ui_file *file, int from_tty,
8292 struct cmd_list_element *c, const char *value)
8294 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8296 if (arm_fp_model == ARM_FLOAT_AUTO
8297 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8298 fprintf_filtered (file, _("\
8299 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8300 fp_model_strings[tdep->fp_model]);
8302 fprintf_filtered (file, _("\
8303 The current ARM floating point model is \"%s\".\n"),
8304 fp_model_strings[arm_fp_model]);
8308 arm_set_abi (char *args, int from_tty,
8309 struct cmd_list_element *c)
8313 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
8314 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
8316 arm_abi_global = (enum arm_abi_kind) arm_abi;
8320 if (arm_abi == ARM_ABI_LAST)
8321 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
8324 arm_update_current_architecture ();
8328 arm_show_abi (struct ui_file *file, int from_tty,
8329 struct cmd_list_element *c, const char *value)
8331 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8333 if (arm_abi_global == ARM_ABI_AUTO
8334 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8335 fprintf_filtered (file, _("\
8336 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8337 arm_abi_strings[tdep->arm_abi]);
8339 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
8344 arm_show_fallback_mode (struct ui_file *file, int from_tty,
8345 struct cmd_list_element *c, const char *value)
8347 fprintf_filtered (file,
8348 _("The current execution mode assumed "
8349 "(when symbols are unavailable) is \"%s\".\n"),
8350 arm_fallback_mode_string);
8354 arm_show_force_mode (struct ui_file *file, int from_tty,
8355 struct cmd_list_element *c, const char *value)
8357 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8359 fprintf_filtered (file,
8360 _("The current execution mode assumed "
8361 "(even when symbols are available) is \"%s\".\n"),
8362 arm_force_mode_string);
8365 /* If the user changes the register disassembly style used for info
8366 register and other commands, we have to also switch the style used
8367 in opcodes for disassembly output. This function is run in the "set
8368 arm disassembly" command, and does that. */
8371 set_disassembly_style_sfunc (char *args, int from_tty,
8372 struct cmd_list_element *c)
8374 set_disassembly_style ();
8377 /* Return the ARM register name corresponding to register I. */
8379 arm_register_name (struct gdbarch *gdbarch, int i)
8381 const int num_regs = gdbarch_num_regs (gdbarch);
8383 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
8384 && i >= num_regs && i < num_regs + 32)
8386 static const char *const vfp_pseudo_names[] = {
8387 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8388 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8389 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8390 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8393 return vfp_pseudo_names[i - num_regs];
8396 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
8397 && i >= num_regs + 32 && i < num_regs + 32 + 16)
8399 static const char *const neon_pseudo_names[] = {
8400 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8401 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8404 return neon_pseudo_names[i - num_regs - 32];
8407 if (i >= ARRAY_SIZE (arm_register_names))
8408 /* These registers are only supported on targets which supply
8409 an XML description. */
8412 return arm_register_names[i];
8416 set_disassembly_style (void)
8420 /* Find the style that the user wants. */
8421 for (current = 0; current < num_disassembly_options; current++)
8422 if (disassembly_style == valid_disassembly_styles[current])
8424 gdb_assert (current < num_disassembly_options);
8426 /* Synchronize the disassembler. */
8427 set_arm_regname_option (current);
8430 /* Test whether the coff symbol specific value corresponds to a Thumb
8434 coff_sym_is_thumb (int val)
8436 return (val == C_THUMBEXT
8437 || val == C_THUMBSTAT
8438 || val == C_THUMBEXTFUNC
8439 || val == C_THUMBSTATFUNC
8440 || val == C_THUMBLABEL);
8443 /* arm_coff_make_msymbol_special()
8444 arm_elf_make_msymbol_special()
8446 These functions test whether the COFF or ELF symbol corresponds to
8447 an address in thumb code, and set a "special" bit in a minimal
8448 symbol to indicate that it does. */
8451 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
8453 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
8454 == ST_BRANCH_TO_THUMB)
8455 MSYMBOL_SET_SPECIAL (msym);
8459 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
8461 if (coff_sym_is_thumb (val))
8462 MSYMBOL_SET_SPECIAL (msym);
8466 arm_objfile_data_free (struct objfile *objfile, void *arg)
8468 struct arm_per_objfile *data = (struct arm_per_objfile *) arg;
8471 for (i = 0; i < objfile->obfd->section_count; i++)
8472 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
8476 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
8479 const char *name = bfd_asymbol_name (sym);
8480 struct arm_per_objfile *data;
8481 VEC(arm_mapping_symbol_s) **map_p;
8482 struct arm_mapping_symbol new_map_sym;
8484 gdb_assert (name[0] == '$');
8485 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
8488 data = (struct arm_per_objfile *) objfile_data (objfile,
8489 arm_objfile_data_key);
8492 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
8493 struct arm_per_objfile);
8494 set_objfile_data (objfile, arm_objfile_data_key, data);
8495 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
8496 objfile->obfd->section_count,
8497 VEC(arm_mapping_symbol_s) *);
8499 map_p = &data->section_maps[bfd_get_section (sym)->index];
8501 new_map_sym.value = sym->value;
8502 new_map_sym.type = name[1];
8504 /* Assume that most mapping symbols appear in order of increasing
8505 value. If they were randomly distributed, it would be faster to
8506 always push here and then sort at first use. */
8507 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
8509 struct arm_mapping_symbol *prev_map_sym;
8511 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
8512 if (prev_map_sym->value >= sym->value)
8515 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
8516 arm_compare_mapping_symbols);
8517 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
8522 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
8526 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
8528 struct gdbarch *gdbarch = get_regcache_arch (regcache);
8529 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
8531 /* If necessary, set the T bit. */
8534 ULONGEST val, t_bit;
8535 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
8536 t_bit = arm_psr_thumb_bit (gdbarch);
8537 if (arm_pc_is_thumb (gdbarch, pc))
8538 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8541 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8546 /* Read the contents of a NEON quad register, by reading from two
8547 double registers. This is used to implement the quad pseudo
8548 registers, and for argument passing in case the quad registers are
8549 missing; vectors are passed in quad registers when using the VFP
8550 ABI, even if a NEON unit is not present. REGNUM is the index of
8551 the quad register, in [0, 15]. */
8553 static enum register_status
8554 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
8555 int regnum, gdb_byte *buf)
8558 gdb_byte reg_buf[8];
8559 int offset, double_regnum;
8560 enum register_status status;
8562 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8563 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8566 /* d0 is always the least significant half of q0. */
8567 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8572 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8573 if (status != REG_VALID)
8575 memcpy (buf + offset, reg_buf, 8);
8577 offset = 8 - offset;
8578 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
8579 if (status != REG_VALID)
8581 memcpy (buf + offset, reg_buf, 8);
8586 static enum register_status
8587 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
8588 int regnum, gdb_byte *buf)
8590 const int num_regs = gdbarch_num_regs (gdbarch);
8592 gdb_byte reg_buf[8];
8593 int offset, double_regnum;
8595 gdb_assert (regnum >= num_regs);
8598 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8599 /* Quad-precision register. */
8600 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
8603 enum register_status status;
8605 /* Single-precision register. */
8606 gdb_assert (regnum < 32);
8608 /* s0 is always the least significant half of d0. */
8609 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8610 offset = (regnum & 1) ? 0 : 4;
8612 offset = (regnum & 1) ? 4 : 0;
8614 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8615 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8618 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8619 if (status == REG_VALID)
8620 memcpy (buf, reg_buf + offset, 4);
8625 /* Store the contents of BUF to a NEON quad register, by writing to
8626 two double registers. This is used to implement the quad pseudo
8627 registers, and for argument passing in case the quad registers are
8628 missing; vectors are passed in quad registers when using the VFP
8629 ABI, even if a NEON unit is not present. REGNUM is the index
8630 of the quad register, in [0, 15]. */
8633 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
8634 int regnum, const gdb_byte *buf)
8637 int offset, double_regnum;
8639 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8640 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8643 /* d0 is always the least significant half of q0. */
8644 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8649 regcache_raw_write (regcache, double_regnum, buf + offset);
8650 offset = 8 - offset;
8651 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
8655 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
8656 int regnum, const gdb_byte *buf)
8658 const int num_regs = gdbarch_num_regs (gdbarch);
8660 gdb_byte reg_buf[8];
8661 int offset, double_regnum;
8663 gdb_assert (regnum >= num_regs);
8666 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8667 /* Quad-precision register. */
8668 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
8671 /* Single-precision register. */
8672 gdb_assert (regnum < 32);
8674 /* s0 is always the least significant half of d0. */
8675 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8676 offset = (regnum & 1) ? 0 : 4;
8678 offset = (regnum & 1) ? 4 : 0;
8680 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8681 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8684 regcache_raw_read (regcache, double_regnum, reg_buf);
8685 memcpy (reg_buf + offset, buf, 4);
8686 regcache_raw_write (regcache, double_regnum, reg_buf);
8690 static struct value *
8691 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
8693 const int *reg_p = (const int *) baton;
8694 return value_of_register (*reg_p, frame);
8697 static enum gdb_osabi
8698 arm_elf_osabi_sniffer (bfd *abfd)
8700 unsigned int elfosabi;
8701 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
8703 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
8705 if (elfosabi == ELFOSABI_ARM)
8706 /* GNU tools use this value. Check note sections in this case,
8708 bfd_map_over_sections (abfd,
8709 generic_elf_osabi_sniff_abi_tag_sections,
8712 /* Anything else will be handled by the generic ELF sniffer. */
8717 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
8718 struct reggroup *group)
8720 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8721 this, FPS register belongs to save_regroup, restore_reggroup, and
8722 all_reggroup, of course. */
8723 if (regnum == ARM_FPS_REGNUM)
8724 return (group == float_reggroup
8725 || group == save_reggroup
8726 || group == restore_reggroup
8727 || group == all_reggroup);
8729 return default_register_reggroup_p (gdbarch, regnum, group);
8733 /* For backward-compatibility we allow two 'g' packet lengths with
8734 the remote protocol depending on whether FPA registers are
8735 supplied. M-profile targets do not have FPA registers, but some
8736 stubs already exist in the wild which use a 'g' packet which
8737 supplies them albeit with dummy values. The packet format which
8738 includes FPA registers should be considered deprecated for
8739 M-profile targets. */
8742 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
8744 if (gdbarch_tdep (gdbarch)->is_m)
8746 /* If we know from the executable this is an M-profile target,
8747 cater for remote targets whose register set layout is the
8748 same as the FPA layout. */
8749 register_remote_g_packet_guess (gdbarch,
8750 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8751 (16 * INT_REGISTER_SIZE)
8752 + (8 * FP_REGISTER_SIZE)
8753 + (2 * INT_REGISTER_SIZE),
8754 tdesc_arm_with_m_fpa_layout);
8756 /* The regular M-profile layout. */
8757 register_remote_g_packet_guess (gdbarch,
8758 /* r0-r12,sp,lr,pc; xpsr */
8759 (16 * INT_REGISTER_SIZE)
8760 + INT_REGISTER_SIZE,
8763 /* M-profile plus M4F VFP. */
8764 register_remote_g_packet_guess (gdbarch,
8765 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8766 (16 * INT_REGISTER_SIZE)
8767 + (16 * VFP_REGISTER_SIZE)
8768 + (2 * INT_REGISTER_SIZE),
8769 tdesc_arm_with_m_vfp_d16);
8772 /* Otherwise we don't have a useful guess. */
8776 /* Initialize the current architecture based on INFO. If possible,
8777 re-use an architecture from ARCHES, which is a list of
8778 architectures already created during this debugging session.
8780 Called e.g. at program startup, when reading a core file, and when
8781 reading a binary file. */
8783 static struct gdbarch *
8784 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8786 struct gdbarch_tdep *tdep;
8787 struct gdbarch *gdbarch;
8788 struct gdbarch_list *best_arch;
8789 enum arm_abi_kind arm_abi = arm_abi_global;
8790 enum arm_float_model fp_model = arm_fp_model;
8791 struct tdesc_arch_data *tdesc_data = NULL;
8793 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
8794 int have_wmmx_registers = 0;
8796 int have_fpa_registers = 1;
8797 const struct target_desc *tdesc = info.target_desc;
8799 /* If we have an object to base this architecture on, try to determine
8802 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
8804 int ei_osabi, e_flags;
8806 switch (bfd_get_flavour (info.abfd))
8808 case bfd_target_aout_flavour:
8809 /* Assume it's an old APCS-style ABI. */
8810 arm_abi = ARM_ABI_APCS;
8813 case bfd_target_coff_flavour:
8814 /* Assume it's an old APCS-style ABI. */
8816 arm_abi = ARM_ABI_APCS;
8819 case bfd_target_elf_flavour:
8820 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
8821 e_flags = elf_elfheader (info.abfd)->e_flags;
8823 if (ei_osabi == ELFOSABI_ARM)
8825 /* GNU tools used to use this value, but do not for EABI
8826 objects. There's nowhere to tag an EABI version
8827 anyway, so assume APCS. */
8828 arm_abi = ARM_ABI_APCS;
8830 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
8832 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
8833 int attr_arch, attr_profile;
8837 case EF_ARM_EABI_UNKNOWN:
8838 /* Assume GNU tools. */
8839 arm_abi = ARM_ABI_APCS;
8842 case EF_ARM_EABI_VER4:
8843 case EF_ARM_EABI_VER5:
8844 arm_abi = ARM_ABI_AAPCS;
8845 /* EABI binaries default to VFP float ordering.
8846 They may also contain build attributes that can
8847 be used to identify if the VFP argument-passing
8849 if (fp_model == ARM_FLOAT_AUTO)
8852 switch (bfd_elf_get_obj_attr_int (info.abfd,
8856 case AEABI_VFP_args_base:
8857 /* "The user intended FP parameter/result
8858 passing to conform to AAPCS, base
8860 fp_model = ARM_FLOAT_SOFT_VFP;
8862 case AEABI_VFP_args_vfp:
8863 /* "The user intended FP parameter/result
8864 passing to conform to AAPCS, VFP
8866 fp_model = ARM_FLOAT_VFP;
8868 case AEABI_VFP_args_toolchain:
8869 /* "The user intended FP parameter/result
8870 passing to conform to tool chain-specific
8871 conventions" - we don't know any such
8872 conventions, so leave it as "auto". */
8874 case AEABI_VFP_args_compatible:
8875 /* "Code is compatible with both the base
8876 and VFP variants; the user did not permit
8877 non-variadic functions to pass FP
8878 parameters/results" - leave it as
8882 /* Attribute value not mentioned in the
8883 November 2012 ABI, so leave it as
8888 fp_model = ARM_FLOAT_SOFT_VFP;
8894 /* Leave it as "auto". */
8895 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
8900 /* Detect M-profile programs. This only works if the
8901 executable file includes build attributes; GCC does
8902 copy them to the executable, but e.g. RealView does
8904 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
8906 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
8908 Tag_CPU_arch_profile);
8909 /* GCC specifies the profile for v6-M; RealView only
8910 specifies the profile for architectures starting with
8911 V7 (as opposed to architectures with a tag
8912 numerically greater than TAG_CPU_ARCH_V7). */
8913 if (!tdesc_has_registers (tdesc)
8914 && (attr_arch == TAG_CPU_ARCH_V6_M
8915 || attr_arch == TAG_CPU_ARCH_V6S_M
8916 || attr_profile == 'M'))
8921 if (fp_model == ARM_FLOAT_AUTO)
8923 int e_flags = elf_elfheader (info.abfd)->e_flags;
8925 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
8928 /* Leave it as "auto". Strictly speaking this case
8929 means FPA, but almost nobody uses that now, and
8930 many toolchains fail to set the appropriate bits
8931 for the floating-point model they use. */
8933 case EF_ARM_SOFT_FLOAT:
8934 fp_model = ARM_FLOAT_SOFT_FPA;
8936 case EF_ARM_VFP_FLOAT:
8937 fp_model = ARM_FLOAT_VFP;
8939 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
8940 fp_model = ARM_FLOAT_SOFT_VFP;
8945 if (e_flags & EF_ARM_BE8)
8946 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
8951 /* Leave it as "auto". */
8956 /* Check any target description for validity. */
8957 if (tdesc_has_registers (tdesc))
8959 /* For most registers we require GDB's default names; but also allow
8960 the numeric names for sp / lr / pc, as a convenience. */
8961 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
8962 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
8963 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
8965 const struct tdesc_feature *feature;
8968 feature = tdesc_find_feature (tdesc,
8969 "org.gnu.gdb.arm.core");
8970 if (feature == NULL)
8972 feature = tdesc_find_feature (tdesc,
8973 "org.gnu.gdb.arm.m-profile");
8974 if (feature == NULL)
8980 tdesc_data = tdesc_data_alloc ();
8983 for (i = 0; i < ARM_SP_REGNUM; i++)
8984 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8985 arm_register_names[i]);
8986 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8989 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8992 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8996 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8997 ARM_PS_REGNUM, "xpsr");
8999 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9000 ARM_PS_REGNUM, "cpsr");
9004 tdesc_data_cleanup (tdesc_data);
9008 feature = tdesc_find_feature (tdesc,
9009 "org.gnu.gdb.arm.fpa");
9010 if (feature != NULL)
9013 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9014 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9015 arm_register_names[i]);
9018 tdesc_data_cleanup (tdesc_data);
9023 have_fpa_registers = 0;
9025 feature = tdesc_find_feature (tdesc,
9026 "org.gnu.gdb.xscale.iwmmxt");
9027 if (feature != NULL)
9029 static const char *const iwmmxt_names[] = {
9030 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9031 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9032 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9033 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9037 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9039 &= tdesc_numbered_register (feature, tdesc_data, i,
9040 iwmmxt_names[i - ARM_WR0_REGNUM]);
9042 /* Check for the control registers, but do not fail if they
9044 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9045 tdesc_numbered_register (feature, tdesc_data, i,
9046 iwmmxt_names[i - ARM_WR0_REGNUM]);
9048 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9050 &= tdesc_numbered_register (feature, tdesc_data, i,
9051 iwmmxt_names[i - ARM_WR0_REGNUM]);
9055 tdesc_data_cleanup (tdesc_data);
9059 have_wmmx_registers = 1;
9062 /* If we have a VFP unit, check whether the single precision registers
9063 are present. If not, then we will synthesize them as pseudo
9065 feature = tdesc_find_feature (tdesc,
9066 "org.gnu.gdb.arm.vfp");
9067 if (feature != NULL)
9069 static const char *const vfp_double_names[] = {
9070 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9071 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9072 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9073 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9076 /* Require the double precision registers. There must be either
9079 for (i = 0; i < 32; i++)
9081 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9083 vfp_double_names[i]);
9087 if (!valid_p && i == 16)
9090 /* Also require FPSCR. */
9091 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9092 ARM_FPSCR_REGNUM, "fpscr");
9095 tdesc_data_cleanup (tdesc_data);
9099 if (tdesc_unnumbered_register (feature, "s0") == 0)
9100 have_vfp_pseudos = 1;
9102 vfp_register_count = i;
9104 /* If we have VFP, also check for NEON. The architecture allows
9105 NEON without VFP (integer vector operations only), but GDB
9106 does not support that. */
9107 feature = tdesc_find_feature (tdesc,
9108 "org.gnu.gdb.arm.neon");
9109 if (feature != NULL)
9111 /* NEON requires 32 double-precision registers. */
9114 tdesc_data_cleanup (tdesc_data);
9118 /* If there are quad registers defined by the stub, use
9119 their type; otherwise (normally) provide them with
9120 the default type. */
9121 if (tdesc_unnumbered_register (feature, "q0") == 0)
9122 have_neon_pseudos = 1;
9129 /* If there is already a candidate, use it. */
9130 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
9132 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
9134 if (arm_abi != ARM_ABI_AUTO
9135 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
9138 if (fp_model != ARM_FLOAT_AUTO
9139 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
9142 /* There are various other properties in tdep that we do not
9143 need to check here: those derived from a target description,
9144 since gdbarches with a different target description are
9145 automatically disqualified. */
9147 /* Do check is_m, though, since it might come from the binary. */
9148 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
9151 /* Found a match. */
9155 if (best_arch != NULL)
9157 if (tdesc_data != NULL)
9158 tdesc_data_cleanup (tdesc_data);
9159 return best_arch->gdbarch;
9162 tdep = XCNEW (struct gdbarch_tdep);
9163 gdbarch = gdbarch_alloc (&info, tdep);
9165 /* Record additional information about the architecture we are defining.
9166 These are gdbarch discriminators, like the OSABI. */
9167 tdep->arm_abi = arm_abi;
9168 tdep->fp_model = fp_model;
9170 tdep->have_fpa_registers = have_fpa_registers;
9171 tdep->have_wmmx_registers = have_wmmx_registers;
9172 gdb_assert (vfp_register_count == 0
9173 || vfp_register_count == 16
9174 || vfp_register_count == 32);
9175 tdep->vfp_register_count = vfp_register_count;
9176 tdep->have_vfp_pseudos = have_vfp_pseudos;
9177 tdep->have_neon_pseudos = have_neon_pseudos;
9178 tdep->have_neon = have_neon;
9180 arm_register_g_packet_guesses (gdbarch);
9183 switch (info.byte_order_for_code)
9185 case BFD_ENDIAN_BIG:
9186 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
9187 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
9188 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
9189 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
9193 case BFD_ENDIAN_LITTLE:
9194 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
9195 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
9196 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
9197 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
9202 internal_error (__FILE__, __LINE__,
9203 _("arm_gdbarch_init: bad byte order for float format"));
9206 /* On ARM targets char defaults to unsigned. */
9207 set_gdbarch_char_signed (gdbarch, 0);
9209 /* Note: for displaced stepping, this includes the breakpoint, and one word
9210 of additional scratch space. This setting isn't used for anything beside
9211 displaced stepping at present. */
9212 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
9214 /* This should be low enough for everything. */
9215 tdep->lowest_pc = 0x20;
9216 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
9218 /* The default, for both APCS and AAPCS, is to return small
9219 structures in registers. */
9220 tdep->struct_return = reg_struct_return;
9222 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
9223 set_gdbarch_frame_align (gdbarch, arm_frame_align);
9225 set_gdbarch_write_pc (gdbarch, arm_write_pc);
9227 /* Frame handling. */
9228 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
9229 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
9230 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
9232 frame_base_set_default (gdbarch, &arm_normal_base);
9234 /* Address manipulation. */
9235 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
9237 /* Advance PC across function entry code. */
9238 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
9240 /* Detect whether PC is at a point where the stack has been destroyed. */
9241 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
9243 /* Skip trampolines. */
9244 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
9246 /* The stack grows downward. */
9247 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
9249 /* Breakpoint manipulation. */
9250 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
9251 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
9252 arm_remote_breakpoint_from_pc);
9254 /* Information about registers, etc. */
9255 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
9256 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
9257 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
9258 set_gdbarch_register_type (gdbarch, arm_register_type);
9259 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
9261 /* This "info float" is FPA-specific. Use the generic version if we
9263 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
9264 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
9266 /* Internal <-> external register number maps. */
9267 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
9268 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
9270 set_gdbarch_register_name (gdbarch, arm_register_name);
9272 /* Returning results. */
9273 set_gdbarch_return_value (gdbarch, arm_return_value);
9276 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
9278 /* Minsymbol frobbing. */
9279 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
9280 set_gdbarch_coff_make_msymbol_special (gdbarch,
9281 arm_coff_make_msymbol_special);
9282 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
9284 /* Thumb-2 IT block support. */
9285 set_gdbarch_adjust_breakpoint_address (gdbarch,
9286 arm_adjust_breakpoint_address);
9288 /* Virtual tables. */
9289 set_gdbarch_vbit_in_delta (gdbarch, 1);
9291 /* Hook in the ABI-specific overrides, if they have been registered. */
9292 gdbarch_init_osabi (info, gdbarch);
9294 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
9296 /* Add some default predicates. */
9298 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
9299 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
9300 dwarf2_append_unwinders (gdbarch);
9301 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
9302 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
9304 /* Now we have tuned the configuration, set a few final things,
9305 based on what the OS ABI has told us. */
9307 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9308 binaries are always marked. */
9309 if (tdep->arm_abi == ARM_ABI_AUTO)
9310 tdep->arm_abi = ARM_ABI_APCS;
9312 /* Watchpoints are not steppable. */
9313 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9315 /* We used to default to FPA for generic ARM, but almost nobody
9316 uses that now, and we now provide a way for the user to force
9317 the model. So default to the most useful variant. */
9318 if (tdep->fp_model == ARM_FLOAT_AUTO)
9319 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
9321 if (tdep->jb_pc >= 0)
9322 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
9324 /* Floating point sizes and format. */
9325 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
9326 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
9328 set_gdbarch_double_format
9329 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9330 set_gdbarch_long_double_format
9331 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9335 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
9336 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
9339 if (have_vfp_pseudos)
9341 /* NOTE: These are the only pseudo registers used by
9342 the ARM target at the moment. If more are added, a
9343 little more care in numbering will be needed. */
9345 int num_pseudos = 32;
9346 if (have_neon_pseudos)
9348 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
9349 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
9350 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
9355 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
9357 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
9359 /* Override tdesc_register_type to adjust the types of VFP
9360 registers for NEON. */
9361 set_gdbarch_register_type (gdbarch, arm_register_type);
9364 /* Add standard register aliases. We add aliases even for those
9365 nanes which are used by the current architecture - it's simpler,
9366 and does no harm, since nothing ever lists user registers. */
9367 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
9368 user_reg_add (gdbarch, arm_register_aliases[i].name,
9369 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
9375 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
9377 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9382 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9383 (unsigned long) tdep->lowest_pc);
9386 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
9389 _initialize_arm_tdep (void)
9391 struct ui_file *stb;
9393 struct cmd_list_element *new_set, *new_show;
9394 const char *setname;
9395 const char *setdesc;
9396 const char *const *regnames;
9398 static char *helptext;
9399 char regdesc[1024], *rdptr = regdesc;
9400 size_t rest = sizeof (regdesc);
9402 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
9404 arm_objfile_data_key
9405 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
9407 /* Add ourselves to objfile event chain. */
9408 observer_attach_new_objfile (arm_exidx_new_objfile);
9410 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
9412 /* Register an ELF OS ABI sniffer for ARM binaries. */
9413 gdbarch_register_osabi_sniffer (bfd_arch_arm,
9414 bfd_target_elf_flavour,
9415 arm_elf_osabi_sniffer);
9417 /* Initialize the standard target descriptions. */
9418 initialize_tdesc_arm_with_m ();
9419 initialize_tdesc_arm_with_m_fpa_layout ();
9420 initialize_tdesc_arm_with_m_vfp_d16 ();
9421 initialize_tdesc_arm_with_iwmmxt ();
9422 initialize_tdesc_arm_with_vfpv2 ();
9423 initialize_tdesc_arm_with_vfpv3 ();
9424 initialize_tdesc_arm_with_neon ();
9426 /* Get the number of possible sets of register names defined in opcodes. */
9427 num_disassembly_options = get_arm_regname_num_options ();
9429 /* Add root prefix command for all "set arm"/"show arm" commands. */
9430 add_prefix_cmd ("arm", no_class, set_arm_command,
9431 _("Various ARM-specific commands."),
9432 &setarmcmdlist, "set arm ", 0, &setlist);
9434 add_prefix_cmd ("arm", no_class, show_arm_command,
9435 _("Various ARM-specific commands."),
9436 &showarmcmdlist, "show arm ", 0, &showlist);
9438 /* Sync the opcode insn printer with our register viewer. */
9439 parse_arm_disassembler_option ("reg-names-std");
9441 /* Initialize the array that will be passed to
9442 add_setshow_enum_cmd(). */
9443 valid_disassembly_styles = XNEWVEC (const char *,
9444 num_disassembly_options + 1);
9445 for (i = 0; i < num_disassembly_options; i++)
9447 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
9448 valid_disassembly_styles[i] = setname;
9449 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
9452 /* When we find the default names, tell the disassembler to use
9454 if (!strcmp (setname, "std"))
9456 disassembly_style = setname;
9457 set_arm_regname_option (i);
9460 /* Mark the end of valid options. */
9461 valid_disassembly_styles[num_disassembly_options] = NULL;
9463 /* Create the help text. */
9464 stb = mem_fileopen ();
9465 fprintf_unfiltered (stb, "%s%s%s",
9466 _("The valid values are:\n"),
9468 _("The default is \"std\"."));
9469 helptext = ui_file_xstrdup (stb, NULL);
9470 ui_file_delete (stb);
9472 add_setshow_enum_cmd("disassembler", no_class,
9473 valid_disassembly_styles, &disassembly_style,
9474 _("Set the disassembly style."),
9475 _("Show the disassembly style."),
9477 set_disassembly_style_sfunc,
9478 NULL, /* FIXME: i18n: The disassembly style is
9480 &setarmcmdlist, &showarmcmdlist);
9482 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
9483 _("Set usage of ARM 32-bit mode."),
9484 _("Show usage of ARM 32-bit mode."),
9485 _("When off, a 26-bit PC will be used."),
9487 NULL, /* FIXME: i18n: Usage of ARM 32-bit
9489 &setarmcmdlist, &showarmcmdlist);
9491 /* Add a command to allow the user to force the FPU model. */
9492 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
9493 _("Set the floating point type."),
9494 _("Show the floating point type."),
9495 _("auto - Determine the FP typefrom the OS-ABI.\n\
9496 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9497 fpa - FPA co-processor (GCC compiled).\n\
9498 softvfp - Software FP with pure-endian doubles.\n\
9499 vfp - VFP co-processor."),
9500 set_fp_model_sfunc, show_fp_model,
9501 &setarmcmdlist, &showarmcmdlist);
9503 /* Add a command to allow the user to force the ABI. */
9504 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
9507 NULL, arm_set_abi, arm_show_abi,
9508 &setarmcmdlist, &showarmcmdlist);
9510 /* Add two commands to allow the user to force the assumed
9512 add_setshow_enum_cmd ("fallback-mode", class_support,
9513 arm_mode_strings, &arm_fallback_mode_string,
9514 _("Set the mode assumed when symbols are unavailable."),
9515 _("Show the mode assumed when symbols are unavailable."),
9516 NULL, NULL, arm_show_fallback_mode,
9517 &setarmcmdlist, &showarmcmdlist);
9518 add_setshow_enum_cmd ("force-mode", class_support,
9519 arm_mode_strings, &arm_force_mode_string,
9520 _("Set the mode assumed even when symbols are available."),
9521 _("Show the mode assumed even when symbols are available."),
9522 NULL, NULL, arm_show_force_mode,
9523 &setarmcmdlist, &showarmcmdlist);
9525 /* Debugging flag. */
9526 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
9527 _("Set ARM debugging."),
9528 _("Show ARM debugging."),
9529 _("When on, arm-specific debugging is enabled."),
9531 NULL, /* FIXME: i18n: "ARM debugging is %s. */
9532 &setdebuglist, &showdebuglist);
9535 /* ARM-reversible process record data structures. */
9537 #define ARM_INSN_SIZE_BYTES 4
9538 #define THUMB_INSN_SIZE_BYTES 2
9539 #define THUMB2_INSN_SIZE_BYTES 4
9542 /* Position of the bit within a 32-bit ARM instruction
9543 that defines whether the instruction is a load or store. */
9544 #define INSN_S_L_BIT_NUM 20
9546 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9549 unsigned int reg_len = LENGTH; \
9552 REGS = XNEWVEC (uint32_t, reg_len); \
9553 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9558 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9561 unsigned int mem_len = LENGTH; \
9564 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9565 memcpy(&MEMS->len, &RECORD_BUF[0], \
9566 sizeof(struct arm_mem_r) * LENGTH); \
9571 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9572 #define INSN_RECORDED(ARM_RECORD) \
9573 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9575 /* ARM memory record structure. */
9578 uint32_t len; /* Record length. */
9579 uint32_t addr; /* Memory address. */
9582 /* ARM instruction record contains opcode of current insn
9583 and execution state (before entry to decode_insn()),
9584 contains list of to-be-modified registers and
9585 memory blocks (on return from decode_insn()). */
9587 typedef struct insn_decode_record_t
9589 struct gdbarch *gdbarch;
9590 struct regcache *regcache;
9591 CORE_ADDR this_addr; /* Address of the insn being decoded. */
9592 uint32_t arm_insn; /* Should accommodate thumb. */
9593 uint32_t cond; /* Condition code. */
9594 uint32_t opcode; /* Insn opcode. */
9595 uint32_t decode; /* Insn decode bits. */
9596 uint32_t mem_rec_count; /* No of mem records. */
9597 uint32_t reg_rec_count; /* No of reg records. */
9598 uint32_t *arm_regs; /* Registers to be saved for this record. */
9599 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
9600 } insn_decode_record;
9603 /* Checks ARM SBZ and SBO mandatory fields. */
9606 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
9608 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
9627 enum arm_record_result
9629 ARM_RECORD_SUCCESS = 0,
9630 ARM_RECORD_FAILURE = 1
9637 } arm_record_strx_t;
9648 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
9649 uint32_t *record_buf_mem, arm_record_strx_t str_type)
9652 struct regcache *reg_cache = arm_insn_r->regcache;
9653 ULONGEST u_regval[2]= {0};
9655 uint32_t reg_src1 = 0, reg_src2 = 0;
9656 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
9657 uint32_t opcode1 = 0;
9659 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
9660 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
9661 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
9664 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
9666 /* 1) Handle misc store, immediate offset. */
9667 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9668 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9669 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9670 regcache_raw_read_unsigned (reg_cache, reg_src1,
9672 if (ARM_PC_REGNUM == reg_src1)
9674 /* If R15 was used as Rn, hence current PC+8. */
9675 u_regval[0] = u_regval[0] + 8;
9677 offset_8 = (immed_high << 4) | immed_low;
9678 /* Calculate target store address. */
9679 if (14 == arm_insn_r->opcode)
9681 tgt_mem_addr = u_regval[0] + offset_8;
9685 tgt_mem_addr = u_regval[0] - offset_8;
9687 if (ARM_RECORD_STRH == str_type)
9689 record_buf_mem[0] = 2;
9690 record_buf_mem[1] = tgt_mem_addr;
9691 arm_insn_r->mem_rec_count = 1;
9693 else if (ARM_RECORD_STRD == str_type)
9695 record_buf_mem[0] = 4;
9696 record_buf_mem[1] = tgt_mem_addr;
9697 record_buf_mem[2] = 4;
9698 record_buf_mem[3] = tgt_mem_addr + 4;
9699 arm_insn_r->mem_rec_count = 2;
9702 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
9704 /* 2) Store, register offset. */
9706 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9708 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9709 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9710 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9713 /* If R15 was used as Rn, hence current PC+8. */
9714 u_regval[0] = u_regval[0] + 8;
9716 /* Calculate target store address, Rn +/- Rm, register offset. */
9717 if (12 == arm_insn_r->opcode)
9719 tgt_mem_addr = u_regval[0] + u_regval[1];
9723 tgt_mem_addr = u_regval[1] - u_regval[0];
9725 if (ARM_RECORD_STRH == str_type)
9727 record_buf_mem[0] = 2;
9728 record_buf_mem[1] = tgt_mem_addr;
9729 arm_insn_r->mem_rec_count = 1;
9731 else if (ARM_RECORD_STRD == str_type)
9733 record_buf_mem[0] = 4;
9734 record_buf_mem[1] = tgt_mem_addr;
9735 record_buf_mem[2] = 4;
9736 record_buf_mem[3] = tgt_mem_addr + 4;
9737 arm_insn_r->mem_rec_count = 2;
9740 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
9741 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9743 /* 3) Store, immediate pre-indexed. */
9744 /* 5) Store, immediate post-indexed. */
9745 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9746 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9747 offset_8 = (immed_high << 4) | immed_low;
9748 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9749 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9750 /* Calculate target store address, Rn +/- Rm, register offset. */
9751 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9753 tgt_mem_addr = u_regval[0] + offset_8;
9757 tgt_mem_addr = u_regval[0] - offset_8;
9759 if (ARM_RECORD_STRH == str_type)
9761 record_buf_mem[0] = 2;
9762 record_buf_mem[1] = tgt_mem_addr;
9763 arm_insn_r->mem_rec_count = 1;
9765 else if (ARM_RECORD_STRD == str_type)
9767 record_buf_mem[0] = 4;
9768 record_buf_mem[1] = tgt_mem_addr;
9769 record_buf_mem[2] = 4;
9770 record_buf_mem[3] = tgt_mem_addr + 4;
9771 arm_insn_r->mem_rec_count = 2;
9773 /* Record Rn also as it changes. */
9774 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9775 arm_insn_r->reg_rec_count = 1;
9777 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
9778 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9780 /* 4) Store, register pre-indexed. */
9781 /* 6) Store, register post -indexed. */
9782 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9783 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9784 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9785 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9786 /* Calculate target store address, Rn +/- Rm, register offset. */
9787 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9789 tgt_mem_addr = u_regval[0] + u_regval[1];
9793 tgt_mem_addr = u_regval[1] - u_regval[0];
9795 if (ARM_RECORD_STRH == str_type)
9797 record_buf_mem[0] = 2;
9798 record_buf_mem[1] = tgt_mem_addr;
9799 arm_insn_r->mem_rec_count = 1;
9801 else if (ARM_RECORD_STRD == str_type)
9803 record_buf_mem[0] = 4;
9804 record_buf_mem[1] = tgt_mem_addr;
9805 record_buf_mem[2] = 4;
9806 record_buf_mem[3] = tgt_mem_addr + 4;
9807 arm_insn_r->mem_rec_count = 2;
9809 /* Record Rn also as it changes. */
9810 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9811 arm_insn_r->reg_rec_count = 1;
9816 /* Handling ARM extension space insns. */
9819 arm_record_extension_space (insn_decode_record *arm_insn_r)
9821 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
9822 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
9823 uint32_t record_buf[8], record_buf_mem[8];
9824 uint32_t reg_src1 = 0;
9825 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
9826 struct regcache *reg_cache = arm_insn_r->regcache;
9827 ULONGEST u_regval = 0;
9829 gdb_assert (!INSN_RECORDED(arm_insn_r));
9830 /* Handle unconditional insn extension space. */
9832 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
9833 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
9834 if (arm_insn_r->cond)
9836 /* PLD has no affect on architectural state, it just affects
9838 if (5 == ((opcode1 & 0xE0) >> 5))
9841 record_buf[0] = ARM_PS_REGNUM;
9842 record_buf[1] = ARM_LR_REGNUM;
9843 arm_insn_r->reg_rec_count = 2;
9845 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9849 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
9850 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
9853 /* Undefined instruction on ARM V5; need to handle if later
9854 versions define it. */
9857 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
9858 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
9859 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
9861 /* Handle arithmetic insn extension space. */
9862 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
9863 && !INSN_RECORDED(arm_insn_r))
9865 /* Handle MLA(S) and MUL(S). */
9866 if (0 <= insn_op1 && 3 >= insn_op1)
9868 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9869 record_buf[1] = ARM_PS_REGNUM;
9870 arm_insn_r->reg_rec_count = 2;
9872 else if (4 <= insn_op1 && 15 >= insn_op1)
9874 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9875 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
9876 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
9877 record_buf[2] = ARM_PS_REGNUM;
9878 arm_insn_r->reg_rec_count = 3;
9882 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
9883 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
9884 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
9886 /* Handle control insn extension space. */
9888 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
9889 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
9891 if (!bit (arm_insn_r->arm_insn,25))
9893 if (!bits (arm_insn_r->arm_insn, 4, 7))
9895 if ((0 == insn_op1) || (2 == insn_op1))
9898 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9899 arm_insn_r->reg_rec_count = 1;
9901 else if (1 == insn_op1)
9903 /* CSPR is going to be changed. */
9904 record_buf[0] = ARM_PS_REGNUM;
9905 arm_insn_r->reg_rec_count = 1;
9907 else if (3 == insn_op1)
9909 /* SPSR is going to be changed. */
9910 /* We need to get SPSR value, which is yet to be done. */
9911 printf_unfiltered (_("Process record does not support "
9912 "instruction 0x%0x at address %s.\n"),
9913 arm_insn_r->arm_insn,
9914 paddress (arm_insn_r->gdbarch,
9915 arm_insn_r->this_addr));
9919 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
9924 record_buf[0] = ARM_PS_REGNUM;
9925 arm_insn_r->reg_rec_count = 1;
9927 else if (3 == insn_op1)
9930 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9931 arm_insn_r->reg_rec_count = 1;
9934 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
9937 record_buf[0] = ARM_PS_REGNUM;
9938 record_buf[1] = ARM_LR_REGNUM;
9939 arm_insn_r->reg_rec_count = 2;
9941 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
9943 /* QADD, QSUB, QDADD, QDSUB */
9944 record_buf[0] = ARM_PS_REGNUM;
9945 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
9946 arm_insn_r->reg_rec_count = 2;
9948 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
9951 record_buf[0] = ARM_PS_REGNUM;
9952 record_buf[1] = ARM_LR_REGNUM;
9953 arm_insn_r->reg_rec_count = 2;
9955 /* Save SPSR also;how? */
9956 printf_unfiltered (_("Process record does not support "
9957 "instruction 0x%0x at address %s.\n"),
9958 arm_insn_r->arm_insn,
9959 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
9962 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
9963 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
9964 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
9965 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
9968 if (0 == insn_op1 || 1 == insn_op1)
9970 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
9971 /* We dont do optimization for SMULW<y> where we
9973 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9974 record_buf[1] = ARM_PS_REGNUM;
9975 arm_insn_r->reg_rec_count = 2;
9977 else if (2 == insn_op1)
9980 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9981 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
9982 arm_insn_r->reg_rec_count = 2;
9984 else if (3 == insn_op1)
9987 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
9988 arm_insn_r->reg_rec_count = 1;
9994 /* MSR : immediate form. */
9997 /* CSPR is going to be changed. */
9998 record_buf[0] = ARM_PS_REGNUM;
9999 arm_insn_r->reg_rec_count = 1;
10001 else if (3 == insn_op1)
10003 /* SPSR is going to be changed. */
10004 /* we need to get SPSR value, which is yet to be done */
10005 printf_unfiltered (_("Process record does not support "
10006 "instruction 0x%0x at address %s.\n"),
10007 arm_insn_r->arm_insn,
10008 paddress (arm_insn_r->gdbarch,
10009 arm_insn_r->this_addr));
10015 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10016 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
10017 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
10019 /* Handle load/store insn extension space. */
10021 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
10022 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
10023 && !INSN_RECORDED(arm_insn_r))
10028 /* These insn, changes register and memory as well. */
10029 /* SWP or SWPB insn. */
10030 /* Get memory address given by Rn. */
10031 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10032 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
10033 /* SWP insn ?, swaps word. */
10034 if (8 == arm_insn_r->opcode)
10036 record_buf_mem[0] = 4;
10040 /* SWPB insn, swaps only byte. */
10041 record_buf_mem[0] = 1;
10043 record_buf_mem[1] = u_regval;
10044 arm_insn_r->mem_rec_count = 1;
10045 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10046 arm_insn_r->reg_rec_count = 1;
10048 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10051 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10054 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10057 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10058 record_buf[1] = record_buf[0] + 1;
10059 arm_insn_r->reg_rec_count = 2;
10061 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10064 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10067 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
10069 /* LDRH, LDRSB, LDRSH. */
10070 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10071 arm_insn_r->reg_rec_count = 1;
10076 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
10077 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
10078 && !INSN_RECORDED(arm_insn_r))
10081 /* Handle coprocessor insn extension space. */
10084 /* To be done for ARMv5 and later; as of now we return -1. */
10086 printf_unfiltered (_("Process record does not support instruction x%0x "
10087 "at address %s.\n"),arm_insn_r->arm_insn,
10088 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
10091 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10092 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10097 /* Handling opcode 000 insns. */
10100 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
10102 struct regcache *reg_cache = arm_insn_r->regcache;
10103 uint32_t record_buf[8], record_buf_mem[8];
10104 ULONGEST u_regval[2] = {0};
10106 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
10107 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
10108 uint32_t opcode1 = 0;
10110 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10111 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10112 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10114 /* Data processing insn /multiply insn. */
10115 if (9 == arm_insn_r->decode
10116 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10117 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
10119 /* Handle multiply instructions. */
10120 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10121 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
10123 /* Handle MLA and MUL. */
10124 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10125 record_buf[1] = ARM_PS_REGNUM;
10126 arm_insn_r->reg_rec_count = 2;
10128 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10130 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10131 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10132 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10133 record_buf[2] = ARM_PS_REGNUM;
10134 arm_insn_r->reg_rec_count = 3;
10137 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10138 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
10140 /* Handle misc load insns, as 20th bit (L = 1). */
10141 /* LDR insn has a capability to do branching, if
10142 MOV LR, PC is precceded by LDR insn having Rn as R15
10143 in that case, it emulates branch and link insn, and hence we
10144 need to save CSPR and PC as well. I am not sure this is right
10145 place; as opcode = 010 LDR insn make this happen, if R15 was
10147 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10148 if (15 != reg_dest)
10150 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10151 arm_insn_r->reg_rec_count = 1;
10155 record_buf[0] = reg_dest;
10156 record_buf[1] = ARM_PS_REGNUM;
10157 arm_insn_r->reg_rec_count = 2;
10160 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10161 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
10162 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10163 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
10165 /* Handle MSR insn. */
10166 if (9 == arm_insn_r->opcode)
10168 /* CSPR is going to be changed. */
10169 record_buf[0] = ARM_PS_REGNUM;
10170 arm_insn_r->reg_rec_count = 1;
10174 /* SPSR is going to be changed. */
10175 /* How to read SPSR value? */
10176 printf_unfiltered (_("Process record does not support instruction "
10177 "0x%0x at address %s.\n"),
10178 arm_insn_r->arm_insn,
10179 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
10183 else if (9 == arm_insn_r->decode
10184 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10185 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10187 /* Handling SWP, SWPB. */
10188 /* These insn, changes register and memory as well. */
10189 /* SWP or SWPB insn. */
10191 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10192 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10193 /* SWP insn ?, swaps word. */
10194 if (8 == arm_insn_r->opcode)
10196 record_buf_mem[0] = 4;
10200 /* SWPB insn, swaps only byte. */
10201 record_buf_mem[0] = 1;
10203 record_buf_mem[1] = u_regval[0];
10204 arm_insn_r->mem_rec_count = 1;
10205 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10206 arm_insn_r->reg_rec_count = 1;
10208 else if (3 == arm_insn_r->decode && 0x12 == opcode1
10209 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10211 /* Handle BLX, branch and link/exchange. */
10212 if (9 == arm_insn_r->opcode)
10214 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10215 and R14 stores the return address. */
10216 record_buf[0] = ARM_PS_REGNUM;
10217 record_buf[1] = ARM_LR_REGNUM;
10218 arm_insn_r->reg_rec_count = 2;
10221 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
10223 /* Handle enhanced software breakpoint insn, BKPT. */
10224 /* CPSR is changed to be executed in ARM state, disabling normal
10225 interrupts, entering abort mode. */
10226 /* According to high vector configuration PC is set. */
10227 /* user hit breakpoint and type reverse, in
10228 that case, we need to go back with previous CPSR and
10229 Program Counter. */
10230 record_buf[0] = ARM_PS_REGNUM;
10231 record_buf[1] = ARM_LR_REGNUM;
10232 arm_insn_r->reg_rec_count = 2;
10234 /* Save SPSR also; how? */
10235 printf_unfiltered (_("Process record does not support instruction "
10236 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
10237 paddress (arm_insn_r->gdbarch,
10238 arm_insn_r->this_addr));
10241 else if (11 == arm_insn_r->decode
10242 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10244 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10246 /* Handle str(x) insn */
10247 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10250 else if (1 == arm_insn_r->decode && 0x12 == opcode1
10251 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10253 /* Handle BX, branch and link/exchange. */
10254 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10255 record_buf[0] = ARM_PS_REGNUM;
10256 arm_insn_r->reg_rec_count = 1;
10258 else if (1 == arm_insn_r->decode && 0x16 == opcode1
10259 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
10260 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
10262 /* Count leading zeros: CLZ. */
10263 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10264 arm_insn_r->reg_rec_count = 1;
10266 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10267 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10268 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
10269 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
10272 /* Handle MRS insn. */
10273 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10274 arm_insn_r->reg_rec_count = 1;
10276 else if (arm_insn_r->opcode <= 15)
10278 /* Normal data processing insns. */
10279 /* Out of 11 shifter operands mode, all the insn modifies destination
10280 register, which is specified by 13-16 decode. */
10281 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10282 record_buf[1] = ARM_PS_REGNUM;
10283 arm_insn_r->reg_rec_count = 2;
10290 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10291 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10295 /* Handling opcode 001 insns. */
10298 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
10300 uint32_t record_buf[8], record_buf_mem[8];
10302 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10303 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10305 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10306 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
10307 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10310 /* Handle MSR insn. */
10311 if (9 == arm_insn_r->opcode)
10313 /* CSPR is going to be changed. */
10314 record_buf[0] = ARM_PS_REGNUM;
10315 arm_insn_r->reg_rec_count = 1;
10319 /* SPSR is going to be changed. */
10322 else if (arm_insn_r->opcode <= 15)
10324 /* Normal data processing insns. */
10325 /* Out of 11 shifter operands mode, all the insn modifies destination
10326 register, which is specified by 13-16 decode. */
10327 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10328 record_buf[1] = ARM_PS_REGNUM;
10329 arm_insn_r->reg_rec_count = 2;
10336 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10337 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10341 /* Handle ARM mode instructions with opcode 010. */
10344 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
10346 struct regcache *reg_cache = arm_insn_r->regcache;
10348 uint32_t reg_base , reg_dest;
10349 uint32_t offset_12, tgt_mem_addr;
10350 uint32_t record_buf[8], record_buf_mem[8];
10351 unsigned char wback;
10354 /* Calculate wback. */
10355 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
10356 || (bit (arm_insn_r->arm_insn, 21) == 1);
10358 arm_insn_r->reg_rec_count = 0;
10359 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10361 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10363 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10366 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10367 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
10369 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10370 preceeds a LDR instruction having R15 as reg_base, it
10371 emulates a branch and link instruction, and hence we need to save
10372 CPSR and PC as well. */
10373 if (ARM_PC_REGNUM == reg_dest)
10374 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10376 /* If wback is true, also save the base register, which is going to be
10379 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10383 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10385 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
10386 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10388 /* Handle bit U. */
10389 if (bit (arm_insn_r->arm_insn, 23))
10391 /* U == 1: Add the offset. */
10392 tgt_mem_addr = (uint32_t) u_regval + offset_12;
10396 /* U == 0: subtract the offset. */
10397 tgt_mem_addr = (uint32_t) u_regval - offset_12;
10400 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10402 if (bit (arm_insn_r->arm_insn, 22))
10404 /* STRB and STRBT: 1 byte. */
10405 record_buf_mem[0] = 1;
10409 /* STR and STRT: 4 bytes. */
10410 record_buf_mem[0] = 4;
10413 /* Handle bit P. */
10414 if (bit (arm_insn_r->arm_insn, 24))
10415 record_buf_mem[1] = tgt_mem_addr;
10417 record_buf_mem[1] = (uint32_t) u_regval;
10419 arm_insn_r->mem_rec_count = 1;
10421 /* If wback is true, also save the base register, which is going to be
10424 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10427 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10428 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10432 /* Handling opcode 011 insns. */
10435 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
10437 struct regcache *reg_cache = arm_insn_r->regcache;
10439 uint32_t shift_imm = 0;
10440 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
10441 uint32_t offset_12 = 0, tgt_mem_addr = 0;
10442 uint32_t record_buf[8], record_buf_mem[8];
10445 ULONGEST u_regval[2];
10447 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10448 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10450 /* Handle enhanced store insns and LDRD DSP insn,
10451 order begins according to addressing modes for store insns
10455 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10457 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10458 /* LDR insn has a capability to do branching, if
10459 MOV LR, PC is precedded by LDR insn having Rn as R15
10460 in that case, it emulates branch and link insn, and hence we
10461 need to save CSPR and PC as well. */
10462 if (15 != reg_dest)
10464 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10465 arm_insn_r->reg_rec_count = 1;
10469 record_buf[0] = reg_dest;
10470 record_buf[1] = ARM_PS_REGNUM;
10471 arm_insn_r->reg_rec_count = 2;
10476 if (! bits (arm_insn_r->arm_insn, 4, 11))
10478 /* Store insn, register offset and register pre-indexed,
10479 register post-indexed. */
10481 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10483 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10484 regcache_raw_read_unsigned (reg_cache, reg_src1
10486 regcache_raw_read_unsigned (reg_cache, reg_src2
10488 if (15 == reg_src2)
10490 /* If R15 was used as Rn, hence current PC+8. */
10491 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10492 u_regval[0] = u_regval[0] + 8;
10494 /* Calculate target store address, Rn +/- Rm, register offset. */
10496 if (bit (arm_insn_r->arm_insn, 23))
10498 tgt_mem_addr = u_regval[0] + u_regval[1];
10502 tgt_mem_addr = u_regval[1] - u_regval[0];
10505 switch (arm_insn_r->opcode)
10519 record_buf_mem[0] = 4;
10534 record_buf_mem[0] = 1;
10538 gdb_assert_not_reached ("no decoding pattern found");
10541 record_buf_mem[1] = tgt_mem_addr;
10542 arm_insn_r->mem_rec_count = 1;
10544 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10545 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10546 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10547 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10548 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10549 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10552 /* Rn is going to be changed in pre-indexed mode and
10553 post-indexed mode as well. */
10554 record_buf[0] = reg_src2;
10555 arm_insn_r->reg_rec_count = 1;
10560 /* Store insn, scaled register offset; scaled pre-indexed. */
10561 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
10563 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10565 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10566 /* Get shift_imm. */
10567 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
10568 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10569 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
10570 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10571 /* Offset_12 used as shift. */
10575 /* Offset_12 used as index. */
10576 offset_12 = u_regval[0] << shift_imm;
10580 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
10586 if (bit (u_regval[0], 31))
10588 offset_12 = 0xFFFFFFFF;
10597 /* This is arithmetic shift. */
10598 offset_12 = s_word >> shift_imm;
10605 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
10607 /* Get C flag value and shift it by 31. */
10608 offset_12 = (((bit (u_regval[1], 29)) << 31) \
10609 | (u_regval[0]) >> 1);
10613 offset_12 = (u_regval[0] >> shift_imm) \
10615 (sizeof(uint32_t) - shift_imm));
10620 gdb_assert_not_reached ("no decoding pattern found");
10624 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10626 if (bit (arm_insn_r->arm_insn, 23))
10628 tgt_mem_addr = u_regval[1] + offset_12;
10632 tgt_mem_addr = u_regval[1] - offset_12;
10635 switch (arm_insn_r->opcode)
10649 record_buf_mem[0] = 4;
10664 record_buf_mem[0] = 1;
10668 gdb_assert_not_reached ("no decoding pattern found");
10671 record_buf_mem[1] = tgt_mem_addr;
10672 arm_insn_r->mem_rec_count = 1;
10674 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10675 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10676 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10677 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10678 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10679 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10682 /* Rn is going to be changed in register scaled pre-indexed
10683 mode,and scaled post indexed mode. */
10684 record_buf[0] = reg_src2;
10685 arm_insn_r->reg_rec_count = 1;
10690 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10691 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10695 /* Handle ARM mode instructions with opcode 100. */
10698 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
10700 struct regcache *reg_cache = arm_insn_r->regcache;
10701 uint32_t register_count = 0, register_bits;
10702 uint32_t reg_base, addr_mode;
10703 uint32_t record_buf[24], record_buf_mem[48];
10707 /* Fetch the list of registers. */
10708 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
10709 arm_insn_r->reg_rec_count = 0;
10711 /* Fetch the base register that contains the address we are loading data
10713 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10715 /* Calculate wback. */
10716 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
10718 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10720 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10722 /* Find out which registers are going to be loaded from memory. */
10723 while (register_bits)
10725 if (register_bits & 0x00000001)
10726 record_buf[arm_insn_r->reg_rec_count++] = register_count;
10727 register_bits = register_bits >> 1;
10732 /* If wback is true, also save the base register, which is going to be
10735 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10737 /* Save the CPSR register. */
10738 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10742 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10744 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
10746 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10748 /* Find out how many registers are going to be stored to memory. */
10749 while (register_bits)
10751 if (register_bits & 0x00000001)
10753 register_bits = register_bits >> 1;
10758 /* STMDA (STMED): Decrement after. */
10760 record_buf_mem[1] = (uint32_t) u_regval
10761 - register_count * INT_REGISTER_SIZE + 4;
10763 /* STM (STMIA, STMEA): Increment after. */
10765 record_buf_mem[1] = (uint32_t) u_regval;
10767 /* STMDB (STMFD): Decrement before. */
10769 record_buf_mem[1] = (uint32_t) u_regval
10770 - register_count * INT_REGISTER_SIZE;
10772 /* STMIB (STMFA): Increment before. */
10774 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
10777 gdb_assert_not_reached ("no decoding pattern found");
10781 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
10782 arm_insn_r->mem_rec_count = 1;
10784 /* If wback is true, also save the base register, which is going to be
10787 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10790 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10791 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10795 /* Handling opcode 101 insns. */
10798 arm_record_b_bl (insn_decode_record *arm_insn_r)
10800 uint32_t record_buf[8];
10802 /* Handle B, BL, BLX(1) insns. */
10803 /* B simply branches so we do nothing here. */
10804 /* Note: BLX(1) doesnt fall here but instead it falls into
10805 extension space. */
10806 if (bit (arm_insn_r->arm_insn, 24))
10808 record_buf[0] = ARM_LR_REGNUM;
10809 arm_insn_r->reg_rec_count = 1;
10812 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10817 /* Handling opcode 110 insns. */
10820 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
10822 printf_unfiltered (_("Process record does not support instruction "
10823 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
10824 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
10829 /* Record handler for vector data transfer instructions. */
10832 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
10834 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
10835 uint32_t record_buf[4];
10837 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
10838 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
10839 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
10840 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
10841 bit_l = bit (arm_insn_r->arm_insn, 20);
10842 bit_c = bit (arm_insn_r->arm_insn, 8);
10844 /* Handle VMOV instruction. */
10845 if (bit_l && bit_c)
10847 record_buf[0] = reg_t;
10848 arm_insn_r->reg_rec_count = 1;
10850 else if (bit_l && !bit_c)
10852 /* Handle VMOV instruction. */
10853 if (bits_a == 0x00)
10855 if (bit (arm_insn_r->arm_insn, 20))
10856 record_buf[0] = reg_t;
10858 record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
10861 arm_insn_r->reg_rec_count = 1;
10863 /* Handle VMRS instruction. */
10864 else if (bits_a == 0x07)
10867 reg_t = ARM_PS_REGNUM;
10869 record_buf[0] = reg_t;
10870 arm_insn_r->reg_rec_count = 1;
10873 else if (!bit_l && !bit_c)
10875 /* Handle VMOV instruction. */
10876 if (bits_a == 0x00)
10878 if (bit (arm_insn_r->arm_insn, 20))
10879 record_buf[0] = reg_t;
10881 record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
10884 arm_insn_r->reg_rec_count = 1;
10886 /* Handle VMSR instruction. */
10887 else if (bits_a == 0x07)
10889 record_buf[0] = ARM_FPSCR_REGNUM;
10890 arm_insn_r->reg_rec_count = 1;
10893 else if (!bit_l && bit_c)
10895 /* Handle VMOV instruction. */
10896 if (!(bits_a & 0x04))
10898 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
10900 arm_insn_r->reg_rec_count = 1;
10902 /* Handle VDUP instruction. */
10905 if (bit (arm_insn_r->arm_insn, 21))
10907 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
10908 record_buf[0] = reg_v + ARM_D0_REGNUM;
10909 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
10910 arm_insn_r->reg_rec_count = 2;
10914 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
10915 record_buf[0] = reg_v + ARM_D0_REGNUM;
10916 arm_insn_r->reg_rec_count = 1;
10921 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10925 /* Record handler for extension register load/store instructions. */
10928 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
10930 uint32_t opcode, single_reg;
10931 uint8_t op_vldm_vstm;
10932 uint32_t record_buf[8], record_buf_mem[128];
10933 ULONGEST u_regval = 0;
10935 struct regcache *reg_cache = arm_insn_r->regcache;
10936 const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
10938 opcode = bits (arm_insn_r->arm_insn, 20, 24);
10939 single_reg = bit (arm_insn_r->arm_insn, 8);
10940 op_vldm_vstm = opcode & 0x1b;
10942 /* Handle VMOV instructions. */
10943 if ((opcode & 0x1e) == 0x04)
10945 if (bit (arm_insn_r->arm_insn, 4))
10947 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10948 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
10949 arm_insn_r->reg_rec_count = 2;
10953 uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1)
10954 | bit (arm_insn_r->arm_insn, 5);
10958 record_buf[0] = num_regs + reg_m;
10959 record_buf[1] = num_regs + reg_m + 1;
10960 arm_insn_r->reg_rec_count = 2;
10964 record_buf[0] = reg_m + ARM_D0_REGNUM;
10965 arm_insn_r->reg_rec_count = 1;
10969 /* Handle VSTM and VPUSH instructions. */
10970 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
10971 || op_vldm_vstm == 0x12)
10973 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
10974 uint32_t memory_index = 0;
10976 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
10977 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
10978 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
10979 imm_off32 = imm_off8 << 24;
10980 memory_count = imm_off8;
10982 if (bit (arm_insn_r->arm_insn, 23))
10983 start_address = u_regval;
10985 start_address = u_regval - imm_off32;
10987 if (bit (arm_insn_r->arm_insn, 21))
10989 record_buf[0] = reg_rn;
10990 arm_insn_r->reg_rec_count = 1;
10993 while (memory_count > 0)
10997 record_buf_mem[memory_index] = start_address;
10998 record_buf_mem[memory_index + 1] = 4;
10999 start_address = start_address + 4;
11000 memory_index = memory_index + 2;
11004 record_buf_mem[memory_index] = start_address;
11005 record_buf_mem[memory_index + 1] = 4;
11006 record_buf_mem[memory_index + 2] = start_address + 4;
11007 record_buf_mem[memory_index + 3] = 4;
11008 start_address = start_address + 8;
11009 memory_index = memory_index + 4;
11013 arm_insn_r->mem_rec_count = (memory_index >> 1);
11015 /* Handle VLDM instructions. */
11016 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
11017 || op_vldm_vstm == 0x13)
11019 uint32_t reg_count, reg_vd;
11020 uint32_t reg_index = 0;
11022 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11023 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
11026 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
11028 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
11030 if (bit (arm_insn_r->arm_insn, 21))
11031 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
11033 while (reg_count > 0)
11036 record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1;
11038 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
11042 arm_insn_r->reg_rec_count = reg_index;
11044 /* VSTR Vector store register. */
11045 else if ((opcode & 0x13) == 0x10)
11047 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
11048 uint32_t memory_index = 0;
11050 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11051 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11052 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11053 imm_off32 = imm_off8 << 24;
11054 memory_count = imm_off8;
11056 if (bit (arm_insn_r->arm_insn, 23))
11057 start_address = u_regval + imm_off32;
11059 start_address = u_regval - imm_off32;
11063 record_buf_mem[memory_index] = start_address;
11064 record_buf_mem[memory_index + 1] = 4;
11065 arm_insn_r->mem_rec_count = 1;
11069 record_buf_mem[memory_index] = start_address;
11070 record_buf_mem[memory_index + 1] = 4;
11071 record_buf_mem[memory_index + 2] = start_address + 4;
11072 record_buf_mem[memory_index + 3] = 4;
11073 arm_insn_r->mem_rec_count = 2;
11076 /* VLDR Vector load register. */
11077 else if ((opcode & 0x13) == 0x11)
11079 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11083 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
11084 record_buf[0] = ARM_D0_REGNUM + reg_vd;
11088 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
11089 record_buf[0] = num_regs + reg_vd;
11091 arm_insn_r->reg_rec_count = 1;
11094 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11095 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11099 /* Record handler for arm/thumb mode VFP data processing instructions. */
11102 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
11104 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
11105 uint32_t record_buf[4];
11106 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
11107 enum insn_types curr_insn_type = INSN_INV;
11109 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11110 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
11111 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
11112 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
11113 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
11114 bit_d = bit (arm_insn_r->arm_insn, 22);
11115 opc1 = opc1 & 0x04;
11117 /* Handle VMLA, VMLS. */
11120 if (bit (arm_insn_r->arm_insn, 10))
11122 if (bit (arm_insn_r->arm_insn, 6))
11123 curr_insn_type = INSN_T0;
11125 curr_insn_type = INSN_T1;
11130 curr_insn_type = INSN_T1;
11132 curr_insn_type = INSN_T2;
11135 /* Handle VNMLA, VNMLS, VNMUL. */
11136 else if (opc1 == 0x01)
11139 curr_insn_type = INSN_T1;
11141 curr_insn_type = INSN_T2;
11144 else if (opc1 == 0x02 && !(opc3 & 0x01))
11146 if (bit (arm_insn_r->arm_insn, 10))
11148 if (bit (arm_insn_r->arm_insn, 6))
11149 curr_insn_type = INSN_T0;
11151 curr_insn_type = INSN_T1;
11156 curr_insn_type = INSN_T1;
11158 curr_insn_type = INSN_T2;
11161 /* Handle VADD, VSUB. */
11162 else if (opc1 == 0x03)
11164 if (!bit (arm_insn_r->arm_insn, 9))
11166 if (bit (arm_insn_r->arm_insn, 6))
11167 curr_insn_type = INSN_T0;
11169 curr_insn_type = INSN_T1;
11174 curr_insn_type = INSN_T1;
11176 curr_insn_type = INSN_T2;
11180 else if (opc1 == 0x0b)
11183 curr_insn_type = INSN_T1;
11185 curr_insn_type = INSN_T2;
11187 /* Handle all other vfp data processing instructions. */
11188 else if (opc1 == 0x0b)
11191 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
11193 if (bit (arm_insn_r->arm_insn, 4))
11195 if (bit (arm_insn_r->arm_insn, 6))
11196 curr_insn_type = INSN_T0;
11198 curr_insn_type = INSN_T1;
11203 curr_insn_type = INSN_T1;
11205 curr_insn_type = INSN_T2;
11208 /* Handle VNEG and VABS. */
11209 else if ((opc2 == 0x01 && opc3 == 0x01)
11210 || (opc2 == 0x00 && opc3 == 0x03))
11212 if (!bit (arm_insn_r->arm_insn, 11))
11214 if (bit (arm_insn_r->arm_insn, 6))
11215 curr_insn_type = INSN_T0;
11217 curr_insn_type = INSN_T1;
11222 curr_insn_type = INSN_T1;
11224 curr_insn_type = INSN_T2;
11227 /* Handle VSQRT. */
11228 else if (opc2 == 0x01 && opc3 == 0x03)
11231 curr_insn_type = INSN_T1;
11233 curr_insn_type = INSN_T2;
11236 else if (opc2 == 0x07 && opc3 == 0x03)
11239 curr_insn_type = INSN_T1;
11241 curr_insn_type = INSN_T2;
11243 else if (opc3 & 0x01)
11246 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
11248 if (!bit (arm_insn_r->arm_insn, 18))
11249 curr_insn_type = INSN_T2;
11253 curr_insn_type = INSN_T1;
11255 curr_insn_type = INSN_T2;
11259 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
11262 curr_insn_type = INSN_T1;
11264 curr_insn_type = INSN_T2;
11266 /* Handle VCVTB, VCVTT. */
11267 else if ((opc2 & 0x0e) == 0x02)
11268 curr_insn_type = INSN_T2;
11269 /* Handle VCMP, VCMPE. */
11270 else if ((opc2 & 0x0e) == 0x04)
11271 curr_insn_type = INSN_T3;
11275 switch (curr_insn_type)
11278 reg_vd = reg_vd | (bit_d << 4);
11279 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11280 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
11281 arm_insn_r->reg_rec_count = 2;
11285 reg_vd = reg_vd | (bit_d << 4);
11286 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11287 arm_insn_r->reg_rec_count = 1;
11291 reg_vd = (reg_vd << 1) | bit_d;
11292 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11293 arm_insn_r->reg_rec_count = 1;
11297 record_buf[0] = ARM_FPSCR_REGNUM;
11298 arm_insn_r->reg_rec_count = 1;
11302 gdb_assert_not_reached ("no decoding pattern found");
11306 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11310 /* Handling opcode 110 insns. */
11313 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
11315 uint32_t op, op1, op1_sbit, op1_ebit, coproc;
11317 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11318 op1 = bits (arm_insn_r->arm_insn, 20, 25);
11319 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11321 if ((coproc & 0x0e) == 0x0a)
11323 /* Handle extension register ld/st instructions. */
11325 return arm_record_exreg_ld_st_insn (arm_insn_r);
11327 /* 64-bit transfers between arm core and extension registers. */
11328 if ((op1 & 0x3e) == 0x04)
11329 return arm_record_exreg_ld_st_insn (arm_insn_r);
11333 /* Handle coprocessor ld/st instructions. */
11338 return arm_record_unsupported_insn (arm_insn_r);
11341 return arm_record_unsupported_insn (arm_insn_r);
11344 /* Move to coprocessor from two arm core registers. */
11346 return arm_record_unsupported_insn (arm_insn_r);
11348 /* Move to two arm core registers from coprocessor. */
11353 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
11354 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
11355 arm_insn_r->reg_rec_count = 2;
11357 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
11361 return arm_record_unsupported_insn (arm_insn_r);
11364 /* Handling opcode 111 insns. */
11367 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11369 uint32_t op, op1_sbit, op1_ebit, coproc;
11370 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11371 struct regcache *reg_cache = arm_insn_r->regcache;
11372 ULONGEST u_regval = 0;
11374 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11375 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11376 op1_sbit = bit (arm_insn_r->arm_insn, 24);
11377 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11378 op = bit (arm_insn_r->arm_insn, 4);
11380 /* Handle arm SWI/SVC system call instructions. */
11383 if (tdep->arm_syscall_record != NULL)
11385 ULONGEST svc_operand, svc_number;
11387 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
11389 if (svc_operand) /* OABI. */
11390 svc_number = svc_operand - 0x900000;
11392 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
11394 return tdep->arm_syscall_record (reg_cache, svc_number);
11398 printf_unfiltered (_("no syscall record support\n"));
11403 if ((coproc & 0x0e) == 0x0a)
11405 /* VFP data-processing instructions. */
11406 if (!op1_sbit && !op)
11407 return arm_record_vfp_data_proc_insn (arm_insn_r);
11409 /* Advanced SIMD, VFP instructions. */
11410 if (!op1_sbit && op)
11411 return arm_record_vdata_transfer_insn (arm_insn_r);
11415 /* Coprocessor data operations. */
11416 if (!op1_sbit && !op)
11417 return arm_record_unsupported_insn (arm_insn_r);
11419 /* Move to Coprocessor from ARM core register. */
11420 if (!op1_sbit && !op1_ebit && op)
11421 return arm_record_unsupported_insn (arm_insn_r);
11423 /* Move to arm core register from coprocessor. */
11424 if (!op1_sbit && op1_ebit && op)
11426 uint32_t record_buf[1];
11428 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11429 if (record_buf[0] == 15)
11430 record_buf[0] = ARM_PS_REGNUM;
11432 arm_insn_r->reg_rec_count = 1;
11433 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
11439 return arm_record_unsupported_insn (arm_insn_r);
11442 /* Handling opcode 000 insns. */
11445 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11447 uint32_t record_buf[8];
11448 uint32_t reg_src1 = 0;
11450 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11452 record_buf[0] = ARM_PS_REGNUM;
11453 record_buf[1] = reg_src1;
11454 thumb_insn_r->reg_rec_count = 2;
11456 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11462 /* Handling opcode 001 insns. */
11465 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11467 uint32_t record_buf[8];
11468 uint32_t reg_src1 = 0;
11470 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11472 record_buf[0] = ARM_PS_REGNUM;
11473 record_buf[1] = reg_src1;
11474 thumb_insn_r->reg_rec_count = 2;
11476 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11481 /* Handling opcode 010 insns. */
11484 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
11486 struct regcache *reg_cache = thumb_insn_r->regcache;
11487 uint32_t record_buf[8], record_buf_mem[8];
11489 uint32_t reg_src1 = 0, reg_src2 = 0;
11490 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
11492 ULONGEST u_regval[2] = {0};
11494 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
11496 if (bit (thumb_insn_r->arm_insn, 12))
11498 /* Handle load/store register offset. */
11499 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
11500 if (opcode2 >= 12 && opcode2 <= 15)
11502 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11503 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
11504 record_buf[0] = reg_src1;
11505 thumb_insn_r->reg_rec_count = 1;
11507 else if (opcode2 >= 8 && opcode2 <= 10)
11509 /* STR(2), STRB(2), STRH(2) . */
11510 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11511 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
11512 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11513 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11515 record_buf_mem[0] = 4; /* STR (2). */
11516 else if (10 == opcode2)
11517 record_buf_mem[0] = 1; /* STRB (2). */
11518 else if (9 == opcode2)
11519 record_buf_mem[0] = 2; /* STRH (2). */
11520 record_buf_mem[1] = u_regval[0] + u_regval[1];
11521 thumb_insn_r->mem_rec_count = 1;
11524 else if (bit (thumb_insn_r->arm_insn, 11))
11526 /* Handle load from literal pool. */
11528 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11529 record_buf[0] = reg_src1;
11530 thumb_insn_r->reg_rec_count = 1;
11534 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
11535 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
11536 if ((3 == opcode2) && (!opcode3))
11538 /* Branch with exchange. */
11539 record_buf[0] = ARM_PS_REGNUM;
11540 thumb_insn_r->reg_rec_count = 1;
11544 /* Format 8; special data processing insns. */
11545 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11546 record_buf[0] = ARM_PS_REGNUM;
11547 record_buf[1] = reg_src1;
11548 thumb_insn_r->reg_rec_count = 2;
11553 /* Format 5; data processing insns. */
11554 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11555 if (bit (thumb_insn_r->arm_insn, 7))
11557 reg_src1 = reg_src1 + 8;
11559 record_buf[0] = ARM_PS_REGNUM;
11560 record_buf[1] = reg_src1;
11561 thumb_insn_r->reg_rec_count = 2;
11564 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11565 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11571 /* Handling opcode 001 insns. */
11574 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
11576 struct regcache *reg_cache = thumb_insn_r->regcache;
11577 uint32_t record_buf[8], record_buf_mem[8];
11579 uint32_t reg_src1 = 0;
11580 uint32_t opcode = 0, immed_5 = 0;
11582 ULONGEST u_regval = 0;
11584 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11589 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11590 record_buf[0] = reg_src1;
11591 thumb_insn_r->reg_rec_count = 1;
11596 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11597 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11598 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11599 record_buf_mem[0] = 4;
11600 record_buf_mem[1] = u_regval + (immed_5 * 4);
11601 thumb_insn_r->mem_rec_count = 1;
11604 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11605 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11611 /* Handling opcode 100 insns. */
11614 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
11616 struct regcache *reg_cache = thumb_insn_r->regcache;
11617 uint32_t record_buf[8], record_buf_mem[8];
11619 uint32_t reg_src1 = 0;
11620 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
11622 ULONGEST u_regval = 0;
11624 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11629 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11630 record_buf[0] = reg_src1;
11631 thumb_insn_r->reg_rec_count = 1;
11633 else if (1 == opcode)
11636 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11637 record_buf[0] = reg_src1;
11638 thumb_insn_r->reg_rec_count = 1;
11640 else if (2 == opcode)
11643 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
11644 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11645 record_buf_mem[0] = 4;
11646 record_buf_mem[1] = u_regval + (immed_8 * 4);
11647 thumb_insn_r->mem_rec_count = 1;
11649 else if (0 == opcode)
11652 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11653 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11654 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11655 record_buf_mem[0] = 2;
11656 record_buf_mem[1] = u_regval + (immed_5 * 2);
11657 thumb_insn_r->mem_rec_count = 1;
11660 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11661 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11667 /* Handling opcode 101 insns. */
11670 thumb_record_misc (insn_decode_record *thumb_insn_r)
11672 struct regcache *reg_cache = thumb_insn_r->regcache;
11674 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
11675 uint32_t register_bits = 0, register_count = 0;
11676 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
11677 uint32_t record_buf[24], record_buf_mem[48];
11680 ULONGEST u_regval = 0;
11682 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11683 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
11684 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
11689 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11690 while (register_bits)
11692 if (register_bits & 0x00000001)
11693 record_buf[index++] = register_count;
11694 register_bits = register_bits >> 1;
11697 record_buf[index++] = ARM_PS_REGNUM;
11698 record_buf[index++] = ARM_SP_REGNUM;
11699 thumb_insn_r->reg_rec_count = index;
11701 else if (10 == opcode2)
11704 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11705 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11706 while (register_bits)
11708 if (register_bits & 0x00000001)
11710 register_bits = register_bits >> 1;
11712 start_address = u_regval - \
11713 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
11714 thumb_insn_r->mem_rec_count = register_count;
11715 while (register_count)
11717 record_buf_mem[(register_count * 2) - 1] = start_address;
11718 record_buf_mem[(register_count * 2) - 2] = 4;
11719 start_address = start_address + 4;
11722 record_buf[0] = ARM_SP_REGNUM;
11723 thumb_insn_r->reg_rec_count = 1;
11725 else if (0x1E == opcode1)
11728 /* Handle enhanced software breakpoint insn, BKPT. */
11729 /* CPSR is changed to be executed in ARM state, disabling normal
11730 interrupts, entering abort mode. */
11731 /* According to high vector configuration PC is set. */
11732 /* User hits breakpoint and type reverse, in that case, we need to go back with
11733 previous CPSR and Program Counter. */
11734 record_buf[0] = ARM_PS_REGNUM;
11735 record_buf[1] = ARM_LR_REGNUM;
11736 thumb_insn_r->reg_rec_count = 2;
11737 /* We need to save SPSR value, which is not yet done. */
11738 printf_unfiltered (_("Process record does not support instruction "
11739 "0x%0x at address %s.\n"),
11740 thumb_insn_r->arm_insn,
11741 paddress (thumb_insn_r->gdbarch,
11742 thumb_insn_r->this_addr));
11745 else if ((0 == opcode) || (1 == opcode))
11747 /* ADD(5), ADD(6). */
11748 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11749 record_buf[0] = reg_src1;
11750 thumb_insn_r->reg_rec_count = 1;
11752 else if (2 == opcode)
11754 /* ADD(7), SUB(4). */
11755 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11756 record_buf[0] = ARM_SP_REGNUM;
11757 thumb_insn_r->reg_rec_count = 1;
11760 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11761 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11767 /* Handling opcode 110 insns. */
11770 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
11772 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
11773 struct regcache *reg_cache = thumb_insn_r->regcache;
11775 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
11776 uint32_t reg_src1 = 0;
11777 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
11778 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
11779 uint32_t record_buf[24], record_buf_mem[48];
11781 ULONGEST u_regval = 0;
11783 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
11784 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
11790 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11792 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11793 while (register_bits)
11795 if (register_bits & 0x00000001)
11796 record_buf[index++] = register_count;
11797 register_bits = register_bits >> 1;
11800 record_buf[index++] = reg_src1;
11801 thumb_insn_r->reg_rec_count = index;
11803 else if (0 == opcode2)
11805 /* It handles both STMIA. */
11806 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11808 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11809 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11810 while (register_bits)
11812 if (register_bits & 0x00000001)
11814 register_bits = register_bits >> 1;
11816 start_address = u_regval;
11817 thumb_insn_r->mem_rec_count = register_count;
11818 while (register_count)
11820 record_buf_mem[(register_count * 2) - 1] = start_address;
11821 record_buf_mem[(register_count * 2) - 2] = 4;
11822 start_address = start_address + 4;
11826 else if (0x1F == opcode1)
11828 /* Handle arm syscall insn. */
11829 if (tdep->arm_syscall_record != NULL)
11831 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
11832 ret = tdep->arm_syscall_record (reg_cache, u_regval);
11836 printf_unfiltered (_("no syscall record support\n"));
11841 /* B (1), conditional branch is automatically taken care in process_record,
11842 as PC is saved there. */
11844 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11845 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11851 /* Handling opcode 111 insns. */
11854 thumb_record_branch (insn_decode_record *thumb_insn_r)
11856 uint32_t record_buf[8];
11857 uint32_t bits_h = 0;
11859 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
11861 if (2 == bits_h || 3 == bits_h)
11864 record_buf[0] = ARM_LR_REGNUM;
11865 thumb_insn_r->reg_rec_count = 1;
11867 else if (1 == bits_h)
11870 record_buf[0] = ARM_PS_REGNUM;
11871 record_buf[1] = ARM_LR_REGNUM;
11872 thumb_insn_r->reg_rec_count = 2;
11875 /* B(2) is automatically taken care in process_record, as PC is
11878 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11883 /* Handler for thumb2 load/store multiple instructions. */
11886 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
11888 struct regcache *reg_cache = thumb2_insn_r->regcache;
11890 uint32_t reg_rn, op;
11891 uint32_t register_bits = 0, register_count = 0;
11892 uint32_t index = 0, start_address = 0;
11893 uint32_t record_buf[24], record_buf_mem[48];
11895 ULONGEST u_regval = 0;
11897 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
11898 op = bits (thumb2_insn_r->arm_insn, 23, 24);
11900 if (0 == op || 3 == op)
11902 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11904 /* Handle RFE instruction. */
11905 record_buf[0] = ARM_PS_REGNUM;
11906 thumb2_insn_r->reg_rec_count = 1;
11910 /* Handle SRS instruction after reading banked SP. */
11911 return arm_record_unsupported_insn (thumb2_insn_r);
11914 else if (1 == op || 2 == op)
11916 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11918 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
11919 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
11920 while (register_bits)
11922 if (register_bits & 0x00000001)
11923 record_buf[index++] = register_count;
11926 register_bits = register_bits >> 1;
11928 record_buf[index++] = reg_rn;
11929 record_buf[index++] = ARM_PS_REGNUM;
11930 thumb2_insn_r->reg_rec_count = index;
11934 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
11935 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
11936 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11937 while (register_bits)
11939 if (register_bits & 0x00000001)
11942 register_bits = register_bits >> 1;
11947 /* Start address calculation for LDMDB/LDMEA. */
11948 start_address = u_regval;
11952 /* Start address calculation for LDMDB/LDMEA. */
11953 start_address = u_regval - register_count * 4;
11956 thumb2_insn_r->mem_rec_count = register_count;
11957 while (register_count)
11959 record_buf_mem[register_count * 2 - 1] = start_address;
11960 record_buf_mem[register_count * 2 - 2] = 4;
11961 start_address = start_address + 4;
11964 record_buf[0] = reg_rn;
11965 record_buf[1] = ARM_PS_REGNUM;
11966 thumb2_insn_r->reg_rec_count = 2;
11970 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
11972 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
11974 return ARM_RECORD_SUCCESS;
11977 /* Handler for thumb2 load/store (dual/exclusive) and table branch
11981 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
11983 struct regcache *reg_cache = thumb2_insn_r->regcache;
11985 uint32_t reg_rd, reg_rn, offset_imm;
11986 uint32_t reg_dest1, reg_dest2;
11987 uint32_t address, offset_addr;
11988 uint32_t record_buf[8], record_buf_mem[8];
11989 uint32_t op1, op2, op3;
11992 ULONGEST u_regval[2];
11994 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
11995 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
11996 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
11998 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12000 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
12002 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
12003 record_buf[0] = reg_dest1;
12004 record_buf[1] = ARM_PS_REGNUM;
12005 thumb2_insn_r->reg_rec_count = 2;
12008 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
12010 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12011 record_buf[2] = reg_dest2;
12012 thumb2_insn_r->reg_rec_count = 3;
12017 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12018 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12020 if (0 == op1 && 0 == op2)
12022 /* Handle STREX. */
12023 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12024 address = u_regval[0] + (offset_imm * 4);
12025 record_buf_mem[0] = 4;
12026 record_buf_mem[1] = address;
12027 thumb2_insn_r->mem_rec_count = 1;
12028 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12029 record_buf[0] = reg_rd;
12030 thumb2_insn_r->reg_rec_count = 1;
12032 else if (1 == op1 && 0 == op2)
12034 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12035 record_buf[0] = reg_rd;
12036 thumb2_insn_r->reg_rec_count = 1;
12037 address = u_regval[0];
12038 record_buf_mem[1] = address;
12042 /* Handle STREXB. */
12043 record_buf_mem[0] = 1;
12044 thumb2_insn_r->mem_rec_count = 1;
12048 /* Handle STREXH. */
12049 record_buf_mem[0] = 2 ;
12050 thumb2_insn_r->mem_rec_count = 1;
12054 /* Handle STREXD. */
12055 address = u_regval[0];
12056 record_buf_mem[0] = 4;
12057 record_buf_mem[2] = 4;
12058 record_buf_mem[3] = address + 4;
12059 thumb2_insn_r->mem_rec_count = 2;
12064 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12066 if (bit (thumb2_insn_r->arm_insn, 24))
12068 if (bit (thumb2_insn_r->arm_insn, 23))
12069 offset_addr = u_regval[0] + (offset_imm * 4);
12071 offset_addr = u_regval[0] - (offset_imm * 4);
12073 address = offset_addr;
12076 address = u_regval[0];
12078 record_buf_mem[0] = 4;
12079 record_buf_mem[1] = address;
12080 record_buf_mem[2] = 4;
12081 record_buf_mem[3] = address + 4;
12082 thumb2_insn_r->mem_rec_count = 2;
12083 record_buf[0] = reg_rn;
12084 thumb2_insn_r->reg_rec_count = 1;
12088 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12090 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12092 return ARM_RECORD_SUCCESS;
12095 /* Handler for thumb2 data processing (shift register and modified immediate)
12099 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
12101 uint32_t reg_rd, op;
12102 uint32_t record_buf[8];
12104 op = bits (thumb2_insn_r->arm_insn, 21, 24);
12105 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12107 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
12109 record_buf[0] = ARM_PS_REGNUM;
12110 thumb2_insn_r->reg_rec_count = 1;
12114 record_buf[0] = reg_rd;
12115 record_buf[1] = ARM_PS_REGNUM;
12116 thumb2_insn_r->reg_rec_count = 2;
12119 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12121 return ARM_RECORD_SUCCESS;
12124 /* Generic handler for thumb2 instructions which effect destination and PS
12128 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
12131 uint32_t record_buf[8];
12133 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12135 record_buf[0] = reg_rd;
12136 record_buf[1] = ARM_PS_REGNUM;
12137 thumb2_insn_r->reg_rec_count = 2;
12139 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12141 return ARM_RECORD_SUCCESS;
12144 /* Handler for thumb2 branch and miscellaneous control instructions. */
12147 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
12149 uint32_t op, op1, op2;
12150 uint32_t record_buf[8];
12152 op = bits (thumb2_insn_r->arm_insn, 20, 26);
12153 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
12154 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12156 /* Handle MSR insn. */
12157 if (!(op1 & 0x2) && 0x38 == op)
12161 /* CPSR is going to be changed. */
12162 record_buf[0] = ARM_PS_REGNUM;
12163 thumb2_insn_r->reg_rec_count = 1;
12167 arm_record_unsupported_insn(thumb2_insn_r);
12171 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
12174 record_buf[0] = ARM_PS_REGNUM;
12175 record_buf[1] = ARM_LR_REGNUM;
12176 thumb2_insn_r->reg_rec_count = 2;
12179 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12181 return ARM_RECORD_SUCCESS;
12184 /* Handler for thumb2 store single data item instructions. */
12187 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
12189 struct regcache *reg_cache = thumb2_insn_r->regcache;
12191 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
12192 uint32_t address, offset_addr;
12193 uint32_t record_buf[8], record_buf_mem[8];
12196 ULONGEST u_regval[2];
12198 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
12199 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
12200 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12201 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12203 if (bit (thumb2_insn_r->arm_insn, 23))
12206 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
12207 offset_addr = u_regval[0] + offset_imm;
12208 address = offset_addr;
12213 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
12215 /* Handle STRB (register). */
12216 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
12217 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
12218 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
12219 offset_addr = u_regval[1] << shift_imm;
12220 address = u_regval[0] + offset_addr;
12224 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12225 if (bit (thumb2_insn_r->arm_insn, 10))
12227 if (bit (thumb2_insn_r->arm_insn, 9))
12228 offset_addr = u_regval[0] + offset_imm;
12230 offset_addr = u_regval[0] - offset_imm;
12232 address = offset_addr;
12235 address = u_regval[0];
12241 /* Store byte instructions. */
12244 record_buf_mem[0] = 1;
12246 /* Store half word instructions. */
12249 record_buf_mem[0] = 2;
12251 /* Store word instructions. */
12254 record_buf_mem[0] = 4;
12258 gdb_assert_not_reached ("no decoding pattern found");
12262 record_buf_mem[1] = address;
12263 thumb2_insn_r->mem_rec_count = 1;
12264 record_buf[0] = reg_rn;
12265 thumb2_insn_r->reg_rec_count = 1;
12267 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12269 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12271 return ARM_RECORD_SUCCESS;
12274 /* Handler for thumb2 load memory hints instructions. */
12277 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
12279 uint32_t record_buf[8];
12280 uint32_t reg_rt, reg_rn;
12282 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
12283 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12285 if (ARM_PC_REGNUM != reg_rt)
12287 record_buf[0] = reg_rt;
12288 record_buf[1] = reg_rn;
12289 record_buf[2] = ARM_PS_REGNUM;
12290 thumb2_insn_r->reg_rec_count = 3;
12292 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12294 return ARM_RECORD_SUCCESS;
12297 return ARM_RECORD_FAILURE;
12300 /* Handler for thumb2 load word instructions. */
12303 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
12305 uint32_t opcode1 = 0, opcode2 = 0;
12306 uint32_t record_buf[8];
12308 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
12309 record_buf[1] = ARM_PS_REGNUM;
12310 thumb2_insn_r->reg_rec_count = 2;
12312 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12314 return ARM_RECORD_SUCCESS;
12317 /* Handler for thumb2 long multiply, long multiply accumulate, and
12318 divide instructions. */
12321 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
12323 uint32_t opcode1 = 0, opcode2 = 0;
12324 uint32_t record_buf[8];
12325 uint32_t reg_src1 = 0;
12327 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
12328 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
12330 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
12332 /* Handle SMULL, UMULL, SMULAL. */
12333 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12334 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12335 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12336 record_buf[2] = ARM_PS_REGNUM;
12337 thumb2_insn_r->reg_rec_count = 3;
12339 else if (1 == opcode1 || 3 == opcode2)
12341 /* Handle SDIV and UDIV. */
12342 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12343 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12344 record_buf[2] = ARM_PS_REGNUM;
12345 thumb2_insn_r->reg_rec_count = 3;
12348 return ARM_RECORD_FAILURE;
12350 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12352 return ARM_RECORD_SUCCESS;
12355 /* Record handler for thumb32 coprocessor instructions. */
12358 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
12360 if (bit (thumb2_insn_r->arm_insn, 25))
12361 return arm_record_coproc_data_proc (thumb2_insn_r);
12363 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
12366 /* Record handler for advance SIMD structure load/store instructions. */
12369 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
12371 struct regcache *reg_cache = thumb2_insn_r->regcache;
12372 uint32_t l_bit, a_bit, b_bits;
12373 uint32_t record_buf[128], record_buf_mem[128];
12374 uint32_t reg_rn, reg_vd, address, f_esize, f_elem;
12375 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
12378 l_bit = bit (thumb2_insn_r->arm_insn, 21);
12379 a_bit = bit (thumb2_insn_r->arm_insn, 23);
12380 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
12381 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12382 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
12383 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
12384 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
12385 f_esize = 8 * f_ebytes;
12386 f_elem = 8 / f_ebytes;
12390 ULONGEST u_regval = 0;
12391 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12392 address = u_regval;
12397 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12399 if (b_bits == 0x07)
12401 else if (b_bits == 0x0a)
12403 else if (b_bits == 0x06)
12405 else if (b_bits == 0x02)
12410 for (index_r = 0; index_r < bf_regs; index_r++)
12412 for (index_e = 0; index_e < f_elem; index_e++)
12414 record_buf_mem[index_m++] = f_ebytes;
12415 record_buf_mem[index_m++] = address;
12416 address = address + f_ebytes;
12417 thumb2_insn_r->mem_rec_count += 1;
12422 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12424 if (b_bits == 0x09 || b_bits == 0x08)
12426 else if (b_bits == 0x03)
12431 for (index_r = 0; index_r < bf_regs; index_r++)
12432 for (index_e = 0; index_e < f_elem; index_e++)
12434 for (loop_t = 0; loop_t < 2; loop_t++)
12436 record_buf_mem[index_m++] = f_ebytes;
12437 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12438 thumb2_insn_r->mem_rec_count += 1;
12440 address = address + (2 * f_ebytes);
12444 else if ((b_bits & 0x0e) == 0x04)
12446 for (index_e = 0; index_e < f_elem; index_e++)
12448 for (loop_t = 0; loop_t < 3; loop_t++)
12450 record_buf_mem[index_m++] = f_ebytes;
12451 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12452 thumb2_insn_r->mem_rec_count += 1;
12454 address = address + (3 * f_ebytes);
12458 else if (!(b_bits & 0x0e))
12460 for (index_e = 0; index_e < f_elem; index_e++)
12462 for (loop_t = 0; loop_t < 4; loop_t++)
12464 record_buf_mem[index_m++] = f_ebytes;
12465 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12466 thumb2_insn_r->mem_rec_count += 1;
12468 address = address + (4 * f_ebytes);
12474 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
12476 if (bft_size == 0x00)
12478 else if (bft_size == 0x01)
12480 else if (bft_size == 0x02)
12486 if (!(b_bits & 0x0b) || b_bits == 0x08)
12487 thumb2_insn_r->mem_rec_count = 1;
12489 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
12490 thumb2_insn_r->mem_rec_count = 2;
12492 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
12493 thumb2_insn_r->mem_rec_count = 3;
12495 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
12496 thumb2_insn_r->mem_rec_count = 4;
12498 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
12500 record_buf_mem[index_m] = f_ebytes;
12501 record_buf_mem[index_m] = address + (index_m * f_ebytes);
12510 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12511 thumb2_insn_r->reg_rec_count = 1;
12513 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12514 thumb2_insn_r->reg_rec_count = 2;
12516 else if ((b_bits & 0x0e) == 0x04)
12517 thumb2_insn_r->reg_rec_count = 3;
12519 else if (!(b_bits & 0x0e))
12520 thumb2_insn_r->reg_rec_count = 4;
12525 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
12526 thumb2_insn_r->reg_rec_count = 1;
12528 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
12529 thumb2_insn_r->reg_rec_count = 2;
12531 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
12532 thumb2_insn_r->reg_rec_count = 3;
12534 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
12535 thumb2_insn_r->reg_rec_count = 4;
12537 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
12538 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
12542 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
12544 record_buf[index_r] = reg_rn;
12545 thumb2_insn_r->reg_rec_count += 1;
12548 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12550 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12555 /* Decodes thumb2 instruction type and invokes its record handler. */
12557 static unsigned int
12558 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
12560 uint32_t op, op1, op2;
12562 op = bit (thumb2_insn_r->arm_insn, 15);
12563 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
12564 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
12568 if (!(op2 & 0x64 ))
12570 /* Load/store multiple instruction. */
12571 return thumb2_record_ld_st_multiple (thumb2_insn_r);
12573 else if (!((op2 & 0x64) ^ 0x04))
12575 /* Load/store (dual/exclusive) and table branch instruction. */
12576 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
12578 else if (!((op2 & 0x20) ^ 0x20))
12580 /* Data-processing (shifted register). */
12581 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12583 else if (op2 & 0x40)
12585 /* Co-processor instructions. */
12586 return thumb2_record_coproc_insn (thumb2_insn_r);
12589 else if (op1 == 0x02)
12593 /* Branches and miscellaneous control instructions. */
12594 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
12596 else if (op2 & 0x20)
12598 /* Data-processing (plain binary immediate) instruction. */
12599 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12603 /* Data-processing (modified immediate). */
12604 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12607 else if (op1 == 0x03)
12609 if (!(op2 & 0x71 ))
12611 /* Store single data item. */
12612 return thumb2_record_str_single_data (thumb2_insn_r);
12614 else if (!((op2 & 0x71) ^ 0x10))
12616 /* Advanced SIMD or structure load/store instructions. */
12617 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
12619 else if (!((op2 & 0x67) ^ 0x01))
12621 /* Load byte, memory hints instruction. */
12622 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12624 else if (!((op2 & 0x67) ^ 0x03))
12626 /* Load halfword, memory hints instruction. */
12627 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12629 else if (!((op2 & 0x67) ^ 0x05))
12631 /* Load word instruction. */
12632 return thumb2_record_ld_word (thumb2_insn_r);
12634 else if (!((op2 & 0x70) ^ 0x20))
12636 /* Data-processing (register) instruction. */
12637 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12639 else if (!((op2 & 0x78) ^ 0x30))
12641 /* Multiply, multiply accumulate, abs diff instruction. */
12642 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12644 else if (!((op2 & 0x78) ^ 0x38))
12646 /* Long multiply, long multiply accumulate, and divide. */
12647 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
12649 else if (op2 & 0x40)
12651 /* Co-processor instructions. */
12652 return thumb2_record_coproc_insn (thumb2_insn_r);
12659 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12660 and positive val on fauilure. */
12663 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12665 gdb_byte buf[insn_size];
12667 memset (&buf[0], 0, insn_size);
12669 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12671 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12673 gdbarch_byte_order_for_code (insn_record->gdbarch));
12677 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12679 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12683 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12684 uint32_t insn_size)
12687 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12688 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
12690 arm_record_data_proc_misc_ld_str, /* 000. */
12691 arm_record_data_proc_imm, /* 001. */
12692 arm_record_ld_st_imm_offset, /* 010. */
12693 arm_record_ld_st_reg_offset, /* 011. */
12694 arm_record_ld_st_multiple, /* 100. */
12695 arm_record_b_bl, /* 101. */
12696 arm_record_asimd_vfp_coproc, /* 110. */
12697 arm_record_coproc_data_proc /* 111. */
12700 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12701 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
12703 thumb_record_shift_add_sub, /* 000. */
12704 thumb_record_add_sub_cmp_mov, /* 001. */
12705 thumb_record_ld_st_reg_offset, /* 010. */
12706 thumb_record_ld_st_imm_offset, /* 011. */
12707 thumb_record_ld_st_stack, /* 100. */
12708 thumb_record_misc, /* 101. */
12709 thumb_record_ldm_stm_swi, /* 110. */
12710 thumb_record_branch /* 111. */
12713 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12714 uint32_t insn_id = 0;
12716 if (extract_arm_insn (arm_record, insn_size))
12720 printf_unfiltered (_("Process record: error reading memory at "
12721 "addr %s len = %d.\n"),
12722 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
12726 else if (ARM_RECORD == record_type)
12728 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12729 insn_id = bits (arm_record->arm_insn, 25, 27);
12730 ret = arm_record_extension_space (arm_record);
12731 /* If this insn has fallen into extension space
12732 then we need not decode it anymore. */
12733 if (ret != -1 && !INSN_RECORDED(arm_record))
12735 ret = arm_handle_insn[insn_id] (arm_record);
12738 else if (THUMB_RECORD == record_type)
12740 /* As thumb does not have condition codes, we set negative. */
12741 arm_record->cond = -1;
12742 insn_id = bits (arm_record->arm_insn, 13, 15);
12743 ret = thumb_handle_insn[insn_id] (arm_record);
12745 else if (THUMB2_RECORD == record_type)
12747 /* As thumb does not have condition codes, we set negative. */
12748 arm_record->cond = -1;
12750 /* Swap first half of 32bit thumb instruction with second half. */
12751 arm_record->arm_insn
12752 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
12754 insn_id = thumb2_record_decode_insn_handler (arm_record);
12756 if (insn_id != ARM_RECORD_SUCCESS)
12758 arm_record_unsupported_insn (arm_record);
12764 /* Throw assertion. */
12765 gdb_assert_not_reached ("not a valid instruction, could not decode");
12772 /* Cleans up local record registers and memory allocations. */
12775 deallocate_reg_mem (insn_decode_record *record)
12777 xfree (record->arm_regs);
12778 xfree (record->arm_mems);
12782 /* Parse the current instruction and record the values of the registers and
12783 memory that will be changed in current instruction to record_arch_list".
12784 Return -1 if something is wrong. */
12787 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
12788 CORE_ADDR insn_addr)
12791 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
12792 uint32_t no_of_rec = 0;
12793 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
12794 ULONGEST t_bit = 0, insn_id = 0;
12796 ULONGEST u_regval = 0;
12798 insn_decode_record arm_record;
12800 memset (&arm_record, 0, sizeof (insn_decode_record));
12801 arm_record.regcache = regcache;
12802 arm_record.this_addr = insn_addr;
12803 arm_record.gdbarch = gdbarch;
12806 if (record_debug > 1)
12808 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
12810 paddress (gdbarch, arm_record.this_addr));
12813 if (extract_arm_insn (&arm_record, 2))
12817 printf_unfiltered (_("Process record: error reading memory at "
12818 "addr %s len = %d.\n"),
12819 paddress (arm_record.gdbarch,
12820 arm_record.this_addr), 2);
12825 /* Check the insn, whether it is thumb or arm one. */
12827 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
12828 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
12831 if (!(u_regval & t_bit))
12833 /* We are decoding arm insn. */
12834 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
12838 insn_id = bits (arm_record.arm_insn, 11, 15);
12839 /* is it thumb2 insn? */
12840 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
12842 ret = decode_insn (&arm_record, THUMB2_RECORD,
12843 THUMB2_INSN_SIZE_BYTES);
12847 /* We are decoding thumb insn. */
12848 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
12854 /* Record registers. */
12855 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
12856 if (arm_record.arm_regs)
12858 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
12860 if (record_full_arch_list_add_reg
12861 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
12865 /* Record memories. */
12866 if (arm_record.arm_mems)
12868 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
12870 if (record_full_arch_list_add_mem
12871 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
12872 arm_record.arm_mems[no_of_rec].len))
12877 if (record_full_arch_list_add_end ())
12882 deallocate_reg_mem (&arm_record);