1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-1989, 1991-1993, 1995-1996, 1998-2012 Free
4 Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include <ctype.h> /* XXX for isupper (). */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "gdb/sim-arm.h"
53 #include "coff/internal.h"
56 #include "gdb_assert.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data *arm_objfile_data_key;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
93 DEF_VEC_O(arm_mapping_symbol_s);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s) **section_maps;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element *setarmcmdlist = NULL;
102 static struct cmd_list_element *showarmcmdlist = NULL;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
118 static const char *current_fp_model = "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
131 static const char *arm_abi_string = "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings[] =
142 static const char *arm_fallback_mode_string = "auto";
143 static const char *arm_force_mode_string = "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode = -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element *);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat *, const void *,
229 static void convert_to_extended (const struct floatformat *, void *,
232 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
233 struct regcache *regcache,
234 int regnum, gdb_byte *buf);
235 static void arm_neon_quad_write (struct gdbarch *gdbarch,
236 struct regcache *regcache,
237 int regnum, const gdb_byte *buf);
239 static int thumb_insn_size (unsigned short inst1);
241 struct arm_prologue_cache
243 /* The stack pointer at the time this frame was created; i.e. the
244 caller's stack pointer when this function was called. It is used
245 to identify this frame. */
248 /* The frame base for this frame is just prev_sp - frame size.
249 FRAMESIZE is the distance from the frame pointer to the
250 initial stack pointer. */
254 /* The register used to hold the frame pointer for this frame. */
257 /* Saved register offsets. */
258 struct trad_frame_saved_reg *saved_regs;
261 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
262 CORE_ADDR prologue_start,
263 CORE_ADDR prologue_end,
264 struct arm_prologue_cache *cache);
266 /* Architecture version for displaced stepping. This effects the behaviour of
267 certain instructions, and really should not be hard-wired. */
269 #define DISPLACED_STEPPING_ARCH_VERSION 5
271 /* Addresses for calling Thumb functions have the bit 0 set.
272 Here are some macros to test, set, or clear bit 0 of addresses. */
273 #define IS_THUMB_ADDR(addr) ((addr) & 1)
274 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
275 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch *gdbarch)
286 if (gdbarch_tdep (gdbarch)->is_m)
292 /* Determine if FRAME is executing in Thumb mode. */
295 arm_frame_is_thumb (struct frame_info *frame)
298 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
300 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
301 directly (from a signal frame or dummy frame) or by interpreting
302 the saved LR (from a prologue or DWARF frame). So consult it and
303 trust the unwinders. */
304 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
306 return (cpsr & t_bit) != 0;
309 /* Callback for VEC_lower_bound. */
312 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
313 const struct arm_mapping_symbol *rhs)
315 return lhs->value < rhs->value;
318 /* Search for the mapping symbol covering MEMADDR. If one is found,
319 return its type. Otherwise, return 0. If START is non-NULL,
320 set *START to the location of the mapping symbol. */
323 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
325 struct obj_section *sec;
327 /* If there are mapping symbols, consult them. */
328 sec = find_pc_section (memaddr);
331 struct arm_per_objfile *data;
332 VEC(arm_mapping_symbol_s) *map;
333 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
337 data = objfile_data (sec->objfile, arm_objfile_data_key);
340 map = data->section_maps[sec->the_bfd_section->index];
341 if (!VEC_empty (arm_mapping_symbol_s, map))
343 struct arm_mapping_symbol *map_sym;
345 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
346 arm_compare_mapping_symbols);
348 /* VEC_lower_bound finds the earliest ordered insertion
349 point. If the following symbol starts at this exact
350 address, we use that; otherwise, the preceding
351 mapping symbol covers this address. */
352 if (idx < VEC_length (arm_mapping_symbol_s, map))
354 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
355 if (map_sym->value == map_key.value)
358 *start = map_sym->value + obj_section_addr (sec);
359 return map_sym->type;
365 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
367 *start = map_sym->value + obj_section_addr (sec);
368 return map_sym->type;
377 /* Determine if the program counter specified in MEMADDR is in a Thumb
378 function. This function should be called for addresses unrelated to
379 any executing frame; otherwise, prefer arm_frame_is_thumb. */
382 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
384 struct minimal_symbol *sym;
386 struct displaced_step_closure* dsc
387 = get_displaced_step_closure_by_addr(memaddr);
389 /* If checking the mode of displaced instruction in copy area, the mode
390 should be determined by instruction on the original address. */
394 fprintf_unfiltered (gdb_stdlog,
395 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (unsigned long) dsc->insn_addr,
397 (unsigned long) memaddr);
398 memaddr = dsc->insn_addr;
401 /* If bit 0 of the address is set, assume this is a Thumb address. */
402 if (IS_THUMB_ADDR (memaddr))
405 /* Respect internal mode override if active. */
406 if (arm_override_mode != -1)
407 return arm_override_mode;
409 /* If the user wants to override the symbol table, let him. */
410 if (strcmp (arm_force_mode_string, "arm") == 0)
412 if (strcmp (arm_force_mode_string, "thumb") == 0)
415 /* ARM v6-M and v7-M are always in Thumb mode. */
416 if (gdbarch_tdep (gdbarch)->is_m)
419 /* If there are mapping symbols, consult them. */
420 type = arm_find_mapping_symbol (memaddr, NULL);
424 /* Thumb functions have a "special" bit set in minimal symbols. */
425 sym = lookup_minimal_symbol_by_pc (memaddr);
427 return (MSYMBOL_IS_SPECIAL (sym));
429 /* If the user wants to override the fallback mode, let them. */
430 if (strcmp (arm_fallback_mode_string, "arm") == 0)
432 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
435 /* If we couldn't find any symbol, but we're talking to a running
436 target, then trust the current value of $cpsr. This lets
437 "display/i $pc" always show the correct mode (though if there is
438 a symbol table we will not reach here, so it still may not be
439 displayed in the mode it will be executed). */
440 if (target_has_registers)
441 return arm_frame_is_thumb (get_current_frame ());
443 /* Otherwise we're out of luck; we assume ARM. */
447 /* Remove useless bits from addresses in a running program. */
449 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
451 /* On M-profile devices, do not strip the low bit from EXC_RETURN
452 (the magic exception return address). */
453 if (gdbarch_tdep (gdbarch)->is_m
454 && (val & 0xfffffff0) == 0xfffffff0)
458 return UNMAKE_THUMB_ADDR (val);
460 return (val & 0x03fffffc);
463 /* When reading symbols, we need to zap the low bit of the address,
464 which may be set to 1 for Thumb functions. */
466 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
471 /* Return 1 if PC is the start of a compiler helper function which
472 can be safely ignored during prologue skipping. IS_THUMB is true
473 if the function is known to be a Thumb function due to the way it
476 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
478 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
479 struct minimal_symbol *msym;
481 msym = lookup_minimal_symbol_by_pc (pc);
483 && SYMBOL_VALUE_ADDRESS (msym) == pc
484 && SYMBOL_LINKAGE_NAME (msym) != NULL)
486 const char *name = SYMBOL_LINKAGE_NAME (msym);
488 /* The GNU linker's Thumb call stub to foo is named
490 if (strstr (name, "_from_thumb") != NULL)
493 /* On soft-float targets, __truncdfsf2 is called to convert promoted
494 arguments to their argument types in non-prototyped
496 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
498 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
501 /* Internal functions related to thread-local storage. */
502 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
504 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
509 /* If we run against a stripped glibc, we may be unable to identify
510 special functions by name. Check for one important case,
511 __aeabi_read_tp, by comparing the *code* against the default
512 implementation (this is hand-written ARM assembler in glibc). */
515 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
516 == 0xe3e00a0f /* mov r0, #0xffff0fff */
517 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
518 == 0xe240f01f) /* sub pc, r0, #31 */
525 /* Support routines for instruction parsing. */
526 #define submask(x) ((1L << ((x) + 1)) - 1)
527 #define bit(obj,st) (((obj) >> (st)) & 1)
528 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
529 #define sbits(obj,st,fn) \
530 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
531 #define BranchDest(addr,instr) \
532 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
534 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
535 the first 16-bit of instruction, and INSN2 is the second 16-bit of
537 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
538 ((bits ((insn1), 0, 3) << 12) \
539 | (bits ((insn1), 10, 10) << 11) \
540 | (bits ((insn2), 12, 14) << 8) \
541 | bits ((insn2), 0, 7))
543 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
544 the 32-bit instruction. */
545 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
546 ((bits ((insn), 16, 19) << 12) \
547 | bits ((insn), 0, 11))
549 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
552 thumb_expand_immediate (unsigned int imm)
554 unsigned int count = imm >> 7;
562 return (imm & 0xff) | ((imm & 0xff) << 16);
564 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
566 return (imm & 0xff) | ((imm & 0xff) << 8)
567 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
570 return (0x80 | (imm & 0x7f)) << (32 - count);
573 /* Return 1 if the 16-bit Thumb instruction INST might change
574 control flow, 0 otherwise. */
577 thumb_instruction_changes_pc (unsigned short inst)
579 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
582 if ((inst & 0xf000) == 0xd000) /* conditional branch */
585 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
588 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
591 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
594 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
600 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
601 might change control flow, 0 otherwise. */
604 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
606 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
608 /* Branches and miscellaneous control instructions. */
610 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
615 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
617 /* SUBS PC, LR, #imm8. */
620 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
622 /* Conditional branch. */
629 if ((inst1 & 0xfe50) == 0xe810)
631 /* Load multiple or RFE. */
633 if (bit (inst1, 7) && !bit (inst1, 8))
639 else if (!bit (inst1, 7) && bit (inst1, 8))
645 else if (bit (inst1, 7) && bit (inst1, 8))
650 else if (!bit (inst1, 7) && !bit (inst1, 8))
659 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
661 /* MOV PC or MOVS PC. */
665 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
668 if (bits (inst1, 0, 3) == 15)
674 if ((inst2 & 0x0fc0) == 0x0000)
680 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
686 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
695 /* Analyze a Thumb prologue, looking for a recognizable stack frame
696 and frame pointer. Scan until we encounter a store that could
697 clobber the stack frame unexpectedly, or an unknown instruction.
698 Return the last address which is definitely safe to skip for an
699 initial breakpoint. */
702 thumb_analyze_prologue (struct gdbarch *gdbarch,
703 CORE_ADDR start, CORE_ADDR limit,
704 struct arm_prologue_cache *cache)
706 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
707 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
710 struct pv_area *stack;
711 struct cleanup *back_to;
713 CORE_ADDR unrecognized_pc = 0;
715 for (i = 0; i < 16; i++)
716 regs[i] = pv_register (i, 0);
717 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
718 back_to = make_cleanup_free_pv_area (stack);
720 while (start < limit)
724 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
726 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
731 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
734 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
735 whether to save LR (R14). */
736 mask = (insn & 0xff) | ((insn & 0x100) << 6);
738 /* Calculate offsets of saved R0-R7 and LR. */
739 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
740 if (mask & (1 << regno))
742 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
744 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
747 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
750 offset = (insn & 0x7f) << 2; /* get scaled offset */
751 if (insn & 0x80) /* Check for SUB. */
752 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
755 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
758 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
759 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
761 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
762 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
763 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
765 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
766 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
767 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
769 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
770 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
771 && pv_is_constant (regs[bits (insn, 3, 5)]))
772 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
773 regs[bits (insn, 6, 8)]);
774 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
775 && pv_is_constant (regs[bits (insn, 3, 6)]))
777 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
778 int rm = bits (insn, 3, 6);
779 regs[rd] = pv_add (regs[rd], regs[rm]);
781 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
783 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
784 int src_reg = (insn & 0x78) >> 3;
785 regs[dst_reg] = regs[src_reg];
787 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
789 /* Handle stores to the stack. Normally pushes are used,
790 but with GCC -mtpcs-frame, there may be other stores
791 in the prologue to create the frame. */
792 int regno = (insn >> 8) & 0x7;
795 offset = (insn & 0xff) << 2;
796 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
798 if (pv_area_store_would_trash (stack, addr))
801 pv_area_store (stack, addr, 4, regs[regno]);
803 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
805 int rd = bits (insn, 0, 2);
806 int rn = bits (insn, 3, 5);
809 offset = bits (insn, 6, 10) << 2;
810 addr = pv_add_constant (regs[rn], offset);
812 if (pv_area_store_would_trash (stack, addr))
815 pv_area_store (stack, addr, 4, regs[rd]);
817 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
818 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
819 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
820 /* Ignore stores of argument registers to the stack. */
822 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
823 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
824 /* Ignore block loads from the stack, potentially copying
825 parameters from memory. */
827 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
828 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
829 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
830 /* Similarly ignore single loads from the stack. */
832 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
833 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
834 /* Skip register copies, i.e. saves to another register
835 instead of the stack. */
837 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
838 /* Recognize constant loads; even with small stacks these are necessary
840 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
841 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
843 /* Constant pool loads, for the same reason. */
844 unsigned int constant;
847 loc = start + 4 + bits (insn, 0, 7) * 4;
848 constant = read_memory_unsigned_integer (loc, 4, byte_order);
849 regs[bits (insn, 8, 10)] = pv_constant (constant);
851 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
853 unsigned short inst2;
855 inst2 = read_memory_unsigned_integer (start + 2, 2,
856 byte_order_for_code);
858 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
860 /* BL, BLX. Allow some special function calls when
861 skipping the prologue; GCC generates these before
862 storing arguments to the stack. */
864 int j1, j2, imm1, imm2;
866 imm1 = sbits (insn, 0, 10);
867 imm2 = bits (inst2, 0, 10);
868 j1 = bit (inst2, 13);
869 j2 = bit (inst2, 11);
871 offset = ((imm1 << 12) + (imm2 << 1));
872 offset ^= ((!j2) << 22) | ((!j1) << 23);
874 nextpc = start + 4 + offset;
875 /* For BLX make sure to clear the low bits. */
876 if (bit (inst2, 12) == 0)
877 nextpc = nextpc & 0xfffffffc;
879 if (!skip_prologue_function (gdbarch, nextpc,
880 bit (inst2, 12) != 0))
884 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
886 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
888 pv_t addr = regs[bits (insn, 0, 3)];
891 if (pv_area_store_would_trash (stack, addr))
894 /* Calculate offsets of saved registers. */
895 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
896 if (inst2 & (1 << regno))
898 addr = pv_add_constant (addr, -4);
899 pv_area_store (stack, addr, 4, regs[regno]);
903 regs[bits (insn, 0, 3)] = addr;
906 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
908 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
910 int regno1 = bits (inst2, 12, 15);
911 int regno2 = bits (inst2, 8, 11);
912 pv_t addr = regs[bits (insn, 0, 3)];
914 offset = inst2 & 0xff;
916 addr = pv_add_constant (addr, offset);
918 addr = pv_add_constant (addr, -offset);
920 if (pv_area_store_would_trash (stack, addr))
923 pv_area_store (stack, addr, 4, regs[regno1]);
924 pv_area_store (stack, pv_add_constant (addr, 4),
928 regs[bits (insn, 0, 3)] = addr;
931 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
932 && (inst2 & 0x0c00) == 0x0c00
933 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
935 int regno = bits (inst2, 12, 15);
936 pv_t addr = regs[bits (insn, 0, 3)];
938 offset = inst2 & 0xff;
940 addr = pv_add_constant (addr, offset);
942 addr = pv_add_constant (addr, -offset);
944 if (pv_area_store_would_trash (stack, addr))
947 pv_area_store (stack, addr, 4, regs[regno]);
950 regs[bits (insn, 0, 3)] = addr;
953 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
954 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
956 int regno = bits (inst2, 12, 15);
959 offset = inst2 & 0xfff;
960 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
962 if (pv_area_store_would_trash (stack, addr))
965 pv_area_store (stack, addr, 4, regs[regno]);
968 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
969 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
970 /* Ignore stores of argument registers to the stack. */
973 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
974 && (inst2 & 0x0d00) == 0x0c00
975 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
976 /* Ignore stores of argument registers to the stack. */
979 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
981 && (inst2 & 0x8000) == 0x0000
982 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
983 /* Ignore block loads from the stack, potentially copying
984 parameters from memory. */
987 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
989 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
990 /* Similarly ignore dual loads from the stack. */
993 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
994 && (inst2 & 0x0d00) == 0x0c00
995 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
996 /* Similarly ignore single loads from the stack. */
999 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1000 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
1001 /* Similarly ignore single loads from the stack. */
1004 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1005 && (inst2 & 0x8000) == 0x0000)
1007 unsigned int imm = ((bits (insn, 10, 10) << 11)
1008 | (bits (inst2, 12, 14) << 8)
1009 | bits (inst2, 0, 7));
1011 regs[bits (inst2, 8, 11)]
1012 = pv_add_constant (regs[bits (insn, 0, 3)],
1013 thumb_expand_immediate (imm));
1016 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1017 && (inst2 & 0x8000) == 0x0000)
1019 unsigned int imm = ((bits (insn, 10, 10) << 11)
1020 | (bits (inst2, 12, 14) << 8)
1021 | bits (inst2, 0, 7));
1023 regs[bits (inst2, 8, 11)]
1024 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1027 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1028 && (inst2 & 0x8000) == 0x0000)
1030 unsigned int imm = ((bits (insn, 10, 10) << 11)
1031 | (bits (inst2, 12, 14) << 8)
1032 | bits (inst2, 0, 7));
1034 regs[bits (inst2, 8, 11)]
1035 = pv_add_constant (regs[bits (insn, 0, 3)],
1036 - (CORE_ADDR) thumb_expand_immediate (imm));
1039 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1040 && (inst2 & 0x8000) == 0x0000)
1042 unsigned int imm = ((bits (insn, 10, 10) << 11)
1043 | (bits (inst2, 12, 14) << 8)
1044 | bits (inst2, 0, 7));
1046 regs[bits (inst2, 8, 11)]
1047 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1050 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1052 unsigned int imm = ((bits (insn, 10, 10) << 11)
1053 | (bits (inst2, 12, 14) << 8)
1054 | bits (inst2, 0, 7));
1056 regs[bits (inst2, 8, 11)]
1057 = pv_constant (thumb_expand_immediate (imm));
1060 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1063 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1065 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1068 else if (insn == 0xea5f /* mov.w Rd,Rm */
1069 && (inst2 & 0xf0f0) == 0)
1071 int dst_reg = (inst2 & 0x0f00) >> 8;
1072 int src_reg = inst2 & 0xf;
1073 regs[dst_reg] = regs[src_reg];
1076 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1078 /* Constant pool loads. */
1079 unsigned int constant;
1082 offset = bits (insn, 0, 11);
1084 loc = start + 4 + offset;
1086 loc = start + 4 - offset;
1088 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1089 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1092 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1094 /* Constant pool loads. */
1095 unsigned int constant;
1098 offset = bits (insn, 0, 7) << 2;
1100 loc = start + 4 + offset;
1102 loc = start + 4 - offset;
1104 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1105 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1107 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1108 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1111 else if (thumb2_instruction_changes_pc (insn, inst2))
1113 /* Don't scan past anything that might change control flow. */
1118 /* The optimizer might shove anything into the prologue,
1119 so we just skip what we don't recognize. */
1120 unrecognized_pc = start;
1125 else if (thumb_instruction_changes_pc (insn))
1127 /* Don't scan past anything that might change control flow. */
1132 /* The optimizer might shove anything into the prologue,
1133 so we just skip what we don't recognize. */
1134 unrecognized_pc = start;
1141 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1142 paddress (gdbarch, start));
1144 if (unrecognized_pc == 0)
1145 unrecognized_pc = start;
1149 do_cleanups (back_to);
1150 return unrecognized_pc;
1153 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1155 /* Frame pointer is fp. Frame size is constant. */
1156 cache->framereg = ARM_FP_REGNUM;
1157 cache->framesize = -regs[ARM_FP_REGNUM].k;
1159 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1161 /* Frame pointer is r7. Frame size is constant. */
1162 cache->framereg = THUMB_FP_REGNUM;
1163 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1167 /* Try the stack pointer... this is a bit desperate. */
1168 cache->framereg = ARM_SP_REGNUM;
1169 cache->framesize = -regs[ARM_SP_REGNUM].k;
1172 for (i = 0; i < 16; i++)
1173 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1174 cache->saved_regs[i].addr = offset;
1176 do_cleanups (back_to);
1177 return unrecognized_pc;
1181 /* Try to analyze the instructions starting from PC, which load symbol
1182 __stack_chk_guard. Return the address of instruction after loading this
1183 symbol, set the dest register number to *BASEREG, and set the size of
1184 instructions for loading symbol in OFFSET. Return 0 if instructions are
1188 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1189 unsigned int *destreg, int *offset)
1191 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1192 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1193 unsigned int low, high, address;
1198 unsigned short insn1
1199 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1201 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1203 *destreg = bits (insn1, 8, 10);
1205 address = bits (insn1, 0, 7);
1207 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1209 unsigned short insn2
1210 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1212 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1215 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1217 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1219 /* movt Rd, #const */
1220 if ((insn1 & 0xfbc0) == 0xf2c0)
1222 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1223 *destreg = bits (insn2, 8, 11);
1225 address = (high << 16 | low);
1232 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1234 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1236 address = bits (insn, 0, 11);
1237 *destreg = bits (insn, 12, 15);
1240 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1242 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1245 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1247 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1249 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1250 *destreg = bits (insn, 12, 15);
1252 address = (high << 16 | low);
1260 /* Try to skip a sequence of instructions used for stack protector. If PC
1261 points to the first instruction of this sequence, return the address of
1262 first instruction after this sequence, otherwise, return original PC.
1264 On arm, this sequence of instructions is composed of mainly three steps,
1265 Step 1: load symbol __stack_chk_guard,
1266 Step 2: load from address of __stack_chk_guard,
1267 Step 3: store it to somewhere else.
1269 Usually, instructions on step 2 and step 3 are the same on various ARM
1270 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1271 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1272 instructions in step 1 vary from different ARM architectures. On ARMv7,
1275 movw Rn, #:lower16:__stack_chk_guard
1276 movt Rn, #:upper16:__stack_chk_guard
1283 .word __stack_chk_guard
1285 Since ldr/str is a very popular instruction, we can't use them as
1286 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1287 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1288 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1291 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1293 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1294 unsigned int basereg;
1295 struct minimal_symbol *stack_chk_guard;
1297 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1300 /* Try to parse the instructions in Step 1. */
1301 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1306 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1307 /* If name of symbol doesn't start with '__stack_chk_guard', this
1308 instruction sequence is not for stack protector. If symbol is
1309 removed, we conservatively think this sequence is for stack protector. */
1311 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
1312 strlen ("__stack_chk_guard")) != 0)
1317 unsigned int destreg;
1319 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1321 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1322 if ((insn & 0xf800) != 0x6800)
1324 if (bits (insn, 3, 5) != basereg)
1326 destreg = bits (insn, 0, 2);
1328 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1329 byte_order_for_code);
1330 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1331 if ((insn & 0xf800) != 0x6000)
1333 if (destreg != bits (insn, 0, 2))
1338 unsigned int destreg;
1340 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1342 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1343 if ((insn & 0x0e500000) != 0x04100000)
1345 if (bits (insn, 16, 19) != basereg)
1347 destreg = bits (insn, 12, 15);
1348 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1349 insn = read_memory_unsigned_integer (pc + offset + 4,
1350 4, byte_order_for_code);
1351 if ((insn & 0x0e500000) != 0x04000000)
1353 if (bits (insn, 12, 15) != destreg)
1356 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1359 return pc + offset + 4;
1361 return pc + offset + 8;
1364 /* Advance the PC across any function entry prologue instructions to
1365 reach some "real" code.
1367 The APCS (ARM Procedure Call Standard) defines the following
1371 [stmfd sp!, {a1,a2,a3,a4}]
1372 stmfd sp!, {...,fp,ip,lr,pc}
1373 [stfe f7, [sp, #-12]!]
1374 [stfe f6, [sp, #-12]!]
1375 [stfe f5, [sp, #-12]!]
1376 [stfe f4, [sp, #-12]!]
1377 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1380 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1382 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1385 CORE_ADDR func_addr, limit_pc;
1387 /* See if we can determine the end of the prologue via the symbol table.
1388 If so, then return either PC, or the PC after the prologue, whichever
1390 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1392 CORE_ADDR post_prologue_pc
1393 = skip_prologue_using_sal (gdbarch, func_addr);
1394 struct symtab *s = find_pc_symtab (func_addr);
1396 if (post_prologue_pc)
1398 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1401 /* GCC always emits a line note before the prologue and another
1402 one after, even if the two are at the same address or on the
1403 same line. Take advantage of this so that we do not need to
1404 know every instruction that might appear in the prologue. We
1405 will have producer information for most binaries; if it is
1406 missing (e.g. for -gstabs), assuming the GNU tools. */
1407 if (post_prologue_pc
1409 || s->producer == NULL
1410 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0
1411 || strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
1412 return post_prologue_pc;
1414 if (post_prologue_pc != 0)
1416 CORE_ADDR analyzed_limit;
1418 /* For non-GCC compilers, make sure the entire line is an
1419 acceptable prologue; GDB will round this function's
1420 return value up to the end of the following line so we
1421 can not skip just part of a line (and we do not want to).
1423 RealView does not treat the prologue specially, but does
1424 associate prologue code with the opening brace; so this
1425 lets us skip the first line if we think it is the opening
1427 if (arm_pc_is_thumb (gdbarch, func_addr))
1428 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1429 post_prologue_pc, NULL);
1431 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1432 post_prologue_pc, NULL);
1434 if (analyzed_limit != post_prologue_pc)
1437 return post_prologue_pc;
1441 /* Can't determine prologue from the symbol table, need to examine
1444 /* Find an upper limit on the function prologue using the debug
1445 information. If the debug information could not be used to provide
1446 that bound, then use an arbitrary large number as the upper bound. */
1447 /* Like arm_scan_prologue, stop no later than pc + 64. */
1448 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1450 limit_pc = pc + 64; /* Magic. */
1453 /* Check if this is Thumb code. */
1454 if (arm_pc_is_thumb (gdbarch, pc))
1455 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1457 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1459 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1461 /* "mov ip, sp" is no longer a required part of the prologue. */
1462 if (inst == 0xe1a0c00d) /* mov ip, sp */
1465 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1468 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1471 /* Some prologues begin with "str lr, [sp, #-4]!". */
1472 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1475 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1478 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1481 /* Any insns after this point may float into the code, if it makes
1482 for better instruction scheduling, so we skip them only if we
1483 find them, but still consider the function to be frame-ful. */
1485 /* We may have either one sfmfd instruction here, or several stfe
1486 insns, depending on the version of floating point code we
1488 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1491 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1494 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1497 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1500 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1501 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1502 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1505 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1506 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1507 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1510 /* Un-recognized instruction; stop scanning. */
1514 return skip_pc; /* End of prologue. */
1518 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1519 This function decodes a Thumb function prologue to determine:
1520 1) the size of the stack frame
1521 2) which registers are saved on it
1522 3) the offsets of saved regs
1523 4) the offset from the stack pointer to the frame pointer
1525 A typical Thumb function prologue would create this stack frame
1526 (offsets relative to FP)
1527 old SP -> 24 stack parameters
1530 R7 -> 0 local variables (16 bytes)
1531 SP -> -12 additional stack space (12 bytes)
1532 The frame size would thus be 36 bytes, and the frame offset would be
1533 12 bytes. The frame register is R7.
1535 The comments for thumb_skip_prolog() describe the algorithm we use
1536 to detect the end of the prolog. */
1540 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1541 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1543 CORE_ADDR prologue_start;
1544 CORE_ADDR prologue_end;
1546 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1549 /* See comment in arm_scan_prologue for an explanation of
1551 if (prologue_end > prologue_start + 64)
1553 prologue_end = prologue_start + 64;
1557 /* We're in the boondocks: we have no idea where the start of the
1561 prologue_end = min (prologue_end, prev_pc);
1563 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1566 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1569 arm_instruction_changes_pc (uint32_t this_instr)
1571 if (bits (this_instr, 28, 31) == INST_NV)
1572 /* Unconditional instructions. */
1573 switch (bits (this_instr, 24, 27))
1577 /* Branch with Link and change to Thumb. */
1582 /* Coprocessor register transfer. */
1583 if (bits (this_instr, 12, 15) == 15)
1584 error (_("Invalid update to pc in instruction"));
1590 switch (bits (this_instr, 25, 27))
1593 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1595 /* Multiplies and extra load/stores. */
1596 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1597 /* Neither multiplies nor extension load/stores are allowed
1601 /* Otherwise, miscellaneous instructions. */
1603 /* BX <reg>, BXJ <reg>, BLX <reg> */
1604 if (bits (this_instr, 4, 27) == 0x12fff1
1605 || bits (this_instr, 4, 27) == 0x12fff2
1606 || bits (this_instr, 4, 27) == 0x12fff3)
1609 /* Other miscellaneous instructions are unpredictable if they
1613 /* Data processing instruction. Fall through. */
1616 if (bits (this_instr, 12, 15) == 15)
1623 /* Media instructions and architecturally undefined instructions. */
1624 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1628 if (bit (this_instr, 20) == 0)
1632 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1638 /* Load/store multiple. */
1639 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1645 /* Branch and branch with link. */
1650 /* Coprocessor transfers or SWIs can not affect PC. */
1654 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1658 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1659 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1660 fill it in. Return the first address not recognized as a prologue
1663 We recognize all the instructions typically found in ARM prologues,
1664 plus harmless instructions which can be skipped (either for analysis
1665 purposes, or a more restrictive set that can be skipped when finding
1666 the end of the prologue). */
1669 arm_analyze_prologue (struct gdbarch *gdbarch,
1670 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1671 struct arm_prologue_cache *cache)
1673 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1674 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1676 CORE_ADDR offset, current_pc;
1677 pv_t regs[ARM_FPS_REGNUM];
1678 struct pv_area *stack;
1679 struct cleanup *back_to;
1680 int framereg, framesize;
1681 CORE_ADDR unrecognized_pc = 0;
1683 /* Search the prologue looking for instructions that set up the
1684 frame pointer, adjust the stack pointer, and save registers.
1686 Be careful, however, and if it doesn't look like a prologue,
1687 don't try to scan it. If, for instance, a frameless function
1688 begins with stmfd sp!, then we will tell ourselves there is
1689 a frame, which will confuse stack traceback, as well as "finish"
1690 and other operations that rely on a knowledge of the stack
1693 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1694 regs[regno] = pv_register (regno, 0);
1695 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1696 back_to = make_cleanup_free_pv_area (stack);
1698 for (current_pc = prologue_start;
1699 current_pc < prologue_end;
1703 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1705 if (insn == 0xe1a0c00d) /* mov ip, sp */
1707 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1710 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1711 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1713 unsigned imm = insn & 0xff; /* immediate value */
1714 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1715 int rd = bits (insn, 12, 15);
1716 imm = (imm >> rot) | (imm << (32 - rot));
1717 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1720 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1721 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1723 unsigned imm = insn & 0xff; /* immediate value */
1724 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1725 int rd = bits (insn, 12, 15);
1726 imm = (imm >> rot) | (imm << (32 - rot));
1727 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1730 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1733 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1735 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1736 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1737 regs[bits (insn, 12, 15)]);
1740 else if ((insn & 0xffff0000) == 0xe92d0000)
1741 /* stmfd sp!, {..., fp, ip, lr, pc}
1743 stmfd sp!, {a1, a2, a3, a4} */
1745 int mask = insn & 0xffff;
1747 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1750 /* Calculate offsets of saved registers. */
1751 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1752 if (mask & (1 << regno))
1755 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1756 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1759 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1760 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1761 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1763 /* No need to add this to saved_regs -- it's just an arg reg. */
1766 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1767 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1768 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1770 /* No need to add this to saved_regs -- it's just an arg reg. */
1773 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1775 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1777 /* No need to add this to saved_regs -- it's just arg regs. */
1780 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1782 unsigned imm = insn & 0xff; /* immediate value */
1783 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1784 imm = (imm >> rot) | (imm << (32 - rot));
1785 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1787 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1789 unsigned imm = insn & 0xff; /* immediate value */
1790 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1791 imm = (imm >> rot) | (imm << (32 - rot));
1792 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1794 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1796 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1798 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1801 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1802 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1803 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1805 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1807 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1809 int n_saved_fp_regs;
1810 unsigned int fp_start_reg, fp_bound_reg;
1812 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1815 if ((insn & 0x800) == 0x800) /* N0 is set */
1817 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1818 n_saved_fp_regs = 3;
1820 n_saved_fp_regs = 1;
1824 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1825 n_saved_fp_regs = 2;
1827 n_saved_fp_regs = 4;
1830 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1831 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1832 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1834 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1835 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1836 regs[fp_start_reg++]);
1839 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1841 /* Allow some special function calls when skipping the
1842 prologue; GCC generates these before storing arguments to
1844 CORE_ADDR dest = BranchDest (current_pc, insn);
1846 if (skip_prologue_function (gdbarch, dest, 0))
1851 else if ((insn & 0xf0000000) != 0xe0000000)
1852 break; /* Condition not true, exit early. */
1853 else if (arm_instruction_changes_pc (insn))
1854 /* Don't scan past anything that might change control flow. */
1856 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1857 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1858 /* Ignore block loads from the stack, potentially copying
1859 parameters from memory. */
1861 else if ((insn & 0xfc500000) == 0xe4100000
1862 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1863 /* Similarly ignore single loads from the stack. */
1865 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1866 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1867 register instead of the stack. */
1871 /* The optimizer might shove anything into the prologue,
1872 so we just skip what we don't recognize. */
1873 unrecognized_pc = current_pc;
1878 if (unrecognized_pc == 0)
1879 unrecognized_pc = current_pc;
1881 /* The frame size is just the distance from the frame register
1882 to the original stack pointer. */
1883 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1885 /* Frame pointer is fp. */
1886 framereg = ARM_FP_REGNUM;
1887 framesize = -regs[ARM_FP_REGNUM].k;
1891 /* Try the stack pointer... this is a bit desperate. */
1892 framereg = ARM_SP_REGNUM;
1893 framesize = -regs[ARM_SP_REGNUM].k;
1898 cache->framereg = framereg;
1899 cache->framesize = framesize;
1901 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1902 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1903 cache->saved_regs[regno].addr = offset;
1907 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1908 paddress (gdbarch, unrecognized_pc));
1910 do_cleanups (back_to);
1911 return unrecognized_pc;
1915 arm_scan_prologue (struct frame_info *this_frame,
1916 struct arm_prologue_cache *cache)
1918 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1919 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1921 CORE_ADDR prologue_start, prologue_end, current_pc;
1922 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1923 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1924 pv_t regs[ARM_FPS_REGNUM];
1925 struct pv_area *stack;
1926 struct cleanup *back_to;
1929 /* Assume there is no frame until proven otherwise. */
1930 cache->framereg = ARM_SP_REGNUM;
1931 cache->framesize = 0;
1933 /* Check for Thumb prologue. */
1934 if (arm_frame_is_thumb (this_frame))
1936 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1940 /* Find the function prologue. If we can't find the function in
1941 the symbol table, peek in the stack frame to find the PC. */
1942 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1945 /* One way to find the end of the prologue (which works well
1946 for unoptimized code) is to do the following:
1948 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1951 prologue_end = prev_pc;
1952 else if (sal.end < prologue_end)
1953 prologue_end = sal.end;
1955 This mechanism is very accurate so long as the optimizer
1956 doesn't move any instructions from the function body into the
1957 prologue. If this happens, sal.end will be the last
1958 instruction in the first hunk of prologue code just before
1959 the first instruction that the scheduler has moved from
1960 the body to the prologue.
1962 In order to make sure that we scan all of the prologue
1963 instructions, we use a slightly less accurate mechanism which
1964 may scan more than necessary. To help compensate for this
1965 lack of accuracy, the prologue scanning loop below contains
1966 several clauses which'll cause the loop to terminate early if
1967 an implausible prologue instruction is encountered.
1973 is a suitable endpoint since it accounts for the largest
1974 possible prologue plus up to five instructions inserted by
1977 if (prologue_end > prologue_start + 64)
1979 prologue_end = prologue_start + 64; /* See above. */
1984 /* We have no symbol information. Our only option is to assume this
1985 function has a standard stack frame and the normal frame register.
1986 Then, we can find the value of our frame pointer on entrance to
1987 the callee (or at the present moment if this is the innermost frame).
1988 The value stored there should be the address of the stmfd + 8. */
1989 CORE_ADDR frame_loc;
1990 LONGEST return_value;
1992 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1993 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1997 prologue_start = gdbarch_addr_bits_remove
1998 (gdbarch, return_value) - 8;
1999 prologue_end = prologue_start + 64; /* See above. */
2003 if (prev_pc < prologue_end)
2004 prologue_end = prev_pc;
2006 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2009 static struct arm_prologue_cache *
2010 arm_make_prologue_cache (struct frame_info *this_frame)
2013 struct arm_prologue_cache *cache;
2014 CORE_ADDR unwound_fp;
2016 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2017 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2019 arm_scan_prologue (this_frame, cache);
2021 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2022 if (unwound_fp == 0)
2025 cache->prev_sp = unwound_fp + cache->framesize;
2027 /* Calculate actual addresses of saved registers using offsets
2028 determined by arm_scan_prologue. */
2029 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2030 if (trad_frame_addr_p (cache->saved_regs, reg))
2031 cache->saved_regs[reg].addr += cache->prev_sp;
2036 /* Our frame ID for a normal frame is the current function's starting PC
2037 and the caller's SP when we were called. */
2040 arm_prologue_this_id (struct frame_info *this_frame,
2042 struct frame_id *this_id)
2044 struct arm_prologue_cache *cache;
2048 if (*this_cache == NULL)
2049 *this_cache = arm_make_prologue_cache (this_frame);
2050 cache = *this_cache;
2052 /* This is meant to halt the backtrace at "_start". */
2053 pc = get_frame_pc (this_frame);
2054 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2057 /* If we've hit a wall, stop. */
2058 if (cache->prev_sp == 0)
2061 /* Use function start address as part of the frame ID. If we cannot
2062 identify the start address (due to missing symbol information),
2063 fall back to just using the current PC. */
2064 func = get_frame_func (this_frame);
2068 id = frame_id_build (cache->prev_sp, func);
2072 static struct value *
2073 arm_prologue_prev_register (struct frame_info *this_frame,
2077 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2078 struct arm_prologue_cache *cache;
2080 if (*this_cache == NULL)
2081 *this_cache = arm_make_prologue_cache (this_frame);
2082 cache = *this_cache;
2084 /* If we are asked to unwind the PC, then we need to return the LR
2085 instead. The prologue may save PC, but it will point into this
2086 frame's prologue, not the next frame's resume location. Also
2087 strip the saved T bit. A valid LR may have the low bit set, but
2088 a valid PC never does. */
2089 if (prev_regnum == ARM_PC_REGNUM)
2093 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2094 return frame_unwind_got_constant (this_frame, prev_regnum,
2095 arm_addr_bits_remove (gdbarch, lr));
2098 /* SP is generally not saved to the stack, but this frame is
2099 identified by the next frame's stack pointer at the time of the call.
2100 The value was already reconstructed into PREV_SP. */
2101 if (prev_regnum == ARM_SP_REGNUM)
2102 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2104 /* The CPSR may have been changed by the call instruction and by the
2105 called function. The only bit we can reconstruct is the T bit,
2106 by checking the low bit of LR as of the call. This is a reliable
2107 indicator of Thumb-ness except for some ARM v4T pre-interworking
2108 Thumb code, which could get away with a clear low bit as long as
2109 the called function did not use bx. Guess that all other
2110 bits are unchanged; the condition flags are presumably lost,
2111 but the processor status is likely valid. */
2112 if (prev_regnum == ARM_PS_REGNUM)
2115 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2117 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2118 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2119 if (IS_THUMB_ADDR (lr))
2123 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2126 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2130 struct frame_unwind arm_prologue_unwind = {
2132 default_frame_unwind_stop_reason,
2133 arm_prologue_this_id,
2134 arm_prologue_prev_register,
2136 default_frame_sniffer
2139 /* Maintain a list of ARM exception table entries per objfile, similar to the
2140 list of mapping symbols. We only cache entries for standard ARM-defined
2141 personality routines; the cache will contain only the frame unwinding
2142 instructions associated with the entry (not the descriptors). */
2144 static const struct objfile_data *arm_exidx_data_key;
2146 struct arm_exidx_entry
2151 typedef struct arm_exidx_entry arm_exidx_entry_s;
2152 DEF_VEC_O(arm_exidx_entry_s);
2154 struct arm_exidx_data
2156 VEC(arm_exidx_entry_s) **section_maps;
2160 arm_exidx_data_free (struct objfile *objfile, void *arg)
2162 struct arm_exidx_data *data = arg;
2165 for (i = 0; i < objfile->obfd->section_count; i++)
2166 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2170 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2171 const struct arm_exidx_entry *rhs)
2173 return lhs->addr < rhs->addr;
2176 static struct obj_section *
2177 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2179 struct obj_section *osect;
2181 ALL_OBJFILE_OSECTIONS (objfile, osect)
2182 if (bfd_get_section_flags (objfile->obfd,
2183 osect->the_bfd_section) & SEC_ALLOC)
2185 bfd_vma start, size;
2186 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2187 size = bfd_get_section_size (osect->the_bfd_section);
2189 if (start <= vma && vma < start + size)
2196 /* Parse contents of exception table and exception index sections
2197 of OBJFILE, and fill in the exception table entry cache.
2199 For each entry that refers to a standard ARM-defined personality
2200 routine, extract the frame unwinding instructions (from either
2201 the index or the table section). The unwinding instructions
2203 - extracting them from the rest of the table data
2204 - converting to host endianness
2205 - appending the implicit 0xb0 ("Finish") code
2207 The extracted and normalized instructions are stored for later
2208 retrieval by the arm_find_exidx_entry routine. */
2211 arm_exidx_new_objfile (struct objfile *objfile)
2213 struct cleanup *cleanups;
2214 struct arm_exidx_data *data;
2215 asection *exidx, *extab;
2216 bfd_vma exidx_vma = 0, extab_vma = 0;
2217 bfd_size_type exidx_size = 0, extab_size = 0;
2218 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2221 /* If we've already touched this file, do nothing. */
2222 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2224 cleanups = make_cleanup (null_cleanup, NULL);
2226 /* Read contents of exception table and index. */
2227 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2230 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2231 exidx_size = bfd_get_section_size (exidx);
2232 exidx_data = xmalloc (exidx_size);
2233 make_cleanup (xfree, exidx_data);
2235 if (!bfd_get_section_contents (objfile->obfd, exidx,
2236 exidx_data, 0, exidx_size))
2238 do_cleanups (cleanups);
2243 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2246 extab_vma = bfd_section_vma (objfile->obfd, extab);
2247 extab_size = bfd_get_section_size (extab);
2248 extab_data = xmalloc (extab_size);
2249 make_cleanup (xfree, extab_data);
2251 if (!bfd_get_section_contents (objfile->obfd, extab,
2252 extab_data, 0, extab_size))
2254 do_cleanups (cleanups);
2259 /* Allocate exception table data structure. */
2260 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2261 set_objfile_data (objfile, arm_exidx_data_key, data);
2262 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2263 objfile->obfd->section_count,
2264 VEC(arm_exidx_entry_s) *);
2266 /* Fill in exception table. */
2267 for (i = 0; i < exidx_size / 8; i++)
2269 struct arm_exidx_entry new_exidx_entry;
2270 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2271 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2272 bfd_vma addr = 0, word = 0;
2273 int n_bytes = 0, n_words = 0;
2274 struct obj_section *sec;
2275 gdb_byte *entry = NULL;
2277 /* Extract address of start of function. */
2278 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2279 idx += exidx_vma + i * 8;
2281 /* Find section containing function and compute section offset. */
2282 sec = arm_obj_section_from_vma (objfile, idx);
2285 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2287 /* Determine address of exception table entry. */
2290 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2292 else if ((val & 0xff000000) == 0x80000000)
2294 /* Exception table entry embedded in .ARM.exidx
2295 -- must be short form. */
2299 else if (!(val & 0x80000000))
2301 /* Exception table entry in .ARM.extab. */
2302 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2303 addr += exidx_vma + i * 8 + 4;
2305 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2307 word = bfd_h_get_32 (objfile->obfd,
2308 extab_data + addr - extab_vma);
2311 if ((word & 0xff000000) == 0x80000000)
2316 else if ((word & 0xff000000) == 0x81000000
2317 || (word & 0xff000000) == 0x82000000)
2321 n_words = ((word >> 16) & 0xff);
2323 else if (!(word & 0x80000000))
2326 struct obj_section *pers_sec;
2327 int gnu_personality = 0;
2329 /* Custom personality routine. */
2330 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2331 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2333 /* Check whether we've got one of the variants of the
2334 GNU personality routines. */
2335 pers_sec = arm_obj_section_from_vma (objfile, pers);
2338 static const char *personality[] =
2340 "__gcc_personality_v0",
2341 "__gxx_personality_v0",
2342 "__gcj_personality_v0",
2343 "__gnu_objc_personality_v0",
2347 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2350 for (k = 0; personality[k]; k++)
2351 if (lookup_minimal_symbol_by_pc_name
2352 (pc, personality[k], objfile))
2354 gnu_personality = 1;
2359 /* If so, the next word contains a word count in the high
2360 byte, followed by the same unwind instructions as the
2361 pre-defined forms. */
2363 && addr + 4 <= extab_vma + extab_size)
2365 word = bfd_h_get_32 (objfile->obfd,
2366 extab_data + addr - extab_vma);
2369 n_words = ((word >> 24) & 0xff);
2375 /* Sanity check address. */
2377 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2378 n_words = n_bytes = 0;
2380 /* The unwind instructions reside in WORD (only the N_BYTES least
2381 significant bytes are valid), followed by N_WORDS words in the
2382 extab section starting at ADDR. */
2383 if (n_bytes || n_words)
2385 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2386 n_bytes + n_words * 4 + 1);
2389 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2393 word = bfd_h_get_32 (objfile->obfd,
2394 extab_data + addr - extab_vma);
2397 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2398 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2399 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2400 *p++ = (gdb_byte) (word & 0xff);
2403 /* Implied "Finish" to terminate the list. */
2407 /* Push entry onto vector. They are guaranteed to always
2408 appear in order of increasing addresses. */
2409 new_exidx_entry.addr = idx;
2410 new_exidx_entry.entry = entry;
2411 VEC_safe_push (arm_exidx_entry_s,
2412 data->section_maps[sec->the_bfd_section->index],
2416 do_cleanups (cleanups);
2419 /* Search for the exception table entry covering MEMADDR. If one is found,
2420 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2421 set *START to the start of the region covered by this entry. */
2424 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2426 struct obj_section *sec;
2428 sec = find_pc_section (memaddr);
2431 struct arm_exidx_data *data;
2432 VEC(arm_exidx_entry_s) *map;
2433 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2436 data = objfile_data (sec->objfile, arm_exidx_data_key);
2439 map = data->section_maps[sec->the_bfd_section->index];
2440 if (!VEC_empty (arm_exidx_entry_s, map))
2442 struct arm_exidx_entry *map_sym;
2444 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2445 arm_compare_exidx_entries);
2447 /* VEC_lower_bound finds the earliest ordered insertion
2448 point. If the following symbol starts at this exact
2449 address, we use that; otherwise, the preceding
2450 exception table entry covers this address. */
2451 if (idx < VEC_length (arm_exidx_entry_s, map))
2453 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2454 if (map_sym->addr == map_key.addr)
2457 *start = map_sym->addr + obj_section_addr (sec);
2458 return map_sym->entry;
2464 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2466 *start = map_sym->addr + obj_section_addr (sec);
2467 return map_sym->entry;
2476 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2477 instruction list from the ARM exception table entry ENTRY, allocate and
2478 return a prologue cache structure describing how to unwind this frame.
2480 Return NULL if the unwinding instruction list contains a "spare",
2481 "reserved" or "refuse to unwind" instruction as defined in section
2482 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2483 for the ARM Architecture" document. */
2485 static struct arm_prologue_cache *
2486 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2491 struct arm_prologue_cache *cache;
2492 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2493 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2499 /* Whenever we reload SP, we actually have to retrieve its
2500 actual value in the current frame. */
2503 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2505 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2506 vsp = get_frame_register_unsigned (this_frame, reg);
2510 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2511 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2517 /* Decode next unwind instruction. */
2520 if ((insn & 0xc0) == 0)
2522 int offset = insn & 0x3f;
2523 vsp += (offset << 2) + 4;
2525 else if ((insn & 0xc0) == 0x40)
2527 int offset = insn & 0x3f;
2528 vsp -= (offset << 2) + 4;
2530 else if ((insn & 0xf0) == 0x80)
2532 int mask = ((insn & 0xf) << 8) | *entry++;
2535 /* The special case of an all-zero mask identifies
2536 "Refuse to unwind". We return NULL to fall back
2537 to the prologue analyzer. */
2541 /* Pop registers r4..r15 under mask. */
2542 for (i = 0; i < 12; i++)
2543 if (mask & (1 << i))
2545 cache->saved_regs[4 + i].addr = vsp;
2549 /* Special-case popping SP -- we need to reload vsp. */
2550 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2553 else if ((insn & 0xf0) == 0x90)
2555 int reg = insn & 0xf;
2557 /* Reserved cases. */
2558 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2561 /* Set SP from another register and mark VSP for reload. */
2562 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2565 else if ((insn & 0xf0) == 0xa0)
2567 int count = insn & 0x7;
2568 int pop_lr = (insn & 0x8) != 0;
2571 /* Pop r4..r[4+count]. */
2572 for (i = 0; i <= count; i++)
2574 cache->saved_regs[4 + i].addr = vsp;
2578 /* If indicated by flag, pop LR as well. */
2581 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2585 else if (insn == 0xb0)
2587 /* We could only have updated PC by popping into it; if so, it
2588 will show up as address. Otherwise, copy LR into PC. */
2589 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2590 cache->saved_regs[ARM_PC_REGNUM]
2591 = cache->saved_regs[ARM_LR_REGNUM];
2596 else if (insn == 0xb1)
2598 int mask = *entry++;
2601 /* All-zero mask and mask >= 16 is "spare". */
2602 if (mask == 0 || mask >= 16)
2605 /* Pop r0..r3 under mask. */
2606 for (i = 0; i < 4; i++)
2607 if (mask & (1 << i))
2609 cache->saved_regs[i].addr = vsp;
2613 else if (insn == 0xb2)
2615 ULONGEST offset = 0;
2620 offset |= (*entry & 0x7f) << shift;
2623 while (*entry++ & 0x80);
2625 vsp += 0x204 + (offset << 2);
2627 else if (insn == 0xb3)
2629 int start = *entry >> 4;
2630 int count = (*entry++) & 0xf;
2633 /* Only registers D0..D15 are valid here. */
2634 if (start + count >= 16)
2637 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2638 for (i = 0; i <= count; i++)
2640 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2644 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2647 else if ((insn & 0xf8) == 0xb8)
2649 int count = insn & 0x7;
2652 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2653 for (i = 0; i <= count; i++)
2655 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2659 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2662 else if (insn == 0xc6)
2664 int start = *entry >> 4;
2665 int count = (*entry++) & 0xf;
2668 /* Only registers WR0..WR15 are valid. */
2669 if (start + count >= 16)
2672 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2673 for (i = 0; i <= count; i++)
2675 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2679 else if (insn == 0xc7)
2681 int mask = *entry++;
2684 /* All-zero mask and mask >= 16 is "spare". */
2685 if (mask == 0 || mask >= 16)
2688 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2689 for (i = 0; i < 4; i++)
2690 if (mask & (1 << i))
2692 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2696 else if ((insn & 0xf8) == 0xc0)
2698 int count = insn & 0x7;
2701 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2702 for (i = 0; i <= count; i++)
2704 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2708 else if (insn == 0xc8)
2710 int start = *entry >> 4;
2711 int count = (*entry++) & 0xf;
2714 /* Only registers D0..D31 are valid. */
2715 if (start + count >= 16)
2718 /* Pop VFP double-precision registers
2719 D[16+start]..D[16+start+count]. */
2720 for (i = 0; i <= count; i++)
2722 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2726 else if (insn == 0xc9)
2728 int start = *entry >> 4;
2729 int count = (*entry++) & 0xf;
2732 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2733 for (i = 0; i <= count; i++)
2735 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2739 else if ((insn & 0xf8) == 0xd0)
2741 int count = insn & 0x7;
2744 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2745 for (i = 0; i <= count; i++)
2747 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2753 /* Everything else is "spare". */
2758 /* If we restore SP from a register, assume this was the frame register.
2759 Otherwise just fall back to SP as frame register. */
2760 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2761 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2763 cache->framereg = ARM_SP_REGNUM;
2765 /* Determine offset to previous frame. */
2767 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2769 /* We already got the previous SP. */
2770 cache->prev_sp = vsp;
2775 /* Unwinding via ARM exception table entries. Note that the sniffer
2776 already computes a filled-in prologue cache, which is then used
2777 with the same arm_prologue_this_id and arm_prologue_prev_register
2778 routines also used for prologue-parsing based unwinding. */
2781 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2782 struct frame_info *this_frame,
2783 void **this_prologue_cache)
2785 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2786 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2787 CORE_ADDR addr_in_block, exidx_region, func_start;
2788 struct arm_prologue_cache *cache;
2791 /* See if we have an ARM exception table entry covering this address. */
2792 addr_in_block = get_frame_address_in_block (this_frame);
2793 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2797 /* The ARM exception table does not describe unwind information
2798 for arbitrary PC values, but is guaranteed to be correct only
2799 at call sites. We have to decide here whether we want to use
2800 ARM exception table information for this frame, or fall back
2801 to using prologue parsing. (Note that if we have DWARF CFI,
2802 this sniffer isn't even called -- CFI is always preferred.)
2804 Before we make this decision, however, we check whether we
2805 actually have *symbol* information for the current frame.
2806 If not, prologue parsing would not work anyway, so we might
2807 as well use the exception table and hope for the best. */
2808 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2812 /* If the next frame is "normal", we are at a call site in this
2813 frame, so exception information is guaranteed to be valid. */
2814 if (get_next_frame (this_frame)
2815 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2818 /* We also assume exception information is valid if we're currently
2819 blocked in a system call. The system library is supposed to
2820 ensure this, so that e.g. pthread cancellation works. */
2821 if (arm_frame_is_thumb (this_frame))
2825 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2826 byte_order_for_code, &insn)
2827 && (insn & 0xff00) == 0xdf00 /* svc */)
2834 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2835 byte_order_for_code, &insn)
2836 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2840 /* Bail out if we don't know that exception information is valid. */
2844 /* The ARM exception index does not mark the *end* of the region
2845 covered by the entry, and some functions will not have any entry.
2846 To correctly recognize the end of the covered region, the linker
2847 should have inserted dummy records with a CANTUNWIND marker.
2849 Unfortunately, current versions of GNU ld do not reliably do
2850 this, and thus we may have found an incorrect entry above.
2851 As a (temporary) sanity check, we only use the entry if it
2852 lies *within* the bounds of the function. Note that this check
2853 might reject perfectly valid entries that just happen to cover
2854 multiple functions; therefore this check ought to be removed
2855 once the linker is fixed. */
2856 if (func_start > exidx_region)
2860 /* Decode the list of unwinding instructions into a prologue cache.
2861 Note that this may fail due to e.g. a "refuse to unwind" code. */
2862 cache = arm_exidx_fill_cache (this_frame, entry);
2866 *this_prologue_cache = cache;
2870 struct frame_unwind arm_exidx_unwind = {
2872 default_frame_unwind_stop_reason,
2873 arm_prologue_this_id,
2874 arm_prologue_prev_register,
2876 arm_exidx_unwind_sniffer
2879 static struct arm_prologue_cache *
2880 arm_make_stub_cache (struct frame_info *this_frame)
2882 struct arm_prologue_cache *cache;
2884 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2885 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2887 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2892 /* Our frame ID for a stub frame is the current SP and LR. */
2895 arm_stub_this_id (struct frame_info *this_frame,
2897 struct frame_id *this_id)
2899 struct arm_prologue_cache *cache;
2901 if (*this_cache == NULL)
2902 *this_cache = arm_make_stub_cache (this_frame);
2903 cache = *this_cache;
2905 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2909 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2910 struct frame_info *this_frame,
2911 void **this_prologue_cache)
2913 CORE_ADDR addr_in_block;
2916 addr_in_block = get_frame_address_in_block (this_frame);
2917 if (in_plt_section (addr_in_block, NULL)
2918 /* We also use the stub winder if the target memory is unreadable
2919 to avoid having the prologue unwinder trying to read it. */
2920 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2926 struct frame_unwind arm_stub_unwind = {
2928 default_frame_unwind_stop_reason,
2930 arm_prologue_prev_register,
2932 arm_stub_unwind_sniffer
2935 /* Put here the code to store, into CACHE->saved_regs, the addresses
2936 of the saved registers of frame described by THIS_FRAME. CACHE is
2939 static struct arm_prologue_cache *
2940 arm_m_exception_cache (struct frame_info *this_frame)
2942 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2943 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2944 struct arm_prologue_cache *cache;
2945 CORE_ADDR unwound_sp;
2948 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2949 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2951 unwound_sp = get_frame_register_unsigned (this_frame,
2954 /* The hardware saves eight 32-bit words, comprising xPSR,
2955 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2956 "B1.5.6 Exception entry behavior" in
2957 "ARMv7-M Architecture Reference Manual". */
2958 cache->saved_regs[0].addr = unwound_sp;
2959 cache->saved_regs[1].addr = unwound_sp + 4;
2960 cache->saved_regs[2].addr = unwound_sp + 8;
2961 cache->saved_regs[3].addr = unwound_sp + 12;
2962 cache->saved_regs[12].addr = unwound_sp + 16;
2963 cache->saved_regs[14].addr = unwound_sp + 20;
2964 cache->saved_regs[15].addr = unwound_sp + 24;
2965 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2967 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2968 aligner between the top of the 32-byte stack frame and the
2969 previous context's stack pointer. */
2970 cache->prev_sp = unwound_sp + 32;
2971 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2972 && (xpsr & (1 << 9)) != 0)
2973 cache->prev_sp += 4;
2978 /* Implementation of function hook 'this_id' in
2979 'struct frame_uwnind'. */
2982 arm_m_exception_this_id (struct frame_info *this_frame,
2984 struct frame_id *this_id)
2986 struct arm_prologue_cache *cache;
2988 if (*this_cache == NULL)
2989 *this_cache = arm_m_exception_cache (this_frame);
2990 cache = *this_cache;
2992 /* Our frame ID for a stub frame is the current SP and LR. */
2993 *this_id = frame_id_build (cache->prev_sp,
2994 get_frame_pc (this_frame));
2997 /* Implementation of function hook 'prev_register' in
2998 'struct frame_uwnind'. */
3000 static struct value *
3001 arm_m_exception_prev_register (struct frame_info *this_frame,
3005 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3006 struct arm_prologue_cache *cache;
3008 if (*this_cache == NULL)
3009 *this_cache = arm_m_exception_cache (this_frame);
3010 cache = *this_cache;
3012 /* The value was already reconstructed into PREV_SP. */
3013 if (prev_regnum == ARM_SP_REGNUM)
3014 return frame_unwind_got_constant (this_frame, prev_regnum,
3017 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3021 /* Implementation of function hook 'sniffer' in
3022 'struct frame_uwnind'. */
3025 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3026 struct frame_info *this_frame,
3027 void **this_prologue_cache)
3029 CORE_ADDR this_pc = get_frame_pc (this_frame);
3031 /* No need to check is_m; this sniffer is only registered for
3032 M-profile architectures. */
3034 /* Exception frames return to one of these magic PCs. Other values
3035 are not defined as of v7-M. See details in "B1.5.8 Exception
3036 return behavior" in "ARMv7-M Architecture Reference Manual". */
3037 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3038 || this_pc == 0xfffffffd)
3044 /* Frame unwinder for M-profile exceptions. */
3046 struct frame_unwind arm_m_exception_unwind =
3049 default_frame_unwind_stop_reason,
3050 arm_m_exception_this_id,
3051 arm_m_exception_prev_register,
3053 arm_m_exception_unwind_sniffer
3057 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3059 struct arm_prologue_cache *cache;
3061 if (*this_cache == NULL)
3062 *this_cache = arm_make_prologue_cache (this_frame);
3063 cache = *this_cache;
3065 return cache->prev_sp - cache->framesize;
3068 struct frame_base arm_normal_base = {
3069 &arm_prologue_unwind,
3070 arm_normal_frame_base,
3071 arm_normal_frame_base,
3072 arm_normal_frame_base
3075 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3076 dummy frame. The frame ID's base needs to match the TOS value
3077 saved by save_dummy_frame_tos() and returned from
3078 arm_push_dummy_call, and the PC needs to match the dummy frame's
3081 static struct frame_id
3082 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3084 return frame_id_build (get_frame_register_unsigned (this_frame,
3086 get_frame_pc (this_frame));
3089 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3090 be used to construct the previous frame's ID, after looking up the
3091 containing function). */
3094 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3097 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3098 return arm_addr_bits_remove (gdbarch, pc);
3102 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3104 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3107 static struct value *
3108 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3111 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3113 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3118 /* The PC is normally copied from the return column, which
3119 describes saves of LR. However, that version may have an
3120 extra bit set to indicate Thumb state. The bit is not
3122 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3123 return frame_unwind_got_constant (this_frame, regnum,
3124 arm_addr_bits_remove (gdbarch, lr));
3127 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3128 cpsr = get_frame_register_unsigned (this_frame, regnum);
3129 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3130 if (IS_THUMB_ADDR (lr))
3134 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3137 internal_error (__FILE__, __LINE__,
3138 _("Unexpected register %d"), regnum);
3143 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3144 struct dwarf2_frame_state_reg *reg,
3145 struct frame_info *this_frame)
3151 reg->how = DWARF2_FRAME_REG_FN;
3152 reg->loc.fn = arm_dwarf2_prev_register;
3155 reg->how = DWARF2_FRAME_REG_CFA;
3160 /* Return true if we are in the function's epilogue, i.e. after the
3161 instruction that destroyed the function's stack frame. */
3164 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3166 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3167 unsigned int insn, insn2;
3168 int found_return = 0, found_stack_adjust = 0;
3169 CORE_ADDR func_start, func_end;
3173 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3176 /* The epilogue is a sequence of instructions along the following lines:
3178 - add stack frame size to SP or FP
3179 - [if frame pointer used] restore SP from FP
3180 - restore registers from SP [may include PC]
3181 - a return-type instruction [if PC wasn't already restored]
3183 In a first pass, we scan forward from the current PC and verify the
3184 instructions we find as compatible with this sequence, ending in a
3187 However, this is not sufficient to distinguish indirect function calls
3188 within a function from indirect tail calls in the epilogue in some cases.
3189 Therefore, if we didn't already find any SP-changing instruction during
3190 forward scan, we add a backward scanning heuristic to ensure we actually
3191 are in the epilogue. */
3194 while (scan_pc < func_end && !found_return)
3196 if (target_read_memory (scan_pc, buf, 2))
3200 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3202 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3204 else if (insn == 0x46f7) /* mov pc, lr */
3206 else if (insn == 0x46bd) /* mov sp, r7 */
3207 found_stack_adjust = 1;
3208 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3209 found_stack_adjust = 1;
3210 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3212 found_stack_adjust = 1;
3213 if (insn & 0x0100) /* <registers> include PC. */
3216 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3218 if (target_read_memory (scan_pc, buf, 2))
3222 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3224 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3226 found_stack_adjust = 1;
3227 if (insn2 & 0x8000) /* <registers> include PC. */
3230 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3231 && (insn2 & 0x0fff) == 0x0b04)
3233 found_stack_adjust = 1;
3234 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3237 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3238 && (insn2 & 0x0e00) == 0x0a00)
3239 found_stack_adjust = 1;
3250 /* Since any instruction in the epilogue sequence, with the possible
3251 exception of return itself, updates the stack pointer, we need to
3252 scan backwards for at most one instruction. Try either a 16-bit or
3253 a 32-bit instruction. This is just a heuristic, so we do not worry
3254 too much about false positives. */
3256 if (!found_stack_adjust)
3258 if (pc - 4 < func_start)
3260 if (target_read_memory (pc - 4, buf, 4))
3263 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3264 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3266 if (insn2 == 0x46bd) /* mov sp, r7 */
3267 found_stack_adjust = 1;
3268 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3269 found_stack_adjust = 1;
3270 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3271 found_stack_adjust = 1;
3272 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3273 found_stack_adjust = 1;
3274 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3275 && (insn2 & 0x0fff) == 0x0b04)
3276 found_stack_adjust = 1;
3277 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3278 && (insn2 & 0x0e00) == 0x0a00)
3279 found_stack_adjust = 1;
3282 return found_stack_adjust;
3285 /* Return true if we are in the function's epilogue, i.e. after the
3286 instruction that destroyed the function's stack frame. */
3289 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3291 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3293 int found_return, found_stack_adjust;
3294 CORE_ADDR func_start, func_end;
3296 if (arm_pc_is_thumb (gdbarch, pc))
3297 return thumb_in_function_epilogue_p (gdbarch, pc);
3299 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3302 /* We are in the epilogue if the previous instruction was a stack
3303 adjustment and the next instruction is a possible return (bx, mov
3304 pc, or pop). We could have to scan backwards to find the stack
3305 adjustment, or forwards to find the return, but this is a decent
3306 approximation. First scan forwards. */
3309 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3310 if (bits (insn, 28, 31) != INST_NV)
3312 if ((insn & 0x0ffffff0) == 0x012fff10)
3315 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3318 else if ((insn & 0x0fff0000) == 0x08bd0000
3319 && (insn & 0x0000c000) != 0)
3320 /* POP (LDMIA), including PC or LR. */
3327 /* Scan backwards. This is just a heuristic, so do not worry about
3328 false positives from mode changes. */
3330 if (pc < func_start + 4)
3333 found_stack_adjust = 0;
3334 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3335 if (bits (insn, 28, 31) != INST_NV)
3337 if ((insn & 0x0df0f000) == 0x0080d000)
3338 /* ADD SP (register or immediate). */
3339 found_stack_adjust = 1;
3340 else if ((insn & 0x0df0f000) == 0x0040d000)
3341 /* SUB SP (register or immediate). */
3342 found_stack_adjust = 1;
3343 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3345 found_stack_adjust = 1;
3346 else if ((insn & 0x0fff0000) == 0x08bd0000)
3348 found_stack_adjust = 1;
3349 else if ((insn & 0x0fff0000) == 0x049d0000)
3350 /* POP of a single register. */
3351 found_stack_adjust = 1;
3354 if (found_stack_adjust)
3361 /* When arguments must be pushed onto the stack, they go on in reverse
3362 order. The code below implements a FILO (stack) to do this. */
3367 struct stack_item *prev;
3371 static struct stack_item *
3372 push_stack_item (struct stack_item *prev, const void *contents, int len)
3374 struct stack_item *si;
3375 si = xmalloc (sizeof (struct stack_item));
3376 si->data = xmalloc (len);
3379 memcpy (si->data, contents, len);
3383 static struct stack_item *
3384 pop_stack_item (struct stack_item *si)
3386 struct stack_item *dead = si;
3394 /* Return the alignment (in bytes) of the given type. */
3397 arm_type_align (struct type *t)
3403 t = check_typedef (t);
3404 switch (TYPE_CODE (t))
3407 /* Should never happen. */
3408 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3412 case TYPE_CODE_ENUM:
3416 case TYPE_CODE_RANGE:
3418 case TYPE_CODE_CHAR:
3419 case TYPE_CODE_BOOL:
3420 return TYPE_LENGTH (t);
3422 case TYPE_CODE_ARRAY:
3423 case TYPE_CODE_COMPLEX:
3424 /* TODO: What about vector types? */
3425 return arm_type_align (TYPE_TARGET_TYPE (t));
3427 case TYPE_CODE_STRUCT:
3428 case TYPE_CODE_UNION:
3430 for (n = 0; n < TYPE_NFIELDS (t); n++)
3432 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3440 /* Possible base types for a candidate for passing and returning in
3443 enum arm_vfp_cprc_base_type
3452 /* The length of one element of base type B. */
3455 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3459 case VFP_CPRC_SINGLE:
3461 case VFP_CPRC_DOUBLE:
3463 case VFP_CPRC_VEC64:
3465 case VFP_CPRC_VEC128:
3468 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3473 /* The character ('s', 'd' or 'q') for the type of VFP register used
3474 for passing base type B. */
3477 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3481 case VFP_CPRC_SINGLE:
3483 case VFP_CPRC_DOUBLE:
3485 case VFP_CPRC_VEC64:
3487 case VFP_CPRC_VEC128:
3490 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3495 /* Determine whether T may be part of a candidate for passing and
3496 returning in VFP registers, ignoring the limit on the total number
3497 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3498 classification of the first valid component found; if it is not
3499 VFP_CPRC_UNKNOWN, all components must have the same classification
3500 as *BASE_TYPE. If it is found that T contains a type not permitted
3501 for passing and returning in VFP registers, a type differently
3502 classified from *BASE_TYPE, or two types differently classified
3503 from each other, return -1, otherwise return the total number of
3504 base-type elements found (possibly 0 in an empty structure or
3505 array). Vectors and complex types are not currently supported,
3506 matching the generic AAPCS support. */
3509 arm_vfp_cprc_sub_candidate (struct type *t,
3510 enum arm_vfp_cprc_base_type *base_type)
3512 t = check_typedef (t);
3513 switch (TYPE_CODE (t))
3516 switch (TYPE_LENGTH (t))
3519 if (*base_type == VFP_CPRC_UNKNOWN)
3520 *base_type = VFP_CPRC_SINGLE;
3521 else if (*base_type != VFP_CPRC_SINGLE)
3526 if (*base_type == VFP_CPRC_UNKNOWN)
3527 *base_type = VFP_CPRC_DOUBLE;
3528 else if (*base_type != VFP_CPRC_DOUBLE)
3537 case TYPE_CODE_ARRAY:
3541 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3544 if (TYPE_LENGTH (t) == 0)
3546 gdb_assert (count == 0);
3549 else if (count == 0)
3551 unitlen = arm_vfp_cprc_unit_length (*base_type);
3552 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3553 return TYPE_LENGTH (t) / unitlen;
3557 case TYPE_CODE_STRUCT:
3562 for (i = 0; i < TYPE_NFIELDS (t); i++)
3564 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3566 if (sub_count == -1)
3570 if (TYPE_LENGTH (t) == 0)
3572 gdb_assert (count == 0);
3575 else if (count == 0)
3577 unitlen = arm_vfp_cprc_unit_length (*base_type);
3578 if (TYPE_LENGTH (t) != unitlen * count)
3583 case TYPE_CODE_UNION:
3588 for (i = 0; i < TYPE_NFIELDS (t); i++)
3590 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3592 if (sub_count == -1)
3594 count = (count > sub_count ? count : sub_count);
3596 if (TYPE_LENGTH (t) == 0)
3598 gdb_assert (count == 0);
3601 else if (count == 0)
3603 unitlen = arm_vfp_cprc_unit_length (*base_type);
3604 if (TYPE_LENGTH (t) != unitlen * count)
3616 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3617 if passed to or returned from a non-variadic function with the VFP
3618 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3619 *BASE_TYPE to the base type for T and *COUNT to the number of
3620 elements of that base type before returning. */
3623 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3626 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3627 int c = arm_vfp_cprc_sub_candidate (t, &b);
3628 if (c <= 0 || c > 4)
3635 /* Return 1 if the VFP ABI should be used for passing arguments to and
3636 returning values from a function of type FUNC_TYPE, 0
3640 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3642 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3643 /* Variadic functions always use the base ABI. Assume that functions
3644 without debug info are not variadic. */
3645 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3647 /* The VFP ABI is only supported as a variant of AAPCS. */
3648 if (tdep->arm_abi != ARM_ABI_AAPCS)
3650 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3653 /* We currently only support passing parameters in integer registers, which
3654 conforms with GCC's default model, and VFP argument passing following
3655 the VFP variant of AAPCS. Several other variants exist and
3656 we should probably support some of them based on the selected ABI. */
3659 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3660 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3661 struct value **args, CORE_ADDR sp, int struct_return,
3662 CORE_ADDR struct_addr)
3664 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3668 struct stack_item *si = NULL;
3671 unsigned vfp_regs_free = (1 << 16) - 1;
3673 /* Determine the type of this function and whether the VFP ABI
3675 ftype = check_typedef (value_type (function));
3676 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3677 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3678 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3680 /* Set the return address. For the ARM, the return breakpoint is
3681 always at BP_ADDR. */
3682 if (arm_pc_is_thumb (gdbarch, bp_addr))
3684 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3686 /* Walk through the list of args and determine how large a temporary
3687 stack is required. Need to take care here as structs may be
3688 passed on the stack, and we have to push them. */
3691 argreg = ARM_A1_REGNUM;
3694 /* The struct_return pointer occupies the first parameter
3695 passing register. */
3699 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3700 gdbarch_register_name (gdbarch, argreg),
3701 paddress (gdbarch, struct_addr));
3702 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3706 for (argnum = 0; argnum < nargs; argnum++)
3709 struct type *arg_type;
3710 struct type *target_type;
3711 enum type_code typecode;
3712 const bfd_byte *val;
3714 enum arm_vfp_cprc_base_type vfp_base_type;
3716 int may_use_core_reg = 1;
3718 arg_type = check_typedef (value_type (args[argnum]));
3719 len = TYPE_LENGTH (arg_type);
3720 target_type = TYPE_TARGET_TYPE (arg_type);
3721 typecode = TYPE_CODE (arg_type);
3722 val = value_contents (args[argnum]);
3724 align = arm_type_align (arg_type);
3725 /* Round alignment up to a whole number of words. */
3726 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3727 /* Different ABIs have different maximum alignments. */
3728 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3730 /* The APCS ABI only requires word alignment. */
3731 align = INT_REGISTER_SIZE;
3735 /* The AAPCS requires at most doubleword alignment. */
3736 if (align > INT_REGISTER_SIZE * 2)
3737 align = INT_REGISTER_SIZE * 2;
3741 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3749 /* Because this is a CPRC it cannot go in a core register or
3750 cause a core register to be skipped for alignment.
3751 Either it goes in VFP registers and the rest of this loop
3752 iteration is skipped for this argument, or it goes on the
3753 stack (and the stack alignment code is correct for this
3755 may_use_core_reg = 0;
3757 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3758 shift = unit_length / 4;
3759 mask = (1 << (shift * vfp_base_count)) - 1;
3760 for (regno = 0; regno < 16; regno += shift)
3761 if (((vfp_regs_free >> regno) & mask) == mask)
3770 vfp_regs_free &= ~(mask << regno);
3771 reg_scaled = regno / shift;
3772 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3773 for (i = 0; i < vfp_base_count; i++)
3777 if (reg_char == 'q')
3778 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3779 val + i * unit_length);
3782 sprintf (name_buf, "%c%d", reg_char, reg_scaled + i);
3783 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3785 regcache_cooked_write (regcache, regnum,
3786 val + i * unit_length);
3793 /* This CPRC could not go in VFP registers, so all VFP
3794 registers are now marked as used. */
3799 /* Push stack padding for dowubleword alignment. */
3800 if (nstack & (align - 1))
3802 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3803 nstack += INT_REGISTER_SIZE;
3806 /* Doubleword aligned quantities must go in even register pairs. */
3807 if (may_use_core_reg
3808 && argreg <= ARM_LAST_ARG_REGNUM
3809 && align > INT_REGISTER_SIZE
3813 /* If the argument is a pointer to a function, and it is a
3814 Thumb function, create a LOCAL copy of the value and set
3815 the THUMB bit in it. */
3816 if (TYPE_CODE_PTR == typecode
3817 && target_type != NULL
3818 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3820 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3821 if (arm_pc_is_thumb (gdbarch, regval))
3823 bfd_byte *copy = alloca (len);
3824 store_unsigned_integer (copy, len, byte_order,
3825 MAKE_THUMB_ADDR (regval));
3830 /* Copy the argument to general registers or the stack in
3831 register-sized pieces. Large arguments are split between
3832 registers and stack. */
3835 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3837 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3839 /* The argument is being passed in a general purpose
3842 = extract_unsigned_integer (val, partial_len, byte_order);
3843 if (byte_order == BFD_ENDIAN_BIG)
3844 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3846 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3848 gdbarch_register_name
3850 phex (regval, INT_REGISTER_SIZE));
3851 regcache_cooked_write_unsigned (regcache, argreg, regval);
3856 /* Push the arguments onto the stack. */
3858 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3860 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3861 nstack += INT_REGISTER_SIZE;
3868 /* If we have an odd number of words to push, then decrement the stack
3869 by one word now, so first stack argument will be dword aligned. */
3876 write_memory (sp, si->data, si->len);
3877 si = pop_stack_item (si);
3880 /* Finally, update teh SP register. */
3881 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3887 /* Always align the frame to an 8-byte boundary. This is required on
3888 some platforms and harmless on the rest. */
3891 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3893 /* Align the stack to eight bytes. */
3894 return sp & ~ (CORE_ADDR) 7;
3898 print_fpu_flags (int flags)
3900 if (flags & (1 << 0))
3901 fputs ("IVO ", stdout);
3902 if (flags & (1 << 1))
3903 fputs ("DVZ ", stdout);
3904 if (flags & (1 << 2))
3905 fputs ("OFL ", stdout);
3906 if (flags & (1 << 3))
3907 fputs ("UFL ", stdout);
3908 if (flags & (1 << 4))
3909 fputs ("INX ", stdout);
3913 /* Print interesting information about the floating point processor
3914 (if present) or emulator. */
3916 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3917 struct frame_info *frame, const char *args)
3919 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3922 type = (status >> 24) & 127;
3923 if (status & (1 << 31))
3924 printf (_("Hardware FPU type %d\n"), type);
3926 printf (_("Software FPU type %d\n"), type);
3927 /* i18n: [floating point unit] mask */
3928 fputs (_("mask: "), stdout);
3929 print_fpu_flags (status >> 16);
3930 /* i18n: [floating point unit] flags */
3931 fputs (_("flags: "), stdout);
3932 print_fpu_flags (status);
3935 /* Construct the ARM extended floating point type. */
3936 static struct type *
3937 arm_ext_type (struct gdbarch *gdbarch)
3939 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3941 if (!tdep->arm_ext_type)
3943 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3944 floatformats_arm_ext);
3946 return tdep->arm_ext_type;
3949 static struct type *
3950 arm_neon_double_type (struct gdbarch *gdbarch)
3952 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3954 if (tdep->neon_double_type == NULL)
3956 struct type *t, *elem;
3958 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3960 elem = builtin_type (gdbarch)->builtin_uint8;
3961 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3962 elem = builtin_type (gdbarch)->builtin_uint16;
3963 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3964 elem = builtin_type (gdbarch)->builtin_uint32;
3965 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3966 elem = builtin_type (gdbarch)->builtin_uint64;
3967 append_composite_type_field (t, "u64", elem);
3968 elem = builtin_type (gdbarch)->builtin_float;
3969 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3970 elem = builtin_type (gdbarch)->builtin_double;
3971 append_composite_type_field (t, "f64", elem);
3973 TYPE_VECTOR (t) = 1;
3974 TYPE_NAME (t) = "neon_d";
3975 tdep->neon_double_type = t;
3978 return tdep->neon_double_type;
3981 /* FIXME: The vector types are not correctly ordered on big-endian
3982 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3983 bits of d0 - regardless of what unit size is being held in d0. So
3984 the offset of the first uint8 in d0 is 7, but the offset of the
3985 first float is 4. This code works as-is for little-endian
3988 static struct type *
3989 arm_neon_quad_type (struct gdbarch *gdbarch)
3991 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3993 if (tdep->neon_quad_type == NULL)
3995 struct type *t, *elem;
3997 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3999 elem = builtin_type (gdbarch)->builtin_uint8;
4000 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4001 elem = builtin_type (gdbarch)->builtin_uint16;
4002 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4003 elem = builtin_type (gdbarch)->builtin_uint32;
4004 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4005 elem = builtin_type (gdbarch)->builtin_uint64;
4006 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4007 elem = builtin_type (gdbarch)->builtin_float;
4008 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4009 elem = builtin_type (gdbarch)->builtin_double;
4010 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4012 TYPE_VECTOR (t) = 1;
4013 TYPE_NAME (t) = "neon_q";
4014 tdep->neon_quad_type = t;
4017 return tdep->neon_quad_type;
4020 /* Return the GDB type object for the "standard" data type of data in
4023 static struct type *
4024 arm_register_type (struct gdbarch *gdbarch, int regnum)
4026 int num_regs = gdbarch_num_regs (gdbarch);
4028 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4029 && regnum >= num_regs && regnum < num_regs + 32)
4030 return builtin_type (gdbarch)->builtin_float;
4032 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4033 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4034 return arm_neon_quad_type (gdbarch);
4036 /* If the target description has register information, we are only
4037 in this function so that we can override the types of
4038 double-precision registers for NEON. */
4039 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4041 struct type *t = tdesc_register_type (gdbarch, regnum);
4043 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4044 && TYPE_CODE (t) == TYPE_CODE_FLT
4045 && gdbarch_tdep (gdbarch)->have_neon)
4046 return arm_neon_double_type (gdbarch);
4051 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4053 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4054 return builtin_type (gdbarch)->builtin_void;
4056 return arm_ext_type (gdbarch);
4058 else if (regnum == ARM_SP_REGNUM)
4059 return builtin_type (gdbarch)->builtin_data_ptr;
4060 else if (regnum == ARM_PC_REGNUM)
4061 return builtin_type (gdbarch)->builtin_func_ptr;
4062 else if (regnum >= ARRAY_SIZE (arm_register_names))
4063 /* These registers are only supported on targets which supply
4064 an XML description. */
4065 return builtin_type (gdbarch)->builtin_int0;
4067 return builtin_type (gdbarch)->builtin_uint32;
4070 /* Map a DWARF register REGNUM onto the appropriate GDB register
4074 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4076 /* Core integer regs. */
4077 if (reg >= 0 && reg <= 15)
4080 /* Legacy FPA encoding. These were once used in a way which
4081 overlapped with VFP register numbering, so their use is
4082 discouraged, but GDB doesn't support the ARM toolchain
4083 which used them for VFP. */
4084 if (reg >= 16 && reg <= 23)
4085 return ARM_F0_REGNUM + reg - 16;
4087 /* New assignments for the FPA registers. */
4088 if (reg >= 96 && reg <= 103)
4089 return ARM_F0_REGNUM + reg - 96;
4091 /* WMMX register assignments. */
4092 if (reg >= 104 && reg <= 111)
4093 return ARM_WCGR0_REGNUM + reg - 104;
4095 if (reg >= 112 && reg <= 127)
4096 return ARM_WR0_REGNUM + reg - 112;
4098 if (reg >= 192 && reg <= 199)
4099 return ARM_WC0_REGNUM + reg - 192;
4101 /* VFP v2 registers. A double precision value is actually
4102 in d1 rather than s2, but the ABI only defines numbering
4103 for the single precision registers. This will "just work"
4104 in GDB for little endian targets (we'll read eight bytes,
4105 starting in s0 and then progressing to s1), but will be
4106 reversed on big endian targets with VFP. This won't
4107 be a problem for the new Neon quad registers; you're supposed
4108 to use DW_OP_piece for those. */
4109 if (reg >= 64 && reg <= 95)
4113 sprintf (name_buf, "s%d", reg - 64);
4114 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4118 /* VFP v3 / Neon registers. This range is also used for VFP v2
4119 registers, except that it now describes d0 instead of s0. */
4120 if (reg >= 256 && reg <= 287)
4124 sprintf (name_buf, "d%d", reg - 256);
4125 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4132 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4134 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4137 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4139 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4140 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4142 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4143 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4145 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4146 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4148 if (reg < NUM_GREGS)
4149 return SIM_ARM_R0_REGNUM + reg;
4152 if (reg < NUM_FREGS)
4153 return SIM_ARM_FP0_REGNUM + reg;
4156 if (reg < NUM_SREGS)
4157 return SIM_ARM_FPS_REGNUM + reg;
4160 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4163 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4164 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4165 It is thought that this is is the floating-point register format on
4166 little-endian systems. */
4169 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4170 void *dbl, int endianess)
4174 if (endianess == BFD_ENDIAN_BIG)
4175 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4177 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4179 floatformat_from_doublest (fmt, &d, dbl);
4183 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4188 floatformat_to_doublest (fmt, ptr, &d);
4189 if (endianess == BFD_ENDIAN_BIG)
4190 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4192 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4197 condition_true (unsigned long cond, unsigned long status_reg)
4199 if (cond == INST_AL || cond == INST_NV)
4205 return ((status_reg & FLAG_Z) != 0);
4207 return ((status_reg & FLAG_Z) == 0);
4209 return ((status_reg & FLAG_C) != 0);
4211 return ((status_reg & FLAG_C) == 0);
4213 return ((status_reg & FLAG_N) != 0);
4215 return ((status_reg & FLAG_N) == 0);
4217 return ((status_reg & FLAG_V) != 0);
4219 return ((status_reg & FLAG_V) == 0);
4221 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4223 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4225 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4227 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4229 return (((status_reg & FLAG_Z) == 0)
4230 && (((status_reg & FLAG_N) == 0)
4231 == ((status_reg & FLAG_V) == 0)));
4233 return (((status_reg & FLAG_Z) != 0)
4234 || (((status_reg & FLAG_N) == 0)
4235 != ((status_reg & FLAG_V) == 0)));
4240 static unsigned long
4241 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4242 unsigned long pc_val, unsigned long status_reg)
4244 unsigned long res, shift;
4245 int rm = bits (inst, 0, 3);
4246 unsigned long shifttype = bits (inst, 5, 6);
4250 int rs = bits (inst, 8, 11);
4251 shift = (rs == 15 ? pc_val + 8
4252 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4255 shift = bits (inst, 7, 11);
4257 res = (rm == ARM_PC_REGNUM
4258 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4259 : get_frame_register_unsigned (frame, rm));
4264 res = shift >= 32 ? 0 : res << shift;
4268 res = shift >= 32 ? 0 : res >> shift;
4274 res = ((res & 0x80000000L)
4275 ? ~((~res) >> shift) : res >> shift);
4278 case 3: /* ROR/RRX */
4281 res = (res >> 1) | (carry ? 0x80000000L : 0);
4283 res = (res >> shift) | (res << (32 - shift));
4287 return res & 0xffffffff;
4290 /* Return number of 1-bits in VAL. */
4293 bitcount (unsigned long val)
4296 for (nbits = 0; val != 0; nbits++)
4297 val &= val - 1; /* Delete rightmost 1-bit in val. */
4301 /* Return the size in bytes of the complete Thumb instruction whose
4302 first halfword is INST1. */
4305 thumb_insn_size (unsigned short inst1)
4307 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4314 thumb_advance_itstate (unsigned int itstate)
4316 /* Preserve IT[7:5], the first three bits of the condition. Shift
4317 the upcoming condition flags left by one bit. */
4318 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4320 /* If we have finished the IT block, clear the state. */
4321 if ((itstate & 0x0f) == 0)
4327 /* Find the next PC after the current instruction executes. In some
4328 cases we can not statically determine the answer (see the IT state
4329 handling in this function); in that case, a breakpoint may be
4330 inserted in addition to the returned PC, which will be used to set
4331 another breakpoint by our caller. */
4334 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4336 struct gdbarch *gdbarch = get_frame_arch (frame);
4337 struct address_space *aspace = get_frame_address_space (frame);
4338 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4339 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4340 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4341 unsigned short inst1;
4342 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4343 unsigned long offset;
4344 ULONGEST status, itstate;
4346 nextpc = MAKE_THUMB_ADDR (nextpc);
4347 pc_val = MAKE_THUMB_ADDR (pc_val);
4349 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4351 /* Thumb-2 conditional execution support. There are eight bits in
4352 the CPSR which describe conditional execution state. Once
4353 reconstructed (they're in a funny order), the low five bits
4354 describe the low bit of the condition for each instruction and
4355 how many instructions remain. The high three bits describe the
4356 base condition. One of the low four bits will be set if an IT
4357 block is active. These bits read as zero on earlier
4359 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4360 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4362 /* If-Then handling. On GNU/Linux, where this routine is used, we
4363 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4364 can disable execution of the undefined instruction. So we might
4365 miss the breakpoint if we set it on a skipped conditional
4366 instruction. Because conditional instructions can change the
4367 flags, affecting the execution of further instructions, we may
4368 need to set two breakpoints. */
4370 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4372 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4374 /* An IT instruction. Because this instruction does not
4375 modify the flags, we can accurately predict the next
4376 executed instruction. */
4377 itstate = inst1 & 0x00ff;
4378 pc += thumb_insn_size (inst1);
4380 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4382 inst1 = read_memory_unsigned_integer (pc, 2,
4383 byte_order_for_code);
4384 pc += thumb_insn_size (inst1);
4385 itstate = thumb_advance_itstate (itstate);
4388 return MAKE_THUMB_ADDR (pc);
4390 else if (itstate != 0)
4392 /* We are in a conditional block. Check the condition. */
4393 if (! condition_true (itstate >> 4, status))
4395 /* Advance to the next executed instruction. */
4396 pc += thumb_insn_size (inst1);
4397 itstate = thumb_advance_itstate (itstate);
4399 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4401 inst1 = read_memory_unsigned_integer (pc, 2,
4402 byte_order_for_code);
4403 pc += thumb_insn_size (inst1);
4404 itstate = thumb_advance_itstate (itstate);
4407 return MAKE_THUMB_ADDR (pc);
4409 else if ((itstate & 0x0f) == 0x08)
4411 /* This is the last instruction of the conditional
4412 block, and it is executed. We can handle it normally
4413 because the following instruction is not conditional,
4414 and we must handle it normally because it is
4415 permitted to branch. Fall through. */
4421 /* There are conditional instructions after this one.
4422 If this instruction modifies the flags, then we can
4423 not predict what the next executed instruction will
4424 be. Fortunately, this instruction is architecturally
4425 forbidden to branch; we know it will fall through.
4426 Start by skipping past it. */
4427 pc += thumb_insn_size (inst1);
4428 itstate = thumb_advance_itstate (itstate);
4430 /* Set a breakpoint on the following instruction. */
4431 gdb_assert ((itstate & 0x0f) != 0);
4432 arm_insert_single_step_breakpoint (gdbarch, aspace,
4433 MAKE_THUMB_ADDR (pc));
4434 cond_negated = (itstate >> 4) & 1;
4436 /* Skip all following instructions with the same
4437 condition. If there is a later instruction in the IT
4438 block with the opposite condition, set the other
4439 breakpoint there. If not, then set a breakpoint on
4440 the instruction after the IT block. */
4443 inst1 = read_memory_unsigned_integer (pc, 2,
4444 byte_order_for_code);
4445 pc += thumb_insn_size (inst1);
4446 itstate = thumb_advance_itstate (itstate);
4448 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4450 return MAKE_THUMB_ADDR (pc);
4454 else if (itstate & 0x0f)
4456 /* We are in a conditional block. Check the condition. */
4457 int cond = itstate >> 4;
4459 if (! condition_true (cond, status))
4460 /* Advance to the next instruction. All the 32-bit
4461 instructions share a common prefix. */
4462 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4464 /* Otherwise, handle the instruction normally. */
4467 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4471 /* Fetch the saved PC from the stack. It's stored above
4472 all of the other registers. */
4473 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4474 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4475 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4477 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4479 unsigned long cond = bits (inst1, 8, 11);
4480 if (cond == 0x0f) /* 0x0f = SWI */
4482 struct gdbarch_tdep *tdep;
4483 tdep = gdbarch_tdep (gdbarch);
4485 if (tdep->syscall_next_pc != NULL)
4486 nextpc = tdep->syscall_next_pc (frame);
4489 else if (cond != 0x0f && condition_true (cond, status))
4490 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4492 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4494 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4496 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4498 unsigned short inst2;
4499 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4501 /* Default to the next instruction. */
4503 nextpc = MAKE_THUMB_ADDR (nextpc);
4505 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4507 /* Branches and miscellaneous control instructions. */
4509 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4512 int j1, j2, imm1, imm2;
4514 imm1 = sbits (inst1, 0, 10);
4515 imm2 = bits (inst2, 0, 10);
4516 j1 = bit (inst2, 13);
4517 j2 = bit (inst2, 11);
4519 offset = ((imm1 << 12) + (imm2 << 1));
4520 offset ^= ((!j2) << 22) | ((!j1) << 23);
4522 nextpc = pc_val + offset;
4523 /* For BLX make sure to clear the low bits. */
4524 if (bit (inst2, 12) == 0)
4525 nextpc = nextpc & 0xfffffffc;
4527 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4529 /* SUBS PC, LR, #imm8. */
4530 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4531 nextpc -= inst2 & 0x00ff;
4533 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4535 /* Conditional branch. */
4536 if (condition_true (bits (inst1, 6, 9), status))
4538 int sign, j1, j2, imm1, imm2;
4540 sign = sbits (inst1, 10, 10);
4541 imm1 = bits (inst1, 0, 5);
4542 imm2 = bits (inst2, 0, 10);
4543 j1 = bit (inst2, 13);
4544 j2 = bit (inst2, 11);
4546 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4547 offset += (imm1 << 12) + (imm2 << 1);
4549 nextpc = pc_val + offset;
4553 else if ((inst1 & 0xfe50) == 0xe810)
4555 /* Load multiple or RFE. */
4556 int rn, offset, load_pc = 1;
4558 rn = bits (inst1, 0, 3);
4559 if (bit (inst1, 7) && !bit (inst1, 8))
4562 if (!bit (inst2, 15))
4564 offset = bitcount (inst2) * 4 - 4;
4566 else if (!bit (inst1, 7) && bit (inst1, 8))
4569 if (!bit (inst2, 15))
4573 else if (bit (inst1, 7) && bit (inst1, 8))
4578 else if (!bit (inst1, 7) && !bit (inst1, 8))
4588 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4589 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4592 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4594 /* MOV PC or MOVS PC. */
4595 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4596 nextpc = MAKE_THUMB_ADDR (nextpc);
4598 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4602 int rn, load_pc = 1;
4604 rn = bits (inst1, 0, 3);
4605 base = get_frame_register_unsigned (frame, rn);
4606 if (rn == ARM_PC_REGNUM)
4608 base = (base + 4) & ~(CORE_ADDR) 0x3;
4610 base += bits (inst2, 0, 11);
4612 base -= bits (inst2, 0, 11);
4614 else if (bit (inst1, 7))
4615 base += bits (inst2, 0, 11);
4616 else if (bit (inst2, 11))
4618 if (bit (inst2, 10))
4621 base += bits (inst2, 0, 7);
4623 base -= bits (inst2, 0, 7);
4626 else if ((inst2 & 0x0fc0) == 0x0000)
4628 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4629 base += get_frame_register_unsigned (frame, rm) << shift;
4636 nextpc = get_frame_memory_unsigned (frame, base, 4);
4638 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4641 CORE_ADDR tbl_reg, table, offset, length;
4643 tbl_reg = bits (inst1, 0, 3);
4644 if (tbl_reg == 0x0f)
4645 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4647 table = get_frame_register_unsigned (frame, tbl_reg);
4649 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4650 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4651 nextpc = pc_val + length;
4653 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4656 CORE_ADDR tbl_reg, table, offset, length;
4658 tbl_reg = bits (inst1, 0, 3);
4659 if (tbl_reg == 0x0f)
4660 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4662 table = get_frame_register_unsigned (frame, tbl_reg);
4664 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4665 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4666 nextpc = pc_val + length;
4669 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4671 if (bits (inst1, 3, 6) == 0x0f)
4672 nextpc = UNMAKE_THUMB_ADDR (pc_val);
4674 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4676 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4678 if (bits (inst1, 3, 6) == 0x0f)
4681 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4683 nextpc = MAKE_THUMB_ADDR (nextpc);
4685 else if ((inst1 & 0xf500) == 0xb100)
4688 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4689 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4691 if (bit (inst1, 11) && reg != 0)
4692 nextpc = pc_val + imm;
4693 else if (!bit (inst1, 11) && reg == 0)
4694 nextpc = pc_val + imm;
4699 /* Get the raw next address. PC is the current program counter, in
4700 FRAME, which is assumed to be executing in ARM mode.
4702 The value returned has the execution state of the next instruction
4703 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4704 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4708 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4710 struct gdbarch *gdbarch = get_frame_arch (frame);
4711 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4712 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4713 unsigned long pc_val;
4714 unsigned long this_instr;
4715 unsigned long status;
4718 pc_val = (unsigned long) pc;
4719 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4721 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4722 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4724 if (bits (this_instr, 28, 31) == INST_NV)
4725 switch (bits (this_instr, 24, 27))
4730 /* Branch with Link and change to Thumb. */
4731 nextpc = BranchDest (pc, this_instr);
4732 nextpc |= bit (this_instr, 24) << 1;
4733 nextpc = MAKE_THUMB_ADDR (nextpc);
4739 /* Coprocessor register transfer. */
4740 if (bits (this_instr, 12, 15) == 15)
4741 error (_("Invalid update to pc in instruction"));
4744 else if (condition_true (bits (this_instr, 28, 31), status))
4746 switch (bits (this_instr, 24, 27))
4749 case 0x1: /* data processing */
4753 unsigned long operand1, operand2, result = 0;
4757 if (bits (this_instr, 12, 15) != 15)
4760 if (bits (this_instr, 22, 25) == 0
4761 && bits (this_instr, 4, 7) == 9) /* multiply */
4762 error (_("Invalid update to pc in instruction"));
4764 /* BX <reg>, BLX <reg> */
4765 if (bits (this_instr, 4, 27) == 0x12fff1
4766 || bits (this_instr, 4, 27) == 0x12fff3)
4768 rn = bits (this_instr, 0, 3);
4769 nextpc = ((rn == ARM_PC_REGNUM)
4771 : get_frame_register_unsigned (frame, rn));
4776 /* Multiply into PC. */
4777 c = (status & FLAG_C) ? 1 : 0;
4778 rn = bits (this_instr, 16, 19);
4779 operand1 = ((rn == ARM_PC_REGNUM)
4781 : get_frame_register_unsigned (frame, rn));
4783 if (bit (this_instr, 25))
4785 unsigned long immval = bits (this_instr, 0, 7);
4786 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4787 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4790 else /* operand 2 is a shifted register. */
4791 operand2 = shifted_reg_val (frame, this_instr, c,
4794 switch (bits (this_instr, 21, 24))
4797 result = operand1 & operand2;
4801 result = operand1 ^ operand2;
4805 result = operand1 - operand2;
4809 result = operand2 - operand1;
4813 result = operand1 + operand2;
4817 result = operand1 + operand2 + c;
4821 result = operand1 - operand2 + c;
4825 result = operand2 - operand1 + c;
4831 case 0xb: /* tst, teq, cmp, cmn */
4832 result = (unsigned long) nextpc;
4836 result = operand1 | operand2;
4840 /* Always step into a function. */
4845 result = operand1 & ~operand2;
4853 /* In 26-bit APCS the bottom two bits of the result are
4854 ignored, and we always end up in ARM state. */
4856 nextpc = arm_addr_bits_remove (gdbarch, result);
4864 case 0x5: /* data transfer */
4867 if (bit (this_instr, 20))
4870 if (bits (this_instr, 12, 15) == 15)
4876 if (bit (this_instr, 22))
4877 error (_("Invalid update to pc in instruction"));
4879 /* byte write to PC */
4880 rn = bits (this_instr, 16, 19);
4881 base = ((rn == ARM_PC_REGNUM)
4883 : get_frame_register_unsigned (frame, rn));
4885 if (bit (this_instr, 24))
4888 int c = (status & FLAG_C) ? 1 : 0;
4889 unsigned long offset =
4890 (bit (this_instr, 25)
4891 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4892 : bits (this_instr, 0, 11));
4894 if (bit (this_instr, 23))
4900 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4907 case 0x9: /* block transfer */
4908 if (bit (this_instr, 20))
4911 if (bit (this_instr, 15))
4915 unsigned long rn_val
4916 = get_frame_register_unsigned (frame,
4917 bits (this_instr, 16, 19));
4919 if (bit (this_instr, 23))
4922 unsigned long reglist = bits (this_instr, 0, 14);
4923 offset = bitcount (reglist) * 4;
4924 if (bit (this_instr, 24)) /* pre */
4927 else if (bit (this_instr, 24))
4931 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
4938 case 0xb: /* branch & link */
4939 case 0xa: /* branch */
4941 nextpc = BranchDest (pc, this_instr);
4947 case 0xe: /* coproc ops */
4951 struct gdbarch_tdep *tdep;
4952 tdep = gdbarch_tdep (gdbarch);
4954 if (tdep->syscall_next_pc != NULL)
4955 nextpc = tdep->syscall_next_pc (frame);
4961 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4969 /* Determine next PC after current instruction executes. Will call either
4970 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4971 loop is detected. */
4974 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4978 if (arm_frame_is_thumb (frame))
4980 nextpc = thumb_get_next_pc_raw (frame, pc);
4981 if (nextpc == MAKE_THUMB_ADDR (pc))
4982 error (_("Infinite loop detected"));
4986 nextpc = arm_get_next_pc_raw (frame, pc);
4988 error (_("Infinite loop detected"));
4994 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4995 of the appropriate mode (as encoded in the PC value), even if this
4996 differs from what would be expected according to the symbol tables. */
4999 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
5000 struct address_space *aspace,
5003 struct cleanup *old_chain
5004 = make_cleanup_restore_integer (&arm_override_mode);
5006 arm_override_mode = IS_THUMB_ADDR (pc);
5007 pc = gdbarch_addr_bits_remove (gdbarch, pc);
5009 insert_single_step_breakpoint (gdbarch, aspace, pc);
5011 do_cleanups (old_chain);
5014 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5015 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5016 is found, attempt to step through it. A breakpoint is placed at the end of
5020 thumb_deal_with_atomic_sequence_raw (struct frame_info *frame)
5022 struct gdbarch *gdbarch = get_frame_arch (frame);
5023 struct address_space *aspace = get_frame_address_space (frame);
5024 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5025 CORE_ADDR pc = get_frame_pc (frame);
5026 CORE_ADDR breaks[2] = {-1, -1};
5028 unsigned short insn1, insn2;
5031 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5032 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5033 ULONGEST status, itstate;
5035 /* We currently do not support atomic sequences within an IT block. */
5036 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
5037 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5041 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5042 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5044 if (thumb_insn_size (insn1) != 4)
5047 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5049 if (!((insn1 & 0xfff0) == 0xe850
5050 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5053 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5055 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5057 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5060 if (thumb_insn_size (insn1) != 4)
5062 /* Assume that there is at most one conditional branch in the
5063 atomic sequence. If a conditional branch is found, put a
5064 breakpoint in its destination address. */
5065 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
5067 if (last_breakpoint > 0)
5068 return 0; /* More than one conditional branch found,
5069 fallback to the standard code. */
5071 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
5075 /* We do not support atomic sequences that use any *other*
5076 instructions but conditional branches to change the PC.
5077 Fall back to standard code to avoid losing control of
5079 else if (thumb_instruction_changes_pc (insn1))
5084 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5087 /* Assume that there is at most one conditional branch in the
5088 atomic sequence. If a conditional branch is found, put a
5089 breakpoint in its destination address. */
5090 if ((insn1 & 0xf800) == 0xf000
5091 && (insn2 & 0xd000) == 0x8000
5092 && (insn1 & 0x0380) != 0x0380)
5094 int sign, j1, j2, imm1, imm2;
5095 unsigned int offset;
5097 sign = sbits (insn1, 10, 10);
5098 imm1 = bits (insn1, 0, 5);
5099 imm2 = bits (insn2, 0, 10);
5100 j1 = bit (insn2, 13);
5101 j2 = bit (insn2, 11);
5103 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5104 offset += (imm1 << 12) + (imm2 << 1);
5106 if (last_breakpoint > 0)
5107 return 0; /* More than one conditional branch found,
5108 fallback to the standard code. */
5110 breaks[1] = loc + offset;
5114 /* We do not support atomic sequences that use any *other*
5115 instructions but conditional branches to change the PC.
5116 Fall back to standard code to avoid losing control of
5118 else if (thumb2_instruction_changes_pc (insn1, insn2))
5121 /* If we find a strex{,b,h,d}, we're done. */
5122 if ((insn1 & 0xfff0) == 0xe840
5123 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5128 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5129 if (insn_count == atomic_sequence_length)
5132 /* Insert a breakpoint right after the end of the atomic sequence. */
5135 /* Check for duplicated breakpoints. Check also for a breakpoint
5136 placed (branch instruction's destination) anywhere in sequence. */
5138 && (breaks[1] == breaks[0]
5139 || (breaks[1] >= pc && breaks[1] < loc)))
5140 last_breakpoint = 0;
5142 /* Effectively inserts the breakpoints. */
5143 for (index = 0; index <= last_breakpoint; index++)
5144 arm_insert_single_step_breakpoint (gdbarch, aspace,
5145 MAKE_THUMB_ADDR (breaks[index]));
5151 arm_deal_with_atomic_sequence_raw (struct frame_info *frame)
5153 struct gdbarch *gdbarch = get_frame_arch (frame);
5154 struct address_space *aspace = get_frame_address_space (frame);
5155 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5156 CORE_ADDR pc = get_frame_pc (frame);
5157 CORE_ADDR breaks[2] = {-1, -1};
5162 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5163 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5165 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5166 Note that we do not currently support conditionally executed atomic
5168 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5170 if ((insn & 0xff9000f0) != 0xe1900090)
5173 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5175 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5177 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5180 /* Assume that there is at most one conditional branch in the atomic
5181 sequence. If a conditional branch is found, put a breakpoint in
5182 its destination address. */
5183 if (bits (insn, 24, 27) == 0xa)
5185 if (last_breakpoint > 0)
5186 return 0; /* More than one conditional branch found, fallback
5187 to the standard single-step code. */
5189 breaks[1] = BranchDest (loc - 4, insn);
5193 /* We do not support atomic sequences that use any *other* instructions
5194 but conditional branches to change the PC. Fall back to standard
5195 code to avoid losing control of execution. */
5196 else if (arm_instruction_changes_pc (insn))
5199 /* If we find a strex{,b,h,d}, we're done. */
5200 if ((insn & 0xff9000f0) == 0xe1800090)
5204 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5205 if (insn_count == atomic_sequence_length)
5208 /* Insert a breakpoint right after the end of the atomic sequence. */
5211 /* Check for duplicated breakpoints. Check also for a breakpoint
5212 placed (branch instruction's destination) anywhere in sequence. */
5214 && (breaks[1] == breaks[0]
5215 || (breaks[1] >= pc && breaks[1] < loc)))
5216 last_breakpoint = 0;
5218 /* Effectively inserts the breakpoints. */
5219 for (index = 0; index <= last_breakpoint; index++)
5220 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5226 arm_deal_with_atomic_sequence (struct frame_info *frame)
5228 if (arm_frame_is_thumb (frame))
5229 return thumb_deal_with_atomic_sequence_raw (frame);
5231 return arm_deal_with_atomic_sequence_raw (frame);
5234 /* single_step() is called just before we want to resume the inferior,
5235 if we want to single-step it but there is no hardware or kernel
5236 single-step support. We find the target of the coming instruction
5237 and breakpoint it. */
5240 arm_software_single_step (struct frame_info *frame)
5242 struct gdbarch *gdbarch = get_frame_arch (frame);
5243 struct address_space *aspace = get_frame_address_space (frame);
5246 if (arm_deal_with_atomic_sequence (frame))
5249 next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
5250 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5255 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5256 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5257 NULL if an error occurs. BUF is freed. */
5260 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5261 int old_len, int new_len)
5264 int bytes_to_read = new_len - old_len;
5266 new_buf = xmalloc (new_len);
5267 memcpy (new_buf + bytes_to_read, buf, old_len);
5269 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5277 /* An IT block is at most the 2-byte IT instruction followed by
5278 four 4-byte instructions. The furthest back we must search to
5279 find an IT block that affects the current instruction is thus
5280 2 + 3 * 4 == 14 bytes. */
5281 #define MAX_IT_BLOCK_PREFIX 14
5283 /* Use a quick scan if there are more than this many bytes of
5285 #define IT_SCAN_THRESHOLD 32
5287 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5288 A breakpoint in an IT block may not be hit, depending on the
5291 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5295 CORE_ADDR boundary, func_start;
5297 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5298 int i, any, last_it, last_it_count;
5300 /* If we are using BKPT breakpoints, none of this is necessary. */
5301 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5304 /* ARM mode does not have this problem. */
5305 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5308 /* We are setting a breakpoint in Thumb code that could potentially
5309 contain an IT block. The first step is to find how much Thumb
5310 code there is; we do not need to read outside of known Thumb
5312 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5314 /* Thumb-2 code must have mapping symbols to have a chance. */
5317 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5319 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5320 && func_start > boundary)
5321 boundary = func_start;
5323 /* Search for a candidate IT instruction. We have to do some fancy
5324 footwork to distinguish a real IT instruction from the second
5325 half of a 32-bit instruction, but there is no need for that if
5326 there's no candidate. */
5327 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5329 /* No room for an IT instruction. */
5332 buf = xmalloc (buf_len);
5333 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5336 for (i = 0; i < buf_len; i += 2)
5338 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5339 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5351 /* OK, the code bytes before this instruction contain at least one
5352 halfword which resembles an IT instruction. We know that it's
5353 Thumb code, but there are still two possibilities. Either the
5354 halfword really is an IT instruction, or it is the second half of
5355 a 32-bit Thumb instruction. The only way we can tell is to
5356 scan forwards from a known instruction boundary. */
5357 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5361 /* There's a lot of code before this instruction. Start with an
5362 optimistic search; it's easy to recognize halfwords that can
5363 not be the start of a 32-bit instruction, and use that to
5364 lock on to the instruction boundaries. */
5365 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5368 buf_len = IT_SCAN_THRESHOLD;
5371 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5373 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5374 if (thumb_insn_size (inst1) == 2)
5381 /* At this point, if DEFINITE, BUF[I] is the first place we
5382 are sure that we know the instruction boundaries, and it is far
5383 enough from BPADDR that we could not miss an IT instruction
5384 affecting BPADDR. If ! DEFINITE, give up - start from a
5388 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5392 buf_len = bpaddr - boundary;
5398 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5401 buf_len = bpaddr - boundary;
5405 /* Scan forwards. Find the last IT instruction before BPADDR. */
5410 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5412 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5417 else if (inst1 & 0x0002)
5419 else if (inst1 & 0x0004)
5424 i += thumb_insn_size (inst1);
5430 /* There wasn't really an IT instruction after all. */
5433 if (last_it_count < 1)
5434 /* It was too far away. */
5437 /* This really is a trouble spot. Move the breakpoint to the IT
5439 return bpaddr - buf_len + last_it;
5442 /* ARM displaced stepping support.
5444 Generally ARM displaced stepping works as follows:
5446 1. When an instruction is to be single-stepped, it is first decoded by
5447 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5448 Depending on the type of instruction, it is then copied to a scratch
5449 location, possibly in a modified form. The copy_* set of functions
5450 performs such modification, as necessary. A breakpoint is placed after
5451 the modified instruction in the scratch space to return control to GDB.
5452 Note in particular that instructions which modify the PC will no longer
5453 do so after modification.
5455 2. The instruction is single-stepped, by setting the PC to the scratch
5456 location address, and resuming. Control returns to GDB when the
5459 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5460 function used for the current instruction. This function's job is to
5461 put the CPU/memory state back to what it would have been if the
5462 instruction had been executed unmodified in its original location. */
5464 /* NOP instruction (mov r0, r0). */
5465 #define ARM_NOP 0xe1a00000
5466 #define THUMB_NOP 0x4600
5468 /* Helper for register reads for displaced stepping. In particular, this
5469 returns the PC as it would be seen by the instruction at its original
5473 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5477 CORE_ADDR from = dsc->insn_addr;
5479 if (regno == ARM_PC_REGNUM)
5481 /* Compute pipeline offset:
5482 - When executing an ARM instruction, PC reads as the address of the
5483 current instruction plus 8.
5484 - When executing a Thumb instruction, PC reads as the address of the
5485 current instruction plus 4. */
5492 if (debug_displaced)
5493 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5494 (unsigned long) from);
5495 return (ULONGEST) from;
5499 regcache_cooked_read_unsigned (regs, regno, &ret);
5500 if (debug_displaced)
5501 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5502 regno, (unsigned long) ret);
5508 displaced_in_arm_mode (struct regcache *regs)
5511 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5513 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5515 return (ps & t_bit) == 0;
5518 /* Write to the PC as from a branch instruction. */
5521 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5525 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5526 architecture versions < 6. */
5527 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5528 val & ~(ULONGEST) 0x3);
5530 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5531 val & ~(ULONGEST) 0x1);
5534 /* Write to the PC as from a branch-exchange instruction. */
5537 bx_write_pc (struct regcache *regs, ULONGEST val)
5540 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5542 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5546 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5547 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5549 else if ((val & 2) == 0)
5551 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5552 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5556 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5557 mode, align dest to 4 bytes). */
5558 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5559 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5560 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5564 /* Write to the PC as if from a load instruction. */
5567 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5570 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5571 bx_write_pc (regs, val);
5573 branch_write_pc (regs, dsc, val);
5576 /* Write to the PC as if from an ALU instruction. */
5579 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5582 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5583 bx_write_pc (regs, val);
5585 branch_write_pc (regs, dsc, val);
5588 /* Helper for writing to registers for displaced stepping. Writing to the PC
5589 has a varying effects depending on the instruction which does the write:
5590 this is controlled by the WRITE_PC argument. */
5593 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5594 int regno, ULONGEST val, enum pc_write_style write_pc)
5596 if (regno == ARM_PC_REGNUM)
5598 if (debug_displaced)
5599 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5600 (unsigned long) val);
5603 case BRANCH_WRITE_PC:
5604 branch_write_pc (regs, dsc, val);
5608 bx_write_pc (regs, val);
5612 load_write_pc (regs, dsc, val);
5616 alu_write_pc (regs, dsc, val);
5619 case CANNOT_WRITE_PC:
5620 warning (_("Instruction wrote to PC in an unexpected way when "
5621 "single-stepping"));
5625 internal_error (__FILE__, __LINE__,
5626 _("Invalid argument to displaced_write_reg"));
5629 dsc->wrote_to_pc = 1;
5633 if (debug_displaced)
5634 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5635 regno, (unsigned long) val);
5636 regcache_cooked_write_unsigned (regs, regno, val);
5640 /* This function is used to concisely determine if an instruction INSN
5641 references PC. Register fields of interest in INSN should have the
5642 corresponding fields of BITMASK set to 0b1111. The function
5643 returns return 1 if any of these fields in INSN reference the PC
5644 (also 0b1111, r15), else it returns 0. */
5647 insn_references_pc (uint32_t insn, uint32_t bitmask)
5649 uint32_t lowbit = 1;
5651 while (bitmask != 0)
5655 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5661 mask = lowbit * 0xf;
5663 if ((insn & mask) == mask)
5672 /* The simplest copy function. Many instructions have the same effect no
5673 matter what address they are executed at: in those cases, use this. */
5676 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5677 const char *iname, struct displaced_step_closure *dsc)
5679 if (debug_displaced)
5680 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5681 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5684 dsc->modinsn[0] = insn;
5690 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5691 uint16_t insn2, const char *iname,
5692 struct displaced_step_closure *dsc)
5694 if (debug_displaced)
5695 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5696 "opcode/class '%s' unmodified\n", insn1, insn2,
5699 dsc->modinsn[0] = insn1;
5700 dsc->modinsn[1] = insn2;
5706 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5709 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5711 struct displaced_step_closure *dsc)
5713 if (debug_displaced)
5714 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5715 "opcode/class '%s' unmodified\n", insn,
5718 dsc->modinsn[0] = insn;
5723 /* Preload instructions with immediate offset. */
5726 cleanup_preload (struct gdbarch *gdbarch,
5727 struct regcache *regs, struct displaced_step_closure *dsc)
5729 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5730 if (!dsc->u.preload.immed)
5731 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5735 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5736 struct displaced_step_closure *dsc, unsigned int rn)
5739 /* Preload instructions:
5741 {pli/pld} [rn, #+/-imm]
5743 {pli/pld} [r0, #+/-imm]. */
5745 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5746 rn_val = displaced_read_reg (regs, dsc, rn);
5747 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5748 dsc->u.preload.immed = 1;
5750 dsc->cleanup = &cleanup_preload;
5754 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5755 struct displaced_step_closure *dsc)
5757 unsigned int rn = bits (insn, 16, 19);
5759 if (!insn_references_pc (insn, 0x000f0000ul))
5760 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5762 if (debug_displaced)
5763 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5764 (unsigned long) insn);
5766 dsc->modinsn[0] = insn & 0xfff0ffff;
5768 install_preload (gdbarch, regs, dsc, rn);
5774 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5775 struct regcache *regs, struct displaced_step_closure *dsc)
5777 unsigned int rn = bits (insn1, 0, 3);
5778 unsigned int u_bit = bit (insn1, 7);
5779 int imm12 = bits (insn2, 0, 11);
5782 if (rn != ARM_PC_REGNUM)
5783 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5785 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5786 PLD (literal) Encoding T1. */
5787 if (debug_displaced)
5788 fprintf_unfiltered (gdb_stdlog,
5789 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5790 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5796 /* Rewrite instruction {pli/pld} PC imm12 into:
5797 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5801 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5803 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5804 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5806 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5808 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5809 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5810 dsc->u.preload.immed = 0;
5812 /* {pli/pld} [r0, r1] */
5813 dsc->modinsn[0] = insn1 & 0xfff0;
5814 dsc->modinsn[1] = 0xf001;
5817 dsc->cleanup = &cleanup_preload;
5821 /* Preload instructions with register offset. */
5824 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5825 struct displaced_step_closure *dsc, unsigned int rn,
5828 ULONGEST rn_val, rm_val;
5830 /* Preload register-offset instructions:
5832 {pli/pld} [rn, rm {, shift}]
5834 {pli/pld} [r0, r1 {, shift}]. */
5836 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5837 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5838 rn_val = displaced_read_reg (regs, dsc, rn);
5839 rm_val = displaced_read_reg (regs, dsc, rm);
5840 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5841 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5842 dsc->u.preload.immed = 0;
5844 dsc->cleanup = &cleanup_preload;
5848 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5849 struct regcache *regs,
5850 struct displaced_step_closure *dsc)
5852 unsigned int rn = bits (insn, 16, 19);
5853 unsigned int rm = bits (insn, 0, 3);
5856 if (!insn_references_pc (insn, 0x000f000ful))
5857 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5859 if (debug_displaced)
5860 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5861 (unsigned long) insn);
5863 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5865 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5869 /* Copy/cleanup coprocessor load and store instructions. */
5872 cleanup_copro_load_store (struct gdbarch *gdbarch,
5873 struct regcache *regs,
5874 struct displaced_step_closure *dsc)
5876 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5878 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5880 if (dsc->u.ldst.writeback)
5881 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5885 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5886 struct displaced_step_closure *dsc,
5887 int writeback, unsigned int rn)
5891 /* Coprocessor load/store instructions:
5893 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5895 {stc/stc2} [r0, #+/-imm].
5897 ldc/ldc2 are handled identically. */
5899 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5900 rn_val = displaced_read_reg (regs, dsc, rn);
5901 /* PC should be 4-byte aligned. */
5902 rn_val = rn_val & 0xfffffffc;
5903 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5905 dsc->u.ldst.writeback = writeback;
5906 dsc->u.ldst.rn = rn;
5908 dsc->cleanup = &cleanup_copro_load_store;
5912 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5913 struct regcache *regs,
5914 struct displaced_step_closure *dsc)
5916 unsigned int rn = bits (insn, 16, 19);
5918 if (!insn_references_pc (insn, 0x000f0000ul))
5919 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5921 if (debug_displaced)
5922 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5923 "load/store insn %.8lx\n", (unsigned long) insn);
5925 dsc->modinsn[0] = insn & 0xfff0ffff;
5927 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5933 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5934 uint16_t insn2, struct regcache *regs,
5935 struct displaced_step_closure *dsc)
5937 unsigned int rn = bits (insn1, 0, 3);
5939 if (rn != ARM_PC_REGNUM)
5940 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5941 "copro load/store", dsc);
5943 if (debug_displaced)
5944 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5945 "load/store insn %.4x%.4x\n", insn1, insn2);
5947 dsc->modinsn[0] = insn1 & 0xfff0;
5948 dsc->modinsn[1] = insn2;
5951 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5952 doesn't support writeback, so pass 0. */
5953 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
5958 /* Clean up branch instructions (actually perform the branch, by setting
5962 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
5963 struct displaced_step_closure *dsc)
5965 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5966 int branch_taken = condition_true (dsc->u.branch.cond, status);
5967 enum pc_write_style write_pc = dsc->u.branch.exchange
5968 ? BX_WRITE_PC : BRANCH_WRITE_PC;
5973 if (dsc->u.branch.link)
5975 /* The value of LR should be the next insn of current one. In order
5976 not to confuse logic hanlding later insn `bx lr', if current insn mode
5977 is Thumb, the bit 0 of LR value should be set to 1. */
5978 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5981 next_insn_addr |= 0x1;
5983 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5987 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5990 /* Copy B/BL/BLX instructions with immediate destinations. */
5993 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
5994 struct displaced_step_closure *dsc,
5995 unsigned int cond, int exchange, int link, long offset)
5997 /* Implement "BL<cond> <label>" as:
5999 Preparation: cond <- instruction condition
6000 Insn: mov r0, r0 (nop)
6001 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6003 B<cond> similar, but don't set r14 in cleanup. */
6005 dsc->u.branch.cond = cond;
6006 dsc->u.branch.link = link;
6007 dsc->u.branch.exchange = exchange;
6009 dsc->u.branch.dest = dsc->insn_addr;
6010 if (link && exchange)
6011 /* For BLX, offset is computed from the Align (PC, 4). */
6012 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6015 dsc->u.branch.dest += 4 + offset;
6017 dsc->u.branch.dest += 8 + offset;
6019 dsc->cleanup = &cleanup_branch;
6022 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
6023 struct regcache *regs, struct displaced_step_closure *dsc)
6025 unsigned int cond = bits (insn, 28, 31);
6026 int exchange = (cond == 0xf);
6027 int link = exchange || bit (insn, 24);
6030 if (debug_displaced)
6031 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
6032 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
6033 (unsigned long) insn);
6035 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6036 then arrange the switch into Thumb mode. */
6037 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
6039 offset = bits (insn, 0, 23) << 2;
6041 if (bit (offset, 25))
6042 offset = offset | ~0x3ffffff;
6044 dsc->modinsn[0] = ARM_NOP;
6046 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6051 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
6052 uint16_t insn2, struct regcache *regs,
6053 struct displaced_step_closure *dsc)
6055 int link = bit (insn2, 14);
6056 int exchange = link && !bit (insn2, 12);
6059 int j1 = bit (insn2, 13);
6060 int j2 = bit (insn2, 11);
6061 int s = sbits (insn1, 10, 10);
6062 int i1 = !(j1 ^ bit (insn1, 10));
6063 int i2 = !(j2 ^ bit (insn1, 10));
6065 if (!link && !exchange) /* B */
6067 offset = (bits (insn2, 0, 10) << 1);
6068 if (bit (insn2, 12)) /* Encoding T4 */
6070 offset |= (bits (insn1, 0, 9) << 12)
6076 else /* Encoding T3 */
6078 offset |= (bits (insn1, 0, 5) << 12)
6082 cond = bits (insn1, 6, 9);
6087 offset = (bits (insn1, 0, 9) << 12);
6088 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6089 offset |= exchange ?
6090 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
6093 if (debug_displaced)
6094 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
6095 "%.4x %.4x with offset %.8lx\n",
6096 link ? (exchange) ? "blx" : "bl" : "b",
6097 insn1, insn2, offset);
6099 dsc->modinsn[0] = THUMB_NOP;
6101 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6105 /* Copy B Thumb instructions. */
6107 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
6108 struct displaced_step_closure *dsc)
6110 unsigned int cond = 0;
6112 unsigned short bit_12_15 = bits (insn, 12, 15);
6113 CORE_ADDR from = dsc->insn_addr;
6115 if (bit_12_15 == 0xd)
6117 /* offset = SignExtend (imm8:0, 32) */
6118 offset = sbits ((insn << 1), 0, 8);
6119 cond = bits (insn, 8, 11);
6121 else if (bit_12_15 == 0xe) /* Encoding T2 */
6123 offset = sbits ((insn << 1), 0, 11);
6127 if (debug_displaced)
6128 fprintf_unfiltered (gdb_stdlog,
6129 "displaced: copying b immediate insn %.4x "
6130 "with offset %d\n", insn, offset);
6132 dsc->u.branch.cond = cond;
6133 dsc->u.branch.link = 0;
6134 dsc->u.branch.exchange = 0;
6135 dsc->u.branch.dest = from + 4 + offset;
6137 dsc->modinsn[0] = THUMB_NOP;
6139 dsc->cleanup = &cleanup_branch;
6144 /* Copy BX/BLX with register-specified destinations. */
6147 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6148 struct displaced_step_closure *dsc, int link,
6149 unsigned int cond, unsigned int rm)
6151 /* Implement {BX,BLX}<cond> <reg>" as:
6153 Preparation: cond <- instruction condition
6154 Insn: mov r0, r0 (nop)
6155 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6157 Don't set r14 in cleanup for BX. */
6159 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6161 dsc->u.branch.cond = cond;
6162 dsc->u.branch.link = link;
6164 dsc->u.branch.exchange = 1;
6166 dsc->cleanup = &cleanup_branch;
6170 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6171 struct regcache *regs, struct displaced_step_closure *dsc)
6173 unsigned int cond = bits (insn, 28, 31);
6176 int link = bit (insn, 5);
6177 unsigned int rm = bits (insn, 0, 3);
6179 if (debug_displaced)
6180 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6181 (unsigned long) insn);
6183 dsc->modinsn[0] = ARM_NOP;
6185 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6190 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6191 struct regcache *regs,
6192 struct displaced_step_closure *dsc)
6194 int link = bit (insn, 7);
6195 unsigned int rm = bits (insn, 3, 6);
6197 if (debug_displaced)
6198 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6199 (unsigned short) insn);
6201 dsc->modinsn[0] = THUMB_NOP;
6203 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6209 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6212 cleanup_alu_imm (struct gdbarch *gdbarch,
6213 struct regcache *regs, struct displaced_step_closure *dsc)
6215 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6216 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6217 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6218 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6222 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6223 struct displaced_step_closure *dsc)
6225 unsigned int rn = bits (insn, 16, 19);
6226 unsigned int rd = bits (insn, 12, 15);
6227 unsigned int op = bits (insn, 21, 24);
6228 int is_mov = (op == 0xd);
6229 ULONGEST rd_val, rn_val;
6231 if (!insn_references_pc (insn, 0x000ff000ul))
6232 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6234 if (debug_displaced)
6235 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6236 "%.8lx\n", is_mov ? "move" : "ALU",
6237 (unsigned long) insn);
6239 /* Instruction is of form:
6241 <op><cond> rd, [rn,] #imm
6245 Preparation: tmp1, tmp2 <- r0, r1;
6247 Insn: <op><cond> r0, r1, #imm
6248 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6251 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6252 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6253 rn_val = displaced_read_reg (regs, dsc, rn);
6254 rd_val = displaced_read_reg (regs, dsc, rd);
6255 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6256 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6260 dsc->modinsn[0] = insn & 0xfff00fff;
6262 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6264 dsc->cleanup = &cleanup_alu_imm;
6270 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6271 uint16_t insn2, struct regcache *regs,
6272 struct displaced_step_closure *dsc)
6274 unsigned int op = bits (insn1, 5, 8);
6275 unsigned int rn, rm, rd;
6276 ULONGEST rd_val, rn_val;
6278 rn = bits (insn1, 0, 3); /* Rn */
6279 rm = bits (insn2, 0, 3); /* Rm */
6280 rd = bits (insn2, 8, 11); /* Rd */
6282 /* This routine is only called for instruction MOV. */
6283 gdb_assert (op == 0x2 && rn == 0xf);
6285 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6286 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6288 if (debug_displaced)
6289 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6290 "ALU", insn1, insn2);
6292 /* Instruction is of form:
6294 <op><cond> rd, [rn,] #imm
6298 Preparation: tmp1, tmp2 <- r0, r1;
6300 Insn: <op><cond> r0, r1, #imm
6301 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6304 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6305 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6306 rn_val = displaced_read_reg (regs, dsc, rn);
6307 rd_val = displaced_read_reg (regs, dsc, rd);
6308 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6309 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6312 dsc->modinsn[0] = insn1;
6313 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6316 dsc->cleanup = &cleanup_alu_imm;
6321 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6324 cleanup_alu_reg (struct gdbarch *gdbarch,
6325 struct regcache *regs, struct displaced_step_closure *dsc)
6330 rd_val = displaced_read_reg (regs, dsc, 0);
6332 for (i = 0; i < 3; i++)
6333 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6335 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6339 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6340 struct displaced_step_closure *dsc,
6341 unsigned int rd, unsigned int rn, unsigned int rm)
6343 ULONGEST rd_val, rn_val, rm_val;
6345 /* Instruction is of form:
6347 <op><cond> rd, [rn,] rm [, <shift>]
6351 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6352 r0, r1, r2 <- rd, rn, rm
6353 Insn: <op><cond> r0, r1, r2 [, <shift>]
6354 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6357 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6358 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6359 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6360 rd_val = displaced_read_reg (regs, dsc, rd);
6361 rn_val = displaced_read_reg (regs, dsc, rn);
6362 rm_val = displaced_read_reg (regs, dsc, rm);
6363 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6364 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6365 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6368 dsc->cleanup = &cleanup_alu_reg;
6372 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6373 struct displaced_step_closure *dsc)
6375 unsigned int op = bits (insn, 21, 24);
6376 int is_mov = (op == 0xd);
6378 if (!insn_references_pc (insn, 0x000ff00ful))
6379 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6381 if (debug_displaced)
6382 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6383 is_mov ? "move" : "ALU", (unsigned long) insn);
6386 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6388 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6390 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6396 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6397 struct regcache *regs,
6398 struct displaced_step_closure *dsc)
6400 unsigned rn, rm, rd;
6402 rd = bits (insn, 3, 6);
6403 rn = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6406 if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6407 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6409 if (debug_displaced)
6410 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n",
6411 "ALU", (unsigned short) insn);
6413 dsc->modinsn[0] = ((insn & 0xff00) | 0x08);
6415 install_alu_reg (gdbarch, regs, dsc, rd, rn, rm);
6420 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6423 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6424 struct regcache *regs,
6425 struct displaced_step_closure *dsc)
6427 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6430 for (i = 0; i < 4; i++)
6431 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6433 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6437 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6438 struct displaced_step_closure *dsc,
6439 unsigned int rd, unsigned int rn, unsigned int rm,
6443 ULONGEST rd_val, rn_val, rm_val, rs_val;
6445 /* Instruction is of form:
6447 <op><cond> rd, [rn,] rm, <shift> rs
6451 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6452 r0, r1, r2, r3 <- rd, rn, rm, rs
6453 Insn: <op><cond> r0, r1, r2, <shift> r3
6455 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6459 for (i = 0; i < 4; i++)
6460 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6462 rd_val = displaced_read_reg (regs, dsc, rd);
6463 rn_val = displaced_read_reg (regs, dsc, rn);
6464 rm_val = displaced_read_reg (regs, dsc, rm);
6465 rs_val = displaced_read_reg (regs, dsc, rs);
6466 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6467 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6468 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6469 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6471 dsc->cleanup = &cleanup_alu_shifted_reg;
6475 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6476 struct regcache *regs,
6477 struct displaced_step_closure *dsc)
6479 unsigned int op = bits (insn, 21, 24);
6480 int is_mov = (op == 0xd);
6481 unsigned int rd, rn, rm, rs;
6483 if (!insn_references_pc (insn, 0x000fff0ful))
6484 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6486 if (debug_displaced)
6487 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6488 "%.8lx\n", is_mov ? "move" : "ALU",
6489 (unsigned long) insn);
6491 rn = bits (insn, 16, 19);
6492 rm = bits (insn, 0, 3);
6493 rs = bits (insn, 8, 11);
6494 rd = bits (insn, 12, 15);
6497 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6499 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6501 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6506 /* Clean up load instructions. */
6509 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6510 struct displaced_step_closure *dsc)
6512 ULONGEST rt_val, rt_val2 = 0, rn_val;
6514 rt_val = displaced_read_reg (regs, dsc, 0);
6515 if (dsc->u.ldst.xfersize == 8)
6516 rt_val2 = displaced_read_reg (regs, dsc, 1);
6517 rn_val = displaced_read_reg (regs, dsc, 2);
6519 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6520 if (dsc->u.ldst.xfersize > 4)
6521 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6522 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6523 if (!dsc->u.ldst.immed)
6524 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6526 /* Handle register writeback. */
6527 if (dsc->u.ldst.writeback)
6528 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6529 /* Put result in right place. */
6530 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6531 if (dsc->u.ldst.xfersize == 8)
6532 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6535 /* Clean up store instructions. */
6538 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6539 struct displaced_step_closure *dsc)
6541 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6543 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6544 if (dsc->u.ldst.xfersize > 4)
6545 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6546 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6547 if (!dsc->u.ldst.immed)
6548 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6549 if (!dsc->u.ldst.restore_r4)
6550 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6553 if (dsc->u.ldst.writeback)
6554 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6557 /* Copy "extra" load/store instructions. These are halfword/doubleword
6558 transfers, which have a different encoding to byte/word transfers. */
6561 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6562 struct regcache *regs, struct displaced_step_closure *dsc)
6564 unsigned int op1 = bits (insn, 20, 24);
6565 unsigned int op2 = bits (insn, 5, 6);
6566 unsigned int rt = bits (insn, 12, 15);
6567 unsigned int rn = bits (insn, 16, 19);
6568 unsigned int rm = bits (insn, 0, 3);
6569 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6570 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6571 int immed = (op1 & 0x4) != 0;
6573 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6575 if (!insn_references_pc (insn, 0x000ff00ful))
6576 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6578 if (debug_displaced)
6579 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6580 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6581 (unsigned long) insn);
6583 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6586 internal_error (__FILE__, __LINE__,
6587 _("copy_extra_ld_st: instruction decode error"));
6589 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6590 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6591 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6593 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6595 rt_val = displaced_read_reg (regs, dsc, rt);
6596 if (bytesize[opcode] == 8)
6597 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6598 rn_val = displaced_read_reg (regs, dsc, rn);
6600 rm_val = displaced_read_reg (regs, dsc, rm);
6602 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6603 if (bytesize[opcode] == 8)
6604 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6605 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6607 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6610 dsc->u.ldst.xfersize = bytesize[opcode];
6611 dsc->u.ldst.rn = rn;
6612 dsc->u.ldst.immed = immed;
6613 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6614 dsc->u.ldst.restore_r4 = 0;
6617 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6619 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6620 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6622 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6624 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6625 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6627 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6632 /* Copy byte/half word/word loads and stores. */
6635 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6636 struct displaced_step_closure *dsc, int load,
6637 int immed, int writeback, int size, int usermode,
6638 int rt, int rm, int rn)
6640 ULONGEST rt_val, rn_val, rm_val = 0;
6642 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6643 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6645 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6647 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6649 rt_val = displaced_read_reg (regs, dsc, rt);
6650 rn_val = displaced_read_reg (regs, dsc, rn);
6652 rm_val = displaced_read_reg (regs, dsc, rm);
6654 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6655 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6657 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6659 dsc->u.ldst.xfersize = size;
6660 dsc->u.ldst.rn = rn;
6661 dsc->u.ldst.immed = immed;
6662 dsc->u.ldst.writeback = writeback;
6664 /* To write PC we can do:
6666 Before this sequence of instructions:
6667 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6668 r2 is the Rn value got from dispalced_read_reg.
6670 Insn1: push {pc} Write address of STR instruction + offset on stack
6671 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6672 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6673 = addr(Insn1) + offset - addr(Insn3) - 8
6675 Insn4: add r4, r4, #8 r4 = offset - 8
6676 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6678 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6680 Otherwise we don't know what value to write for PC, since the offset is
6681 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6682 of this can be found in Section "Saving from r15" in
6683 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6685 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6690 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6691 uint16_t insn2, struct regcache *regs,
6692 struct displaced_step_closure *dsc, int size)
6694 unsigned int u_bit = bit (insn1, 7);
6695 unsigned int rt = bits (insn2, 12, 15);
6696 int imm12 = bits (insn2, 0, 11);
6699 if (debug_displaced)
6700 fprintf_unfiltered (gdb_stdlog,
6701 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6702 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6708 /* Rewrite instruction LDR Rt imm12 into:
6710 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6714 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6717 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6718 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6719 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6721 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6723 pc_val = pc_val & 0xfffffffc;
6725 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6726 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6730 dsc->u.ldst.xfersize = size;
6731 dsc->u.ldst.immed = 0;
6732 dsc->u.ldst.writeback = 0;
6733 dsc->u.ldst.restore_r4 = 0;
6735 /* LDR R0, R2, R3 */
6736 dsc->modinsn[0] = 0xf852;
6737 dsc->modinsn[1] = 0x3;
6740 dsc->cleanup = &cleanup_load;
6746 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6747 uint16_t insn2, struct regcache *regs,
6748 struct displaced_step_closure *dsc,
6749 int writeback, int immed)
6751 unsigned int rt = bits (insn2, 12, 15);
6752 unsigned int rn = bits (insn1, 0, 3);
6753 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6754 /* In LDR (register), there is also a register Rm, which is not allowed to
6755 be PC, so we don't have to check it. */
6757 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6758 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6761 if (debug_displaced)
6762 fprintf_unfiltered (gdb_stdlog,
6763 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6764 rt, rn, insn1, insn2);
6766 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6769 dsc->u.ldst.restore_r4 = 0;
6772 /* ldr[b]<cond> rt, [rn, #imm], etc.
6774 ldr[b]<cond> r0, [r2, #imm]. */
6776 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6777 dsc->modinsn[1] = insn2 & 0x0fff;
6780 /* ldr[b]<cond> rt, [rn, rm], etc.
6782 ldr[b]<cond> r0, [r2, r3]. */
6784 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6785 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6795 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6796 struct regcache *regs,
6797 struct displaced_step_closure *dsc,
6798 int load, int size, int usermode)
6800 int immed = !bit (insn, 25);
6801 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6802 unsigned int rt = bits (insn, 12, 15);
6803 unsigned int rn = bits (insn, 16, 19);
6804 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6806 if (!insn_references_pc (insn, 0x000ff00ful))
6807 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6809 if (debug_displaced)
6810 fprintf_unfiltered (gdb_stdlog,
6811 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6812 load ? (size == 1 ? "ldrb" : "ldr")
6813 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6815 (unsigned long) insn);
6817 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6818 usermode, rt, rm, rn);
6820 if (load || rt != ARM_PC_REGNUM)
6822 dsc->u.ldst.restore_r4 = 0;
6825 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6827 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6828 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6830 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6832 {ldr,str}[b]<cond> r0, [r2, r3]. */
6833 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6837 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6838 dsc->u.ldst.restore_r4 = 1;
6839 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6840 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6841 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6842 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6843 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6847 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6849 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6854 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6859 /* Cleanup LDM instructions with fully-populated register list. This is an
6860 unfortunate corner case: it's impossible to implement correctly by modifying
6861 the instruction. The issue is as follows: we have an instruction,
6865 which we must rewrite to avoid loading PC. A possible solution would be to
6866 do the load in two halves, something like (with suitable cleanup
6870 ldm[id][ab] r8!, {r0-r7}
6872 ldm[id][ab] r8, {r7-r14}
6875 but at present there's no suitable place for <temp>, since the scratch space
6876 is overwritten before the cleanup routine is called. For now, we simply
6877 emulate the instruction. */
6880 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6881 struct displaced_step_closure *dsc)
6883 int inc = dsc->u.block.increment;
6884 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6885 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6886 uint32_t regmask = dsc->u.block.regmask;
6887 int regno = inc ? 0 : 15;
6888 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6889 int exception_return = dsc->u.block.load && dsc->u.block.user
6890 && (regmask & 0x8000) != 0;
6891 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6892 int do_transfer = condition_true (dsc->u.block.cond, status);
6893 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6898 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6899 sensible we can do here. Complain loudly. */
6900 if (exception_return)
6901 error (_("Cannot single-step exception return"));
6903 /* We don't handle any stores here for now. */
6904 gdb_assert (dsc->u.block.load != 0);
6906 if (debug_displaced)
6907 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6908 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6909 dsc->u.block.increment ? "inc" : "dec",
6910 dsc->u.block.before ? "before" : "after");
6917 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6920 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6923 xfer_addr += bump_before;
6925 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6926 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6928 xfer_addr += bump_after;
6930 regmask &= ~(1 << regno);
6933 if (dsc->u.block.writeback)
6934 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6938 /* Clean up an STM which included the PC in the register list. */
6941 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6942 struct displaced_step_closure *dsc)
6944 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6945 int store_executed = condition_true (dsc->u.block.cond, status);
6946 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
6947 CORE_ADDR stm_insn_addr;
6950 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6952 /* If condition code fails, there's nothing else to do. */
6953 if (!store_executed)
6956 if (dsc->u.block.increment)
6958 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6960 if (dsc->u.block.before)
6965 pc_stored_at = dsc->u.block.xfer_addr;
6967 if (dsc->u.block.before)
6971 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
6972 stm_insn_addr = dsc->scratch_base;
6973 offset = pc_val - stm_insn_addr;
6975 if (debug_displaced)
6976 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
6977 "STM instruction\n", offset);
6979 /* Rewrite the stored PC to the proper value for the non-displaced original
6981 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
6982 dsc->insn_addr + offset);
6985 /* Clean up an LDM which includes the PC in the register list. We clumped all
6986 the registers in the transferred list into a contiguous range r0...rX (to
6987 avoid loading PC directly and losing control of the debugged program), so we
6988 must undo that here. */
6991 cleanup_block_load_pc (struct gdbarch *gdbarch,
6992 struct regcache *regs,
6993 struct displaced_step_closure *dsc)
6995 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6996 int load_executed = condition_true (dsc->u.block.cond, status);
6997 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6998 unsigned int regs_loaded = bitcount (mask);
6999 unsigned int num_to_shuffle = regs_loaded, clobbered;
7001 /* The method employed here will fail if the register list is fully populated
7002 (we need to avoid loading PC directly). */
7003 gdb_assert (num_to_shuffle < 16);
7008 clobbered = (1 << num_to_shuffle) - 1;
7010 while (num_to_shuffle > 0)
7012 if ((mask & (1 << write_reg)) != 0)
7014 unsigned int read_reg = num_to_shuffle - 1;
7016 if (read_reg != write_reg)
7018 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
7019 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7020 if (debug_displaced)
7021 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
7022 "loaded register r%d to r%d\n"), read_reg,
7025 else if (debug_displaced)
7026 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
7027 "r%d already in the right place\n"),
7030 clobbered &= ~(1 << write_reg);
7038 /* Restore any registers we scribbled over. */
7039 for (write_reg = 0; clobbered != 0; write_reg++)
7041 if ((clobbered & (1 << write_reg)) != 0)
7043 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7045 if (debug_displaced)
7046 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
7047 "clobbered register r%d\n"), write_reg);
7048 clobbered &= ~(1 << write_reg);
7052 /* Perform register writeback manually. */
7053 if (dsc->u.block.writeback)
7055 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7057 if (dsc->u.block.increment)
7058 new_rn_val += regs_loaded * 4;
7060 new_rn_val -= regs_loaded * 4;
7062 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7067 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7068 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7071 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
7072 struct regcache *regs,
7073 struct displaced_step_closure *dsc)
7075 int load = bit (insn, 20);
7076 int user = bit (insn, 22);
7077 int increment = bit (insn, 23);
7078 int before = bit (insn, 24);
7079 int writeback = bit (insn, 21);
7080 int rn = bits (insn, 16, 19);
7082 /* Block transfers which don't mention PC can be run directly
7084 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
7085 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7087 if (rn == ARM_PC_REGNUM)
7089 warning (_("displaced: Unpredictable LDM or STM with "
7090 "base register r15"));
7091 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7094 if (debug_displaced)
7095 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7096 "%.8lx\n", (unsigned long) insn);
7098 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7099 dsc->u.block.rn = rn;
7101 dsc->u.block.load = load;
7102 dsc->u.block.user = user;
7103 dsc->u.block.increment = increment;
7104 dsc->u.block.before = before;
7105 dsc->u.block.writeback = writeback;
7106 dsc->u.block.cond = bits (insn, 28, 31);
7108 dsc->u.block.regmask = insn & 0xffff;
7112 if ((insn & 0xffff) == 0xffff)
7114 /* LDM with a fully-populated register list. This case is
7115 particularly tricky. Implement for now by fully emulating the
7116 instruction (which might not behave perfectly in all cases, but
7117 these instructions should be rare enough for that not to matter
7119 dsc->modinsn[0] = ARM_NOP;
7121 dsc->cleanup = &cleanup_block_load_all;
7125 /* LDM of a list of registers which includes PC. Implement by
7126 rewriting the list of registers to be transferred into a
7127 contiguous chunk r0...rX before doing the transfer, then shuffling
7128 registers into the correct places in the cleanup routine. */
7129 unsigned int regmask = insn & 0xffff;
7130 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7131 unsigned int to = 0, from = 0, i, new_rn;
7133 for (i = 0; i < num_in_list; i++)
7134 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7136 /* Writeback makes things complicated. We need to avoid clobbering
7137 the base register with one of the registers in our modified
7138 register list, but just using a different register can't work in
7141 ldm r14!, {r0-r13,pc}
7143 which would need to be rewritten as:
7147 but that can't work, because there's no free register for N.
7149 Solve this by turning off the writeback bit, and emulating
7150 writeback manually in the cleanup routine. */
7155 new_regmask = (1 << num_in_list) - 1;
7157 if (debug_displaced)
7158 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7159 "{..., pc}: original reg list %.4x, modified "
7160 "list %.4x\n"), rn, writeback ? "!" : "",
7161 (int) insn & 0xffff, new_regmask);
7163 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7165 dsc->cleanup = &cleanup_block_load_pc;
7170 /* STM of a list of registers which includes PC. Run the instruction
7171 as-is, but out of line: this will store the wrong value for the PC,
7172 so we must manually fix up the memory in the cleanup routine.
7173 Doing things this way has the advantage that we can auto-detect
7174 the offset of the PC write (which is architecture-dependent) in
7175 the cleanup routine. */
7176 dsc->modinsn[0] = insn;
7178 dsc->cleanup = &cleanup_block_store_pc;
7185 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7186 struct regcache *regs,
7187 struct displaced_step_closure *dsc)
7189 int rn = bits (insn1, 0, 3);
7190 int load = bit (insn1, 4);
7191 int writeback = bit (insn1, 5);
7193 /* Block transfers which don't mention PC can be run directly
7195 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7196 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7198 if (rn == ARM_PC_REGNUM)
7200 warning (_("displaced: Unpredictable LDM or STM with "
7201 "base register r15"));
7202 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7203 "unpredictable ldm/stm", dsc);
7206 if (debug_displaced)
7207 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7208 "%.4x%.4x\n", insn1, insn2);
7210 /* Clear bit 13, since it should be always zero. */
7211 dsc->u.block.regmask = (insn2 & 0xdfff);
7212 dsc->u.block.rn = rn;
7214 dsc->u.block.load = load;
7215 dsc->u.block.user = 0;
7216 dsc->u.block.increment = bit (insn1, 7);
7217 dsc->u.block.before = bit (insn1, 8);
7218 dsc->u.block.writeback = writeback;
7219 dsc->u.block.cond = INST_AL;
7220 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7224 if (dsc->u.block.regmask == 0xffff)
7226 /* This branch is impossible to happen. */
7231 unsigned int regmask = dsc->u.block.regmask;
7232 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7233 unsigned int to = 0, from = 0, i, new_rn;
7235 for (i = 0; i < num_in_list; i++)
7236 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7241 new_regmask = (1 << num_in_list) - 1;
7243 if (debug_displaced)
7244 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7245 "{..., pc}: original reg list %.4x, modified "
7246 "list %.4x\n"), rn, writeback ? "!" : "",
7247 (int) dsc->u.block.regmask, new_regmask);
7249 dsc->modinsn[0] = insn1;
7250 dsc->modinsn[1] = (new_regmask & 0xffff);
7253 dsc->cleanup = &cleanup_block_load_pc;
7258 dsc->modinsn[0] = insn1;
7259 dsc->modinsn[1] = insn2;
7261 dsc->cleanup = &cleanup_block_store_pc;
7266 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7267 for Linux, where some SVC instructions must be treated specially. */
7270 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7271 struct displaced_step_closure *dsc)
7273 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7275 if (debug_displaced)
7276 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7277 "%.8lx\n", (unsigned long) resume_addr);
7279 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7283 /* Common copy routine for svc instruciton. */
7286 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7287 struct displaced_step_closure *dsc)
7289 /* Preparation: none.
7290 Insn: unmodified svc.
7291 Cleanup: pc <- insn_addr + insn_size. */
7293 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7295 dsc->wrote_to_pc = 1;
7297 /* Allow OS-specific code to override SVC handling. */
7298 if (dsc->u.svc.copy_svc_os)
7299 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7302 dsc->cleanup = &cleanup_svc;
7308 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7309 struct regcache *regs, struct displaced_step_closure *dsc)
7312 if (debug_displaced)
7313 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7314 (unsigned long) insn);
7316 dsc->modinsn[0] = insn;
7318 return install_svc (gdbarch, regs, dsc);
7322 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7323 struct regcache *regs, struct displaced_step_closure *dsc)
7326 if (debug_displaced)
7327 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7330 dsc->modinsn[0] = insn;
7332 return install_svc (gdbarch, regs, dsc);
7335 /* Copy undefined instructions. */
7338 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7339 struct displaced_step_closure *dsc)
7341 if (debug_displaced)
7342 fprintf_unfiltered (gdb_stdlog,
7343 "displaced: copying undefined insn %.8lx\n",
7344 (unsigned long) insn);
7346 dsc->modinsn[0] = insn;
7352 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7353 struct displaced_step_closure *dsc)
7356 if (debug_displaced)
7357 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7358 "%.4x %.4x\n", (unsigned short) insn1,
7359 (unsigned short) insn2);
7361 dsc->modinsn[0] = insn1;
7362 dsc->modinsn[1] = insn2;
7368 /* Copy unpredictable instructions. */
7371 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7372 struct displaced_step_closure *dsc)
7374 if (debug_displaced)
7375 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7376 "%.8lx\n", (unsigned long) insn);
7378 dsc->modinsn[0] = insn;
7383 /* The decode_* functions are instruction decoding helpers. They mostly follow
7384 the presentation in the ARM ARM. */
7387 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7388 struct regcache *regs,
7389 struct displaced_step_closure *dsc)
7391 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7392 unsigned int rn = bits (insn, 16, 19);
7394 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7395 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7396 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7397 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7398 else if ((op1 & 0x60) == 0x20)
7399 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7400 else if ((op1 & 0x71) == 0x40)
7401 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7403 else if ((op1 & 0x77) == 0x41)
7404 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7405 else if ((op1 & 0x77) == 0x45)
7406 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7407 else if ((op1 & 0x77) == 0x51)
7410 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7412 return arm_copy_unpred (gdbarch, insn, dsc);
7414 else if ((op1 & 0x77) == 0x55)
7415 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7416 else if (op1 == 0x57)
7419 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7420 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7421 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7422 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7423 default: return arm_copy_unpred (gdbarch, insn, dsc);
7425 else if ((op1 & 0x63) == 0x43)
7426 return arm_copy_unpred (gdbarch, insn, dsc);
7427 else if ((op2 & 0x1) == 0x0)
7428 switch (op1 & ~0x80)
7431 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7433 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7434 case 0x71: case 0x75:
7436 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7437 case 0x63: case 0x67: case 0x73: case 0x77:
7438 return arm_copy_unpred (gdbarch, insn, dsc);
7440 return arm_copy_undef (gdbarch, insn, dsc);
7443 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7447 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7448 struct regcache *regs,
7449 struct displaced_step_closure *dsc)
7451 if (bit (insn, 27) == 0)
7452 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7453 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7454 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7457 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7460 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7462 case 0x4: case 0x5: case 0x6: case 0x7:
7463 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7466 switch ((insn & 0xe00000) >> 21)
7468 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7470 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7473 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7476 return arm_copy_undef (gdbarch, insn, dsc);
7481 int rn_f = (bits (insn, 16, 19) == 0xf);
7482 switch ((insn & 0xe00000) >> 21)
7485 /* ldc/ldc2 imm (undefined for rn == pc). */
7486 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7487 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7490 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7492 case 0x4: case 0x5: case 0x6: case 0x7:
7493 /* ldc/ldc2 lit (undefined for rn != pc). */
7494 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7495 : arm_copy_undef (gdbarch, insn, dsc);
7498 return arm_copy_undef (gdbarch, insn, dsc);
7503 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7506 if (bits (insn, 16, 19) == 0xf)
7508 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7510 return arm_copy_undef (gdbarch, insn, dsc);
7514 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7516 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7520 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7522 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7525 return arm_copy_undef (gdbarch, insn, dsc);
7529 /* Decode miscellaneous instructions in dp/misc encoding space. */
7532 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7533 struct regcache *regs,
7534 struct displaced_step_closure *dsc)
7536 unsigned int op2 = bits (insn, 4, 6);
7537 unsigned int op = bits (insn, 21, 22);
7538 unsigned int op1 = bits (insn, 16, 19);
7543 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7546 if (op == 0x1) /* bx. */
7547 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7549 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7551 return arm_copy_undef (gdbarch, insn, dsc);
7555 /* Not really supported. */
7556 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7558 return arm_copy_undef (gdbarch, insn, dsc);
7562 return arm_copy_bx_blx_reg (gdbarch, insn,
7563 regs, dsc); /* blx register. */
7565 return arm_copy_undef (gdbarch, insn, dsc);
7568 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7572 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7574 /* Not really supported. */
7575 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7578 return arm_copy_undef (gdbarch, insn, dsc);
7583 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7584 struct regcache *regs,
7585 struct displaced_step_closure *dsc)
7588 switch (bits (insn, 20, 24))
7591 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7594 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7596 case 0x12: case 0x16:
7597 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7600 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7604 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7606 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7607 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7608 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7609 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7610 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7611 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7612 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7613 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7614 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7615 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7616 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7617 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7618 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7619 /* 2nd arg means "unpriveleged". */
7620 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7624 /* Should be unreachable. */
7629 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7630 struct regcache *regs,
7631 struct displaced_step_closure *dsc)
7633 int a = bit (insn, 25), b = bit (insn, 4);
7634 uint32_t op1 = bits (insn, 20, 24);
7635 int rn_f = bits (insn, 16, 19) == 0xf;
7637 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7638 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7639 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7640 else if ((!a && (op1 & 0x17) == 0x02)
7641 || (a && (op1 & 0x17) == 0x02 && !b))
7642 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7643 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7644 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7645 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7646 else if ((!a && (op1 & 0x17) == 0x03)
7647 || (a && (op1 & 0x17) == 0x03 && !b))
7648 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7649 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7650 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7651 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7652 else if ((!a && (op1 & 0x17) == 0x06)
7653 || (a && (op1 & 0x17) == 0x06 && !b))
7654 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7655 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7656 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7657 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7658 else if ((!a && (op1 & 0x17) == 0x07)
7659 || (a && (op1 & 0x17) == 0x07 && !b))
7660 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7662 /* Should be unreachable. */
7667 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7668 struct displaced_step_closure *dsc)
7670 switch (bits (insn, 20, 24))
7672 case 0x00: case 0x01: case 0x02: case 0x03:
7673 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7675 case 0x04: case 0x05: case 0x06: case 0x07:
7676 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7678 case 0x08: case 0x09: case 0x0a: case 0x0b:
7679 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7680 return arm_copy_unmodified (gdbarch, insn,
7681 "decode/pack/unpack/saturate/reverse", dsc);
7684 if (bits (insn, 5, 7) == 0) /* op2. */
7686 if (bits (insn, 12, 15) == 0xf)
7687 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7689 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7692 return arm_copy_undef (gdbarch, insn, dsc);
7694 case 0x1a: case 0x1b:
7695 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7696 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7698 return arm_copy_undef (gdbarch, insn, dsc);
7700 case 0x1c: case 0x1d:
7701 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7703 if (bits (insn, 0, 3) == 0xf)
7704 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7706 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7709 return arm_copy_undef (gdbarch, insn, dsc);
7711 case 0x1e: case 0x1f:
7712 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7713 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7715 return arm_copy_undef (gdbarch, insn, dsc);
7718 /* Should be unreachable. */
7723 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7724 struct regcache *regs,
7725 struct displaced_step_closure *dsc)
7728 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7730 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7734 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7735 struct regcache *regs,
7736 struct displaced_step_closure *dsc)
7738 unsigned int opcode = bits (insn, 20, 24);
7742 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7743 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7745 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7746 case 0x12: case 0x16:
7747 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7749 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7750 case 0x13: case 0x17:
7751 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7753 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7754 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7755 /* Note: no writeback for these instructions. Bit 25 will always be
7756 zero though (via caller), so the following works OK. */
7757 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7760 /* Should be unreachable. */
7764 /* Decode shifted register instructions. */
7767 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7768 uint16_t insn2, struct regcache *regs,
7769 struct displaced_step_closure *dsc)
7771 /* PC is only allowed to be used in instruction MOV. */
7773 unsigned int op = bits (insn1, 5, 8);
7774 unsigned int rn = bits (insn1, 0, 3);
7776 if (op == 0x2 && rn == 0xf) /* MOV */
7777 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7779 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7780 "dp (shift reg)", dsc);
7784 /* Decode extension register load/store. Exactly the same as
7785 arm_decode_ext_reg_ld_st. */
7788 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7789 uint16_t insn2, struct regcache *regs,
7790 struct displaced_step_closure *dsc)
7792 unsigned int opcode = bits (insn1, 4, 8);
7796 case 0x04: case 0x05:
7797 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7798 "vfp/neon vmov", dsc);
7800 case 0x08: case 0x0c: /* 01x00 */
7801 case 0x0a: case 0x0e: /* 01x10 */
7802 case 0x12: case 0x16: /* 10x10 */
7803 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7804 "vfp/neon vstm/vpush", dsc);
7806 case 0x09: case 0x0d: /* 01x01 */
7807 case 0x0b: case 0x0f: /* 01x11 */
7808 case 0x13: case 0x17: /* 10x11 */
7809 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7810 "vfp/neon vldm/vpop", dsc);
7812 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7813 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7815 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7816 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7819 /* Should be unreachable. */
7824 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7825 struct regcache *regs, struct displaced_step_closure *dsc)
7827 unsigned int op1 = bits (insn, 20, 25);
7828 int op = bit (insn, 4);
7829 unsigned int coproc = bits (insn, 8, 11);
7830 unsigned int rn = bits (insn, 16, 19);
7832 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7833 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7834 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7835 && (coproc & 0xe) != 0xa)
7837 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7838 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7839 && (coproc & 0xe) != 0xa)
7840 /* ldc/ldc2 imm/lit. */
7841 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7842 else if ((op1 & 0x3e) == 0x00)
7843 return arm_copy_undef (gdbarch, insn, dsc);
7844 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7845 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7846 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7847 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7848 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7849 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7850 else if ((op1 & 0x30) == 0x20 && !op)
7852 if ((coproc & 0xe) == 0xa)
7853 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7855 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7857 else if ((op1 & 0x30) == 0x20 && op)
7858 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7859 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7860 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7861 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7862 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7863 else if ((op1 & 0x30) == 0x30)
7864 return arm_copy_svc (gdbarch, insn, regs, dsc);
7866 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7870 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7871 uint16_t insn2, struct regcache *regs,
7872 struct displaced_step_closure *dsc)
7874 unsigned int coproc = bits (insn2, 8, 11);
7875 unsigned int op1 = bits (insn1, 4, 9);
7876 unsigned int bit_5_8 = bits (insn1, 5, 8);
7877 unsigned int bit_9 = bit (insn1, 9);
7878 unsigned int bit_4 = bit (insn1, 4);
7879 unsigned int rn = bits (insn1, 0, 3);
7884 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7885 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7887 else if (bit_5_8 == 0) /* UNDEFINED. */
7888 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7891 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7892 if ((coproc & 0xe) == 0xa)
7893 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7895 else /* coproc is not 101x. */
7897 if (bit_4 == 0) /* STC/STC2. */
7898 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7900 else /* LDC/LDC2 {literal, immeidate}. */
7901 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7907 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7913 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7914 struct displaced_step_closure *dsc, int rd)
7920 Preparation: Rd <- PC
7926 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7927 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7931 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7932 struct displaced_step_closure *dsc,
7933 int rd, unsigned int imm)
7936 /* Encoding T2: ADDS Rd, #imm */
7937 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7939 install_pc_relative (gdbarch, regs, dsc, rd);
7945 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
7946 struct regcache *regs,
7947 struct displaced_step_closure *dsc)
7949 unsigned int rd = bits (insn, 8, 10);
7950 unsigned int imm8 = bits (insn, 0, 7);
7952 if (debug_displaced)
7953 fprintf_unfiltered (gdb_stdlog,
7954 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7957 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7961 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7962 uint16_t insn2, struct regcache *regs,
7963 struct displaced_step_closure *dsc)
7965 unsigned int rd = bits (insn2, 8, 11);
7966 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7967 extract raw immediate encoding rather than computing immediate. When
7968 generating ADD or SUB instruction, we can simply perform OR operation to
7969 set immediate into ADD. */
7970 unsigned int imm_3_8 = insn2 & 0x70ff;
7971 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7973 if (debug_displaced)
7974 fprintf_unfiltered (gdb_stdlog,
7975 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7976 rd, imm_i, imm_3_8, insn1, insn2);
7978 if (bit (insn1, 7)) /* Encoding T2 */
7980 /* Encoding T3: SUB Rd, Rd, #imm */
7981 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7982 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7984 else /* Encoding T3 */
7986 /* Encoding T3: ADD Rd, Rd, #imm */
7987 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7988 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7992 install_pc_relative (gdbarch, regs, dsc, rd);
7998 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
7999 struct regcache *regs,
8000 struct displaced_step_closure *dsc)
8002 unsigned int rt = bits (insn1, 8, 10);
8004 int imm8 = (bits (insn1, 0, 7) << 2);
8005 CORE_ADDR from = dsc->insn_addr;
8011 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8013 Insn: LDR R0, [R2, R3];
8014 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8016 if (debug_displaced)
8017 fprintf_unfiltered (gdb_stdlog,
8018 "displaced: copying thumb ldr r%d [pc #%d]\n"
8021 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8022 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8023 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8024 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8025 /* The assembler calculates the required value of the offset from the
8026 Align(PC,4) value of this instruction to the label. */
8027 pc = pc & 0xfffffffc;
8029 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8030 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8033 dsc->u.ldst.xfersize = 4;
8035 dsc->u.ldst.immed = 0;
8036 dsc->u.ldst.writeback = 0;
8037 dsc->u.ldst.restore_r4 = 0;
8039 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8041 dsc->cleanup = &cleanup_load;
8046 /* Copy Thumb cbnz/cbz insruction. */
8049 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
8050 struct regcache *regs,
8051 struct displaced_step_closure *dsc)
8053 int non_zero = bit (insn1, 11);
8054 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
8055 CORE_ADDR from = dsc->insn_addr;
8056 int rn = bits (insn1, 0, 2);
8057 int rn_val = displaced_read_reg (regs, dsc, rn);
8059 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8060 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8061 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8062 condition is false, let it be, cleanup_branch will do nothing. */
8063 if (dsc->u.branch.cond)
8065 dsc->u.branch.cond = INST_AL;
8066 dsc->u.branch.dest = from + 4 + imm5;
8069 dsc->u.branch.dest = from + 2;
8071 dsc->u.branch.link = 0;
8072 dsc->u.branch.exchange = 0;
8074 if (debug_displaced)
8075 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
8076 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
8077 rn, rn_val, insn1, dsc->u.branch.dest);
8079 dsc->modinsn[0] = THUMB_NOP;
8081 dsc->cleanup = &cleanup_branch;
8085 /* Copy Table Branch Byte/Halfword */
8087 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
8088 uint16_t insn2, struct regcache *regs,
8089 struct displaced_step_closure *dsc)
8091 ULONGEST rn_val, rm_val;
8092 int is_tbh = bit (insn2, 4);
8093 CORE_ADDR halfwords = 0;
8094 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8096 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8097 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8103 target_read_memory (rn_val + 2 * rm_val, buf, 2);
8104 halfwords = extract_unsigned_integer (buf, 2, byte_order);
8110 target_read_memory (rn_val + rm_val, buf, 1);
8111 halfwords = extract_unsigned_integer (buf, 1, byte_order);
8114 if (debug_displaced)
8115 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
8116 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
8117 (unsigned int) rn_val, (unsigned int) rm_val,
8118 (unsigned int) halfwords);
8120 dsc->u.branch.cond = INST_AL;
8121 dsc->u.branch.link = 0;
8122 dsc->u.branch.exchange = 0;
8123 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8125 dsc->cleanup = &cleanup_branch;
8131 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8132 struct displaced_step_closure *dsc)
8135 int val = displaced_read_reg (regs, dsc, 7);
8136 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8139 val = displaced_read_reg (regs, dsc, 8);
8140 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8143 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8148 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8149 struct regcache *regs,
8150 struct displaced_step_closure *dsc)
8152 dsc->u.block.regmask = insn1 & 0x00ff;
8154 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8157 (1) register list is full, that is, r0-r7 are used.
8158 Prepare: tmp[0] <- r8
8160 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8161 MOV r8, r7; Move value of r7 to r8;
8162 POP {r7}; Store PC value into r7.
8164 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8166 (2) register list is not full, supposing there are N registers in
8167 register list (except PC, 0 <= N <= 7).
8168 Prepare: for each i, 0 - N, tmp[i] <- ri.
8170 POP {r0, r1, ...., rN};
8172 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8173 from tmp[] properly.
8175 if (debug_displaced)
8176 fprintf_unfiltered (gdb_stdlog,
8177 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8178 dsc->u.block.regmask, insn1);
8180 if (dsc->u.block.regmask == 0xff)
8182 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8184 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8185 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8186 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8189 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8193 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8194 unsigned int new_regmask, bit = 1;
8195 unsigned int to = 0, from = 0, i, new_rn;
8197 for (i = 0; i < num_in_list + 1; i++)
8198 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8200 new_regmask = (1 << (num_in_list + 1)) - 1;
8202 if (debug_displaced)
8203 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8204 "{..., pc}: original reg list %.4x,"
8205 " modified list %.4x\n"),
8206 (int) dsc->u.block.regmask, new_regmask);
8208 dsc->u.block.regmask |= 0x8000;
8209 dsc->u.block.writeback = 0;
8210 dsc->u.block.cond = INST_AL;
8212 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8214 dsc->cleanup = &cleanup_block_load_pc;
8221 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8222 struct regcache *regs,
8223 struct displaced_step_closure *dsc)
8225 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8226 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8229 /* 16-bit thumb instructions. */
8230 switch (op_bit_12_15)
8232 /* Shift (imme), add, subtract, move and compare. */
8233 case 0: case 1: case 2: case 3:
8234 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8235 "shift/add/sub/mov/cmp",
8239 switch (op_bit_10_11)
8241 case 0: /* Data-processing */
8242 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8246 case 1: /* Special data instructions and branch and exchange. */
8248 unsigned short op = bits (insn1, 7, 9);
8249 if (op == 6 || op == 7) /* BX or BLX */
8250 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8251 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8252 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8254 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8258 default: /* LDR (literal) */
8259 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8262 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8263 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8266 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8267 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8268 else /* Generate SP-relative address */
8269 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8271 case 11: /* Misc 16-bit instructions */
8273 switch (bits (insn1, 8, 11))
8275 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8276 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8278 case 12: case 13: /* POP */
8279 if (bit (insn1, 8)) /* PC is in register list. */
8280 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8282 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8284 case 15: /* If-Then, and hints */
8285 if (bits (insn1, 0, 3))
8286 /* If-Then makes up to four following instructions conditional.
8287 IT instruction itself is not conditional, so handle it as a
8288 common unmodified instruction. */
8289 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8292 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8295 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8300 if (op_bit_10_11 < 2) /* Store multiple registers */
8301 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8302 else /* Load multiple registers */
8303 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8305 case 13: /* Conditional branch and supervisor call */
8306 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8307 err = thumb_copy_b (gdbarch, insn1, dsc);
8309 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8311 case 14: /* Unconditional branch */
8312 err = thumb_copy_b (gdbarch, insn1, dsc);
8319 internal_error (__FILE__, __LINE__,
8320 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8324 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8325 uint16_t insn1, uint16_t insn2,
8326 struct regcache *regs,
8327 struct displaced_step_closure *dsc)
8329 int rt = bits (insn2, 12, 15);
8330 int rn = bits (insn1, 0, 3);
8331 int op1 = bits (insn1, 7, 8);
8334 switch (bits (insn1, 5, 6))
8336 case 0: /* Load byte and memory hints */
8337 if (rt == 0xf) /* PLD/PLI */
8340 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8341 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8343 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8348 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8349 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8352 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8353 "ldrb{reg, immediate}/ldrbt",
8358 case 1: /* Load halfword and memory hints. */
8359 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8360 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8361 "pld/unalloc memhint", dsc);
8365 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8368 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8372 case 2: /* Load word */
8374 int insn2_bit_8_11 = bits (insn2, 8, 11);
8377 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8378 else if (op1 == 0x1) /* Encoding T3 */
8379 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8381 else /* op1 == 0x0 */
8383 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8384 /* LDR (immediate) */
8385 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8386 dsc, bit (insn2, 8), 1);
8387 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8388 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8391 /* LDR (register) */
8392 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8398 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8405 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8406 uint16_t insn2, struct regcache *regs,
8407 struct displaced_step_closure *dsc)
8410 unsigned short op = bit (insn2, 15);
8411 unsigned int op1 = bits (insn1, 11, 12);
8417 switch (bits (insn1, 9, 10))
8422 /* Load/store {dual, execlusive}, table branch. */
8423 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8424 && bits (insn2, 5, 7) == 0)
8425 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8428 /* PC is not allowed to use in load/store {dual, exclusive}
8430 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8431 "load/store dual/ex", dsc);
8433 else /* load/store multiple */
8435 switch (bits (insn1, 7, 8))
8437 case 0: case 3: /* SRS, RFE */
8438 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8441 case 1: case 2: /* LDM/STM/PUSH/POP */
8442 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8449 /* Data-processing (shift register). */
8450 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8453 default: /* Coprocessor instructions. */
8454 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8459 case 2: /* op1 = 2 */
8460 if (op) /* Branch and misc control. */
8462 if (bit (insn2, 14) /* BLX/BL */
8463 || bit (insn2, 12) /* Unconditional branch */
8464 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8465 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8467 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8472 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8474 int op = bits (insn1, 4, 8);
8475 int rn = bits (insn1, 0, 3);
8476 if ((op == 0 || op == 0xa) && rn == 0xf)
8477 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8480 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8483 else /* Data processing (modified immeidate) */
8484 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8488 case 3: /* op1 = 3 */
8489 switch (bits (insn1, 9, 10))
8493 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8495 else /* NEON Load/Store and Store single data item */
8496 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8497 "neon elt/struct load/store",
8500 case 1: /* op1 = 3, bits (9, 10) == 1 */
8501 switch (bits (insn1, 7, 8))
8503 case 0: case 1: /* Data processing (register) */
8504 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8507 case 2: /* Multiply and absolute difference */
8508 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8509 "mul/mua/diff", dsc);
8511 case 3: /* Long multiply and divide */
8512 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8517 default: /* Coprocessor instructions */
8518 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8527 internal_error (__FILE__, __LINE__,
8528 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8533 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8534 CORE_ADDR to, struct regcache *regs,
8535 struct displaced_step_closure *dsc)
8537 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8539 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8541 if (debug_displaced)
8542 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8543 "at %.8lx\n", insn1, (unsigned long) from);
8546 dsc->insn_size = thumb_insn_size (insn1);
8547 if (thumb_insn_size (insn1) == 4)
8550 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8551 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8554 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8558 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8559 CORE_ADDR to, struct regcache *regs,
8560 struct displaced_step_closure *dsc)
8563 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8566 /* Most displaced instructions use a 1-instruction scratch space, so set this
8567 here and override below if/when necessary. */
8569 dsc->insn_addr = from;
8570 dsc->scratch_base = to;
8571 dsc->cleanup = NULL;
8572 dsc->wrote_to_pc = 0;
8574 if (!displaced_in_arm_mode (regs))
8575 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8579 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8580 if (debug_displaced)
8581 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8582 "at %.8lx\n", (unsigned long) insn,
8583 (unsigned long) from);
8585 if ((insn & 0xf0000000) == 0xf0000000)
8586 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8587 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8589 case 0x0: case 0x1: case 0x2: case 0x3:
8590 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8593 case 0x4: case 0x5: case 0x6:
8594 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8598 err = arm_decode_media (gdbarch, insn, dsc);
8601 case 0x8: case 0x9: case 0xa: case 0xb:
8602 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8605 case 0xc: case 0xd: case 0xe: case 0xf:
8606 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8611 internal_error (__FILE__, __LINE__,
8612 _("arm_process_displaced_insn: Instruction decode error"));
8615 /* Actually set up the scratch space for a displaced instruction. */
8618 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8619 CORE_ADDR to, struct displaced_step_closure *dsc)
8621 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8622 unsigned int i, len, offset;
8623 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8624 int size = dsc->is_thumb? 2 : 4;
8625 const unsigned char *bkp_insn;
8628 /* Poke modified instruction(s). */
8629 for (i = 0; i < dsc->numinsns; i++)
8631 if (debug_displaced)
8633 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8635 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8638 fprintf_unfiltered (gdb_stdlog, "%.4x",
8639 (unsigned short)dsc->modinsn[i]);
8641 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8642 (unsigned long) to + offset);
8645 write_memory_unsigned_integer (to + offset, size,
8646 byte_order_for_code,
8651 /* Choose the correct breakpoint instruction. */
8654 bkp_insn = tdep->thumb_breakpoint;
8655 len = tdep->thumb_breakpoint_size;
8659 bkp_insn = tdep->arm_breakpoint;
8660 len = tdep->arm_breakpoint_size;
8663 /* Put breakpoint afterwards. */
8664 write_memory (to + offset, bkp_insn, len);
8666 if (debug_displaced)
8667 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8668 paddress (gdbarch, from), paddress (gdbarch, to));
8671 /* Entry point for copying an instruction into scratch space for displaced
8674 struct displaced_step_closure *
8675 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8676 CORE_ADDR from, CORE_ADDR to,
8677 struct regcache *regs)
8679 struct displaced_step_closure *dsc
8680 = xmalloc (sizeof (struct displaced_step_closure));
8681 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8682 arm_displaced_init_closure (gdbarch, from, to, dsc);
8687 /* Entry point for cleaning things up after a displaced instruction has been
8691 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8692 struct displaced_step_closure *dsc,
8693 CORE_ADDR from, CORE_ADDR to,
8694 struct regcache *regs)
8697 dsc->cleanup (gdbarch, regs, dsc);
8699 if (!dsc->wrote_to_pc)
8700 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8701 dsc->insn_addr + dsc->insn_size);
8705 #include "bfd-in2.h"
8706 #include "libcoff.h"
8709 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8711 struct gdbarch *gdbarch = info->application_data;
8713 if (arm_pc_is_thumb (gdbarch, memaddr))
8715 static asymbol *asym;
8716 static combined_entry_type ce;
8717 static struct coff_symbol_struct csym;
8718 static struct bfd fake_bfd;
8719 static bfd_target fake_target;
8721 if (csym.native == NULL)
8723 /* Create a fake symbol vector containing a Thumb symbol.
8724 This is solely so that the code in print_insn_little_arm()
8725 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8726 the presence of a Thumb symbol and switch to decoding
8727 Thumb instructions. */
8729 fake_target.flavour = bfd_target_coff_flavour;
8730 fake_bfd.xvec = &fake_target;
8731 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8733 csym.symbol.the_bfd = &fake_bfd;
8734 csym.symbol.name = "fake";
8735 asym = (asymbol *) & csym;
8738 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8739 info->symbols = &asym;
8742 info->symbols = NULL;
8744 if (info->endian == BFD_ENDIAN_BIG)
8745 return print_insn_big_arm (memaddr, info);
8747 return print_insn_little_arm (memaddr, info);
8750 /* The following define instruction sequences that will cause ARM
8751 cpu's to take an undefined instruction trap. These are used to
8752 signal a breakpoint to GDB.
8754 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8755 modes. A different instruction is required for each mode. The ARM
8756 cpu's can also be big or little endian. Thus four different
8757 instructions are needed to support all cases.
8759 Note: ARMv4 defines several new instructions that will take the
8760 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8761 not in fact add the new instructions. The new undefined
8762 instructions in ARMv4 are all instructions that had no defined
8763 behaviour in earlier chips. There is no guarantee that they will
8764 raise an exception, but may be treated as NOP's. In practice, it
8765 may only safe to rely on instructions matching:
8767 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8768 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8769 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8771 Even this may only true if the condition predicate is true. The
8772 following use a condition predicate of ALWAYS so it is always TRUE.
8774 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8775 and NetBSD all use a software interrupt rather than an undefined
8776 instruction to force a trap. This can be handled by by the
8777 abi-specific code during establishment of the gdbarch vector. */
8779 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8780 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8781 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8782 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8784 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8785 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8786 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8787 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8789 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8790 the program counter value to determine whether a 16-bit or 32-bit
8791 breakpoint should be used. It returns a pointer to a string of
8792 bytes that encode a breakpoint instruction, stores the length of
8793 the string to *lenptr, and adjusts the program counter (if
8794 necessary) to point to the actual memory location where the
8795 breakpoint should be inserted. */
8797 static const unsigned char *
8798 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8800 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8801 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8803 if (arm_pc_is_thumb (gdbarch, *pcptr))
8805 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8807 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8808 check whether we are replacing a 32-bit instruction. */
8809 if (tdep->thumb2_breakpoint != NULL)
8812 if (target_read_memory (*pcptr, buf, 2) == 0)
8814 unsigned short inst1;
8815 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8816 if (thumb_insn_size (inst1) == 4)
8818 *lenptr = tdep->thumb2_breakpoint_size;
8819 return tdep->thumb2_breakpoint;
8824 *lenptr = tdep->thumb_breakpoint_size;
8825 return tdep->thumb_breakpoint;
8829 *lenptr = tdep->arm_breakpoint_size;
8830 return tdep->arm_breakpoint;
8835 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8838 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8840 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8841 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8842 that this is not confused with a 32-bit ARM breakpoint. */
8846 /* Extract from an array REGBUF containing the (raw) register state a
8847 function return value of type TYPE, and copy that, in virtual
8848 format, into VALBUF. */
8851 arm_extract_return_value (struct type *type, struct regcache *regs,
8854 struct gdbarch *gdbarch = get_regcache_arch (regs);
8855 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8857 if (TYPE_CODE_FLT == TYPE_CODE (type))
8859 switch (gdbarch_tdep (gdbarch)->fp_model)
8863 /* The value is in register F0 in internal format. We need to
8864 extract the raw value and then convert it to the desired
8866 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8868 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8869 convert_from_extended (floatformat_from_type (type), tmpbuf,
8870 valbuf, gdbarch_byte_order (gdbarch));
8874 case ARM_FLOAT_SOFT_FPA:
8875 case ARM_FLOAT_SOFT_VFP:
8876 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8877 not using the VFP ABI code. */
8879 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8880 if (TYPE_LENGTH (type) > 4)
8881 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8882 valbuf + INT_REGISTER_SIZE);
8886 internal_error (__FILE__, __LINE__,
8887 _("arm_extract_return_value: "
8888 "Floating point model not supported"));
8892 else if (TYPE_CODE (type) == TYPE_CODE_INT
8893 || TYPE_CODE (type) == TYPE_CODE_CHAR
8894 || TYPE_CODE (type) == TYPE_CODE_BOOL
8895 || TYPE_CODE (type) == TYPE_CODE_PTR
8896 || TYPE_CODE (type) == TYPE_CODE_REF
8897 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8899 /* If the type is a plain integer, then the access is
8900 straight-forward. Otherwise we have to play around a bit
8902 int len = TYPE_LENGTH (type);
8903 int regno = ARM_A1_REGNUM;
8908 /* By using store_unsigned_integer we avoid having to do
8909 anything special for small big-endian values. */
8910 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8911 store_unsigned_integer (valbuf,
8912 (len > INT_REGISTER_SIZE
8913 ? INT_REGISTER_SIZE : len),
8915 len -= INT_REGISTER_SIZE;
8916 valbuf += INT_REGISTER_SIZE;
8921 /* For a structure or union the behaviour is as if the value had
8922 been stored to word-aligned memory and then loaded into
8923 registers with 32-bit load instruction(s). */
8924 int len = TYPE_LENGTH (type);
8925 int regno = ARM_A1_REGNUM;
8926 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8930 regcache_cooked_read (regs, regno++, tmpbuf);
8931 memcpy (valbuf, tmpbuf,
8932 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8933 len -= INT_REGISTER_SIZE;
8934 valbuf += INT_REGISTER_SIZE;
8940 /* Will a function return an aggregate type in memory or in a
8941 register? Return 0 if an aggregate type can be returned in a
8942 register, 1 if it must be returned in memory. */
8945 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8948 enum type_code code;
8950 CHECK_TYPEDEF (type);
8952 /* In the ARM ABI, "integer" like aggregate types are returned in
8953 registers. For an aggregate type to be integer like, its size
8954 must be less than or equal to INT_REGISTER_SIZE and the
8955 offset of each addressable subfield must be zero. Note that bit
8956 fields are not addressable, and all addressable subfields of
8957 unions always start at offset zero.
8959 This function is based on the behaviour of GCC 2.95.1.
8960 See: gcc/arm.c: arm_return_in_memory() for details.
8962 Note: All versions of GCC before GCC 2.95.2 do not set up the
8963 parameters correctly for a function returning the following
8964 structure: struct { float f;}; This should be returned in memory,
8965 not a register. Richard Earnshaw sent me a patch, but I do not
8966 know of any way to detect if a function like the above has been
8967 compiled with the correct calling convention. */
8969 /* All aggregate types that won't fit in a register must be returned
8971 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8976 /* The AAPCS says all aggregates not larger than a word are returned
8978 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8981 /* The only aggregate types that can be returned in a register are
8982 structs and unions. Arrays must be returned in memory. */
8983 code = TYPE_CODE (type);
8984 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
8989 /* Assume all other aggregate types can be returned in a register.
8990 Run a check for structures, unions and arrays. */
8993 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8996 /* Need to check if this struct/union is "integer" like. For
8997 this to be true, its size must be less than or equal to
8998 INT_REGISTER_SIZE and the offset of each addressable
8999 subfield must be zero. Note that bit fields are not
9000 addressable, and unions always start at offset zero. If any
9001 of the subfields is a floating point type, the struct/union
9002 cannot be an integer type. */
9004 /* For each field in the object, check:
9005 1) Is it FP? --> yes, nRc = 1;
9006 2) Is it addressable (bitpos != 0) and
9007 not packed (bitsize == 0)?
9011 for (i = 0; i < TYPE_NFIELDS (type); i++)
9013 enum type_code field_type_code;
9014 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
9017 /* Is it a floating point type field? */
9018 if (field_type_code == TYPE_CODE_FLT)
9024 /* If bitpos != 0, then we have to care about it. */
9025 if (TYPE_FIELD_BITPOS (type, i) != 0)
9027 /* Bitfields are not addressable. If the field bitsize is
9028 zero, then the field is not packed. Hence it cannot be
9029 a bitfield or any other packed type. */
9030 if (TYPE_FIELD_BITSIZE (type, i) == 0)
9042 /* Write into appropriate registers a function return value of type
9043 TYPE, given in virtual format. */
9046 arm_store_return_value (struct type *type, struct regcache *regs,
9047 const gdb_byte *valbuf)
9049 struct gdbarch *gdbarch = get_regcache_arch (regs);
9050 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9052 if (TYPE_CODE (type) == TYPE_CODE_FLT)
9054 char buf[MAX_REGISTER_SIZE];
9056 switch (gdbarch_tdep (gdbarch)->fp_model)
9060 convert_to_extended (floatformat_from_type (type), buf, valbuf,
9061 gdbarch_byte_order (gdbarch));
9062 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
9065 case ARM_FLOAT_SOFT_FPA:
9066 case ARM_FLOAT_SOFT_VFP:
9067 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9068 not using the VFP ABI code. */
9070 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
9071 if (TYPE_LENGTH (type) > 4)
9072 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
9073 valbuf + INT_REGISTER_SIZE);
9077 internal_error (__FILE__, __LINE__,
9078 _("arm_store_return_value: Floating "
9079 "point model not supported"));
9083 else if (TYPE_CODE (type) == TYPE_CODE_INT
9084 || TYPE_CODE (type) == TYPE_CODE_CHAR
9085 || TYPE_CODE (type) == TYPE_CODE_BOOL
9086 || TYPE_CODE (type) == TYPE_CODE_PTR
9087 || TYPE_CODE (type) == TYPE_CODE_REF
9088 || TYPE_CODE (type) == TYPE_CODE_ENUM)
9090 if (TYPE_LENGTH (type) <= 4)
9092 /* Values of one word or less are zero/sign-extended and
9094 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9095 LONGEST val = unpack_long (type, valbuf);
9097 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
9098 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
9102 /* Integral values greater than one word are stored in consecutive
9103 registers starting with r0. This will always be a multiple of
9104 the regiser size. */
9105 int len = TYPE_LENGTH (type);
9106 int regno = ARM_A1_REGNUM;
9110 regcache_cooked_write (regs, regno++, valbuf);
9111 len -= INT_REGISTER_SIZE;
9112 valbuf += INT_REGISTER_SIZE;
9118 /* For a structure or union the behaviour is as if the value had
9119 been stored to word-aligned memory and then loaded into
9120 registers with 32-bit load instruction(s). */
9121 int len = TYPE_LENGTH (type);
9122 int regno = ARM_A1_REGNUM;
9123 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9127 memcpy (tmpbuf, valbuf,
9128 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9129 regcache_cooked_write (regs, regno++, tmpbuf);
9130 len -= INT_REGISTER_SIZE;
9131 valbuf += INT_REGISTER_SIZE;
9137 /* Handle function return values. */
9139 static enum return_value_convention
9140 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9141 struct type *valtype, struct regcache *regcache,
9142 gdb_byte *readbuf, const gdb_byte *writebuf)
9144 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9145 struct type *func_type = function ? value_type (function) : NULL;
9146 enum arm_vfp_cprc_base_type vfp_base_type;
9149 if (arm_vfp_abi_for_function (gdbarch, func_type)
9150 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9152 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9153 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9155 for (i = 0; i < vfp_base_count; i++)
9157 if (reg_char == 'q')
9160 arm_neon_quad_write (gdbarch, regcache, i,
9161 writebuf + i * unit_length);
9164 arm_neon_quad_read (gdbarch, regcache, i,
9165 readbuf + i * unit_length);
9172 sprintf (name_buf, "%c%d", reg_char, i);
9173 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9176 regcache_cooked_write (regcache, regnum,
9177 writebuf + i * unit_length);
9179 regcache_cooked_read (regcache, regnum,
9180 readbuf + i * unit_length);
9183 return RETURN_VALUE_REGISTER_CONVENTION;
9186 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9187 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9188 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9190 if (tdep->struct_return == pcc_struct_return
9191 || arm_return_in_memory (gdbarch, valtype))
9192 return RETURN_VALUE_STRUCT_CONVENTION;
9195 /* AAPCS returns complex types longer than a register in memory. */
9196 if (tdep->arm_abi != ARM_ABI_APCS
9197 && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
9198 && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE)
9199 return RETURN_VALUE_STRUCT_CONVENTION;
9202 arm_store_return_value (valtype, regcache, writebuf);
9205 arm_extract_return_value (valtype, regcache, readbuf);
9207 return RETURN_VALUE_REGISTER_CONVENTION;
9212 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9214 struct gdbarch *gdbarch = get_frame_arch (frame);
9215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9216 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9218 char buf[INT_REGISTER_SIZE];
9220 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9222 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9226 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9230 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9231 return the target PC. Otherwise return 0. */
9234 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9238 CORE_ADDR start_addr;
9240 /* Find the starting address and name of the function containing the PC. */
9241 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9244 /* If PC is in a Thumb call or return stub, return the address of the
9245 target PC, which is in a register. The thunk functions are called
9246 _call_via_xx, where x is the register name. The possible names
9247 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9248 functions, named __ARM_call_via_r[0-7]. */
9249 if (strncmp (name, "_call_via_", 10) == 0
9250 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9252 /* Use the name suffix to determine which register contains the
9254 static char *table[15] =
9255 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9256 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9259 int offset = strlen (name) - 2;
9261 for (regno = 0; regno <= 14; regno++)
9262 if (strcmp (&name[offset], table[regno]) == 0)
9263 return get_frame_register_unsigned (frame, regno);
9266 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9267 non-interworking calls to foo. We could decode the stubs
9268 to find the target but it's easier to use the symbol table. */
9269 namelen = strlen (name);
9270 if (name[0] == '_' && name[1] == '_'
9271 && ((namelen > 2 + strlen ("_from_thumb")
9272 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
9273 strlen ("_from_thumb")) == 0)
9274 || (namelen > 2 + strlen ("_from_arm")
9275 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
9276 strlen ("_from_arm")) == 0)))
9279 int target_len = namelen - 2;
9280 struct minimal_symbol *minsym;
9281 struct objfile *objfile;
9282 struct obj_section *sec;
9284 if (name[namelen - 1] == 'b')
9285 target_len -= strlen ("_from_thumb");
9287 target_len -= strlen ("_from_arm");
9289 target_name = alloca (target_len + 1);
9290 memcpy (target_name, name + 2, target_len);
9291 target_name[target_len] = '\0';
9293 sec = find_pc_section (pc);
9294 objfile = (sec == NULL) ? NULL : sec->objfile;
9295 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9297 return SYMBOL_VALUE_ADDRESS (minsym);
9302 return 0; /* not a stub */
9306 set_arm_command (char *args, int from_tty)
9308 printf_unfiltered (_("\
9309 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9310 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9314 show_arm_command (char *args, int from_tty)
9316 cmd_show_list (showarmcmdlist, from_tty, "");
9320 arm_update_current_architecture (void)
9322 struct gdbarch_info info;
9324 /* If the current architecture is not ARM, we have nothing to do. */
9325 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
9328 /* Update the architecture. */
9329 gdbarch_info_init (&info);
9331 if (!gdbarch_update_p (info))
9332 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9336 set_fp_model_sfunc (char *args, int from_tty,
9337 struct cmd_list_element *c)
9339 enum arm_float_model fp_model;
9341 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9342 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9344 arm_fp_model = fp_model;
9348 if (fp_model == ARM_FLOAT_LAST)
9349 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9352 arm_update_current_architecture ();
9356 show_fp_model (struct ui_file *file, int from_tty,
9357 struct cmd_list_element *c, const char *value)
9359 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9361 if (arm_fp_model == ARM_FLOAT_AUTO
9362 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9363 fprintf_filtered (file, _("\
9364 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9365 fp_model_strings[tdep->fp_model]);
9367 fprintf_filtered (file, _("\
9368 The current ARM floating point model is \"%s\".\n"),
9369 fp_model_strings[arm_fp_model]);
9373 arm_set_abi (char *args, int from_tty,
9374 struct cmd_list_element *c)
9376 enum arm_abi_kind arm_abi;
9378 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9379 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9381 arm_abi_global = arm_abi;
9385 if (arm_abi == ARM_ABI_LAST)
9386 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9389 arm_update_current_architecture ();
9393 arm_show_abi (struct ui_file *file, int from_tty,
9394 struct cmd_list_element *c, const char *value)
9396 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9398 if (arm_abi_global == ARM_ABI_AUTO
9399 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9400 fprintf_filtered (file, _("\
9401 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9402 arm_abi_strings[tdep->arm_abi]);
9404 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9409 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9410 struct cmd_list_element *c, const char *value)
9412 fprintf_filtered (file,
9413 _("The current execution mode assumed "
9414 "(when symbols are unavailable) is \"%s\".\n"),
9415 arm_fallback_mode_string);
9419 arm_show_force_mode (struct ui_file *file, int from_tty,
9420 struct cmd_list_element *c, const char *value)
9422 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9424 fprintf_filtered (file,
9425 _("The current execution mode assumed "
9426 "(even when symbols are available) is \"%s\".\n"),
9427 arm_force_mode_string);
9430 /* If the user changes the register disassembly style used for info
9431 register and other commands, we have to also switch the style used
9432 in opcodes for disassembly output. This function is run in the "set
9433 arm disassembly" command, and does that. */
9436 set_disassembly_style_sfunc (char *args, int from_tty,
9437 struct cmd_list_element *c)
9439 set_disassembly_style ();
9442 /* Return the ARM register name corresponding to register I. */
9444 arm_register_name (struct gdbarch *gdbarch, int i)
9446 const int num_regs = gdbarch_num_regs (gdbarch);
9448 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9449 && i >= num_regs && i < num_regs + 32)
9451 static const char *const vfp_pseudo_names[] = {
9452 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9453 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9454 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9455 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9458 return vfp_pseudo_names[i - num_regs];
9461 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9462 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9464 static const char *const neon_pseudo_names[] = {
9465 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9466 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9469 return neon_pseudo_names[i - num_regs - 32];
9472 if (i >= ARRAY_SIZE (arm_register_names))
9473 /* These registers are only supported on targets which supply
9474 an XML description. */
9477 return arm_register_names[i];
9481 set_disassembly_style (void)
9485 /* Find the style that the user wants. */
9486 for (current = 0; current < num_disassembly_options; current++)
9487 if (disassembly_style == valid_disassembly_styles[current])
9489 gdb_assert (current < num_disassembly_options);
9491 /* Synchronize the disassembler. */
9492 set_arm_regname_option (current);
9495 /* Test whether the coff symbol specific value corresponds to a Thumb
9499 coff_sym_is_thumb (int val)
9501 return (val == C_THUMBEXT
9502 || val == C_THUMBSTAT
9503 || val == C_THUMBEXTFUNC
9504 || val == C_THUMBSTATFUNC
9505 || val == C_THUMBLABEL);
9508 /* arm_coff_make_msymbol_special()
9509 arm_elf_make_msymbol_special()
9511 These functions test whether the COFF or ELF symbol corresponds to
9512 an address in thumb code, and set a "special" bit in a minimal
9513 symbol to indicate that it does. */
9516 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9518 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9519 == ST_BRANCH_TO_THUMB)
9520 MSYMBOL_SET_SPECIAL (msym);
9524 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9526 if (coff_sym_is_thumb (val))
9527 MSYMBOL_SET_SPECIAL (msym);
9531 arm_objfile_data_free (struct objfile *objfile, void *arg)
9533 struct arm_per_objfile *data = arg;
9536 for (i = 0; i < objfile->obfd->section_count; i++)
9537 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9541 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9544 const char *name = bfd_asymbol_name (sym);
9545 struct arm_per_objfile *data;
9546 VEC(arm_mapping_symbol_s) **map_p;
9547 struct arm_mapping_symbol new_map_sym;
9549 gdb_assert (name[0] == '$');
9550 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9553 data = objfile_data (objfile, arm_objfile_data_key);
9556 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9557 struct arm_per_objfile);
9558 set_objfile_data (objfile, arm_objfile_data_key, data);
9559 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9560 objfile->obfd->section_count,
9561 VEC(arm_mapping_symbol_s) *);
9563 map_p = &data->section_maps[bfd_get_section (sym)->index];
9565 new_map_sym.value = sym->value;
9566 new_map_sym.type = name[1];
9568 /* Assume that most mapping symbols appear in order of increasing
9569 value. If they were randomly distributed, it would be faster to
9570 always push here and then sort at first use. */
9571 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9573 struct arm_mapping_symbol *prev_map_sym;
9575 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9576 if (prev_map_sym->value >= sym->value)
9579 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9580 arm_compare_mapping_symbols);
9581 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9586 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9590 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9592 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9593 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9595 /* If necessary, set the T bit. */
9598 ULONGEST val, t_bit;
9599 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9600 t_bit = arm_psr_thumb_bit (gdbarch);
9601 if (arm_pc_is_thumb (gdbarch, pc))
9602 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9605 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9610 /* Read the contents of a NEON quad register, by reading from two
9611 double registers. This is used to implement the quad pseudo
9612 registers, and for argument passing in case the quad registers are
9613 missing; vectors are passed in quad registers when using the VFP
9614 ABI, even if a NEON unit is not present. REGNUM is the index of
9615 the quad register, in [0, 15]. */
9617 static enum register_status
9618 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9619 int regnum, gdb_byte *buf)
9622 gdb_byte reg_buf[8];
9623 int offset, double_regnum;
9624 enum register_status status;
9626 sprintf (name_buf, "d%d", regnum << 1);
9627 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9630 /* d0 is always the least significant half of q0. */
9631 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9636 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9637 if (status != REG_VALID)
9639 memcpy (buf + offset, reg_buf, 8);
9641 offset = 8 - offset;
9642 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9643 if (status != REG_VALID)
9645 memcpy (buf + offset, reg_buf, 8);
9650 static enum register_status
9651 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9652 int regnum, gdb_byte *buf)
9654 const int num_regs = gdbarch_num_regs (gdbarch);
9656 gdb_byte reg_buf[8];
9657 int offset, double_regnum;
9659 gdb_assert (regnum >= num_regs);
9662 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9663 /* Quad-precision register. */
9664 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9667 enum register_status status;
9669 /* Single-precision register. */
9670 gdb_assert (regnum < 32);
9672 /* s0 is always the least significant half of d0. */
9673 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9674 offset = (regnum & 1) ? 0 : 4;
9676 offset = (regnum & 1) ? 4 : 0;
9678 sprintf (name_buf, "d%d", regnum >> 1);
9679 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9682 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9683 if (status == REG_VALID)
9684 memcpy (buf, reg_buf + offset, 4);
9689 /* Store the contents of BUF to a NEON quad register, by writing to
9690 two double registers. This is used to implement the quad pseudo
9691 registers, and for argument passing in case the quad registers are
9692 missing; vectors are passed in quad registers when using the VFP
9693 ABI, even if a NEON unit is not present. REGNUM is the index
9694 of the quad register, in [0, 15]. */
9697 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9698 int regnum, const gdb_byte *buf)
9701 int offset, double_regnum;
9703 sprintf (name_buf, "d%d", regnum << 1);
9704 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9707 /* d0 is always the least significant half of q0. */
9708 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9713 regcache_raw_write (regcache, double_regnum, buf + offset);
9714 offset = 8 - offset;
9715 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9719 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9720 int regnum, const gdb_byte *buf)
9722 const int num_regs = gdbarch_num_regs (gdbarch);
9724 gdb_byte reg_buf[8];
9725 int offset, double_regnum;
9727 gdb_assert (regnum >= num_regs);
9730 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9731 /* Quad-precision register. */
9732 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9735 /* Single-precision register. */
9736 gdb_assert (regnum < 32);
9738 /* s0 is always the least significant half of d0. */
9739 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9740 offset = (regnum & 1) ? 0 : 4;
9742 offset = (regnum & 1) ? 4 : 0;
9744 sprintf (name_buf, "d%d", regnum >> 1);
9745 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9748 regcache_raw_read (regcache, double_regnum, reg_buf);
9749 memcpy (reg_buf + offset, buf, 4);
9750 regcache_raw_write (regcache, double_regnum, reg_buf);
9754 static struct value *
9755 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9757 const int *reg_p = baton;
9758 return value_of_register (*reg_p, frame);
9761 static enum gdb_osabi
9762 arm_elf_osabi_sniffer (bfd *abfd)
9764 unsigned int elfosabi;
9765 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9767 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9769 if (elfosabi == ELFOSABI_ARM)
9770 /* GNU tools use this value. Check note sections in this case,
9772 bfd_map_over_sections (abfd,
9773 generic_elf_osabi_sniff_abi_tag_sections,
9776 /* Anything else will be handled by the generic ELF sniffer. */
9781 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9782 struct reggroup *group)
9784 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9785 this, FPS register belongs to save_regroup, restore_reggroup, and
9786 all_reggroup, of course. */
9787 if (regnum == ARM_FPS_REGNUM)
9788 return (group == float_reggroup
9789 || group == save_reggroup
9790 || group == restore_reggroup
9791 || group == all_reggroup);
9793 return default_register_reggroup_p (gdbarch, regnum, group);
9797 /* For backward-compatibility we allow two 'g' packet lengths with
9798 the remote protocol depending on whether FPA registers are
9799 supplied. M-profile targets do not have FPA registers, but some
9800 stubs already exist in the wild which use a 'g' packet which
9801 supplies them albeit with dummy values. The packet format which
9802 includes FPA registers should be considered deprecated for
9803 M-profile targets. */
9806 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9808 if (gdbarch_tdep (gdbarch)->is_m)
9810 /* If we know from the executable this is an M-profile target,
9811 cater for remote targets whose register set layout is the
9812 same as the FPA layout. */
9813 register_remote_g_packet_guess (gdbarch,
9814 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9815 (16 * INT_REGISTER_SIZE)
9816 + (8 * FP_REGISTER_SIZE)
9817 + (2 * INT_REGISTER_SIZE),
9818 tdesc_arm_with_m_fpa_layout);
9820 /* The regular M-profile layout. */
9821 register_remote_g_packet_guess (gdbarch,
9822 /* r0-r12,sp,lr,pc; xpsr */
9823 (16 * INT_REGISTER_SIZE)
9824 + INT_REGISTER_SIZE,
9827 /* M-profile plus M4F VFP. */
9828 register_remote_g_packet_guess (gdbarch,
9829 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9830 (16 * INT_REGISTER_SIZE)
9831 + (16 * VFP_REGISTER_SIZE)
9832 + (2 * INT_REGISTER_SIZE),
9833 tdesc_arm_with_m_vfp_d16);
9836 /* Otherwise we don't have a useful guess. */
9840 /* Initialize the current architecture based on INFO. If possible,
9841 re-use an architecture from ARCHES, which is a list of
9842 architectures already created during this debugging session.
9844 Called e.g. at program startup, when reading a core file, and when
9845 reading a binary file. */
9847 static struct gdbarch *
9848 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9850 struct gdbarch_tdep *tdep;
9851 struct gdbarch *gdbarch;
9852 struct gdbarch_list *best_arch;
9853 enum arm_abi_kind arm_abi = arm_abi_global;
9854 enum arm_float_model fp_model = arm_fp_model;
9855 struct tdesc_arch_data *tdesc_data = NULL;
9857 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9859 int have_fpa_registers = 1;
9860 const struct target_desc *tdesc = info.target_desc;
9862 /* If we have an object to base this architecture on, try to determine
9865 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9867 int ei_osabi, e_flags;
9869 switch (bfd_get_flavour (info.abfd))
9871 case bfd_target_aout_flavour:
9872 /* Assume it's an old APCS-style ABI. */
9873 arm_abi = ARM_ABI_APCS;
9876 case bfd_target_coff_flavour:
9877 /* Assume it's an old APCS-style ABI. */
9879 arm_abi = ARM_ABI_APCS;
9882 case bfd_target_elf_flavour:
9883 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9884 e_flags = elf_elfheader (info.abfd)->e_flags;
9886 if (ei_osabi == ELFOSABI_ARM)
9888 /* GNU tools used to use this value, but do not for EABI
9889 objects. There's nowhere to tag an EABI version
9890 anyway, so assume APCS. */
9891 arm_abi = ARM_ABI_APCS;
9893 else if (ei_osabi == ELFOSABI_NONE)
9895 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9896 int attr_arch, attr_profile;
9900 case EF_ARM_EABI_UNKNOWN:
9901 /* Assume GNU tools. */
9902 arm_abi = ARM_ABI_APCS;
9905 case EF_ARM_EABI_VER4:
9906 case EF_ARM_EABI_VER5:
9907 arm_abi = ARM_ABI_AAPCS;
9908 /* EABI binaries default to VFP float ordering.
9909 They may also contain build attributes that can
9910 be used to identify if the VFP argument-passing
9912 if (fp_model == ARM_FLOAT_AUTO)
9915 switch (bfd_elf_get_obj_attr_int (info.abfd,
9920 /* "The user intended FP parameter/result
9921 passing to conform to AAPCS, base
9923 fp_model = ARM_FLOAT_SOFT_VFP;
9926 /* "The user intended FP parameter/result
9927 passing to conform to AAPCS, VFP
9929 fp_model = ARM_FLOAT_VFP;
9932 /* "The user intended FP parameter/result
9933 passing to conform to tool chain-specific
9934 conventions" - we don't know any such
9935 conventions, so leave it as "auto". */
9938 /* Attribute value not mentioned in the
9939 October 2008 ABI, so leave it as
9944 fp_model = ARM_FLOAT_SOFT_VFP;
9950 /* Leave it as "auto". */
9951 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9956 /* Detect M-profile programs. This only works if the
9957 executable file includes build attributes; GCC does
9958 copy them to the executable, but e.g. RealView does
9960 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9962 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9964 Tag_CPU_arch_profile);
9965 /* GCC specifies the profile for v6-M; RealView only
9966 specifies the profile for architectures starting with
9967 V7 (as opposed to architectures with a tag
9968 numerically greater than TAG_CPU_ARCH_V7). */
9969 if (!tdesc_has_registers (tdesc)
9970 && (attr_arch == TAG_CPU_ARCH_V6_M
9971 || attr_arch == TAG_CPU_ARCH_V6S_M
9972 || attr_profile == 'M'))
9977 if (fp_model == ARM_FLOAT_AUTO)
9979 int e_flags = elf_elfheader (info.abfd)->e_flags;
9981 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9984 /* Leave it as "auto". Strictly speaking this case
9985 means FPA, but almost nobody uses that now, and
9986 many toolchains fail to set the appropriate bits
9987 for the floating-point model they use. */
9989 case EF_ARM_SOFT_FLOAT:
9990 fp_model = ARM_FLOAT_SOFT_FPA;
9992 case EF_ARM_VFP_FLOAT:
9993 fp_model = ARM_FLOAT_VFP;
9995 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9996 fp_model = ARM_FLOAT_SOFT_VFP;
10001 if (e_flags & EF_ARM_BE8)
10002 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10007 /* Leave it as "auto". */
10012 /* Check any target description for validity. */
10013 if (tdesc_has_registers (tdesc))
10015 /* For most registers we require GDB's default names; but also allow
10016 the numeric names for sp / lr / pc, as a convenience. */
10017 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
10018 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
10019 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
10021 const struct tdesc_feature *feature;
10024 feature = tdesc_find_feature (tdesc,
10025 "org.gnu.gdb.arm.core");
10026 if (feature == NULL)
10028 feature = tdesc_find_feature (tdesc,
10029 "org.gnu.gdb.arm.m-profile");
10030 if (feature == NULL)
10036 tdesc_data = tdesc_data_alloc ();
10039 for (i = 0; i < ARM_SP_REGNUM; i++)
10040 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10041 arm_register_names[i]);
10042 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10045 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10048 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10052 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10053 ARM_PS_REGNUM, "xpsr");
10055 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10056 ARM_PS_REGNUM, "cpsr");
10060 tdesc_data_cleanup (tdesc_data);
10064 feature = tdesc_find_feature (tdesc,
10065 "org.gnu.gdb.arm.fpa");
10066 if (feature != NULL)
10069 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
10070 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10071 arm_register_names[i]);
10074 tdesc_data_cleanup (tdesc_data);
10079 have_fpa_registers = 0;
10081 feature = tdesc_find_feature (tdesc,
10082 "org.gnu.gdb.xscale.iwmmxt");
10083 if (feature != NULL)
10085 static const char *const iwmmxt_names[] = {
10086 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10087 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10088 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10089 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10093 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
10095 &= tdesc_numbered_register (feature, tdesc_data, i,
10096 iwmmxt_names[i - ARM_WR0_REGNUM]);
10098 /* Check for the control registers, but do not fail if they
10100 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
10101 tdesc_numbered_register (feature, tdesc_data, i,
10102 iwmmxt_names[i - ARM_WR0_REGNUM]);
10104 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
10106 &= tdesc_numbered_register (feature, tdesc_data, i,
10107 iwmmxt_names[i - ARM_WR0_REGNUM]);
10111 tdesc_data_cleanup (tdesc_data);
10116 /* If we have a VFP unit, check whether the single precision registers
10117 are present. If not, then we will synthesize them as pseudo
10119 feature = tdesc_find_feature (tdesc,
10120 "org.gnu.gdb.arm.vfp");
10121 if (feature != NULL)
10123 static const char *const vfp_double_names[] = {
10124 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10125 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10126 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10127 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10130 /* Require the double precision registers. There must be either
10133 for (i = 0; i < 32; i++)
10135 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10137 vfp_double_names[i]);
10141 if (!valid_p && i == 16)
10144 /* Also require FPSCR. */
10145 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10146 ARM_FPSCR_REGNUM, "fpscr");
10149 tdesc_data_cleanup (tdesc_data);
10153 if (tdesc_unnumbered_register (feature, "s0") == 0)
10154 have_vfp_pseudos = 1;
10156 have_vfp_registers = 1;
10158 /* If we have VFP, also check for NEON. The architecture allows
10159 NEON without VFP (integer vector operations only), but GDB
10160 does not support that. */
10161 feature = tdesc_find_feature (tdesc,
10162 "org.gnu.gdb.arm.neon");
10163 if (feature != NULL)
10165 /* NEON requires 32 double-precision registers. */
10168 tdesc_data_cleanup (tdesc_data);
10172 /* If there are quad registers defined by the stub, use
10173 their type; otherwise (normally) provide them with
10174 the default type. */
10175 if (tdesc_unnumbered_register (feature, "q0") == 0)
10176 have_neon_pseudos = 1;
10183 /* If there is already a candidate, use it. */
10184 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10186 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10188 if (arm_abi != ARM_ABI_AUTO
10189 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10192 if (fp_model != ARM_FLOAT_AUTO
10193 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10196 /* There are various other properties in tdep that we do not
10197 need to check here: those derived from a target description,
10198 since gdbarches with a different target description are
10199 automatically disqualified. */
10201 /* Do check is_m, though, since it might come from the binary. */
10202 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10205 /* Found a match. */
10209 if (best_arch != NULL)
10211 if (tdesc_data != NULL)
10212 tdesc_data_cleanup (tdesc_data);
10213 return best_arch->gdbarch;
10216 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
10217 gdbarch = gdbarch_alloc (&info, tdep);
10219 /* Record additional information about the architecture we are defining.
10220 These are gdbarch discriminators, like the OSABI. */
10221 tdep->arm_abi = arm_abi;
10222 tdep->fp_model = fp_model;
10224 tdep->have_fpa_registers = have_fpa_registers;
10225 tdep->have_vfp_registers = have_vfp_registers;
10226 tdep->have_vfp_pseudos = have_vfp_pseudos;
10227 tdep->have_neon_pseudos = have_neon_pseudos;
10228 tdep->have_neon = have_neon;
10230 arm_register_g_packet_guesses (gdbarch);
10233 switch (info.byte_order_for_code)
10235 case BFD_ENDIAN_BIG:
10236 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10237 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10238 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10239 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10243 case BFD_ENDIAN_LITTLE:
10244 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10245 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10246 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10247 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10252 internal_error (__FILE__, __LINE__,
10253 _("arm_gdbarch_init: bad byte order for float format"));
10256 /* On ARM targets char defaults to unsigned. */
10257 set_gdbarch_char_signed (gdbarch, 0);
10259 /* Note: for displaced stepping, this includes the breakpoint, and one word
10260 of additional scratch space. This setting isn't used for anything beside
10261 displaced stepping at present. */
10262 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10264 /* This should be low enough for everything. */
10265 tdep->lowest_pc = 0x20;
10266 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10268 /* The default, for both APCS and AAPCS, is to return small
10269 structures in registers. */
10270 tdep->struct_return = reg_struct_return;
10272 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10273 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10275 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10277 /* Frame handling. */
10278 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10279 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10280 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10282 frame_base_set_default (gdbarch, &arm_normal_base);
10284 /* Address manipulation. */
10285 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
10286 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10288 /* Advance PC across function entry code. */
10289 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10291 /* Detect whether PC is in function epilogue. */
10292 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
10294 /* Skip trampolines. */
10295 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10297 /* The stack grows downward. */
10298 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10300 /* Breakpoint manipulation. */
10301 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10302 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10303 arm_remote_breakpoint_from_pc);
10305 /* Information about registers, etc. */
10306 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10307 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10308 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10309 set_gdbarch_register_type (gdbarch, arm_register_type);
10310 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10312 /* This "info float" is FPA-specific. Use the generic version if we
10313 do not have FPA. */
10314 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10315 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10317 /* Internal <-> external register number maps. */
10318 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10319 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10321 set_gdbarch_register_name (gdbarch, arm_register_name);
10323 /* Returning results. */
10324 set_gdbarch_return_value (gdbarch, arm_return_value);
10327 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10329 /* Minsymbol frobbing. */
10330 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10331 set_gdbarch_coff_make_msymbol_special (gdbarch,
10332 arm_coff_make_msymbol_special);
10333 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10335 /* Thumb-2 IT block support. */
10336 set_gdbarch_adjust_breakpoint_address (gdbarch,
10337 arm_adjust_breakpoint_address);
10339 /* Virtual tables. */
10340 set_gdbarch_vbit_in_delta (gdbarch, 1);
10342 /* Hook in the ABI-specific overrides, if they have been registered. */
10343 gdbarch_init_osabi (info, gdbarch);
10345 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10347 /* Add some default predicates. */
10349 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
10350 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10351 dwarf2_append_unwinders (gdbarch);
10352 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10353 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10355 /* Now we have tuned the configuration, set a few final things,
10356 based on what the OS ABI has told us. */
10358 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10359 binaries are always marked. */
10360 if (tdep->arm_abi == ARM_ABI_AUTO)
10361 tdep->arm_abi = ARM_ABI_APCS;
10363 /* Watchpoints are not steppable. */
10364 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10366 /* We used to default to FPA for generic ARM, but almost nobody
10367 uses that now, and we now provide a way for the user to force
10368 the model. So default to the most useful variant. */
10369 if (tdep->fp_model == ARM_FLOAT_AUTO)
10370 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10372 if (tdep->jb_pc >= 0)
10373 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10375 /* Floating point sizes and format. */
10376 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10377 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10379 set_gdbarch_double_format
10380 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10381 set_gdbarch_long_double_format
10382 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10386 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10387 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10390 if (have_vfp_pseudos)
10392 /* NOTE: These are the only pseudo registers used by
10393 the ARM target at the moment. If more are added, a
10394 little more care in numbering will be needed. */
10396 int num_pseudos = 32;
10397 if (have_neon_pseudos)
10399 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10400 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10401 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10406 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10408 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10410 /* Override tdesc_register_type to adjust the types of VFP
10411 registers for NEON. */
10412 set_gdbarch_register_type (gdbarch, arm_register_type);
10415 /* Add standard register aliases. We add aliases even for those
10416 nanes which are used by the current architecture - it's simpler,
10417 and does no harm, since nothing ever lists user registers. */
10418 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10419 user_reg_add (gdbarch, arm_register_aliases[i].name,
10420 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10426 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10433 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10434 (unsigned long) tdep->lowest_pc);
10437 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10440 _initialize_arm_tdep (void)
10442 struct ui_file *stb;
10444 struct cmd_list_element *new_set, *new_show;
10445 const char *setname;
10446 const char *setdesc;
10447 const char *const *regnames;
10449 static char *helptext;
10450 char regdesc[1024], *rdptr = regdesc;
10451 size_t rest = sizeof (regdesc);
10453 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10455 arm_objfile_data_key
10456 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10458 /* Add ourselves to objfile event chain. */
10459 observer_attach_new_objfile (arm_exidx_new_objfile);
10461 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10463 /* Register an ELF OS ABI sniffer for ARM binaries. */
10464 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10465 bfd_target_elf_flavour,
10466 arm_elf_osabi_sniffer);
10468 /* Initialize the standard target descriptions. */
10469 initialize_tdesc_arm_with_m ();
10470 initialize_tdesc_arm_with_m_fpa_layout ();
10471 initialize_tdesc_arm_with_m_vfp_d16 ();
10472 initialize_tdesc_arm_with_iwmmxt ();
10473 initialize_tdesc_arm_with_vfpv2 ();
10474 initialize_tdesc_arm_with_vfpv3 ();
10475 initialize_tdesc_arm_with_neon ();
10477 /* Get the number of possible sets of register names defined in opcodes. */
10478 num_disassembly_options = get_arm_regname_num_options ();
10480 /* Add root prefix command for all "set arm"/"show arm" commands. */
10481 add_prefix_cmd ("arm", no_class, set_arm_command,
10482 _("Various ARM-specific commands."),
10483 &setarmcmdlist, "set arm ", 0, &setlist);
10485 add_prefix_cmd ("arm", no_class, show_arm_command,
10486 _("Various ARM-specific commands."),
10487 &showarmcmdlist, "show arm ", 0, &showlist);
10489 /* Sync the opcode insn printer with our register viewer. */
10490 parse_arm_disassembler_option ("reg-names-std");
10492 /* Initialize the array that will be passed to
10493 add_setshow_enum_cmd(). */
10494 valid_disassembly_styles
10495 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10496 for (i = 0; i < num_disassembly_options; i++)
10498 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10499 valid_disassembly_styles[i] = setname;
10500 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10503 /* When we find the default names, tell the disassembler to use
10505 if (!strcmp (setname, "std"))
10507 disassembly_style = setname;
10508 set_arm_regname_option (i);
10511 /* Mark the end of valid options. */
10512 valid_disassembly_styles[num_disassembly_options] = NULL;
10514 /* Create the help text. */
10515 stb = mem_fileopen ();
10516 fprintf_unfiltered (stb, "%s%s%s",
10517 _("The valid values are:\n"),
10519 _("The default is \"std\"."));
10520 helptext = ui_file_xstrdup (stb, NULL);
10521 ui_file_delete (stb);
10523 add_setshow_enum_cmd("disassembler", no_class,
10524 valid_disassembly_styles, &disassembly_style,
10525 _("Set the disassembly style."),
10526 _("Show the disassembly style."),
10528 set_disassembly_style_sfunc,
10529 NULL, /* FIXME: i18n: The disassembly style is
10531 &setarmcmdlist, &showarmcmdlist);
10533 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10534 _("Set usage of ARM 32-bit mode."),
10535 _("Show usage of ARM 32-bit mode."),
10536 _("When off, a 26-bit PC will be used."),
10538 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10540 &setarmcmdlist, &showarmcmdlist);
10542 /* Add a command to allow the user to force the FPU model. */
10543 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10544 _("Set the floating point type."),
10545 _("Show the floating point type."),
10546 _("auto - Determine the FP typefrom the OS-ABI.\n\
10547 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10548 fpa - FPA co-processor (GCC compiled).\n\
10549 softvfp - Software FP with pure-endian doubles.\n\
10550 vfp - VFP co-processor."),
10551 set_fp_model_sfunc, show_fp_model,
10552 &setarmcmdlist, &showarmcmdlist);
10554 /* Add a command to allow the user to force the ABI. */
10555 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10557 _("Show the ABI."),
10558 NULL, arm_set_abi, arm_show_abi,
10559 &setarmcmdlist, &showarmcmdlist);
10561 /* Add two commands to allow the user to force the assumed
10563 add_setshow_enum_cmd ("fallback-mode", class_support,
10564 arm_mode_strings, &arm_fallback_mode_string,
10565 _("Set the mode assumed when symbols are unavailable."),
10566 _("Show the mode assumed when symbols are unavailable."),
10567 NULL, NULL, arm_show_fallback_mode,
10568 &setarmcmdlist, &showarmcmdlist);
10569 add_setshow_enum_cmd ("force-mode", class_support,
10570 arm_mode_strings, &arm_force_mode_string,
10571 _("Set the mode assumed even when symbols are available."),
10572 _("Show the mode assumed even when symbols are available."),
10573 NULL, NULL, arm_show_force_mode,
10574 &setarmcmdlist, &showarmcmdlist);
10576 /* Debugging flag. */
10577 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10578 _("Set ARM debugging."),
10579 _("Show ARM debugging."),
10580 _("When on, arm-specific debugging is enabled."),
10582 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10583 &setdebuglist, &showdebuglist);
10586 /* ARM-reversible process record data structures. */
10588 #define ARM_INSN_SIZE_BYTES 4
10589 #define THUMB_INSN_SIZE_BYTES 2
10590 #define THUMB2_INSN_SIZE_BYTES 4
10593 #define INSN_S_L_BIT_NUM 20
10595 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10598 unsigned int reg_len = LENGTH; \
10601 REGS = XNEWVEC (uint32_t, reg_len); \
10602 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10607 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10610 unsigned int mem_len = LENGTH; \
10613 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10614 memcpy(&MEMS->len, &RECORD_BUF[0], \
10615 sizeof(struct arm_mem_r) * LENGTH); \
10620 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10621 #define INSN_RECORDED(ARM_RECORD) \
10622 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10624 /* ARM memory record structure. */
10627 uint32_t len; /* Record length. */
10628 CORE_ADDR addr; /* Memory address. */
10631 /* ARM instruction record contains opcode of current insn
10632 and execution state (before entry to decode_insn()),
10633 contains list of to-be-modified registers and
10634 memory blocks (on return from decode_insn()). */
10636 typedef struct insn_decode_record_t
10638 struct gdbarch *gdbarch;
10639 struct regcache *regcache;
10640 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10641 uint32_t arm_insn; /* Should accommodate thumb. */
10642 uint32_t cond; /* Condition code. */
10643 uint32_t opcode; /* Insn opcode. */
10644 uint32_t decode; /* Insn decode bits. */
10645 uint32_t mem_rec_count; /* No of mem records. */
10646 uint32_t reg_rec_count; /* No of reg records. */
10647 uint32_t *arm_regs; /* Registers to be saved for this record. */
10648 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10649 } insn_decode_record;
10652 /* Checks ARM SBZ and SBO mandatory fields. */
10655 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10657 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10680 } arm_record_strx_t;
10691 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10692 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10695 struct regcache *reg_cache = arm_insn_r->regcache;
10696 ULONGEST u_regval[2]= {0};
10698 uint32_t reg_src1 = 0, reg_src2 = 0;
10699 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10700 uint32_t opcode1 = 0;
10702 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10703 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10704 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10707 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10709 /* 1) Handle misc store, immediate offset. */
10710 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10711 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10712 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10713 regcache_raw_read_unsigned (reg_cache, reg_src1,
10715 if (ARM_PC_REGNUM == reg_src1)
10717 /* If R15 was used as Rn, hence current PC+8. */
10718 u_regval[0] = u_regval[0] + 8;
10720 offset_8 = (immed_high << 4) | immed_low;
10721 /* Calculate target store address. */
10722 if (14 == arm_insn_r->opcode)
10724 tgt_mem_addr = u_regval[0] + offset_8;
10728 tgt_mem_addr = u_regval[0] - offset_8;
10730 if (ARM_RECORD_STRH == str_type)
10732 record_buf_mem[0] = 2;
10733 record_buf_mem[1] = tgt_mem_addr;
10734 arm_insn_r->mem_rec_count = 1;
10736 else if (ARM_RECORD_STRD == str_type)
10738 record_buf_mem[0] = 4;
10739 record_buf_mem[1] = tgt_mem_addr;
10740 record_buf_mem[2] = 4;
10741 record_buf_mem[3] = tgt_mem_addr + 4;
10742 arm_insn_r->mem_rec_count = 2;
10745 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10747 /* 2) Store, register offset. */
10749 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10751 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10752 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10753 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10754 if (15 == reg_src2)
10756 /* If R15 was used as Rn, hence current PC+8. */
10757 u_regval[0] = u_regval[0] + 8;
10759 /* Calculate target store address, Rn +/- Rm, register offset. */
10760 if (12 == arm_insn_r->opcode)
10762 tgt_mem_addr = u_regval[0] + u_regval[1];
10766 tgt_mem_addr = u_regval[1] - u_regval[0];
10768 if (ARM_RECORD_STRH == str_type)
10770 record_buf_mem[0] = 2;
10771 record_buf_mem[1] = tgt_mem_addr;
10772 arm_insn_r->mem_rec_count = 1;
10774 else if (ARM_RECORD_STRD == str_type)
10776 record_buf_mem[0] = 4;
10777 record_buf_mem[1] = tgt_mem_addr;
10778 record_buf_mem[2] = 4;
10779 record_buf_mem[3] = tgt_mem_addr + 4;
10780 arm_insn_r->mem_rec_count = 2;
10783 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10784 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10786 /* 3) Store, immediate pre-indexed. */
10787 /* 5) Store, immediate post-indexed. */
10788 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10789 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10790 offset_8 = (immed_high << 4) | immed_low;
10791 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10792 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10793 /* Calculate target store address, Rn +/- Rm, register offset. */
10794 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10796 tgt_mem_addr = u_regval[0] + offset_8;
10800 tgt_mem_addr = u_regval[0] - offset_8;
10802 if (ARM_RECORD_STRH == str_type)
10804 record_buf_mem[0] = 2;
10805 record_buf_mem[1] = tgt_mem_addr;
10806 arm_insn_r->mem_rec_count = 1;
10808 else if (ARM_RECORD_STRD == str_type)
10810 record_buf_mem[0] = 4;
10811 record_buf_mem[1] = tgt_mem_addr;
10812 record_buf_mem[2] = 4;
10813 record_buf_mem[3] = tgt_mem_addr + 4;
10814 arm_insn_r->mem_rec_count = 2;
10816 /* Record Rn also as it changes. */
10817 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10818 arm_insn_r->reg_rec_count = 1;
10820 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10821 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10823 /* 4) Store, register pre-indexed. */
10824 /* 6) Store, register post -indexed. */
10825 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10826 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10827 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10828 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10829 /* Calculate target store address, Rn +/- Rm, register offset. */
10830 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10832 tgt_mem_addr = u_regval[0] + u_regval[1];
10836 tgt_mem_addr = u_regval[1] - u_regval[0];
10838 if (ARM_RECORD_STRH == str_type)
10840 record_buf_mem[0] = 2;
10841 record_buf_mem[1] = tgt_mem_addr;
10842 arm_insn_r->mem_rec_count = 1;
10844 else if (ARM_RECORD_STRD == str_type)
10846 record_buf_mem[0] = 4;
10847 record_buf_mem[1] = tgt_mem_addr;
10848 record_buf_mem[2] = 4;
10849 record_buf_mem[3] = tgt_mem_addr + 4;
10850 arm_insn_r->mem_rec_count = 2;
10852 /* Record Rn also as it changes. */
10853 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10854 arm_insn_r->reg_rec_count = 1;
10859 /* Handling ARM extension space insns. */
10862 arm_record_extension_space (insn_decode_record *arm_insn_r)
10864 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10865 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10866 uint32_t record_buf[8], record_buf_mem[8];
10867 uint32_t reg_src1 = 0;
10868 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10869 struct regcache *reg_cache = arm_insn_r->regcache;
10870 ULONGEST u_regval = 0;
10872 gdb_assert (!INSN_RECORDED(arm_insn_r));
10873 /* Handle unconditional insn extension space. */
10875 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10876 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10877 if (arm_insn_r->cond)
10879 /* PLD has no affect on architectural state, it just affects
10881 if (5 == ((opcode1 & 0xE0) >> 5))
10884 record_buf[0] = ARM_PS_REGNUM;
10885 record_buf[1] = ARM_LR_REGNUM;
10886 arm_insn_r->reg_rec_count = 2;
10888 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10892 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10893 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10896 /* Undefined instruction on ARM V5; need to handle if later
10897 versions define it. */
10900 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10901 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10902 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10904 /* Handle arithmetic insn extension space. */
10905 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10906 && !INSN_RECORDED(arm_insn_r))
10908 /* Handle MLA(S) and MUL(S). */
10909 if (0 <= insn_op1 && 3 >= insn_op1)
10911 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10912 record_buf[1] = ARM_PS_REGNUM;
10913 arm_insn_r->reg_rec_count = 2;
10915 else if (4 <= insn_op1 && 15 >= insn_op1)
10917 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10918 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10919 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10920 record_buf[2] = ARM_PS_REGNUM;
10921 arm_insn_r->reg_rec_count = 3;
10925 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10926 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10927 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10929 /* Handle control insn extension space. */
10931 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10932 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10934 if (!bit (arm_insn_r->arm_insn,25))
10936 if (!bits (arm_insn_r->arm_insn, 4, 7))
10938 if ((0 == insn_op1) || (2 == insn_op1))
10941 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10942 arm_insn_r->reg_rec_count = 1;
10944 else if (1 == insn_op1)
10946 /* CSPR is going to be changed. */
10947 record_buf[0] = ARM_PS_REGNUM;
10948 arm_insn_r->reg_rec_count = 1;
10950 else if (3 == insn_op1)
10952 /* SPSR is going to be changed. */
10953 /* We need to get SPSR value, which is yet to be done. */
10954 printf_unfiltered (_("Process record does not support "
10955 "instruction 0x%0x at address %s.\n"),
10956 arm_insn_r->arm_insn,
10957 paddress (arm_insn_r->gdbarch,
10958 arm_insn_r->this_addr));
10962 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10967 record_buf[0] = ARM_PS_REGNUM;
10968 arm_insn_r->reg_rec_count = 1;
10970 else if (3 == insn_op1)
10973 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10974 arm_insn_r->reg_rec_count = 1;
10977 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10980 record_buf[0] = ARM_PS_REGNUM;
10981 record_buf[1] = ARM_LR_REGNUM;
10982 arm_insn_r->reg_rec_count = 2;
10984 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10986 /* QADD, QSUB, QDADD, QDSUB */
10987 record_buf[0] = ARM_PS_REGNUM;
10988 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10989 arm_insn_r->reg_rec_count = 2;
10991 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10994 record_buf[0] = ARM_PS_REGNUM;
10995 record_buf[1] = ARM_LR_REGNUM;
10996 arm_insn_r->reg_rec_count = 2;
10998 /* Save SPSR also;how? */
10999 printf_unfiltered (_("Process record does not support "
11000 "instruction 0x%0x at address %s.\n"),
11001 arm_insn_r->arm_insn,
11002 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11005 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
11006 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
11007 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
11008 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
11011 if (0 == insn_op1 || 1 == insn_op1)
11013 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11014 /* We dont do optimization for SMULW<y> where we
11016 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11017 record_buf[1] = ARM_PS_REGNUM;
11018 arm_insn_r->reg_rec_count = 2;
11020 else if (2 == insn_op1)
11023 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11024 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11025 arm_insn_r->reg_rec_count = 2;
11027 else if (3 == insn_op1)
11030 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11031 arm_insn_r->reg_rec_count = 1;
11037 /* MSR : immediate form. */
11040 /* CSPR is going to be changed. */
11041 record_buf[0] = ARM_PS_REGNUM;
11042 arm_insn_r->reg_rec_count = 1;
11044 else if (3 == insn_op1)
11046 /* SPSR is going to be changed. */
11047 /* we need to get SPSR value, which is yet to be done */
11048 printf_unfiltered (_("Process record does not support "
11049 "instruction 0x%0x at address %s.\n"),
11050 arm_insn_r->arm_insn,
11051 paddress (arm_insn_r->gdbarch,
11052 arm_insn_r->this_addr));
11058 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
11059 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
11060 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
11062 /* Handle load/store insn extension space. */
11064 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
11065 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
11066 && !INSN_RECORDED(arm_insn_r))
11071 /* These insn, changes register and memory as well. */
11072 /* SWP or SWPB insn. */
11073 /* Get memory address given by Rn. */
11074 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11075 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11076 /* SWP insn ?, swaps word. */
11077 if (8 == arm_insn_r->opcode)
11079 record_buf_mem[0] = 4;
11083 /* SWPB insn, swaps only byte. */
11084 record_buf_mem[0] = 1;
11086 record_buf_mem[1] = u_regval;
11087 arm_insn_r->mem_rec_count = 1;
11088 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11089 arm_insn_r->reg_rec_count = 1;
11091 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11094 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11097 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11100 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11101 record_buf[1] = record_buf[0] + 1;
11102 arm_insn_r->reg_rec_count = 2;
11104 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11107 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11110 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
11112 /* LDRH, LDRSB, LDRSH. */
11113 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11114 arm_insn_r->reg_rec_count = 1;
11119 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
11120 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
11121 && !INSN_RECORDED(arm_insn_r))
11124 /* Handle coprocessor insn extension space. */
11127 /* To be done for ARMv5 and later; as of now we return -1. */
11129 printf_unfiltered (_("Process record does not support instruction x%0x "
11130 "at address %s.\n"),arm_insn_r->arm_insn,
11131 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11134 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11135 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11140 /* Handling opcode 000 insns. */
11143 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11145 struct regcache *reg_cache = arm_insn_r->regcache;
11146 uint32_t record_buf[8], record_buf_mem[8];
11147 ULONGEST u_regval[2] = {0};
11149 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11150 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11151 uint32_t opcode1 = 0;
11153 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11154 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11155 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11157 /* Data processing insn /multiply insn. */
11158 if (9 == arm_insn_r->decode
11159 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11160 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11162 /* Handle multiply instructions. */
11163 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11164 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11166 /* Handle MLA and MUL. */
11167 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11168 record_buf[1] = ARM_PS_REGNUM;
11169 arm_insn_r->reg_rec_count = 2;
11171 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11173 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11174 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11175 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11176 record_buf[2] = ARM_PS_REGNUM;
11177 arm_insn_r->reg_rec_count = 3;
11180 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11181 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11183 /* Handle misc load insns, as 20th bit (L = 1). */
11184 /* LDR insn has a capability to do branching, if
11185 MOV LR, PC is precceded by LDR insn having Rn as R15
11186 in that case, it emulates branch and link insn, and hence we
11187 need to save CSPR and PC as well. I am not sure this is right
11188 place; as opcode = 010 LDR insn make this happen, if R15 was
11190 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11191 if (15 != reg_dest)
11193 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11194 arm_insn_r->reg_rec_count = 1;
11198 record_buf[0] = reg_dest;
11199 record_buf[1] = ARM_PS_REGNUM;
11200 arm_insn_r->reg_rec_count = 2;
11203 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11204 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11205 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11206 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11208 /* Handle MSR insn. */
11209 if (9 == arm_insn_r->opcode)
11211 /* CSPR is going to be changed. */
11212 record_buf[0] = ARM_PS_REGNUM;
11213 arm_insn_r->reg_rec_count = 1;
11217 /* SPSR is going to be changed. */
11218 /* How to read SPSR value? */
11219 printf_unfiltered (_("Process record does not support instruction "
11220 "0x%0x at address %s.\n"),
11221 arm_insn_r->arm_insn,
11222 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11226 else if (9 == arm_insn_r->decode
11227 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11228 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11230 /* Handling SWP, SWPB. */
11231 /* These insn, changes register and memory as well. */
11232 /* SWP or SWPB insn. */
11234 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11235 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11236 /* SWP insn ?, swaps word. */
11237 if (8 == arm_insn_r->opcode)
11239 record_buf_mem[0] = 4;
11243 /* SWPB insn, swaps only byte. */
11244 record_buf_mem[0] = 1;
11246 record_buf_mem[1] = u_regval[0];
11247 arm_insn_r->mem_rec_count = 1;
11248 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11249 arm_insn_r->reg_rec_count = 1;
11251 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11252 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11254 /* Handle BLX, branch and link/exchange. */
11255 if (9 == arm_insn_r->opcode)
11257 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11258 and R14 stores the return address. */
11259 record_buf[0] = ARM_PS_REGNUM;
11260 record_buf[1] = ARM_LR_REGNUM;
11261 arm_insn_r->reg_rec_count = 2;
11264 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11266 /* Handle enhanced software breakpoint insn, BKPT. */
11267 /* CPSR is changed to be executed in ARM state, disabling normal
11268 interrupts, entering abort mode. */
11269 /* According to high vector configuration PC is set. */
11270 /* user hit breakpoint and type reverse, in
11271 that case, we need to go back with previous CPSR and
11272 Program Counter. */
11273 record_buf[0] = ARM_PS_REGNUM;
11274 record_buf[1] = ARM_LR_REGNUM;
11275 arm_insn_r->reg_rec_count = 2;
11277 /* Save SPSR also; how? */
11278 printf_unfiltered (_("Process record does not support instruction "
11279 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11280 paddress (arm_insn_r->gdbarch,
11281 arm_insn_r->this_addr));
11284 else if (11 == arm_insn_r->decode
11285 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11287 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11289 /* Handle str(x) insn */
11290 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11293 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11294 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11296 /* Handle BX, branch and link/exchange. */
11297 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11298 record_buf[0] = ARM_PS_REGNUM;
11299 arm_insn_r->reg_rec_count = 1;
11301 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11302 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11303 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11305 /* Count leading zeros: CLZ. */
11306 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11307 arm_insn_r->reg_rec_count = 1;
11309 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11310 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11311 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11312 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11315 /* Handle MRS insn. */
11316 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11317 arm_insn_r->reg_rec_count = 1;
11319 else if (arm_insn_r->opcode <= 15)
11321 /* Normal data processing insns. */
11322 /* Out of 11 shifter operands mode, all the insn modifies destination
11323 register, which is specified by 13-16 decode. */
11324 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11325 record_buf[1] = ARM_PS_REGNUM;
11326 arm_insn_r->reg_rec_count = 2;
11333 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11334 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11338 /* Handling opcode 001 insns. */
11341 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11343 uint32_t record_buf[8], record_buf_mem[8];
11345 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11346 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11348 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11349 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11350 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11353 /* Handle MSR insn. */
11354 if (9 == arm_insn_r->opcode)
11356 /* CSPR is going to be changed. */
11357 record_buf[0] = ARM_PS_REGNUM;
11358 arm_insn_r->reg_rec_count = 1;
11362 /* SPSR is going to be changed. */
11365 else if (arm_insn_r->opcode <= 15)
11367 /* Normal data processing insns. */
11368 /* Out of 11 shifter operands mode, all the insn modifies destination
11369 register, which is specified by 13-16 decode. */
11370 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11371 record_buf[1] = ARM_PS_REGNUM;
11372 arm_insn_r->reg_rec_count = 2;
11379 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11380 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11384 /* Handling opcode 010 insns. */
11387 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11389 struct regcache *reg_cache = arm_insn_r->regcache;
11391 uint32_t reg_src1 = 0 , reg_dest = 0;
11392 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11393 uint32_t record_buf[8], record_buf_mem[8];
11395 ULONGEST u_regval = 0;
11397 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11398 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11400 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11402 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11403 /* LDR insn has a capability to do branching, if
11404 MOV LR, PC is precedded by LDR insn having Rn as R15
11405 in that case, it emulates branch and link insn, and hence we
11406 need to save CSPR and PC as well. */
11407 if (ARM_PC_REGNUM != reg_dest)
11409 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11410 arm_insn_r->reg_rec_count = 1;
11414 record_buf[0] = reg_dest;
11415 record_buf[1] = ARM_PS_REGNUM;
11416 arm_insn_r->reg_rec_count = 2;
11421 /* Store, immediate offset, immediate pre-indexed,
11422 immediate post-indexed. */
11423 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11424 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11425 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11427 if (bit (arm_insn_r->arm_insn, 23))
11429 tgt_mem_addr = u_regval + offset_12;
11433 tgt_mem_addr = u_regval - offset_12;
11436 switch (arm_insn_r->opcode)
11450 record_buf_mem[0] = 4;
11465 record_buf_mem[0] = 1;
11469 gdb_assert_not_reached ("no decoding pattern found");
11472 record_buf_mem[1] = tgt_mem_addr;
11473 arm_insn_r->mem_rec_count = 1;
11475 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11476 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11477 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11478 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11479 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11480 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11483 /* We are handling pre-indexed mode; post-indexed mode;
11484 where Rn is going to be changed. */
11485 record_buf[0] = reg_src1;
11486 arm_insn_r->reg_rec_count = 1;
11490 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11491 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11495 /* Handling opcode 011 insns. */
11498 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11500 struct regcache *reg_cache = arm_insn_r->regcache;
11502 uint32_t shift_imm = 0;
11503 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11504 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11505 uint32_t record_buf[8], record_buf_mem[8];
11508 ULONGEST u_regval[2];
11510 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11511 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11513 /* Handle enhanced store insns and LDRD DSP insn,
11514 order begins according to addressing modes for store insns
11518 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11520 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11521 /* LDR insn has a capability to do branching, if
11522 MOV LR, PC is precedded by LDR insn having Rn as R15
11523 in that case, it emulates branch and link insn, and hence we
11524 need to save CSPR and PC as well. */
11525 if (15 != reg_dest)
11527 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11528 arm_insn_r->reg_rec_count = 1;
11532 record_buf[0] = reg_dest;
11533 record_buf[1] = ARM_PS_REGNUM;
11534 arm_insn_r->reg_rec_count = 2;
11539 if (! bits (arm_insn_r->arm_insn, 4, 11))
11541 /* Store insn, register offset and register pre-indexed,
11542 register post-indexed. */
11544 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11546 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11547 regcache_raw_read_unsigned (reg_cache, reg_src1
11549 regcache_raw_read_unsigned (reg_cache, reg_src2
11551 if (15 == reg_src2)
11553 /* If R15 was used as Rn, hence current PC+8. */
11554 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11555 u_regval[0] = u_regval[0] + 8;
11557 /* Calculate target store address, Rn +/- Rm, register offset. */
11559 if (bit (arm_insn_r->arm_insn, 23))
11561 tgt_mem_addr = u_regval[0] + u_regval[1];
11565 tgt_mem_addr = u_regval[1] - u_regval[0];
11568 switch (arm_insn_r->opcode)
11582 record_buf_mem[0] = 4;
11597 record_buf_mem[0] = 1;
11601 gdb_assert_not_reached ("no decoding pattern found");
11604 record_buf_mem[1] = tgt_mem_addr;
11605 arm_insn_r->mem_rec_count = 1;
11607 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11608 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11609 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11610 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11611 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11612 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11615 /* Rn is going to be changed in pre-indexed mode and
11616 post-indexed mode as well. */
11617 record_buf[0] = reg_src2;
11618 arm_insn_r->reg_rec_count = 1;
11623 /* Store insn, scaled register offset; scaled pre-indexed. */
11624 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11626 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11628 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11629 /* Get shift_imm. */
11630 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11631 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11632 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11633 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11634 /* Offset_12 used as shift. */
11638 /* Offset_12 used as index. */
11639 offset_12 = u_regval[0] << shift_imm;
11643 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11649 if (bit (u_regval[0], 31))
11651 offset_12 = 0xFFFFFFFF;
11660 /* This is arithmetic shift. */
11661 offset_12 = s_word >> shift_imm;
11668 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11670 /* Get C flag value and shift it by 31. */
11671 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11672 | (u_regval[0]) >> 1);
11676 offset_12 = (u_regval[0] >> shift_imm) \
11678 (sizeof(uint32_t) - shift_imm));
11683 gdb_assert_not_reached ("no decoding pattern found");
11687 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11689 if (bit (arm_insn_r->arm_insn, 23))
11691 tgt_mem_addr = u_regval[1] + offset_12;
11695 tgt_mem_addr = u_regval[1] - offset_12;
11698 switch (arm_insn_r->opcode)
11712 record_buf_mem[0] = 4;
11727 record_buf_mem[0] = 1;
11731 gdb_assert_not_reached ("no decoding pattern found");
11734 record_buf_mem[1] = tgt_mem_addr;
11735 arm_insn_r->mem_rec_count = 1;
11737 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11738 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11739 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11740 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11741 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11742 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11745 /* Rn is going to be changed in register scaled pre-indexed
11746 mode,and scaled post indexed mode. */
11747 record_buf[0] = reg_src2;
11748 arm_insn_r->reg_rec_count = 1;
11753 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11754 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11758 /* Handling opcode 100 insns. */
11761 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11763 struct regcache *reg_cache = arm_insn_r->regcache;
11765 uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0;
11766 uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0;
11767 uint32_t start_address = 0, index = 0;
11768 uint32_t record_buf[24], record_buf_mem[48];
11770 ULONGEST u_regval[2] = {0};
11772 /* This mode is exclusively for load and store multiple. */
11773 /* Handle incremenrt after/before and decrment after.before mode;
11774 Rn is changing depending on W bit, but as of now we store Rn too
11775 without optimization. */
11777 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11779 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11781 if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22))
11783 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11788 register_bits = bits (arm_insn_r->arm_insn, 0, 14);
11792 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11793 while (register_bits)
11795 if (register_bits & 0x00000001)
11796 register_list[register_count++] = 1;
11797 register_bits = register_bits >> 1;
11800 /* Extra space for Base Register and CPSR; wihtout optimization. */
11801 record_buf[register_count] = reg_src1;
11802 record_buf[register_count + 1] = ARM_PS_REGNUM;
11803 arm_insn_r->reg_rec_count = register_count + 2;
11805 for (register_count = 0; register_count < no_of_regs; register_count++)
11807 if (register_list[register_count])
11809 /* Register_count gives total no of registers
11810 and dually working as reg number. */
11811 record_buf[index] = register_count;
11819 /* It handles both STM(1) and STM(2). */
11820 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11822 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11824 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11825 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11826 while (register_bits)
11828 if (register_bits & 0x00000001)
11830 register_bits = register_bits >> 1;
11835 /* Decrement after. */
11837 start_address = (u_regval[0]) - (register_count * 4) + 4;
11838 arm_insn_r->mem_rec_count = register_count;
11839 while (register_count)
11841 record_buf_mem[(register_count * 2) - 1] = start_address;
11842 record_buf_mem[(register_count * 2) - 2] = 4;
11843 start_address = start_address + 4;
11848 /* Increment after. */
11850 start_address = u_regval[0];
11851 arm_insn_r->mem_rec_count = register_count;
11852 while (register_count)
11854 record_buf_mem[(register_count * 2) - 1] = start_address;
11855 record_buf_mem[(register_count * 2) - 2] = 4;
11856 start_address = start_address + 4;
11861 /* Decrement before. */
11864 start_address = (u_regval[0]) - (register_count * 4);
11865 arm_insn_r->mem_rec_count = register_count;
11866 while (register_count)
11868 record_buf_mem[(register_count * 2) - 1] = start_address;
11869 record_buf_mem[(register_count * 2) - 2] = 4;
11870 start_address = start_address + 4;
11875 /* Increment before. */
11877 start_address = u_regval[0] + 4;
11878 arm_insn_r->mem_rec_count = register_count;
11879 while (register_count)
11881 record_buf_mem[(register_count * 2) - 1] = start_address;
11882 record_buf_mem[(register_count * 2) - 2] = 4;
11883 start_address = start_address + 4;
11889 gdb_assert_not_reached ("no decoding pattern found");
11893 /* Base register also changes; based on condition and W bit. */
11894 /* We save it anyway without optimization. */
11895 record_buf[0] = reg_src1;
11896 arm_insn_r->reg_rec_count = 1;
11899 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11900 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11904 /* Handling opcode 101 insns. */
11907 arm_record_b_bl (insn_decode_record *arm_insn_r)
11909 uint32_t record_buf[8];
11911 /* Handle B, BL, BLX(1) insns. */
11912 /* B simply branches so we do nothing here. */
11913 /* Note: BLX(1) doesnt fall here but instead it falls into
11914 extension space. */
11915 if (bit (arm_insn_r->arm_insn, 24))
11917 record_buf[0] = ARM_LR_REGNUM;
11918 arm_insn_r->reg_rec_count = 1;
11921 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11926 /* Handling opcode 110 insns. */
11929 arm_record_coproc (insn_decode_record *arm_insn_r)
11931 printf_unfiltered (_("Process record does not support instruction "
11932 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11933 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11938 /* Handling opcode 111 insns. */
11941 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11943 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11944 struct regcache *reg_cache = arm_insn_r->regcache;
11945 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
11947 /* Handle SWI insn; system call would be handled over here. */
11949 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11950 if (15 == arm_insn_r->opcode)
11952 /* Handle arm syscall insn. */
11953 if (tdep->arm_swi_record != NULL)
11955 ret = tdep->arm_swi_record(reg_cache);
11959 printf_unfiltered (_("no syscall record support\n"));
11964 printf_unfiltered (_("Process record does not support instruction "
11965 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11966 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11970 /* Handling opcode 000 insns. */
11973 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11975 uint32_t record_buf[8];
11976 uint32_t reg_src1 = 0;
11978 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11980 record_buf[0] = ARM_PS_REGNUM;
11981 record_buf[1] = reg_src1;
11982 thumb_insn_r->reg_rec_count = 2;
11984 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11990 /* Handling opcode 001 insns. */
11993 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11995 uint32_t record_buf[8];
11996 uint32_t reg_src1 = 0;
11998 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12000 record_buf[0] = ARM_PS_REGNUM;
12001 record_buf[1] = reg_src1;
12002 thumb_insn_r->reg_rec_count = 2;
12004 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12009 /* Handling opcode 010 insns. */
12012 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
12014 struct regcache *reg_cache = thumb_insn_r->regcache;
12015 uint32_t record_buf[8], record_buf_mem[8];
12017 uint32_t reg_src1 = 0, reg_src2 = 0;
12018 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12020 ULONGEST u_regval[2] = {0};
12022 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
12024 if (bit (thumb_insn_r->arm_insn, 12))
12026 /* Handle load/store register offset. */
12027 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
12028 if (opcode2 >= 12 && opcode2 <= 15)
12030 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12031 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
12032 record_buf[0] = reg_src1;
12033 thumb_insn_r->reg_rec_count = 1;
12035 else if (opcode2 >= 8 && opcode2 <= 10)
12037 /* STR(2), STRB(2), STRH(2) . */
12038 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12039 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
12040 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
12041 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
12043 record_buf_mem[0] = 4; /* STR (2). */
12044 else if (10 == opcode2)
12045 record_buf_mem[0] = 1; /* STRB (2). */
12046 else if (9 == opcode2)
12047 record_buf_mem[0] = 2; /* STRH (2). */
12048 record_buf_mem[1] = u_regval[0] + u_regval[1];
12049 thumb_insn_r->mem_rec_count = 1;
12052 else if (bit (thumb_insn_r->arm_insn, 11))
12054 /* Handle load from literal pool. */
12056 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12057 record_buf[0] = reg_src1;
12058 thumb_insn_r->reg_rec_count = 1;
12062 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
12063 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
12064 if ((3 == opcode2) && (!opcode3))
12066 /* Branch with exchange. */
12067 record_buf[0] = ARM_PS_REGNUM;
12068 thumb_insn_r->reg_rec_count = 1;
12072 /* Format 8; special data processing insns. */
12073 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12074 record_buf[0] = ARM_PS_REGNUM;
12075 record_buf[1] = reg_src1;
12076 thumb_insn_r->reg_rec_count = 2;
12081 /* Format 5; data processing insns. */
12082 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12083 if (bit (thumb_insn_r->arm_insn, 7))
12085 reg_src1 = reg_src1 + 8;
12087 record_buf[0] = ARM_PS_REGNUM;
12088 record_buf[1] = reg_src1;
12089 thumb_insn_r->reg_rec_count = 2;
12092 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12093 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12099 /* Handling opcode 001 insns. */
12102 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
12104 struct regcache *reg_cache = thumb_insn_r->regcache;
12105 uint32_t record_buf[8], record_buf_mem[8];
12107 uint32_t reg_src1 = 0;
12108 uint32_t opcode = 0, immed_5 = 0;
12110 ULONGEST u_regval = 0;
12112 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12117 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12118 record_buf[0] = reg_src1;
12119 thumb_insn_r->reg_rec_count = 1;
12124 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12125 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12126 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12127 record_buf_mem[0] = 4;
12128 record_buf_mem[1] = u_regval + (immed_5 * 4);
12129 thumb_insn_r->mem_rec_count = 1;
12132 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12133 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12139 /* Handling opcode 100 insns. */
12142 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12144 struct regcache *reg_cache = thumb_insn_r->regcache;
12145 uint32_t record_buf[8], record_buf_mem[8];
12147 uint32_t reg_src1 = 0;
12148 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12150 ULONGEST u_regval = 0;
12152 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12157 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12158 record_buf[0] = reg_src1;
12159 thumb_insn_r->reg_rec_count = 1;
12161 else if (1 == opcode)
12164 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12165 record_buf[0] = reg_src1;
12166 thumb_insn_r->reg_rec_count = 1;
12168 else if (2 == opcode)
12171 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12172 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12173 record_buf_mem[0] = 4;
12174 record_buf_mem[1] = u_regval + (immed_8 * 4);
12175 thumb_insn_r->mem_rec_count = 1;
12177 else if (0 == opcode)
12180 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12181 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12182 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12183 record_buf_mem[0] = 2;
12184 record_buf_mem[1] = u_regval + (immed_5 * 2);
12185 thumb_insn_r->mem_rec_count = 1;
12188 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12189 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12195 /* Handling opcode 101 insns. */
12198 thumb_record_misc (insn_decode_record *thumb_insn_r)
12200 struct regcache *reg_cache = thumb_insn_r->regcache;
12202 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12203 uint32_t register_bits = 0, register_count = 0;
12204 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12205 uint32_t record_buf[24], record_buf_mem[48];
12208 ULONGEST u_regval = 0;
12210 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12211 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12212 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12217 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12218 while (register_bits)
12220 if (register_bits & 0x00000001)
12221 register_list[register_count++] = 1;
12222 register_bits = register_bits >> 1;
12224 record_buf[register_count] = ARM_PS_REGNUM;
12225 record_buf[register_count + 1] = ARM_SP_REGNUM;
12226 thumb_insn_r->reg_rec_count = register_count + 2;
12227 for (register_count = 0; register_count < 8; register_count++)
12229 if (register_list[register_count])
12231 record_buf[index] = register_count;
12236 else if (10 == opcode2)
12239 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12240 regcache_raw_read_unsigned (reg_cache, ARM_PC_REGNUM, &u_regval);
12241 while (register_bits)
12243 if (register_bits & 0x00000001)
12245 register_bits = register_bits >> 1;
12247 start_address = u_regval - \
12248 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12249 thumb_insn_r->mem_rec_count = register_count;
12250 while (register_count)
12252 record_buf_mem[(register_count * 2) - 1] = start_address;
12253 record_buf_mem[(register_count * 2) - 2] = 4;
12254 start_address = start_address + 4;
12257 record_buf[0] = ARM_SP_REGNUM;
12258 thumb_insn_r->reg_rec_count = 1;
12260 else if (0x1E == opcode1)
12263 /* Handle enhanced software breakpoint insn, BKPT. */
12264 /* CPSR is changed to be executed in ARM state, disabling normal
12265 interrupts, entering abort mode. */
12266 /* According to high vector configuration PC is set. */
12267 /* User hits breakpoint and type reverse, in that case, we need to go back with
12268 previous CPSR and Program Counter. */
12269 record_buf[0] = ARM_PS_REGNUM;
12270 record_buf[1] = ARM_LR_REGNUM;
12271 thumb_insn_r->reg_rec_count = 2;
12272 /* We need to save SPSR value, which is not yet done. */
12273 printf_unfiltered (_("Process record does not support instruction "
12274 "0x%0x at address %s.\n"),
12275 thumb_insn_r->arm_insn,
12276 paddress (thumb_insn_r->gdbarch,
12277 thumb_insn_r->this_addr));
12280 else if ((0 == opcode) || (1 == opcode))
12282 /* ADD(5), ADD(6). */
12283 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12284 record_buf[0] = reg_src1;
12285 thumb_insn_r->reg_rec_count = 1;
12287 else if (2 == opcode)
12289 /* ADD(7), SUB(4). */
12290 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12291 record_buf[0] = ARM_SP_REGNUM;
12292 thumb_insn_r->reg_rec_count = 1;
12295 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12296 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12302 /* Handling opcode 110 insns. */
12305 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12307 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12308 struct regcache *reg_cache = thumb_insn_r->regcache;
12310 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12311 uint32_t reg_src1 = 0;
12312 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12313 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12314 uint32_t record_buf[24], record_buf_mem[48];
12316 ULONGEST u_regval = 0;
12318 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12319 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12325 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12327 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12328 while (register_bits)
12330 if (register_bits & 0x00000001)
12331 register_list[register_count++] = 1;
12332 register_bits = register_bits >> 1;
12334 record_buf[register_count] = reg_src1;
12335 thumb_insn_r->reg_rec_count = register_count + 1;
12336 for (register_count = 0; register_count < 8; register_count++)
12338 if (register_list[register_count])
12340 record_buf[index] = register_count;
12345 else if (0 == opcode2)
12347 /* It handles both STMIA. */
12348 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12350 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12351 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12352 while (register_bits)
12354 if (register_bits & 0x00000001)
12356 register_bits = register_bits >> 1;
12358 start_address = u_regval;
12359 thumb_insn_r->mem_rec_count = register_count;
12360 while (register_count)
12362 record_buf_mem[(register_count * 2) - 1] = start_address;
12363 record_buf_mem[(register_count * 2) - 2] = 4;
12364 start_address = start_address + 4;
12368 else if (0x1F == opcode1)
12370 /* Handle arm syscall insn. */
12371 if (tdep->arm_swi_record != NULL)
12373 ret = tdep->arm_swi_record(reg_cache);
12377 printf_unfiltered (_("no syscall record support\n"));
12382 /* B (1), conditional branch is automatically taken care in process_record,
12383 as PC is saved there. */
12385 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12386 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12392 /* Handling opcode 111 insns. */
12395 thumb_record_branch (insn_decode_record *thumb_insn_r)
12397 uint32_t record_buf[8];
12398 uint32_t bits_h = 0;
12400 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12402 if (2 == bits_h || 3 == bits_h)
12405 record_buf[0] = ARM_LR_REGNUM;
12406 thumb_insn_r->reg_rec_count = 1;
12408 else if (1 == bits_h)
12411 record_buf[0] = ARM_PS_REGNUM;
12412 record_buf[1] = ARM_LR_REGNUM;
12413 thumb_insn_r->reg_rec_count = 2;
12416 /* B(2) is automatically taken care in process_record, as PC is
12419 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12425 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12426 and positive val on fauilure. */
12429 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12431 gdb_byte buf[insn_size];
12433 memset (&buf[0], 0, insn_size);
12435 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12437 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12439 gdbarch_byte_order (insn_record->gdbarch));
12443 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12445 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12449 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12450 uint32_t insn_size)
12453 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12454 static const sti_arm_hdl_fp_t const arm_handle_insn[8] =
12456 arm_record_data_proc_misc_ld_str, /* 000. */
12457 arm_record_data_proc_imm, /* 001. */
12458 arm_record_ld_st_imm_offset, /* 010. */
12459 arm_record_ld_st_reg_offset, /* 011. */
12460 arm_record_ld_st_multiple, /* 100. */
12461 arm_record_b_bl, /* 101. */
12462 arm_record_coproc, /* 110. */
12463 arm_record_coproc_data_proc /* 111. */
12466 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12467 static const sti_arm_hdl_fp_t const thumb_handle_insn[8] =
12469 thumb_record_shift_add_sub, /* 000. */
12470 thumb_record_add_sub_cmp_mov, /* 001. */
12471 thumb_record_ld_st_reg_offset, /* 010. */
12472 thumb_record_ld_st_imm_offset, /* 011. */
12473 thumb_record_ld_st_stack, /* 100. */
12474 thumb_record_misc, /* 101. */
12475 thumb_record_ldm_stm_swi, /* 110. */
12476 thumb_record_branch /* 111. */
12479 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12480 uint32_t insn_id = 0;
12482 if (extract_arm_insn (arm_record, insn_size))
12486 printf_unfiltered (_("Process record: error reading memory at "
12487 "addr %s len = %d.\n"),
12488 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
12492 else if (ARM_RECORD == record_type)
12494 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12495 insn_id = bits (arm_record->arm_insn, 25, 27);
12496 ret = arm_record_extension_space (arm_record);
12497 /* If this insn has fallen into extension space
12498 then we need not decode it anymore. */
12499 if (ret != -1 && !INSN_RECORDED(arm_record))
12501 ret = arm_handle_insn[insn_id] (arm_record);
12504 else if (THUMB_RECORD == record_type)
12506 /* As thumb does not have condition codes, we set negative. */
12507 arm_record->cond = -1;
12508 insn_id = bits (arm_record->arm_insn, 13, 15);
12509 ret = thumb_handle_insn[insn_id] (arm_record);
12511 else if (THUMB2_RECORD == record_type)
12513 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12514 "0x%0x at address %s.\n"),arm_record->arm_insn,
12515 paddress (arm_record->gdbarch,
12516 arm_record->this_addr));
12521 /* Throw assertion. */
12522 gdb_assert_not_reached ("not a valid instruction, could not decode");
12529 /* Cleans up local record registers and memory allocations. */
12532 deallocate_reg_mem (insn_decode_record *record)
12534 xfree (record->arm_regs);
12535 xfree (record->arm_mems);
12539 /* Parse the current instruction and record the values of the registers and
12540 memory that will be changed in current instruction to record_arch_list".
12541 Return -1 if something is wrong. */
12544 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
12545 CORE_ADDR insn_addr)
12548 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
12549 uint32_t no_of_rec = 0;
12550 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
12551 ULONGEST t_bit = 0, insn_id = 0;
12553 ULONGEST u_regval = 0;
12555 insn_decode_record arm_record;
12557 memset (&arm_record, 0, sizeof (insn_decode_record));
12558 arm_record.regcache = regcache;
12559 arm_record.this_addr = insn_addr;
12560 arm_record.gdbarch = gdbarch;
12563 if (record_debug > 1)
12565 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
12567 paddress (gdbarch, arm_record.this_addr));
12570 if (extract_arm_insn (&arm_record, 2))
12574 printf_unfiltered (_("Process record: error reading memory at "
12575 "addr %s len = %d.\n"),
12576 paddress (arm_record.gdbarch,
12577 arm_record.this_addr), 2);
12582 /* Check the insn, whether it is thumb or arm one. */
12584 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
12585 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
12588 if (!(u_regval & t_bit))
12590 /* We are decoding arm insn. */
12591 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
12595 insn_id = bits (arm_record.arm_insn, 11, 15);
12596 /* is it thumb2 insn? */
12597 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
12599 ret = decode_insn (&arm_record, THUMB2_RECORD,
12600 THUMB2_INSN_SIZE_BYTES);
12604 /* We are decoding thumb insn. */
12605 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
12611 /* Record registers. */
12612 record_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
12613 if (arm_record.arm_regs)
12615 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
12617 if (record_arch_list_add_reg (arm_record.regcache ,
12618 arm_record.arm_regs[no_of_rec]))
12622 /* Record memories. */
12623 if (arm_record.arm_mems)
12625 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
12627 if (record_arch_list_add_mem
12628 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
12629 arm_record.arm_mems[no_of_rec].len))
12634 if (record_arch_list_add_end ())
12639 deallocate_reg_mem (&arm_record);