1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
39 #include "gdb/sim-arm.h"
42 #include "coff/internal.h"
45 #include "gdb_assert.h"
47 /* Each OS has a different mechanism for accessing the various
48 registers stored in the sigcontext structure.
50 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
51 function pointer) which may be used to determine the addresses
52 of the various saved registers in the sigcontext structure.
54 For the ARM target, there are three parameters to this function.
55 The first is the pc value of the frame under consideration, the
56 second the stack pointer of this frame, and the last is the
57 register number to fetch.
59 If the tm.h file does not define this macro, then it's assumed that
60 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
63 When it comes time to multi-arching this code, see the identically
64 named machinery in ia64-tdep.c for an example of how it could be
65 done. It should not be necessary to modify the code below where
66 this macro is used. */
68 #ifdef SIGCONTEXT_REGISTER_ADDRESS
69 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
70 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
73 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
74 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
77 /* Macros for setting and testing a bit in a minimal symbol that marks
78 it as Thumb function. The MSB of the minimal symbol's "info" field
79 is used for this purpose. This field is already being used to store
80 the symbol size, so the assumption is that the symbol size cannot
83 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
84 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
85 MSYMBOL_SIZE Returns the size of the minimal symbol,
86 i.e. the "info" field with the "special" bit
89 #define MSYMBOL_SET_SPECIAL(msym) \
90 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
93 #define MSYMBOL_IS_SPECIAL(msym) \
94 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
96 #define MSYMBOL_SIZE(msym) \
97 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
99 /* Number of different reg name sets (options). */
100 static int num_flavor_options;
102 /* We have more registers than the disassembler as gdb can print the value
103 of special registers as well.
104 The general register names are overwritten by whatever is being used by
105 the disassembler at the moment. We also adjust the case of cpsr and fps. */
107 /* Initial value: Register names used in ARM's ISA documentation. */
108 static char * arm_register_name_strings[] =
109 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
110 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
111 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
112 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
113 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
114 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
115 "fps", "cpsr" }; /* 24 25 */
116 static char **arm_register_names = arm_register_name_strings;
118 /* Valid register name flavors. */
119 static const char **valid_flavors;
121 /* Disassembly flavor to use. Default to "std" register names. */
122 static const char *disassembly_flavor;
123 /* Index to that option in the opcodes table. */
124 static int current_option;
126 /* This is used to keep the bfd arch_info in sync with the disassembly
128 static void set_disassembly_flavor_sfunc(char *, int,
129 struct cmd_list_element *);
130 static void set_disassembly_flavor (void);
132 static void convert_from_extended (void *ptr, void *dbl);
134 /* Define other aspects of the stack frame. We keep the offsets of
135 all saved registers, 'cause we need 'em a lot! We also keep the
136 current size of the stack frame, and the offset of the frame
137 pointer from the stack pointer (for frameless functions, and when
138 we're still in the prologue of a function with a frame). */
140 struct frame_extra_info
147 /* Addresses for calling Thumb functions have the bit 0 set.
148 Here are some macros to test, set, or clear bit 0 of addresses. */
149 #define IS_THUMB_ADDR(addr) ((addr) & 1)
150 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
151 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
154 arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
156 return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
159 /* Set to true if the 32-bit mode is in use. */
163 /* Flag set by arm_fix_call_dummy that tells whether the target
164 function is a Thumb function. This flag is checked by
165 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
166 its use in valops.c) to pass the function address as an additional
169 static int target_is_thumb;
171 /* Flag set by arm_fix_call_dummy that tells whether the calling
172 function is a Thumb function. This flag is checked by
173 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
175 static int caller_is_thumb;
177 /* Determine if the program counter specified in MEMADDR is in a Thumb
181 arm_pc_is_thumb (CORE_ADDR memaddr)
183 struct minimal_symbol *sym;
185 /* If bit 0 of the address is set, assume this is a Thumb address. */
186 if (IS_THUMB_ADDR (memaddr))
189 /* Thumb functions have a "special" bit set in minimal symbols. */
190 sym = lookup_minimal_symbol_by_pc (memaddr);
193 return (MSYMBOL_IS_SPECIAL (sym));
201 /* Determine if the program counter specified in MEMADDR is in a call
202 dummy being called from a Thumb function. */
205 arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
207 CORE_ADDR sp = read_sp ();
209 /* FIXME: Until we switch for the new call dummy macros, this heuristic
210 is the best we can do. We are trying to determine if the pc is on
211 the stack, which (hopefully) will only happen in a call dummy.
212 We hope the current stack pointer is not so far alway from the dummy
213 frame location (true if we have not pushed large data structures or
214 gone too many levels deep) and that our 1024 is not enough to consider
215 code regions as part of the stack (true for most practical purposes). */
216 if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
217 return caller_is_thumb;
222 /* Remove useless bits from addresses in a running program. */
224 arm_addr_bits_remove (CORE_ADDR val)
226 if (arm_pc_is_thumb (val))
227 return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
229 return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
232 /* When reading symbols, we need to zap the low bit of the address,
233 which may be set to 1 for Thumb functions. */
235 arm_smash_text_address (CORE_ADDR val)
240 /* Immediately after a function call, return the saved pc. Can't
241 always go through the frames for this because on some machines the
242 new frame is not set up until the new function executes some
246 arm_saved_pc_after_call (struct frame_info *frame)
248 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
251 /* Determine whether the function invocation represented by FI has a
252 frame on the stack associated with it. If it does return zero,
253 otherwise return 1. */
256 arm_frameless_function_invocation (struct frame_info *fi)
258 CORE_ADDR func_start, after_prologue;
261 /* Sometimes we have functions that do a little setup (like saving the
262 vN registers with the stmdb instruction, but DO NOT set up a frame.
263 The symbol table will report this as a prologue. However, it is
264 important not to try to parse these partial frames as frames, or we
265 will get really confused.
267 So I will demand 3 instructions between the start & end of the
268 prologue before I call it a real prologue, i.e. at least
273 func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
274 after_prologue = SKIP_PROLOGUE (func_start);
276 /* There are some frameless functions whose first two instructions
277 follow the standard APCS form, in which case after_prologue will
278 be func_start + 8. */
280 frameless = (after_prologue < func_start + 12);
284 /* The address of the arguments in the frame. */
286 arm_frame_args_address (struct frame_info *fi)
291 /* The address of the local variables in the frame. */
293 arm_frame_locals_address (struct frame_info *fi)
298 /* The number of arguments being passed in the frame. */
300 arm_frame_num_args (struct frame_info *fi)
302 /* We have no way of knowing. */
306 /* A typical Thumb prologue looks like this:
310 Sometimes the latter instruction may be replaced by:
318 or, on tpcs, like this:
325 There is always one instruction of three classes:
330 When we have found at least one of each class we are done with the prolog.
331 Note that the "sub sp, #NN" before the push does not count.
335 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
337 CORE_ADDR current_pc;
339 bit 0 - push { rlist }
340 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
341 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
345 for (current_pc = pc;
346 current_pc + 2 < func_end && current_pc < pc + 40;
349 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
351 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
353 findmask |= 1; /* push found */
355 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
358 if ((findmask & 1) == 0) /* before push ? */
361 findmask |= 4; /* add/sub sp found */
363 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
365 findmask |= 2; /* setting of r7 found */
367 else if (insn == 0x466f) /* mov r7, sp */
369 findmask |= 2; /* setting of r7 found */
371 else if (findmask == (4+2+1))
373 /* We have found one of each type of prologue instruction */
377 /* Something in the prolog that we don't care about or some
378 instruction from outside the prolog scheduled here for
386 /* Advance the PC across any function entry prologue instructions to
387 reach some "real" code.
389 The APCS (ARM Procedure Call Standard) defines the following
393 [stmfd sp!, {a1,a2,a3,a4}]
394 stmfd sp!, {...,fp,ip,lr,pc}
395 [stfe f7, [sp, #-12]!]
396 [stfe f6, [sp, #-12]!]
397 [stfe f5, [sp, #-12]!]
398 [stfe f4, [sp, #-12]!]
399 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
402 arm_skip_prologue (CORE_ADDR pc)
406 CORE_ADDR func_addr, func_end = 0;
408 struct symtab_and_line sal;
410 /* If we're in a dummy frame, don't even try to skip the prologue. */
411 if (USE_GENERIC_DUMMY_FRAMES
412 && PC_IN_CALL_DUMMY (pc, 0, 0))
415 /* See what the symbol table says. */
417 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
421 /* Found a function. */
422 sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL);
423 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
425 /* Don't use this trick for assembly source files. */
426 sal = find_pc_line (func_addr, 0);
427 if ((sal.line != 0) && (sal.end < func_end))
432 /* Check if this is Thumb code. */
433 if (arm_pc_is_thumb (pc))
434 return thumb_skip_prologue (pc, func_end);
436 /* Can't find the prologue end in the symbol table, try it the hard way
437 by disassembling the instructions. */
439 /* Like arm_scan_prologue, stop no later than pc + 64. */
440 if (func_end == 0 || func_end > pc + 64)
443 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
445 inst = read_memory_integer (skip_pc, 4);
447 /* "mov ip, sp" is no longer a required part of the prologue. */
448 if (inst == 0xe1a0c00d) /* mov ip, sp */
451 /* Some prologues begin with "str lr, [sp, #-4]!". */
452 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
455 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
458 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
461 /* Any insns after this point may float into the code, if it makes
462 for better instruction scheduling, so we skip them only if we
463 find them, but still consider the function to be frame-ful. */
465 /* We may have either one sfmfd instruction here, or several stfe
466 insns, depending on the version of floating point code we
468 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
471 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
474 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
477 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
480 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
481 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
482 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
485 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
486 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
487 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
490 /* Un-recognized instruction; stop scanning. */
494 return skip_pc; /* End of prologue */
498 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
499 This function decodes a Thumb function prologue to determine:
500 1) the size of the stack frame
501 2) which registers are saved on it
502 3) the offsets of saved regs
503 4) the offset from the stack pointer to the frame pointer
504 This information is stored in the "extra" fields of the frame_info.
506 A typical Thumb function prologue would create this stack frame
507 (offsets relative to FP)
508 old SP -> 24 stack parameters
511 R7 -> 0 local variables (16 bytes)
512 SP -> -12 additional stack space (12 bytes)
513 The frame size would thus be 36 bytes, and the frame offset would be
514 12 bytes. The frame register is R7.
516 The comments for thumb_skip_prolog() describe the algorithm we use
517 to detect the end of the prolog. */
521 thumb_scan_prologue (struct frame_info *fi)
523 CORE_ADDR prologue_start;
524 CORE_ADDR prologue_end;
525 CORE_ADDR current_pc;
526 /* Which register has been copied to register n? */
529 bit 0 - push { rlist }
530 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
531 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
536 /* Don't try to scan dummy frames. */
537 if (USE_GENERIC_DUMMY_FRAMES
539 && PC_IN_CALL_DUMMY (fi->pc, 0, 0))
542 if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
544 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
546 if (sal.line == 0) /* no line info, use current PC */
547 prologue_end = fi->pc;
548 else if (sal.end < prologue_end) /* next line begins after fn end */
549 prologue_end = sal.end; /* (probably means no prologue) */
552 /* We're in the boondocks: allow for
553 16 pushes, an add, and "mv fp,sp". */
554 prologue_end = prologue_start + 40;
556 prologue_end = min (prologue_end, fi->pc);
558 /* Initialize the saved register map. When register H is copied to
559 register L, we will put H in saved_reg[L]. */
560 for (i = 0; i < 16; i++)
563 /* Search the prologue looking for instructions that set up the
564 frame pointer, adjust the stack pointer, and save registers.
565 Do this until all basic prolog instructions are found. */
567 fi->extra_info->framesize = 0;
568 for (current_pc = prologue_start;
569 (current_pc < prologue_end) && ((findmask & 7) != 7);
576 insn = read_memory_unsigned_integer (current_pc, 2);
578 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
581 findmask |= 1; /* push found */
582 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
583 whether to save LR (R14). */
584 mask = (insn & 0xff) | ((insn & 0x100) << 6);
586 /* Calculate offsets of saved R0-R7 and LR. */
587 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
588 if (mask & (1 << regno))
590 fi->extra_info->framesize += 4;
591 fi->saved_regs[saved_reg[regno]] =
592 -(fi->extra_info->framesize);
593 /* Reset saved register map. */
594 saved_reg[regno] = regno;
597 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
600 if ((findmask & 1) == 0) /* before push? */
603 findmask |= 4; /* add/sub sp found */
605 offset = (insn & 0x7f) << 2; /* get scaled offset */
606 if (insn & 0x80) /* is it signed? (==subtracting) */
608 fi->extra_info->frameoffset += offset;
611 fi->extra_info->framesize -= offset;
613 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
615 findmask |= 2; /* setting of r7 found */
616 fi->extra_info->framereg = THUMB_FP_REGNUM;
617 /* get scaled offset */
618 fi->extra_info->frameoffset = (insn & 0xff) << 2;
620 else if (insn == 0x466f) /* mov r7, sp */
622 findmask |= 2; /* setting of r7 found */
623 fi->extra_info->framereg = THUMB_FP_REGNUM;
624 fi->extra_info->frameoffset = 0;
625 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
627 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
629 int lo_reg = insn & 7; /* dest. register (r0-r7) */
630 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
631 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
634 /* Something in the prolog that we don't care about or some
635 instruction from outside the prolog scheduled here for
641 /* Check if prologue for this frame's PC has already been scanned. If
642 it has, copy the relevant information about that prologue and
643 return non-zero. Otherwise do not copy anything and return zero.
645 The information saved in the cache includes:
646 * the frame register number;
647 * the size of the stack frame;
648 * the offsets of saved regs (relative to the old SP); and
649 * the offset from the stack pointer to the frame pointer
651 The cache contains only one entry, since this is adequate for the
652 typical sequence of prologue scan requests we get. When performing
653 a backtrace, GDB will usually ask to scan the same function twice
654 in a row (once to get the frame chain, and once to fill in the
655 extra frame information). */
657 static struct frame_info prologue_cache;
660 check_prologue_cache (struct frame_info *fi)
664 if (fi->pc == prologue_cache.pc)
666 fi->extra_info->framereg = prologue_cache.extra_info->framereg;
667 fi->extra_info->framesize = prologue_cache.extra_info->framesize;
668 fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset;
669 for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
670 fi->saved_regs[i] = prologue_cache.saved_regs[i];
678 /* Copy the prologue information from fi to the prologue cache. */
681 save_prologue_cache (struct frame_info *fi)
685 prologue_cache.pc = fi->pc;
686 prologue_cache.extra_info->framereg = fi->extra_info->framereg;
687 prologue_cache.extra_info->framesize = fi->extra_info->framesize;
688 prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset;
690 for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
691 prologue_cache.saved_regs[i] = fi->saved_regs[i];
695 /* This function decodes an ARM function prologue to determine:
696 1) the size of the stack frame
697 2) which registers are saved on it
698 3) the offsets of saved regs
699 4) the offset from the stack pointer to the frame pointer
700 This information is stored in the "extra" fields of the frame_info.
702 There are two basic forms for the ARM prologue. The fixed argument
703 function call will look like:
706 stmfd sp!, {fp, ip, lr, pc}
710 Which would create this stack frame (offsets relative to FP):
711 IP -> 4 (caller's stack)
712 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
713 -4 LR (return address in caller)
714 -8 IP (copy of caller's SP)
716 SP -> -28 Local variables
718 The frame size would thus be 32 bytes, and the frame offset would be
719 28 bytes. The stmfd call can also save any of the vN registers it
720 plans to use, which increases the frame size accordingly.
722 Note: The stored PC is 8 off of the STMFD instruction that stored it
723 because the ARM Store instructions always store PC + 8 when you read
726 A variable argument function call will look like:
729 stmfd sp!, {a1, a2, a3, a4}
730 stmfd sp!, {fp, ip, lr, pc}
733 Which would create this stack frame (offsets relative to FP):
734 IP -> 20 (caller's stack)
739 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
740 -4 LR (return address in caller)
741 -8 IP (copy of caller's SP)
743 SP -> -28 Local variables
745 The frame size would thus be 48 bytes, and the frame offset would be
748 There is another potential complication, which is that the optimizer
749 will try to separate the store of fp in the "stmfd" instruction from
750 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
751 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
753 Also, note, the original version of the ARM toolchain claimed that there
756 instruction at the end of the prologue. I have never seen GCC produce
757 this, and the ARM docs don't mention it. We still test for it below in
763 arm_scan_prologue (struct frame_info *fi)
765 int regno, sp_offset, fp_offset;
766 LONGEST return_value;
767 CORE_ADDR prologue_start, prologue_end, current_pc;
769 /* Check if this function is already in the cache of frame information. */
770 if (check_prologue_cache (fi))
773 /* Assume there is no frame until proven otherwise. */
774 fi->extra_info->framereg = ARM_SP_REGNUM;
775 fi->extra_info->framesize = 0;
776 fi->extra_info->frameoffset = 0;
778 /* Check for Thumb prologue. */
779 if (arm_pc_is_thumb (fi->pc))
781 thumb_scan_prologue (fi);
782 save_prologue_cache (fi);
786 /* Find the function prologue. If we can't find the function in
787 the symbol table, peek in the stack frame to find the PC. */
788 if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
790 /* One way to find the end of the prologue (which works well
791 for unoptimized code) is to do the following:
793 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
796 prologue_end = fi->pc;
797 else if (sal.end < prologue_end)
798 prologue_end = sal.end;
800 This mechanism is very accurate so long as the optimizer
801 doesn't move any instructions from the function body into the
802 prologue. If this happens, sal.end will be the last
803 instruction in the first hunk of prologue code just before
804 the first instruction that the scheduler has moved from
805 the body to the prologue.
807 In order to make sure that we scan all of the prologue
808 instructions, we use a slightly less accurate mechanism which
809 may scan more than necessary. To help compensate for this
810 lack of accuracy, the prologue scanning loop below contains
811 several clauses which'll cause the loop to terminate early if
812 an implausible prologue instruction is encountered.
818 is a suitable endpoint since it accounts for the largest
819 possible prologue plus up to five instructions inserted by
822 if (prologue_end > prologue_start + 64)
824 prologue_end = prologue_start + 64; /* See above. */
829 /* Get address of the stmfd in the prologue of the callee;
830 the saved PC is the address of the stmfd + 8. */
831 if (!safe_read_memory_integer (fi->frame, 4, &return_value))
835 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
836 prologue_end = prologue_start + 64; /* See above. */
840 /* Now search the prologue looking for instructions that set up the
841 frame pointer, adjust the stack pointer, and save registers.
843 Be careful, however, and if it doesn't look like a prologue,
844 don't try to scan it. If, for instance, a frameless function
845 begins with stmfd sp!, then we will tell ourselves there is
846 a frame, which will confuse stack traceback, as well as "finish"
847 and other operations that rely on a knowledge of the stack
850 In the APCS, the prologue should start with "mov ip, sp" so
851 if we don't see this as the first insn, we will stop.
853 [Note: This doesn't seem to be true any longer, so it's now an
854 optional part of the prologue. - Kevin Buettner, 2001-11-20]
856 [Note further: The "mov ip,sp" only seems to be missing in
857 frameless functions at optimization level "-O2" or above,
858 in which case it is often (but not always) replaced by
859 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
861 sp_offset = fp_offset = 0;
863 for (current_pc = prologue_start;
864 current_pc < prologue_end;
867 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
869 if (insn == 0xe1a0c00d) /* mov ip, sp */
873 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
875 /* Function is frameless: extra_info defaults OK? */
878 else if ((insn & 0xffff0000) == 0xe92d0000)
879 /* stmfd sp!, {..., fp, ip, lr, pc}
881 stmfd sp!, {a1, a2, a3, a4} */
883 int mask = insn & 0xffff;
885 /* Calculate offsets of saved registers. */
886 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
887 if (mask & (1 << regno))
890 fi->saved_regs[regno] = sp_offset;
893 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
894 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
895 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
897 /* No need to add this to saved_regs -- it's just an arg reg. */
900 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
901 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
902 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
904 /* No need to add this to saved_regs -- it's just an arg reg. */
907 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
909 unsigned imm = insn & 0xff; /* immediate value */
910 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
911 imm = (imm >> rot) | (imm << (32 - rot));
913 fi->extra_info->framereg = ARM_FP_REGNUM;
915 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
917 unsigned imm = insn & 0xff; /* immediate value */
918 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
919 imm = (imm >> rot) | (imm << (32 - rot));
922 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
925 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
926 fi->saved_regs[regno] = sp_offset;
928 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
931 unsigned int fp_start_reg, fp_bound_reg;
933 if ((insn & 0x800) == 0x800) /* N0 is set */
935 if ((insn & 0x40000) == 0x40000) /* N1 is set */
942 if ((insn & 0x40000) == 0x40000) /* N1 is set */
948 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
949 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
950 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
953 fi->saved_regs[fp_start_reg++] = sp_offset;
956 else if ((insn & 0xf0000000) != 0xe0000000)
957 break; /* Condition not true, exit early */
958 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
959 break; /* Don't scan past a block load */
961 /* The optimizer might shove anything into the prologue,
962 so we just skip what we don't recognize. */
966 /* The frame size is just the negative of the offset (from the
967 original SP) of the last thing thing we pushed on the stack.
968 The frame offset is [new FP] - [new SP]. */
969 fi->extra_info->framesize = -sp_offset;
970 if (fi->extra_info->framereg == ARM_FP_REGNUM)
971 fi->extra_info->frameoffset = fp_offset - sp_offset;
973 fi->extra_info->frameoffset = 0;
975 save_prologue_cache (fi);
978 /* Find REGNUM on the stack. Otherwise, it's in an active register.
979 One thing we might want to do here is to check REGNUM against the
980 clobber mask, and somehow flag it as invalid if it isn't saved on
981 the stack somewhere. This would provide a graceful failure mode
982 when trying to get the value of caller-saves registers for an inner
986 arm_find_callers_reg (struct frame_info *fi, int regnum)
988 /* NOTE: cagney/2002-05-03: This function really shouldn't be
989 needed. Instead the (still being written) register unwind
990 function could be called directly. */
991 for (; fi; fi = fi->next)
993 if (USE_GENERIC_DUMMY_FRAMES
994 && PC_IN_CALL_DUMMY (fi->pc, 0, 0))
996 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
998 else if (fi->saved_regs[regnum] != 0)
1000 /* NOTE: cagney/2002-05-03: This would normally need to
1001 handle ARM_SP_REGNUM as a special case as, according to
1002 the frame.h comments, saved_regs[SP_REGNUM] contains the
1003 SP value not its address. It appears that the ARM isn't
1004 doing this though. */
1005 return read_memory_integer (fi->saved_regs[regnum],
1006 REGISTER_RAW_SIZE (regnum));
1009 return read_register (regnum);
1011 /* Function: frame_chain Given a GDB frame, determine the address of
1012 the calling function's frame. This will be used to create a new
1013 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1014 will be called for the new frame. For ARM, we save the frame size
1015 when we initialize the frame_info. */
1018 arm_frame_chain (struct frame_info *fi)
1020 CORE_ADDR caller_pc;
1021 int framereg = fi->extra_info->framereg;
1023 if (USE_GENERIC_DUMMY_FRAMES
1024 && PC_IN_CALL_DUMMY (fi->pc, 0, 0))
1025 /* A generic call dummy's frame is the same as caller's. */
1028 if (fi->pc < LOWEST_PC)
1031 /* If the caller is the startup code, we're at the end of the chain. */
1032 caller_pc = FRAME_SAVED_PC (fi);
1034 /* If the caller is Thumb and the caller is ARM, or vice versa,
1035 the frame register of the caller is different from ours.
1036 So we must scan the prologue of the caller to determine its
1037 frame register number. */
1038 /* XXX Fixme, we should try to do this without creating a temporary
1040 if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
1042 struct frame_info caller_fi;
1043 struct cleanup *old_chain;
1045 /* Create a temporary frame suitable for scanning the caller's
1047 memset (&caller_fi, 0, sizeof (caller_fi));
1048 caller_fi.extra_info = (struct frame_extra_info *)
1049 xcalloc (1, sizeof (struct frame_extra_info));
1050 old_chain = make_cleanup (xfree, caller_fi.extra_info);
1051 caller_fi.saved_regs = (CORE_ADDR *)
1052 xcalloc (1, SIZEOF_FRAME_SAVED_REGS);
1053 make_cleanup (xfree, caller_fi.saved_regs);
1055 /* Now, scan the prologue and obtain the frame register. */
1056 caller_fi.pc = caller_pc;
1057 arm_scan_prologue (&caller_fi);
1058 framereg = caller_fi.extra_info->framereg;
1060 /* Deallocate the storage associated with the temporary frame
1062 do_cleanups (old_chain);
1065 /* If the caller used a frame register, return its value.
1066 Otherwise, return the caller's stack pointer. */
1067 if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM)
1068 return arm_find_callers_reg (fi, framereg);
1070 return fi->frame + fi->extra_info->framesize;
1073 /* This function actually figures out the frame address for a given pc
1074 and sp. This is tricky because we sometimes don't use an explicit
1075 frame pointer, and the previous stack pointer isn't necessarily
1076 recorded on the stack. The only reliable way to get this info is
1077 to examine the prologue. FROMLEAF is a little confusing, it means
1078 this is the next frame up the chain AFTER a frameless function. If
1079 this is true, then the frame value for this frame is still in the
1083 arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1088 if (fi->saved_regs == NULL)
1089 frame_saved_regs_zalloc (fi);
1091 fi->extra_info = (struct frame_extra_info *)
1092 frame_obstack_alloc (sizeof (struct frame_extra_info));
1094 fi->extra_info->framesize = 0;
1095 fi->extra_info->frameoffset = 0;
1096 fi->extra_info->framereg = 0;
1099 fi->pc = FRAME_SAVED_PC (fi->next);
1101 memset (fi->saved_regs, '\000', sizeof fi->saved_regs);
1103 /* Compute stack pointer for this frame. We use this value for both
1104 the sigtramp and call dummy cases. */
1107 else if (USE_GENERIC_DUMMY_FRAMES
1108 && PC_IN_CALL_DUMMY (fi->next->pc, 0, 0))
1109 /* For generic dummy frames, pull the value direct from the frame.
1110 Having an unwind function to do this would be nice. */
1111 sp = generic_read_register_dummy (fi->next->pc, fi->next->frame,
1114 sp = (fi->next->frame - fi->next->extra_info->frameoffset
1115 + fi->next->extra_info->framesize);
1117 /* Determine whether or not we're in a sigtramp frame.
1118 Unfortunately, it isn't sufficient to test
1119 fi->signal_handler_caller because this value is sometimes set
1120 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1121 fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we
1122 need to use the sigcontext addresses for the saved registers.
1124 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1125 against the name of the function, the code below will have to be
1126 changed to first fetch the name of the function and then pass
1127 this name to PC_IN_SIGTRAMP. */
1129 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1130 && (fi->signal_handler_caller || PC_IN_SIGTRAMP (fi->pc, (char *)0)))
1132 for (reg = 0; reg < NUM_REGS; reg++)
1133 fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg);
1135 /* FIXME: What about thumb mode? */
1136 fi->extra_info->framereg = ARM_SP_REGNUM;
1138 read_memory_integer (fi->saved_regs[fi->extra_info->framereg],
1139 REGISTER_RAW_SIZE (fi->extra_info->framereg));
1140 fi->extra_info->framesize = 0;
1141 fi->extra_info->frameoffset = 0;
1144 else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame))
1147 CORE_ADDR callers_sp;
1149 /* Set rp point at the high end of the saved registers. */
1150 rp = fi->frame - REGISTER_SIZE;
1152 /* Fill in addresses of saved registers. */
1153 fi->saved_regs[ARM_PS_REGNUM] = rp;
1154 rp -= REGISTER_RAW_SIZE (ARM_PS_REGNUM);
1155 for (reg = ARM_PC_REGNUM; reg >= 0; reg--)
1157 fi->saved_regs[reg] = rp;
1158 rp -= REGISTER_RAW_SIZE (reg);
1161 callers_sp = read_memory_integer (fi->saved_regs[ARM_SP_REGNUM],
1162 REGISTER_RAW_SIZE (ARM_SP_REGNUM));
1163 fi->extra_info->framereg = ARM_FP_REGNUM;
1164 fi->extra_info->framesize = callers_sp - sp;
1165 fi->extra_info->frameoffset = fi->frame - sp;
1169 arm_scan_prologue (fi);
1172 /* This is the innermost frame? */
1173 fi->frame = read_register (fi->extra_info->framereg);
1174 else if (USE_GENERIC_DUMMY_FRAMES
1175 && PC_IN_CALL_DUMMY (fi->next->pc, 0, 0))
1176 /* Next inner most frame is a dummy, just grab its frame.
1177 Dummy frames always have the same FP as their caller. */
1178 fi->frame = fi->next->frame;
1179 else if (fi->extra_info->framereg == ARM_FP_REGNUM
1180 || fi->extra_info->framereg == THUMB_FP_REGNUM)
1182 /* not the innermost frame */
1183 /* If we have an FP, the callee saved it. */
1184 if (fi->next->saved_regs[fi->extra_info->framereg] != 0)
1186 read_memory_integer (fi->next
1187 ->saved_regs[fi->extra_info->framereg], 4);
1189 /* If we were called by a frameless fn. then our frame is
1190 still in the frame pointer register on the board... */
1191 fi->frame = read_fp ();
1194 /* Calculate actual addresses of saved registers using offsets
1195 determined by arm_scan_prologue. */
1196 for (reg = 0; reg < NUM_REGS; reg++)
1197 if (fi->saved_regs[reg] != 0)
1198 fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize
1199 - fi->extra_info->frameoffset);
1204 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1205 is saved in the stack anywhere, otherwise we get it from the
1208 The old definition of this function was a macro:
1209 #define FRAME_SAVED_PC(FRAME) \
1210 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1213 arm_frame_saved_pc (struct frame_info *fi)
1215 /* If a dummy frame, pull the PC out of the frame's register buffer. */
1216 if (USE_GENERIC_DUMMY_FRAMES
1217 && PC_IN_CALL_DUMMY (fi->pc, 0, 0))
1218 return generic_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM);
1220 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset,
1223 return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM],
1224 REGISTER_RAW_SIZE (ARM_PC_REGNUM));
1228 CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM);
1229 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1233 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1234 Examine the Program Status Register to decide which state we're in. */
1239 if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
1240 return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
1242 return read_register (ARM_FP_REGNUM); /* R11 if ARM */
1245 /* Store into a struct frame_saved_regs the addresses of the saved
1246 registers of frame described by FRAME_INFO. This includes special
1247 registers such as PC and FP saved in special ways in the stack
1248 frame. SP is even more special: the address we return for it IS
1249 the sp for the next frame. */
1252 arm_frame_init_saved_regs (struct frame_info *fip)
1255 if (fip->saved_regs)
1258 arm_init_extra_frame_info (0, fip);
1261 /* Set the return address for a generic dummy frame. ARM uses the
1265 arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1267 write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ());
1271 /* Push an empty stack frame, to record the current PC, etc. */
1274 arm_push_dummy_frame (void)
1276 CORE_ADDR old_sp = read_register (ARM_SP_REGNUM);
1277 CORE_ADDR sp = old_sp;
1278 CORE_ADDR fp, prologue_start;
1281 /* Push the two dummy prologue instructions in reverse order,
1282 so that they'll be in the correct low-to-high order in memory. */
1283 /* sub fp, ip, #4 */
1284 sp = push_word (sp, 0xe24cb004);
1285 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1286 prologue_start = sp = push_word (sp, 0xe92ddfff);
1288 /* Push a pointer to the dummy prologue + 12, because when stm
1289 instruction stores the PC, it stores the address of the stm
1290 instruction itself plus 12. */
1291 fp = sp = push_word (sp, prologue_start + 12);
1293 /* Push the processor status. */
1294 sp = push_word (sp, read_register (ARM_PS_REGNUM));
1296 /* Push all 16 registers starting with r15. */
1297 for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--)
1298 sp = push_word (sp, read_register (regnum));
1300 /* Update fp (for both Thumb and ARM) and sp. */
1301 write_register (ARM_FP_REGNUM, fp);
1302 write_register (THUMB_FP_REGNUM, fp);
1303 write_register (ARM_SP_REGNUM, sp);
1306 /* CALL_DUMMY_WORDS:
1307 This sequence of words is the instructions
1313 Note this is 12 bytes. */
1315 static LONGEST arm_call_dummy_words[] =
1317 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1320 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1321 breakpoint to the proper address in the call dummy, so that
1322 `finish' after a stop in a call dummy works.
1324 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1325 optimal solution, but the call to arm_fix_call_dummy is immediately
1326 followed by a call to run_stack_dummy, which is the only function
1327 where call_dummy_breakpoint_offset is actually used. */
1331 arm_set_call_dummy_breakpoint_offset (void)
1333 if (caller_is_thumb)
1334 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4);
1336 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8);
1339 /* Fix up the call dummy, based on whether the processor is currently
1340 in Thumb or ARM mode, and whether the target function is Thumb or
1341 ARM. There are three different situations requiring three
1344 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1345 been copied into the dummy parameter to this function.
1346 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1347 "mov pc,r4" instruction patched to be a "bx r4" instead.
1348 * Thumb calling anything: uses the Thumb dummy defined below, which
1349 works for calling both ARM and Thumb functions.
1351 All three call dummies expect to receive the target function
1352 address in R4, with the low bit set if it's a Thumb function. */
1355 arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1356 struct value **args, struct type *type, int gcc_p)
1358 static short thumb_dummy[4] =
1360 0xf000, 0xf801, /* bl label */
1361 0xdf18, /* swi 24 */
1362 0x4720, /* label: bx r4 */
1364 static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
1366 /* Set flag indicating whether the current PC is in a Thumb function. */
1367 caller_is_thumb = arm_pc_is_thumb (read_pc ());
1368 arm_set_call_dummy_breakpoint_offset ();
1370 /* If the target function is Thumb, set the low bit of the function
1371 address. And if the CPU is currently in ARM mode, patch the
1372 second instruction of call dummy to use a BX instruction to
1373 switch to Thumb mode. */
1374 target_is_thumb = arm_pc_is_thumb (fun);
1375 if (target_is_thumb)
1378 if (!caller_is_thumb)
1379 store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
1382 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1383 instead of the ARM one that's already been copied. This will
1384 work for both Thumb and ARM target functions. */
1385 if (caller_is_thumb)
1389 int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
1391 for (i = 0; i < len; i++)
1393 store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
1394 p += sizeof (thumb_dummy[0]);
1398 /* Put the target address in r4; the call dummy will copy this to
1400 write_register (4, fun);
1405 This function does not support passing parameters using the FPA
1406 variant of the APCS. It passes any floating point arguments in the
1407 general registers and/or on the stack. */
1410 arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1411 int struct_return, CORE_ADDR struct_addr)
1414 int argnum, argreg, nstack_size;
1416 /* Walk through the list of args and determine how large a temporary
1417 stack is required. Need to take care here as structs may be
1418 passed on the stack, and we have to to push them. */
1419 nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
1420 if (struct_return) /* The struct address goes in A1. */
1421 nstack_size += REGISTER_SIZE;
1423 /* Walk through the arguments and add their size to nstack_size. */
1424 for (argnum = 0; argnum < nargs; argnum++)
1427 struct type *arg_type;
1429 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1430 len = TYPE_LENGTH (arg_type);
1435 /* Allocate room on the stack, and initialize our stack frame
1438 if (nstack_size > 0)
1444 /* Initialize the integer argument register pointer. */
1445 argreg = ARM_A1_REGNUM;
1447 /* The struct_return pointer occupies the first parameter passing
1450 write_register (argreg++, struct_addr);
1452 /* Process arguments from left to right. Store as many as allowed
1453 in the parameter passing registers (A1-A4), and save the rest on
1454 the temporary stack. */
1455 for (argnum = 0; argnum < nargs; argnum++)
1460 enum type_code typecode;
1461 struct type *arg_type, *target_type;
1463 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1464 target_type = TYPE_TARGET_TYPE (arg_type);
1465 len = TYPE_LENGTH (arg_type);
1466 typecode = TYPE_CODE (arg_type);
1467 val = (char *) VALUE_CONTENTS (args[argnum]);
1470 /* I don't know why this code was disable. The only logical use
1471 for a function pointer is to call that function, so setting
1472 the mode bit is perfectly fine. FN */
1473 /* If the argument is a pointer to a function, and it is a Thumb
1474 function, set the low bit of the pointer. */
1475 if (TYPE_CODE_PTR == typecode
1476 && NULL != target_type
1477 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1479 CORE_ADDR regval = extract_address (val, len);
1480 if (arm_pc_is_thumb (regval))
1481 store_address (val, len, MAKE_THUMB_ADDR (regval));
1484 /* Copy the argument to general registers or the stack in
1485 register-sized pieces. Large arguments are split between
1486 registers and stack. */
1489 int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
1491 if (argreg <= ARM_LAST_ARG_REGNUM)
1493 /* It's an argument being passed in a general register. */
1494 regval = extract_address (val, partial_len);
1495 write_register (argreg++, regval);
1499 /* Push the arguments onto the stack. */
1500 write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
1501 fp += REGISTER_SIZE;
1509 /* Return adjusted stack pointer. */
1513 /* Pop the current frame. So long as the frame info has been
1514 initialized properly (see arm_init_extra_frame_info), this code
1515 works for dummy frames as well as regular frames. I.e, there's no
1516 need to have a special case for dummy frames. */
1518 arm_pop_frame (void)
1521 struct frame_info *frame = get_current_frame ();
1522 CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset
1523 + frame->extra_info->framesize);
1525 if (USE_GENERIC_DUMMY_FRAMES
1526 && PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1528 generic_pop_dummy_frame ();
1529 flush_cached_frames ();
1533 for (regnum = 0; regnum < NUM_REGS; regnum++)
1534 if (frame->saved_regs[regnum] != 0)
1535 write_register (regnum,
1536 read_memory_integer (frame->saved_regs[regnum],
1537 REGISTER_RAW_SIZE (regnum)));
1539 write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame));
1540 write_register (ARM_SP_REGNUM, old_SP);
1542 flush_cached_frames ();
1546 print_fpu_flags (int flags)
1548 if (flags & (1 << 0))
1549 fputs ("IVO ", stdout);
1550 if (flags & (1 << 1))
1551 fputs ("DVZ ", stdout);
1552 if (flags & (1 << 2))
1553 fputs ("OFL ", stdout);
1554 if (flags & (1 << 3))
1555 fputs ("UFL ", stdout);
1556 if (flags & (1 << 4))
1557 fputs ("INX ", stdout);
1561 /* Print interesting information about the floating point processor
1562 (if present) or emulator. */
1564 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1565 struct frame_info *frame)
1567 register unsigned long status = read_register (ARM_FPS_REGNUM);
1570 type = (status >> 24) & 127;
1571 printf ("%s FPU type %d\n",
1572 (status & (1 << 31)) ? "Hardware" : "Software",
1574 fputs ("mask: ", stdout);
1575 print_fpu_flags (status >> 16);
1576 fputs ("flags: ", stdout);
1577 print_fpu_flags (status);
1580 /* Return the GDB type object for the "standard" data type of data in
1583 static struct type *
1584 arm_register_type (int regnum)
1586 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1588 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1589 return builtin_type_arm_ext_big;
1591 return builtin_type_arm_ext_littlebyte_bigword;
1594 return builtin_type_int32;
1597 /* Index within `registers' of the first byte of the space for
1601 arm_register_byte (int regnum)
1603 if (regnum < ARM_F0_REGNUM)
1604 return regnum * INT_REGISTER_RAW_SIZE;
1605 else if (regnum < ARM_PS_REGNUM)
1606 return (NUM_GREGS * INT_REGISTER_RAW_SIZE
1607 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE);
1609 return (NUM_GREGS * INT_REGISTER_RAW_SIZE
1610 + NUM_FREGS * FP_REGISTER_RAW_SIZE
1611 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1614 /* Number of bytes of storage in the actual machine representation for
1615 register N. All registers are 4 bytes, except fp0 - fp7, which are
1616 12 bytes in length. */
1619 arm_register_raw_size (int regnum)
1621 if (regnum < ARM_F0_REGNUM)
1622 return INT_REGISTER_RAW_SIZE;
1623 else if (regnum < ARM_FPS_REGNUM)
1624 return FP_REGISTER_RAW_SIZE;
1626 return STATUS_REGISTER_SIZE;
1629 /* Number of bytes of storage in a program's representation
1632 arm_register_virtual_size (int regnum)
1634 if (regnum < ARM_F0_REGNUM)
1635 return INT_REGISTER_VIRTUAL_SIZE;
1636 else if (regnum < ARM_FPS_REGNUM)
1637 return FP_REGISTER_VIRTUAL_SIZE;
1639 return STATUS_REGISTER_SIZE;
1642 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1644 arm_register_sim_regno (int regnum)
1647 gdb_assert (reg >= 0 && reg < NUM_REGS);
1649 if (reg < NUM_GREGS)
1650 return SIM_ARM_R0_REGNUM + reg;
1653 if (reg < NUM_FREGS)
1654 return SIM_ARM_FP0_REGNUM + reg;
1657 if (reg < NUM_SREGS)
1658 return SIM_ARM_FPS_REGNUM + reg;
1661 internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
1664 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1665 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1666 It is thought that this is is the floating-point register format on
1667 little-endian systems. */
1670 convert_from_extended (void *ptr, void *dbl)
1673 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1674 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1676 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1678 floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl);
1682 convert_to_extended (void *dbl, void *ptr)
1685 floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d);
1686 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1687 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1689 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1694 condition_true (unsigned long cond, unsigned long status_reg)
1696 if (cond == INST_AL || cond == INST_NV)
1702 return ((status_reg & FLAG_Z) != 0);
1704 return ((status_reg & FLAG_Z) == 0);
1706 return ((status_reg & FLAG_C) != 0);
1708 return ((status_reg & FLAG_C) == 0);
1710 return ((status_reg & FLAG_N) != 0);
1712 return ((status_reg & FLAG_N) == 0);
1714 return ((status_reg & FLAG_V) != 0);
1716 return ((status_reg & FLAG_V) == 0);
1718 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1720 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1722 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1724 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1726 return (((status_reg & FLAG_Z) == 0) &&
1727 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1729 return (((status_reg & FLAG_Z) != 0) ||
1730 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1735 /* Support routines for single stepping. Calculate the next PC value. */
1736 #define submask(x) ((1L << ((x) + 1)) - 1)
1737 #define bit(obj,st) (((obj) >> (st)) & 1)
1738 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1739 #define sbits(obj,st,fn) \
1740 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1741 #define BranchDest(addr,instr) \
1742 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1745 static unsigned long
1746 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1747 unsigned long status_reg)
1749 unsigned long res, shift;
1750 int rm = bits (inst, 0, 3);
1751 unsigned long shifttype = bits (inst, 5, 6);
1755 int rs = bits (inst, 8, 11);
1756 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1759 shift = bits (inst, 7, 11);
1762 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1763 + (bit (inst, 4) ? 12 : 8))
1764 : read_register (rm));
1769 res = shift >= 32 ? 0 : res << shift;
1773 res = shift >= 32 ? 0 : res >> shift;
1779 res = ((res & 0x80000000L)
1780 ? ~((~res) >> shift) : res >> shift);
1783 case 3: /* ROR/RRX */
1786 res = (res >> 1) | (carry ? 0x80000000L : 0);
1788 res = (res >> shift) | (res << (32 - shift));
1792 return res & 0xffffffff;
1795 /* Return number of 1-bits in VAL. */
1798 bitcount (unsigned long val)
1801 for (nbits = 0; val != 0; nbits++)
1802 val &= val - 1; /* delete rightmost 1-bit in val */
1807 thumb_get_next_pc (CORE_ADDR pc)
1809 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1810 unsigned short inst1 = read_memory_integer (pc, 2);
1811 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1812 unsigned long offset;
1814 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1818 /* Fetch the saved PC from the stack. It's stored above
1819 all of the other registers. */
1820 offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
1821 sp = read_register (ARM_SP_REGNUM);
1822 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1823 nextpc = ADDR_BITS_REMOVE (nextpc);
1825 error ("Infinite loop detected");
1827 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1829 unsigned long status = read_register (ARM_PS_REGNUM);
1830 unsigned long cond = bits (inst1, 8, 11);
1831 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1832 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1834 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1836 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1838 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
1840 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1841 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1842 nextpc = pc_val + offset;
1849 arm_get_next_pc (CORE_ADDR pc)
1851 unsigned long pc_val;
1852 unsigned long this_instr;
1853 unsigned long status;
1856 if (arm_pc_is_thumb (pc))
1857 return thumb_get_next_pc (pc);
1859 pc_val = (unsigned long) pc;
1860 this_instr = read_memory_integer (pc, 4);
1861 status = read_register (ARM_PS_REGNUM);
1862 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1864 if (condition_true (bits (this_instr, 28, 31), status))
1866 switch (bits (this_instr, 24, 27))
1869 case 0x1: /* data processing */
1873 unsigned long operand1, operand2, result = 0;
1877 if (bits (this_instr, 12, 15) != 15)
1880 if (bits (this_instr, 22, 25) == 0
1881 && bits (this_instr, 4, 7) == 9) /* multiply */
1882 error ("Illegal update to pc in instruction");
1884 /* Multiply into PC */
1885 c = (status & FLAG_C) ? 1 : 0;
1886 rn = bits (this_instr, 16, 19);
1887 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1889 if (bit (this_instr, 25))
1891 unsigned long immval = bits (this_instr, 0, 7);
1892 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1893 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1896 else /* operand 2 is a shifted register */
1897 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1899 switch (bits (this_instr, 21, 24))
1902 result = operand1 & operand2;
1906 result = operand1 ^ operand2;
1910 result = operand1 - operand2;
1914 result = operand2 - operand1;
1918 result = operand1 + operand2;
1922 result = operand1 + operand2 + c;
1926 result = operand1 - operand2 + c;
1930 result = operand2 - operand1 + c;
1936 case 0xb: /* tst, teq, cmp, cmn */
1937 result = (unsigned long) nextpc;
1941 result = operand1 | operand2;
1945 /* Always step into a function. */
1950 result = operand1 & ~operand2;
1957 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1960 error ("Infinite loop detected");
1965 case 0x5: /* data transfer */
1968 if (bit (this_instr, 20))
1971 if (bits (this_instr, 12, 15) == 15)
1977 if (bit (this_instr, 22))
1978 error ("Illegal update to pc in instruction");
1980 /* byte write to PC */
1981 rn = bits (this_instr, 16, 19);
1982 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1983 if (bit (this_instr, 24))
1986 int c = (status & FLAG_C) ? 1 : 0;
1987 unsigned long offset =
1988 (bit (this_instr, 25)
1989 ? shifted_reg_val (this_instr, c, pc_val, status)
1990 : bits (this_instr, 0, 11));
1992 if (bit (this_instr, 23))
1997 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
2000 nextpc = ADDR_BITS_REMOVE (nextpc);
2003 error ("Infinite loop detected");
2009 case 0x9: /* block transfer */
2010 if (bit (this_instr, 20))
2013 if (bit (this_instr, 15))
2018 if (bit (this_instr, 23))
2021 unsigned long reglist = bits (this_instr, 0, 14);
2022 offset = bitcount (reglist) * 4;
2023 if (bit (this_instr, 24)) /* pre */
2026 else if (bit (this_instr, 24))
2030 unsigned long rn_val =
2031 read_register (bits (this_instr, 16, 19));
2033 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2037 nextpc = ADDR_BITS_REMOVE (nextpc);
2039 error ("Infinite loop detected");
2044 case 0xb: /* branch & link */
2045 case 0xa: /* branch */
2047 nextpc = BranchDest (pc, this_instr);
2049 nextpc = ADDR_BITS_REMOVE (nextpc);
2051 error ("Infinite loop detected");
2057 case 0xe: /* coproc ops */
2062 fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
2070 /* single_step() is called just before we want to resume the inferior,
2071 if we want to single-step it but there is no hardware or kernel
2072 single-step support. We find the target of the coming instruction
2075 single_step() is also called just after the inferior stops. If we
2076 had set up a simulated single-step, we undo our damage. */
2079 arm_software_single_step (enum target_signal sig, int insert_bpt)
2081 static int next_pc; /* State between setting and unsetting. */
2082 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
2086 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
2087 target_insert_breakpoint (next_pc, break_mem);
2090 target_remove_breakpoint (next_pc, break_mem);
2093 #include "bfd-in2.h"
2094 #include "libcoff.h"
2097 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2099 if (arm_pc_is_thumb (memaddr))
2101 static asymbol *asym;
2102 static combined_entry_type ce;
2103 static struct coff_symbol_struct csym;
2104 static struct _bfd fake_bfd;
2105 static bfd_target fake_target;
2107 if (csym.native == NULL)
2109 /* Create a fake symbol vector containing a Thumb symbol.
2110 This is solely so that the code in print_insn_little_arm()
2111 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2112 the presence of a Thumb symbol and switch to decoding
2113 Thumb instructions. */
2115 fake_target.flavour = bfd_target_coff_flavour;
2116 fake_bfd.xvec = &fake_target;
2117 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2119 csym.symbol.the_bfd = &fake_bfd;
2120 csym.symbol.name = "fake";
2121 asym = (asymbol *) & csym;
2124 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2125 info->symbols = &asym;
2128 info->symbols = NULL;
2130 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2131 return print_insn_big_arm (memaddr, info);
2133 return print_insn_little_arm (memaddr, info);
2136 /* The following define instruction sequences that will cause ARM
2137 cpu's to take an undefined instruction trap. These are used to
2138 signal a breakpoint to GDB.
2140 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2141 modes. A different instruction is required for each mode. The ARM
2142 cpu's can also be big or little endian. Thus four different
2143 instructions are needed to support all cases.
2145 Note: ARMv4 defines several new instructions that will take the
2146 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2147 not in fact add the new instructions. The new undefined
2148 instructions in ARMv4 are all instructions that had no defined
2149 behaviour in earlier chips. There is no guarantee that they will
2150 raise an exception, but may be treated as NOP's. In practice, it
2151 may only safe to rely on instructions matching:
2153 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2154 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2155 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2157 Even this may only true if the condition predicate is true. The
2158 following use a condition predicate of ALWAYS so it is always TRUE.
2160 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2161 and NetBSD all use a software interrupt rather than an undefined
2162 instruction to force a trap. This can be handled by by the
2163 abi-specific code during establishment of the gdbarch vector. */
2166 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2167 override these definitions. */
2168 #ifndef ARM_LE_BREAKPOINT
2169 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2171 #ifndef ARM_BE_BREAKPOINT
2172 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2174 #ifndef THUMB_LE_BREAKPOINT
2175 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2177 #ifndef THUMB_BE_BREAKPOINT
2178 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2181 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2182 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2183 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2184 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2186 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2187 the program counter value to determine whether a 16-bit or 32-bit
2188 breakpoint should be used. It returns a pointer to a string of
2189 bytes that encode a breakpoint instruction, stores the length of
2190 the string to *lenptr, and adjusts the program counter (if
2191 necessary) to point to the actual memory location where the
2192 breakpoint should be inserted. */
2194 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2195 breakpoints and storing their handles instread of what was in
2196 memory. It is nice that this is the same size as a handle -
2197 otherwise remote-rdp will have to change. */
2199 static const unsigned char *
2200 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2202 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2204 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
2206 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2207 *lenptr = tdep->thumb_breakpoint_size;
2208 return tdep->thumb_breakpoint;
2212 *lenptr = tdep->arm_breakpoint_size;
2213 return tdep->arm_breakpoint;
2217 /* Extract from an array REGBUF containing the (raw) register state a
2218 function return value of type TYPE, and copy that, in virtual
2219 format, into VALBUF. */
2222 arm_extract_return_value (struct type *type,
2223 char regbuf[REGISTER_BYTES],
2226 if (TYPE_CODE_FLT == TYPE_CODE (type))
2228 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2230 switch (tdep->fp_model)
2233 convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)],
2237 case ARM_FLOAT_SOFT:
2238 case ARM_FLOAT_SOFT_VFP:
2239 memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)],
2240 TYPE_LENGTH (type));
2245 (__FILE__, __LINE__,
2246 "arm_extract_return_value: Floating point model not supported");
2251 memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)],
2252 TYPE_LENGTH (type));
2255 /* Extract from an array REGBUF containing the (raw) register state
2256 the address in which a function should return its structure value. */
2259 arm_extract_struct_value_address (char *regbuf)
2261 return extract_address (regbuf, REGISTER_RAW_SIZE(ARM_A1_REGNUM));
2264 /* Will a function return an aggregate type in memory or in a
2265 register? Return 0 if an aggregate type can be returned in a
2266 register, 1 if it must be returned in memory. */
2269 arm_use_struct_convention (int gcc_p, struct type *type)
2272 register enum type_code code;
2274 /* In the ARM ABI, "integer" like aggregate types are returned in
2275 registers. For an aggregate type to be integer like, its size
2276 must be less than or equal to REGISTER_SIZE and the offset of
2277 each addressable subfield must be zero. Note that bit fields are
2278 not addressable, and all addressable subfields of unions always
2279 start at offset zero.
2281 This function is based on the behaviour of GCC 2.95.1.
2282 See: gcc/arm.c: arm_return_in_memory() for details.
2284 Note: All versions of GCC before GCC 2.95.2 do not set up the
2285 parameters correctly for a function returning the following
2286 structure: struct { float f;}; This should be returned in memory,
2287 not a register. Richard Earnshaw sent me a patch, but I do not
2288 know of any way to detect if a function like the above has been
2289 compiled with the correct calling convention. */
2291 /* All aggregate types that won't fit in a register must be returned
2293 if (TYPE_LENGTH (type) > REGISTER_SIZE)
2298 /* The only aggregate types that can be returned in a register are
2299 structs and unions. Arrays must be returned in memory. */
2300 code = TYPE_CODE (type);
2301 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2306 /* Assume all other aggregate types can be returned in a register.
2307 Run a check for structures, unions and arrays. */
2310 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2313 /* Need to check if this struct/union is "integer" like. For
2314 this to be true, its size must be less than or equal to
2315 REGISTER_SIZE and the offset of each addressable subfield
2316 must be zero. Note that bit fields are not addressable, and
2317 unions always start at offset zero. If any of the subfields
2318 is a floating point type, the struct/union cannot be an
2321 /* For each field in the object, check:
2322 1) Is it FP? --> yes, nRc = 1;
2323 2) Is it addressable (bitpos != 0) and
2324 not packed (bitsize == 0)?
2328 for (i = 0; i < TYPE_NFIELDS (type); i++)
2330 enum type_code field_type_code;
2331 field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
2333 /* Is it a floating point type field? */
2334 if (field_type_code == TYPE_CODE_FLT)
2340 /* If bitpos != 0, then we have to care about it. */
2341 if (TYPE_FIELD_BITPOS (type, i) != 0)
2343 /* Bitfields are not addressable. If the field bitsize is
2344 zero, then the field is not packed. Hence it cannot be
2345 a bitfield or any other packed type. */
2346 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2358 /* Write into appropriate registers a function return value of type
2359 TYPE, given in virtual format. */
2362 arm_store_return_value (struct type *type, char *valbuf)
2364 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2366 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2367 char buf[ARM_MAX_REGISTER_RAW_SIZE];
2369 switch (tdep->fp_model)
2373 convert_to_extended (valbuf, buf);
2374 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf,
2375 FP_REGISTER_RAW_SIZE);
2378 case ARM_FLOAT_SOFT:
2379 case ARM_FLOAT_SOFT_VFP:
2380 write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type));
2385 (__FILE__, __LINE__,
2386 "arm_store_return_value: Floating point model not supported");
2391 write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type));
2394 /* Store the address of the place in which to copy the structure the
2395 subroutine will return. This is called from call_function. */
2398 arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
2400 write_register (ARM_A1_REGNUM, addr);
2404 arm_get_longjmp_target (CORE_ADDR *pc)
2407 char buf[INT_REGISTER_RAW_SIZE];
2408 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2410 jb_addr = read_register (ARM_A1_REGNUM);
2412 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2413 INT_REGISTER_RAW_SIZE))
2416 *pc = extract_address (buf, INT_REGISTER_RAW_SIZE);
2420 /* Return non-zero if the PC is inside a thumb call thunk. */
2423 arm_in_call_stub (CORE_ADDR pc, char *name)
2425 CORE_ADDR start_addr;
2427 /* Find the starting address of the function containing the PC. If
2428 the caller didn't give us a name, look it up at the same time. */
2429 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2433 return strncmp (name, "_call_via_r", 11) == 0;
2436 /* If PC is in a Thumb call or return stub, return the address of the
2437 target PC, which is in a register. The thunk functions are called
2438 _called_via_xx, where x is the register name. The possible names
2439 are r0-r9, sl, fp, ip, sp, and lr. */
2442 arm_skip_stub (CORE_ADDR pc)
2445 CORE_ADDR start_addr;
2447 /* Find the starting address and name of the function containing the PC. */
2448 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2451 /* Call thunks always start with "_call_via_". */
2452 if (strncmp (name, "_call_via_", 10) == 0)
2454 /* Use the name suffix to determine which register contains the
2456 static char *table[15] =
2457 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2458 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2462 for (regno = 0; regno <= 14; regno++)
2463 if (strcmp (&name[10], table[regno]) == 0)
2464 return read_register (regno);
2467 return 0; /* not a stub */
2470 /* If the user changes the register disassembly flavor used for info
2471 register and other commands, we have to also switch the flavor used
2472 in opcodes for disassembly output. This function is run in the set
2473 disassembly_flavor command, and does that. */
2476 set_disassembly_flavor_sfunc (char *args, int from_tty,
2477 struct cmd_list_element *c)
2479 set_disassembly_flavor ();
2482 /* Return the ARM register name corresponding to register I. */
2484 arm_register_name (int i)
2486 return arm_register_names[i];
2490 set_disassembly_flavor (void)
2492 const char *setname, *setdesc, **regnames;
2495 /* Find the flavor that the user wants in the opcodes table. */
2497 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2498 while ((disassembly_flavor != setname)
2499 && (current < num_flavor_options))
2500 get_arm_regnames (++current, &setname, &setdesc, ®names);
2501 current_option = current;
2503 /* Fill our copy. */
2504 for (j = 0; j < numregs; j++)
2505 arm_register_names[j] = (char *) regnames[j];
2508 if (isupper (*regnames[ARM_PC_REGNUM]))
2510 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2511 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2515 arm_register_names[ARM_FPS_REGNUM] = "fps";
2516 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2519 /* Synchronize the disassembler. */
2520 set_arm_regname_option (current);
2523 /* arm_othernames implements the "othernames" command. This is kind
2524 of hacky, and I prefer the set-show disassembly-flavor which is
2525 also used for the x86 gdb. I will keep this around, however, in
2526 case anyone is actually using it. */
2529 arm_othernames (char *names, int n)
2531 /* Circle through the various flavors. */
2532 current_option = (current_option + 1) % num_flavor_options;
2534 disassembly_flavor = valid_flavors[current_option];
2535 set_disassembly_flavor ();
2538 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2539 for ARM linux targets using the struct offsets defined in <link.h>.
2540 Note, however, that link.h is not actually referred to in this file.
2541 Instead, the relevant structs offsets were obtained from examining
2542 link.h. (We can't refer to link.h from this file because the host
2543 system won't necessarily have it, or if it does, the structs which
2544 it defines will refer to the host system, not the target). */
2546 struct link_map_offsets *
2547 arm_linux_svr4_fetch_link_map_offsets (void)
2549 static struct link_map_offsets lmo;
2550 static struct link_map_offsets *lmp = 0;
2556 lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
2559 lmo.r_map_offset = 4;
2562 lmo.link_map_size = 20; /* Actual size is 552, but this is all we
2565 lmo.l_addr_offset = 0;
2566 lmo.l_addr_size = 4;
2568 lmo.l_name_offset = 4;
2569 lmo.l_name_size = 4;
2571 lmo.l_next_offset = 12;
2572 lmo.l_next_size = 4;
2574 lmo.l_prev_offset = 16;
2575 lmo.l_prev_size = 4;
2581 /* Test whether the coff symbol specific value corresponds to a Thumb
2585 coff_sym_is_thumb (int val)
2587 return (val == C_THUMBEXT ||
2588 val == C_THUMBSTAT ||
2589 val == C_THUMBEXTFUNC ||
2590 val == C_THUMBSTATFUNC ||
2591 val == C_THUMBLABEL);
2594 /* arm_coff_make_msymbol_special()
2595 arm_elf_make_msymbol_special()
2597 These functions test whether the COFF or ELF symbol corresponds to
2598 an address in thumb code, and set a "special" bit in a minimal
2599 symbol to indicate that it does. */
2602 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2604 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2606 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2608 MSYMBOL_SET_SPECIAL (msym);
2612 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2614 if (coff_sym_is_thumb (val))
2615 MSYMBOL_SET_SPECIAL (msym);
2619 static enum gdb_osabi
2620 arm_elf_osabi_sniffer (bfd *abfd)
2622 unsigned int elfosabi, eflags;
2623 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2625 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2630 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2631 file are conforming to the base specification for that machine
2632 (there are no OS-specific extensions). In order to determine the
2633 real OS in use we must look for OS notes that have been added. */
2634 bfd_map_over_sections (abfd,
2635 generic_elf_osabi_sniff_abi_tag_sections,
2637 if (osabi == GDB_OSABI_UNKNOWN)
2639 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2640 field for more information. */
2641 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2644 case EF_ARM_EABI_VER1:
2645 osabi = GDB_OSABI_ARM_EABI_V1;
2648 case EF_ARM_EABI_VER2:
2649 osabi = GDB_OSABI_ARM_EABI_V2;
2652 case EF_ARM_EABI_UNKNOWN:
2653 /* Assume GNU tools. */
2654 osabi = GDB_OSABI_ARM_APCS;
2658 internal_error (__FILE__, __LINE__,
2659 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2660 "version 0x%x", eflags);
2666 /* GNU tools use this value. Check note sections in this case,
2668 bfd_map_over_sections (abfd,
2669 generic_elf_osabi_sniff_abi_tag_sections,
2671 if (osabi == GDB_OSABI_UNKNOWN)
2673 /* Assume APCS ABI. */
2674 osabi = GDB_OSABI_ARM_APCS;
2678 case ELFOSABI_FREEBSD:
2679 osabi = GDB_OSABI_FREEBSD_ELF;
2682 case ELFOSABI_NETBSD:
2683 osabi = GDB_OSABI_NETBSD_ELF;
2686 case ELFOSABI_LINUX:
2687 osabi = GDB_OSABI_LINUX;
2695 /* Initialize the current architecture based on INFO. If possible,
2696 re-use an architecture from ARCHES, which is a list of
2697 architectures already created during this debugging session.
2699 Called e.g. at program startup, when reading a core file, and when
2700 reading a binary file. */
2702 static struct gdbarch *
2703 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2705 struct gdbarch_tdep *tdep;
2706 struct gdbarch *gdbarch;
2707 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2709 /* Try to deterimine the ABI of the object we are loading. */
2711 if (info.abfd != NULL)
2713 osabi = gdbarch_lookup_osabi (info.abfd);
2714 if (osabi == GDB_OSABI_UNKNOWN)
2716 switch (bfd_get_flavour (info.abfd))
2718 case bfd_target_aout_flavour:
2719 /* Assume it's an old APCS-style ABI. */
2720 osabi = GDB_OSABI_ARM_APCS;
2723 case bfd_target_coff_flavour:
2724 /* Assume it's an old APCS-style ABI. */
2726 osabi = GDB_OSABI_ARM_APCS;
2730 /* Leave it as "unknown". */
2735 /* Find a candidate among extant architectures. */
2736 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2738 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2740 /* Make sure the ABI selection matches. */
2741 tdep = gdbarch_tdep (arches->gdbarch);
2742 if (tdep && tdep->osabi == osabi)
2743 return arches->gdbarch;
2746 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2747 gdbarch = gdbarch_alloc (&info, tdep);
2749 tdep->osabi = osabi;
2751 /* This is the way it has always defaulted. */
2752 tdep->fp_model = ARM_FLOAT_FPA;
2755 switch (info.byte_order)
2757 case BFD_ENDIAN_BIG:
2758 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2759 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2760 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2761 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2765 case BFD_ENDIAN_LITTLE:
2766 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2767 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2768 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2769 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2774 internal_error (__FILE__, __LINE__,
2775 "arm_gdbarch_init: bad byte order for float format");
2778 /* On ARM targets char defaults to unsigned. */
2779 set_gdbarch_char_signed (gdbarch, 0);
2781 /* This should be low enough for everything. */
2782 tdep->lowest_pc = 0x20;
2783 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2785 #if OLD_STYLE_ARM_DUMMY_FRAMES
2786 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2787 specific (non-generic) dummy frame code. Might be useful if
2788 there appears to be a problem with the generic dummy frame
2789 mechanism that replaced it. */
2790 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
2792 /* Call dummy code. */
2793 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2794 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
2795 /* We have to give this a value now, even though we will re-set it
2796 during each call to arm_fix_call_dummy. */
2797 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8);
2798 set_gdbarch_call_dummy_p (gdbarch, 1);
2799 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2801 set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
2802 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (arm_call_dummy_words));
2803 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2804 set_gdbarch_call_dummy_length (gdbarch, 0);
2806 set_gdbarch_fix_call_dummy (gdbarch, arm_fix_call_dummy);
2808 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack);
2810 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2811 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2813 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
2814 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2816 set_gdbarch_call_dummy_p (gdbarch, 1);
2817 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2819 set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
2820 set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
2821 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2822 set_gdbarch_call_dummy_length (gdbarch, 0);
2824 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2825 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2827 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2828 set_gdbarch_push_return_address (gdbarch, arm_push_return_address);
2831 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2832 set_gdbarch_push_arguments (gdbarch, arm_push_arguments);
2833 set_gdbarch_coerce_float_to_double (gdbarch,
2834 standard_coerce_float_to_double);
2836 /* Frame handling. */
2837 set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid);
2838 set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info);
2839 set_gdbarch_read_fp (gdbarch, arm_read_fp);
2840 set_gdbarch_frame_chain (gdbarch, arm_frame_chain);
2841 set_gdbarch_frameless_function_invocation
2842 (gdbarch, arm_frameless_function_invocation);
2843 set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc);
2844 set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address);
2845 set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address);
2846 set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args);
2847 set_gdbarch_frame_args_skip (gdbarch, 0);
2848 set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs);
2849 #if OLD_STYLE_ARM_DUMMY_FRAMES
2850 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2851 specific (non-generic) dummy frame code. Might be useful if
2852 there appears to be a problem with the generic dummy frame
2853 mechanism that replaced it. */
2854 set_gdbarch_push_dummy_frame (gdbarch, arm_push_dummy_frame);
2856 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2858 set_gdbarch_pop_frame (gdbarch, arm_pop_frame);
2860 /* Address manipulation. */
2861 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2862 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2864 /* Offset from address of function to start of its code. */
2865 set_gdbarch_function_start_offset (gdbarch, 0);
2867 /* Advance PC across function entry code. */
2868 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2870 /* Get the PC when a frame might not be available. */
2871 set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2873 /* The stack grows downward. */
2874 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2876 /* Breakpoint manipulation. */
2877 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2878 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2880 /* Information about registers, etc. */
2881 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2882 set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2883 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2884 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2885 set_gdbarch_register_byte (gdbarch, arm_register_byte);
2886 set_gdbarch_register_bytes (gdbarch,
2887 (NUM_GREGS * INT_REGISTER_RAW_SIZE
2888 + NUM_FREGS * FP_REGISTER_RAW_SIZE
2889 + NUM_SREGS * STATUS_REGISTER_SIZE));
2890 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2891 set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size);
2892 set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size);
2893 set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
2894 set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
2895 set_gdbarch_register_virtual_type (gdbarch, arm_register_type);
2897 /* Internal <-> external register number maps. */
2898 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2900 /* Integer registers are 4 bytes. */
2901 set_gdbarch_register_size (gdbarch, 4);
2902 set_gdbarch_register_name (gdbarch, arm_register_name);
2904 /* Returning results. */
2905 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2906 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
2907 set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return);
2908 set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
2909 set_gdbarch_extract_struct_value_address (gdbarch,
2910 arm_extract_struct_value_address);
2912 /* Single stepping. */
2913 /* XXX For an RDI target we should ask the target if it can single-step. */
2914 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2916 /* Minsymbol frobbing. */
2917 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2918 set_gdbarch_coff_make_msymbol_special (gdbarch,
2919 arm_coff_make_msymbol_special);
2921 /* Hook in the ABI-specific overrides, if they have been registered. */
2922 gdbarch_init_osabi (info, gdbarch, osabi);
2924 /* Now we have tuned the configuration, set a few final things,
2925 based on what the OS ABI has told us. */
2927 if (tdep->jb_pc >= 0)
2928 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2930 /* Floating point sizes and format. */
2931 switch (info.byte_order)
2933 case BFD_ENDIAN_BIG:
2934 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2935 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2936 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2940 case BFD_ENDIAN_LITTLE:
2941 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2942 if (tdep->fp_model == ARM_FLOAT_VFP
2943 || tdep->fp_model == ARM_FLOAT_SOFT_VFP)
2945 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2946 set_gdbarch_long_double_format (gdbarch,
2947 &floatformat_ieee_double_little);
2951 set_gdbarch_double_format
2952 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2953 set_gdbarch_long_double_format
2954 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2959 internal_error (__FILE__, __LINE__,
2960 "arm_gdbarch_init: bad byte order for float format");
2963 /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
2964 references the old architecture vector, not the one we are
2966 if (prologue_cache.saved_regs != NULL)
2967 xfree (prologue_cache.saved_regs);
2969 /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
2970 references the old architecture vector, not the one we are
2972 prologue_cache.saved_regs = (CORE_ADDR *)
2973 xcalloc (1, (sizeof (CORE_ADDR)
2974 * (gdbarch_num_regs (gdbarch)
2975 + gdbarch_num_pseudo_regs (gdbarch))));
2981 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2983 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2988 fprintf_unfiltered (file, "arm_dump_tdep: OS ABI = %s\n",
2989 gdbarch_osabi_name (tdep->osabi));
2991 fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
2992 (unsigned long) tdep->lowest_pc);
2996 arm_init_abi_eabi_v1 (struct gdbarch_info info,
2997 struct gdbarch *gdbarch)
3003 arm_init_abi_eabi_v2 (struct gdbarch_info info,
3004 struct gdbarch *gdbarch)
3010 arm_init_abi_apcs (struct gdbarch_info info,
3011 struct gdbarch *gdbarch)
3017 _initialize_arm_tdep (void)
3019 struct ui_file *stb;
3021 struct cmd_list_element *new_cmd;
3022 const char *setname;
3023 const char *setdesc;
3024 const char **regnames;
3026 static char *helptext;
3029 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3031 /* Register an ELF OS ABI sniffer for ARM binaries. */
3032 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3033 bfd_target_elf_flavour,
3034 arm_elf_osabi_sniffer);
3036 /* Register some ABI variants for embedded systems. */
3037 gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V1,
3038 arm_init_abi_eabi_v1);
3039 gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V2,
3040 arm_init_abi_eabi_v2);
3041 gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_APCS,
3044 tm_print_insn = gdb_print_insn_arm;
3046 /* Get the number of possible sets of register names defined in opcodes. */
3047 num_flavor_options = get_arm_regname_num_options ();
3049 /* Sync the opcode insn printer with our register viewer. */
3050 parse_arm_disassembler_option ("reg-names-std");
3052 /* Begin creating the help text. */
3053 stb = mem_fileopen ();
3054 fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
3055 The valid values are:\n");
3057 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3058 valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
3059 for (i = 0; i < num_flavor_options; i++)
3061 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3062 valid_flavors[i] = setname;
3063 fprintf_unfiltered (stb, "%s - %s\n", setname,
3065 /* Copy the default names (if found) and synchronize disassembler. */
3066 if (!strcmp (setname, "std"))
3068 disassembly_flavor = setname;
3070 for (j = 0; j < numregs; j++)
3071 arm_register_names[j] = (char *) regnames[j];
3072 set_arm_regname_option (i);
3075 /* Mark the end of valid options. */
3076 valid_flavors[num_flavor_options] = NULL;
3078 /* Finish the creation of the help text. */
3079 fprintf_unfiltered (stb, "The default is \"std\".");
3080 helptext = ui_file_xstrdup (stb, &length);
3081 ui_file_delete (stb);
3083 /* Add the disassembly-flavor command. */
3084 new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
3086 &disassembly_flavor,
3089 set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc);
3090 add_show_from_set (new_cmd, &showlist);
3092 /* ??? Maybe this should be a boolean. */
3093 add_show_from_set (add_set_cmd ("apcs32", no_class,
3094 var_zinteger, (char *) &arm_apcs_32,
3095 "Set usage of ARM 32-bit mode.\n", &setlist),
3098 /* Add the deprecated "othernames" command. */
3100 add_com ("othernames", class_obscure, arm_othernames,
3101 "Switch to the next set of register names.");
3103 /* Fill in the prologue_cache fields. */
3104 prologue_cache.saved_regs = NULL;
3105 prologue_cache.extra_info = (struct frame_extra_info *)
3106 xcalloc (1, sizeof (struct frame_extra_info));