1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
59 #include "record-full.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data *arm_objfile_data_key;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
93 DEF_VEC_O(arm_mapping_symbol_s);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s) **section_maps;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element *setarmcmdlist = NULL;
102 static struct cmd_list_element *showarmcmdlist = NULL;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
118 static const char *current_fp_model = "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
131 static const char *arm_abi_string = "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings[] =
142 static const char *arm_fallback_mode_string = "auto";
143 static const char *arm_force_mode_string = "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode = -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element *);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat *, const void *,
229 static void convert_to_extended (const struct floatformat *, void *,
232 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
233 struct regcache *regcache,
234 int regnum, gdb_byte *buf);
235 static void arm_neon_quad_write (struct gdbarch *gdbarch,
236 struct regcache *regcache,
237 int regnum, const gdb_byte *buf);
239 static int thumb_insn_size (unsigned short inst1);
241 struct arm_prologue_cache
243 /* The stack pointer at the time this frame was created; i.e. the
244 caller's stack pointer when this function was called. It is used
245 to identify this frame. */
248 /* The frame base for this frame is just prev_sp - frame size.
249 FRAMESIZE is the distance from the frame pointer to the
250 initial stack pointer. */
254 /* The register used to hold the frame pointer for this frame. */
257 /* Saved register offsets. */
258 struct trad_frame_saved_reg *saved_regs;
261 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
262 CORE_ADDR prologue_start,
263 CORE_ADDR prologue_end,
264 struct arm_prologue_cache *cache);
266 /* Architecture version for displaced stepping. This effects the behaviour of
267 certain instructions, and really should not be hard-wired. */
269 #define DISPLACED_STEPPING_ARCH_VERSION 5
271 /* Addresses for calling Thumb functions have the bit 0 set.
272 Here are some macros to test, set, or clear bit 0 of addresses. */
273 #define IS_THUMB_ADDR(addr) ((addr) & 1)
274 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
275 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch *gdbarch)
286 if (gdbarch_tdep (gdbarch)->is_m)
292 /* Determine if FRAME is executing in Thumb mode. */
295 arm_frame_is_thumb (struct frame_info *frame)
298 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
300 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
301 directly (from a signal frame or dummy frame) or by interpreting
302 the saved LR (from a prologue or DWARF frame). So consult it and
303 trust the unwinders. */
304 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
306 return (cpsr & t_bit) != 0;
309 /* Callback for VEC_lower_bound. */
312 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
313 const struct arm_mapping_symbol *rhs)
315 return lhs->value < rhs->value;
318 /* Search for the mapping symbol covering MEMADDR. If one is found,
319 return its type. Otherwise, return 0. If START is non-NULL,
320 set *START to the location of the mapping symbol. */
323 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
325 struct obj_section *sec;
327 /* If there are mapping symbols, consult them. */
328 sec = find_pc_section (memaddr);
331 struct arm_per_objfile *data;
332 VEC(arm_mapping_symbol_s) *map;
333 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
337 data = objfile_data (sec->objfile, arm_objfile_data_key);
340 map = data->section_maps[sec->the_bfd_section->index];
341 if (!VEC_empty (arm_mapping_symbol_s, map))
343 struct arm_mapping_symbol *map_sym;
345 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
346 arm_compare_mapping_symbols);
348 /* VEC_lower_bound finds the earliest ordered insertion
349 point. If the following symbol starts at this exact
350 address, we use that; otherwise, the preceding
351 mapping symbol covers this address. */
352 if (idx < VEC_length (arm_mapping_symbol_s, map))
354 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
355 if (map_sym->value == map_key.value)
358 *start = map_sym->value + obj_section_addr (sec);
359 return map_sym->type;
365 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
367 *start = map_sym->value + obj_section_addr (sec);
368 return map_sym->type;
377 /* Determine if the program counter specified in MEMADDR is in a Thumb
378 function. This function should be called for addresses unrelated to
379 any executing frame; otherwise, prefer arm_frame_is_thumb. */
382 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
384 struct bound_minimal_symbol sym;
386 struct displaced_step_closure* dsc
387 = get_displaced_step_closure_by_addr(memaddr);
389 /* If checking the mode of displaced instruction in copy area, the mode
390 should be determined by instruction on the original address. */
394 fprintf_unfiltered (gdb_stdlog,
395 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (unsigned long) dsc->insn_addr,
397 (unsigned long) memaddr);
398 memaddr = dsc->insn_addr;
401 /* If bit 0 of the address is set, assume this is a Thumb address. */
402 if (IS_THUMB_ADDR (memaddr))
405 /* Respect internal mode override if active. */
406 if (arm_override_mode != -1)
407 return arm_override_mode;
409 /* If the user wants to override the symbol table, let him. */
410 if (strcmp (arm_force_mode_string, "arm") == 0)
412 if (strcmp (arm_force_mode_string, "thumb") == 0)
415 /* ARM v6-M and v7-M are always in Thumb mode. */
416 if (gdbarch_tdep (gdbarch)->is_m)
419 /* If there are mapping symbols, consult them. */
420 type = arm_find_mapping_symbol (memaddr, NULL);
424 /* Thumb functions have a "special" bit set in minimal symbols. */
425 sym = lookup_minimal_symbol_by_pc (memaddr);
427 return (MSYMBOL_IS_SPECIAL (sym.minsym));
429 /* If the user wants to override the fallback mode, let them. */
430 if (strcmp (arm_fallback_mode_string, "arm") == 0)
432 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
435 /* If we couldn't find any symbol, but we're talking to a running
436 target, then trust the current value of $cpsr. This lets
437 "display/i $pc" always show the correct mode (though if there is
438 a symbol table we will not reach here, so it still may not be
439 displayed in the mode it will be executed). */
440 if (target_has_registers)
441 return arm_frame_is_thumb (get_current_frame ());
443 /* Otherwise we're out of luck; we assume ARM. */
447 /* Remove useless bits from addresses in a running program. */
449 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
451 /* On M-profile devices, do not strip the low bit from EXC_RETURN
452 (the magic exception return address). */
453 if (gdbarch_tdep (gdbarch)->is_m
454 && (val & 0xfffffff0) == 0xfffffff0)
458 return UNMAKE_THUMB_ADDR (val);
460 return (val & 0x03fffffc);
463 /* Return 1 if PC is the start of a compiler helper function which
464 can be safely ignored during prologue skipping. IS_THUMB is true
465 if the function is known to be a Thumb function due to the way it
468 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
470 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
471 struct bound_minimal_symbol msym;
473 msym = lookup_minimal_symbol_by_pc (pc);
474 if (msym.minsym != NULL
475 && SYMBOL_VALUE_ADDRESS (msym.minsym) == pc
476 && SYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
478 const char *name = SYMBOL_LINKAGE_NAME (msym.minsym);
480 /* The GNU linker's Thumb call stub to foo is named
482 if (strstr (name, "_from_thumb") != NULL)
485 /* On soft-float targets, __truncdfsf2 is called to convert promoted
486 arguments to their argument types in non-prototyped
488 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
490 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
493 /* Internal functions related to thread-local storage. */
494 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
496 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
501 /* If we run against a stripped glibc, we may be unable to identify
502 special functions by name. Check for one important case,
503 __aeabi_read_tp, by comparing the *code* against the default
504 implementation (this is hand-written ARM assembler in glibc). */
507 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
508 == 0xe3e00a0f /* mov r0, #0xffff0fff */
509 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
510 == 0xe240f01f) /* sub pc, r0, #31 */
517 /* Support routines for instruction parsing. */
518 #define submask(x) ((1L << ((x) + 1)) - 1)
519 #define bit(obj,st) (((obj) >> (st)) & 1)
520 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
521 #define sbits(obj,st,fn) \
522 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
523 #define BranchDest(addr,instr) \
524 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
526 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
527 the first 16-bit of instruction, and INSN2 is the second 16-bit of
529 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
530 ((bits ((insn1), 0, 3) << 12) \
531 | (bits ((insn1), 10, 10) << 11) \
532 | (bits ((insn2), 12, 14) << 8) \
533 | bits ((insn2), 0, 7))
535 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
536 the 32-bit instruction. */
537 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
538 ((bits ((insn), 16, 19) << 12) \
539 | bits ((insn), 0, 11))
541 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
544 thumb_expand_immediate (unsigned int imm)
546 unsigned int count = imm >> 7;
554 return (imm & 0xff) | ((imm & 0xff) << 16);
556 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
558 return (imm & 0xff) | ((imm & 0xff) << 8)
559 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
562 return (0x80 | (imm & 0x7f)) << (32 - count);
565 /* Return 1 if the 16-bit Thumb instruction INST might change
566 control flow, 0 otherwise. */
569 thumb_instruction_changes_pc (unsigned short inst)
571 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
574 if ((inst & 0xf000) == 0xd000) /* conditional branch */
577 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
580 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
583 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
586 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
592 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
593 might change control flow, 0 otherwise. */
596 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
598 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
600 /* Branches and miscellaneous control instructions. */
602 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
607 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
609 /* SUBS PC, LR, #imm8. */
612 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
614 /* Conditional branch. */
621 if ((inst1 & 0xfe50) == 0xe810)
623 /* Load multiple or RFE. */
625 if (bit (inst1, 7) && !bit (inst1, 8))
631 else if (!bit (inst1, 7) && bit (inst1, 8))
637 else if (bit (inst1, 7) && bit (inst1, 8))
642 else if (!bit (inst1, 7) && !bit (inst1, 8))
651 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
653 /* MOV PC or MOVS PC. */
657 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
660 if (bits (inst1, 0, 3) == 15)
666 if ((inst2 & 0x0fc0) == 0x0000)
672 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
678 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
687 /* Analyze a Thumb prologue, looking for a recognizable stack frame
688 and frame pointer. Scan until we encounter a store that could
689 clobber the stack frame unexpectedly, or an unknown instruction.
690 Return the last address which is definitely safe to skip for an
691 initial breakpoint. */
694 thumb_analyze_prologue (struct gdbarch *gdbarch,
695 CORE_ADDR start, CORE_ADDR limit,
696 struct arm_prologue_cache *cache)
698 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
699 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
702 struct pv_area *stack;
703 struct cleanup *back_to;
705 CORE_ADDR unrecognized_pc = 0;
707 for (i = 0; i < 16; i++)
708 regs[i] = pv_register (i, 0);
709 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
710 back_to = make_cleanup_free_pv_area (stack);
712 while (start < limit)
716 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
718 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
723 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
726 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
727 whether to save LR (R14). */
728 mask = (insn & 0xff) | ((insn & 0x100) << 6);
730 /* Calculate offsets of saved R0-R7 and LR. */
731 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
732 if (mask & (1 << regno))
734 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
736 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
739 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
742 offset = (insn & 0x7f) << 2; /* get scaled offset */
743 if (insn & 0x80) /* Check for SUB. */
744 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
747 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
750 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
751 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
753 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
754 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
755 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
757 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
758 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
759 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
761 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
762 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
763 && pv_is_constant (regs[bits (insn, 3, 5)]))
764 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
765 regs[bits (insn, 6, 8)]);
766 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
767 && pv_is_constant (regs[bits (insn, 3, 6)]))
769 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
770 int rm = bits (insn, 3, 6);
771 regs[rd] = pv_add (regs[rd], regs[rm]);
773 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
775 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
776 int src_reg = (insn & 0x78) >> 3;
777 regs[dst_reg] = regs[src_reg];
779 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
781 /* Handle stores to the stack. Normally pushes are used,
782 but with GCC -mtpcs-frame, there may be other stores
783 in the prologue to create the frame. */
784 int regno = (insn >> 8) & 0x7;
787 offset = (insn & 0xff) << 2;
788 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
790 if (pv_area_store_would_trash (stack, addr))
793 pv_area_store (stack, addr, 4, regs[regno]);
795 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
797 int rd = bits (insn, 0, 2);
798 int rn = bits (insn, 3, 5);
801 offset = bits (insn, 6, 10) << 2;
802 addr = pv_add_constant (regs[rn], offset);
804 if (pv_area_store_would_trash (stack, addr))
807 pv_area_store (stack, addr, 4, regs[rd]);
809 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
810 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
811 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
812 /* Ignore stores of argument registers to the stack. */
814 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
815 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
816 /* Ignore block loads from the stack, potentially copying
817 parameters from memory. */
819 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
820 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
821 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
822 /* Similarly ignore single loads from the stack. */
824 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
825 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
826 /* Skip register copies, i.e. saves to another register
827 instead of the stack. */
829 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
830 /* Recognize constant loads; even with small stacks these are necessary
832 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
833 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
835 /* Constant pool loads, for the same reason. */
836 unsigned int constant;
839 loc = start + 4 + bits (insn, 0, 7) * 4;
840 constant = read_memory_unsigned_integer (loc, 4, byte_order);
841 regs[bits (insn, 8, 10)] = pv_constant (constant);
843 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
845 unsigned short inst2;
847 inst2 = read_memory_unsigned_integer (start + 2, 2,
848 byte_order_for_code);
850 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
852 /* BL, BLX. Allow some special function calls when
853 skipping the prologue; GCC generates these before
854 storing arguments to the stack. */
856 int j1, j2, imm1, imm2;
858 imm1 = sbits (insn, 0, 10);
859 imm2 = bits (inst2, 0, 10);
860 j1 = bit (inst2, 13);
861 j2 = bit (inst2, 11);
863 offset = ((imm1 << 12) + (imm2 << 1));
864 offset ^= ((!j2) << 22) | ((!j1) << 23);
866 nextpc = start + 4 + offset;
867 /* For BLX make sure to clear the low bits. */
868 if (bit (inst2, 12) == 0)
869 nextpc = nextpc & 0xfffffffc;
871 if (!skip_prologue_function (gdbarch, nextpc,
872 bit (inst2, 12) != 0))
876 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
878 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
880 pv_t addr = regs[bits (insn, 0, 3)];
883 if (pv_area_store_would_trash (stack, addr))
886 /* Calculate offsets of saved registers. */
887 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
888 if (inst2 & (1 << regno))
890 addr = pv_add_constant (addr, -4);
891 pv_area_store (stack, addr, 4, regs[regno]);
895 regs[bits (insn, 0, 3)] = addr;
898 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
900 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
902 int regno1 = bits (inst2, 12, 15);
903 int regno2 = bits (inst2, 8, 11);
904 pv_t addr = regs[bits (insn, 0, 3)];
906 offset = inst2 & 0xff;
908 addr = pv_add_constant (addr, offset);
910 addr = pv_add_constant (addr, -offset);
912 if (pv_area_store_would_trash (stack, addr))
915 pv_area_store (stack, addr, 4, regs[regno1]);
916 pv_area_store (stack, pv_add_constant (addr, 4),
920 regs[bits (insn, 0, 3)] = addr;
923 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
924 && (inst2 & 0x0c00) == 0x0c00
925 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
927 int regno = bits (inst2, 12, 15);
928 pv_t addr = regs[bits (insn, 0, 3)];
930 offset = inst2 & 0xff;
932 addr = pv_add_constant (addr, offset);
934 addr = pv_add_constant (addr, -offset);
936 if (pv_area_store_would_trash (stack, addr))
939 pv_area_store (stack, addr, 4, regs[regno]);
942 regs[bits (insn, 0, 3)] = addr;
945 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
946 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
948 int regno = bits (inst2, 12, 15);
951 offset = inst2 & 0xfff;
952 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
954 if (pv_area_store_would_trash (stack, addr))
957 pv_area_store (stack, addr, 4, regs[regno]);
960 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
961 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
962 /* Ignore stores of argument registers to the stack. */
965 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
966 && (inst2 & 0x0d00) == 0x0c00
967 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
968 /* Ignore stores of argument registers to the stack. */
971 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
973 && (inst2 & 0x8000) == 0x0000
974 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
975 /* Ignore block loads from the stack, potentially copying
976 parameters from memory. */
979 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
981 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
982 /* Similarly ignore dual loads from the stack. */
985 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
986 && (inst2 & 0x0d00) == 0x0c00
987 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
988 /* Similarly ignore single loads from the stack. */
991 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
992 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
993 /* Similarly ignore single loads from the stack. */
996 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
997 && (inst2 & 0x8000) == 0x0000)
999 unsigned int imm = ((bits (insn, 10, 10) << 11)
1000 | (bits (inst2, 12, 14) << 8)
1001 | bits (inst2, 0, 7));
1003 regs[bits (inst2, 8, 11)]
1004 = pv_add_constant (regs[bits (insn, 0, 3)],
1005 thumb_expand_immediate (imm));
1008 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1009 && (inst2 & 0x8000) == 0x0000)
1011 unsigned int imm = ((bits (insn, 10, 10) << 11)
1012 | (bits (inst2, 12, 14) << 8)
1013 | bits (inst2, 0, 7));
1015 regs[bits (inst2, 8, 11)]
1016 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1019 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1020 && (inst2 & 0x8000) == 0x0000)
1022 unsigned int imm = ((bits (insn, 10, 10) << 11)
1023 | (bits (inst2, 12, 14) << 8)
1024 | bits (inst2, 0, 7));
1026 regs[bits (inst2, 8, 11)]
1027 = pv_add_constant (regs[bits (insn, 0, 3)],
1028 - (CORE_ADDR) thumb_expand_immediate (imm));
1031 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1032 && (inst2 & 0x8000) == 0x0000)
1034 unsigned int imm = ((bits (insn, 10, 10) << 11)
1035 | (bits (inst2, 12, 14) << 8)
1036 | bits (inst2, 0, 7));
1038 regs[bits (inst2, 8, 11)]
1039 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1042 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1044 unsigned int imm = ((bits (insn, 10, 10) << 11)
1045 | (bits (inst2, 12, 14) << 8)
1046 | bits (inst2, 0, 7));
1048 regs[bits (inst2, 8, 11)]
1049 = pv_constant (thumb_expand_immediate (imm));
1052 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1055 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1057 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1060 else if (insn == 0xea5f /* mov.w Rd,Rm */
1061 && (inst2 & 0xf0f0) == 0)
1063 int dst_reg = (inst2 & 0x0f00) >> 8;
1064 int src_reg = inst2 & 0xf;
1065 regs[dst_reg] = regs[src_reg];
1068 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1070 /* Constant pool loads. */
1071 unsigned int constant;
1074 offset = bits (insn, 0, 11);
1076 loc = start + 4 + offset;
1078 loc = start + 4 - offset;
1080 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1081 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1084 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1086 /* Constant pool loads. */
1087 unsigned int constant;
1090 offset = bits (insn, 0, 7) << 2;
1092 loc = start + 4 + offset;
1094 loc = start + 4 - offset;
1096 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1097 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1099 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1100 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1103 else if (thumb2_instruction_changes_pc (insn, inst2))
1105 /* Don't scan past anything that might change control flow. */
1110 /* The optimizer might shove anything into the prologue,
1111 so we just skip what we don't recognize. */
1112 unrecognized_pc = start;
1117 else if (thumb_instruction_changes_pc (insn))
1119 /* Don't scan past anything that might change control flow. */
1124 /* The optimizer might shove anything into the prologue,
1125 so we just skip what we don't recognize. */
1126 unrecognized_pc = start;
1133 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1134 paddress (gdbarch, start));
1136 if (unrecognized_pc == 0)
1137 unrecognized_pc = start;
1141 do_cleanups (back_to);
1142 return unrecognized_pc;
1145 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1147 /* Frame pointer is fp. Frame size is constant. */
1148 cache->framereg = ARM_FP_REGNUM;
1149 cache->framesize = -regs[ARM_FP_REGNUM].k;
1151 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1153 /* Frame pointer is r7. Frame size is constant. */
1154 cache->framereg = THUMB_FP_REGNUM;
1155 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1159 /* Try the stack pointer... this is a bit desperate. */
1160 cache->framereg = ARM_SP_REGNUM;
1161 cache->framesize = -regs[ARM_SP_REGNUM].k;
1164 for (i = 0; i < 16; i++)
1165 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1166 cache->saved_regs[i].addr = offset;
1168 do_cleanups (back_to);
1169 return unrecognized_pc;
1173 /* Try to analyze the instructions starting from PC, which load symbol
1174 __stack_chk_guard. Return the address of instruction after loading this
1175 symbol, set the dest register number to *BASEREG, and set the size of
1176 instructions for loading symbol in OFFSET. Return 0 if instructions are
1180 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1181 unsigned int *destreg, int *offset)
1183 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1184 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1185 unsigned int low, high, address;
1190 unsigned short insn1
1191 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1193 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1195 *destreg = bits (insn1, 8, 10);
1197 address = bits (insn1, 0, 7);
1199 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1201 unsigned short insn2
1202 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1204 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1207 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1209 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1211 /* movt Rd, #const */
1212 if ((insn1 & 0xfbc0) == 0xf2c0)
1214 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1215 *destreg = bits (insn2, 8, 11);
1217 address = (high << 16 | low);
1224 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1226 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1228 address = bits (insn, 0, 11);
1229 *destreg = bits (insn, 12, 15);
1232 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1234 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1237 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1239 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1241 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1242 *destreg = bits (insn, 12, 15);
1244 address = (high << 16 | low);
1252 /* Try to skip a sequence of instructions used for stack protector. If PC
1253 points to the first instruction of this sequence, return the address of
1254 first instruction after this sequence, otherwise, return original PC.
1256 On arm, this sequence of instructions is composed of mainly three steps,
1257 Step 1: load symbol __stack_chk_guard,
1258 Step 2: load from address of __stack_chk_guard,
1259 Step 3: store it to somewhere else.
1261 Usually, instructions on step 2 and step 3 are the same on various ARM
1262 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1263 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1264 instructions in step 1 vary from different ARM architectures. On ARMv7,
1267 movw Rn, #:lower16:__stack_chk_guard
1268 movt Rn, #:upper16:__stack_chk_guard
1275 .word __stack_chk_guard
1277 Since ldr/str is a very popular instruction, we can't use them as
1278 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1279 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1280 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1283 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1285 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1286 unsigned int basereg;
1287 struct bound_minimal_symbol stack_chk_guard;
1289 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1292 /* Try to parse the instructions in Step 1. */
1293 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1298 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1299 /* If name of symbol doesn't start with '__stack_chk_guard', this
1300 instruction sequence is not for stack protector. If symbol is
1301 removed, we conservatively think this sequence is for stack protector. */
1302 if (stack_chk_guard.minsym
1303 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard.minsym),
1304 "__stack_chk_guard",
1305 strlen ("__stack_chk_guard")) != 0)
1310 unsigned int destreg;
1312 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1314 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1315 if ((insn & 0xf800) != 0x6800)
1317 if (bits (insn, 3, 5) != basereg)
1319 destreg = bits (insn, 0, 2);
1321 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1322 byte_order_for_code);
1323 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1324 if ((insn & 0xf800) != 0x6000)
1326 if (destreg != bits (insn, 0, 2))
1331 unsigned int destreg;
1333 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1335 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1336 if ((insn & 0x0e500000) != 0x04100000)
1338 if (bits (insn, 16, 19) != basereg)
1340 destreg = bits (insn, 12, 15);
1341 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1342 insn = read_memory_unsigned_integer (pc + offset + 4,
1343 4, byte_order_for_code);
1344 if ((insn & 0x0e500000) != 0x04000000)
1346 if (bits (insn, 12, 15) != destreg)
1349 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1352 return pc + offset + 4;
1354 return pc + offset + 8;
1357 /* Advance the PC across any function entry prologue instructions to
1358 reach some "real" code.
1360 The APCS (ARM Procedure Call Standard) defines the following
1364 [stmfd sp!, {a1,a2,a3,a4}]
1365 stmfd sp!, {...,fp,ip,lr,pc}
1366 [stfe f7, [sp, #-12]!]
1367 [stfe f6, [sp, #-12]!]
1368 [stfe f5, [sp, #-12]!]
1369 [stfe f4, [sp, #-12]!]
1370 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1373 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1375 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1378 CORE_ADDR func_addr, limit_pc;
1380 /* See if we can determine the end of the prologue via the symbol table.
1381 If so, then return either PC, or the PC after the prologue, whichever
1383 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1385 CORE_ADDR post_prologue_pc
1386 = skip_prologue_using_sal (gdbarch, func_addr);
1387 struct symtab *s = find_pc_symtab (func_addr);
1389 if (post_prologue_pc)
1391 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1394 /* GCC always emits a line note before the prologue and another
1395 one after, even if the two are at the same address or on the
1396 same line. Take advantage of this so that we do not need to
1397 know every instruction that might appear in the prologue. We
1398 will have producer information for most binaries; if it is
1399 missing (e.g. for -gstabs), assuming the GNU tools. */
1400 if (post_prologue_pc
1402 || s->producer == NULL
1403 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0
1404 || strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
1405 return post_prologue_pc;
1407 if (post_prologue_pc != 0)
1409 CORE_ADDR analyzed_limit;
1411 /* For non-GCC compilers, make sure the entire line is an
1412 acceptable prologue; GDB will round this function's
1413 return value up to the end of the following line so we
1414 can not skip just part of a line (and we do not want to).
1416 RealView does not treat the prologue specially, but does
1417 associate prologue code with the opening brace; so this
1418 lets us skip the first line if we think it is the opening
1420 if (arm_pc_is_thumb (gdbarch, func_addr))
1421 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1422 post_prologue_pc, NULL);
1424 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1425 post_prologue_pc, NULL);
1427 if (analyzed_limit != post_prologue_pc)
1430 return post_prologue_pc;
1434 /* Can't determine prologue from the symbol table, need to examine
1437 /* Find an upper limit on the function prologue using the debug
1438 information. If the debug information could not be used to provide
1439 that bound, then use an arbitrary large number as the upper bound. */
1440 /* Like arm_scan_prologue, stop no later than pc + 64. */
1441 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1443 limit_pc = pc + 64; /* Magic. */
1446 /* Check if this is Thumb code. */
1447 if (arm_pc_is_thumb (gdbarch, pc))
1448 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1450 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1452 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1454 /* "mov ip, sp" is no longer a required part of the prologue. */
1455 if (inst == 0xe1a0c00d) /* mov ip, sp */
1458 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1461 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1464 /* Some prologues begin with "str lr, [sp, #-4]!". */
1465 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1468 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1471 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1474 /* Any insns after this point may float into the code, if it makes
1475 for better instruction scheduling, so we skip them only if we
1476 find them, but still consider the function to be frame-ful. */
1478 /* We may have either one sfmfd instruction here, or several stfe
1479 insns, depending on the version of floating point code we
1481 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1484 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1487 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1490 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1493 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1494 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1495 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1498 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1499 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1500 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1503 /* Un-recognized instruction; stop scanning. */
1507 return skip_pc; /* End of prologue. */
1511 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1512 This function decodes a Thumb function prologue to determine:
1513 1) the size of the stack frame
1514 2) which registers are saved on it
1515 3) the offsets of saved regs
1516 4) the offset from the stack pointer to the frame pointer
1518 A typical Thumb function prologue would create this stack frame
1519 (offsets relative to FP)
1520 old SP -> 24 stack parameters
1523 R7 -> 0 local variables (16 bytes)
1524 SP -> -12 additional stack space (12 bytes)
1525 The frame size would thus be 36 bytes, and the frame offset would be
1526 12 bytes. The frame register is R7.
1528 The comments for thumb_skip_prolog() describe the algorithm we use
1529 to detect the end of the prolog. */
1533 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1534 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1536 CORE_ADDR prologue_start;
1537 CORE_ADDR prologue_end;
1539 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1542 /* See comment in arm_scan_prologue for an explanation of
1544 if (prologue_end > prologue_start + 64)
1546 prologue_end = prologue_start + 64;
1550 /* We're in the boondocks: we have no idea where the start of the
1554 prologue_end = min (prologue_end, prev_pc);
1556 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1559 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1562 arm_instruction_changes_pc (uint32_t this_instr)
1564 if (bits (this_instr, 28, 31) == INST_NV)
1565 /* Unconditional instructions. */
1566 switch (bits (this_instr, 24, 27))
1570 /* Branch with Link and change to Thumb. */
1575 /* Coprocessor register transfer. */
1576 if (bits (this_instr, 12, 15) == 15)
1577 error (_("Invalid update to pc in instruction"));
1583 switch (bits (this_instr, 25, 27))
1586 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1588 /* Multiplies and extra load/stores. */
1589 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1590 /* Neither multiplies nor extension load/stores are allowed
1594 /* Otherwise, miscellaneous instructions. */
1596 /* BX <reg>, BXJ <reg>, BLX <reg> */
1597 if (bits (this_instr, 4, 27) == 0x12fff1
1598 || bits (this_instr, 4, 27) == 0x12fff2
1599 || bits (this_instr, 4, 27) == 0x12fff3)
1602 /* Other miscellaneous instructions are unpredictable if they
1606 /* Data processing instruction. Fall through. */
1609 if (bits (this_instr, 12, 15) == 15)
1616 /* Media instructions and architecturally undefined instructions. */
1617 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1621 if (bit (this_instr, 20) == 0)
1625 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1631 /* Load/store multiple. */
1632 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1638 /* Branch and branch with link. */
1643 /* Coprocessor transfers or SWIs can not affect PC. */
1647 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1651 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1652 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1653 fill it in. Return the first address not recognized as a prologue
1656 We recognize all the instructions typically found in ARM prologues,
1657 plus harmless instructions which can be skipped (either for analysis
1658 purposes, or a more restrictive set that can be skipped when finding
1659 the end of the prologue). */
1662 arm_analyze_prologue (struct gdbarch *gdbarch,
1663 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1664 struct arm_prologue_cache *cache)
1666 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1667 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1669 CORE_ADDR offset, current_pc;
1670 pv_t regs[ARM_FPS_REGNUM];
1671 struct pv_area *stack;
1672 struct cleanup *back_to;
1673 int framereg, framesize;
1674 CORE_ADDR unrecognized_pc = 0;
1676 /* Search the prologue looking for instructions that set up the
1677 frame pointer, adjust the stack pointer, and save registers.
1679 Be careful, however, and if it doesn't look like a prologue,
1680 don't try to scan it. If, for instance, a frameless function
1681 begins with stmfd sp!, then we will tell ourselves there is
1682 a frame, which will confuse stack traceback, as well as "finish"
1683 and other operations that rely on a knowledge of the stack
1686 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1687 regs[regno] = pv_register (regno, 0);
1688 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1689 back_to = make_cleanup_free_pv_area (stack);
1691 for (current_pc = prologue_start;
1692 current_pc < prologue_end;
1696 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1698 if (insn == 0xe1a0c00d) /* mov ip, sp */
1700 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1703 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1704 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1706 unsigned imm = insn & 0xff; /* immediate value */
1707 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1708 int rd = bits (insn, 12, 15);
1709 imm = (imm >> rot) | (imm << (32 - rot));
1710 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1713 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1714 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1716 unsigned imm = insn & 0xff; /* immediate value */
1717 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1718 int rd = bits (insn, 12, 15);
1719 imm = (imm >> rot) | (imm << (32 - rot));
1720 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1723 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1726 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1728 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1729 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1730 regs[bits (insn, 12, 15)]);
1733 else if ((insn & 0xffff0000) == 0xe92d0000)
1734 /* stmfd sp!, {..., fp, ip, lr, pc}
1736 stmfd sp!, {a1, a2, a3, a4} */
1738 int mask = insn & 0xffff;
1740 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1743 /* Calculate offsets of saved registers. */
1744 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1745 if (mask & (1 << regno))
1748 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1749 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1752 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1753 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1754 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1756 /* No need to add this to saved_regs -- it's just an arg reg. */
1759 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1760 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1761 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1763 /* No need to add this to saved_regs -- it's just an arg reg. */
1766 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1768 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1770 /* No need to add this to saved_regs -- it's just arg regs. */
1773 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1775 unsigned imm = insn & 0xff; /* immediate value */
1776 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1777 imm = (imm >> rot) | (imm << (32 - rot));
1778 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1780 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1782 unsigned imm = insn & 0xff; /* immediate value */
1783 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1784 imm = (imm >> rot) | (imm << (32 - rot));
1785 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1787 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1789 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1791 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1794 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1795 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1796 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1798 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1800 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1802 int n_saved_fp_regs;
1803 unsigned int fp_start_reg, fp_bound_reg;
1805 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1808 if ((insn & 0x800) == 0x800) /* N0 is set */
1810 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1811 n_saved_fp_regs = 3;
1813 n_saved_fp_regs = 1;
1817 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1818 n_saved_fp_regs = 2;
1820 n_saved_fp_regs = 4;
1823 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1824 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1825 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1827 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1828 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1829 regs[fp_start_reg++]);
1832 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1834 /* Allow some special function calls when skipping the
1835 prologue; GCC generates these before storing arguments to
1837 CORE_ADDR dest = BranchDest (current_pc, insn);
1839 if (skip_prologue_function (gdbarch, dest, 0))
1844 else if ((insn & 0xf0000000) != 0xe0000000)
1845 break; /* Condition not true, exit early. */
1846 else if (arm_instruction_changes_pc (insn))
1847 /* Don't scan past anything that might change control flow. */
1849 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1850 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1851 /* Ignore block loads from the stack, potentially copying
1852 parameters from memory. */
1854 else if ((insn & 0xfc500000) == 0xe4100000
1855 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1856 /* Similarly ignore single loads from the stack. */
1858 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1859 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1860 register instead of the stack. */
1864 /* The optimizer might shove anything into the prologue,
1865 so we just skip what we don't recognize. */
1866 unrecognized_pc = current_pc;
1871 if (unrecognized_pc == 0)
1872 unrecognized_pc = current_pc;
1874 /* The frame size is just the distance from the frame register
1875 to the original stack pointer. */
1876 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1878 /* Frame pointer is fp. */
1879 framereg = ARM_FP_REGNUM;
1880 framesize = -regs[ARM_FP_REGNUM].k;
1884 /* Try the stack pointer... this is a bit desperate. */
1885 framereg = ARM_SP_REGNUM;
1886 framesize = -regs[ARM_SP_REGNUM].k;
1891 cache->framereg = framereg;
1892 cache->framesize = framesize;
1894 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1895 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1896 cache->saved_regs[regno].addr = offset;
1900 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1901 paddress (gdbarch, unrecognized_pc));
1903 do_cleanups (back_to);
1904 return unrecognized_pc;
1908 arm_scan_prologue (struct frame_info *this_frame,
1909 struct arm_prologue_cache *cache)
1911 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1912 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1914 CORE_ADDR prologue_start, prologue_end, current_pc;
1915 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1916 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1917 pv_t regs[ARM_FPS_REGNUM];
1918 struct pv_area *stack;
1919 struct cleanup *back_to;
1922 /* Assume there is no frame until proven otherwise. */
1923 cache->framereg = ARM_SP_REGNUM;
1924 cache->framesize = 0;
1926 /* Check for Thumb prologue. */
1927 if (arm_frame_is_thumb (this_frame))
1929 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1933 /* Find the function prologue. If we can't find the function in
1934 the symbol table, peek in the stack frame to find the PC. */
1935 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1938 /* One way to find the end of the prologue (which works well
1939 for unoptimized code) is to do the following:
1941 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1944 prologue_end = prev_pc;
1945 else if (sal.end < prologue_end)
1946 prologue_end = sal.end;
1948 This mechanism is very accurate so long as the optimizer
1949 doesn't move any instructions from the function body into the
1950 prologue. If this happens, sal.end will be the last
1951 instruction in the first hunk of prologue code just before
1952 the first instruction that the scheduler has moved from
1953 the body to the prologue.
1955 In order to make sure that we scan all of the prologue
1956 instructions, we use a slightly less accurate mechanism which
1957 may scan more than necessary. To help compensate for this
1958 lack of accuracy, the prologue scanning loop below contains
1959 several clauses which'll cause the loop to terminate early if
1960 an implausible prologue instruction is encountered.
1966 is a suitable endpoint since it accounts for the largest
1967 possible prologue plus up to five instructions inserted by
1970 if (prologue_end > prologue_start + 64)
1972 prologue_end = prologue_start + 64; /* See above. */
1977 /* We have no symbol information. Our only option is to assume this
1978 function has a standard stack frame and the normal frame register.
1979 Then, we can find the value of our frame pointer on entrance to
1980 the callee (or at the present moment if this is the innermost frame).
1981 The value stored there should be the address of the stmfd + 8. */
1982 CORE_ADDR frame_loc;
1983 LONGEST return_value;
1985 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1986 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1990 prologue_start = gdbarch_addr_bits_remove
1991 (gdbarch, return_value) - 8;
1992 prologue_end = prologue_start + 64; /* See above. */
1996 if (prev_pc < prologue_end)
1997 prologue_end = prev_pc;
1999 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2002 static struct arm_prologue_cache *
2003 arm_make_prologue_cache (struct frame_info *this_frame)
2006 struct arm_prologue_cache *cache;
2007 CORE_ADDR unwound_fp;
2009 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2010 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2012 arm_scan_prologue (this_frame, cache);
2014 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2015 if (unwound_fp == 0)
2018 cache->prev_sp = unwound_fp + cache->framesize;
2020 /* Calculate actual addresses of saved registers using offsets
2021 determined by arm_scan_prologue. */
2022 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2023 if (trad_frame_addr_p (cache->saved_regs, reg))
2024 cache->saved_regs[reg].addr += cache->prev_sp;
2029 /* Our frame ID for a normal frame is the current function's starting PC
2030 and the caller's SP when we were called. */
2033 arm_prologue_this_id (struct frame_info *this_frame,
2035 struct frame_id *this_id)
2037 struct arm_prologue_cache *cache;
2041 if (*this_cache == NULL)
2042 *this_cache = arm_make_prologue_cache (this_frame);
2043 cache = *this_cache;
2045 /* This is meant to halt the backtrace at "_start". */
2046 pc = get_frame_pc (this_frame);
2047 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2050 /* If we've hit a wall, stop. */
2051 if (cache->prev_sp == 0)
2054 /* Use function start address as part of the frame ID. If we cannot
2055 identify the start address (due to missing symbol information),
2056 fall back to just using the current PC. */
2057 func = get_frame_func (this_frame);
2061 id = frame_id_build (cache->prev_sp, func);
2065 static struct value *
2066 arm_prologue_prev_register (struct frame_info *this_frame,
2070 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2071 struct arm_prologue_cache *cache;
2073 if (*this_cache == NULL)
2074 *this_cache = arm_make_prologue_cache (this_frame);
2075 cache = *this_cache;
2077 /* If we are asked to unwind the PC, then we need to return the LR
2078 instead. The prologue may save PC, but it will point into this
2079 frame's prologue, not the next frame's resume location. Also
2080 strip the saved T bit. A valid LR may have the low bit set, but
2081 a valid PC never does. */
2082 if (prev_regnum == ARM_PC_REGNUM)
2086 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2087 return frame_unwind_got_constant (this_frame, prev_regnum,
2088 arm_addr_bits_remove (gdbarch, lr));
2091 /* SP is generally not saved to the stack, but this frame is
2092 identified by the next frame's stack pointer at the time of the call.
2093 The value was already reconstructed into PREV_SP. */
2094 if (prev_regnum == ARM_SP_REGNUM)
2095 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2097 /* The CPSR may have been changed by the call instruction and by the
2098 called function. The only bit we can reconstruct is the T bit,
2099 by checking the low bit of LR as of the call. This is a reliable
2100 indicator of Thumb-ness except for some ARM v4T pre-interworking
2101 Thumb code, which could get away with a clear low bit as long as
2102 the called function did not use bx. Guess that all other
2103 bits are unchanged; the condition flags are presumably lost,
2104 but the processor status is likely valid. */
2105 if (prev_regnum == ARM_PS_REGNUM)
2108 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2110 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2111 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2112 if (IS_THUMB_ADDR (lr))
2116 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2119 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2123 struct frame_unwind arm_prologue_unwind = {
2125 default_frame_unwind_stop_reason,
2126 arm_prologue_this_id,
2127 arm_prologue_prev_register,
2129 default_frame_sniffer
2132 /* Maintain a list of ARM exception table entries per objfile, similar to the
2133 list of mapping symbols. We only cache entries for standard ARM-defined
2134 personality routines; the cache will contain only the frame unwinding
2135 instructions associated with the entry (not the descriptors). */
2137 static const struct objfile_data *arm_exidx_data_key;
2139 struct arm_exidx_entry
2144 typedef struct arm_exidx_entry arm_exidx_entry_s;
2145 DEF_VEC_O(arm_exidx_entry_s);
2147 struct arm_exidx_data
2149 VEC(arm_exidx_entry_s) **section_maps;
2153 arm_exidx_data_free (struct objfile *objfile, void *arg)
2155 struct arm_exidx_data *data = arg;
2158 for (i = 0; i < objfile->obfd->section_count; i++)
2159 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2163 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2164 const struct arm_exidx_entry *rhs)
2166 return lhs->addr < rhs->addr;
2169 static struct obj_section *
2170 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2172 struct obj_section *osect;
2174 ALL_OBJFILE_OSECTIONS (objfile, osect)
2175 if (bfd_get_section_flags (objfile->obfd,
2176 osect->the_bfd_section) & SEC_ALLOC)
2178 bfd_vma start, size;
2179 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2180 size = bfd_get_section_size (osect->the_bfd_section);
2182 if (start <= vma && vma < start + size)
2189 /* Parse contents of exception table and exception index sections
2190 of OBJFILE, and fill in the exception table entry cache.
2192 For each entry that refers to a standard ARM-defined personality
2193 routine, extract the frame unwinding instructions (from either
2194 the index or the table section). The unwinding instructions
2196 - extracting them from the rest of the table data
2197 - converting to host endianness
2198 - appending the implicit 0xb0 ("Finish") code
2200 The extracted and normalized instructions are stored for later
2201 retrieval by the arm_find_exidx_entry routine. */
2204 arm_exidx_new_objfile (struct objfile *objfile)
2206 struct cleanup *cleanups;
2207 struct arm_exidx_data *data;
2208 asection *exidx, *extab;
2209 bfd_vma exidx_vma = 0, extab_vma = 0;
2210 bfd_size_type exidx_size = 0, extab_size = 0;
2211 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2214 /* If we've already touched this file, do nothing. */
2215 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2217 cleanups = make_cleanup (null_cleanup, NULL);
2219 /* Read contents of exception table and index. */
2220 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2223 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2224 exidx_size = bfd_get_section_size (exidx);
2225 exidx_data = xmalloc (exidx_size);
2226 make_cleanup (xfree, exidx_data);
2228 if (!bfd_get_section_contents (objfile->obfd, exidx,
2229 exidx_data, 0, exidx_size))
2231 do_cleanups (cleanups);
2236 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2239 extab_vma = bfd_section_vma (objfile->obfd, extab);
2240 extab_size = bfd_get_section_size (extab);
2241 extab_data = xmalloc (extab_size);
2242 make_cleanup (xfree, extab_data);
2244 if (!bfd_get_section_contents (objfile->obfd, extab,
2245 extab_data, 0, extab_size))
2247 do_cleanups (cleanups);
2252 /* Allocate exception table data structure. */
2253 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2254 set_objfile_data (objfile, arm_exidx_data_key, data);
2255 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2256 objfile->obfd->section_count,
2257 VEC(arm_exidx_entry_s) *);
2259 /* Fill in exception table. */
2260 for (i = 0; i < exidx_size / 8; i++)
2262 struct arm_exidx_entry new_exidx_entry;
2263 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2264 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2265 bfd_vma addr = 0, word = 0;
2266 int n_bytes = 0, n_words = 0;
2267 struct obj_section *sec;
2268 gdb_byte *entry = NULL;
2270 /* Extract address of start of function. */
2271 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2272 idx += exidx_vma + i * 8;
2274 /* Find section containing function and compute section offset. */
2275 sec = arm_obj_section_from_vma (objfile, idx);
2278 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2280 /* Determine address of exception table entry. */
2283 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2285 else if ((val & 0xff000000) == 0x80000000)
2287 /* Exception table entry embedded in .ARM.exidx
2288 -- must be short form. */
2292 else if (!(val & 0x80000000))
2294 /* Exception table entry in .ARM.extab. */
2295 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2296 addr += exidx_vma + i * 8 + 4;
2298 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2300 word = bfd_h_get_32 (objfile->obfd,
2301 extab_data + addr - extab_vma);
2304 if ((word & 0xff000000) == 0x80000000)
2309 else if ((word & 0xff000000) == 0x81000000
2310 || (word & 0xff000000) == 0x82000000)
2314 n_words = ((word >> 16) & 0xff);
2316 else if (!(word & 0x80000000))
2319 struct obj_section *pers_sec;
2320 int gnu_personality = 0;
2322 /* Custom personality routine. */
2323 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2324 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2326 /* Check whether we've got one of the variants of the
2327 GNU personality routines. */
2328 pers_sec = arm_obj_section_from_vma (objfile, pers);
2331 static const char *personality[] =
2333 "__gcc_personality_v0",
2334 "__gxx_personality_v0",
2335 "__gcj_personality_v0",
2336 "__gnu_objc_personality_v0",
2340 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2343 for (k = 0; personality[k]; k++)
2344 if (lookup_minimal_symbol_by_pc_name
2345 (pc, personality[k], objfile))
2347 gnu_personality = 1;
2352 /* If so, the next word contains a word count in the high
2353 byte, followed by the same unwind instructions as the
2354 pre-defined forms. */
2356 && addr + 4 <= extab_vma + extab_size)
2358 word = bfd_h_get_32 (objfile->obfd,
2359 extab_data + addr - extab_vma);
2362 n_words = ((word >> 24) & 0xff);
2368 /* Sanity check address. */
2370 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2371 n_words = n_bytes = 0;
2373 /* The unwind instructions reside in WORD (only the N_BYTES least
2374 significant bytes are valid), followed by N_WORDS words in the
2375 extab section starting at ADDR. */
2376 if (n_bytes || n_words)
2378 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2379 n_bytes + n_words * 4 + 1);
2382 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2386 word = bfd_h_get_32 (objfile->obfd,
2387 extab_data + addr - extab_vma);
2390 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2391 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2392 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2393 *p++ = (gdb_byte) (word & 0xff);
2396 /* Implied "Finish" to terminate the list. */
2400 /* Push entry onto vector. They are guaranteed to always
2401 appear in order of increasing addresses. */
2402 new_exidx_entry.addr = idx;
2403 new_exidx_entry.entry = entry;
2404 VEC_safe_push (arm_exidx_entry_s,
2405 data->section_maps[sec->the_bfd_section->index],
2409 do_cleanups (cleanups);
2412 /* Search for the exception table entry covering MEMADDR. If one is found,
2413 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2414 set *START to the start of the region covered by this entry. */
2417 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2419 struct obj_section *sec;
2421 sec = find_pc_section (memaddr);
2424 struct arm_exidx_data *data;
2425 VEC(arm_exidx_entry_s) *map;
2426 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2429 data = objfile_data (sec->objfile, arm_exidx_data_key);
2432 map = data->section_maps[sec->the_bfd_section->index];
2433 if (!VEC_empty (arm_exidx_entry_s, map))
2435 struct arm_exidx_entry *map_sym;
2437 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2438 arm_compare_exidx_entries);
2440 /* VEC_lower_bound finds the earliest ordered insertion
2441 point. If the following symbol starts at this exact
2442 address, we use that; otherwise, the preceding
2443 exception table entry covers this address. */
2444 if (idx < VEC_length (arm_exidx_entry_s, map))
2446 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2447 if (map_sym->addr == map_key.addr)
2450 *start = map_sym->addr + obj_section_addr (sec);
2451 return map_sym->entry;
2457 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2459 *start = map_sym->addr + obj_section_addr (sec);
2460 return map_sym->entry;
2469 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2470 instruction list from the ARM exception table entry ENTRY, allocate and
2471 return a prologue cache structure describing how to unwind this frame.
2473 Return NULL if the unwinding instruction list contains a "spare",
2474 "reserved" or "refuse to unwind" instruction as defined in section
2475 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2476 for the ARM Architecture" document. */
2478 static struct arm_prologue_cache *
2479 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2484 struct arm_prologue_cache *cache;
2485 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2486 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2492 /* Whenever we reload SP, we actually have to retrieve its
2493 actual value in the current frame. */
2496 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2498 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2499 vsp = get_frame_register_unsigned (this_frame, reg);
2503 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2504 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2510 /* Decode next unwind instruction. */
2513 if ((insn & 0xc0) == 0)
2515 int offset = insn & 0x3f;
2516 vsp += (offset << 2) + 4;
2518 else if ((insn & 0xc0) == 0x40)
2520 int offset = insn & 0x3f;
2521 vsp -= (offset << 2) + 4;
2523 else if ((insn & 0xf0) == 0x80)
2525 int mask = ((insn & 0xf) << 8) | *entry++;
2528 /* The special case of an all-zero mask identifies
2529 "Refuse to unwind". We return NULL to fall back
2530 to the prologue analyzer. */
2534 /* Pop registers r4..r15 under mask. */
2535 for (i = 0; i < 12; i++)
2536 if (mask & (1 << i))
2538 cache->saved_regs[4 + i].addr = vsp;
2542 /* Special-case popping SP -- we need to reload vsp. */
2543 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2546 else if ((insn & 0xf0) == 0x90)
2548 int reg = insn & 0xf;
2550 /* Reserved cases. */
2551 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2554 /* Set SP from another register and mark VSP for reload. */
2555 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2558 else if ((insn & 0xf0) == 0xa0)
2560 int count = insn & 0x7;
2561 int pop_lr = (insn & 0x8) != 0;
2564 /* Pop r4..r[4+count]. */
2565 for (i = 0; i <= count; i++)
2567 cache->saved_regs[4 + i].addr = vsp;
2571 /* If indicated by flag, pop LR as well. */
2574 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2578 else if (insn == 0xb0)
2580 /* We could only have updated PC by popping into it; if so, it
2581 will show up as address. Otherwise, copy LR into PC. */
2582 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2583 cache->saved_regs[ARM_PC_REGNUM]
2584 = cache->saved_regs[ARM_LR_REGNUM];
2589 else if (insn == 0xb1)
2591 int mask = *entry++;
2594 /* All-zero mask and mask >= 16 is "spare". */
2595 if (mask == 0 || mask >= 16)
2598 /* Pop r0..r3 under mask. */
2599 for (i = 0; i < 4; i++)
2600 if (mask & (1 << i))
2602 cache->saved_regs[i].addr = vsp;
2606 else if (insn == 0xb2)
2608 ULONGEST offset = 0;
2613 offset |= (*entry & 0x7f) << shift;
2616 while (*entry++ & 0x80);
2618 vsp += 0x204 + (offset << 2);
2620 else if (insn == 0xb3)
2622 int start = *entry >> 4;
2623 int count = (*entry++) & 0xf;
2626 /* Only registers D0..D15 are valid here. */
2627 if (start + count >= 16)
2630 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2631 for (i = 0; i <= count; i++)
2633 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2637 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2640 else if ((insn & 0xf8) == 0xb8)
2642 int count = insn & 0x7;
2645 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2646 for (i = 0; i <= count; i++)
2648 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2652 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2655 else if (insn == 0xc6)
2657 int start = *entry >> 4;
2658 int count = (*entry++) & 0xf;
2661 /* Only registers WR0..WR15 are valid. */
2662 if (start + count >= 16)
2665 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2666 for (i = 0; i <= count; i++)
2668 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2672 else if (insn == 0xc7)
2674 int mask = *entry++;
2677 /* All-zero mask and mask >= 16 is "spare". */
2678 if (mask == 0 || mask >= 16)
2681 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2682 for (i = 0; i < 4; i++)
2683 if (mask & (1 << i))
2685 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2689 else if ((insn & 0xf8) == 0xc0)
2691 int count = insn & 0x7;
2694 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2695 for (i = 0; i <= count; i++)
2697 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2701 else if (insn == 0xc8)
2703 int start = *entry >> 4;
2704 int count = (*entry++) & 0xf;
2707 /* Only registers D0..D31 are valid. */
2708 if (start + count >= 16)
2711 /* Pop VFP double-precision registers
2712 D[16+start]..D[16+start+count]. */
2713 for (i = 0; i <= count; i++)
2715 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2719 else if (insn == 0xc9)
2721 int start = *entry >> 4;
2722 int count = (*entry++) & 0xf;
2725 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2726 for (i = 0; i <= count; i++)
2728 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2732 else if ((insn & 0xf8) == 0xd0)
2734 int count = insn & 0x7;
2737 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2738 for (i = 0; i <= count; i++)
2740 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2746 /* Everything else is "spare". */
2751 /* If we restore SP from a register, assume this was the frame register.
2752 Otherwise just fall back to SP as frame register. */
2753 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2754 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2756 cache->framereg = ARM_SP_REGNUM;
2758 /* Determine offset to previous frame. */
2760 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2762 /* We already got the previous SP. */
2763 cache->prev_sp = vsp;
2768 /* Unwinding via ARM exception table entries. Note that the sniffer
2769 already computes a filled-in prologue cache, which is then used
2770 with the same arm_prologue_this_id and arm_prologue_prev_register
2771 routines also used for prologue-parsing based unwinding. */
2774 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2775 struct frame_info *this_frame,
2776 void **this_prologue_cache)
2778 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2779 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2780 CORE_ADDR addr_in_block, exidx_region, func_start;
2781 struct arm_prologue_cache *cache;
2784 /* See if we have an ARM exception table entry covering this address. */
2785 addr_in_block = get_frame_address_in_block (this_frame);
2786 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2790 /* The ARM exception table does not describe unwind information
2791 for arbitrary PC values, but is guaranteed to be correct only
2792 at call sites. We have to decide here whether we want to use
2793 ARM exception table information for this frame, or fall back
2794 to using prologue parsing. (Note that if we have DWARF CFI,
2795 this sniffer isn't even called -- CFI is always preferred.)
2797 Before we make this decision, however, we check whether we
2798 actually have *symbol* information for the current frame.
2799 If not, prologue parsing would not work anyway, so we might
2800 as well use the exception table and hope for the best. */
2801 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2805 /* If the next frame is "normal", we are at a call site in this
2806 frame, so exception information is guaranteed to be valid. */
2807 if (get_next_frame (this_frame)
2808 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2811 /* We also assume exception information is valid if we're currently
2812 blocked in a system call. The system library is supposed to
2813 ensure this, so that e.g. pthread cancellation works. */
2814 if (arm_frame_is_thumb (this_frame))
2818 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2819 byte_order_for_code, &insn)
2820 && (insn & 0xff00) == 0xdf00 /* svc */)
2827 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2828 byte_order_for_code, &insn)
2829 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2833 /* Bail out if we don't know that exception information is valid. */
2837 /* The ARM exception index does not mark the *end* of the region
2838 covered by the entry, and some functions will not have any entry.
2839 To correctly recognize the end of the covered region, the linker
2840 should have inserted dummy records with a CANTUNWIND marker.
2842 Unfortunately, current versions of GNU ld do not reliably do
2843 this, and thus we may have found an incorrect entry above.
2844 As a (temporary) sanity check, we only use the entry if it
2845 lies *within* the bounds of the function. Note that this check
2846 might reject perfectly valid entries that just happen to cover
2847 multiple functions; therefore this check ought to be removed
2848 once the linker is fixed. */
2849 if (func_start > exidx_region)
2853 /* Decode the list of unwinding instructions into a prologue cache.
2854 Note that this may fail due to e.g. a "refuse to unwind" code. */
2855 cache = arm_exidx_fill_cache (this_frame, entry);
2859 *this_prologue_cache = cache;
2863 struct frame_unwind arm_exidx_unwind = {
2865 default_frame_unwind_stop_reason,
2866 arm_prologue_this_id,
2867 arm_prologue_prev_register,
2869 arm_exidx_unwind_sniffer
2872 static struct arm_prologue_cache *
2873 arm_make_stub_cache (struct frame_info *this_frame)
2875 struct arm_prologue_cache *cache;
2877 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2878 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2880 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2885 /* Our frame ID for a stub frame is the current SP and LR. */
2888 arm_stub_this_id (struct frame_info *this_frame,
2890 struct frame_id *this_id)
2892 struct arm_prologue_cache *cache;
2894 if (*this_cache == NULL)
2895 *this_cache = arm_make_stub_cache (this_frame);
2896 cache = *this_cache;
2898 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2902 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2903 struct frame_info *this_frame,
2904 void **this_prologue_cache)
2906 CORE_ADDR addr_in_block;
2909 addr_in_block = get_frame_address_in_block (this_frame);
2910 if (in_plt_section (addr_in_block)
2911 /* We also use the stub winder if the target memory is unreadable
2912 to avoid having the prologue unwinder trying to read it. */
2913 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2919 struct frame_unwind arm_stub_unwind = {
2921 default_frame_unwind_stop_reason,
2923 arm_prologue_prev_register,
2925 arm_stub_unwind_sniffer
2928 /* Put here the code to store, into CACHE->saved_regs, the addresses
2929 of the saved registers of frame described by THIS_FRAME. CACHE is
2932 static struct arm_prologue_cache *
2933 arm_m_exception_cache (struct frame_info *this_frame)
2935 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2936 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2937 struct arm_prologue_cache *cache;
2938 CORE_ADDR unwound_sp;
2941 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2942 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2944 unwound_sp = get_frame_register_unsigned (this_frame,
2947 /* The hardware saves eight 32-bit words, comprising xPSR,
2948 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2949 "B1.5.6 Exception entry behavior" in
2950 "ARMv7-M Architecture Reference Manual". */
2951 cache->saved_regs[0].addr = unwound_sp;
2952 cache->saved_regs[1].addr = unwound_sp + 4;
2953 cache->saved_regs[2].addr = unwound_sp + 8;
2954 cache->saved_regs[3].addr = unwound_sp + 12;
2955 cache->saved_regs[12].addr = unwound_sp + 16;
2956 cache->saved_regs[14].addr = unwound_sp + 20;
2957 cache->saved_regs[15].addr = unwound_sp + 24;
2958 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2960 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2961 aligner between the top of the 32-byte stack frame and the
2962 previous context's stack pointer. */
2963 cache->prev_sp = unwound_sp + 32;
2964 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2965 && (xpsr & (1 << 9)) != 0)
2966 cache->prev_sp += 4;
2971 /* Implementation of function hook 'this_id' in
2972 'struct frame_uwnind'. */
2975 arm_m_exception_this_id (struct frame_info *this_frame,
2977 struct frame_id *this_id)
2979 struct arm_prologue_cache *cache;
2981 if (*this_cache == NULL)
2982 *this_cache = arm_m_exception_cache (this_frame);
2983 cache = *this_cache;
2985 /* Our frame ID for a stub frame is the current SP and LR. */
2986 *this_id = frame_id_build (cache->prev_sp,
2987 get_frame_pc (this_frame));
2990 /* Implementation of function hook 'prev_register' in
2991 'struct frame_uwnind'. */
2993 static struct value *
2994 arm_m_exception_prev_register (struct frame_info *this_frame,
2998 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2999 struct arm_prologue_cache *cache;
3001 if (*this_cache == NULL)
3002 *this_cache = arm_m_exception_cache (this_frame);
3003 cache = *this_cache;
3005 /* The value was already reconstructed into PREV_SP. */
3006 if (prev_regnum == ARM_SP_REGNUM)
3007 return frame_unwind_got_constant (this_frame, prev_regnum,
3010 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3014 /* Implementation of function hook 'sniffer' in
3015 'struct frame_uwnind'. */
3018 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3019 struct frame_info *this_frame,
3020 void **this_prologue_cache)
3022 CORE_ADDR this_pc = get_frame_pc (this_frame);
3024 /* No need to check is_m; this sniffer is only registered for
3025 M-profile architectures. */
3027 /* Exception frames return to one of these magic PCs. Other values
3028 are not defined as of v7-M. See details in "B1.5.8 Exception
3029 return behavior" in "ARMv7-M Architecture Reference Manual". */
3030 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3031 || this_pc == 0xfffffffd)
3037 /* Frame unwinder for M-profile exceptions. */
3039 struct frame_unwind arm_m_exception_unwind =
3042 default_frame_unwind_stop_reason,
3043 arm_m_exception_this_id,
3044 arm_m_exception_prev_register,
3046 arm_m_exception_unwind_sniffer
3050 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3052 struct arm_prologue_cache *cache;
3054 if (*this_cache == NULL)
3055 *this_cache = arm_make_prologue_cache (this_frame);
3056 cache = *this_cache;
3058 return cache->prev_sp - cache->framesize;
3061 struct frame_base arm_normal_base = {
3062 &arm_prologue_unwind,
3063 arm_normal_frame_base,
3064 arm_normal_frame_base,
3065 arm_normal_frame_base
3068 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3069 dummy frame. The frame ID's base needs to match the TOS value
3070 saved by save_dummy_frame_tos() and returned from
3071 arm_push_dummy_call, and the PC needs to match the dummy frame's
3074 static struct frame_id
3075 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3077 return frame_id_build (get_frame_register_unsigned (this_frame,
3079 get_frame_pc (this_frame));
3082 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3083 be used to construct the previous frame's ID, after looking up the
3084 containing function). */
3087 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3090 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3091 return arm_addr_bits_remove (gdbarch, pc);
3095 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3097 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3100 static struct value *
3101 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3104 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3106 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3111 /* The PC is normally copied from the return column, which
3112 describes saves of LR. However, that version may have an
3113 extra bit set to indicate Thumb state. The bit is not
3115 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3116 return frame_unwind_got_constant (this_frame, regnum,
3117 arm_addr_bits_remove (gdbarch, lr));
3120 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3121 cpsr = get_frame_register_unsigned (this_frame, regnum);
3122 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3123 if (IS_THUMB_ADDR (lr))
3127 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3130 internal_error (__FILE__, __LINE__,
3131 _("Unexpected register %d"), regnum);
3136 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3137 struct dwarf2_frame_state_reg *reg,
3138 struct frame_info *this_frame)
3144 reg->how = DWARF2_FRAME_REG_FN;
3145 reg->loc.fn = arm_dwarf2_prev_register;
3148 reg->how = DWARF2_FRAME_REG_CFA;
3153 /* Return true if we are in the function's epilogue, i.e. after the
3154 instruction that destroyed the function's stack frame. */
3157 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3159 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3160 unsigned int insn, insn2;
3161 int found_return = 0, found_stack_adjust = 0;
3162 CORE_ADDR func_start, func_end;
3166 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3169 /* The epilogue is a sequence of instructions along the following lines:
3171 - add stack frame size to SP or FP
3172 - [if frame pointer used] restore SP from FP
3173 - restore registers from SP [may include PC]
3174 - a return-type instruction [if PC wasn't already restored]
3176 In a first pass, we scan forward from the current PC and verify the
3177 instructions we find as compatible with this sequence, ending in a
3180 However, this is not sufficient to distinguish indirect function calls
3181 within a function from indirect tail calls in the epilogue in some cases.
3182 Therefore, if we didn't already find any SP-changing instruction during
3183 forward scan, we add a backward scanning heuristic to ensure we actually
3184 are in the epilogue. */
3187 while (scan_pc < func_end && !found_return)
3189 if (target_read_memory (scan_pc, buf, 2))
3193 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3195 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3197 else if (insn == 0x46f7) /* mov pc, lr */
3199 else if (insn == 0x46bd) /* mov sp, r7 */
3200 found_stack_adjust = 1;
3201 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3202 found_stack_adjust = 1;
3203 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3205 found_stack_adjust = 1;
3206 if (insn & 0x0100) /* <registers> include PC. */
3209 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3211 if (target_read_memory (scan_pc, buf, 2))
3215 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3217 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3219 found_stack_adjust = 1;
3220 if (insn2 & 0x8000) /* <registers> include PC. */
3223 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3224 && (insn2 & 0x0fff) == 0x0b04)
3226 found_stack_adjust = 1;
3227 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3230 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3231 && (insn2 & 0x0e00) == 0x0a00)
3232 found_stack_adjust = 1;
3243 /* Since any instruction in the epilogue sequence, with the possible
3244 exception of return itself, updates the stack pointer, we need to
3245 scan backwards for at most one instruction. Try either a 16-bit or
3246 a 32-bit instruction. This is just a heuristic, so we do not worry
3247 too much about false positives. */
3249 if (!found_stack_adjust)
3251 if (pc - 4 < func_start)
3253 if (target_read_memory (pc - 4, buf, 4))
3256 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3257 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3259 if (insn2 == 0x46bd) /* mov sp, r7 */
3260 found_stack_adjust = 1;
3261 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3262 found_stack_adjust = 1;
3263 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3264 found_stack_adjust = 1;
3265 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3266 found_stack_adjust = 1;
3267 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3268 && (insn2 & 0x0fff) == 0x0b04)
3269 found_stack_adjust = 1;
3270 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3271 && (insn2 & 0x0e00) == 0x0a00)
3272 found_stack_adjust = 1;
3275 return found_stack_adjust;
3278 /* Return true if we are in the function's epilogue, i.e. after the
3279 instruction that destroyed the function's stack frame. */
3282 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3284 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3286 int found_return, found_stack_adjust;
3287 CORE_ADDR func_start, func_end;
3289 if (arm_pc_is_thumb (gdbarch, pc))
3290 return thumb_in_function_epilogue_p (gdbarch, pc);
3292 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3295 /* We are in the epilogue if the previous instruction was a stack
3296 adjustment and the next instruction is a possible return (bx, mov
3297 pc, or pop). We could have to scan backwards to find the stack
3298 adjustment, or forwards to find the return, but this is a decent
3299 approximation. First scan forwards. */
3302 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3303 if (bits (insn, 28, 31) != INST_NV)
3305 if ((insn & 0x0ffffff0) == 0x012fff10)
3308 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3311 else if ((insn & 0x0fff0000) == 0x08bd0000
3312 && (insn & 0x0000c000) != 0)
3313 /* POP (LDMIA), including PC or LR. */
3320 /* Scan backwards. This is just a heuristic, so do not worry about
3321 false positives from mode changes. */
3323 if (pc < func_start + 4)
3326 found_stack_adjust = 0;
3327 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3328 if (bits (insn, 28, 31) != INST_NV)
3330 if ((insn & 0x0df0f000) == 0x0080d000)
3331 /* ADD SP (register or immediate). */
3332 found_stack_adjust = 1;
3333 else if ((insn & 0x0df0f000) == 0x0040d000)
3334 /* SUB SP (register or immediate). */
3335 found_stack_adjust = 1;
3336 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3338 found_stack_adjust = 1;
3339 else if ((insn & 0x0fff0000) == 0x08bd0000)
3341 found_stack_adjust = 1;
3342 else if ((insn & 0x0fff0000) == 0x049d0000)
3343 /* POP of a single register. */
3344 found_stack_adjust = 1;
3347 if (found_stack_adjust)
3354 /* When arguments must be pushed onto the stack, they go on in reverse
3355 order. The code below implements a FILO (stack) to do this. */
3360 struct stack_item *prev;
3364 static struct stack_item *
3365 push_stack_item (struct stack_item *prev, const void *contents, int len)
3367 struct stack_item *si;
3368 si = xmalloc (sizeof (struct stack_item));
3369 si->data = xmalloc (len);
3372 memcpy (si->data, contents, len);
3376 static struct stack_item *
3377 pop_stack_item (struct stack_item *si)
3379 struct stack_item *dead = si;
3387 /* Return the alignment (in bytes) of the given type. */
3390 arm_type_align (struct type *t)
3396 t = check_typedef (t);
3397 switch (TYPE_CODE (t))
3400 /* Should never happen. */
3401 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3405 case TYPE_CODE_ENUM:
3409 case TYPE_CODE_RANGE:
3411 case TYPE_CODE_CHAR:
3412 case TYPE_CODE_BOOL:
3413 return TYPE_LENGTH (t);
3415 case TYPE_CODE_ARRAY:
3416 case TYPE_CODE_COMPLEX:
3417 /* TODO: What about vector types? */
3418 return arm_type_align (TYPE_TARGET_TYPE (t));
3420 case TYPE_CODE_STRUCT:
3421 case TYPE_CODE_UNION:
3423 for (n = 0; n < TYPE_NFIELDS (t); n++)
3425 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3433 /* Possible base types for a candidate for passing and returning in
3436 enum arm_vfp_cprc_base_type
3445 /* The length of one element of base type B. */
3448 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3452 case VFP_CPRC_SINGLE:
3454 case VFP_CPRC_DOUBLE:
3456 case VFP_CPRC_VEC64:
3458 case VFP_CPRC_VEC128:
3461 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3466 /* The character ('s', 'd' or 'q') for the type of VFP register used
3467 for passing base type B. */
3470 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3474 case VFP_CPRC_SINGLE:
3476 case VFP_CPRC_DOUBLE:
3478 case VFP_CPRC_VEC64:
3480 case VFP_CPRC_VEC128:
3483 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3488 /* Determine whether T may be part of a candidate for passing and
3489 returning in VFP registers, ignoring the limit on the total number
3490 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3491 classification of the first valid component found; if it is not
3492 VFP_CPRC_UNKNOWN, all components must have the same classification
3493 as *BASE_TYPE. If it is found that T contains a type not permitted
3494 for passing and returning in VFP registers, a type differently
3495 classified from *BASE_TYPE, or two types differently classified
3496 from each other, return -1, otherwise return the total number of
3497 base-type elements found (possibly 0 in an empty structure or
3498 array). Vectors and complex types are not currently supported,
3499 matching the generic AAPCS support. */
3502 arm_vfp_cprc_sub_candidate (struct type *t,
3503 enum arm_vfp_cprc_base_type *base_type)
3505 t = check_typedef (t);
3506 switch (TYPE_CODE (t))
3509 switch (TYPE_LENGTH (t))
3512 if (*base_type == VFP_CPRC_UNKNOWN)
3513 *base_type = VFP_CPRC_SINGLE;
3514 else if (*base_type != VFP_CPRC_SINGLE)
3519 if (*base_type == VFP_CPRC_UNKNOWN)
3520 *base_type = VFP_CPRC_DOUBLE;
3521 else if (*base_type != VFP_CPRC_DOUBLE)
3530 case TYPE_CODE_ARRAY:
3534 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3537 if (TYPE_LENGTH (t) == 0)
3539 gdb_assert (count == 0);
3542 else if (count == 0)
3544 unitlen = arm_vfp_cprc_unit_length (*base_type);
3545 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3546 return TYPE_LENGTH (t) / unitlen;
3550 case TYPE_CODE_STRUCT:
3555 for (i = 0; i < TYPE_NFIELDS (t); i++)
3557 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3559 if (sub_count == -1)
3563 if (TYPE_LENGTH (t) == 0)
3565 gdb_assert (count == 0);
3568 else if (count == 0)
3570 unitlen = arm_vfp_cprc_unit_length (*base_type);
3571 if (TYPE_LENGTH (t) != unitlen * count)
3576 case TYPE_CODE_UNION:
3581 for (i = 0; i < TYPE_NFIELDS (t); i++)
3583 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3585 if (sub_count == -1)
3587 count = (count > sub_count ? count : sub_count);
3589 if (TYPE_LENGTH (t) == 0)
3591 gdb_assert (count == 0);
3594 else if (count == 0)
3596 unitlen = arm_vfp_cprc_unit_length (*base_type);
3597 if (TYPE_LENGTH (t) != unitlen * count)
3609 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3610 if passed to or returned from a non-variadic function with the VFP
3611 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3612 *BASE_TYPE to the base type for T and *COUNT to the number of
3613 elements of that base type before returning. */
3616 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3619 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3620 int c = arm_vfp_cprc_sub_candidate (t, &b);
3621 if (c <= 0 || c > 4)
3628 /* Return 1 if the VFP ABI should be used for passing arguments to and
3629 returning values from a function of type FUNC_TYPE, 0
3633 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3635 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3636 /* Variadic functions always use the base ABI. Assume that functions
3637 without debug info are not variadic. */
3638 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3640 /* The VFP ABI is only supported as a variant of AAPCS. */
3641 if (tdep->arm_abi != ARM_ABI_AAPCS)
3643 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3646 /* We currently only support passing parameters in integer registers, which
3647 conforms with GCC's default model, and VFP argument passing following
3648 the VFP variant of AAPCS. Several other variants exist and
3649 we should probably support some of them based on the selected ABI. */
3652 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3653 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3654 struct value **args, CORE_ADDR sp, int struct_return,
3655 CORE_ADDR struct_addr)
3657 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3661 struct stack_item *si = NULL;
3664 unsigned vfp_regs_free = (1 << 16) - 1;
3666 /* Determine the type of this function and whether the VFP ABI
3668 ftype = check_typedef (value_type (function));
3669 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3670 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3671 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3673 /* Set the return address. For the ARM, the return breakpoint is
3674 always at BP_ADDR. */
3675 if (arm_pc_is_thumb (gdbarch, bp_addr))
3677 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3679 /* Walk through the list of args and determine how large a temporary
3680 stack is required. Need to take care here as structs may be
3681 passed on the stack, and we have to push them. */
3684 argreg = ARM_A1_REGNUM;
3687 /* The struct_return pointer occupies the first parameter
3688 passing register. */
3692 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3693 gdbarch_register_name (gdbarch, argreg),
3694 paddress (gdbarch, struct_addr));
3695 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3699 for (argnum = 0; argnum < nargs; argnum++)
3702 struct type *arg_type;
3703 struct type *target_type;
3704 enum type_code typecode;
3705 const bfd_byte *val;
3707 enum arm_vfp_cprc_base_type vfp_base_type;
3709 int may_use_core_reg = 1;
3711 arg_type = check_typedef (value_type (args[argnum]));
3712 len = TYPE_LENGTH (arg_type);
3713 target_type = TYPE_TARGET_TYPE (arg_type);
3714 typecode = TYPE_CODE (arg_type);
3715 val = value_contents (args[argnum]);
3717 align = arm_type_align (arg_type);
3718 /* Round alignment up to a whole number of words. */
3719 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3720 /* Different ABIs have different maximum alignments. */
3721 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3723 /* The APCS ABI only requires word alignment. */
3724 align = INT_REGISTER_SIZE;
3728 /* The AAPCS requires at most doubleword alignment. */
3729 if (align > INT_REGISTER_SIZE * 2)
3730 align = INT_REGISTER_SIZE * 2;
3734 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3742 /* Because this is a CPRC it cannot go in a core register or
3743 cause a core register to be skipped for alignment.
3744 Either it goes in VFP registers and the rest of this loop
3745 iteration is skipped for this argument, or it goes on the
3746 stack (and the stack alignment code is correct for this
3748 may_use_core_reg = 0;
3750 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3751 shift = unit_length / 4;
3752 mask = (1 << (shift * vfp_base_count)) - 1;
3753 for (regno = 0; regno < 16; regno += shift)
3754 if (((vfp_regs_free >> regno) & mask) == mask)
3763 vfp_regs_free &= ~(mask << regno);
3764 reg_scaled = regno / shift;
3765 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3766 for (i = 0; i < vfp_base_count; i++)
3770 if (reg_char == 'q')
3771 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3772 val + i * unit_length);
3775 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3776 reg_char, reg_scaled + i);
3777 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3779 regcache_cooked_write (regcache, regnum,
3780 val + i * unit_length);
3787 /* This CPRC could not go in VFP registers, so all VFP
3788 registers are now marked as used. */
3793 /* Push stack padding for dowubleword alignment. */
3794 if (nstack & (align - 1))
3796 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3797 nstack += INT_REGISTER_SIZE;
3800 /* Doubleword aligned quantities must go in even register pairs. */
3801 if (may_use_core_reg
3802 && argreg <= ARM_LAST_ARG_REGNUM
3803 && align > INT_REGISTER_SIZE
3807 /* If the argument is a pointer to a function, and it is a
3808 Thumb function, create a LOCAL copy of the value and set
3809 the THUMB bit in it. */
3810 if (TYPE_CODE_PTR == typecode
3811 && target_type != NULL
3812 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3814 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3815 if (arm_pc_is_thumb (gdbarch, regval))
3817 bfd_byte *copy = alloca (len);
3818 store_unsigned_integer (copy, len, byte_order,
3819 MAKE_THUMB_ADDR (regval));
3824 /* Copy the argument to general registers or the stack in
3825 register-sized pieces. Large arguments are split between
3826 registers and stack. */
3829 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3831 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3833 /* The argument is being passed in a general purpose
3836 = extract_unsigned_integer (val, partial_len, byte_order);
3837 if (byte_order == BFD_ENDIAN_BIG)
3838 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3840 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3842 gdbarch_register_name
3844 phex (regval, INT_REGISTER_SIZE));
3845 regcache_cooked_write_unsigned (regcache, argreg, regval);
3850 /* Push the arguments onto the stack. */
3852 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3854 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3855 nstack += INT_REGISTER_SIZE;
3862 /* If we have an odd number of words to push, then decrement the stack
3863 by one word now, so first stack argument will be dword aligned. */
3870 write_memory (sp, si->data, si->len);
3871 si = pop_stack_item (si);
3874 /* Finally, update teh SP register. */
3875 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3881 /* Always align the frame to an 8-byte boundary. This is required on
3882 some platforms and harmless on the rest. */
3885 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3887 /* Align the stack to eight bytes. */
3888 return sp & ~ (CORE_ADDR) 7;
3892 print_fpu_flags (struct ui_file *file, int flags)
3894 if (flags & (1 << 0))
3895 fputs_filtered ("IVO ", file);
3896 if (flags & (1 << 1))
3897 fputs_filtered ("DVZ ", file);
3898 if (flags & (1 << 2))
3899 fputs_filtered ("OFL ", file);
3900 if (flags & (1 << 3))
3901 fputs_filtered ("UFL ", file);
3902 if (flags & (1 << 4))
3903 fputs_filtered ("INX ", file);
3904 fputc_filtered ('\n', file);
3907 /* Print interesting information about the floating point processor
3908 (if present) or emulator. */
3910 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3911 struct frame_info *frame, const char *args)
3913 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3916 type = (status >> 24) & 127;
3917 if (status & (1 << 31))
3918 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3920 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3921 /* i18n: [floating point unit] mask */
3922 fputs_filtered (_("mask: "), file);
3923 print_fpu_flags (file, status >> 16);
3924 /* i18n: [floating point unit] flags */
3925 fputs_filtered (_("flags: "), file);
3926 print_fpu_flags (file, status);
3929 /* Construct the ARM extended floating point type. */
3930 static struct type *
3931 arm_ext_type (struct gdbarch *gdbarch)
3933 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3935 if (!tdep->arm_ext_type)
3937 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3938 floatformats_arm_ext);
3940 return tdep->arm_ext_type;
3943 static struct type *
3944 arm_neon_double_type (struct gdbarch *gdbarch)
3946 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3948 if (tdep->neon_double_type == NULL)
3950 struct type *t, *elem;
3952 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3954 elem = builtin_type (gdbarch)->builtin_uint8;
3955 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3956 elem = builtin_type (gdbarch)->builtin_uint16;
3957 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3958 elem = builtin_type (gdbarch)->builtin_uint32;
3959 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3960 elem = builtin_type (gdbarch)->builtin_uint64;
3961 append_composite_type_field (t, "u64", elem);
3962 elem = builtin_type (gdbarch)->builtin_float;
3963 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3964 elem = builtin_type (gdbarch)->builtin_double;
3965 append_composite_type_field (t, "f64", elem);
3967 TYPE_VECTOR (t) = 1;
3968 TYPE_NAME (t) = "neon_d";
3969 tdep->neon_double_type = t;
3972 return tdep->neon_double_type;
3975 /* FIXME: The vector types are not correctly ordered on big-endian
3976 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3977 bits of d0 - regardless of what unit size is being held in d0. So
3978 the offset of the first uint8 in d0 is 7, but the offset of the
3979 first float is 4. This code works as-is for little-endian
3982 static struct type *
3983 arm_neon_quad_type (struct gdbarch *gdbarch)
3985 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3987 if (tdep->neon_quad_type == NULL)
3989 struct type *t, *elem;
3991 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3993 elem = builtin_type (gdbarch)->builtin_uint8;
3994 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3995 elem = builtin_type (gdbarch)->builtin_uint16;
3996 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3997 elem = builtin_type (gdbarch)->builtin_uint32;
3998 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3999 elem = builtin_type (gdbarch)->builtin_uint64;
4000 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4001 elem = builtin_type (gdbarch)->builtin_float;
4002 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4003 elem = builtin_type (gdbarch)->builtin_double;
4004 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4006 TYPE_VECTOR (t) = 1;
4007 TYPE_NAME (t) = "neon_q";
4008 tdep->neon_quad_type = t;
4011 return tdep->neon_quad_type;
4014 /* Return the GDB type object for the "standard" data type of data in
4017 static struct type *
4018 arm_register_type (struct gdbarch *gdbarch, int regnum)
4020 int num_regs = gdbarch_num_regs (gdbarch);
4022 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4023 && regnum >= num_regs && regnum < num_regs + 32)
4024 return builtin_type (gdbarch)->builtin_float;
4026 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4027 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4028 return arm_neon_quad_type (gdbarch);
4030 /* If the target description has register information, we are only
4031 in this function so that we can override the types of
4032 double-precision registers for NEON. */
4033 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4035 struct type *t = tdesc_register_type (gdbarch, regnum);
4037 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4038 && TYPE_CODE (t) == TYPE_CODE_FLT
4039 && gdbarch_tdep (gdbarch)->have_neon)
4040 return arm_neon_double_type (gdbarch);
4045 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4047 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4048 return builtin_type (gdbarch)->builtin_void;
4050 return arm_ext_type (gdbarch);
4052 else if (regnum == ARM_SP_REGNUM)
4053 return builtin_type (gdbarch)->builtin_data_ptr;
4054 else if (regnum == ARM_PC_REGNUM)
4055 return builtin_type (gdbarch)->builtin_func_ptr;
4056 else if (regnum >= ARRAY_SIZE (arm_register_names))
4057 /* These registers are only supported on targets which supply
4058 an XML description. */
4059 return builtin_type (gdbarch)->builtin_int0;
4061 return builtin_type (gdbarch)->builtin_uint32;
4064 /* Map a DWARF register REGNUM onto the appropriate GDB register
4068 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4070 /* Core integer regs. */
4071 if (reg >= 0 && reg <= 15)
4074 /* Legacy FPA encoding. These were once used in a way which
4075 overlapped with VFP register numbering, so their use is
4076 discouraged, but GDB doesn't support the ARM toolchain
4077 which used them for VFP. */
4078 if (reg >= 16 && reg <= 23)
4079 return ARM_F0_REGNUM + reg - 16;
4081 /* New assignments for the FPA registers. */
4082 if (reg >= 96 && reg <= 103)
4083 return ARM_F0_REGNUM + reg - 96;
4085 /* WMMX register assignments. */
4086 if (reg >= 104 && reg <= 111)
4087 return ARM_WCGR0_REGNUM + reg - 104;
4089 if (reg >= 112 && reg <= 127)
4090 return ARM_WR0_REGNUM + reg - 112;
4092 if (reg >= 192 && reg <= 199)
4093 return ARM_WC0_REGNUM + reg - 192;
4095 /* VFP v2 registers. A double precision value is actually
4096 in d1 rather than s2, but the ABI only defines numbering
4097 for the single precision registers. This will "just work"
4098 in GDB for little endian targets (we'll read eight bytes,
4099 starting in s0 and then progressing to s1), but will be
4100 reversed on big endian targets with VFP. This won't
4101 be a problem for the new Neon quad registers; you're supposed
4102 to use DW_OP_piece for those. */
4103 if (reg >= 64 && reg <= 95)
4107 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4108 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4112 /* VFP v3 / Neon registers. This range is also used for VFP v2
4113 registers, except that it now describes d0 instead of s0. */
4114 if (reg >= 256 && reg <= 287)
4118 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4119 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4126 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4128 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4131 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4133 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4134 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4136 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4137 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4139 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4140 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4142 if (reg < NUM_GREGS)
4143 return SIM_ARM_R0_REGNUM + reg;
4146 if (reg < NUM_FREGS)
4147 return SIM_ARM_FP0_REGNUM + reg;
4150 if (reg < NUM_SREGS)
4151 return SIM_ARM_FPS_REGNUM + reg;
4154 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4157 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4158 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4159 It is thought that this is is the floating-point register format on
4160 little-endian systems. */
4163 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4164 void *dbl, int endianess)
4168 if (endianess == BFD_ENDIAN_BIG)
4169 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4171 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4173 floatformat_from_doublest (fmt, &d, dbl);
4177 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4182 floatformat_to_doublest (fmt, ptr, &d);
4183 if (endianess == BFD_ENDIAN_BIG)
4184 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4186 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4191 condition_true (unsigned long cond, unsigned long status_reg)
4193 if (cond == INST_AL || cond == INST_NV)
4199 return ((status_reg & FLAG_Z) != 0);
4201 return ((status_reg & FLAG_Z) == 0);
4203 return ((status_reg & FLAG_C) != 0);
4205 return ((status_reg & FLAG_C) == 0);
4207 return ((status_reg & FLAG_N) != 0);
4209 return ((status_reg & FLAG_N) == 0);
4211 return ((status_reg & FLAG_V) != 0);
4213 return ((status_reg & FLAG_V) == 0);
4215 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4217 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4219 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4221 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4223 return (((status_reg & FLAG_Z) == 0)
4224 && (((status_reg & FLAG_N) == 0)
4225 == ((status_reg & FLAG_V) == 0)));
4227 return (((status_reg & FLAG_Z) != 0)
4228 || (((status_reg & FLAG_N) == 0)
4229 != ((status_reg & FLAG_V) == 0)));
4234 static unsigned long
4235 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4236 unsigned long pc_val, unsigned long status_reg)
4238 unsigned long res, shift;
4239 int rm = bits (inst, 0, 3);
4240 unsigned long shifttype = bits (inst, 5, 6);
4244 int rs = bits (inst, 8, 11);
4245 shift = (rs == 15 ? pc_val + 8
4246 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4249 shift = bits (inst, 7, 11);
4251 res = (rm == ARM_PC_REGNUM
4252 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4253 : get_frame_register_unsigned (frame, rm));
4258 res = shift >= 32 ? 0 : res << shift;
4262 res = shift >= 32 ? 0 : res >> shift;
4268 res = ((res & 0x80000000L)
4269 ? ~((~res) >> shift) : res >> shift);
4272 case 3: /* ROR/RRX */
4275 res = (res >> 1) | (carry ? 0x80000000L : 0);
4277 res = (res >> shift) | (res << (32 - shift));
4281 return res & 0xffffffff;
4284 /* Return number of 1-bits in VAL. */
4287 bitcount (unsigned long val)
4290 for (nbits = 0; val != 0; nbits++)
4291 val &= val - 1; /* Delete rightmost 1-bit in val. */
4295 /* Return the size in bytes of the complete Thumb instruction whose
4296 first halfword is INST1. */
4299 thumb_insn_size (unsigned short inst1)
4301 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4308 thumb_advance_itstate (unsigned int itstate)
4310 /* Preserve IT[7:5], the first three bits of the condition. Shift
4311 the upcoming condition flags left by one bit. */
4312 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4314 /* If we have finished the IT block, clear the state. */
4315 if ((itstate & 0x0f) == 0)
4321 /* Find the next PC after the current instruction executes. In some
4322 cases we can not statically determine the answer (see the IT state
4323 handling in this function); in that case, a breakpoint may be
4324 inserted in addition to the returned PC, which will be used to set
4325 another breakpoint by our caller. */
4328 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4330 struct gdbarch *gdbarch = get_frame_arch (frame);
4331 struct address_space *aspace = get_frame_address_space (frame);
4332 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4333 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4334 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4335 unsigned short inst1;
4336 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4337 unsigned long offset;
4338 ULONGEST status, itstate;
4340 nextpc = MAKE_THUMB_ADDR (nextpc);
4341 pc_val = MAKE_THUMB_ADDR (pc_val);
4343 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4345 /* Thumb-2 conditional execution support. There are eight bits in
4346 the CPSR which describe conditional execution state. Once
4347 reconstructed (they're in a funny order), the low five bits
4348 describe the low bit of the condition for each instruction and
4349 how many instructions remain. The high three bits describe the
4350 base condition. One of the low four bits will be set if an IT
4351 block is active. These bits read as zero on earlier
4353 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4354 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4356 /* If-Then handling. On GNU/Linux, where this routine is used, we
4357 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4358 can disable execution of the undefined instruction. So we might
4359 miss the breakpoint if we set it on a skipped conditional
4360 instruction. Because conditional instructions can change the
4361 flags, affecting the execution of further instructions, we may
4362 need to set two breakpoints. */
4364 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4366 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4368 /* An IT instruction. Because this instruction does not
4369 modify the flags, we can accurately predict the next
4370 executed instruction. */
4371 itstate = inst1 & 0x00ff;
4372 pc += thumb_insn_size (inst1);
4374 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4376 inst1 = read_memory_unsigned_integer (pc, 2,
4377 byte_order_for_code);
4378 pc += thumb_insn_size (inst1);
4379 itstate = thumb_advance_itstate (itstate);
4382 return MAKE_THUMB_ADDR (pc);
4384 else if (itstate != 0)
4386 /* We are in a conditional block. Check the condition. */
4387 if (! condition_true (itstate >> 4, status))
4389 /* Advance to the next executed instruction. */
4390 pc += thumb_insn_size (inst1);
4391 itstate = thumb_advance_itstate (itstate);
4393 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4395 inst1 = read_memory_unsigned_integer (pc, 2,
4396 byte_order_for_code);
4397 pc += thumb_insn_size (inst1);
4398 itstate = thumb_advance_itstate (itstate);
4401 return MAKE_THUMB_ADDR (pc);
4403 else if ((itstate & 0x0f) == 0x08)
4405 /* This is the last instruction of the conditional
4406 block, and it is executed. We can handle it normally
4407 because the following instruction is not conditional,
4408 and we must handle it normally because it is
4409 permitted to branch. Fall through. */
4415 /* There are conditional instructions after this one.
4416 If this instruction modifies the flags, then we can
4417 not predict what the next executed instruction will
4418 be. Fortunately, this instruction is architecturally
4419 forbidden to branch; we know it will fall through.
4420 Start by skipping past it. */
4421 pc += thumb_insn_size (inst1);
4422 itstate = thumb_advance_itstate (itstate);
4424 /* Set a breakpoint on the following instruction. */
4425 gdb_assert ((itstate & 0x0f) != 0);
4426 arm_insert_single_step_breakpoint (gdbarch, aspace,
4427 MAKE_THUMB_ADDR (pc));
4428 cond_negated = (itstate >> 4) & 1;
4430 /* Skip all following instructions with the same
4431 condition. If there is a later instruction in the IT
4432 block with the opposite condition, set the other
4433 breakpoint there. If not, then set a breakpoint on
4434 the instruction after the IT block. */
4437 inst1 = read_memory_unsigned_integer (pc, 2,
4438 byte_order_for_code);
4439 pc += thumb_insn_size (inst1);
4440 itstate = thumb_advance_itstate (itstate);
4442 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4444 return MAKE_THUMB_ADDR (pc);
4448 else if (itstate & 0x0f)
4450 /* We are in a conditional block. Check the condition. */
4451 int cond = itstate >> 4;
4453 if (! condition_true (cond, status))
4454 /* Advance to the next instruction. All the 32-bit
4455 instructions share a common prefix. */
4456 return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1));
4458 /* Otherwise, handle the instruction normally. */
4461 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4465 /* Fetch the saved PC from the stack. It's stored above
4466 all of the other registers. */
4467 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4468 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4469 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4471 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4473 unsigned long cond = bits (inst1, 8, 11);
4474 if (cond == 0x0f) /* 0x0f = SWI */
4476 struct gdbarch_tdep *tdep;
4477 tdep = gdbarch_tdep (gdbarch);
4479 if (tdep->syscall_next_pc != NULL)
4480 nextpc = tdep->syscall_next_pc (frame);
4483 else if (cond != 0x0f && condition_true (cond, status))
4484 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4486 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4488 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4490 else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */
4492 unsigned short inst2;
4493 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4495 /* Default to the next instruction. */
4497 nextpc = MAKE_THUMB_ADDR (nextpc);
4499 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4501 /* Branches and miscellaneous control instructions. */
4503 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4506 int j1, j2, imm1, imm2;
4508 imm1 = sbits (inst1, 0, 10);
4509 imm2 = bits (inst2, 0, 10);
4510 j1 = bit (inst2, 13);
4511 j2 = bit (inst2, 11);
4513 offset = ((imm1 << 12) + (imm2 << 1));
4514 offset ^= ((!j2) << 22) | ((!j1) << 23);
4516 nextpc = pc_val + offset;
4517 /* For BLX make sure to clear the low bits. */
4518 if (bit (inst2, 12) == 0)
4519 nextpc = nextpc & 0xfffffffc;
4521 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4523 /* SUBS PC, LR, #imm8. */
4524 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4525 nextpc -= inst2 & 0x00ff;
4527 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4529 /* Conditional branch. */
4530 if (condition_true (bits (inst1, 6, 9), status))
4532 int sign, j1, j2, imm1, imm2;
4534 sign = sbits (inst1, 10, 10);
4535 imm1 = bits (inst1, 0, 5);
4536 imm2 = bits (inst2, 0, 10);
4537 j1 = bit (inst2, 13);
4538 j2 = bit (inst2, 11);
4540 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4541 offset += (imm1 << 12) + (imm2 << 1);
4543 nextpc = pc_val + offset;
4547 else if ((inst1 & 0xfe50) == 0xe810)
4549 /* Load multiple or RFE. */
4550 int rn, offset, load_pc = 1;
4552 rn = bits (inst1, 0, 3);
4553 if (bit (inst1, 7) && !bit (inst1, 8))
4556 if (!bit (inst2, 15))
4558 offset = bitcount (inst2) * 4 - 4;
4560 else if (!bit (inst1, 7) && bit (inst1, 8))
4563 if (!bit (inst2, 15))
4567 else if (bit (inst1, 7) && bit (inst1, 8))
4572 else if (!bit (inst1, 7) && !bit (inst1, 8))
4582 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4583 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4586 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4588 /* MOV PC or MOVS PC. */
4589 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4590 nextpc = MAKE_THUMB_ADDR (nextpc);
4592 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4596 int rn, load_pc = 1;
4598 rn = bits (inst1, 0, 3);
4599 base = get_frame_register_unsigned (frame, rn);
4600 if (rn == ARM_PC_REGNUM)
4602 base = (base + 4) & ~(CORE_ADDR) 0x3;
4604 base += bits (inst2, 0, 11);
4606 base -= bits (inst2, 0, 11);
4608 else if (bit (inst1, 7))
4609 base += bits (inst2, 0, 11);
4610 else if (bit (inst2, 11))
4612 if (bit (inst2, 10))
4615 base += bits (inst2, 0, 7);
4617 base -= bits (inst2, 0, 7);
4620 else if ((inst2 & 0x0fc0) == 0x0000)
4622 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4623 base += get_frame_register_unsigned (frame, rm) << shift;
4630 nextpc = get_frame_memory_unsigned (frame, base, 4);
4632 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4635 CORE_ADDR tbl_reg, table, offset, length;
4637 tbl_reg = bits (inst1, 0, 3);
4638 if (tbl_reg == 0x0f)
4639 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4641 table = get_frame_register_unsigned (frame, tbl_reg);
4643 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4644 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4645 nextpc = pc_val + length;
4647 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4650 CORE_ADDR tbl_reg, table, offset, length;
4652 tbl_reg = bits (inst1, 0, 3);
4653 if (tbl_reg == 0x0f)
4654 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4656 table = get_frame_register_unsigned (frame, tbl_reg);
4658 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4659 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4660 nextpc = pc_val + length;
4663 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4665 if (bits (inst1, 3, 6) == 0x0f)
4666 nextpc = UNMAKE_THUMB_ADDR (pc_val);
4668 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4670 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4672 if (bits (inst1, 3, 6) == 0x0f)
4675 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4677 nextpc = MAKE_THUMB_ADDR (nextpc);
4679 else if ((inst1 & 0xf500) == 0xb100)
4682 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4683 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4685 if (bit (inst1, 11) && reg != 0)
4686 nextpc = pc_val + imm;
4687 else if (!bit (inst1, 11) && reg == 0)
4688 nextpc = pc_val + imm;
4693 /* Get the raw next address. PC is the current program counter, in
4694 FRAME, which is assumed to be executing in ARM mode.
4696 The value returned has the execution state of the next instruction
4697 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4698 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4702 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4704 struct gdbarch *gdbarch = get_frame_arch (frame);
4705 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4706 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4707 unsigned long pc_val;
4708 unsigned long this_instr;
4709 unsigned long status;
4712 pc_val = (unsigned long) pc;
4713 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4715 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4716 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4718 if (bits (this_instr, 28, 31) == INST_NV)
4719 switch (bits (this_instr, 24, 27))
4724 /* Branch with Link and change to Thumb. */
4725 nextpc = BranchDest (pc, this_instr);
4726 nextpc |= bit (this_instr, 24) << 1;
4727 nextpc = MAKE_THUMB_ADDR (nextpc);
4733 /* Coprocessor register transfer. */
4734 if (bits (this_instr, 12, 15) == 15)
4735 error (_("Invalid update to pc in instruction"));
4738 else if (condition_true (bits (this_instr, 28, 31), status))
4740 switch (bits (this_instr, 24, 27))
4743 case 0x1: /* data processing */
4747 unsigned long operand1, operand2, result = 0;
4751 if (bits (this_instr, 12, 15) != 15)
4754 if (bits (this_instr, 22, 25) == 0
4755 && bits (this_instr, 4, 7) == 9) /* multiply */
4756 error (_("Invalid update to pc in instruction"));
4758 /* BX <reg>, BLX <reg> */
4759 if (bits (this_instr, 4, 27) == 0x12fff1
4760 || bits (this_instr, 4, 27) == 0x12fff3)
4762 rn = bits (this_instr, 0, 3);
4763 nextpc = ((rn == ARM_PC_REGNUM)
4765 : get_frame_register_unsigned (frame, rn));
4770 /* Multiply into PC. */
4771 c = (status & FLAG_C) ? 1 : 0;
4772 rn = bits (this_instr, 16, 19);
4773 operand1 = ((rn == ARM_PC_REGNUM)
4775 : get_frame_register_unsigned (frame, rn));
4777 if (bit (this_instr, 25))
4779 unsigned long immval = bits (this_instr, 0, 7);
4780 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4781 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4784 else /* operand 2 is a shifted register. */
4785 operand2 = shifted_reg_val (frame, this_instr, c,
4788 switch (bits (this_instr, 21, 24))
4791 result = operand1 & operand2;
4795 result = operand1 ^ operand2;
4799 result = operand1 - operand2;
4803 result = operand2 - operand1;
4807 result = operand1 + operand2;
4811 result = operand1 + operand2 + c;
4815 result = operand1 - operand2 + c;
4819 result = operand2 - operand1 + c;
4825 case 0xb: /* tst, teq, cmp, cmn */
4826 result = (unsigned long) nextpc;
4830 result = operand1 | operand2;
4834 /* Always step into a function. */
4839 result = operand1 & ~operand2;
4847 /* In 26-bit APCS the bottom two bits of the result are
4848 ignored, and we always end up in ARM state. */
4850 nextpc = arm_addr_bits_remove (gdbarch, result);
4858 case 0x5: /* data transfer */
4861 if (bit (this_instr, 20))
4864 if (bits (this_instr, 12, 15) == 15)
4870 if (bit (this_instr, 22))
4871 error (_("Invalid update to pc in instruction"));
4873 /* byte write to PC */
4874 rn = bits (this_instr, 16, 19);
4875 base = ((rn == ARM_PC_REGNUM)
4877 : get_frame_register_unsigned (frame, rn));
4879 if (bit (this_instr, 24))
4882 int c = (status & FLAG_C) ? 1 : 0;
4883 unsigned long offset =
4884 (bit (this_instr, 25)
4885 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4886 : bits (this_instr, 0, 11));
4888 if (bit (this_instr, 23))
4894 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base,
4901 case 0x9: /* block transfer */
4902 if (bit (this_instr, 20))
4905 if (bit (this_instr, 15))
4909 unsigned long rn_val
4910 = get_frame_register_unsigned (frame,
4911 bits (this_instr, 16, 19));
4913 if (bit (this_instr, 23))
4916 unsigned long reglist = bits (this_instr, 0, 14);
4917 offset = bitcount (reglist) * 4;
4918 if (bit (this_instr, 24)) /* pre */
4921 else if (bit (this_instr, 24))
4925 (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR)
4932 case 0xb: /* branch & link */
4933 case 0xa: /* branch */
4935 nextpc = BranchDest (pc, this_instr);
4941 case 0xe: /* coproc ops */
4945 struct gdbarch_tdep *tdep;
4946 tdep = gdbarch_tdep (gdbarch);
4948 if (tdep->syscall_next_pc != NULL)
4949 nextpc = tdep->syscall_next_pc (frame);
4955 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4963 /* Determine next PC after current instruction executes. Will call either
4964 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4965 loop is detected. */
4968 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4972 if (arm_frame_is_thumb (frame))
4974 nextpc = thumb_get_next_pc_raw (frame, pc);
4975 if (nextpc == MAKE_THUMB_ADDR (pc))
4976 error (_("Infinite loop detected"));
4980 nextpc = arm_get_next_pc_raw (frame, pc);
4982 error (_("Infinite loop detected"));
4988 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4989 of the appropriate mode (as encoded in the PC value), even if this
4990 differs from what would be expected according to the symbol tables. */
4993 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
4994 struct address_space *aspace,
4997 struct cleanup *old_chain
4998 = make_cleanup_restore_integer (&arm_override_mode);
5000 arm_override_mode = IS_THUMB_ADDR (pc);
5001 pc = gdbarch_addr_bits_remove (gdbarch, pc);
5003 insert_single_step_breakpoint (gdbarch, aspace, pc);
5005 do_cleanups (old_chain);
5008 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5009 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5010 is found, attempt to step through it. A breakpoint is placed at the end of
5014 thumb_deal_with_atomic_sequence_raw (struct frame_info *frame)
5016 struct gdbarch *gdbarch = get_frame_arch (frame);
5017 struct address_space *aspace = get_frame_address_space (frame);
5018 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5019 CORE_ADDR pc = get_frame_pc (frame);
5020 CORE_ADDR breaks[2] = {-1, -1};
5022 unsigned short insn1, insn2;
5025 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5026 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5027 ULONGEST status, itstate;
5029 /* We currently do not support atomic sequences within an IT block. */
5030 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
5031 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5035 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5036 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5038 if (thumb_insn_size (insn1) != 4)
5041 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5043 if (!((insn1 & 0xfff0) == 0xe850
5044 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5047 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5049 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5051 insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5054 if (thumb_insn_size (insn1) != 4)
5056 /* Assume that there is at most one conditional branch in the
5057 atomic sequence. If a conditional branch is found, put a
5058 breakpoint in its destination address. */
5059 if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
5061 if (last_breakpoint > 0)
5062 return 0; /* More than one conditional branch found,
5063 fallback to the standard code. */
5065 breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
5069 /* We do not support atomic sequences that use any *other*
5070 instructions but conditional branches to change the PC.
5071 Fall back to standard code to avoid losing control of
5073 else if (thumb_instruction_changes_pc (insn1))
5078 insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code);
5081 /* Assume that there is at most one conditional branch in the
5082 atomic sequence. If a conditional branch is found, put a
5083 breakpoint in its destination address. */
5084 if ((insn1 & 0xf800) == 0xf000
5085 && (insn2 & 0xd000) == 0x8000
5086 && (insn1 & 0x0380) != 0x0380)
5088 int sign, j1, j2, imm1, imm2;
5089 unsigned int offset;
5091 sign = sbits (insn1, 10, 10);
5092 imm1 = bits (insn1, 0, 5);
5093 imm2 = bits (insn2, 0, 10);
5094 j1 = bit (insn2, 13);
5095 j2 = bit (insn2, 11);
5097 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5098 offset += (imm1 << 12) + (imm2 << 1);
5100 if (last_breakpoint > 0)
5101 return 0; /* More than one conditional branch found,
5102 fallback to the standard code. */
5104 breaks[1] = loc + offset;
5108 /* We do not support atomic sequences that use any *other*
5109 instructions but conditional branches to change the PC.
5110 Fall back to standard code to avoid losing control of
5112 else if (thumb2_instruction_changes_pc (insn1, insn2))
5115 /* If we find a strex{,b,h,d}, we're done. */
5116 if ((insn1 & 0xfff0) == 0xe840
5117 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5122 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5123 if (insn_count == atomic_sequence_length)
5126 /* Insert a breakpoint right after the end of the atomic sequence. */
5129 /* Check for duplicated breakpoints. Check also for a breakpoint
5130 placed (branch instruction's destination) anywhere in sequence. */
5132 && (breaks[1] == breaks[0]
5133 || (breaks[1] >= pc && breaks[1] < loc)))
5134 last_breakpoint = 0;
5136 /* Effectively inserts the breakpoints. */
5137 for (index = 0; index <= last_breakpoint; index++)
5138 arm_insert_single_step_breakpoint (gdbarch, aspace,
5139 MAKE_THUMB_ADDR (breaks[index]));
5145 arm_deal_with_atomic_sequence_raw (struct frame_info *frame)
5147 struct gdbarch *gdbarch = get_frame_arch (frame);
5148 struct address_space *aspace = get_frame_address_space (frame);
5149 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
5150 CORE_ADDR pc = get_frame_pc (frame);
5151 CORE_ADDR breaks[2] = {-1, -1};
5156 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
5157 const int atomic_sequence_length = 16; /* Instruction sequence length. */
5159 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5160 Note that we do not currently support conditionally executed atomic
5162 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5164 if ((insn & 0xff9000f0) != 0xe1900090)
5167 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5169 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5171 insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code);
5174 /* Assume that there is at most one conditional branch in the atomic
5175 sequence. If a conditional branch is found, put a breakpoint in
5176 its destination address. */
5177 if (bits (insn, 24, 27) == 0xa)
5179 if (last_breakpoint > 0)
5180 return 0; /* More than one conditional branch found, fallback
5181 to the standard single-step code. */
5183 breaks[1] = BranchDest (loc - 4, insn);
5187 /* We do not support atomic sequences that use any *other* instructions
5188 but conditional branches to change the PC. Fall back to standard
5189 code to avoid losing control of execution. */
5190 else if (arm_instruction_changes_pc (insn))
5193 /* If we find a strex{,b,h,d}, we're done. */
5194 if ((insn & 0xff9000f0) == 0xe1800090)
5198 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5199 if (insn_count == atomic_sequence_length)
5202 /* Insert a breakpoint right after the end of the atomic sequence. */
5205 /* Check for duplicated breakpoints. Check also for a breakpoint
5206 placed (branch instruction's destination) anywhere in sequence. */
5208 && (breaks[1] == breaks[0]
5209 || (breaks[1] >= pc && breaks[1] < loc)))
5210 last_breakpoint = 0;
5212 /* Effectively inserts the breakpoints. */
5213 for (index = 0; index <= last_breakpoint; index++)
5214 arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
5220 arm_deal_with_atomic_sequence (struct frame_info *frame)
5222 if (arm_frame_is_thumb (frame))
5223 return thumb_deal_with_atomic_sequence_raw (frame);
5225 return arm_deal_with_atomic_sequence_raw (frame);
5228 /* single_step() is called just before we want to resume the inferior,
5229 if we want to single-step it but there is no hardware or kernel
5230 single-step support. We find the target of the coming instruction
5231 and breakpoint it. */
5234 arm_software_single_step (struct frame_info *frame)
5236 struct gdbarch *gdbarch = get_frame_arch (frame);
5237 struct address_space *aspace = get_frame_address_space (frame);
5240 if (arm_deal_with_atomic_sequence (frame))
5243 next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
5244 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
5249 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5250 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5251 NULL if an error occurs. BUF is freed. */
5254 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
5255 int old_len, int new_len)
5258 int bytes_to_read = new_len - old_len;
5260 new_buf = xmalloc (new_len);
5261 memcpy (new_buf + bytes_to_read, buf, old_len);
5263 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
5271 /* An IT block is at most the 2-byte IT instruction followed by
5272 four 4-byte instructions. The furthest back we must search to
5273 find an IT block that affects the current instruction is thus
5274 2 + 3 * 4 == 14 bytes. */
5275 #define MAX_IT_BLOCK_PREFIX 14
5277 /* Use a quick scan if there are more than this many bytes of
5279 #define IT_SCAN_THRESHOLD 32
5281 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5282 A breakpoint in an IT block may not be hit, depending on the
5285 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
5289 CORE_ADDR boundary, func_start;
5291 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
5292 int i, any, last_it, last_it_count;
5294 /* If we are using BKPT breakpoints, none of this is necessary. */
5295 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
5298 /* ARM mode does not have this problem. */
5299 if (!arm_pc_is_thumb (gdbarch, bpaddr))
5302 /* We are setting a breakpoint in Thumb code that could potentially
5303 contain an IT block. The first step is to find how much Thumb
5304 code there is; we do not need to read outside of known Thumb
5306 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
5308 /* Thumb-2 code must have mapping symbols to have a chance. */
5311 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
5313 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
5314 && func_start > boundary)
5315 boundary = func_start;
5317 /* Search for a candidate IT instruction. We have to do some fancy
5318 footwork to distinguish a real IT instruction from the second
5319 half of a 32-bit instruction, but there is no need for that if
5320 there's no candidate. */
5321 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
5323 /* No room for an IT instruction. */
5326 buf = xmalloc (buf_len);
5327 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
5330 for (i = 0; i < buf_len; i += 2)
5332 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5333 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5345 /* OK, the code bytes before this instruction contain at least one
5346 halfword which resembles an IT instruction. We know that it's
5347 Thumb code, but there are still two possibilities. Either the
5348 halfword really is an IT instruction, or it is the second half of
5349 a 32-bit Thumb instruction. The only way we can tell is to
5350 scan forwards from a known instruction boundary. */
5351 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5355 /* There's a lot of code before this instruction. Start with an
5356 optimistic search; it's easy to recognize halfwords that can
5357 not be the start of a 32-bit instruction, and use that to
5358 lock on to the instruction boundaries. */
5359 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5362 buf_len = IT_SCAN_THRESHOLD;
5365 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5367 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5368 if (thumb_insn_size (inst1) == 2)
5375 /* At this point, if DEFINITE, BUF[I] is the first place we
5376 are sure that we know the instruction boundaries, and it is far
5377 enough from BPADDR that we could not miss an IT instruction
5378 affecting BPADDR. If ! DEFINITE, give up - start from a
5382 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5386 buf_len = bpaddr - boundary;
5392 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5395 buf_len = bpaddr - boundary;
5399 /* Scan forwards. Find the last IT instruction before BPADDR. */
5404 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5406 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5411 else if (inst1 & 0x0002)
5413 else if (inst1 & 0x0004)
5418 i += thumb_insn_size (inst1);
5424 /* There wasn't really an IT instruction after all. */
5427 if (last_it_count < 1)
5428 /* It was too far away. */
5431 /* This really is a trouble spot. Move the breakpoint to the IT
5433 return bpaddr - buf_len + last_it;
5436 /* ARM displaced stepping support.
5438 Generally ARM displaced stepping works as follows:
5440 1. When an instruction is to be single-stepped, it is first decoded by
5441 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5442 Depending on the type of instruction, it is then copied to a scratch
5443 location, possibly in a modified form. The copy_* set of functions
5444 performs such modification, as necessary. A breakpoint is placed after
5445 the modified instruction in the scratch space to return control to GDB.
5446 Note in particular that instructions which modify the PC will no longer
5447 do so after modification.
5449 2. The instruction is single-stepped, by setting the PC to the scratch
5450 location address, and resuming. Control returns to GDB when the
5453 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5454 function used for the current instruction. This function's job is to
5455 put the CPU/memory state back to what it would have been if the
5456 instruction had been executed unmodified in its original location. */
5458 /* NOP instruction (mov r0, r0). */
5459 #define ARM_NOP 0xe1a00000
5460 #define THUMB_NOP 0x4600
5462 /* Helper for register reads for displaced stepping. In particular, this
5463 returns the PC as it would be seen by the instruction at its original
5467 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5471 CORE_ADDR from = dsc->insn_addr;
5473 if (regno == ARM_PC_REGNUM)
5475 /* Compute pipeline offset:
5476 - When executing an ARM instruction, PC reads as the address of the
5477 current instruction plus 8.
5478 - When executing a Thumb instruction, PC reads as the address of the
5479 current instruction plus 4. */
5486 if (debug_displaced)
5487 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5488 (unsigned long) from);
5489 return (ULONGEST) from;
5493 regcache_cooked_read_unsigned (regs, regno, &ret);
5494 if (debug_displaced)
5495 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5496 regno, (unsigned long) ret);
5502 displaced_in_arm_mode (struct regcache *regs)
5505 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5507 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5509 return (ps & t_bit) == 0;
5512 /* Write to the PC as from a branch instruction. */
5515 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5519 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5520 architecture versions < 6. */
5521 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5522 val & ~(ULONGEST) 0x3);
5524 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5525 val & ~(ULONGEST) 0x1);
5528 /* Write to the PC as from a branch-exchange instruction. */
5531 bx_write_pc (struct regcache *regs, ULONGEST val)
5534 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5536 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5540 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5541 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5543 else if ((val & 2) == 0)
5545 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5546 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5550 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5551 mode, align dest to 4 bytes). */
5552 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5553 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5554 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5558 /* Write to the PC as if from a load instruction. */
5561 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5564 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5565 bx_write_pc (regs, val);
5567 branch_write_pc (regs, dsc, val);
5570 /* Write to the PC as if from an ALU instruction. */
5573 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5576 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5577 bx_write_pc (regs, val);
5579 branch_write_pc (regs, dsc, val);
5582 /* Helper for writing to registers for displaced stepping. Writing to the PC
5583 has a varying effects depending on the instruction which does the write:
5584 this is controlled by the WRITE_PC argument. */
5587 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5588 int regno, ULONGEST val, enum pc_write_style write_pc)
5590 if (regno == ARM_PC_REGNUM)
5592 if (debug_displaced)
5593 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5594 (unsigned long) val);
5597 case BRANCH_WRITE_PC:
5598 branch_write_pc (regs, dsc, val);
5602 bx_write_pc (regs, val);
5606 load_write_pc (regs, dsc, val);
5610 alu_write_pc (regs, dsc, val);
5613 case CANNOT_WRITE_PC:
5614 warning (_("Instruction wrote to PC in an unexpected way when "
5615 "single-stepping"));
5619 internal_error (__FILE__, __LINE__,
5620 _("Invalid argument to displaced_write_reg"));
5623 dsc->wrote_to_pc = 1;
5627 if (debug_displaced)
5628 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5629 regno, (unsigned long) val);
5630 regcache_cooked_write_unsigned (regs, regno, val);
5634 /* This function is used to concisely determine if an instruction INSN
5635 references PC. Register fields of interest in INSN should have the
5636 corresponding fields of BITMASK set to 0b1111. The function
5637 returns return 1 if any of these fields in INSN reference the PC
5638 (also 0b1111, r15), else it returns 0. */
5641 insn_references_pc (uint32_t insn, uint32_t bitmask)
5643 uint32_t lowbit = 1;
5645 while (bitmask != 0)
5649 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5655 mask = lowbit * 0xf;
5657 if ((insn & mask) == mask)
5666 /* The simplest copy function. Many instructions have the same effect no
5667 matter what address they are executed at: in those cases, use this. */
5670 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5671 const char *iname, struct displaced_step_closure *dsc)
5673 if (debug_displaced)
5674 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5675 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5678 dsc->modinsn[0] = insn;
5684 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
5685 uint16_t insn2, const char *iname,
5686 struct displaced_step_closure *dsc)
5688 if (debug_displaced)
5689 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
5690 "opcode/class '%s' unmodified\n", insn1, insn2,
5693 dsc->modinsn[0] = insn1;
5694 dsc->modinsn[1] = insn2;
5700 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5703 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn,
5705 struct displaced_step_closure *dsc)
5707 if (debug_displaced)
5708 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
5709 "opcode/class '%s' unmodified\n", insn,
5712 dsc->modinsn[0] = insn;
5717 /* Preload instructions with immediate offset. */
5720 cleanup_preload (struct gdbarch *gdbarch,
5721 struct regcache *regs, struct displaced_step_closure *dsc)
5723 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5724 if (!dsc->u.preload.immed)
5725 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5729 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5730 struct displaced_step_closure *dsc, unsigned int rn)
5733 /* Preload instructions:
5735 {pli/pld} [rn, #+/-imm]
5737 {pli/pld} [r0, #+/-imm]. */
5739 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5740 rn_val = displaced_read_reg (regs, dsc, rn);
5741 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5742 dsc->u.preload.immed = 1;
5744 dsc->cleanup = &cleanup_preload;
5748 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5749 struct displaced_step_closure *dsc)
5751 unsigned int rn = bits (insn, 16, 19);
5753 if (!insn_references_pc (insn, 0x000f0000ul))
5754 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5756 if (debug_displaced)
5757 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5758 (unsigned long) insn);
5760 dsc->modinsn[0] = insn & 0xfff0ffff;
5762 install_preload (gdbarch, regs, dsc, rn);
5768 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
5769 struct regcache *regs, struct displaced_step_closure *dsc)
5771 unsigned int rn = bits (insn1, 0, 3);
5772 unsigned int u_bit = bit (insn1, 7);
5773 int imm12 = bits (insn2, 0, 11);
5776 if (rn != ARM_PC_REGNUM)
5777 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5779 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5780 PLD (literal) Encoding T1. */
5781 if (debug_displaced)
5782 fprintf_unfiltered (gdb_stdlog,
5783 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5784 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5790 /* Rewrite instruction {pli/pld} PC imm12 into:
5791 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5795 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5797 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5798 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5800 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5802 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5803 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5804 dsc->u.preload.immed = 0;
5806 /* {pli/pld} [r0, r1] */
5807 dsc->modinsn[0] = insn1 & 0xfff0;
5808 dsc->modinsn[1] = 0xf001;
5811 dsc->cleanup = &cleanup_preload;
5815 /* Preload instructions with register offset. */
5818 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5819 struct displaced_step_closure *dsc, unsigned int rn,
5822 ULONGEST rn_val, rm_val;
5824 /* Preload register-offset instructions:
5826 {pli/pld} [rn, rm {, shift}]
5828 {pli/pld} [r0, r1 {, shift}]. */
5830 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5831 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5832 rn_val = displaced_read_reg (regs, dsc, rn);
5833 rm_val = displaced_read_reg (regs, dsc, rm);
5834 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5835 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5836 dsc->u.preload.immed = 0;
5838 dsc->cleanup = &cleanup_preload;
5842 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5843 struct regcache *regs,
5844 struct displaced_step_closure *dsc)
5846 unsigned int rn = bits (insn, 16, 19);
5847 unsigned int rm = bits (insn, 0, 3);
5850 if (!insn_references_pc (insn, 0x000f000ful))
5851 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5853 if (debug_displaced)
5854 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5855 (unsigned long) insn);
5857 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5859 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5863 /* Copy/cleanup coprocessor load and store instructions. */
5866 cleanup_copro_load_store (struct gdbarch *gdbarch,
5867 struct regcache *regs,
5868 struct displaced_step_closure *dsc)
5870 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5872 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5874 if (dsc->u.ldst.writeback)
5875 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5879 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5880 struct displaced_step_closure *dsc,
5881 int writeback, unsigned int rn)
5885 /* Coprocessor load/store instructions:
5887 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5889 {stc/stc2} [r0, #+/-imm].
5891 ldc/ldc2 are handled identically. */
5893 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5894 rn_val = displaced_read_reg (regs, dsc, rn);
5895 /* PC should be 4-byte aligned. */
5896 rn_val = rn_val & 0xfffffffc;
5897 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5899 dsc->u.ldst.writeback = writeback;
5900 dsc->u.ldst.rn = rn;
5902 dsc->cleanup = &cleanup_copro_load_store;
5906 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5907 struct regcache *regs,
5908 struct displaced_step_closure *dsc)
5910 unsigned int rn = bits (insn, 16, 19);
5912 if (!insn_references_pc (insn, 0x000f0000ul))
5913 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5915 if (debug_displaced)
5916 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5917 "load/store insn %.8lx\n", (unsigned long) insn);
5919 dsc->modinsn[0] = insn & 0xfff0ffff;
5921 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5927 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
5928 uint16_t insn2, struct regcache *regs,
5929 struct displaced_step_closure *dsc)
5931 unsigned int rn = bits (insn1, 0, 3);
5933 if (rn != ARM_PC_REGNUM)
5934 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
5935 "copro load/store", dsc);
5937 if (debug_displaced)
5938 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5939 "load/store insn %.4x%.4x\n", insn1, insn2);
5941 dsc->modinsn[0] = insn1 & 0xfff0;
5942 dsc->modinsn[1] = insn2;
5945 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5946 doesn't support writeback, so pass 0. */
5947 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
5952 /* Clean up branch instructions (actually perform the branch, by setting
5956 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
5957 struct displaced_step_closure *dsc)
5959 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5960 int branch_taken = condition_true (dsc->u.branch.cond, status);
5961 enum pc_write_style write_pc = dsc->u.branch.exchange
5962 ? BX_WRITE_PC : BRANCH_WRITE_PC;
5967 if (dsc->u.branch.link)
5969 /* The value of LR should be the next insn of current one. In order
5970 not to confuse logic hanlding later insn `bx lr', if current insn mode
5971 is Thumb, the bit 0 of LR value should be set to 1. */
5972 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5975 next_insn_addr |= 0x1;
5977 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5981 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5984 /* Copy B/BL/BLX instructions with immediate destinations. */
5987 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
5988 struct displaced_step_closure *dsc,
5989 unsigned int cond, int exchange, int link, long offset)
5991 /* Implement "BL<cond> <label>" as:
5993 Preparation: cond <- instruction condition
5994 Insn: mov r0, r0 (nop)
5995 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5997 B<cond> similar, but don't set r14 in cleanup. */
5999 dsc->u.branch.cond = cond;
6000 dsc->u.branch.link = link;
6001 dsc->u.branch.exchange = exchange;
6003 dsc->u.branch.dest = dsc->insn_addr;
6004 if (link && exchange)
6005 /* For BLX, offset is computed from the Align (PC, 4). */
6006 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6009 dsc->u.branch.dest += 4 + offset;
6011 dsc->u.branch.dest += 8 + offset;
6013 dsc->cleanup = &cleanup_branch;
6016 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
6017 struct regcache *regs, struct displaced_step_closure *dsc)
6019 unsigned int cond = bits (insn, 28, 31);
6020 int exchange = (cond == 0xf);
6021 int link = exchange || bit (insn, 24);
6024 if (debug_displaced)
6025 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
6026 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
6027 (unsigned long) insn);
6029 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6030 then arrange the switch into Thumb mode. */
6031 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
6033 offset = bits (insn, 0, 23) << 2;
6035 if (bit (offset, 25))
6036 offset = offset | ~0x3ffffff;
6038 dsc->modinsn[0] = ARM_NOP;
6040 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6045 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
6046 uint16_t insn2, struct regcache *regs,
6047 struct displaced_step_closure *dsc)
6049 int link = bit (insn2, 14);
6050 int exchange = link && !bit (insn2, 12);
6053 int j1 = bit (insn2, 13);
6054 int j2 = bit (insn2, 11);
6055 int s = sbits (insn1, 10, 10);
6056 int i1 = !(j1 ^ bit (insn1, 10));
6057 int i2 = !(j2 ^ bit (insn1, 10));
6059 if (!link && !exchange) /* B */
6061 offset = (bits (insn2, 0, 10) << 1);
6062 if (bit (insn2, 12)) /* Encoding T4 */
6064 offset |= (bits (insn1, 0, 9) << 12)
6070 else /* Encoding T3 */
6072 offset |= (bits (insn1, 0, 5) << 12)
6076 cond = bits (insn1, 6, 9);
6081 offset = (bits (insn1, 0, 9) << 12);
6082 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6083 offset |= exchange ?
6084 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
6087 if (debug_displaced)
6088 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
6089 "%.4x %.4x with offset %.8lx\n",
6090 link ? (exchange) ? "blx" : "bl" : "b",
6091 insn1, insn2, offset);
6093 dsc->modinsn[0] = THUMB_NOP;
6095 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6099 /* Copy B Thumb instructions. */
6101 thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn,
6102 struct displaced_step_closure *dsc)
6104 unsigned int cond = 0;
6106 unsigned short bit_12_15 = bits (insn, 12, 15);
6107 CORE_ADDR from = dsc->insn_addr;
6109 if (bit_12_15 == 0xd)
6111 /* offset = SignExtend (imm8:0, 32) */
6112 offset = sbits ((insn << 1), 0, 8);
6113 cond = bits (insn, 8, 11);
6115 else if (bit_12_15 == 0xe) /* Encoding T2 */
6117 offset = sbits ((insn << 1), 0, 11);
6121 if (debug_displaced)
6122 fprintf_unfiltered (gdb_stdlog,
6123 "displaced: copying b immediate insn %.4x "
6124 "with offset %d\n", insn, offset);
6126 dsc->u.branch.cond = cond;
6127 dsc->u.branch.link = 0;
6128 dsc->u.branch.exchange = 0;
6129 dsc->u.branch.dest = from + 4 + offset;
6131 dsc->modinsn[0] = THUMB_NOP;
6133 dsc->cleanup = &cleanup_branch;
6138 /* Copy BX/BLX with register-specified destinations. */
6141 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
6142 struct displaced_step_closure *dsc, int link,
6143 unsigned int cond, unsigned int rm)
6145 /* Implement {BX,BLX}<cond> <reg>" as:
6147 Preparation: cond <- instruction condition
6148 Insn: mov r0, r0 (nop)
6149 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6151 Don't set r14 in cleanup for BX. */
6153 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6155 dsc->u.branch.cond = cond;
6156 dsc->u.branch.link = link;
6158 dsc->u.branch.exchange = 1;
6160 dsc->cleanup = &cleanup_branch;
6164 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
6165 struct regcache *regs, struct displaced_step_closure *dsc)
6167 unsigned int cond = bits (insn, 28, 31);
6170 int link = bit (insn, 5);
6171 unsigned int rm = bits (insn, 0, 3);
6173 if (debug_displaced)
6174 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
6175 (unsigned long) insn);
6177 dsc->modinsn[0] = ARM_NOP;
6179 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6184 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
6185 struct regcache *regs,
6186 struct displaced_step_closure *dsc)
6188 int link = bit (insn, 7);
6189 unsigned int rm = bits (insn, 3, 6);
6191 if (debug_displaced)
6192 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
6193 (unsigned short) insn);
6195 dsc->modinsn[0] = THUMB_NOP;
6197 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6203 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6206 cleanup_alu_imm (struct gdbarch *gdbarch,
6207 struct regcache *regs, struct displaced_step_closure *dsc)
6209 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6210 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6211 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6212 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6216 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6217 struct displaced_step_closure *dsc)
6219 unsigned int rn = bits (insn, 16, 19);
6220 unsigned int rd = bits (insn, 12, 15);
6221 unsigned int op = bits (insn, 21, 24);
6222 int is_mov = (op == 0xd);
6223 ULONGEST rd_val, rn_val;
6225 if (!insn_references_pc (insn, 0x000ff000ul))
6226 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6228 if (debug_displaced)
6229 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
6230 "%.8lx\n", is_mov ? "move" : "ALU",
6231 (unsigned long) insn);
6233 /* Instruction is of form:
6235 <op><cond> rd, [rn,] #imm
6239 Preparation: tmp1, tmp2 <- r0, r1;
6241 Insn: <op><cond> r0, r1, #imm
6242 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6245 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6246 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6247 rn_val = displaced_read_reg (regs, dsc, rn);
6248 rd_val = displaced_read_reg (regs, dsc, rd);
6249 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6250 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6254 dsc->modinsn[0] = insn & 0xfff00fff;
6256 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6258 dsc->cleanup = &cleanup_alu_imm;
6264 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
6265 uint16_t insn2, struct regcache *regs,
6266 struct displaced_step_closure *dsc)
6268 unsigned int op = bits (insn1, 5, 8);
6269 unsigned int rn, rm, rd;
6270 ULONGEST rd_val, rn_val;
6272 rn = bits (insn1, 0, 3); /* Rn */
6273 rm = bits (insn2, 0, 3); /* Rm */
6274 rd = bits (insn2, 8, 11); /* Rd */
6276 /* This routine is only called for instruction MOV. */
6277 gdb_assert (op == 0x2 && rn == 0xf);
6279 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
6280 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6282 if (debug_displaced)
6283 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
6284 "ALU", insn1, insn2);
6286 /* Instruction is of form:
6288 <op><cond> rd, [rn,] #imm
6292 Preparation: tmp1, tmp2 <- r0, r1;
6294 Insn: <op><cond> r0, r1, #imm
6295 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6298 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6299 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6300 rn_val = displaced_read_reg (regs, dsc, rn);
6301 rd_val = displaced_read_reg (regs, dsc, rd);
6302 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6303 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6306 dsc->modinsn[0] = insn1;
6307 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6310 dsc->cleanup = &cleanup_alu_imm;
6315 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6318 cleanup_alu_reg (struct gdbarch *gdbarch,
6319 struct regcache *regs, struct displaced_step_closure *dsc)
6324 rd_val = displaced_read_reg (regs, dsc, 0);
6326 for (i = 0; i < 3; i++)
6327 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6329 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6333 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
6334 struct displaced_step_closure *dsc,
6335 unsigned int rd, unsigned int rn, unsigned int rm)
6337 ULONGEST rd_val, rn_val, rm_val;
6339 /* Instruction is of form:
6341 <op><cond> rd, [rn,] rm [, <shift>]
6345 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6346 r0, r1, r2 <- rd, rn, rm
6347 Insn: <op><cond> r0, r1, r2 [, <shift>]
6348 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6351 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6352 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6353 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6354 rd_val = displaced_read_reg (regs, dsc, rd);
6355 rn_val = displaced_read_reg (regs, dsc, rn);
6356 rm_val = displaced_read_reg (regs, dsc, rm);
6357 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6358 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6359 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6362 dsc->cleanup = &cleanup_alu_reg;
6366 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
6367 struct displaced_step_closure *dsc)
6369 unsigned int op = bits (insn, 21, 24);
6370 int is_mov = (op == 0xd);
6372 if (!insn_references_pc (insn, 0x000ff00ful))
6373 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6375 if (debug_displaced)
6376 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
6377 is_mov ? "move" : "ALU", (unsigned long) insn);
6380 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6382 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6384 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6390 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
6391 struct regcache *regs,
6392 struct displaced_step_closure *dsc)
6394 unsigned rn, rm, rd;
6396 rd = bits (insn, 3, 6);
6397 rn = (bit (insn, 7) << 3) | bits (insn, 0, 2);
6400 if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6401 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6403 if (debug_displaced)
6404 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n",
6405 "ALU", (unsigned short) insn);
6407 dsc->modinsn[0] = ((insn & 0xff00) | 0x08);
6409 install_alu_reg (gdbarch, regs, dsc, rd, rn, rm);
6414 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6417 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
6418 struct regcache *regs,
6419 struct displaced_step_closure *dsc)
6421 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6424 for (i = 0; i < 4; i++)
6425 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6427 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6431 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
6432 struct displaced_step_closure *dsc,
6433 unsigned int rd, unsigned int rn, unsigned int rm,
6437 ULONGEST rd_val, rn_val, rm_val, rs_val;
6439 /* Instruction is of form:
6441 <op><cond> rd, [rn,] rm, <shift> rs
6445 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6446 r0, r1, r2, r3 <- rd, rn, rm, rs
6447 Insn: <op><cond> r0, r1, r2, <shift> r3
6449 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6453 for (i = 0; i < 4; i++)
6454 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6456 rd_val = displaced_read_reg (regs, dsc, rd);
6457 rn_val = displaced_read_reg (regs, dsc, rn);
6458 rm_val = displaced_read_reg (regs, dsc, rm);
6459 rs_val = displaced_read_reg (regs, dsc, rs);
6460 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6461 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6462 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6463 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6465 dsc->cleanup = &cleanup_alu_shifted_reg;
6469 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
6470 struct regcache *regs,
6471 struct displaced_step_closure *dsc)
6473 unsigned int op = bits (insn, 21, 24);
6474 int is_mov = (op == 0xd);
6475 unsigned int rd, rn, rm, rs;
6477 if (!insn_references_pc (insn, 0x000fff0ful))
6478 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6480 if (debug_displaced)
6481 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
6482 "%.8lx\n", is_mov ? "move" : "ALU",
6483 (unsigned long) insn);
6485 rn = bits (insn, 16, 19);
6486 rm = bits (insn, 0, 3);
6487 rs = bits (insn, 8, 11);
6488 rd = bits (insn, 12, 15);
6491 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6493 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6495 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6500 /* Clean up load instructions. */
6503 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
6504 struct displaced_step_closure *dsc)
6506 ULONGEST rt_val, rt_val2 = 0, rn_val;
6508 rt_val = displaced_read_reg (regs, dsc, 0);
6509 if (dsc->u.ldst.xfersize == 8)
6510 rt_val2 = displaced_read_reg (regs, dsc, 1);
6511 rn_val = displaced_read_reg (regs, dsc, 2);
6513 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6514 if (dsc->u.ldst.xfersize > 4)
6515 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6516 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6517 if (!dsc->u.ldst.immed)
6518 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6520 /* Handle register writeback. */
6521 if (dsc->u.ldst.writeback)
6522 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6523 /* Put result in right place. */
6524 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6525 if (dsc->u.ldst.xfersize == 8)
6526 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6529 /* Clean up store instructions. */
6532 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
6533 struct displaced_step_closure *dsc)
6535 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6537 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6538 if (dsc->u.ldst.xfersize > 4)
6539 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6540 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6541 if (!dsc->u.ldst.immed)
6542 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6543 if (!dsc->u.ldst.restore_r4)
6544 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6547 if (dsc->u.ldst.writeback)
6548 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6551 /* Copy "extra" load/store instructions. These are halfword/doubleword
6552 transfers, which have a different encoding to byte/word transfers. */
6555 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
6556 struct regcache *regs, struct displaced_step_closure *dsc)
6558 unsigned int op1 = bits (insn, 20, 24);
6559 unsigned int op2 = bits (insn, 5, 6);
6560 unsigned int rt = bits (insn, 12, 15);
6561 unsigned int rn = bits (insn, 16, 19);
6562 unsigned int rm = bits (insn, 0, 3);
6563 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6564 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6565 int immed = (op1 & 0x4) != 0;
6567 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6569 if (!insn_references_pc (insn, 0x000ff00ful))
6570 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6572 if (debug_displaced)
6573 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
6574 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
6575 (unsigned long) insn);
6577 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6580 internal_error (__FILE__, __LINE__,
6581 _("copy_extra_ld_st: instruction decode error"));
6583 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6584 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6585 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6587 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6589 rt_val = displaced_read_reg (regs, dsc, rt);
6590 if (bytesize[opcode] == 8)
6591 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6592 rn_val = displaced_read_reg (regs, dsc, rn);
6594 rm_val = displaced_read_reg (regs, dsc, rm);
6596 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6597 if (bytesize[opcode] == 8)
6598 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6599 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6601 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6604 dsc->u.ldst.xfersize = bytesize[opcode];
6605 dsc->u.ldst.rn = rn;
6606 dsc->u.ldst.immed = immed;
6607 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6608 dsc->u.ldst.restore_r4 = 0;
6611 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6613 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6614 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6616 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6618 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6619 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6621 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6626 /* Copy byte/half word/word loads and stores. */
6629 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
6630 struct displaced_step_closure *dsc, int load,
6631 int immed, int writeback, int size, int usermode,
6632 int rt, int rm, int rn)
6634 ULONGEST rt_val, rn_val, rm_val = 0;
6636 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6637 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6639 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6641 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6643 rt_val = displaced_read_reg (regs, dsc, rt);
6644 rn_val = displaced_read_reg (regs, dsc, rn);
6646 rm_val = displaced_read_reg (regs, dsc, rm);
6648 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6649 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6651 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6653 dsc->u.ldst.xfersize = size;
6654 dsc->u.ldst.rn = rn;
6655 dsc->u.ldst.immed = immed;
6656 dsc->u.ldst.writeback = writeback;
6658 /* To write PC we can do:
6660 Before this sequence of instructions:
6661 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6662 r2 is the Rn value got from dispalced_read_reg.
6664 Insn1: push {pc} Write address of STR instruction + offset on stack
6665 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6666 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6667 = addr(Insn1) + offset - addr(Insn3) - 8
6669 Insn4: add r4, r4, #8 r4 = offset - 8
6670 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6672 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6674 Otherwise we don't know what value to write for PC, since the offset is
6675 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6676 of this can be found in Section "Saving from r15" in
6677 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6679 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6684 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
6685 uint16_t insn2, struct regcache *regs,
6686 struct displaced_step_closure *dsc, int size)
6688 unsigned int u_bit = bit (insn1, 7);
6689 unsigned int rt = bits (insn2, 12, 15);
6690 int imm12 = bits (insn2, 0, 11);
6693 if (debug_displaced)
6694 fprintf_unfiltered (gdb_stdlog,
6695 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6696 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6702 /* Rewrite instruction LDR Rt imm12 into:
6704 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6708 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6711 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6712 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6713 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6715 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6717 pc_val = pc_val & 0xfffffffc;
6719 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6720 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6724 dsc->u.ldst.xfersize = size;
6725 dsc->u.ldst.immed = 0;
6726 dsc->u.ldst.writeback = 0;
6727 dsc->u.ldst.restore_r4 = 0;
6729 /* LDR R0, R2, R3 */
6730 dsc->modinsn[0] = 0xf852;
6731 dsc->modinsn[1] = 0x3;
6734 dsc->cleanup = &cleanup_load;
6740 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
6741 uint16_t insn2, struct regcache *regs,
6742 struct displaced_step_closure *dsc,
6743 int writeback, int immed)
6745 unsigned int rt = bits (insn2, 12, 15);
6746 unsigned int rn = bits (insn1, 0, 3);
6747 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
6748 /* In LDR (register), there is also a register Rm, which is not allowed to
6749 be PC, so we don't have to check it. */
6751 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
6752 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
6755 if (debug_displaced)
6756 fprintf_unfiltered (gdb_stdlog,
6757 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6758 rt, rn, insn1, insn2);
6760 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6763 dsc->u.ldst.restore_r4 = 0;
6766 /* ldr[b]<cond> rt, [rn, #imm], etc.
6768 ldr[b]<cond> r0, [r2, #imm]. */
6770 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6771 dsc->modinsn[1] = insn2 & 0x0fff;
6774 /* ldr[b]<cond> rt, [rn, rm], etc.
6776 ldr[b]<cond> r0, [r2, r3]. */
6778 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6779 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6789 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6790 struct regcache *regs,
6791 struct displaced_step_closure *dsc,
6792 int load, int size, int usermode)
6794 int immed = !bit (insn, 25);
6795 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6796 unsigned int rt = bits (insn, 12, 15);
6797 unsigned int rn = bits (insn, 16, 19);
6798 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6800 if (!insn_references_pc (insn, 0x000ff00ful))
6801 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6803 if (debug_displaced)
6804 fprintf_unfiltered (gdb_stdlog,
6805 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6806 load ? (size == 1 ? "ldrb" : "ldr")
6807 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
6809 (unsigned long) insn);
6811 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6812 usermode, rt, rm, rn);
6814 if (load || rt != ARM_PC_REGNUM)
6816 dsc->u.ldst.restore_r4 = 0;
6819 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6821 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6822 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6824 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6826 {ldr,str}[b]<cond> r0, [r2, r3]. */
6827 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6831 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6832 dsc->u.ldst.restore_r4 = 1;
6833 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6834 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6835 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6836 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6837 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6841 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6843 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6848 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6853 /* Cleanup LDM instructions with fully-populated register list. This is an
6854 unfortunate corner case: it's impossible to implement correctly by modifying
6855 the instruction. The issue is as follows: we have an instruction,
6859 which we must rewrite to avoid loading PC. A possible solution would be to
6860 do the load in two halves, something like (with suitable cleanup
6864 ldm[id][ab] r8!, {r0-r7}
6866 ldm[id][ab] r8, {r7-r14}
6869 but at present there's no suitable place for <temp>, since the scratch space
6870 is overwritten before the cleanup routine is called. For now, we simply
6871 emulate the instruction. */
6874 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6875 struct displaced_step_closure *dsc)
6877 int inc = dsc->u.block.increment;
6878 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6879 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6880 uint32_t regmask = dsc->u.block.regmask;
6881 int regno = inc ? 0 : 15;
6882 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6883 int exception_return = dsc->u.block.load && dsc->u.block.user
6884 && (regmask & 0x8000) != 0;
6885 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6886 int do_transfer = condition_true (dsc->u.block.cond, status);
6887 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6892 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6893 sensible we can do here. Complain loudly. */
6894 if (exception_return)
6895 error (_("Cannot single-step exception return"));
6897 /* We don't handle any stores here for now. */
6898 gdb_assert (dsc->u.block.load != 0);
6900 if (debug_displaced)
6901 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6902 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6903 dsc->u.block.increment ? "inc" : "dec",
6904 dsc->u.block.before ? "before" : "after");
6911 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6914 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6917 xfer_addr += bump_before;
6919 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6920 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6922 xfer_addr += bump_after;
6924 regmask &= ~(1 << regno);
6927 if (dsc->u.block.writeback)
6928 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6932 /* Clean up an STM which included the PC in the register list. */
6935 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6936 struct displaced_step_closure *dsc)
6938 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6939 int store_executed = condition_true (dsc->u.block.cond, status);
6940 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
6941 CORE_ADDR stm_insn_addr;
6944 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6946 /* If condition code fails, there's nothing else to do. */
6947 if (!store_executed)
6950 if (dsc->u.block.increment)
6952 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6954 if (dsc->u.block.before)
6959 pc_stored_at = dsc->u.block.xfer_addr;
6961 if (dsc->u.block.before)
6965 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
6966 stm_insn_addr = dsc->scratch_base;
6967 offset = pc_val - stm_insn_addr;
6969 if (debug_displaced)
6970 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
6971 "STM instruction\n", offset);
6973 /* Rewrite the stored PC to the proper value for the non-displaced original
6975 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
6976 dsc->insn_addr + offset);
6979 /* Clean up an LDM which includes the PC in the register list. We clumped all
6980 the registers in the transferred list into a contiguous range r0...rX (to
6981 avoid loading PC directly and losing control of the debugged program), so we
6982 must undo that here. */
6985 cleanup_block_load_pc (struct gdbarch *gdbarch,
6986 struct regcache *regs,
6987 struct displaced_step_closure *dsc)
6989 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6990 int load_executed = condition_true (dsc->u.block.cond, status);
6991 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6992 unsigned int regs_loaded = bitcount (mask);
6993 unsigned int num_to_shuffle = regs_loaded, clobbered;
6995 /* The method employed here will fail if the register list is fully populated
6996 (we need to avoid loading PC directly). */
6997 gdb_assert (num_to_shuffle < 16);
7002 clobbered = (1 << num_to_shuffle) - 1;
7004 while (num_to_shuffle > 0)
7006 if ((mask & (1 << write_reg)) != 0)
7008 unsigned int read_reg = num_to_shuffle - 1;
7010 if (read_reg != write_reg)
7012 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
7013 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7014 if (debug_displaced)
7015 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
7016 "loaded register r%d to r%d\n"), read_reg,
7019 else if (debug_displaced)
7020 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
7021 "r%d already in the right place\n"),
7024 clobbered &= ~(1 << write_reg);
7032 /* Restore any registers we scribbled over. */
7033 for (write_reg = 0; clobbered != 0; write_reg++)
7035 if ((clobbered & (1 << write_reg)) != 0)
7037 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7039 if (debug_displaced)
7040 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
7041 "clobbered register r%d\n"), write_reg);
7042 clobbered &= ~(1 << write_reg);
7046 /* Perform register writeback manually. */
7047 if (dsc->u.block.writeback)
7049 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7051 if (dsc->u.block.increment)
7052 new_rn_val += regs_loaded * 4;
7054 new_rn_val -= regs_loaded * 4;
7056 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7061 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7062 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7065 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
7066 struct regcache *regs,
7067 struct displaced_step_closure *dsc)
7069 int load = bit (insn, 20);
7070 int user = bit (insn, 22);
7071 int increment = bit (insn, 23);
7072 int before = bit (insn, 24);
7073 int writeback = bit (insn, 21);
7074 int rn = bits (insn, 16, 19);
7076 /* Block transfers which don't mention PC can be run directly
7078 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
7079 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7081 if (rn == ARM_PC_REGNUM)
7083 warning (_("displaced: Unpredictable LDM or STM with "
7084 "base register r15"));
7085 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7088 if (debug_displaced)
7089 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7090 "%.8lx\n", (unsigned long) insn);
7092 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7093 dsc->u.block.rn = rn;
7095 dsc->u.block.load = load;
7096 dsc->u.block.user = user;
7097 dsc->u.block.increment = increment;
7098 dsc->u.block.before = before;
7099 dsc->u.block.writeback = writeback;
7100 dsc->u.block.cond = bits (insn, 28, 31);
7102 dsc->u.block.regmask = insn & 0xffff;
7106 if ((insn & 0xffff) == 0xffff)
7108 /* LDM with a fully-populated register list. This case is
7109 particularly tricky. Implement for now by fully emulating the
7110 instruction (which might not behave perfectly in all cases, but
7111 these instructions should be rare enough for that not to matter
7113 dsc->modinsn[0] = ARM_NOP;
7115 dsc->cleanup = &cleanup_block_load_all;
7119 /* LDM of a list of registers which includes PC. Implement by
7120 rewriting the list of registers to be transferred into a
7121 contiguous chunk r0...rX before doing the transfer, then shuffling
7122 registers into the correct places in the cleanup routine. */
7123 unsigned int regmask = insn & 0xffff;
7124 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7125 unsigned int to = 0, from = 0, i, new_rn;
7127 for (i = 0; i < num_in_list; i++)
7128 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7130 /* Writeback makes things complicated. We need to avoid clobbering
7131 the base register with one of the registers in our modified
7132 register list, but just using a different register can't work in
7135 ldm r14!, {r0-r13,pc}
7137 which would need to be rewritten as:
7141 but that can't work, because there's no free register for N.
7143 Solve this by turning off the writeback bit, and emulating
7144 writeback manually in the cleanup routine. */
7149 new_regmask = (1 << num_in_list) - 1;
7151 if (debug_displaced)
7152 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7153 "{..., pc}: original reg list %.4x, modified "
7154 "list %.4x\n"), rn, writeback ? "!" : "",
7155 (int) insn & 0xffff, new_regmask);
7157 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7159 dsc->cleanup = &cleanup_block_load_pc;
7164 /* STM of a list of registers which includes PC. Run the instruction
7165 as-is, but out of line: this will store the wrong value for the PC,
7166 so we must manually fix up the memory in the cleanup routine.
7167 Doing things this way has the advantage that we can auto-detect
7168 the offset of the PC write (which is architecture-dependent) in
7169 the cleanup routine. */
7170 dsc->modinsn[0] = insn;
7172 dsc->cleanup = &cleanup_block_store_pc;
7179 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7180 struct regcache *regs,
7181 struct displaced_step_closure *dsc)
7183 int rn = bits (insn1, 0, 3);
7184 int load = bit (insn1, 4);
7185 int writeback = bit (insn1, 5);
7187 /* Block transfers which don't mention PC can be run directly
7189 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
7190 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7192 if (rn == ARM_PC_REGNUM)
7194 warning (_("displaced: Unpredictable LDM or STM with "
7195 "base register r15"));
7196 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7197 "unpredictable ldm/stm", dsc);
7200 if (debug_displaced)
7201 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
7202 "%.4x%.4x\n", insn1, insn2);
7204 /* Clear bit 13, since it should be always zero. */
7205 dsc->u.block.regmask = (insn2 & 0xdfff);
7206 dsc->u.block.rn = rn;
7208 dsc->u.block.load = load;
7209 dsc->u.block.user = 0;
7210 dsc->u.block.increment = bit (insn1, 7);
7211 dsc->u.block.before = bit (insn1, 8);
7212 dsc->u.block.writeback = writeback;
7213 dsc->u.block.cond = INST_AL;
7214 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7218 if (dsc->u.block.regmask == 0xffff)
7220 /* This branch is impossible to happen. */
7225 unsigned int regmask = dsc->u.block.regmask;
7226 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
7227 unsigned int to = 0, from = 0, i, new_rn;
7229 for (i = 0; i < num_in_list; i++)
7230 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7235 new_regmask = (1 << num_in_list) - 1;
7237 if (debug_displaced)
7238 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
7239 "{..., pc}: original reg list %.4x, modified "
7240 "list %.4x\n"), rn, writeback ? "!" : "",
7241 (int) dsc->u.block.regmask, new_regmask);
7243 dsc->modinsn[0] = insn1;
7244 dsc->modinsn[1] = (new_regmask & 0xffff);
7247 dsc->cleanup = &cleanup_block_load_pc;
7252 dsc->modinsn[0] = insn1;
7253 dsc->modinsn[1] = insn2;
7255 dsc->cleanup = &cleanup_block_store_pc;
7260 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7261 for Linux, where some SVC instructions must be treated specially. */
7264 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
7265 struct displaced_step_closure *dsc)
7267 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7269 if (debug_displaced)
7270 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
7271 "%.8lx\n", (unsigned long) resume_addr);
7273 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7277 /* Common copy routine for svc instruciton. */
7280 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
7281 struct displaced_step_closure *dsc)
7283 /* Preparation: none.
7284 Insn: unmodified svc.
7285 Cleanup: pc <- insn_addr + insn_size. */
7287 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7289 dsc->wrote_to_pc = 1;
7291 /* Allow OS-specific code to override SVC handling. */
7292 if (dsc->u.svc.copy_svc_os)
7293 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7296 dsc->cleanup = &cleanup_svc;
7302 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
7303 struct regcache *regs, struct displaced_step_closure *dsc)
7306 if (debug_displaced)
7307 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
7308 (unsigned long) insn);
7310 dsc->modinsn[0] = insn;
7312 return install_svc (gdbarch, regs, dsc);
7316 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
7317 struct regcache *regs, struct displaced_step_closure *dsc)
7320 if (debug_displaced)
7321 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
7324 dsc->modinsn[0] = insn;
7326 return install_svc (gdbarch, regs, dsc);
7329 /* Copy undefined instructions. */
7332 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
7333 struct displaced_step_closure *dsc)
7335 if (debug_displaced)
7336 fprintf_unfiltered (gdb_stdlog,
7337 "displaced: copying undefined insn %.8lx\n",
7338 (unsigned long) insn);
7340 dsc->modinsn[0] = insn;
7346 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
7347 struct displaced_step_closure *dsc)
7350 if (debug_displaced)
7351 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
7352 "%.4x %.4x\n", (unsigned short) insn1,
7353 (unsigned short) insn2);
7355 dsc->modinsn[0] = insn1;
7356 dsc->modinsn[1] = insn2;
7362 /* Copy unpredictable instructions. */
7365 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
7366 struct displaced_step_closure *dsc)
7368 if (debug_displaced)
7369 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
7370 "%.8lx\n", (unsigned long) insn);
7372 dsc->modinsn[0] = insn;
7377 /* The decode_* functions are instruction decoding helpers. They mostly follow
7378 the presentation in the ARM ARM. */
7381 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
7382 struct regcache *regs,
7383 struct displaced_step_closure *dsc)
7385 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
7386 unsigned int rn = bits (insn, 16, 19);
7388 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7389 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7390 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7391 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7392 else if ((op1 & 0x60) == 0x20)
7393 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7394 else if ((op1 & 0x71) == 0x40)
7395 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
7397 else if ((op1 & 0x77) == 0x41)
7398 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7399 else if ((op1 & 0x77) == 0x45)
7400 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7401 else if ((op1 & 0x77) == 0x51)
7404 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7406 return arm_copy_unpred (gdbarch, insn, dsc);
7408 else if ((op1 & 0x77) == 0x55)
7409 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7410 else if (op1 == 0x57)
7413 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7414 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7415 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7416 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7417 default: return arm_copy_unpred (gdbarch, insn, dsc);
7419 else if ((op1 & 0x63) == 0x43)
7420 return arm_copy_unpred (gdbarch, insn, dsc);
7421 else if ((op2 & 0x1) == 0x0)
7422 switch (op1 & ~0x80)
7425 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7427 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7428 case 0x71: case 0x75:
7430 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7431 case 0x63: case 0x67: case 0x73: case 0x77:
7432 return arm_copy_unpred (gdbarch, insn, dsc);
7434 return arm_copy_undef (gdbarch, insn, dsc);
7437 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7441 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
7442 struct regcache *regs,
7443 struct displaced_step_closure *dsc)
7445 if (bit (insn, 27) == 0)
7446 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7447 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7448 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7451 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7454 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7456 case 0x4: case 0x5: case 0x6: case 0x7:
7457 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7460 switch ((insn & 0xe00000) >> 21)
7462 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7464 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7467 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7470 return arm_copy_undef (gdbarch, insn, dsc);
7475 int rn_f = (bits (insn, 16, 19) == 0xf);
7476 switch ((insn & 0xe00000) >> 21)
7479 /* ldc/ldc2 imm (undefined for rn == pc). */
7480 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7481 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7484 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7486 case 0x4: case 0x5: case 0x6: case 0x7:
7487 /* ldc/ldc2 lit (undefined for rn != pc). */
7488 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7489 : arm_copy_undef (gdbarch, insn, dsc);
7492 return arm_copy_undef (gdbarch, insn, dsc);
7497 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7500 if (bits (insn, 16, 19) == 0xf)
7502 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7504 return arm_copy_undef (gdbarch, insn, dsc);
7508 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7510 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7514 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7516 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7519 return arm_copy_undef (gdbarch, insn, dsc);
7523 /* Decode miscellaneous instructions in dp/misc encoding space. */
7526 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
7527 struct regcache *regs,
7528 struct displaced_step_closure *dsc)
7530 unsigned int op2 = bits (insn, 4, 6);
7531 unsigned int op = bits (insn, 21, 22);
7532 unsigned int op1 = bits (insn, 16, 19);
7537 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7540 if (op == 0x1) /* bx. */
7541 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7543 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7545 return arm_copy_undef (gdbarch, insn, dsc);
7549 /* Not really supported. */
7550 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7552 return arm_copy_undef (gdbarch, insn, dsc);
7556 return arm_copy_bx_blx_reg (gdbarch, insn,
7557 regs, dsc); /* blx register. */
7559 return arm_copy_undef (gdbarch, insn, dsc);
7562 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7566 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7568 /* Not really supported. */
7569 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7572 return arm_copy_undef (gdbarch, insn, dsc);
7577 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
7578 struct regcache *regs,
7579 struct displaced_step_closure *dsc)
7582 switch (bits (insn, 20, 24))
7585 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7588 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7590 case 0x12: case 0x16:
7591 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7594 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7598 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
7600 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7601 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7602 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7603 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7604 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7605 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7606 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7607 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
7608 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7609 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7610 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7611 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7612 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7613 /* 2nd arg means "unpriveleged". */
7614 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
7618 /* Should be unreachable. */
7623 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
7624 struct regcache *regs,
7625 struct displaced_step_closure *dsc)
7627 int a = bit (insn, 25), b = bit (insn, 4);
7628 uint32_t op1 = bits (insn, 20, 24);
7629 int rn_f = bits (insn, 16, 19) == 0xf;
7631 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7632 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7633 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7634 else if ((!a && (op1 & 0x17) == 0x02)
7635 || (a && (op1 & 0x17) == 0x02 && !b))
7636 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7637 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7638 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7639 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7640 else if ((!a && (op1 & 0x17) == 0x03)
7641 || (a && (op1 & 0x17) == 0x03 && !b))
7642 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7643 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7644 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7645 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7646 else if ((!a && (op1 & 0x17) == 0x06)
7647 || (a && (op1 & 0x17) == 0x06 && !b))
7648 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7649 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7650 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7651 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7652 else if ((!a && (op1 & 0x17) == 0x07)
7653 || (a && (op1 & 0x17) == 0x07 && !b))
7654 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7656 /* Should be unreachable. */
7661 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
7662 struct displaced_step_closure *dsc)
7664 switch (bits (insn, 20, 24))
7666 case 0x00: case 0x01: case 0x02: case 0x03:
7667 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7669 case 0x04: case 0x05: case 0x06: case 0x07:
7670 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7672 case 0x08: case 0x09: case 0x0a: case 0x0b:
7673 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7674 return arm_copy_unmodified (gdbarch, insn,
7675 "decode/pack/unpack/saturate/reverse", dsc);
7678 if (bits (insn, 5, 7) == 0) /* op2. */
7680 if (bits (insn, 12, 15) == 0xf)
7681 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7683 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7686 return arm_copy_undef (gdbarch, insn, dsc);
7688 case 0x1a: case 0x1b:
7689 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7690 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7692 return arm_copy_undef (gdbarch, insn, dsc);
7694 case 0x1c: case 0x1d:
7695 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
7697 if (bits (insn, 0, 3) == 0xf)
7698 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7700 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7703 return arm_copy_undef (gdbarch, insn, dsc);
7705 case 0x1e: case 0x1f:
7706 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
7707 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7709 return arm_copy_undef (gdbarch, insn, dsc);
7712 /* Should be unreachable. */
7717 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
7718 struct regcache *regs,
7719 struct displaced_step_closure *dsc)
7722 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7724 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7728 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
7729 struct regcache *regs,
7730 struct displaced_step_closure *dsc)
7732 unsigned int opcode = bits (insn, 20, 24);
7736 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7737 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7739 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7740 case 0x12: case 0x16:
7741 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7743 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7744 case 0x13: case 0x17:
7745 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7747 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7748 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7749 /* Note: no writeback for these instructions. Bit 25 will always be
7750 zero though (via caller), so the following works OK. */
7751 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7754 /* Should be unreachable. */
7758 /* Decode shifted register instructions. */
7761 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
7762 uint16_t insn2, struct regcache *regs,
7763 struct displaced_step_closure *dsc)
7765 /* PC is only allowed to be used in instruction MOV. */
7767 unsigned int op = bits (insn1, 5, 8);
7768 unsigned int rn = bits (insn1, 0, 3);
7770 if (op == 0x2 && rn == 0xf) /* MOV */
7771 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7773 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7774 "dp (shift reg)", dsc);
7778 /* Decode extension register load/store. Exactly the same as
7779 arm_decode_ext_reg_ld_st. */
7782 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
7783 uint16_t insn2, struct regcache *regs,
7784 struct displaced_step_closure *dsc)
7786 unsigned int opcode = bits (insn1, 4, 8);
7790 case 0x04: case 0x05:
7791 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7792 "vfp/neon vmov", dsc);
7794 case 0x08: case 0x0c: /* 01x00 */
7795 case 0x0a: case 0x0e: /* 01x10 */
7796 case 0x12: case 0x16: /* 10x10 */
7797 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7798 "vfp/neon vstm/vpush", dsc);
7800 case 0x09: case 0x0d: /* 01x01 */
7801 case 0x0b: case 0x0f: /* 01x11 */
7802 case 0x13: case 0x17: /* 10x11 */
7803 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7804 "vfp/neon vldm/vpop", dsc);
7806 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7807 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7809 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7810 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7813 /* Should be unreachable. */
7818 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
7819 struct regcache *regs, struct displaced_step_closure *dsc)
7821 unsigned int op1 = bits (insn, 20, 25);
7822 int op = bit (insn, 4);
7823 unsigned int coproc = bits (insn, 8, 11);
7824 unsigned int rn = bits (insn, 16, 19);
7826 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7827 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7828 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7829 && (coproc & 0xe) != 0xa)
7831 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7832 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7833 && (coproc & 0xe) != 0xa)
7834 /* ldc/ldc2 imm/lit. */
7835 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7836 else if ((op1 & 0x3e) == 0x00)
7837 return arm_copy_undef (gdbarch, insn, dsc);
7838 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7839 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7840 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7841 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7842 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7843 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7844 else if ((op1 & 0x30) == 0x20 && !op)
7846 if ((coproc & 0xe) == 0xa)
7847 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7849 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7851 else if ((op1 & 0x30) == 0x20 && op)
7852 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7853 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7854 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7855 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7856 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7857 else if ((op1 & 0x30) == 0x30)
7858 return arm_copy_svc (gdbarch, insn, regs, dsc);
7860 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7864 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
7865 uint16_t insn2, struct regcache *regs,
7866 struct displaced_step_closure *dsc)
7868 unsigned int coproc = bits (insn2, 8, 11);
7869 unsigned int op1 = bits (insn1, 4, 9);
7870 unsigned int bit_5_8 = bits (insn1, 5, 8);
7871 unsigned int bit_9 = bit (insn1, 9);
7872 unsigned int bit_4 = bit (insn1, 4);
7873 unsigned int rn = bits (insn1, 0, 3);
7878 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7879 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7881 else if (bit_5_8 == 0) /* UNDEFINED. */
7882 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7885 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7886 if ((coproc & 0xe) == 0xa)
7887 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
7889 else /* coproc is not 101x. */
7891 if (bit_4 == 0) /* STC/STC2. */
7892 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7894 else /* LDC/LDC2 {literal, immeidate}. */
7895 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
7901 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7907 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
7908 struct displaced_step_closure *dsc, int rd)
7914 Preparation: Rd <- PC
7920 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7921 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7925 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
7926 struct displaced_step_closure *dsc,
7927 int rd, unsigned int imm)
7930 /* Encoding T2: ADDS Rd, #imm */
7931 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7933 install_pc_relative (gdbarch, regs, dsc, rd);
7939 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
7940 struct regcache *regs,
7941 struct displaced_step_closure *dsc)
7943 unsigned int rd = bits (insn, 8, 10);
7944 unsigned int imm8 = bits (insn, 0, 7);
7946 if (debug_displaced)
7947 fprintf_unfiltered (gdb_stdlog,
7948 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7951 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7955 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7956 uint16_t insn2, struct regcache *regs,
7957 struct displaced_step_closure *dsc)
7959 unsigned int rd = bits (insn2, 8, 11);
7960 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7961 extract raw immediate encoding rather than computing immediate. When
7962 generating ADD or SUB instruction, we can simply perform OR operation to
7963 set immediate into ADD. */
7964 unsigned int imm_3_8 = insn2 & 0x70ff;
7965 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7967 if (debug_displaced)
7968 fprintf_unfiltered (gdb_stdlog,
7969 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7970 rd, imm_i, imm_3_8, insn1, insn2);
7972 if (bit (insn1, 7)) /* Encoding T2 */
7974 /* Encoding T3: SUB Rd, Rd, #imm */
7975 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7976 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7978 else /* Encoding T3 */
7980 /* Encoding T3: ADD Rd, Rd, #imm */
7981 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7982 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7986 install_pc_relative (gdbarch, regs, dsc, rd);
7992 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1,
7993 struct regcache *regs,
7994 struct displaced_step_closure *dsc)
7996 unsigned int rt = bits (insn1, 8, 10);
7998 int imm8 = (bits (insn1, 0, 7) << 2);
7999 CORE_ADDR from = dsc->insn_addr;
8005 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8007 Insn: LDR R0, [R2, R3];
8008 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8010 if (debug_displaced)
8011 fprintf_unfiltered (gdb_stdlog,
8012 "displaced: copying thumb ldr r%d [pc #%d]\n"
8015 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8016 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8017 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8018 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8019 /* The assembler calculates the required value of the offset from the
8020 Align(PC,4) value of this instruction to the label. */
8021 pc = pc & 0xfffffffc;
8023 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8024 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8027 dsc->u.ldst.xfersize = 4;
8029 dsc->u.ldst.immed = 0;
8030 dsc->u.ldst.writeback = 0;
8031 dsc->u.ldst.restore_r4 = 0;
8033 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8035 dsc->cleanup = &cleanup_load;
8040 /* Copy Thumb cbnz/cbz insruction. */
8043 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
8044 struct regcache *regs,
8045 struct displaced_step_closure *dsc)
8047 int non_zero = bit (insn1, 11);
8048 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
8049 CORE_ADDR from = dsc->insn_addr;
8050 int rn = bits (insn1, 0, 2);
8051 int rn_val = displaced_read_reg (regs, dsc, rn);
8053 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8054 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8055 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8056 condition is false, let it be, cleanup_branch will do nothing. */
8057 if (dsc->u.branch.cond)
8059 dsc->u.branch.cond = INST_AL;
8060 dsc->u.branch.dest = from + 4 + imm5;
8063 dsc->u.branch.dest = from + 2;
8065 dsc->u.branch.link = 0;
8066 dsc->u.branch.exchange = 0;
8068 if (debug_displaced)
8069 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
8070 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
8071 rn, rn_val, insn1, dsc->u.branch.dest);
8073 dsc->modinsn[0] = THUMB_NOP;
8075 dsc->cleanup = &cleanup_branch;
8079 /* Copy Table Branch Byte/Halfword */
8081 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
8082 uint16_t insn2, struct regcache *regs,
8083 struct displaced_step_closure *dsc)
8085 ULONGEST rn_val, rm_val;
8086 int is_tbh = bit (insn2, 4);
8087 CORE_ADDR halfwords = 0;
8088 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8090 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8091 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8097 target_read_memory (rn_val + 2 * rm_val, buf, 2);
8098 halfwords = extract_unsigned_integer (buf, 2, byte_order);
8104 target_read_memory (rn_val + rm_val, buf, 1);
8105 halfwords = extract_unsigned_integer (buf, 1, byte_order);
8108 if (debug_displaced)
8109 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
8110 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
8111 (unsigned int) rn_val, (unsigned int) rm_val,
8112 (unsigned int) halfwords);
8114 dsc->u.branch.cond = INST_AL;
8115 dsc->u.branch.link = 0;
8116 dsc->u.branch.exchange = 0;
8117 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8119 dsc->cleanup = &cleanup_branch;
8125 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
8126 struct displaced_step_closure *dsc)
8129 int val = displaced_read_reg (regs, dsc, 7);
8130 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8133 val = displaced_read_reg (regs, dsc, 8);
8134 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8137 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8142 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1,
8143 struct regcache *regs,
8144 struct displaced_step_closure *dsc)
8146 dsc->u.block.regmask = insn1 & 0x00ff;
8148 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8151 (1) register list is full, that is, r0-r7 are used.
8152 Prepare: tmp[0] <- r8
8154 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8155 MOV r8, r7; Move value of r7 to r8;
8156 POP {r7}; Store PC value into r7.
8158 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8160 (2) register list is not full, supposing there are N registers in
8161 register list (except PC, 0 <= N <= 7).
8162 Prepare: for each i, 0 - N, tmp[i] <- ri.
8164 POP {r0, r1, ...., rN};
8166 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8167 from tmp[] properly.
8169 if (debug_displaced)
8170 fprintf_unfiltered (gdb_stdlog,
8171 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8172 dsc->u.block.regmask, insn1);
8174 if (dsc->u.block.regmask == 0xff)
8176 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8178 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8179 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8180 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8183 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8187 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
8188 unsigned int new_regmask, bit = 1;
8189 unsigned int to = 0, from = 0, i, new_rn;
8191 for (i = 0; i < num_in_list + 1; i++)
8192 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8194 new_regmask = (1 << (num_in_list + 1)) - 1;
8196 if (debug_displaced)
8197 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
8198 "{..., pc}: original reg list %.4x,"
8199 " modified list %.4x\n"),
8200 (int) dsc->u.block.regmask, new_regmask);
8202 dsc->u.block.regmask |= 0x8000;
8203 dsc->u.block.writeback = 0;
8204 dsc->u.block.cond = INST_AL;
8206 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8208 dsc->cleanup = &cleanup_block_load_pc;
8215 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8216 struct regcache *regs,
8217 struct displaced_step_closure *dsc)
8219 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
8220 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
8223 /* 16-bit thumb instructions. */
8224 switch (op_bit_12_15)
8226 /* Shift (imme), add, subtract, move and compare. */
8227 case 0: case 1: case 2: case 3:
8228 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8229 "shift/add/sub/mov/cmp",
8233 switch (op_bit_10_11)
8235 case 0: /* Data-processing */
8236 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
8240 case 1: /* Special data instructions and branch and exchange. */
8242 unsigned short op = bits (insn1, 7, 9);
8243 if (op == 6 || op == 7) /* BX or BLX */
8244 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8245 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8246 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8248 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
8252 default: /* LDR (literal) */
8253 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8256 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8257 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8260 if (op_bit_10_11 < 2) /* Generate PC-relative address */
8261 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8262 else /* Generate SP-relative address */
8263 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8265 case 11: /* Misc 16-bit instructions */
8267 switch (bits (insn1, 8, 11))
8269 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8270 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8272 case 12: case 13: /* POP */
8273 if (bit (insn1, 8)) /* PC is in register list. */
8274 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8276 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8278 case 15: /* If-Then, and hints */
8279 if (bits (insn1, 0, 3))
8280 /* If-Then makes up to four following instructions conditional.
8281 IT instruction itself is not conditional, so handle it as a
8282 common unmodified instruction. */
8283 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
8286 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8289 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8294 if (op_bit_10_11 < 2) /* Store multiple registers */
8295 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8296 else /* Load multiple registers */
8297 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8299 case 13: /* Conditional branch and supervisor call */
8300 if (bits (insn1, 9, 11) != 7) /* conditional branch */
8301 err = thumb_copy_b (gdbarch, insn1, dsc);
8303 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8305 case 14: /* Unconditional branch */
8306 err = thumb_copy_b (gdbarch, insn1, dsc);
8313 internal_error (__FILE__, __LINE__,
8314 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8318 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
8319 uint16_t insn1, uint16_t insn2,
8320 struct regcache *regs,
8321 struct displaced_step_closure *dsc)
8323 int rt = bits (insn2, 12, 15);
8324 int rn = bits (insn1, 0, 3);
8325 int op1 = bits (insn1, 7, 8);
8328 switch (bits (insn1, 5, 6))
8330 case 0: /* Load byte and memory hints */
8331 if (rt == 0xf) /* PLD/PLI */
8334 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8335 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8337 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8342 if (rn == 0xf) /* LDRB/LDRSB (literal) */
8343 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8346 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8347 "ldrb{reg, immediate}/ldrbt",
8352 case 1: /* Load halfword and memory hints. */
8353 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
8354 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8355 "pld/unalloc memhint", dsc);
8359 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8362 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8366 case 2: /* Load word */
8368 int insn2_bit_8_11 = bits (insn2, 8, 11);
8371 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8372 else if (op1 == 0x1) /* Encoding T3 */
8373 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8375 else /* op1 == 0x0 */
8377 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8378 /* LDR (immediate) */
8379 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8380 dsc, bit (insn2, 8), 1);
8381 else if (insn2_bit_8_11 == 0xe) /* LDRT */
8382 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8385 /* LDR (register) */
8386 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
8392 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8399 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
8400 uint16_t insn2, struct regcache *regs,
8401 struct displaced_step_closure *dsc)
8404 unsigned short op = bit (insn2, 15);
8405 unsigned int op1 = bits (insn1, 11, 12);
8411 switch (bits (insn1, 9, 10))
8416 /* Load/store {dual, execlusive}, table branch. */
8417 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
8418 && bits (insn2, 5, 7) == 0)
8419 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
8422 /* PC is not allowed to use in load/store {dual, exclusive}
8424 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8425 "load/store dual/ex", dsc);
8427 else /* load/store multiple */
8429 switch (bits (insn1, 7, 8))
8431 case 0: case 3: /* SRS, RFE */
8432 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8435 case 1: case 2: /* LDM/STM/PUSH/POP */
8436 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8443 /* Data-processing (shift register). */
8444 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
8447 default: /* Coprocessor instructions. */
8448 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8453 case 2: /* op1 = 2 */
8454 if (op) /* Branch and misc control. */
8456 if (bit (insn2, 14) /* BLX/BL */
8457 || bit (insn2, 12) /* Unconditional branch */
8458 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
8459 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8461 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8466 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
8468 int op = bits (insn1, 4, 8);
8469 int rn = bits (insn1, 0, 3);
8470 if ((op == 0 || op == 0xa) && rn == 0xf)
8471 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
8474 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8477 else /* Data processing (modified immeidate) */
8478 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8482 case 3: /* op1 = 3 */
8483 switch (bits (insn1, 9, 10))
8487 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
8489 else /* NEON Load/Store and Store single data item */
8490 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8491 "neon elt/struct load/store",
8494 case 1: /* op1 = 3, bits (9, 10) == 1 */
8495 switch (bits (insn1, 7, 8))
8497 case 0: case 1: /* Data processing (register) */
8498 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8501 case 2: /* Multiply and absolute difference */
8502 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8503 "mul/mua/diff", dsc);
8505 case 3: /* Long multiply and divide */
8506 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
8511 default: /* Coprocessor instructions */
8512 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8521 internal_error (__FILE__, __LINE__,
8522 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8527 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8528 CORE_ADDR to, struct regcache *regs,
8529 struct displaced_step_closure *dsc)
8531 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8533 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
8535 if (debug_displaced)
8536 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
8537 "at %.8lx\n", insn1, (unsigned long) from);
8540 dsc->insn_size = thumb_insn_size (insn1);
8541 if (thumb_insn_size (insn1) == 4)
8544 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
8545 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8548 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8552 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
8553 CORE_ADDR to, struct regcache *regs,
8554 struct displaced_step_closure *dsc)
8557 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8560 /* Most displaced instructions use a 1-instruction scratch space, so set this
8561 here and override below if/when necessary. */
8563 dsc->insn_addr = from;
8564 dsc->scratch_base = to;
8565 dsc->cleanup = NULL;
8566 dsc->wrote_to_pc = 0;
8568 if (!displaced_in_arm_mode (regs))
8569 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
8573 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
8574 if (debug_displaced)
8575 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
8576 "at %.8lx\n", (unsigned long) insn,
8577 (unsigned long) from);
8579 if ((insn & 0xf0000000) == 0xf0000000)
8580 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8581 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8583 case 0x0: case 0x1: case 0x2: case 0x3:
8584 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8587 case 0x4: case 0x5: case 0x6:
8588 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8592 err = arm_decode_media (gdbarch, insn, dsc);
8595 case 0x8: case 0x9: case 0xa: case 0xb:
8596 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8599 case 0xc: case 0xd: case 0xe: case 0xf:
8600 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
8605 internal_error (__FILE__, __LINE__,
8606 _("arm_process_displaced_insn: Instruction decode error"));
8609 /* Actually set up the scratch space for a displaced instruction. */
8612 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
8613 CORE_ADDR to, struct displaced_step_closure *dsc)
8615 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8616 unsigned int i, len, offset;
8617 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8618 int size = dsc->is_thumb? 2 : 4;
8619 const gdb_byte *bkp_insn;
8622 /* Poke modified instruction(s). */
8623 for (i = 0; i < dsc->numinsns; i++)
8625 if (debug_displaced)
8627 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
8629 fprintf_unfiltered (gdb_stdlog, "%.8lx",
8632 fprintf_unfiltered (gdb_stdlog, "%.4x",
8633 (unsigned short)dsc->modinsn[i]);
8635 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
8636 (unsigned long) to + offset);
8639 write_memory_unsigned_integer (to + offset, size,
8640 byte_order_for_code,
8645 /* Choose the correct breakpoint instruction. */
8648 bkp_insn = tdep->thumb_breakpoint;
8649 len = tdep->thumb_breakpoint_size;
8653 bkp_insn = tdep->arm_breakpoint;
8654 len = tdep->arm_breakpoint_size;
8657 /* Put breakpoint afterwards. */
8658 write_memory (to + offset, bkp_insn, len);
8660 if (debug_displaced)
8661 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
8662 paddress (gdbarch, from), paddress (gdbarch, to));
8665 /* Entry point for copying an instruction into scratch space for displaced
8668 struct displaced_step_closure *
8669 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
8670 CORE_ADDR from, CORE_ADDR to,
8671 struct regcache *regs)
8673 struct displaced_step_closure *dsc
8674 = xmalloc (sizeof (struct displaced_step_closure));
8675 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
8676 arm_displaced_init_closure (gdbarch, from, to, dsc);
8681 /* Entry point for cleaning things up after a displaced instruction has been
8685 arm_displaced_step_fixup (struct gdbarch *gdbarch,
8686 struct displaced_step_closure *dsc,
8687 CORE_ADDR from, CORE_ADDR to,
8688 struct regcache *regs)
8691 dsc->cleanup (gdbarch, regs, dsc);
8693 if (!dsc->wrote_to_pc)
8694 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
8695 dsc->insn_addr + dsc->insn_size);
8699 #include "bfd-in2.h"
8700 #include "libcoff.h"
8703 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
8705 struct gdbarch *gdbarch = info->application_data;
8707 if (arm_pc_is_thumb (gdbarch, memaddr))
8709 static asymbol *asym;
8710 static combined_entry_type ce;
8711 static struct coff_symbol_struct csym;
8712 static struct bfd fake_bfd;
8713 static bfd_target fake_target;
8715 if (csym.native == NULL)
8717 /* Create a fake symbol vector containing a Thumb symbol.
8718 This is solely so that the code in print_insn_little_arm()
8719 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8720 the presence of a Thumb symbol and switch to decoding
8721 Thumb instructions. */
8723 fake_target.flavour = bfd_target_coff_flavour;
8724 fake_bfd.xvec = &fake_target;
8725 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8727 csym.symbol.the_bfd = &fake_bfd;
8728 csym.symbol.name = "fake";
8729 asym = (asymbol *) & csym;
8732 memaddr = UNMAKE_THUMB_ADDR (memaddr);
8733 info->symbols = &asym;
8736 info->symbols = NULL;
8738 if (info->endian == BFD_ENDIAN_BIG)
8739 return print_insn_big_arm (memaddr, info);
8741 return print_insn_little_arm (memaddr, info);
8744 /* The following define instruction sequences that will cause ARM
8745 cpu's to take an undefined instruction trap. These are used to
8746 signal a breakpoint to GDB.
8748 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8749 modes. A different instruction is required for each mode. The ARM
8750 cpu's can also be big or little endian. Thus four different
8751 instructions are needed to support all cases.
8753 Note: ARMv4 defines several new instructions that will take the
8754 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8755 not in fact add the new instructions. The new undefined
8756 instructions in ARMv4 are all instructions that had no defined
8757 behaviour in earlier chips. There is no guarantee that they will
8758 raise an exception, but may be treated as NOP's. In practice, it
8759 may only safe to rely on instructions matching:
8761 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8762 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8763 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8765 Even this may only true if the condition predicate is true. The
8766 following use a condition predicate of ALWAYS so it is always TRUE.
8768 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8769 and NetBSD all use a software interrupt rather than an undefined
8770 instruction to force a trap. This can be handled by by the
8771 abi-specific code during establishment of the gdbarch vector. */
8773 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8774 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8775 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8776 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8778 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
8779 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
8780 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
8781 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
8783 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8784 the program counter value to determine whether a 16-bit or 32-bit
8785 breakpoint should be used. It returns a pointer to a string of
8786 bytes that encode a breakpoint instruction, stores the length of
8787 the string to *lenptr, and adjusts the program counter (if
8788 necessary) to point to the actual memory location where the
8789 breakpoint should be inserted. */
8791 static const unsigned char *
8792 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
8794 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8795 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
8797 if (arm_pc_is_thumb (gdbarch, *pcptr))
8799 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
8801 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8802 check whether we are replacing a 32-bit instruction. */
8803 if (tdep->thumb2_breakpoint != NULL)
8806 if (target_read_memory (*pcptr, buf, 2) == 0)
8808 unsigned short inst1;
8809 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
8810 if (thumb_insn_size (inst1) == 4)
8812 *lenptr = tdep->thumb2_breakpoint_size;
8813 return tdep->thumb2_breakpoint;
8818 *lenptr = tdep->thumb_breakpoint_size;
8819 return tdep->thumb_breakpoint;
8823 *lenptr = tdep->arm_breakpoint_size;
8824 return tdep->arm_breakpoint;
8829 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
8832 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
8834 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
8835 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8836 that this is not confused with a 32-bit ARM breakpoint. */
8840 /* Extract from an array REGBUF containing the (raw) register state a
8841 function return value of type TYPE, and copy that, in virtual
8842 format, into VALBUF. */
8845 arm_extract_return_value (struct type *type, struct regcache *regs,
8848 struct gdbarch *gdbarch = get_regcache_arch (regs);
8849 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8851 if (TYPE_CODE_FLT == TYPE_CODE (type))
8853 switch (gdbarch_tdep (gdbarch)->fp_model)
8857 /* The value is in register F0 in internal format. We need to
8858 extract the raw value and then convert it to the desired
8860 bfd_byte tmpbuf[FP_REGISTER_SIZE];
8862 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
8863 convert_from_extended (floatformat_from_type (type), tmpbuf,
8864 valbuf, gdbarch_byte_order (gdbarch));
8868 case ARM_FLOAT_SOFT_FPA:
8869 case ARM_FLOAT_SOFT_VFP:
8870 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8871 not using the VFP ABI code. */
8873 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
8874 if (TYPE_LENGTH (type) > 4)
8875 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
8876 valbuf + INT_REGISTER_SIZE);
8880 internal_error (__FILE__, __LINE__,
8881 _("arm_extract_return_value: "
8882 "Floating point model not supported"));
8886 else if (TYPE_CODE (type) == TYPE_CODE_INT
8887 || TYPE_CODE (type) == TYPE_CODE_CHAR
8888 || TYPE_CODE (type) == TYPE_CODE_BOOL
8889 || TYPE_CODE (type) == TYPE_CODE_PTR
8890 || TYPE_CODE (type) == TYPE_CODE_REF
8891 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8893 /* If the type is a plain integer, then the access is
8894 straight-forward. Otherwise we have to play around a bit
8896 int len = TYPE_LENGTH (type);
8897 int regno = ARM_A1_REGNUM;
8902 /* By using store_unsigned_integer we avoid having to do
8903 anything special for small big-endian values. */
8904 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8905 store_unsigned_integer (valbuf,
8906 (len > INT_REGISTER_SIZE
8907 ? INT_REGISTER_SIZE : len),
8909 len -= INT_REGISTER_SIZE;
8910 valbuf += INT_REGISTER_SIZE;
8915 /* For a structure or union the behaviour is as if the value had
8916 been stored to word-aligned memory and then loaded into
8917 registers with 32-bit load instruction(s). */
8918 int len = TYPE_LENGTH (type);
8919 int regno = ARM_A1_REGNUM;
8920 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8924 regcache_cooked_read (regs, regno++, tmpbuf);
8925 memcpy (valbuf, tmpbuf,
8926 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8927 len -= INT_REGISTER_SIZE;
8928 valbuf += INT_REGISTER_SIZE;
8934 /* Will a function return an aggregate type in memory or in a
8935 register? Return 0 if an aggregate type can be returned in a
8936 register, 1 if it must be returned in memory. */
8939 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8942 enum type_code code;
8944 CHECK_TYPEDEF (type);
8946 /* In the ARM ABI, "integer" like aggregate types are returned in
8947 registers. For an aggregate type to be integer like, its size
8948 must be less than or equal to INT_REGISTER_SIZE and the
8949 offset of each addressable subfield must be zero. Note that bit
8950 fields are not addressable, and all addressable subfields of
8951 unions always start at offset zero.
8953 This function is based on the behaviour of GCC 2.95.1.
8954 See: gcc/arm.c: arm_return_in_memory() for details.
8956 Note: All versions of GCC before GCC 2.95.2 do not set up the
8957 parameters correctly for a function returning the following
8958 structure: struct { float f;}; This should be returned in memory,
8959 not a register. Richard Earnshaw sent me a patch, but I do not
8960 know of any way to detect if a function like the above has been
8961 compiled with the correct calling convention. */
8963 /* All aggregate types that won't fit in a register must be returned
8965 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8970 /* The AAPCS says all aggregates not larger than a word are returned
8972 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8975 /* The only aggregate types that can be returned in a register are
8976 structs and unions. Arrays must be returned in memory. */
8977 code = TYPE_CODE (type);
8978 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
8983 /* Assume all other aggregate types can be returned in a register.
8984 Run a check for structures, unions and arrays. */
8987 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8990 /* Need to check if this struct/union is "integer" like. For
8991 this to be true, its size must be less than or equal to
8992 INT_REGISTER_SIZE and the offset of each addressable
8993 subfield must be zero. Note that bit fields are not
8994 addressable, and unions always start at offset zero. If any
8995 of the subfields is a floating point type, the struct/union
8996 cannot be an integer type. */
8998 /* For each field in the object, check:
8999 1) Is it FP? --> yes, nRc = 1;
9000 2) Is it addressable (bitpos != 0) and
9001 not packed (bitsize == 0)?
9005 for (i = 0; i < TYPE_NFIELDS (type); i++)
9007 enum type_code field_type_code;
9008 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
9011 /* Is it a floating point type field? */
9012 if (field_type_code == TYPE_CODE_FLT)
9018 /* If bitpos != 0, then we have to care about it. */
9019 if (TYPE_FIELD_BITPOS (type, i) != 0)
9021 /* Bitfields are not addressable. If the field bitsize is
9022 zero, then the field is not packed. Hence it cannot be
9023 a bitfield or any other packed type. */
9024 if (TYPE_FIELD_BITSIZE (type, i) == 0)
9036 /* Write into appropriate registers a function return value of type
9037 TYPE, given in virtual format. */
9040 arm_store_return_value (struct type *type, struct regcache *regs,
9041 const gdb_byte *valbuf)
9043 struct gdbarch *gdbarch = get_regcache_arch (regs);
9044 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9046 if (TYPE_CODE (type) == TYPE_CODE_FLT)
9048 gdb_byte buf[MAX_REGISTER_SIZE];
9050 switch (gdbarch_tdep (gdbarch)->fp_model)
9054 convert_to_extended (floatformat_from_type (type), buf, valbuf,
9055 gdbarch_byte_order (gdbarch));
9056 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
9059 case ARM_FLOAT_SOFT_FPA:
9060 case ARM_FLOAT_SOFT_VFP:
9061 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9062 not using the VFP ABI code. */
9064 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
9065 if (TYPE_LENGTH (type) > 4)
9066 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
9067 valbuf + INT_REGISTER_SIZE);
9071 internal_error (__FILE__, __LINE__,
9072 _("arm_store_return_value: Floating "
9073 "point model not supported"));
9077 else if (TYPE_CODE (type) == TYPE_CODE_INT
9078 || TYPE_CODE (type) == TYPE_CODE_CHAR
9079 || TYPE_CODE (type) == TYPE_CODE_BOOL
9080 || TYPE_CODE (type) == TYPE_CODE_PTR
9081 || TYPE_CODE (type) == TYPE_CODE_REF
9082 || TYPE_CODE (type) == TYPE_CODE_ENUM)
9084 if (TYPE_LENGTH (type) <= 4)
9086 /* Values of one word or less are zero/sign-extended and
9088 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9089 LONGEST val = unpack_long (type, valbuf);
9091 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
9092 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
9096 /* Integral values greater than one word are stored in consecutive
9097 registers starting with r0. This will always be a multiple of
9098 the regiser size. */
9099 int len = TYPE_LENGTH (type);
9100 int regno = ARM_A1_REGNUM;
9104 regcache_cooked_write (regs, regno++, valbuf);
9105 len -= INT_REGISTER_SIZE;
9106 valbuf += INT_REGISTER_SIZE;
9112 /* For a structure or union the behaviour is as if the value had
9113 been stored to word-aligned memory and then loaded into
9114 registers with 32-bit load instruction(s). */
9115 int len = TYPE_LENGTH (type);
9116 int regno = ARM_A1_REGNUM;
9117 bfd_byte tmpbuf[INT_REGISTER_SIZE];
9121 memcpy (tmpbuf, valbuf,
9122 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
9123 regcache_cooked_write (regs, regno++, tmpbuf);
9124 len -= INT_REGISTER_SIZE;
9125 valbuf += INT_REGISTER_SIZE;
9131 /* Handle function return values. */
9133 static enum return_value_convention
9134 arm_return_value (struct gdbarch *gdbarch, struct value *function,
9135 struct type *valtype, struct regcache *regcache,
9136 gdb_byte *readbuf, const gdb_byte *writebuf)
9138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9139 struct type *func_type = function ? value_type (function) : NULL;
9140 enum arm_vfp_cprc_base_type vfp_base_type;
9143 if (arm_vfp_abi_for_function (gdbarch, func_type)
9144 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
9146 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
9147 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
9149 for (i = 0; i < vfp_base_count; i++)
9151 if (reg_char == 'q')
9154 arm_neon_quad_write (gdbarch, regcache, i,
9155 writebuf + i * unit_length);
9158 arm_neon_quad_read (gdbarch, regcache, i,
9159 readbuf + i * unit_length);
9166 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
9167 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9170 regcache_cooked_write (regcache, regnum,
9171 writebuf + i * unit_length);
9173 regcache_cooked_read (regcache, regnum,
9174 readbuf + i * unit_length);
9177 return RETURN_VALUE_REGISTER_CONVENTION;
9180 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
9181 || TYPE_CODE (valtype) == TYPE_CODE_UNION
9182 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
9184 if (tdep->struct_return == pcc_struct_return
9185 || arm_return_in_memory (gdbarch, valtype))
9186 return RETURN_VALUE_STRUCT_CONVENTION;
9189 /* AAPCS returns complex types longer than a register in memory. */
9190 if (tdep->arm_abi != ARM_ABI_APCS
9191 && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
9192 && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE)
9193 return RETURN_VALUE_STRUCT_CONVENTION;
9196 arm_store_return_value (valtype, regcache, writebuf);
9199 arm_extract_return_value (valtype, regcache, readbuf);
9201 return RETURN_VALUE_REGISTER_CONVENTION;
9206 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9208 struct gdbarch *gdbarch = get_frame_arch (frame);
9209 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9210 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9212 gdb_byte buf[INT_REGISTER_SIZE];
9214 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9216 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
9220 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
9224 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9225 return the target PC. Otherwise return 0. */
9228 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
9232 CORE_ADDR start_addr;
9234 /* Find the starting address and name of the function containing the PC. */
9235 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
9238 /* If PC is in a Thumb call or return stub, return the address of the
9239 target PC, which is in a register. The thunk functions are called
9240 _call_via_xx, where x is the register name. The possible names
9241 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9242 functions, named __ARM_call_via_r[0-7]. */
9243 if (strncmp (name, "_call_via_", 10) == 0
9244 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9246 /* Use the name suffix to determine which register contains the
9248 static char *table[15] =
9249 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9250 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9253 int offset = strlen (name) - 2;
9255 for (regno = 0; regno <= 14; regno++)
9256 if (strcmp (&name[offset], table[regno]) == 0)
9257 return get_frame_register_unsigned (frame, regno);
9260 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9261 non-interworking calls to foo. We could decode the stubs
9262 to find the target but it's easier to use the symbol table. */
9263 namelen = strlen (name);
9264 if (name[0] == '_' && name[1] == '_'
9265 && ((namelen > 2 + strlen ("_from_thumb")
9266 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
9267 strlen ("_from_thumb")) == 0)
9268 || (namelen > 2 + strlen ("_from_arm")
9269 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
9270 strlen ("_from_arm")) == 0)))
9273 int target_len = namelen - 2;
9274 struct minimal_symbol *minsym;
9275 struct objfile *objfile;
9276 struct obj_section *sec;
9278 if (name[namelen - 1] == 'b')
9279 target_len -= strlen ("_from_thumb");
9281 target_len -= strlen ("_from_arm");
9283 target_name = alloca (target_len + 1);
9284 memcpy (target_name, name + 2, target_len);
9285 target_name[target_len] = '\0';
9287 sec = find_pc_section (pc);
9288 objfile = (sec == NULL) ? NULL : sec->objfile;
9289 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
9291 return SYMBOL_VALUE_ADDRESS (minsym);
9296 return 0; /* not a stub */
9300 set_arm_command (char *args, int from_tty)
9302 printf_unfiltered (_("\
9303 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9304 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
9308 show_arm_command (char *args, int from_tty)
9310 cmd_show_list (showarmcmdlist, from_tty, "");
9314 arm_update_current_architecture (void)
9316 struct gdbarch_info info;
9318 /* If the current architecture is not ARM, we have nothing to do. */
9319 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
9322 /* Update the architecture. */
9323 gdbarch_info_init (&info);
9325 if (!gdbarch_update_p (info))
9326 internal_error (__FILE__, __LINE__, _("could not update architecture"));
9330 set_fp_model_sfunc (char *args, int from_tty,
9331 struct cmd_list_element *c)
9333 enum arm_float_model fp_model;
9335 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
9336 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
9338 arm_fp_model = fp_model;
9342 if (fp_model == ARM_FLOAT_LAST)
9343 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
9346 arm_update_current_architecture ();
9350 show_fp_model (struct ui_file *file, int from_tty,
9351 struct cmd_list_element *c, const char *value)
9353 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9355 if (arm_fp_model == ARM_FLOAT_AUTO
9356 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9357 fprintf_filtered (file, _("\
9358 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9359 fp_model_strings[tdep->fp_model]);
9361 fprintf_filtered (file, _("\
9362 The current ARM floating point model is \"%s\".\n"),
9363 fp_model_strings[arm_fp_model]);
9367 arm_set_abi (char *args, int from_tty,
9368 struct cmd_list_element *c)
9370 enum arm_abi_kind arm_abi;
9372 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
9373 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
9375 arm_abi_global = arm_abi;
9379 if (arm_abi == ARM_ABI_LAST)
9380 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
9383 arm_update_current_architecture ();
9387 arm_show_abi (struct ui_file *file, int from_tty,
9388 struct cmd_list_element *c, const char *value)
9390 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9392 if (arm_abi_global == ARM_ABI_AUTO
9393 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
9394 fprintf_filtered (file, _("\
9395 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9396 arm_abi_strings[tdep->arm_abi]);
9398 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
9403 arm_show_fallback_mode (struct ui_file *file, int from_tty,
9404 struct cmd_list_element *c, const char *value)
9406 fprintf_filtered (file,
9407 _("The current execution mode assumed "
9408 "(when symbols are unavailable) is \"%s\".\n"),
9409 arm_fallback_mode_string);
9413 arm_show_force_mode (struct ui_file *file, int from_tty,
9414 struct cmd_list_element *c, const char *value)
9416 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
9418 fprintf_filtered (file,
9419 _("The current execution mode assumed "
9420 "(even when symbols are available) is \"%s\".\n"),
9421 arm_force_mode_string);
9424 /* If the user changes the register disassembly style used for info
9425 register and other commands, we have to also switch the style used
9426 in opcodes for disassembly output. This function is run in the "set
9427 arm disassembly" command, and does that. */
9430 set_disassembly_style_sfunc (char *args, int from_tty,
9431 struct cmd_list_element *c)
9433 set_disassembly_style ();
9436 /* Return the ARM register name corresponding to register I. */
9438 arm_register_name (struct gdbarch *gdbarch, int i)
9440 const int num_regs = gdbarch_num_regs (gdbarch);
9442 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
9443 && i >= num_regs && i < num_regs + 32)
9445 static const char *const vfp_pseudo_names[] = {
9446 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9447 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9448 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9449 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9452 return vfp_pseudo_names[i - num_regs];
9455 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
9456 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9458 static const char *const neon_pseudo_names[] = {
9459 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9460 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9463 return neon_pseudo_names[i - num_regs - 32];
9466 if (i >= ARRAY_SIZE (arm_register_names))
9467 /* These registers are only supported on targets which supply
9468 an XML description. */
9471 return arm_register_names[i];
9475 set_disassembly_style (void)
9479 /* Find the style that the user wants. */
9480 for (current = 0; current < num_disassembly_options; current++)
9481 if (disassembly_style == valid_disassembly_styles[current])
9483 gdb_assert (current < num_disassembly_options);
9485 /* Synchronize the disassembler. */
9486 set_arm_regname_option (current);
9489 /* Test whether the coff symbol specific value corresponds to a Thumb
9493 coff_sym_is_thumb (int val)
9495 return (val == C_THUMBEXT
9496 || val == C_THUMBSTAT
9497 || val == C_THUMBEXTFUNC
9498 || val == C_THUMBSTATFUNC
9499 || val == C_THUMBLABEL);
9502 /* arm_coff_make_msymbol_special()
9503 arm_elf_make_msymbol_special()
9505 These functions test whether the COFF or ELF symbol corresponds to
9506 an address in thumb code, and set a "special" bit in a minimal
9507 symbol to indicate that it does. */
9510 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
9512 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9513 == ST_BRANCH_TO_THUMB)
9514 MSYMBOL_SET_SPECIAL (msym);
9518 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
9520 if (coff_sym_is_thumb (val))
9521 MSYMBOL_SET_SPECIAL (msym);
9525 arm_objfile_data_free (struct objfile *objfile, void *arg)
9527 struct arm_per_objfile *data = arg;
9530 for (i = 0; i < objfile->obfd->section_count; i++)
9531 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
9535 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
9538 const char *name = bfd_asymbol_name (sym);
9539 struct arm_per_objfile *data;
9540 VEC(arm_mapping_symbol_s) **map_p;
9541 struct arm_mapping_symbol new_map_sym;
9543 gdb_assert (name[0] == '$');
9544 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
9547 data = objfile_data (objfile, arm_objfile_data_key);
9550 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
9551 struct arm_per_objfile);
9552 set_objfile_data (objfile, arm_objfile_data_key, data);
9553 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
9554 objfile->obfd->section_count,
9555 VEC(arm_mapping_symbol_s) *);
9557 map_p = &data->section_maps[bfd_get_section (sym)->index];
9559 new_map_sym.value = sym->value;
9560 new_map_sym.type = name[1];
9562 /* Assume that most mapping symbols appear in order of increasing
9563 value. If they were randomly distributed, it would be faster to
9564 always push here and then sort at first use. */
9565 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
9567 struct arm_mapping_symbol *prev_map_sym;
9569 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
9570 if (prev_map_sym->value >= sym->value)
9573 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
9574 arm_compare_mapping_symbols);
9575 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
9580 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
9584 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
9586 struct gdbarch *gdbarch = get_regcache_arch (regcache);
9587 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
9589 /* If necessary, set the T bit. */
9592 ULONGEST val, t_bit;
9593 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
9594 t_bit = arm_psr_thumb_bit (gdbarch);
9595 if (arm_pc_is_thumb (gdbarch, pc))
9596 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9599 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
9604 /* Read the contents of a NEON quad register, by reading from two
9605 double registers. This is used to implement the quad pseudo
9606 registers, and for argument passing in case the quad registers are
9607 missing; vectors are passed in quad registers when using the VFP
9608 ABI, even if a NEON unit is not present. REGNUM is the index of
9609 the quad register, in [0, 15]. */
9611 static enum register_status
9612 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
9613 int regnum, gdb_byte *buf)
9616 gdb_byte reg_buf[8];
9617 int offset, double_regnum;
9618 enum register_status status;
9620 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9621 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9624 /* d0 is always the least significant half of q0. */
9625 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9630 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9631 if (status != REG_VALID)
9633 memcpy (buf + offset, reg_buf, 8);
9635 offset = 8 - offset;
9636 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
9637 if (status != REG_VALID)
9639 memcpy (buf + offset, reg_buf, 8);
9644 static enum register_status
9645 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
9646 int regnum, gdb_byte *buf)
9648 const int num_regs = gdbarch_num_regs (gdbarch);
9650 gdb_byte reg_buf[8];
9651 int offset, double_regnum;
9653 gdb_assert (regnum >= num_regs);
9656 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9657 /* Quad-precision register. */
9658 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
9661 enum register_status status;
9663 /* Single-precision register. */
9664 gdb_assert (regnum < 32);
9666 /* s0 is always the least significant half of d0. */
9667 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9668 offset = (regnum & 1) ? 0 : 4;
9670 offset = (regnum & 1) ? 4 : 0;
9672 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9673 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9676 status = regcache_raw_read (regcache, double_regnum, reg_buf);
9677 if (status == REG_VALID)
9678 memcpy (buf, reg_buf + offset, 4);
9683 /* Store the contents of BUF to a NEON quad register, by writing to
9684 two double registers. This is used to implement the quad pseudo
9685 registers, and for argument passing in case the quad registers are
9686 missing; vectors are passed in quad registers when using the VFP
9687 ABI, even if a NEON unit is not present. REGNUM is the index
9688 of the quad register, in [0, 15]. */
9691 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
9692 int regnum, const gdb_byte *buf)
9695 int offset, double_regnum;
9697 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
9698 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9701 /* d0 is always the least significant half of q0. */
9702 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9707 regcache_raw_write (regcache, double_regnum, buf + offset);
9708 offset = 8 - offset;
9709 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
9713 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
9714 int regnum, const gdb_byte *buf)
9716 const int num_regs = gdbarch_num_regs (gdbarch);
9718 gdb_byte reg_buf[8];
9719 int offset, double_regnum;
9721 gdb_assert (regnum >= num_regs);
9724 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9725 /* Quad-precision register. */
9726 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
9729 /* Single-precision register. */
9730 gdb_assert (regnum < 32);
9732 /* s0 is always the least significant half of d0. */
9733 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
9734 offset = (regnum & 1) ? 0 : 4;
9736 offset = (regnum & 1) ? 4 : 0;
9738 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
9739 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
9742 regcache_raw_read (regcache, double_regnum, reg_buf);
9743 memcpy (reg_buf + offset, buf, 4);
9744 regcache_raw_write (regcache, double_regnum, reg_buf);
9748 static struct value *
9749 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
9751 const int *reg_p = baton;
9752 return value_of_register (*reg_p, frame);
9755 static enum gdb_osabi
9756 arm_elf_osabi_sniffer (bfd *abfd)
9758 unsigned int elfosabi;
9759 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
9761 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9763 if (elfosabi == ELFOSABI_ARM)
9764 /* GNU tools use this value. Check note sections in this case,
9766 bfd_map_over_sections (abfd,
9767 generic_elf_osabi_sniff_abi_tag_sections,
9770 /* Anything else will be handled by the generic ELF sniffer. */
9775 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
9776 struct reggroup *group)
9778 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9779 this, FPS register belongs to save_regroup, restore_reggroup, and
9780 all_reggroup, of course. */
9781 if (regnum == ARM_FPS_REGNUM)
9782 return (group == float_reggroup
9783 || group == save_reggroup
9784 || group == restore_reggroup
9785 || group == all_reggroup);
9787 return default_register_reggroup_p (gdbarch, regnum, group);
9791 /* For backward-compatibility we allow two 'g' packet lengths with
9792 the remote protocol depending on whether FPA registers are
9793 supplied. M-profile targets do not have FPA registers, but some
9794 stubs already exist in the wild which use a 'g' packet which
9795 supplies them albeit with dummy values. The packet format which
9796 includes FPA registers should be considered deprecated for
9797 M-profile targets. */
9800 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
9802 if (gdbarch_tdep (gdbarch)->is_m)
9804 /* If we know from the executable this is an M-profile target,
9805 cater for remote targets whose register set layout is the
9806 same as the FPA layout. */
9807 register_remote_g_packet_guess (gdbarch,
9808 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9809 (16 * INT_REGISTER_SIZE)
9810 + (8 * FP_REGISTER_SIZE)
9811 + (2 * INT_REGISTER_SIZE),
9812 tdesc_arm_with_m_fpa_layout);
9814 /* The regular M-profile layout. */
9815 register_remote_g_packet_guess (gdbarch,
9816 /* r0-r12,sp,lr,pc; xpsr */
9817 (16 * INT_REGISTER_SIZE)
9818 + INT_REGISTER_SIZE,
9821 /* M-profile plus M4F VFP. */
9822 register_remote_g_packet_guess (gdbarch,
9823 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9824 (16 * INT_REGISTER_SIZE)
9825 + (16 * VFP_REGISTER_SIZE)
9826 + (2 * INT_REGISTER_SIZE),
9827 tdesc_arm_with_m_vfp_d16);
9830 /* Otherwise we don't have a useful guess. */
9834 /* Initialize the current architecture based on INFO. If possible,
9835 re-use an architecture from ARCHES, which is a list of
9836 architectures already created during this debugging session.
9838 Called e.g. at program startup, when reading a core file, and when
9839 reading a binary file. */
9841 static struct gdbarch *
9842 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
9844 struct gdbarch_tdep *tdep;
9845 struct gdbarch *gdbarch;
9846 struct gdbarch_list *best_arch;
9847 enum arm_abi_kind arm_abi = arm_abi_global;
9848 enum arm_float_model fp_model = arm_fp_model;
9849 struct tdesc_arch_data *tdesc_data = NULL;
9851 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9853 int have_fpa_registers = 1;
9854 const struct target_desc *tdesc = info.target_desc;
9856 /* If we have an object to base this architecture on, try to determine
9859 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
9861 int ei_osabi, e_flags;
9863 switch (bfd_get_flavour (info.abfd))
9865 case bfd_target_aout_flavour:
9866 /* Assume it's an old APCS-style ABI. */
9867 arm_abi = ARM_ABI_APCS;
9870 case bfd_target_coff_flavour:
9871 /* Assume it's an old APCS-style ABI. */
9873 arm_abi = ARM_ABI_APCS;
9876 case bfd_target_elf_flavour:
9877 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9878 e_flags = elf_elfheader (info.abfd)->e_flags;
9880 if (ei_osabi == ELFOSABI_ARM)
9882 /* GNU tools used to use this value, but do not for EABI
9883 objects. There's nowhere to tag an EABI version
9884 anyway, so assume APCS. */
9885 arm_abi = ARM_ABI_APCS;
9887 else if (ei_osabi == ELFOSABI_NONE)
9889 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9890 int attr_arch, attr_profile;
9894 case EF_ARM_EABI_UNKNOWN:
9895 /* Assume GNU tools. */
9896 arm_abi = ARM_ABI_APCS;
9899 case EF_ARM_EABI_VER4:
9900 case EF_ARM_EABI_VER5:
9901 arm_abi = ARM_ABI_AAPCS;
9902 /* EABI binaries default to VFP float ordering.
9903 They may also contain build attributes that can
9904 be used to identify if the VFP argument-passing
9906 if (fp_model == ARM_FLOAT_AUTO)
9909 switch (bfd_elf_get_obj_attr_int (info.abfd,
9914 /* "The user intended FP parameter/result
9915 passing to conform to AAPCS, base
9917 fp_model = ARM_FLOAT_SOFT_VFP;
9920 /* "The user intended FP parameter/result
9921 passing to conform to AAPCS, VFP
9923 fp_model = ARM_FLOAT_VFP;
9926 /* "The user intended FP parameter/result
9927 passing to conform to tool chain-specific
9928 conventions" - we don't know any such
9929 conventions, so leave it as "auto". */
9932 /* Attribute value not mentioned in the
9933 October 2008 ABI, so leave it as
9938 fp_model = ARM_FLOAT_SOFT_VFP;
9944 /* Leave it as "auto". */
9945 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9950 /* Detect M-profile programs. This only works if the
9951 executable file includes build attributes; GCC does
9952 copy them to the executable, but e.g. RealView does
9954 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9956 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9958 Tag_CPU_arch_profile);
9959 /* GCC specifies the profile for v6-M; RealView only
9960 specifies the profile for architectures starting with
9961 V7 (as opposed to architectures with a tag
9962 numerically greater than TAG_CPU_ARCH_V7). */
9963 if (!tdesc_has_registers (tdesc)
9964 && (attr_arch == TAG_CPU_ARCH_V6_M
9965 || attr_arch == TAG_CPU_ARCH_V6S_M
9966 || attr_profile == 'M'))
9971 if (fp_model == ARM_FLOAT_AUTO)
9973 int e_flags = elf_elfheader (info.abfd)->e_flags;
9975 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9978 /* Leave it as "auto". Strictly speaking this case
9979 means FPA, but almost nobody uses that now, and
9980 many toolchains fail to set the appropriate bits
9981 for the floating-point model they use. */
9983 case EF_ARM_SOFT_FLOAT:
9984 fp_model = ARM_FLOAT_SOFT_FPA;
9986 case EF_ARM_VFP_FLOAT:
9987 fp_model = ARM_FLOAT_VFP;
9989 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9990 fp_model = ARM_FLOAT_SOFT_VFP;
9995 if (e_flags & EF_ARM_BE8)
9996 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10001 /* Leave it as "auto". */
10006 /* Check any target description for validity. */
10007 if (tdesc_has_registers (tdesc))
10009 /* For most registers we require GDB's default names; but also allow
10010 the numeric names for sp / lr / pc, as a convenience. */
10011 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
10012 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
10013 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
10015 const struct tdesc_feature *feature;
10018 feature = tdesc_find_feature (tdesc,
10019 "org.gnu.gdb.arm.core");
10020 if (feature == NULL)
10022 feature = tdesc_find_feature (tdesc,
10023 "org.gnu.gdb.arm.m-profile");
10024 if (feature == NULL)
10030 tdesc_data = tdesc_data_alloc ();
10033 for (i = 0; i < ARM_SP_REGNUM; i++)
10034 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10035 arm_register_names[i]);
10036 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10039 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10042 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
10046 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10047 ARM_PS_REGNUM, "xpsr");
10049 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10050 ARM_PS_REGNUM, "cpsr");
10054 tdesc_data_cleanup (tdesc_data);
10058 feature = tdesc_find_feature (tdesc,
10059 "org.gnu.gdb.arm.fpa");
10060 if (feature != NULL)
10063 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
10064 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
10065 arm_register_names[i]);
10068 tdesc_data_cleanup (tdesc_data);
10073 have_fpa_registers = 0;
10075 feature = tdesc_find_feature (tdesc,
10076 "org.gnu.gdb.xscale.iwmmxt");
10077 if (feature != NULL)
10079 static const char *const iwmmxt_names[] = {
10080 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10081 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10082 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10083 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10087 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
10089 &= tdesc_numbered_register (feature, tdesc_data, i,
10090 iwmmxt_names[i - ARM_WR0_REGNUM]);
10092 /* Check for the control registers, but do not fail if they
10094 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
10095 tdesc_numbered_register (feature, tdesc_data, i,
10096 iwmmxt_names[i - ARM_WR0_REGNUM]);
10098 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
10100 &= tdesc_numbered_register (feature, tdesc_data, i,
10101 iwmmxt_names[i - ARM_WR0_REGNUM]);
10105 tdesc_data_cleanup (tdesc_data);
10110 /* If we have a VFP unit, check whether the single precision registers
10111 are present. If not, then we will synthesize them as pseudo
10113 feature = tdesc_find_feature (tdesc,
10114 "org.gnu.gdb.arm.vfp");
10115 if (feature != NULL)
10117 static const char *const vfp_double_names[] = {
10118 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10119 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10120 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10121 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10124 /* Require the double precision registers. There must be either
10127 for (i = 0; i < 32; i++)
10129 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10131 vfp_double_names[i]);
10135 if (!valid_p && i == 16)
10138 /* Also require FPSCR. */
10139 valid_p &= tdesc_numbered_register (feature, tdesc_data,
10140 ARM_FPSCR_REGNUM, "fpscr");
10143 tdesc_data_cleanup (tdesc_data);
10147 if (tdesc_unnumbered_register (feature, "s0") == 0)
10148 have_vfp_pseudos = 1;
10150 have_vfp_registers = 1;
10152 /* If we have VFP, also check for NEON. The architecture allows
10153 NEON without VFP (integer vector operations only), but GDB
10154 does not support that. */
10155 feature = tdesc_find_feature (tdesc,
10156 "org.gnu.gdb.arm.neon");
10157 if (feature != NULL)
10159 /* NEON requires 32 double-precision registers. */
10162 tdesc_data_cleanup (tdesc_data);
10166 /* If there are quad registers defined by the stub, use
10167 their type; otherwise (normally) provide them with
10168 the default type. */
10169 if (tdesc_unnumbered_register (feature, "q0") == 0)
10170 have_neon_pseudos = 1;
10177 /* If there is already a candidate, use it. */
10178 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
10180 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
10182 if (arm_abi != ARM_ABI_AUTO
10183 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
10186 if (fp_model != ARM_FLOAT_AUTO
10187 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
10190 /* There are various other properties in tdep that we do not
10191 need to check here: those derived from a target description,
10192 since gdbarches with a different target description are
10193 automatically disqualified. */
10195 /* Do check is_m, though, since it might come from the binary. */
10196 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
10199 /* Found a match. */
10203 if (best_arch != NULL)
10205 if (tdesc_data != NULL)
10206 tdesc_data_cleanup (tdesc_data);
10207 return best_arch->gdbarch;
10210 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
10211 gdbarch = gdbarch_alloc (&info, tdep);
10213 /* Record additional information about the architecture we are defining.
10214 These are gdbarch discriminators, like the OSABI. */
10215 tdep->arm_abi = arm_abi;
10216 tdep->fp_model = fp_model;
10218 tdep->have_fpa_registers = have_fpa_registers;
10219 tdep->have_vfp_registers = have_vfp_registers;
10220 tdep->have_vfp_pseudos = have_vfp_pseudos;
10221 tdep->have_neon_pseudos = have_neon_pseudos;
10222 tdep->have_neon = have_neon;
10224 arm_register_g_packet_guesses (gdbarch);
10227 switch (info.byte_order_for_code)
10229 case BFD_ENDIAN_BIG:
10230 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
10231 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
10232 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
10233 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
10237 case BFD_ENDIAN_LITTLE:
10238 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
10239 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
10240 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
10241 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
10246 internal_error (__FILE__, __LINE__,
10247 _("arm_gdbarch_init: bad byte order for float format"));
10250 /* On ARM targets char defaults to unsigned. */
10251 set_gdbarch_char_signed (gdbarch, 0);
10253 /* Note: for displaced stepping, this includes the breakpoint, and one word
10254 of additional scratch space. This setting isn't used for anything beside
10255 displaced stepping at present. */
10256 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
10258 /* This should be low enough for everything. */
10259 tdep->lowest_pc = 0x20;
10260 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
10262 /* The default, for both APCS and AAPCS, is to return small
10263 structures in registers. */
10264 tdep->struct_return = reg_struct_return;
10266 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
10267 set_gdbarch_frame_align (gdbarch, arm_frame_align);
10269 set_gdbarch_write_pc (gdbarch, arm_write_pc);
10271 /* Frame handling. */
10272 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
10273 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
10274 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
10276 frame_base_set_default (gdbarch, &arm_normal_base);
10278 /* Address manipulation. */
10279 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
10281 /* Advance PC across function entry code. */
10282 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
10284 /* Detect whether PC is in function epilogue. */
10285 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
10287 /* Skip trampolines. */
10288 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
10290 /* The stack grows downward. */
10291 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
10293 /* Breakpoint manipulation. */
10294 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
10295 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
10296 arm_remote_breakpoint_from_pc);
10298 /* Information about registers, etc. */
10299 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
10300 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
10301 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
10302 set_gdbarch_register_type (gdbarch, arm_register_type);
10303 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
10305 /* This "info float" is FPA-specific. Use the generic version if we
10306 do not have FPA. */
10307 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
10308 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
10310 /* Internal <-> external register number maps. */
10311 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
10312 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
10314 set_gdbarch_register_name (gdbarch, arm_register_name);
10316 /* Returning results. */
10317 set_gdbarch_return_value (gdbarch, arm_return_value);
10320 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
10322 /* Minsymbol frobbing. */
10323 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
10324 set_gdbarch_coff_make_msymbol_special (gdbarch,
10325 arm_coff_make_msymbol_special);
10326 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
10328 /* Thumb-2 IT block support. */
10329 set_gdbarch_adjust_breakpoint_address (gdbarch,
10330 arm_adjust_breakpoint_address);
10332 /* Virtual tables. */
10333 set_gdbarch_vbit_in_delta (gdbarch, 1);
10335 /* Hook in the ABI-specific overrides, if they have been registered. */
10336 gdbarch_init_osabi (info, gdbarch);
10338 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
10340 /* Add some default predicates. */
10342 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
10343 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
10344 dwarf2_append_unwinders (gdbarch);
10345 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
10346 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
10348 /* Now we have tuned the configuration, set a few final things,
10349 based on what the OS ABI has told us. */
10351 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10352 binaries are always marked. */
10353 if (tdep->arm_abi == ARM_ABI_AUTO)
10354 tdep->arm_abi = ARM_ABI_APCS;
10356 /* Watchpoints are not steppable. */
10357 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
10359 /* We used to default to FPA for generic ARM, but almost nobody
10360 uses that now, and we now provide a way for the user to force
10361 the model. So default to the most useful variant. */
10362 if (tdep->fp_model == ARM_FLOAT_AUTO)
10363 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
10365 if (tdep->jb_pc >= 0)
10366 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
10368 /* Floating point sizes and format. */
10369 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
10370 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
10372 set_gdbarch_double_format
10373 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10374 set_gdbarch_long_double_format
10375 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
10379 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
10380 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
10383 if (have_vfp_pseudos)
10385 /* NOTE: These are the only pseudo registers used by
10386 the ARM target at the moment. If more are added, a
10387 little more care in numbering will be needed. */
10389 int num_pseudos = 32;
10390 if (have_neon_pseudos)
10392 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
10393 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
10394 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
10399 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
10401 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
10403 /* Override tdesc_register_type to adjust the types of VFP
10404 registers for NEON. */
10405 set_gdbarch_register_type (gdbarch, arm_register_type);
10408 /* Add standard register aliases. We add aliases even for those
10409 nanes which are used by the current architecture - it's simpler,
10410 and does no harm, since nothing ever lists user registers. */
10411 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
10412 user_reg_add (gdbarch, arm_register_aliases[i].name,
10413 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
10419 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
10421 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
10426 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10427 (unsigned long) tdep->lowest_pc);
10430 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
10433 _initialize_arm_tdep (void)
10435 struct ui_file *stb;
10437 struct cmd_list_element *new_set, *new_show;
10438 const char *setname;
10439 const char *setdesc;
10440 const char *const *regnames;
10442 static char *helptext;
10443 char regdesc[1024], *rdptr = regdesc;
10444 size_t rest = sizeof (regdesc);
10446 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
10448 arm_objfile_data_key
10449 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
10451 /* Add ourselves to objfile event chain. */
10452 observer_attach_new_objfile (arm_exidx_new_objfile);
10454 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
10456 /* Register an ELF OS ABI sniffer for ARM binaries. */
10457 gdbarch_register_osabi_sniffer (bfd_arch_arm,
10458 bfd_target_elf_flavour,
10459 arm_elf_osabi_sniffer);
10461 /* Initialize the standard target descriptions. */
10462 initialize_tdesc_arm_with_m ();
10463 initialize_tdesc_arm_with_m_fpa_layout ();
10464 initialize_tdesc_arm_with_m_vfp_d16 ();
10465 initialize_tdesc_arm_with_iwmmxt ();
10466 initialize_tdesc_arm_with_vfpv2 ();
10467 initialize_tdesc_arm_with_vfpv3 ();
10468 initialize_tdesc_arm_with_neon ();
10470 /* Get the number of possible sets of register names defined in opcodes. */
10471 num_disassembly_options = get_arm_regname_num_options ();
10473 /* Add root prefix command for all "set arm"/"show arm" commands. */
10474 add_prefix_cmd ("arm", no_class, set_arm_command,
10475 _("Various ARM-specific commands."),
10476 &setarmcmdlist, "set arm ", 0, &setlist);
10478 add_prefix_cmd ("arm", no_class, show_arm_command,
10479 _("Various ARM-specific commands."),
10480 &showarmcmdlist, "show arm ", 0, &showlist);
10482 /* Sync the opcode insn printer with our register viewer. */
10483 parse_arm_disassembler_option ("reg-names-std");
10485 /* Initialize the array that will be passed to
10486 add_setshow_enum_cmd(). */
10487 valid_disassembly_styles
10488 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
10489 for (i = 0; i < num_disassembly_options; i++)
10491 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10492 valid_disassembly_styles[i] = setname;
10493 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
10496 /* When we find the default names, tell the disassembler to use
10498 if (!strcmp (setname, "std"))
10500 disassembly_style = setname;
10501 set_arm_regname_option (i);
10504 /* Mark the end of valid options. */
10505 valid_disassembly_styles[num_disassembly_options] = NULL;
10507 /* Create the help text. */
10508 stb = mem_fileopen ();
10509 fprintf_unfiltered (stb, "%s%s%s",
10510 _("The valid values are:\n"),
10512 _("The default is \"std\"."));
10513 helptext = ui_file_xstrdup (stb, NULL);
10514 ui_file_delete (stb);
10516 add_setshow_enum_cmd("disassembler", no_class,
10517 valid_disassembly_styles, &disassembly_style,
10518 _("Set the disassembly style."),
10519 _("Show the disassembly style."),
10521 set_disassembly_style_sfunc,
10522 NULL, /* FIXME: i18n: The disassembly style is
10524 &setarmcmdlist, &showarmcmdlist);
10526 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
10527 _("Set usage of ARM 32-bit mode."),
10528 _("Show usage of ARM 32-bit mode."),
10529 _("When off, a 26-bit PC will be used."),
10531 NULL, /* FIXME: i18n: Usage of ARM 32-bit
10533 &setarmcmdlist, &showarmcmdlist);
10535 /* Add a command to allow the user to force the FPU model. */
10536 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
10537 _("Set the floating point type."),
10538 _("Show the floating point type."),
10539 _("auto - Determine the FP typefrom the OS-ABI.\n\
10540 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10541 fpa - FPA co-processor (GCC compiled).\n\
10542 softvfp - Software FP with pure-endian doubles.\n\
10543 vfp - VFP co-processor."),
10544 set_fp_model_sfunc, show_fp_model,
10545 &setarmcmdlist, &showarmcmdlist);
10547 /* Add a command to allow the user to force the ABI. */
10548 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
10550 _("Show the ABI."),
10551 NULL, arm_set_abi, arm_show_abi,
10552 &setarmcmdlist, &showarmcmdlist);
10554 /* Add two commands to allow the user to force the assumed
10556 add_setshow_enum_cmd ("fallback-mode", class_support,
10557 arm_mode_strings, &arm_fallback_mode_string,
10558 _("Set the mode assumed when symbols are unavailable."),
10559 _("Show the mode assumed when symbols are unavailable."),
10560 NULL, NULL, arm_show_fallback_mode,
10561 &setarmcmdlist, &showarmcmdlist);
10562 add_setshow_enum_cmd ("force-mode", class_support,
10563 arm_mode_strings, &arm_force_mode_string,
10564 _("Set the mode assumed even when symbols are available."),
10565 _("Show the mode assumed even when symbols are available."),
10566 NULL, NULL, arm_show_force_mode,
10567 &setarmcmdlist, &showarmcmdlist);
10569 /* Debugging flag. */
10570 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
10571 _("Set ARM debugging."),
10572 _("Show ARM debugging."),
10573 _("When on, arm-specific debugging is enabled."),
10575 NULL, /* FIXME: i18n: "ARM debugging is %s. */
10576 &setdebuglist, &showdebuglist);
10579 /* ARM-reversible process record data structures. */
10581 #define ARM_INSN_SIZE_BYTES 4
10582 #define THUMB_INSN_SIZE_BYTES 2
10583 #define THUMB2_INSN_SIZE_BYTES 4
10586 #define INSN_S_L_BIT_NUM 20
10588 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10591 unsigned int reg_len = LENGTH; \
10594 REGS = XNEWVEC (uint32_t, reg_len); \
10595 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10600 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10603 unsigned int mem_len = LENGTH; \
10606 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10607 memcpy(&MEMS->len, &RECORD_BUF[0], \
10608 sizeof(struct arm_mem_r) * LENGTH); \
10613 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10614 #define INSN_RECORDED(ARM_RECORD) \
10615 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10617 /* ARM memory record structure. */
10620 uint32_t len; /* Record length. */
10621 CORE_ADDR addr; /* Memory address. */
10624 /* ARM instruction record contains opcode of current insn
10625 and execution state (before entry to decode_insn()),
10626 contains list of to-be-modified registers and
10627 memory blocks (on return from decode_insn()). */
10629 typedef struct insn_decode_record_t
10631 struct gdbarch *gdbarch;
10632 struct regcache *regcache;
10633 CORE_ADDR this_addr; /* Address of the insn being decoded. */
10634 uint32_t arm_insn; /* Should accommodate thumb. */
10635 uint32_t cond; /* Condition code. */
10636 uint32_t opcode; /* Insn opcode. */
10637 uint32_t decode; /* Insn decode bits. */
10638 uint32_t mem_rec_count; /* No of mem records. */
10639 uint32_t reg_rec_count; /* No of reg records. */
10640 uint32_t *arm_regs; /* Registers to be saved for this record. */
10641 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
10642 } insn_decode_record;
10645 /* Checks ARM SBZ and SBO mandatory fields. */
10648 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
10650 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10673 } arm_record_strx_t;
10684 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
10685 uint32_t *record_buf_mem, arm_record_strx_t str_type)
10688 struct regcache *reg_cache = arm_insn_r->regcache;
10689 ULONGEST u_regval[2]= {0};
10691 uint32_t reg_src1 = 0, reg_src2 = 0;
10692 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10693 uint32_t opcode1 = 0;
10695 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10696 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10697 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10700 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10702 /* 1) Handle misc store, immediate offset. */
10703 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10704 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10705 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10706 regcache_raw_read_unsigned (reg_cache, reg_src1,
10708 if (ARM_PC_REGNUM == reg_src1)
10710 /* If R15 was used as Rn, hence current PC+8. */
10711 u_regval[0] = u_regval[0] + 8;
10713 offset_8 = (immed_high << 4) | immed_low;
10714 /* Calculate target store address. */
10715 if (14 == arm_insn_r->opcode)
10717 tgt_mem_addr = u_regval[0] + offset_8;
10721 tgt_mem_addr = u_regval[0] - offset_8;
10723 if (ARM_RECORD_STRH == str_type)
10725 record_buf_mem[0] = 2;
10726 record_buf_mem[1] = tgt_mem_addr;
10727 arm_insn_r->mem_rec_count = 1;
10729 else if (ARM_RECORD_STRD == str_type)
10731 record_buf_mem[0] = 4;
10732 record_buf_mem[1] = tgt_mem_addr;
10733 record_buf_mem[2] = 4;
10734 record_buf_mem[3] = tgt_mem_addr + 4;
10735 arm_insn_r->mem_rec_count = 2;
10738 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
10740 /* 2) Store, register offset. */
10742 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10744 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10745 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10746 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10747 if (15 == reg_src2)
10749 /* If R15 was used as Rn, hence current PC+8. */
10750 u_regval[0] = u_regval[0] + 8;
10752 /* Calculate target store address, Rn +/- Rm, register offset. */
10753 if (12 == arm_insn_r->opcode)
10755 tgt_mem_addr = u_regval[0] + u_regval[1];
10759 tgt_mem_addr = u_regval[1] - u_regval[0];
10761 if (ARM_RECORD_STRH == str_type)
10763 record_buf_mem[0] = 2;
10764 record_buf_mem[1] = tgt_mem_addr;
10765 arm_insn_r->mem_rec_count = 1;
10767 else if (ARM_RECORD_STRD == str_type)
10769 record_buf_mem[0] = 4;
10770 record_buf_mem[1] = tgt_mem_addr;
10771 record_buf_mem[2] = 4;
10772 record_buf_mem[3] = tgt_mem_addr + 4;
10773 arm_insn_r->mem_rec_count = 2;
10776 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10777 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10779 /* 3) Store, immediate pre-indexed. */
10780 /* 5) Store, immediate post-indexed. */
10781 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
10782 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
10783 offset_8 = (immed_high << 4) | immed_low;
10784 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10785 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10786 /* Calculate target store address, Rn +/- Rm, register offset. */
10787 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
10789 tgt_mem_addr = u_regval[0] + offset_8;
10793 tgt_mem_addr = u_regval[0] - offset_8;
10795 if (ARM_RECORD_STRH == str_type)
10797 record_buf_mem[0] = 2;
10798 record_buf_mem[1] = tgt_mem_addr;
10799 arm_insn_r->mem_rec_count = 1;
10801 else if (ARM_RECORD_STRD == str_type)
10803 record_buf_mem[0] = 4;
10804 record_buf_mem[1] = tgt_mem_addr;
10805 record_buf_mem[2] = 4;
10806 record_buf_mem[3] = tgt_mem_addr + 4;
10807 arm_insn_r->mem_rec_count = 2;
10809 /* Record Rn also as it changes. */
10810 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10811 arm_insn_r->reg_rec_count = 1;
10813 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
10814 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10816 /* 4) Store, register pre-indexed. */
10817 /* 6) Store, register post -indexed. */
10818 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10819 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10820 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10821 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10822 /* Calculate target store address, Rn +/- Rm, register offset. */
10823 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
10825 tgt_mem_addr = u_regval[0] + u_regval[1];
10829 tgt_mem_addr = u_regval[1] - u_regval[0];
10831 if (ARM_RECORD_STRH == str_type)
10833 record_buf_mem[0] = 2;
10834 record_buf_mem[1] = tgt_mem_addr;
10835 arm_insn_r->mem_rec_count = 1;
10837 else if (ARM_RECORD_STRD == str_type)
10839 record_buf_mem[0] = 4;
10840 record_buf_mem[1] = tgt_mem_addr;
10841 record_buf_mem[2] = 4;
10842 record_buf_mem[3] = tgt_mem_addr + 4;
10843 arm_insn_r->mem_rec_count = 2;
10845 /* Record Rn also as it changes. */
10846 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10847 arm_insn_r->reg_rec_count = 1;
10852 /* Handling ARM extension space insns. */
10855 arm_record_extension_space (insn_decode_record *arm_insn_r)
10857 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10858 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10859 uint32_t record_buf[8], record_buf_mem[8];
10860 uint32_t reg_src1 = 0;
10861 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10862 struct regcache *reg_cache = arm_insn_r->regcache;
10863 ULONGEST u_regval = 0;
10865 gdb_assert (!INSN_RECORDED(arm_insn_r));
10866 /* Handle unconditional insn extension space. */
10868 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10869 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10870 if (arm_insn_r->cond)
10872 /* PLD has no affect on architectural state, it just affects
10874 if (5 == ((opcode1 & 0xE0) >> 5))
10877 record_buf[0] = ARM_PS_REGNUM;
10878 record_buf[1] = ARM_LR_REGNUM;
10879 arm_insn_r->reg_rec_count = 2;
10881 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10885 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10886 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10889 /* Undefined instruction on ARM V5; need to handle if later
10890 versions define it. */
10893 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10894 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10895 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10897 /* Handle arithmetic insn extension space. */
10898 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10899 && !INSN_RECORDED(arm_insn_r))
10901 /* Handle MLA(S) and MUL(S). */
10902 if (0 <= insn_op1 && 3 >= insn_op1)
10904 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10905 record_buf[1] = ARM_PS_REGNUM;
10906 arm_insn_r->reg_rec_count = 2;
10908 else if (4 <= insn_op1 && 15 >= insn_op1)
10910 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10911 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10912 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10913 record_buf[2] = ARM_PS_REGNUM;
10914 arm_insn_r->reg_rec_count = 3;
10918 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10919 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10920 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10922 /* Handle control insn extension space. */
10924 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10925 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10927 if (!bit (arm_insn_r->arm_insn,25))
10929 if (!bits (arm_insn_r->arm_insn, 4, 7))
10931 if ((0 == insn_op1) || (2 == insn_op1))
10934 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10935 arm_insn_r->reg_rec_count = 1;
10937 else if (1 == insn_op1)
10939 /* CSPR is going to be changed. */
10940 record_buf[0] = ARM_PS_REGNUM;
10941 arm_insn_r->reg_rec_count = 1;
10943 else if (3 == insn_op1)
10945 /* SPSR is going to be changed. */
10946 /* We need to get SPSR value, which is yet to be done. */
10947 printf_unfiltered (_("Process record does not support "
10948 "instruction 0x%0x at address %s.\n"),
10949 arm_insn_r->arm_insn,
10950 paddress (arm_insn_r->gdbarch,
10951 arm_insn_r->this_addr));
10955 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10960 record_buf[0] = ARM_PS_REGNUM;
10961 arm_insn_r->reg_rec_count = 1;
10963 else if (3 == insn_op1)
10966 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10967 arm_insn_r->reg_rec_count = 1;
10970 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10973 record_buf[0] = ARM_PS_REGNUM;
10974 record_buf[1] = ARM_LR_REGNUM;
10975 arm_insn_r->reg_rec_count = 2;
10977 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10979 /* QADD, QSUB, QDADD, QDSUB */
10980 record_buf[0] = ARM_PS_REGNUM;
10981 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10982 arm_insn_r->reg_rec_count = 2;
10984 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10987 record_buf[0] = ARM_PS_REGNUM;
10988 record_buf[1] = ARM_LR_REGNUM;
10989 arm_insn_r->reg_rec_count = 2;
10991 /* Save SPSR also;how? */
10992 printf_unfiltered (_("Process record does not support "
10993 "instruction 0x%0x at address %s.\n"),
10994 arm_insn_r->arm_insn,
10995 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
10998 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
10999 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
11000 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
11001 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
11004 if (0 == insn_op1 || 1 == insn_op1)
11006 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11007 /* We dont do optimization for SMULW<y> where we
11009 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11010 record_buf[1] = ARM_PS_REGNUM;
11011 arm_insn_r->reg_rec_count = 2;
11013 else if (2 == insn_op1)
11016 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11017 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11018 arm_insn_r->reg_rec_count = 2;
11020 else if (3 == insn_op1)
11023 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11024 arm_insn_r->reg_rec_count = 1;
11030 /* MSR : immediate form. */
11033 /* CSPR is going to be changed. */
11034 record_buf[0] = ARM_PS_REGNUM;
11035 arm_insn_r->reg_rec_count = 1;
11037 else if (3 == insn_op1)
11039 /* SPSR is going to be changed. */
11040 /* we need to get SPSR value, which is yet to be done */
11041 printf_unfiltered (_("Process record does not support "
11042 "instruction 0x%0x at address %s.\n"),
11043 arm_insn_r->arm_insn,
11044 paddress (arm_insn_r->gdbarch,
11045 arm_insn_r->this_addr));
11051 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
11052 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
11053 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
11055 /* Handle load/store insn extension space. */
11057 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
11058 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
11059 && !INSN_RECORDED(arm_insn_r))
11064 /* These insn, changes register and memory as well. */
11065 /* SWP or SWPB insn. */
11066 /* Get memory address given by Rn. */
11067 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11068 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11069 /* SWP insn ?, swaps word. */
11070 if (8 == arm_insn_r->opcode)
11072 record_buf_mem[0] = 4;
11076 /* SWPB insn, swaps only byte. */
11077 record_buf_mem[0] = 1;
11079 record_buf_mem[1] = u_regval;
11080 arm_insn_r->mem_rec_count = 1;
11081 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11082 arm_insn_r->reg_rec_count = 1;
11084 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11087 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11090 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11093 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11094 record_buf[1] = record_buf[0] + 1;
11095 arm_insn_r->reg_rec_count = 2;
11097 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
11100 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11103 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
11105 /* LDRH, LDRSB, LDRSH. */
11106 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11107 arm_insn_r->reg_rec_count = 1;
11112 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
11113 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
11114 && !INSN_RECORDED(arm_insn_r))
11117 /* Handle coprocessor insn extension space. */
11120 /* To be done for ARMv5 and later; as of now we return -1. */
11122 printf_unfiltered (_("Process record does not support instruction x%0x "
11123 "at address %s.\n"),arm_insn_r->arm_insn,
11124 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11127 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11128 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11133 /* Handling opcode 000 insns. */
11136 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
11138 struct regcache *reg_cache = arm_insn_r->regcache;
11139 uint32_t record_buf[8], record_buf_mem[8];
11140 ULONGEST u_regval[2] = {0};
11142 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11143 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11144 uint32_t opcode1 = 0;
11146 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11147 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11148 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
11150 /* Data processing insn /multiply insn. */
11151 if (9 == arm_insn_r->decode
11152 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11153 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
11155 /* Handle multiply instructions. */
11156 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11157 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
11159 /* Handle MLA and MUL. */
11160 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11161 record_buf[1] = ARM_PS_REGNUM;
11162 arm_insn_r->reg_rec_count = 2;
11164 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
11166 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11167 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
11168 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
11169 record_buf[2] = ARM_PS_REGNUM;
11170 arm_insn_r->reg_rec_count = 3;
11173 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11174 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
11176 /* Handle misc load insns, as 20th bit (L = 1). */
11177 /* LDR insn has a capability to do branching, if
11178 MOV LR, PC is precceded by LDR insn having Rn as R15
11179 in that case, it emulates branch and link insn, and hence we
11180 need to save CSPR and PC as well. I am not sure this is right
11181 place; as opcode = 010 LDR insn make this happen, if R15 was
11183 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11184 if (15 != reg_dest)
11186 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11187 arm_insn_r->reg_rec_count = 1;
11191 record_buf[0] = reg_dest;
11192 record_buf[1] = ARM_PS_REGNUM;
11193 arm_insn_r->reg_rec_count = 2;
11196 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11197 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
11198 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11199 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
11201 /* Handle MSR insn. */
11202 if (9 == arm_insn_r->opcode)
11204 /* CSPR is going to be changed. */
11205 record_buf[0] = ARM_PS_REGNUM;
11206 arm_insn_r->reg_rec_count = 1;
11210 /* SPSR is going to be changed. */
11211 /* How to read SPSR value? */
11212 printf_unfiltered (_("Process record does not support instruction "
11213 "0x%0x at address %s.\n"),
11214 arm_insn_r->arm_insn,
11215 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11219 else if (9 == arm_insn_r->decode
11220 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11221 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11223 /* Handling SWP, SWPB. */
11224 /* These insn, changes register and memory as well. */
11225 /* SWP or SWPB insn. */
11227 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11228 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11229 /* SWP insn ?, swaps word. */
11230 if (8 == arm_insn_r->opcode)
11232 record_buf_mem[0] = 4;
11236 /* SWPB insn, swaps only byte. */
11237 record_buf_mem[0] = 1;
11239 record_buf_mem[1] = u_regval[0];
11240 arm_insn_r->mem_rec_count = 1;
11241 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11242 arm_insn_r->reg_rec_count = 1;
11244 else if (3 == arm_insn_r->decode && 0x12 == opcode1
11245 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11247 /* Handle BLX, branch and link/exchange. */
11248 if (9 == arm_insn_r->opcode)
11250 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11251 and R14 stores the return address. */
11252 record_buf[0] = ARM_PS_REGNUM;
11253 record_buf[1] = ARM_LR_REGNUM;
11254 arm_insn_r->reg_rec_count = 2;
11257 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
11259 /* Handle enhanced software breakpoint insn, BKPT. */
11260 /* CPSR is changed to be executed in ARM state, disabling normal
11261 interrupts, entering abort mode. */
11262 /* According to high vector configuration PC is set. */
11263 /* user hit breakpoint and type reverse, in
11264 that case, we need to go back with previous CPSR and
11265 Program Counter. */
11266 record_buf[0] = ARM_PS_REGNUM;
11267 record_buf[1] = ARM_LR_REGNUM;
11268 arm_insn_r->reg_rec_count = 2;
11270 /* Save SPSR also; how? */
11271 printf_unfiltered (_("Process record does not support instruction "
11272 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11273 paddress (arm_insn_r->gdbarch,
11274 arm_insn_r->this_addr));
11277 else if (11 == arm_insn_r->decode
11278 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11280 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11282 /* Handle str(x) insn */
11283 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
11286 else if (1 == arm_insn_r->decode && 0x12 == opcode1
11287 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
11289 /* Handle BX, branch and link/exchange. */
11290 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11291 record_buf[0] = ARM_PS_REGNUM;
11292 arm_insn_r->reg_rec_count = 1;
11294 else if (1 == arm_insn_r->decode && 0x16 == opcode1
11295 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
11296 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
11298 /* Count leading zeros: CLZ. */
11299 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11300 arm_insn_r->reg_rec_count = 1;
11302 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
11303 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
11304 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
11305 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
11308 /* Handle MRS insn. */
11309 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11310 arm_insn_r->reg_rec_count = 1;
11312 else if (arm_insn_r->opcode <= 15)
11314 /* Normal data processing insns. */
11315 /* Out of 11 shifter operands mode, all the insn modifies destination
11316 register, which is specified by 13-16 decode. */
11317 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11318 record_buf[1] = ARM_PS_REGNUM;
11319 arm_insn_r->reg_rec_count = 2;
11326 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11327 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11331 /* Handling opcode 001 insns. */
11334 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
11336 uint32_t record_buf[8], record_buf_mem[8];
11338 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11339 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11341 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
11342 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
11343 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
11346 /* Handle MSR insn. */
11347 if (9 == arm_insn_r->opcode)
11349 /* CSPR is going to be changed. */
11350 record_buf[0] = ARM_PS_REGNUM;
11351 arm_insn_r->reg_rec_count = 1;
11355 /* SPSR is going to be changed. */
11358 else if (arm_insn_r->opcode <= 15)
11360 /* Normal data processing insns. */
11361 /* Out of 11 shifter operands mode, all the insn modifies destination
11362 register, which is specified by 13-16 decode. */
11363 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11364 record_buf[1] = ARM_PS_REGNUM;
11365 arm_insn_r->reg_rec_count = 2;
11372 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11373 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11377 /* Handling opcode 010 insns. */
11380 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
11382 struct regcache *reg_cache = arm_insn_r->regcache;
11384 uint32_t reg_src1 = 0 , reg_dest = 0;
11385 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11386 uint32_t record_buf[8], record_buf_mem[8];
11388 ULONGEST u_regval = 0;
11390 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11391 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11393 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11395 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11396 /* LDR insn has a capability to do branching, if
11397 MOV LR, PC is precedded by LDR insn having Rn as R15
11398 in that case, it emulates branch and link insn, and hence we
11399 need to save CSPR and PC as well. */
11400 if (ARM_PC_REGNUM != reg_dest)
11402 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11403 arm_insn_r->reg_rec_count = 1;
11407 record_buf[0] = reg_dest;
11408 record_buf[1] = ARM_PS_REGNUM;
11409 arm_insn_r->reg_rec_count = 2;
11414 /* Store, immediate offset, immediate pre-indexed,
11415 immediate post-indexed. */
11416 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11417 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
11418 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11420 if (bit (arm_insn_r->arm_insn, 23))
11422 tgt_mem_addr = u_regval + offset_12;
11426 tgt_mem_addr = u_regval - offset_12;
11429 switch (arm_insn_r->opcode)
11443 record_buf_mem[0] = 4;
11458 record_buf_mem[0] = 1;
11462 gdb_assert_not_reached ("no decoding pattern found");
11465 record_buf_mem[1] = tgt_mem_addr;
11466 arm_insn_r->mem_rec_count = 1;
11468 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11469 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11470 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11471 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11472 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11473 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11476 /* We are handling pre-indexed mode; post-indexed mode;
11477 where Rn is going to be changed. */
11478 record_buf[0] = reg_src1;
11479 arm_insn_r->reg_rec_count = 1;
11483 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11484 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11488 /* Handling opcode 011 insns. */
11491 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
11493 struct regcache *reg_cache = arm_insn_r->regcache;
11495 uint32_t shift_imm = 0;
11496 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11497 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11498 uint32_t record_buf[8], record_buf_mem[8];
11501 ULONGEST u_regval[2];
11503 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
11504 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
11506 /* Handle enhanced store insns and LDRD DSP insn,
11507 order begins according to addressing modes for store insns
11511 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11513 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
11514 /* LDR insn has a capability to do branching, if
11515 MOV LR, PC is precedded by LDR insn having Rn as R15
11516 in that case, it emulates branch and link insn, and hence we
11517 need to save CSPR and PC as well. */
11518 if (15 != reg_dest)
11520 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11521 arm_insn_r->reg_rec_count = 1;
11525 record_buf[0] = reg_dest;
11526 record_buf[1] = ARM_PS_REGNUM;
11527 arm_insn_r->reg_rec_count = 2;
11532 if (! bits (arm_insn_r->arm_insn, 4, 11))
11534 /* Store insn, register offset and register pre-indexed,
11535 register post-indexed. */
11537 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11539 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11540 regcache_raw_read_unsigned (reg_cache, reg_src1
11542 regcache_raw_read_unsigned (reg_cache, reg_src2
11544 if (15 == reg_src2)
11546 /* If R15 was used as Rn, hence current PC+8. */
11547 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11548 u_regval[0] = u_regval[0] + 8;
11550 /* Calculate target store address, Rn +/- Rm, register offset. */
11552 if (bit (arm_insn_r->arm_insn, 23))
11554 tgt_mem_addr = u_regval[0] + u_regval[1];
11558 tgt_mem_addr = u_regval[1] - u_regval[0];
11561 switch (arm_insn_r->opcode)
11575 record_buf_mem[0] = 4;
11590 record_buf_mem[0] = 1;
11594 gdb_assert_not_reached ("no decoding pattern found");
11597 record_buf_mem[1] = tgt_mem_addr;
11598 arm_insn_r->mem_rec_count = 1;
11600 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11601 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11602 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11603 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11604 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11605 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11608 /* Rn is going to be changed in pre-indexed mode and
11609 post-indexed mode as well. */
11610 record_buf[0] = reg_src2;
11611 arm_insn_r->reg_rec_count = 1;
11616 /* Store insn, scaled register offset; scaled pre-indexed. */
11617 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
11619 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
11621 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
11622 /* Get shift_imm. */
11623 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
11624 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11625 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
11626 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11627 /* Offset_12 used as shift. */
11631 /* Offset_12 used as index. */
11632 offset_12 = u_regval[0] << shift_imm;
11636 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11642 if (bit (u_regval[0], 31))
11644 offset_12 = 0xFFFFFFFF;
11653 /* This is arithmetic shift. */
11654 offset_12 = s_word >> shift_imm;
11661 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
11663 /* Get C flag value and shift it by 31. */
11664 offset_12 = (((bit (u_regval[1], 29)) << 31) \
11665 | (u_regval[0]) >> 1);
11669 offset_12 = (u_regval[0] >> shift_imm) \
11671 (sizeof(uint32_t) - shift_imm));
11676 gdb_assert_not_reached ("no decoding pattern found");
11680 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11682 if (bit (arm_insn_r->arm_insn, 23))
11684 tgt_mem_addr = u_regval[1] + offset_12;
11688 tgt_mem_addr = u_regval[1] - offset_12;
11691 switch (arm_insn_r->opcode)
11705 record_buf_mem[0] = 4;
11720 record_buf_mem[0] = 1;
11724 gdb_assert_not_reached ("no decoding pattern found");
11727 record_buf_mem[1] = tgt_mem_addr;
11728 arm_insn_r->mem_rec_count = 1;
11730 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
11731 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
11732 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
11733 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
11734 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
11735 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
11738 /* Rn is going to be changed in register scaled pre-indexed
11739 mode,and scaled post indexed mode. */
11740 record_buf[0] = reg_src2;
11741 arm_insn_r->reg_rec_count = 1;
11746 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11747 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11751 /* Handling opcode 100 insns. */
11754 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
11756 struct regcache *reg_cache = arm_insn_r->regcache;
11758 uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0;
11759 uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0;
11760 uint32_t start_address = 0, index = 0;
11761 uint32_t record_buf[24], record_buf_mem[48];
11763 ULONGEST u_regval[2] = {0};
11765 /* This mode is exclusively for load and store multiple. */
11766 /* Handle incremenrt after/before and decrment after.before mode;
11767 Rn is changing depending on W bit, but as of now we store Rn too
11768 without optimization. */
11770 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
11772 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11774 if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22))
11776 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11781 register_bits = bits (arm_insn_r->arm_insn, 0, 14);
11785 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11786 while (register_bits)
11788 if (register_bits & 0x00000001)
11789 register_list[register_count++] = 1;
11790 register_bits = register_bits >> 1;
11793 /* Extra space for Base Register and CPSR; wihtout optimization. */
11794 record_buf[register_count] = reg_src1;
11795 record_buf[register_count + 1] = ARM_PS_REGNUM;
11796 arm_insn_r->reg_rec_count = register_count + 2;
11798 for (register_count = 0; register_count < no_of_regs; register_count++)
11800 if (register_list[register_count])
11802 /* Register_count gives total no of registers
11803 and dually working as reg number. */
11804 record_buf[index] = register_count;
11812 /* It handles both STM(1) and STM(2). */
11813 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11815 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
11817 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
11818 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11819 while (register_bits)
11821 if (register_bits & 0x00000001)
11823 register_bits = register_bits >> 1;
11828 /* Decrement after. */
11830 start_address = (u_regval[0]) - (register_count * 4) + 4;
11831 arm_insn_r->mem_rec_count = register_count;
11832 while (register_count)
11834 record_buf_mem[(register_count * 2) - 1] = start_address;
11835 record_buf_mem[(register_count * 2) - 2] = 4;
11836 start_address = start_address + 4;
11841 /* Increment after. */
11843 start_address = u_regval[0];
11844 arm_insn_r->mem_rec_count = register_count;
11845 while (register_count)
11847 record_buf_mem[(register_count * 2) - 1] = start_address;
11848 record_buf_mem[(register_count * 2) - 2] = 4;
11849 start_address = start_address + 4;
11854 /* Decrement before. */
11857 start_address = (u_regval[0]) - (register_count * 4);
11858 arm_insn_r->mem_rec_count = register_count;
11859 while (register_count)
11861 record_buf_mem[(register_count * 2) - 1] = start_address;
11862 record_buf_mem[(register_count * 2) - 2] = 4;
11863 start_address = start_address + 4;
11868 /* Increment before. */
11870 start_address = u_regval[0] + 4;
11871 arm_insn_r->mem_rec_count = register_count;
11872 while (register_count)
11874 record_buf_mem[(register_count * 2) - 1] = start_address;
11875 record_buf_mem[(register_count * 2) - 2] = 4;
11876 start_address = start_address + 4;
11882 gdb_assert_not_reached ("no decoding pattern found");
11886 /* Base register also changes; based on condition and W bit. */
11887 /* We save it anyway without optimization. */
11888 record_buf[0] = reg_src1;
11889 arm_insn_r->reg_rec_count = 1;
11892 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11893 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11897 /* Handling opcode 101 insns. */
11900 arm_record_b_bl (insn_decode_record *arm_insn_r)
11902 uint32_t record_buf[8];
11904 /* Handle B, BL, BLX(1) insns. */
11905 /* B simply branches so we do nothing here. */
11906 /* Note: BLX(1) doesnt fall here but instead it falls into
11907 extension space. */
11908 if (bit (arm_insn_r->arm_insn, 24))
11910 record_buf[0] = ARM_LR_REGNUM;
11911 arm_insn_r->reg_rec_count = 1;
11914 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11919 /* Handling opcode 110 insns. */
11922 arm_record_coproc (insn_decode_record *arm_insn_r)
11924 printf_unfiltered (_("Process record does not support instruction "
11925 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11926 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11931 /* Handling opcode 111 insns. */
11934 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11936 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11937 struct regcache *reg_cache = arm_insn_r->regcache;
11938 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
11940 /* Handle SWI insn; system call would be handled over here. */
11942 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11943 if (15 == arm_insn_r->opcode)
11945 /* Handle arm syscall insn. */
11946 if (tdep->arm_swi_record != NULL)
11948 ret = tdep->arm_swi_record(reg_cache);
11952 printf_unfiltered (_("no syscall record support\n"));
11957 printf_unfiltered (_("Process record does not support instruction "
11958 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11959 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11963 /* Handling opcode 000 insns. */
11966 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11968 uint32_t record_buf[8];
11969 uint32_t reg_src1 = 0;
11971 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11973 record_buf[0] = ARM_PS_REGNUM;
11974 record_buf[1] = reg_src1;
11975 thumb_insn_r->reg_rec_count = 2;
11977 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11983 /* Handling opcode 001 insns. */
11986 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11988 uint32_t record_buf[8];
11989 uint32_t reg_src1 = 0;
11991 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11993 record_buf[0] = ARM_PS_REGNUM;
11994 record_buf[1] = reg_src1;
11995 thumb_insn_r->reg_rec_count = 2;
11997 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12002 /* Handling opcode 010 insns. */
12005 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
12007 struct regcache *reg_cache = thumb_insn_r->regcache;
12008 uint32_t record_buf[8], record_buf_mem[8];
12010 uint32_t reg_src1 = 0, reg_src2 = 0;
12011 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12013 ULONGEST u_regval[2] = {0};
12015 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
12017 if (bit (thumb_insn_r->arm_insn, 12))
12019 /* Handle load/store register offset. */
12020 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
12021 if (opcode2 >= 12 && opcode2 <= 15)
12023 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12024 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
12025 record_buf[0] = reg_src1;
12026 thumb_insn_r->reg_rec_count = 1;
12028 else if (opcode2 >= 8 && opcode2 <= 10)
12030 /* STR(2), STRB(2), STRH(2) . */
12031 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12032 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
12033 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
12034 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
12036 record_buf_mem[0] = 4; /* STR (2). */
12037 else if (10 == opcode2)
12038 record_buf_mem[0] = 1; /* STRB (2). */
12039 else if (9 == opcode2)
12040 record_buf_mem[0] = 2; /* STRH (2). */
12041 record_buf_mem[1] = u_regval[0] + u_regval[1];
12042 thumb_insn_r->mem_rec_count = 1;
12045 else if (bit (thumb_insn_r->arm_insn, 11))
12047 /* Handle load from literal pool. */
12049 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12050 record_buf[0] = reg_src1;
12051 thumb_insn_r->reg_rec_count = 1;
12055 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
12056 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
12057 if ((3 == opcode2) && (!opcode3))
12059 /* Branch with exchange. */
12060 record_buf[0] = ARM_PS_REGNUM;
12061 thumb_insn_r->reg_rec_count = 1;
12065 /* Format 8; special data processing insns. */
12066 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12067 record_buf[0] = ARM_PS_REGNUM;
12068 record_buf[1] = reg_src1;
12069 thumb_insn_r->reg_rec_count = 2;
12074 /* Format 5; data processing insns. */
12075 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12076 if (bit (thumb_insn_r->arm_insn, 7))
12078 reg_src1 = reg_src1 + 8;
12080 record_buf[0] = ARM_PS_REGNUM;
12081 record_buf[1] = reg_src1;
12082 thumb_insn_r->reg_rec_count = 2;
12085 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12086 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12092 /* Handling opcode 001 insns. */
12095 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
12097 struct regcache *reg_cache = thumb_insn_r->regcache;
12098 uint32_t record_buf[8], record_buf_mem[8];
12100 uint32_t reg_src1 = 0;
12101 uint32_t opcode = 0, immed_5 = 0;
12103 ULONGEST u_regval = 0;
12105 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12110 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12111 record_buf[0] = reg_src1;
12112 thumb_insn_r->reg_rec_count = 1;
12117 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12118 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12119 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12120 record_buf_mem[0] = 4;
12121 record_buf_mem[1] = u_regval + (immed_5 * 4);
12122 thumb_insn_r->mem_rec_count = 1;
12125 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12126 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12132 /* Handling opcode 100 insns. */
12135 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
12137 struct regcache *reg_cache = thumb_insn_r->regcache;
12138 uint32_t record_buf[8], record_buf_mem[8];
12140 uint32_t reg_src1 = 0;
12141 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12143 ULONGEST u_regval = 0;
12145 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12150 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12151 record_buf[0] = reg_src1;
12152 thumb_insn_r->reg_rec_count = 1;
12154 else if (1 == opcode)
12157 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
12158 record_buf[0] = reg_src1;
12159 thumb_insn_r->reg_rec_count = 1;
12161 else if (2 == opcode)
12164 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
12165 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
12166 record_buf_mem[0] = 4;
12167 record_buf_mem[1] = u_regval + (immed_8 * 4);
12168 thumb_insn_r->mem_rec_count = 1;
12170 else if (0 == opcode)
12173 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
12174 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
12175 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12176 record_buf_mem[0] = 2;
12177 record_buf_mem[1] = u_regval + (immed_5 * 2);
12178 thumb_insn_r->mem_rec_count = 1;
12181 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12182 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12188 /* Handling opcode 101 insns. */
12191 thumb_record_misc (insn_decode_record *thumb_insn_r)
12193 struct regcache *reg_cache = thumb_insn_r->regcache;
12195 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12196 uint32_t register_bits = 0, register_count = 0;
12197 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12198 uint32_t record_buf[24], record_buf_mem[48];
12201 ULONGEST u_regval = 0;
12203 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
12204 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12205 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
12210 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12211 while (register_bits)
12213 if (register_bits & 0x00000001)
12214 register_list[register_count++] = 1;
12215 register_bits = register_bits >> 1;
12217 record_buf[register_count] = ARM_PS_REGNUM;
12218 record_buf[register_count + 1] = ARM_SP_REGNUM;
12219 thumb_insn_r->reg_rec_count = register_count + 2;
12220 for (register_count = 0; register_count < 8; register_count++)
12222 if (register_list[register_count])
12224 record_buf[index] = register_count;
12229 else if (10 == opcode2)
12232 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12233 regcache_raw_read_unsigned (reg_cache, ARM_PC_REGNUM, &u_regval);
12234 while (register_bits)
12236 if (register_bits & 0x00000001)
12238 register_bits = register_bits >> 1;
12240 start_address = u_regval - \
12241 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
12242 thumb_insn_r->mem_rec_count = register_count;
12243 while (register_count)
12245 record_buf_mem[(register_count * 2) - 1] = start_address;
12246 record_buf_mem[(register_count * 2) - 2] = 4;
12247 start_address = start_address + 4;
12250 record_buf[0] = ARM_SP_REGNUM;
12251 thumb_insn_r->reg_rec_count = 1;
12253 else if (0x1E == opcode1)
12256 /* Handle enhanced software breakpoint insn, BKPT. */
12257 /* CPSR is changed to be executed in ARM state, disabling normal
12258 interrupts, entering abort mode. */
12259 /* According to high vector configuration PC is set. */
12260 /* User hits breakpoint and type reverse, in that case, we need to go back with
12261 previous CPSR and Program Counter. */
12262 record_buf[0] = ARM_PS_REGNUM;
12263 record_buf[1] = ARM_LR_REGNUM;
12264 thumb_insn_r->reg_rec_count = 2;
12265 /* We need to save SPSR value, which is not yet done. */
12266 printf_unfiltered (_("Process record does not support instruction "
12267 "0x%0x at address %s.\n"),
12268 thumb_insn_r->arm_insn,
12269 paddress (thumb_insn_r->gdbarch,
12270 thumb_insn_r->this_addr));
12273 else if ((0 == opcode) || (1 == opcode))
12275 /* ADD(5), ADD(6). */
12276 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12277 record_buf[0] = reg_src1;
12278 thumb_insn_r->reg_rec_count = 1;
12280 else if (2 == opcode)
12282 /* ADD(7), SUB(4). */
12283 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12284 record_buf[0] = ARM_SP_REGNUM;
12285 thumb_insn_r->reg_rec_count = 1;
12288 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12289 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12295 /* Handling opcode 110 insns. */
12298 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12300 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12301 struct regcache *reg_cache = thumb_insn_r->regcache;
12303 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12304 uint32_t reg_src1 = 0;
12305 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12306 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12307 uint32_t record_buf[24], record_buf_mem[48];
12309 ULONGEST u_regval = 0;
12311 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12312 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12318 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12320 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12321 while (register_bits)
12323 if (register_bits & 0x00000001)
12324 register_list[register_count++] = 1;
12325 register_bits = register_bits >> 1;
12327 record_buf[register_count] = reg_src1;
12328 thumb_insn_r->reg_rec_count = register_count + 1;
12329 for (register_count = 0; register_count < 8; register_count++)
12331 if (register_list[register_count])
12333 record_buf[index] = register_count;
12338 else if (0 == opcode2)
12340 /* It handles both STMIA. */
12341 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12343 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12344 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12345 while (register_bits)
12347 if (register_bits & 0x00000001)
12349 register_bits = register_bits >> 1;
12351 start_address = u_regval;
12352 thumb_insn_r->mem_rec_count = register_count;
12353 while (register_count)
12355 record_buf_mem[(register_count * 2) - 1] = start_address;
12356 record_buf_mem[(register_count * 2) - 2] = 4;
12357 start_address = start_address + 4;
12361 else if (0x1F == opcode1)
12363 /* Handle arm syscall insn. */
12364 if (tdep->arm_swi_record != NULL)
12366 ret = tdep->arm_swi_record(reg_cache);
12370 printf_unfiltered (_("no syscall record support\n"));
12375 /* B (1), conditional branch is automatically taken care in process_record,
12376 as PC is saved there. */
12378 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12379 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12385 /* Handling opcode 111 insns. */
12388 thumb_record_branch (insn_decode_record *thumb_insn_r)
12390 uint32_t record_buf[8];
12391 uint32_t bits_h = 0;
12393 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12395 if (2 == bits_h || 3 == bits_h)
12398 record_buf[0] = ARM_LR_REGNUM;
12399 thumb_insn_r->reg_rec_count = 1;
12401 else if (1 == bits_h)
12404 record_buf[0] = ARM_PS_REGNUM;
12405 record_buf[1] = ARM_LR_REGNUM;
12406 thumb_insn_r->reg_rec_count = 2;
12409 /* B(2) is automatically taken care in process_record, as PC is
12412 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12418 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12419 and positive val on fauilure. */
12422 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12424 gdb_byte buf[insn_size];
12426 memset (&buf[0], 0, insn_size);
12428 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12430 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12432 gdbarch_byte_order (insn_record->gdbarch));
12436 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12438 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12442 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12443 uint32_t insn_size)
12446 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12447 static const sti_arm_hdl_fp_t const arm_handle_insn[8] =
12449 arm_record_data_proc_misc_ld_str, /* 000. */
12450 arm_record_data_proc_imm, /* 001. */
12451 arm_record_ld_st_imm_offset, /* 010. */
12452 arm_record_ld_st_reg_offset, /* 011. */
12453 arm_record_ld_st_multiple, /* 100. */
12454 arm_record_b_bl, /* 101. */
12455 arm_record_coproc, /* 110. */
12456 arm_record_coproc_data_proc /* 111. */
12459 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12460 static const sti_arm_hdl_fp_t const thumb_handle_insn[8] =
12462 thumb_record_shift_add_sub, /* 000. */
12463 thumb_record_add_sub_cmp_mov, /* 001. */
12464 thumb_record_ld_st_reg_offset, /* 010. */
12465 thumb_record_ld_st_imm_offset, /* 011. */
12466 thumb_record_ld_st_stack, /* 100. */
12467 thumb_record_misc, /* 101. */
12468 thumb_record_ldm_stm_swi, /* 110. */
12469 thumb_record_branch /* 111. */
12472 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12473 uint32_t insn_id = 0;
12475 if (extract_arm_insn (arm_record, insn_size))
12479 printf_unfiltered (_("Process record: error reading memory at "
12480 "addr %s len = %d.\n"),
12481 paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
12485 else if (ARM_RECORD == record_type)
12487 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12488 insn_id = bits (arm_record->arm_insn, 25, 27);
12489 ret = arm_record_extension_space (arm_record);
12490 /* If this insn has fallen into extension space
12491 then we need not decode it anymore. */
12492 if (ret != -1 && !INSN_RECORDED(arm_record))
12494 ret = arm_handle_insn[insn_id] (arm_record);
12497 else if (THUMB_RECORD == record_type)
12499 /* As thumb does not have condition codes, we set negative. */
12500 arm_record->cond = -1;
12501 insn_id = bits (arm_record->arm_insn, 13, 15);
12502 ret = thumb_handle_insn[insn_id] (arm_record);
12504 else if (THUMB2_RECORD == record_type)
12506 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12507 "0x%0x at address %s.\n"),arm_record->arm_insn,
12508 paddress (arm_record->gdbarch,
12509 arm_record->this_addr));
12514 /* Throw assertion. */
12515 gdb_assert_not_reached ("not a valid instruction, could not decode");
12522 /* Cleans up local record registers and memory allocations. */
12525 deallocate_reg_mem (insn_decode_record *record)
12527 xfree (record->arm_regs);
12528 xfree (record->arm_mems);
12532 /* Parse the current instruction and record the values of the registers and
12533 memory that will be changed in current instruction to record_arch_list".
12534 Return -1 if something is wrong. */
12537 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
12538 CORE_ADDR insn_addr)
12541 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
12542 uint32_t no_of_rec = 0;
12543 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
12544 ULONGEST t_bit = 0, insn_id = 0;
12546 ULONGEST u_regval = 0;
12548 insn_decode_record arm_record;
12550 memset (&arm_record, 0, sizeof (insn_decode_record));
12551 arm_record.regcache = regcache;
12552 arm_record.this_addr = insn_addr;
12553 arm_record.gdbarch = gdbarch;
12556 if (record_debug > 1)
12558 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
12560 paddress (gdbarch, arm_record.this_addr));
12563 if (extract_arm_insn (&arm_record, 2))
12567 printf_unfiltered (_("Process record: error reading memory at "
12568 "addr %s len = %d.\n"),
12569 paddress (arm_record.gdbarch,
12570 arm_record.this_addr), 2);
12575 /* Check the insn, whether it is thumb or arm one. */
12577 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
12578 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
12581 if (!(u_regval & t_bit))
12583 /* We are decoding arm insn. */
12584 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
12588 insn_id = bits (arm_record.arm_insn, 11, 15);
12589 /* is it thumb2 insn? */
12590 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
12592 ret = decode_insn (&arm_record, THUMB2_RECORD,
12593 THUMB2_INSN_SIZE_BYTES);
12597 /* We are decoding thumb insn. */
12598 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
12604 /* Record registers. */
12605 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
12606 if (arm_record.arm_regs)
12608 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
12610 if (record_full_arch_list_add_reg
12611 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
12615 /* Record memories. */
12616 if (arm_record.arm_mems)
12618 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
12620 if (record_full_arch_list_add_mem
12621 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
12622 arm_record.arm_mems[no_of_rec].len))
12627 if (record_full_arch_list_add_end ())
12632 deallocate_reg_mem (&arm_record);