1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
63 #include "features/arm/arm-with-m.c"
64 #include "features/arm/arm-with-m-fpa-layout.c"
65 #include "features/arm/arm-with-m-vfp-d16.c"
66 #include "features/arm/arm-with-iwmmxt.c"
67 #include "features/arm/arm-with-vfpv2.c"
68 #include "features/arm/arm-with-vfpv3.c"
69 #include "features/arm/arm-with-neon.c"
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose.
77 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
78 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
80 #define MSYMBOL_SET_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym) = 1
83 #define MSYMBOL_IS_SPECIAL(msym) \
84 MSYMBOL_TARGET_FLAG_1 (msym)
86 /* Per-objfile data used for mapping symbols. */
87 static const struct objfile_data *arm_objfile_data_key;
89 struct arm_mapping_symbol
94 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
95 DEF_VEC_O(arm_mapping_symbol_s);
97 struct arm_per_objfile
99 VEC(arm_mapping_symbol_s) **section_maps;
102 /* The list of available "set arm ..." and "show arm ..." commands. */
103 static struct cmd_list_element *setarmcmdlist = NULL;
104 static struct cmd_list_element *showarmcmdlist = NULL;
106 /* The type of floating-point to use. Keep this in sync with enum
107 arm_float_model, and the help string in _initialize_arm_tdep. */
108 static const char *const fp_model_strings[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
120 static const char *current_fp_model = "auto";
122 /* The ABI to use. Keep this in sync with arm_abi_kind. */
123 static const char *const arm_abi_strings[] =
131 /* A variable that can be configured by the user. */
132 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
133 static const char *arm_abi_string = "auto";
135 /* The execution mode to assume. */
136 static const char *const arm_mode_strings[] =
144 static const char *arm_fallback_mode_string = "auto";
145 static const char *arm_force_mode_string = "auto";
147 /* Number of different reg name sets (options). */
148 static int num_disassembly_options;
150 /* The standard register names, and all the valid aliases for them. Note
151 that `fp', `sp' and `pc' are not added in this alias list, because they
152 have been added as builtin user registers in
153 std-regs.c:_initialize_frame_reg. */
158 } arm_register_aliases[] = {
159 /* Basic register numbers. */
176 /* Synonyms (argument and variable registers). */
189 /* Other platform-specific names for r9. */
195 /* Names used by GCC (not listed in the ARM EABI). */
197 /* A special name from the older ATPCS. */
201 static const char *const arm_register_names[] =
202 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
203 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
204 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
205 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
206 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
207 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
208 "fps", "cpsr" }; /* 24 25 */
210 /* Valid register name styles. */
211 static const char **valid_disassembly_styles;
213 /* Disassembly style to use. Default to "std" register names. */
214 static const char *disassembly_style;
216 /* This is used to keep the bfd arch_info in sync with the disassembly
218 static void set_disassembly_style_sfunc(char *, int,
219 struct cmd_list_element *);
220 static void set_disassembly_style (void);
222 static void convert_from_extended (const struct floatformat *, const void *,
224 static void convert_to_extended (const struct floatformat *, void *,
227 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
228 struct regcache *regcache,
229 int regnum, gdb_byte *buf);
230 static void arm_neon_quad_write (struct gdbarch *gdbarch,
231 struct regcache *regcache,
232 int regnum, const gdb_byte *buf);
235 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self);
238 /* get_next_pcs operations. */
239 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = {
240 arm_get_next_pcs_read_memory_unsigned_integer,
241 arm_get_next_pcs_syscall_next_pc,
242 arm_get_next_pcs_addr_bits_remove,
243 arm_get_next_pcs_is_thumb,
247 struct arm_prologue_cache
249 /* The stack pointer at the time this frame was created; i.e. the
250 caller's stack pointer when this function was called. It is used
251 to identify this frame. */
254 /* The frame base for this frame is just prev_sp - frame size.
255 FRAMESIZE is the distance from the frame pointer to the
256 initial stack pointer. */
260 /* The register used to hold the frame pointer for this frame. */
263 /* Saved register offsets. */
264 struct trad_frame_saved_reg *saved_regs;
267 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
268 CORE_ADDR prologue_start,
269 CORE_ADDR prologue_end,
270 struct arm_prologue_cache *cache);
272 /* Architecture version for displaced stepping. This effects the behaviour of
273 certain instructions, and really should not be hard-wired. */
275 #define DISPLACED_STEPPING_ARCH_VERSION 5
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch *gdbarch)
286 if (gdbarch_tdep (gdbarch)->is_m)
292 /* Determine if the processor is currently executing in Thumb mode. */
295 arm_is_thumb (struct regcache *regcache)
298 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
300 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
302 return (cpsr & t_bit) != 0;
305 /* Determine if FRAME is executing in Thumb mode. */
308 arm_frame_is_thumb (struct frame_info *frame)
311 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
313 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
314 directly (from a signal frame or dummy frame) or by interpreting
315 the saved LR (from a prologue or DWARF frame). So consult it and
316 trust the unwinders. */
317 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
319 return (cpsr & t_bit) != 0;
322 /* Callback for VEC_lower_bound. */
325 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
326 const struct arm_mapping_symbol *rhs)
328 return lhs->value < rhs->value;
331 /* Search for the mapping symbol covering MEMADDR. If one is found,
332 return its type. Otherwise, return 0. If START is non-NULL,
333 set *START to the location of the mapping symbol. */
336 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
338 struct obj_section *sec;
340 /* If there are mapping symbols, consult them. */
341 sec = find_pc_section (memaddr);
344 struct arm_per_objfile *data;
345 VEC(arm_mapping_symbol_s) *map;
346 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
350 data = (struct arm_per_objfile *) objfile_data (sec->objfile,
351 arm_objfile_data_key);
354 map = data->section_maps[sec->the_bfd_section->index];
355 if (!VEC_empty (arm_mapping_symbol_s, map))
357 struct arm_mapping_symbol *map_sym;
359 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
360 arm_compare_mapping_symbols);
362 /* VEC_lower_bound finds the earliest ordered insertion
363 point. If the following symbol starts at this exact
364 address, we use that; otherwise, the preceding
365 mapping symbol covers this address. */
366 if (idx < VEC_length (arm_mapping_symbol_s, map))
368 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
369 if (map_sym->value == map_key.value)
372 *start = map_sym->value + obj_section_addr (sec);
373 return map_sym->type;
379 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
381 *start = map_sym->value + obj_section_addr (sec);
382 return map_sym->type;
391 /* Determine if the program counter specified in MEMADDR is in a Thumb
392 function. This function should be called for addresses unrelated to
393 any executing frame; otherwise, prefer arm_frame_is_thumb. */
396 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
398 struct bound_minimal_symbol sym;
400 struct displaced_step_closure* dsc
401 = get_displaced_step_closure_by_addr(memaddr);
403 /* If checking the mode of displaced instruction in copy area, the mode
404 should be determined by instruction on the original address. */
408 fprintf_unfiltered (gdb_stdlog,
409 "displaced: check mode of %.8lx instead of %.8lx\n",
410 (unsigned long) dsc->insn_addr,
411 (unsigned long) memaddr);
412 memaddr = dsc->insn_addr;
415 /* If bit 0 of the address is set, assume this is a Thumb address. */
416 if (IS_THUMB_ADDR (memaddr))
419 /* If the user wants to override the symbol table, let him. */
420 if (strcmp (arm_force_mode_string, "arm") == 0)
422 if (strcmp (arm_force_mode_string, "thumb") == 0)
425 /* ARM v6-M and v7-M are always in Thumb mode. */
426 if (gdbarch_tdep (gdbarch)->is_m)
429 /* If there are mapping symbols, consult them. */
430 type = arm_find_mapping_symbol (memaddr, NULL);
434 /* Thumb functions have a "special" bit set in minimal symbols. */
435 sym = lookup_minimal_symbol_by_pc (memaddr);
437 return (MSYMBOL_IS_SPECIAL (sym.minsym));
439 /* If the user wants to override the fallback mode, let them. */
440 if (strcmp (arm_fallback_mode_string, "arm") == 0)
442 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
445 /* If we couldn't find any symbol, but we're talking to a running
446 target, then trust the current value of $cpsr. This lets
447 "display/i $pc" always show the correct mode (though if there is
448 a symbol table we will not reach here, so it still may not be
449 displayed in the mode it will be executed). */
450 if (target_has_registers)
451 return arm_frame_is_thumb (get_current_frame ());
453 /* Otherwise we're out of luck; we assume ARM. */
457 /* Determine if the address specified equals any of these magic return
458 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
461 From ARMv6-M Reference Manual B1.5.8
462 Table B1-5 Exception return behavior
464 EXC_RETURN Return To Return Stack
465 0xFFFFFFF1 Handler mode Main
466 0xFFFFFFF9 Thread mode Main
467 0xFFFFFFFD Thread mode Process
469 From ARMv7-M Reference Manual B1.5.8
470 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
472 EXC_RETURN Return To Return Stack
473 0xFFFFFFF1 Handler mode Main
474 0xFFFFFFF9 Thread mode Main
475 0xFFFFFFFD Thread mode Process
477 Table B1-9 EXC_RETURN definition of exception return behavior, with
480 EXC_RETURN Return To Return Stack Frame Type
481 0xFFFFFFE1 Handler mode Main Extended
482 0xFFFFFFE9 Thread mode Main Extended
483 0xFFFFFFED Thread mode Process Extended
484 0xFFFFFFF1 Handler mode Main Basic
485 0xFFFFFFF9 Thread mode Main Basic
486 0xFFFFFFFD Thread mode Process Basic
488 For more details see "B1.5.8 Exception return behavior"
489 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
492 arm_m_addr_is_magic (CORE_ADDR addr)
496 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
497 the exception return behavior. */
504 /* Address is magic. */
508 /* Address is not magic. */
513 /* Remove useless bits from addresses in a running program. */
515 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
517 /* On M-profile devices, do not strip the low bit from EXC_RETURN
518 (the magic exception return address). */
519 if (gdbarch_tdep (gdbarch)->is_m
520 && arm_m_addr_is_magic (val))
524 return UNMAKE_THUMB_ADDR (val);
526 return (val & 0x03fffffc);
529 /* Return 1 if PC is the start of a compiler helper function which
530 can be safely ignored during prologue skipping. IS_THUMB is true
531 if the function is known to be a Thumb function due to the way it
534 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
536 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
537 struct bound_minimal_symbol msym;
539 msym = lookup_minimal_symbol_by_pc (pc);
540 if (msym.minsym != NULL
541 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
542 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
544 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
546 /* The GNU linker's Thumb call stub to foo is named
548 if (strstr (name, "_from_thumb") != NULL)
551 /* On soft-float targets, __truncdfsf2 is called to convert promoted
552 arguments to their argument types in non-prototyped
554 if (startswith (name, "__truncdfsf2"))
556 if (startswith (name, "__aeabi_d2f"))
559 /* Internal functions related to thread-local storage. */
560 if (startswith (name, "__tls_get_addr"))
562 if (startswith (name, "__aeabi_read_tp"))
567 /* If we run against a stripped glibc, we may be unable to identify
568 special functions by name. Check for one important case,
569 __aeabi_read_tp, by comparing the *code* against the default
570 implementation (this is hand-written ARM assembler in glibc). */
573 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
574 == 0xe3e00a0f /* mov r0, #0xffff0fff */
575 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
576 == 0xe240f01f) /* sub pc, r0, #31 */
583 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
584 the first 16-bit of instruction, and INSN2 is the second 16-bit of
586 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
587 ((bits ((insn1), 0, 3) << 12) \
588 | (bits ((insn1), 10, 10) << 11) \
589 | (bits ((insn2), 12, 14) << 8) \
590 | bits ((insn2), 0, 7))
592 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
593 the 32-bit instruction. */
594 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
595 ((bits ((insn), 16, 19) << 12) \
596 | bits ((insn), 0, 11))
598 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
601 thumb_expand_immediate (unsigned int imm)
603 unsigned int count = imm >> 7;
611 return (imm & 0xff) | ((imm & 0xff) << 16);
613 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
615 return (imm & 0xff) | ((imm & 0xff) << 8)
616 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
619 return (0x80 | (imm & 0x7f)) << (32 - count);
622 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
623 epilogue, 0 otherwise. */
626 thumb_instruction_restores_sp (unsigned short insn)
628 return (insn == 0x46bd /* mov sp, r7 */
629 || (insn & 0xff80) == 0xb000 /* add sp, imm */
630 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
633 /* Analyze a Thumb prologue, looking for a recognizable stack frame
634 and frame pointer. Scan until we encounter a store that could
635 clobber the stack frame unexpectedly, or an unknown instruction.
636 Return the last address which is definitely safe to skip for an
637 initial breakpoint. */
640 thumb_analyze_prologue (struct gdbarch *gdbarch,
641 CORE_ADDR start, CORE_ADDR limit,
642 struct arm_prologue_cache *cache)
644 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
645 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
648 struct pv_area *stack;
649 struct cleanup *back_to;
651 CORE_ADDR unrecognized_pc = 0;
653 for (i = 0; i < 16; i++)
654 regs[i] = pv_register (i, 0);
655 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
656 back_to = make_cleanup_free_pv_area (stack);
658 while (start < limit)
662 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
664 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
669 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
672 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
673 whether to save LR (R14). */
674 mask = (insn & 0xff) | ((insn & 0x100) << 6);
676 /* Calculate offsets of saved R0-R7 and LR. */
677 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
678 if (mask & (1 << regno))
680 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
682 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
685 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
687 offset = (insn & 0x7f) << 2; /* get scaled offset */
688 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
691 else if (thumb_instruction_restores_sp (insn))
693 /* Don't scan past the epilogue. */
696 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
697 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
699 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
700 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
701 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
703 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
704 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
705 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
707 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
708 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
709 && pv_is_constant (regs[bits (insn, 3, 5)]))
710 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
711 regs[bits (insn, 6, 8)]);
712 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
713 && pv_is_constant (regs[bits (insn, 3, 6)]))
715 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
716 int rm = bits (insn, 3, 6);
717 regs[rd] = pv_add (regs[rd], regs[rm]);
719 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
721 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
722 int src_reg = (insn & 0x78) >> 3;
723 regs[dst_reg] = regs[src_reg];
725 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
727 /* Handle stores to the stack. Normally pushes are used,
728 but with GCC -mtpcs-frame, there may be other stores
729 in the prologue to create the frame. */
730 int regno = (insn >> 8) & 0x7;
733 offset = (insn & 0xff) << 2;
734 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
736 if (pv_area_store_would_trash (stack, addr))
739 pv_area_store (stack, addr, 4, regs[regno]);
741 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
743 int rd = bits (insn, 0, 2);
744 int rn = bits (insn, 3, 5);
747 offset = bits (insn, 6, 10) << 2;
748 addr = pv_add_constant (regs[rn], offset);
750 if (pv_area_store_would_trash (stack, addr))
753 pv_area_store (stack, addr, 4, regs[rd]);
755 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
756 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
757 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
758 /* Ignore stores of argument registers to the stack. */
760 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
761 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
762 /* Ignore block loads from the stack, potentially copying
763 parameters from memory. */
765 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
766 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
767 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
768 /* Similarly ignore single loads from the stack. */
770 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
771 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
772 /* Skip register copies, i.e. saves to another register
773 instead of the stack. */
775 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
776 /* Recognize constant loads; even with small stacks these are necessary
778 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
779 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
781 /* Constant pool loads, for the same reason. */
782 unsigned int constant;
785 loc = start + 4 + bits (insn, 0, 7) * 4;
786 constant = read_memory_unsigned_integer (loc, 4, byte_order);
787 regs[bits (insn, 8, 10)] = pv_constant (constant);
789 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
791 unsigned short inst2;
793 inst2 = read_memory_unsigned_integer (start + 2, 2,
794 byte_order_for_code);
796 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
798 /* BL, BLX. Allow some special function calls when
799 skipping the prologue; GCC generates these before
800 storing arguments to the stack. */
802 int j1, j2, imm1, imm2;
804 imm1 = sbits (insn, 0, 10);
805 imm2 = bits (inst2, 0, 10);
806 j1 = bit (inst2, 13);
807 j2 = bit (inst2, 11);
809 offset = ((imm1 << 12) + (imm2 << 1));
810 offset ^= ((!j2) << 22) | ((!j1) << 23);
812 nextpc = start + 4 + offset;
813 /* For BLX make sure to clear the low bits. */
814 if (bit (inst2, 12) == 0)
815 nextpc = nextpc & 0xfffffffc;
817 if (!skip_prologue_function (gdbarch, nextpc,
818 bit (inst2, 12) != 0))
822 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
824 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
826 pv_t addr = regs[bits (insn, 0, 3)];
829 if (pv_area_store_would_trash (stack, addr))
832 /* Calculate offsets of saved registers. */
833 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
834 if (inst2 & (1 << regno))
836 addr = pv_add_constant (addr, -4);
837 pv_area_store (stack, addr, 4, regs[regno]);
841 regs[bits (insn, 0, 3)] = addr;
844 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
846 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
848 int regno1 = bits (inst2, 12, 15);
849 int regno2 = bits (inst2, 8, 11);
850 pv_t addr = regs[bits (insn, 0, 3)];
852 offset = inst2 & 0xff;
854 addr = pv_add_constant (addr, offset);
856 addr = pv_add_constant (addr, -offset);
858 if (pv_area_store_would_trash (stack, addr))
861 pv_area_store (stack, addr, 4, regs[regno1]);
862 pv_area_store (stack, pv_add_constant (addr, 4),
866 regs[bits (insn, 0, 3)] = addr;
869 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
870 && (inst2 & 0x0c00) == 0x0c00
871 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
873 int regno = bits (inst2, 12, 15);
874 pv_t addr = regs[bits (insn, 0, 3)];
876 offset = inst2 & 0xff;
878 addr = pv_add_constant (addr, offset);
880 addr = pv_add_constant (addr, -offset);
882 if (pv_area_store_would_trash (stack, addr))
885 pv_area_store (stack, addr, 4, regs[regno]);
888 regs[bits (insn, 0, 3)] = addr;
891 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
892 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
894 int regno = bits (inst2, 12, 15);
897 offset = inst2 & 0xfff;
898 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
900 if (pv_area_store_would_trash (stack, addr))
903 pv_area_store (stack, addr, 4, regs[regno]);
906 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
907 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
908 /* Ignore stores of argument registers to the stack. */
911 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
912 && (inst2 & 0x0d00) == 0x0c00
913 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
914 /* Ignore stores of argument registers to the stack. */
917 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
919 && (inst2 & 0x8000) == 0x0000
920 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
921 /* Ignore block loads from the stack, potentially copying
922 parameters from memory. */
925 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
927 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
928 /* Similarly ignore dual loads from the stack. */
931 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
932 && (inst2 & 0x0d00) == 0x0c00
933 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
934 /* Similarly ignore single loads from the stack. */
937 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
938 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
939 /* Similarly ignore single loads from the stack. */
942 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
943 && (inst2 & 0x8000) == 0x0000)
945 unsigned int imm = ((bits (insn, 10, 10) << 11)
946 | (bits (inst2, 12, 14) << 8)
947 | bits (inst2, 0, 7));
949 regs[bits (inst2, 8, 11)]
950 = pv_add_constant (regs[bits (insn, 0, 3)],
951 thumb_expand_immediate (imm));
954 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
955 && (inst2 & 0x8000) == 0x0000)
957 unsigned int imm = ((bits (insn, 10, 10) << 11)
958 | (bits (inst2, 12, 14) << 8)
959 | bits (inst2, 0, 7));
961 regs[bits (inst2, 8, 11)]
962 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
965 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
966 && (inst2 & 0x8000) == 0x0000)
968 unsigned int imm = ((bits (insn, 10, 10) << 11)
969 | (bits (inst2, 12, 14) << 8)
970 | bits (inst2, 0, 7));
972 regs[bits (inst2, 8, 11)]
973 = pv_add_constant (regs[bits (insn, 0, 3)],
974 - (CORE_ADDR) thumb_expand_immediate (imm));
977 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
978 && (inst2 & 0x8000) == 0x0000)
980 unsigned int imm = ((bits (insn, 10, 10) << 11)
981 | (bits (inst2, 12, 14) << 8)
982 | bits (inst2, 0, 7));
984 regs[bits (inst2, 8, 11)]
985 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
988 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
990 unsigned int imm = ((bits (insn, 10, 10) << 11)
991 | (bits (inst2, 12, 14) << 8)
992 | bits (inst2, 0, 7));
994 regs[bits (inst2, 8, 11)]
995 = pv_constant (thumb_expand_immediate (imm));
998 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1001 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1003 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1006 else if (insn == 0xea5f /* mov.w Rd,Rm */
1007 && (inst2 & 0xf0f0) == 0)
1009 int dst_reg = (inst2 & 0x0f00) >> 8;
1010 int src_reg = inst2 & 0xf;
1011 regs[dst_reg] = regs[src_reg];
1014 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1016 /* Constant pool loads. */
1017 unsigned int constant;
1020 offset = bits (inst2, 0, 11);
1022 loc = start + 4 + offset;
1024 loc = start + 4 - offset;
1026 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1027 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1030 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1032 /* Constant pool loads. */
1033 unsigned int constant;
1036 offset = bits (inst2, 0, 7) << 2;
1038 loc = start + 4 + offset;
1040 loc = start + 4 - offset;
1042 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1043 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1045 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1046 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1049 else if (thumb2_instruction_changes_pc (insn, inst2))
1051 /* Don't scan past anything that might change control flow. */
1056 /* The optimizer might shove anything into the prologue,
1057 so we just skip what we don't recognize. */
1058 unrecognized_pc = start;
1063 else if (thumb_instruction_changes_pc (insn))
1065 /* Don't scan past anything that might change control flow. */
1070 /* The optimizer might shove anything into the prologue,
1071 so we just skip what we don't recognize. */
1072 unrecognized_pc = start;
1079 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1080 paddress (gdbarch, start));
1082 if (unrecognized_pc == 0)
1083 unrecognized_pc = start;
1087 do_cleanups (back_to);
1088 return unrecognized_pc;
1091 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1093 /* Frame pointer is fp. Frame size is constant. */
1094 cache->framereg = ARM_FP_REGNUM;
1095 cache->framesize = -regs[ARM_FP_REGNUM].k;
1097 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1099 /* Frame pointer is r7. Frame size is constant. */
1100 cache->framereg = THUMB_FP_REGNUM;
1101 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1105 /* Try the stack pointer... this is a bit desperate. */
1106 cache->framereg = ARM_SP_REGNUM;
1107 cache->framesize = -regs[ARM_SP_REGNUM].k;
1110 for (i = 0; i < 16; i++)
1111 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1112 cache->saved_regs[i].addr = offset;
1114 do_cleanups (back_to);
1115 return unrecognized_pc;
1119 /* Try to analyze the instructions starting from PC, which load symbol
1120 __stack_chk_guard. Return the address of instruction after loading this
1121 symbol, set the dest register number to *BASEREG, and set the size of
1122 instructions for loading symbol in OFFSET. Return 0 if instructions are
1126 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1127 unsigned int *destreg, int *offset)
1129 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1130 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1131 unsigned int low, high, address;
1136 unsigned short insn1
1137 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1139 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1141 *destreg = bits (insn1, 8, 10);
1143 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1144 address = read_memory_unsigned_integer (address, 4,
1145 byte_order_for_code);
1147 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1149 unsigned short insn2
1150 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1152 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1155 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1157 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1159 /* movt Rd, #const */
1160 if ((insn1 & 0xfbc0) == 0xf2c0)
1162 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1163 *destreg = bits (insn2, 8, 11);
1165 address = (high << 16 | low);
1172 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1174 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1176 address = bits (insn, 0, 11) + pc + 8;
1177 address = read_memory_unsigned_integer (address, 4,
1178 byte_order_for_code);
1180 *destreg = bits (insn, 12, 15);
1183 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1185 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1188 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1190 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1192 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1193 *destreg = bits (insn, 12, 15);
1195 address = (high << 16 | low);
1203 /* Try to skip a sequence of instructions used for stack protector. If PC
1204 points to the first instruction of this sequence, return the address of
1205 first instruction after this sequence, otherwise, return original PC.
1207 On arm, this sequence of instructions is composed of mainly three steps,
1208 Step 1: load symbol __stack_chk_guard,
1209 Step 2: load from address of __stack_chk_guard,
1210 Step 3: store it to somewhere else.
1212 Usually, instructions on step 2 and step 3 are the same on various ARM
1213 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1214 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1215 instructions in step 1 vary from different ARM architectures. On ARMv7,
1218 movw Rn, #:lower16:__stack_chk_guard
1219 movt Rn, #:upper16:__stack_chk_guard
1226 .word __stack_chk_guard
1228 Since ldr/str is a very popular instruction, we can't use them as
1229 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1230 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1231 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1234 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1236 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1237 unsigned int basereg;
1238 struct bound_minimal_symbol stack_chk_guard;
1240 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1243 /* Try to parse the instructions in Step 1. */
1244 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1249 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1250 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1251 Otherwise, this sequence cannot be for stack protector. */
1252 if (stack_chk_guard.minsym == NULL
1253 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1258 unsigned int destreg;
1260 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1262 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1263 if ((insn & 0xf800) != 0x6800)
1265 if (bits (insn, 3, 5) != basereg)
1267 destreg = bits (insn, 0, 2);
1269 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1270 byte_order_for_code);
1271 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1272 if ((insn & 0xf800) != 0x6000)
1274 if (destreg != bits (insn, 0, 2))
1279 unsigned int destreg;
1281 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1283 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1284 if ((insn & 0x0e500000) != 0x04100000)
1286 if (bits (insn, 16, 19) != basereg)
1288 destreg = bits (insn, 12, 15);
1289 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1290 insn = read_memory_unsigned_integer (pc + offset + 4,
1291 4, byte_order_for_code);
1292 if ((insn & 0x0e500000) != 0x04000000)
1294 if (bits (insn, 12, 15) != destreg)
1297 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1300 return pc + offset + 4;
1302 return pc + offset + 8;
1305 /* Advance the PC across any function entry prologue instructions to
1306 reach some "real" code.
1308 The APCS (ARM Procedure Call Standard) defines the following
1312 [stmfd sp!, {a1,a2,a3,a4}]
1313 stmfd sp!, {...,fp,ip,lr,pc}
1314 [stfe f7, [sp, #-12]!]
1315 [stfe f6, [sp, #-12]!]
1316 [stfe f5, [sp, #-12]!]
1317 [stfe f4, [sp, #-12]!]
1318 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1321 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1323 CORE_ADDR func_addr, limit_pc;
1325 /* See if we can determine the end of the prologue via the symbol table.
1326 If so, then return either PC, or the PC after the prologue, whichever
1328 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1330 CORE_ADDR post_prologue_pc
1331 = skip_prologue_using_sal (gdbarch, func_addr);
1332 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1334 if (post_prologue_pc)
1336 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1339 /* GCC always emits a line note before the prologue and another
1340 one after, even if the two are at the same address or on the
1341 same line. Take advantage of this so that we do not need to
1342 know every instruction that might appear in the prologue. We
1343 will have producer information for most binaries; if it is
1344 missing (e.g. for -gstabs), assuming the GNU tools. */
1345 if (post_prologue_pc
1347 || COMPUNIT_PRODUCER (cust) == NULL
1348 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1349 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1350 return post_prologue_pc;
1352 if (post_prologue_pc != 0)
1354 CORE_ADDR analyzed_limit;
1356 /* For non-GCC compilers, make sure the entire line is an
1357 acceptable prologue; GDB will round this function's
1358 return value up to the end of the following line so we
1359 can not skip just part of a line (and we do not want to).
1361 RealView does not treat the prologue specially, but does
1362 associate prologue code with the opening brace; so this
1363 lets us skip the first line if we think it is the opening
1365 if (arm_pc_is_thumb (gdbarch, func_addr))
1366 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1367 post_prologue_pc, NULL);
1369 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1370 post_prologue_pc, NULL);
1372 if (analyzed_limit != post_prologue_pc)
1375 return post_prologue_pc;
1379 /* Can't determine prologue from the symbol table, need to examine
1382 /* Find an upper limit on the function prologue using the debug
1383 information. If the debug information could not be used to provide
1384 that bound, then use an arbitrary large number as the upper bound. */
1385 /* Like arm_scan_prologue, stop no later than pc + 64. */
1386 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1388 limit_pc = pc + 64; /* Magic. */
1391 /* Check if this is Thumb code. */
1392 if (arm_pc_is_thumb (gdbarch, pc))
1393 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1395 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1399 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1400 This function decodes a Thumb function prologue to determine:
1401 1) the size of the stack frame
1402 2) which registers are saved on it
1403 3) the offsets of saved regs
1404 4) the offset from the stack pointer to the frame pointer
1406 A typical Thumb function prologue would create this stack frame
1407 (offsets relative to FP)
1408 old SP -> 24 stack parameters
1411 R7 -> 0 local variables (16 bytes)
1412 SP -> -12 additional stack space (12 bytes)
1413 The frame size would thus be 36 bytes, and the frame offset would be
1414 12 bytes. The frame register is R7.
1416 The comments for thumb_skip_prolog() describe the algorithm we use
1417 to detect the end of the prolog. */
1421 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1422 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1424 CORE_ADDR prologue_start;
1425 CORE_ADDR prologue_end;
1427 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1430 /* See comment in arm_scan_prologue for an explanation of
1432 if (prologue_end > prologue_start + 64)
1434 prologue_end = prologue_start + 64;
1438 /* We're in the boondocks: we have no idea where the start of the
1442 prologue_end = std::min (prologue_end, prev_pc);
1444 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1447 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1451 arm_instruction_restores_sp (unsigned int insn)
1453 if (bits (insn, 28, 31) != INST_NV)
1455 if ((insn & 0x0df0f000) == 0x0080d000
1456 /* ADD SP (register or immediate). */
1457 || (insn & 0x0df0f000) == 0x0040d000
1458 /* SUB SP (register or immediate). */
1459 || (insn & 0x0ffffff0) == 0x01a0d000
1461 || (insn & 0x0fff0000) == 0x08bd0000
1463 || (insn & 0x0fff0000) == 0x049d0000)
1464 /* POP of a single register. */
1471 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1472 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1473 fill it in. Return the first address not recognized as a prologue
1476 We recognize all the instructions typically found in ARM prologues,
1477 plus harmless instructions which can be skipped (either for analysis
1478 purposes, or a more restrictive set that can be skipped when finding
1479 the end of the prologue). */
1482 arm_analyze_prologue (struct gdbarch *gdbarch,
1483 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1484 struct arm_prologue_cache *cache)
1486 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1488 CORE_ADDR offset, current_pc;
1489 pv_t regs[ARM_FPS_REGNUM];
1490 struct pv_area *stack;
1491 struct cleanup *back_to;
1492 CORE_ADDR unrecognized_pc = 0;
1494 /* Search the prologue looking for instructions that set up the
1495 frame pointer, adjust the stack pointer, and save registers.
1497 Be careful, however, and if it doesn't look like a prologue,
1498 don't try to scan it. If, for instance, a frameless function
1499 begins with stmfd sp!, then we will tell ourselves there is
1500 a frame, which will confuse stack traceback, as well as "finish"
1501 and other operations that rely on a knowledge of the stack
1504 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1505 regs[regno] = pv_register (regno, 0);
1506 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1507 back_to = make_cleanup_free_pv_area (stack);
1509 for (current_pc = prologue_start;
1510 current_pc < prologue_end;
1514 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1516 if (insn == 0xe1a0c00d) /* mov ip, sp */
1518 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1521 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1522 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1524 unsigned imm = insn & 0xff; /* immediate value */
1525 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1526 int rd = bits (insn, 12, 15);
1527 imm = (imm >> rot) | (imm << (32 - rot));
1528 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1531 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1532 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1534 unsigned imm = insn & 0xff; /* immediate value */
1535 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1536 int rd = bits (insn, 12, 15);
1537 imm = (imm >> rot) | (imm << (32 - rot));
1538 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1541 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1544 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1546 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1547 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1548 regs[bits (insn, 12, 15)]);
1551 else if ((insn & 0xffff0000) == 0xe92d0000)
1552 /* stmfd sp!, {..., fp, ip, lr, pc}
1554 stmfd sp!, {a1, a2, a3, a4} */
1556 int mask = insn & 0xffff;
1558 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1561 /* Calculate offsets of saved registers. */
1562 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1563 if (mask & (1 << regno))
1566 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1567 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1570 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1571 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1572 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1574 /* No need to add this to saved_regs -- it's just an arg reg. */
1577 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1578 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1579 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1581 /* No need to add this to saved_regs -- it's just an arg reg. */
1584 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1586 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1588 /* No need to add this to saved_regs -- it's just arg regs. */
1591 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1593 unsigned imm = insn & 0xff; /* immediate value */
1594 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1595 imm = (imm >> rot) | (imm << (32 - rot));
1596 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1598 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1600 unsigned imm = insn & 0xff; /* immediate value */
1601 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1602 imm = (imm >> rot) | (imm << (32 - rot));
1603 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1605 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1607 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1609 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1612 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1613 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1614 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1616 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1618 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1620 int n_saved_fp_regs;
1621 unsigned int fp_start_reg, fp_bound_reg;
1623 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1626 if ((insn & 0x800) == 0x800) /* N0 is set */
1628 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1629 n_saved_fp_regs = 3;
1631 n_saved_fp_regs = 1;
1635 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1636 n_saved_fp_regs = 2;
1638 n_saved_fp_regs = 4;
1641 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1642 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1643 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1645 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1646 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1647 regs[fp_start_reg++]);
1650 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1652 /* Allow some special function calls when skipping the
1653 prologue; GCC generates these before storing arguments to
1655 CORE_ADDR dest = BranchDest (current_pc, insn);
1657 if (skip_prologue_function (gdbarch, dest, 0))
1662 else if ((insn & 0xf0000000) != 0xe0000000)
1663 break; /* Condition not true, exit early. */
1664 else if (arm_instruction_changes_pc (insn))
1665 /* Don't scan past anything that might change control flow. */
1667 else if (arm_instruction_restores_sp (insn))
1669 /* Don't scan past the epilogue. */
1672 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1673 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1674 /* Ignore block loads from the stack, potentially copying
1675 parameters from memory. */
1677 else if ((insn & 0xfc500000) == 0xe4100000
1678 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1679 /* Similarly ignore single loads from the stack. */
1681 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1682 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1683 register instead of the stack. */
1687 /* The optimizer might shove anything into the prologue, if
1688 we build up cache (cache != NULL) from scanning prologue,
1689 we just skip what we don't recognize and scan further to
1690 make cache as complete as possible. However, if we skip
1691 prologue, we'll stop immediately on unrecognized
1693 unrecognized_pc = current_pc;
1701 if (unrecognized_pc == 0)
1702 unrecognized_pc = current_pc;
1706 int framereg, framesize;
1708 /* The frame size is just the distance from the frame register
1709 to the original stack pointer. */
1710 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1712 /* Frame pointer is fp. */
1713 framereg = ARM_FP_REGNUM;
1714 framesize = -regs[ARM_FP_REGNUM].k;
1718 /* Try the stack pointer... this is a bit desperate. */
1719 framereg = ARM_SP_REGNUM;
1720 framesize = -regs[ARM_SP_REGNUM].k;
1723 cache->framereg = framereg;
1724 cache->framesize = framesize;
1726 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1727 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1728 cache->saved_regs[regno].addr = offset;
1732 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1733 paddress (gdbarch, unrecognized_pc));
1735 do_cleanups (back_to);
1736 return unrecognized_pc;
1740 arm_scan_prologue (struct frame_info *this_frame,
1741 struct arm_prologue_cache *cache)
1743 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1744 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1745 CORE_ADDR prologue_start, prologue_end;
1746 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1747 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1749 /* Assume there is no frame until proven otherwise. */
1750 cache->framereg = ARM_SP_REGNUM;
1751 cache->framesize = 0;
1753 /* Check for Thumb prologue. */
1754 if (arm_frame_is_thumb (this_frame))
1756 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1760 /* Find the function prologue. If we can't find the function in
1761 the symbol table, peek in the stack frame to find the PC. */
1762 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1765 /* One way to find the end of the prologue (which works well
1766 for unoptimized code) is to do the following:
1768 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1771 prologue_end = prev_pc;
1772 else if (sal.end < prologue_end)
1773 prologue_end = sal.end;
1775 This mechanism is very accurate so long as the optimizer
1776 doesn't move any instructions from the function body into the
1777 prologue. If this happens, sal.end will be the last
1778 instruction in the first hunk of prologue code just before
1779 the first instruction that the scheduler has moved from
1780 the body to the prologue.
1782 In order to make sure that we scan all of the prologue
1783 instructions, we use a slightly less accurate mechanism which
1784 may scan more than necessary. To help compensate for this
1785 lack of accuracy, the prologue scanning loop below contains
1786 several clauses which'll cause the loop to terminate early if
1787 an implausible prologue instruction is encountered.
1793 is a suitable endpoint since it accounts for the largest
1794 possible prologue plus up to five instructions inserted by
1797 if (prologue_end > prologue_start + 64)
1799 prologue_end = prologue_start + 64; /* See above. */
1804 /* We have no symbol information. Our only option is to assume this
1805 function has a standard stack frame and the normal frame register.
1806 Then, we can find the value of our frame pointer on entrance to
1807 the callee (or at the present moment if this is the innermost frame).
1808 The value stored there should be the address of the stmfd + 8. */
1809 CORE_ADDR frame_loc;
1810 LONGEST return_value;
1812 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1813 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1817 prologue_start = gdbarch_addr_bits_remove
1818 (gdbarch, return_value) - 8;
1819 prologue_end = prologue_start + 64; /* See above. */
1823 if (prev_pc < prologue_end)
1824 prologue_end = prev_pc;
1826 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1829 static struct arm_prologue_cache *
1830 arm_make_prologue_cache (struct frame_info *this_frame)
1833 struct arm_prologue_cache *cache;
1834 CORE_ADDR unwound_fp;
1836 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1837 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1839 arm_scan_prologue (this_frame, cache);
1841 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1842 if (unwound_fp == 0)
1845 cache->prev_sp = unwound_fp + cache->framesize;
1847 /* Calculate actual addresses of saved registers using offsets
1848 determined by arm_scan_prologue. */
1849 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1850 if (trad_frame_addr_p (cache->saved_regs, reg))
1851 cache->saved_regs[reg].addr += cache->prev_sp;
1856 /* Implementation of the stop_reason hook for arm_prologue frames. */
1858 static enum unwind_stop_reason
1859 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
1862 struct arm_prologue_cache *cache;
1865 if (*this_cache == NULL)
1866 *this_cache = arm_make_prologue_cache (this_frame);
1867 cache = (struct arm_prologue_cache *) *this_cache;
1869 /* This is meant to halt the backtrace at "_start". */
1870 pc = get_frame_pc (this_frame);
1871 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1872 return UNWIND_OUTERMOST;
1874 /* If we've hit a wall, stop. */
1875 if (cache->prev_sp == 0)
1876 return UNWIND_OUTERMOST;
1878 return UNWIND_NO_REASON;
1881 /* Our frame ID for a normal frame is the current function's starting PC
1882 and the caller's SP when we were called. */
1885 arm_prologue_this_id (struct frame_info *this_frame,
1887 struct frame_id *this_id)
1889 struct arm_prologue_cache *cache;
1893 if (*this_cache == NULL)
1894 *this_cache = arm_make_prologue_cache (this_frame);
1895 cache = (struct arm_prologue_cache *) *this_cache;
1897 /* Use function start address as part of the frame ID. If we cannot
1898 identify the start address (due to missing symbol information),
1899 fall back to just using the current PC. */
1900 pc = get_frame_pc (this_frame);
1901 func = get_frame_func (this_frame);
1905 id = frame_id_build (cache->prev_sp, func);
1909 static struct value *
1910 arm_prologue_prev_register (struct frame_info *this_frame,
1914 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1915 struct arm_prologue_cache *cache;
1917 if (*this_cache == NULL)
1918 *this_cache = arm_make_prologue_cache (this_frame);
1919 cache = (struct arm_prologue_cache *) *this_cache;
1921 /* If we are asked to unwind the PC, then we need to return the LR
1922 instead. The prologue may save PC, but it will point into this
1923 frame's prologue, not the next frame's resume location. Also
1924 strip the saved T bit. A valid LR may have the low bit set, but
1925 a valid PC never does. */
1926 if (prev_regnum == ARM_PC_REGNUM)
1930 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1931 return frame_unwind_got_constant (this_frame, prev_regnum,
1932 arm_addr_bits_remove (gdbarch, lr));
1935 /* SP is generally not saved to the stack, but this frame is
1936 identified by the next frame's stack pointer at the time of the call.
1937 The value was already reconstructed into PREV_SP. */
1938 if (prev_regnum == ARM_SP_REGNUM)
1939 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1941 /* The CPSR may have been changed by the call instruction and by the
1942 called function. The only bit we can reconstruct is the T bit,
1943 by checking the low bit of LR as of the call. This is a reliable
1944 indicator of Thumb-ness except for some ARM v4T pre-interworking
1945 Thumb code, which could get away with a clear low bit as long as
1946 the called function did not use bx. Guess that all other
1947 bits are unchanged; the condition flags are presumably lost,
1948 but the processor status is likely valid. */
1949 if (prev_regnum == ARM_PS_REGNUM)
1952 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
1954 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1955 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1956 if (IS_THUMB_ADDR (lr))
1960 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1963 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1967 struct frame_unwind arm_prologue_unwind = {
1969 arm_prologue_unwind_stop_reason,
1970 arm_prologue_this_id,
1971 arm_prologue_prev_register,
1973 default_frame_sniffer
1976 /* Maintain a list of ARM exception table entries per objfile, similar to the
1977 list of mapping symbols. We only cache entries for standard ARM-defined
1978 personality routines; the cache will contain only the frame unwinding
1979 instructions associated with the entry (not the descriptors). */
1981 static const struct objfile_data *arm_exidx_data_key;
1983 struct arm_exidx_entry
1988 typedef struct arm_exidx_entry arm_exidx_entry_s;
1989 DEF_VEC_O(arm_exidx_entry_s);
1991 struct arm_exidx_data
1993 VEC(arm_exidx_entry_s) **section_maps;
1997 arm_exidx_data_free (struct objfile *objfile, void *arg)
1999 struct arm_exidx_data *data = (struct arm_exidx_data *) arg;
2002 for (i = 0; i < objfile->obfd->section_count; i++)
2003 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2007 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2008 const struct arm_exidx_entry *rhs)
2010 return lhs->addr < rhs->addr;
2013 static struct obj_section *
2014 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2016 struct obj_section *osect;
2018 ALL_OBJFILE_OSECTIONS (objfile, osect)
2019 if (bfd_get_section_flags (objfile->obfd,
2020 osect->the_bfd_section) & SEC_ALLOC)
2022 bfd_vma start, size;
2023 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2024 size = bfd_get_section_size (osect->the_bfd_section);
2026 if (start <= vma && vma < start + size)
2033 /* Parse contents of exception table and exception index sections
2034 of OBJFILE, and fill in the exception table entry cache.
2036 For each entry that refers to a standard ARM-defined personality
2037 routine, extract the frame unwinding instructions (from either
2038 the index or the table section). The unwinding instructions
2040 - extracting them from the rest of the table data
2041 - converting to host endianness
2042 - appending the implicit 0xb0 ("Finish") code
2044 The extracted and normalized instructions are stored for later
2045 retrieval by the arm_find_exidx_entry routine. */
2048 arm_exidx_new_objfile (struct objfile *objfile)
2050 struct cleanup *cleanups;
2051 struct arm_exidx_data *data;
2052 asection *exidx, *extab;
2053 bfd_vma exidx_vma = 0, extab_vma = 0;
2054 bfd_size_type exidx_size = 0, extab_size = 0;
2055 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2058 /* If we've already touched this file, do nothing. */
2059 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2061 cleanups = make_cleanup (null_cleanup, NULL);
2063 /* Read contents of exception table and index. */
2064 exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
2067 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2068 exidx_size = bfd_get_section_size (exidx);
2069 exidx_data = (gdb_byte *) xmalloc (exidx_size);
2070 make_cleanup (xfree, exidx_data);
2072 if (!bfd_get_section_contents (objfile->obfd, exidx,
2073 exidx_data, 0, exidx_size))
2075 do_cleanups (cleanups);
2080 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2083 extab_vma = bfd_section_vma (objfile->obfd, extab);
2084 extab_size = bfd_get_section_size (extab);
2085 extab_data = (gdb_byte *) xmalloc (extab_size);
2086 make_cleanup (xfree, extab_data);
2088 if (!bfd_get_section_contents (objfile->obfd, extab,
2089 extab_data, 0, extab_size))
2091 do_cleanups (cleanups);
2096 /* Allocate exception table data structure. */
2097 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2098 set_objfile_data (objfile, arm_exidx_data_key, data);
2099 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2100 objfile->obfd->section_count,
2101 VEC(arm_exidx_entry_s) *);
2103 /* Fill in exception table. */
2104 for (i = 0; i < exidx_size / 8; i++)
2106 struct arm_exidx_entry new_exidx_entry;
2107 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2108 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2109 bfd_vma addr = 0, word = 0;
2110 int n_bytes = 0, n_words = 0;
2111 struct obj_section *sec;
2112 gdb_byte *entry = NULL;
2114 /* Extract address of start of function. */
2115 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2116 idx += exidx_vma + i * 8;
2118 /* Find section containing function and compute section offset. */
2119 sec = arm_obj_section_from_vma (objfile, idx);
2122 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2124 /* Determine address of exception table entry. */
2127 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2129 else if ((val & 0xff000000) == 0x80000000)
2131 /* Exception table entry embedded in .ARM.exidx
2132 -- must be short form. */
2136 else if (!(val & 0x80000000))
2138 /* Exception table entry in .ARM.extab. */
2139 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2140 addr += exidx_vma + i * 8 + 4;
2142 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2144 word = bfd_h_get_32 (objfile->obfd,
2145 extab_data + addr - extab_vma);
2148 if ((word & 0xff000000) == 0x80000000)
2153 else if ((word & 0xff000000) == 0x81000000
2154 || (word & 0xff000000) == 0x82000000)
2158 n_words = ((word >> 16) & 0xff);
2160 else if (!(word & 0x80000000))
2163 struct obj_section *pers_sec;
2164 int gnu_personality = 0;
2166 /* Custom personality routine. */
2167 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2168 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2170 /* Check whether we've got one of the variants of the
2171 GNU personality routines. */
2172 pers_sec = arm_obj_section_from_vma (objfile, pers);
2175 static const char *personality[] =
2177 "__gcc_personality_v0",
2178 "__gxx_personality_v0",
2179 "__gcj_personality_v0",
2180 "__gnu_objc_personality_v0",
2184 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2187 for (k = 0; personality[k]; k++)
2188 if (lookup_minimal_symbol_by_pc_name
2189 (pc, personality[k], objfile))
2191 gnu_personality = 1;
2196 /* If so, the next word contains a word count in the high
2197 byte, followed by the same unwind instructions as the
2198 pre-defined forms. */
2200 && addr + 4 <= extab_vma + extab_size)
2202 word = bfd_h_get_32 (objfile->obfd,
2203 extab_data + addr - extab_vma);
2206 n_words = ((word >> 24) & 0xff);
2212 /* Sanity check address. */
2214 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2215 n_words = n_bytes = 0;
2217 /* The unwind instructions reside in WORD (only the N_BYTES least
2218 significant bytes are valid), followed by N_WORDS words in the
2219 extab section starting at ADDR. */
2220 if (n_bytes || n_words)
2223 = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack,
2224 n_bytes + n_words * 4 + 1);
2227 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2231 word = bfd_h_get_32 (objfile->obfd,
2232 extab_data + addr - extab_vma);
2235 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2236 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2237 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2238 *p++ = (gdb_byte) (word & 0xff);
2241 /* Implied "Finish" to terminate the list. */
2245 /* Push entry onto vector. They are guaranteed to always
2246 appear in order of increasing addresses. */
2247 new_exidx_entry.addr = idx;
2248 new_exidx_entry.entry = entry;
2249 VEC_safe_push (arm_exidx_entry_s,
2250 data->section_maps[sec->the_bfd_section->index],
2254 do_cleanups (cleanups);
2257 /* Search for the exception table entry covering MEMADDR. If one is found,
2258 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2259 set *START to the start of the region covered by this entry. */
2262 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2264 struct obj_section *sec;
2266 sec = find_pc_section (memaddr);
2269 struct arm_exidx_data *data;
2270 VEC(arm_exidx_entry_s) *map;
2271 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2274 data = ((struct arm_exidx_data *)
2275 objfile_data (sec->objfile, arm_exidx_data_key));
2278 map = data->section_maps[sec->the_bfd_section->index];
2279 if (!VEC_empty (arm_exidx_entry_s, map))
2281 struct arm_exidx_entry *map_sym;
2283 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2284 arm_compare_exidx_entries);
2286 /* VEC_lower_bound finds the earliest ordered insertion
2287 point. If the following symbol starts at this exact
2288 address, we use that; otherwise, the preceding
2289 exception table entry covers this address. */
2290 if (idx < VEC_length (arm_exidx_entry_s, map))
2292 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2293 if (map_sym->addr == map_key.addr)
2296 *start = map_sym->addr + obj_section_addr (sec);
2297 return map_sym->entry;
2303 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2305 *start = map_sym->addr + obj_section_addr (sec);
2306 return map_sym->entry;
2315 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2316 instruction list from the ARM exception table entry ENTRY, allocate and
2317 return a prologue cache structure describing how to unwind this frame.
2319 Return NULL if the unwinding instruction list contains a "spare",
2320 "reserved" or "refuse to unwind" instruction as defined in section
2321 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2322 for the ARM Architecture" document. */
2324 static struct arm_prologue_cache *
2325 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2330 struct arm_prologue_cache *cache;
2331 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2332 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2338 /* Whenever we reload SP, we actually have to retrieve its
2339 actual value in the current frame. */
2342 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2344 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2345 vsp = get_frame_register_unsigned (this_frame, reg);
2349 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2350 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2356 /* Decode next unwind instruction. */
2359 if ((insn & 0xc0) == 0)
2361 int offset = insn & 0x3f;
2362 vsp += (offset << 2) + 4;
2364 else if ((insn & 0xc0) == 0x40)
2366 int offset = insn & 0x3f;
2367 vsp -= (offset << 2) + 4;
2369 else if ((insn & 0xf0) == 0x80)
2371 int mask = ((insn & 0xf) << 8) | *entry++;
2374 /* The special case of an all-zero mask identifies
2375 "Refuse to unwind". We return NULL to fall back
2376 to the prologue analyzer. */
2380 /* Pop registers r4..r15 under mask. */
2381 for (i = 0; i < 12; i++)
2382 if (mask & (1 << i))
2384 cache->saved_regs[4 + i].addr = vsp;
2388 /* Special-case popping SP -- we need to reload vsp. */
2389 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2392 else if ((insn & 0xf0) == 0x90)
2394 int reg = insn & 0xf;
2396 /* Reserved cases. */
2397 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2400 /* Set SP from another register and mark VSP for reload. */
2401 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2404 else if ((insn & 0xf0) == 0xa0)
2406 int count = insn & 0x7;
2407 int pop_lr = (insn & 0x8) != 0;
2410 /* Pop r4..r[4+count]. */
2411 for (i = 0; i <= count; i++)
2413 cache->saved_regs[4 + i].addr = vsp;
2417 /* If indicated by flag, pop LR as well. */
2420 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2424 else if (insn == 0xb0)
2426 /* We could only have updated PC by popping into it; if so, it
2427 will show up as address. Otherwise, copy LR into PC. */
2428 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2429 cache->saved_regs[ARM_PC_REGNUM]
2430 = cache->saved_regs[ARM_LR_REGNUM];
2435 else if (insn == 0xb1)
2437 int mask = *entry++;
2440 /* All-zero mask and mask >= 16 is "spare". */
2441 if (mask == 0 || mask >= 16)
2444 /* Pop r0..r3 under mask. */
2445 for (i = 0; i < 4; i++)
2446 if (mask & (1 << i))
2448 cache->saved_regs[i].addr = vsp;
2452 else if (insn == 0xb2)
2454 ULONGEST offset = 0;
2459 offset |= (*entry & 0x7f) << shift;
2462 while (*entry++ & 0x80);
2464 vsp += 0x204 + (offset << 2);
2466 else if (insn == 0xb3)
2468 int start = *entry >> 4;
2469 int count = (*entry++) & 0xf;
2472 /* Only registers D0..D15 are valid here. */
2473 if (start + count >= 16)
2476 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2477 for (i = 0; i <= count; i++)
2479 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2483 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2486 else if ((insn & 0xf8) == 0xb8)
2488 int count = insn & 0x7;
2491 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2492 for (i = 0; i <= count; i++)
2494 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2498 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2501 else if (insn == 0xc6)
2503 int start = *entry >> 4;
2504 int count = (*entry++) & 0xf;
2507 /* Only registers WR0..WR15 are valid. */
2508 if (start + count >= 16)
2511 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2512 for (i = 0; i <= count; i++)
2514 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2518 else if (insn == 0xc7)
2520 int mask = *entry++;
2523 /* All-zero mask and mask >= 16 is "spare". */
2524 if (mask == 0 || mask >= 16)
2527 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2528 for (i = 0; i < 4; i++)
2529 if (mask & (1 << i))
2531 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2535 else if ((insn & 0xf8) == 0xc0)
2537 int count = insn & 0x7;
2540 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2541 for (i = 0; i <= count; i++)
2543 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2547 else if (insn == 0xc8)
2549 int start = *entry >> 4;
2550 int count = (*entry++) & 0xf;
2553 /* Only registers D0..D31 are valid. */
2554 if (start + count >= 16)
2557 /* Pop VFP double-precision registers
2558 D[16+start]..D[16+start+count]. */
2559 for (i = 0; i <= count; i++)
2561 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2565 else if (insn == 0xc9)
2567 int start = *entry >> 4;
2568 int count = (*entry++) & 0xf;
2571 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2572 for (i = 0; i <= count; i++)
2574 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2578 else if ((insn & 0xf8) == 0xd0)
2580 int count = insn & 0x7;
2583 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2584 for (i = 0; i <= count; i++)
2586 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2592 /* Everything else is "spare". */
2597 /* If we restore SP from a register, assume this was the frame register.
2598 Otherwise just fall back to SP as frame register. */
2599 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2600 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2602 cache->framereg = ARM_SP_REGNUM;
2604 /* Determine offset to previous frame. */
2606 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2608 /* We already got the previous SP. */
2609 cache->prev_sp = vsp;
2614 /* Unwinding via ARM exception table entries. Note that the sniffer
2615 already computes a filled-in prologue cache, which is then used
2616 with the same arm_prologue_this_id and arm_prologue_prev_register
2617 routines also used for prologue-parsing based unwinding. */
2620 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2621 struct frame_info *this_frame,
2622 void **this_prologue_cache)
2624 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2625 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2626 CORE_ADDR addr_in_block, exidx_region, func_start;
2627 struct arm_prologue_cache *cache;
2630 /* See if we have an ARM exception table entry covering this address. */
2631 addr_in_block = get_frame_address_in_block (this_frame);
2632 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2636 /* The ARM exception table does not describe unwind information
2637 for arbitrary PC values, but is guaranteed to be correct only
2638 at call sites. We have to decide here whether we want to use
2639 ARM exception table information for this frame, or fall back
2640 to using prologue parsing. (Note that if we have DWARF CFI,
2641 this sniffer isn't even called -- CFI is always preferred.)
2643 Before we make this decision, however, we check whether we
2644 actually have *symbol* information for the current frame.
2645 If not, prologue parsing would not work anyway, so we might
2646 as well use the exception table and hope for the best. */
2647 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2651 /* If the next frame is "normal", we are at a call site in this
2652 frame, so exception information is guaranteed to be valid. */
2653 if (get_next_frame (this_frame)
2654 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2657 /* We also assume exception information is valid if we're currently
2658 blocked in a system call. The system library is supposed to
2659 ensure this, so that e.g. pthread cancellation works. */
2660 if (arm_frame_is_thumb (this_frame))
2664 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2665 byte_order_for_code, &insn)
2666 && (insn & 0xff00) == 0xdf00 /* svc */)
2673 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2674 byte_order_for_code, &insn)
2675 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2679 /* Bail out if we don't know that exception information is valid. */
2683 /* The ARM exception index does not mark the *end* of the region
2684 covered by the entry, and some functions will not have any entry.
2685 To correctly recognize the end of the covered region, the linker
2686 should have inserted dummy records with a CANTUNWIND marker.
2688 Unfortunately, current versions of GNU ld do not reliably do
2689 this, and thus we may have found an incorrect entry above.
2690 As a (temporary) sanity check, we only use the entry if it
2691 lies *within* the bounds of the function. Note that this check
2692 might reject perfectly valid entries that just happen to cover
2693 multiple functions; therefore this check ought to be removed
2694 once the linker is fixed. */
2695 if (func_start > exidx_region)
2699 /* Decode the list of unwinding instructions into a prologue cache.
2700 Note that this may fail due to e.g. a "refuse to unwind" code. */
2701 cache = arm_exidx_fill_cache (this_frame, entry);
2705 *this_prologue_cache = cache;
2709 struct frame_unwind arm_exidx_unwind = {
2711 default_frame_unwind_stop_reason,
2712 arm_prologue_this_id,
2713 arm_prologue_prev_register,
2715 arm_exidx_unwind_sniffer
2718 static struct arm_prologue_cache *
2719 arm_make_epilogue_frame_cache (struct frame_info *this_frame)
2721 struct arm_prologue_cache *cache;
2724 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2725 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2727 /* Still rely on the offset calculated from prologue. */
2728 arm_scan_prologue (this_frame, cache);
2730 /* Since we are in epilogue, the SP has been restored. */
2731 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2733 /* Calculate actual addresses of saved registers using offsets
2734 determined by arm_scan_prologue. */
2735 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2736 if (trad_frame_addr_p (cache->saved_regs, reg))
2737 cache->saved_regs[reg].addr += cache->prev_sp;
2742 /* Implementation of function hook 'this_id' in
2743 'struct frame_uwnind' for epilogue unwinder. */
2746 arm_epilogue_frame_this_id (struct frame_info *this_frame,
2748 struct frame_id *this_id)
2750 struct arm_prologue_cache *cache;
2753 if (*this_cache == NULL)
2754 *this_cache = arm_make_epilogue_frame_cache (this_frame);
2755 cache = (struct arm_prologue_cache *) *this_cache;
2757 /* Use function start address as part of the frame ID. If we cannot
2758 identify the start address (due to missing symbol information),
2759 fall back to just using the current PC. */
2760 pc = get_frame_pc (this_frame);
2761 func = get_frame_func (this_frame);
2765 (*this_id) = frame_id_build (cache->prev_sp, pc);
2768 /* Implementation of function hook 'prev_register' in
2769 'struct frame_uwnind' for epilogue unwinder. */
2771 static struct value *
2772 arm_epilogue_frame_prev_register (struct frame_info *this_frame,
2773 void **this_cache, int regnum)
2775 if (*this_cache == NULL)
2776 *this_cache = arm_make_epilogue_frame_cache (this_frame);
2778 return arm_prologue_prev_register (this_frame, this_cache, regnum);
2781 static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch,
2783 static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch,
2786 /* Implementation of function hook 'sniffer' in
2787 'struct frame_uwnind' for epilogue unwinder. */
2790 arm_epilogue_frame_sniffer (const struct frame_unwind *self,
2791 struct frame_info *this_frame,
2792 void **this_prologue_cache)
2794 if (frame_relative_level (this_frame) == 0)
2796 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2797 CORE_ADDR pc = get_frame_pc (this_frame);
2799 if (arm_frame_is_thumb (this_frame))
2800 return thumb_stack_frame_destroyed_p (gdbarch, pc);
2802 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
2808 /* Frame unwinder from epilogue. */
2810 static const struct frame_unwind arm_epilogue_frame_unwind =
2813 default_frame_unwind_stop_reason,
2814 arm_epilogue_frame_this_id,
2815 arm_epilogue_frame_prev_register,
2817 arm_epilogue_frame_sniffer,
2820 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2821 trampoline, return the target PC. Otherwise return 0.
2823 void call0a (char c, short s, int i, long l) {}
2827 (*pointer_to_call0a) (c, s, i, l);
2830 Instead of calling a stub library function _call_via_xx (xx is
2831 the register name), GCC may inline the trampoline in the object
2832 file as below (register r2 has the address of call0a).
2835 .type main, %function
2844 The trampoline 'bx r2' doesn't belong to main. */
2847 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2849 /* The heuristics of recognizing such trampoline is that FRAME is
2850 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2851 if (arm_frame_is_thumb (frame))
2855 if (target_read_memory (pc, buf, 2) == 0)
2857 struct gdbarch *gdbarch = get_frame_arch (frame);
2858 enum bfd_endian byte_order_for_code
2859 = gdbarch_byte_order_for_code (gdbarch);
2861 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2863 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2866 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2868 /* Clear the LSB so that gdb core sets step-resume
2869 breakpoint at the right address. */
2870 return UNMAKE_THUMB_ADDR (dest);
2878 static struct arm_prologue_cache *
2879 arm_make_stub_cache (struct frame_info *this_frame)
2881 struct arm_prologue_cache *cache;
2883 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2884 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2886 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2891 /* Our frame ID for a stub frame is the current SP and LR. */
2894 arm_stub_this_id (struct frame_info *this_frame,
2896 struct frame_id *this_id)
2898 struct arm_prologue_cache *cache;
2900 if (*this_cache == NULL)
2901 *this_cache = arm_make_stub_cache (this_frame);
2902 cache = (struct arm_prologue_cache *) *this_cache;
2904 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2908 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2909 struct frame_info *this_frame,
2910 void **this_prologue_cache)
2912 CORE_ADDR addr_in_block;
2914 CORE_ADDR pc, start_addr;
2917 addr_in_block = get_frame_address_in_block (this_frame);
2918 pc = get_frame_pc (this_frame);
2919 if (in_plt_section (addr_in_block)
2920 /* We also use the stub winder if the target memory is unreadable
2921 to avoid having the prologue unwinder trying to read it. */
2922 || target_read_memory (pc, dummy, 4) != 0)
2925 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2926 && arm_skip_bx_reg (this_frame, pc) != 0)
2932 struct frame_unwind arm_stub_unwind = {
2934 default_frame_unwind_stop_reason,
2936 arm_prologue_prev_register,
2938 arm_stub_unwind_sniffer
2941 /* Put here the code to store, into CACHE->saved_regs, the addresses
2942 of the saved registers of frame described by THIS_FRAME. CACHE is
2945 static struct arm_prologue_cache *
2946 arm_m_exception_cache (struct frame_info *this_frame)
2948 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2949 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2950 struct arm_prologue_cache *cache;
2951 CORE_ADDR unwound_sp;
2954 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2955 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2957 unwound_sp = get_frame_register_unsigned (this_frame,
2960 /* The hardware saves eight 32-bit words, comprising xPSR,
2961 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2962 "B1.5.6 Exception entry behavior" in
2963 "ARMv7-M Architecture Reference Manual". */
2964 cache->saved_regs[0].addr = unwound_sp;
2965 cache->saved_regs[1].addr = unwound_sp + 4;
2966 cache->saved_regs[2].addr = unwound_sp + 8;
2967 cache->saved_regs[3].addr = unwound_sp + 12;
2968 cache->saved_regs[12].addr = unwound_sp + 16;
2969 cache->saved_regs[14].addr = unwound_sp + 20;
2970 cache->saved_regs[15].addr = unwound_sp + 24;
2971 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2973 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2974 aligner between the top of the 32-byte stack frame and the
2975 previous context's stack pointer. */
2976 cache->prev_sp = unwound_sp + 32;
2977 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2978 && (xpsr & (1 << 9)) != 0)
2979 cache->prev_sp += 4;
2984 /* Implementation of function hook 'this_id' in
2985 'struct frame_uwnind'. */
2988 arm_m_exception_this_id (struct frame_info *this_frame,
2990 struct frame_id *this_id)
2992 struct arm_prologue_cache *cache;
2994 if (*this_cache == NULL)
2995 *this_cache = arm_m_exception_cache (this_frame);
2996 cache = (struct arm_prologue_cache *) *this_cache;
2998 /* Our frame ID for a stub frame is the current SP and LR. */
2999 *this_id = frame_id_build (cache->prev_sp,
3000 get_frame_pc (this_frame));
3003 /* Implementation of function hook 'prev_register' in
3004 'struct frame_uwnind'. */
3006 static struct value *
3007 arm_m_exception_prev_register (struct frame_info *this_frame,
3011 struct arm_prologue_cache *cache;
3013 if (*this_cache == NULL)
3014 *this_cache = arm_m_exception_cache (this_frame);
3015 cache = (struct arm_prologue_cache *) *this_cache;
3017 /* The value was already reconstructed into PREV_SP. */
3018 if (prev_regnum == ARM_SP_REGNUM)
3019 return frame_unwind_got_constant (this_frame, prev_regnum,
3022 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3026 /* Implementation of function hook 'sniffer' in
3027 'struct frame_uwnind'. */
3030 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3031 struct frame_info *this_frame,
3032 void **this_prologue_cache)
3034 CORE_ADDR this_pc = get_frame_pc (this_frame);
3036 /* No need to check is_m; this sniffer is only registered for
3037 M-profile architectures. */
3039 /* Check if exception frame returns to a magic PC value. */
3040 return arm_m_addr_is_magic (this_pc);
3043 /* Frame unwinder for M-profile exceptions. */
3045 struct frame_unwind arm_m_exception_unwind =
3048 default_frame_unwind_stop_reason,
3049 arm_m_exception_this_id,
3050 arm_m_exception_prev_register,
3052 arm_m_exception_unwind_sniffer
3056 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3058 struct arm_prologue_cache *cache;
3060 if (*this_cache == NULL)
3061 *this_cache = arm_make_prologue_cache (this_frame);
3062 cache = (struct arm_prologue_cache *) *this_cache;
3064 return cache->prev_sp - cache->framesize;
3067 struct frame_base arm_normal_base = {
3068 &arm_prologue_unwind,
3069 arm_normal_frame_base,
3070 arm_normal_frame_base,
3071 arm_normal_frame_base
3074 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3075 dummy frame. The frame ID's base needs to match the TOS value
3076 saved by save_dummy_frame_tos() and returned from
3077 arm_push_dummy_call, and the PC needs to match the dummy frame's
3080 static struct frame_id
3081 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3083 return frame_id_build (get_frame_register_unsigned (this_frame,
3085 get_frame_pc (this_frame));
3088 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3089 be used to construct the previous frame's ID, after looking up the
3090 containing function). */
3093 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3096 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3097 return arm_addr_bits_remove (gdbarch, pc);
3101 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3103 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3106 static struct value *
3107 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3110 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3112 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3117 /* The PC is normally copied from the return column, which
3118 describes saves of LR. However, that version may have an
3119 extra bit set to indicate Thumb state. The bit is not
3121 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3122 return frame_unwind_got_constant (this_frame, regnum,
3123 arm_addr_bits_remove (gdbarch, lr));
3126 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3127 cpsr = get_frame_register_unsigned (this_frame, regnum);
3128 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3129 if (IS_THUMB_ADDR (lr))
3133 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3136 internal_error (__FILE__, __LINE__,
3137 _("Unexpected register %d"), regnum);
3142 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3143 struct dwarf2_frame_state_reg *reg,
3144 struct frame_info *this_frame)
3150 reg->how = DWARF2_FRAME_REG_FN;
3151 reg->loc.fn = arm_dwarf2_prev_register;
3154 reg->how = DWARF2_FRAME_REG_CFA;
3159 /* Implement the stack_frame_destroyed_p gdbarch method. */
3162 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3164 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3165 unsigned int insn, insn2;
3166 int found_return = 0, found_stack_adjust = 0;
3167 CORE_ADDR func_start, func_end;
3171 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3174 /* The epilogue is a sequence of instructions along the following lines:
3176 - add stack frame size to SP or FP
3177 - [if frame pointer used] restore SP from FP
3178 - restore registers from SP [may include PC]
3179 - a return-type instruction [if PC wasn't already restored]
3181 In a first pass, we scan forward from the current PC and verify the
3182 instructions we find as compatible with this sequence, ending in a
3185 However, this is not sufficient to distinguish indirect function calls
3186 within a function from indirect tail calls in the epilogue in some cases.
3187 Therefore, if we didn't already find any SP-changing instruction during
3188 forward scan, we add a backward scanning heuristic to ensure we actually
3189 are in the epilogue. */
3192 while (scan_pc < func_end && !found_return)
3194 if (target_read_memory (scan_pc, buf, 2))
3198 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3200 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3202 else if (insn == 0x46f7) /* mov pc, lr */
3204 else if (thumb_instruction_restores_sp (insn))
3206 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3209 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3211 if (target_read_memory (scan_pc, buf, 2))
3215 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3217 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3219 if (insn2 & 0x8000) /* <registers> include PC. */
3222 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3223 && (insn2 & 0x0fff) == 0x0b04)
3225 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3228 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3229 && (insn2 & 0x0e00) == 0x0a00)
3241 /* Since any instruction in the epilogue sequence, with the possible
3242 exception of return itself, updates the stack pointer, we need to
3243 scan backwards for at most one instruction. Try either a 16-bit or
3244 a 32-bit instruction. This is just a heuristic, so we do not worry
3245 too much about false positives. */
3247 if (pc - 4 < func_start)
3249 if (target_read_memory (pc - 4, buf, 4))
3252 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3253 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3255 if (thumb_instruction_restores_sp (insn2))
3256 found_stack_adjust = 1;
3257 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3258 found_stack_adjust = 1;
3259 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3260 && (insn2 & 0x0fff) == 0x0b04)
3261 found_stack_adjust = 1;
3262 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3263 && (insn2 & 0x0e00) == 0x0a00)
3264 found_stack_adjust = 1;
3266 return found_stack_adjust;
3270 arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc)
3272 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3275 CORE_ADDR func_start, func_end;
3277 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3280 /* We are in the epilogue if the previous instruction was a stack
3281 adjustment and the next instruction is a possible return (bx, mov
3282 pc, or pop). We could have to scan backwards to find the stack
3283 adjustment, or forwards to find the return, but this is a decent
3284 approximation. First scan forwards. */
3287 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3288 if (bits (insn, 28, 31) != INST_NV)
3290 if ((insn & 0x0ffffff0) == 0x012fff10)
3293 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3296 else if ((insn & 0x0fff0000) == 0x08bd0000
3297 && (insn & 0x0000c000) != 0)
3298 /* POP (LDMIA), including PC or LR. */
3305 /* Scan backwards. This is just a heuristic, so do not worry about
3306 false positives from mode changes. */
3308 if (pc < func_start + 4)
3311 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3312 if (arm_instruction_restores_sp (insn))
3318 /* Implement the stack_frame_destroyed_p gdbarch method. */
3321 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3323 if (arm_pc_is_thumb (gdbarch, pc))
3324 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3326 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
3329 /* When arguments must be pushed onto the stack, they go on in reverse
3330 order. The code below implements a FILO (stack) to do this. */
3335 struct stack_item *prev;
3339 static struct stack_item *
3340 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
3342 struct stack_item *si;
3343 si = XNEW (struct stack_item);
3344 si->data = (gdb_byte *) xmalloc (len);
3347 memcpy (si->data, contents, len);
3351 static struct stack_item *
3352 pop_stack_item (struct stack_item *si)
3354 struct stack_item *dead = si;
3362 /* Return the alignment (in bytes) of the given type. */
3365 arm_type_align (struct type *t)
3371 t = check_typedef (t);
3372 switch (TYPE_CODE (t))
3375 /* Should never happen. */
3376 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3380 case TYPE_CODE_ENUM:
3384 case TYPE_CODE_RANGE:
3386 case TYPE_CODE_CHAR:
3387 case TYPE_CODE_BOOL:
3388 return TYPE_LENGTH (t);
3390 case TYPE_CODE_ARRAY:
3391 if (TYPE_VECTOR (t))
3393 /* Use the natural alignment for vector types (the same for
3394 scalar type), but the maximum alignment is 64-bit. */
3395 if (TYPE_LENGTH (t) > 8)
3398 return TYPE_LENGTH (t);
3401 return arm_type_align (TYPE_TARGET_TYPE (t));
3402 case TYPE_CODE_COMPLEX:
3403 return arm_type_align (TYPE_TARGET_TYPE (t));
3405 case TYPE_CODE_STRUCT:
3406 case TYPE_CODE_UNION:
3408 for (n = 0; n < TYPE_NFIELDS (t); n++)
3410 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3418 /* Possible base types for a candidate for passing and returning in
3421 enum arm_vfp_cprc_base_type
3430 /* The length of one element of base type B. */
3433 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3437 case VFP_CPRC_SINGLE:
3439 case VFP_CPRC_DOUBLE:
3441 case VFP_CPRC_VEC64:
3443 case VFP_CPRC_VEC128:
3446 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3451 /* The character ('s', 'd' or 'q') for the type of VFP register used
3452 for passing base type B. */
3455 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3459 case VFP_CPRC_SINGLE:
3461 case VFP_CPRC_DOUBLE:
3463 case VFP_CPRC_VEC64:
3465 case VFP_CPRC_VEC128:
3468 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3473 /* Determine whether T may be part of a candidate for passing and
3474 returning in VFP registers, ignoring the limit on the total number
3475 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3476 classification of the first valid component found; if it is not
3477 VFP_CPRC_UNKNOWN, all components must have the same classification
3478 as *BASE_TYPE. If it is found that T contains a type not permitted
3479 for passing and returning in VFP registers, a type differently
3480 classified from *BASE_TYPE, or two types differently classified
3481 from each other, return -1, otherwise return the total number of
3482 base-type elements found (possibly 0 in an empty structure or
3483 array). Vector types are not currently supported, matching the
3484 generic AAPCS support. */
3487 arm_vfp_cprc_sub_candidate (struct type *t,
3488 enum arm_vfp_cprc_base_type *base_type)
3490 t = check_typedef (t);
3491 switch (TYPE_CODE (t))
3494 switch (TYPE_LENGTH (t))
3497 if (*base_type == VFP_CPRC_UNKNOWN)
3498 *base_type = VFP_CPRC_SINGLE;
3499 else if (*base_type != VFP_CPRC_SINGLE)
3504 if (*base_type == VFP_CPRC_UNKNOWN)
3505 *base_type = VFP_CPRC_DOUBLE;
3506 else if (*base_type != VFP_CPRC_DOUBLE)
3515 case TYPE_CODE_COMPLEX:
3516 /* Arguments of complex T where T is one of the types float or
3517 double get treated as if they are implemented as:
3526 switch (TYPE_LENGTH (t))
3529 if (*base_type == VFP_CPRC_UNKNOWN)
3530 *base_type = VFP_CPRC_SINGLE;
3531 else if (*base_type != VFP_CPRC_SINGLE)
3536 if (*base_type == VFP_CPRC_UNKNOWN)
3537 *base_type = VFP_CPRC_DOUBLE;
3538 else if (*base_type != VFP_CPRC_DOUBLE)
3547 case TYPE_CODE_ARRAY:
3549 if (TYPE_VECTOR (t))
3551 /* A 64-bit or 128-bit containerized vector type are VFP
3553 switch (TYPE_LENGTH (t))
3556 if (*base_type == VFP_CPRC_UNKNOWN)
3557 *base_type = VFP_CPRC_VEC64;
3560 if (*base_type == VFP_CPRC_UNKNOWN)
3561 *base_type = VFP_CPRC_VEC128;
3572 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t),
3576 if (TYPE_LENGTH (t) == 0)
3578 gdb_assert (count == 0);
3581 else if (count == 0)
3583 unitlen = arm_vfp_cprc_unit_length (*base_type);
3584 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3585 return TYPE_LENGTH (t) / unitlen;
3590 case TYPE_CODE_STRUCT:
3595 for (i = 0; i < TYPE_NFIELDS (t); i++)
3599 if (!field_is_static (&TYPE_FIELD (t, i)))
3600 sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3602 if (sub_count == -1)
3606 if (TYPE_LENGTH (t) == 0)
3608 gdb_assert (count == 0);
3611 else if (count == 0)
3613 unitlen = arm_vfp_cprc_unit_length (*base_type);
3614 if (TYPE_LENGTH (t) != unitlen * count)
3619 case TYPE_CODE_UNION:
3624 for (i = 0; i < TYPE_NFIELDS (t); i++)
3626 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3628 if (sub_count == -1)
3630 count = (count > sub_count ? count : sub_count);
3632 if (TYPE_LENGTH (t) == 0)
3634 gdb_assert (count == 0);
3637 else if (count == 0)
3639 unitlen = arm_vfp_cprc_unit_length (*base_type);
3640 if (TYPE_LENGTH (t) != unitlen * count)
3652 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3653 if passed to or returned from a non-variadic function with the VFP
3654 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3655 *BASE_TYPE to the base type for T and *COUNT to the number of
3656 elements of that base type before returning. */
3659 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3662 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3663 int c = arm_vfp_cprc_sub_candidate (t, &b);
3664 if (c <= 0 || c > 4)
3671 /* Return 1 if the VFP ABI should be used for passing arguments to and
3672 returning values from a function of type FUNC_TYPE, 0
3676 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3678 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3679 /* Variadic functions always use the base ABI. Assume that functions
3680 without debug info are not variadic. */
3681 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3683 /* The VFP ABI is only supported as a variant of AAPCS. */
3684 if (tdep->arm_abi != ARM_ABI_AAPCS)
3686 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3689 /* We currently only support passing parameters in integer registers, which
3690 conforms with GCC's default model, and VFP argument passing following
3691 the VFP variant of AAPCS. Several other variants exist and
3692 we should probably support some of them based on the selected ABI. */
3695 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3696 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3697 struct value **args, CORE_ADDR sp, int struct_return,
3698 CORE_ADDR struct_addr)
3700 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3704 struct stack_item *si = NULL;
3707 unsigned vfp_regs_free = (1 << 16) - 1;
3709 /* Determine the type of this function and whether the VFP ABI
3711 ftype = check_typedef (value_type (function));
3712 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3713 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3714 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3716 /* Set the return address. For the ARM, the return breakpoint is
3717 always at BP_ADDR. */
3718 if (arm_pc_is_thumb (gdbarch, bp_addr))
3720 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3722 /* Walk through the list of args and determine how large a temporary
3723 stack is required. Need to take care here as structs may be
3724 passed on the stack, and we have to push them. */
3727 argreg = ARM_A1_REGNUM;
3730 /* The struct_return pointer occupies the first parameter
3731 passing register. */
3735 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3736 gdbarch_register_name (gdbarch, argreg),
3737 paddress (gdbarch, struct_addr));
3738 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3742 for (argnum = 0; argnum < nargs; argnum++)
3745 struct type *arg_type;
3746 struct type *target_type;
3747 enum type_code typecode;
3748 const bfd_byte *val;
3750 enum arm_vfp_cprc_base_type vfp_base_type;
3752 int may_use_core_reg = 1;
3754 arg_type = check_typedef (value_type (args[argnum]));
3755 len = TYPE_LENGTH (arg_type);
3756 target_type = TYPE_TARGET_TYPE (arg_type);
3757 typecode = TYPE_CODE (arg_type);
3758 val = value_contents (args[argnum]);
3760 align = arm_type_align (arg_type);
3761 /* Round alignment up to a whole number of words. */
3762 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3763 /* Different ABIs have different maximum alignments. */
3764 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3766 /* The APCS ABI only requires word alignment. */
3767 align = INT_REGISTER_SIZE;
3771 /* The AAPCS requires at most doubleword alignment. */
3772 if (align > INT_REGISTER_SIZE * 2)
3773 align = INT_REGISTER_SIZE * 2;
3777 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3785 /* Because this is a CPRC it cannot go in a core register or
3786 cause a core register to be skipped for alignment.
3787 Either it goes in VFP registers and the rest of this loop
3788 iteration is skipped for this argument, or it goes on the
3789 stack (and the stack alignment code is correct for this
3791 may_use_core_reg = 0;
3793 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3794 shift = unit_length / 4;
3795 mask = (1 << (shift * vfp_base_count)) - 1;
3796 for (regno = 0; regno < 16; regno += shift)
3797 if (((vfp_regs_free >> regno) & mask) == mask)
3806 vfp_regs_free &= ~(mask << regno);
3807 reg_scaled = regno / shift;
3808 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3809 for (i = 0; i < vfp_base_count; i++)
3813 if (reg_char == 'q')
3814 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3815 val + i * unit_length);
3818 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3819 reg_char, reg_scaled + i);
3820 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3822 regcache_cooked_write (regcache, regnum,
3823 val + i * unit_length);
3830 /* This CPRC could not go in VFP registers, so all VFP
3831 registers are now marked as used. */
3836 /* Push stack padding for dowubleword alignment. */
3837 if (nstack & (align - 1))
3839 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3840 nstack += INT_REGISTER_SIZE;
3843 /* Doubleword aligned quantities must go in even register pairs. */
3844 if (may_use_core_reg
3845 && argreg <= ARM_LAST_ARG_REGNUM
3846 && align > INT_REGISTER_SIZE
3850 /* If the argument is a pointer to a function, and it is a
3851 Thumb function, create a LOCAL copy of the value and set
3852 the THUMB bit in it. */
3853 if (TYPE_CODE_PTR == typecode
3854 && target_type != NULL
3855 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3857 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3858 if (arm_pc_is_thumb (gdbarch, regval))
3860 bfd_byte *copy = (bfd_byte *) alloca (len);
3861 store_unsigned_integer (copy, len, byte_order,
3862 MAKE_THUMB_ADDR (regval));
3867 /* Copy the argument to general registers or the stack in
3868 register-sized pieces. Large arguments are split between
3869 registers and stack. */
3872 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3874 = extract_unsigned_integer (val, partial_len, byte_order);
3876 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3878 /* The argument is being passed in a general purpose
3880 if (byte_order == BFD_ENDIAN_BIG)
3881 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3883 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3885 gdbarch_register_name
3887 phex (regval, INT_REGISTER_SIZE));
3888 regcache_cooked_write_unsigned (regcache, argreg, regval);
3893 gdb_byte buf[INT_REGISTER_SIZE];
3895 memset (buf, 0, sizeof (buf));
3896 store_unsigned_integer (buf, partial_len, byte_order, regval);
3898 /* Push the arguments onto the stack. */
3900 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3902 si = push_stack_item (si, buf, INT_REGISTER_SIZE);
3903 nstack += INT_REGISTER_SIZE;
3910 /* If we have an odd number of words to push, then decrement the stack
3911 by one word now, so first stack argument will be dword aligned. */
3918 write_memory (sp, si->data, si->len);
3919 si = pop_stack_item (si);
3922 /* Finally, update teh SP register. */
3923 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3929 /* Always align the frame to an 8-byte boundary. This is required on
3930 some platforms and harmless on the rest. */
3933 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3935 /* Align the stack to eight bytes. */
3936 return sp & ~ (CORE_ADDR) 7;
3940 print_fpu_flags (struct ui_file *file, int flags)
3942 if (flags & (1 << 0))
3943 fputs_filtered ("IVO ", file);
3944 if (flags & (1 << 1))
3945 fputs_filtered ("DVZ ", file);
3946 if (flags & (1 << 2))
3947 fputs_filtered ("OFL ", file);
3948 if (flags & (1 << 3))
3949 fputs_filtered ("UFL ", file);
3950 if (flags & (1 << 4))
3951 fputs_filtered ("INX ", file);
3952 fputc_filtered ('\n', file);
3955 /* Print interesting information about the floating point processor
3956 (if present) or emulator. */
3958 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3959 struct frame_info *frame, const char *args)
3961 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3964 type = (status >> 24) & 127;
3965 if (status & (1 << 31))
3966 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3968 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3969 /* i18n: [floating point unit] mask */
3970 fputs_filtered (_("mask: "), file);
3971 print_fpu_flags (file, status >> 16);
3972 /* i18n: [floating point unit] flags */
3973 fputs_filtered (_("flags: "), file);
3974 print_fpu_flags (file, status);
3977 /* Construct the ARM extended floating point type. */
3978 static struct type *
3979 arm_ext_type (struct gdbarch *gdbarch)
3981 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3983 if (!tdep->arm_ext_type)
3985 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3986 floatformats_arm_ext);
3988 return tdep->arm_ext_type;
3991 static struct type *
3992 arm_neon_double_type (struct gdbarch *gdbarch)
3994 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3996 if (tdep->neon_double_type == NULL)
3998 struct type *t, *elem;
4000 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
4002 elem = builtin_type (gdbarch)->builtin_uint8;
4003 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
4004 elem = builtin_type (gdbarch)->builtin_uint16;
4005 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
4006 elem = builtin_type (gdbarch)->builtin_uint32;
4007 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
4008 elem = builtin_type (gdbarch)->builtin_uint64;
4009 append_composite_type_field (t, "u64", elem);
4010 elem = builtin_type (gdbarch)->builtin_float;
4011 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
4012 elem = builtin_type (gdbarch)->builtin_double;
4013 append_composite_type_field (t, "f64", elem);
4015 TYPE_VECTOR (t) = 1;
4016 TYPE_NAME (t) = "neon_d";
4017 tdep->neon_double_type = t;
4020 return tdep->neon_double_type;
4023 /* FIXME: The vector types are not correctly ordered on big-endian
4024 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4025 bits of d0 - regardless of what unit size is being held in d0. So
4026 the offset of the first uint8 in d0 is 7, but the offset of the
4027 first float is 4. This code works as-is for little-endian
4030 static struct type *
4031 arm_neon_quad_type (struct gdbarch *gdbarch)
4033 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4035 if (tdep->neon_quad_type == NULL)
4037 struct type *t, *elem;
4039 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4041 elem = builtin_type (gdbarch)->builtin_uint8;
4042 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4043 elem = builtin_type (gdbarch)->builtin_uint16;
4044 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4045 elem = builtin_type (gdbarch)->builtin_uint32;
4046 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4047 elem = builtin_type (gdbarch)->builtin_uint64;
4048 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4049 elem = builtin_type (gdbarch)->builtin_float;
4050 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4051 elem = builtin_type (gdbarch)->builtin_double;
4052 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4054 TYPE_VECTOR (t) = 1;
4055 TYPE_NAME (t) = "neon_q";
4056 tdep->neon_quad_type = t;
4059 return tdep->neon_quad_type;
4062 /* Return the GDB type object for the "standard" data type of data in
4065 static struct type *
4066 arm_register_type (struct gdbarch *gdbarch, int regnum)
4068 int num_regs = gdbarch_num_regs (gdbarch);
4070 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4071 && regnum >= num_regs && regnum < num_regs + 32)
4072 return builtin_type (gdbarch)->builtin_float;
4074 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4075 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4076 return arm_neon_quad_type (gdbarch);
4078 /* If the target description has register information, we are only
4079 in this function so that we can override the types of
4080 double-precision registers for NEON. */
4081 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4083 struct type *t = tdesc_register_type (gdbarch, regnum);
4085 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4086 && TYPE_CODE (t) == TYPE_CODE_FLT
4087 && gdbarch_tdep (gdbarch)->have_neon)
4088 return arm_neon_double_type (gdbarch);
4093 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4095 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4096 return builtin_type (gdbarch)->builtin_void;
4098 return arm_ext_type (gdbarch);
4100 else if (regnum == ARM_SP_REGNUM)
4101 return builtin_type (gdbarch)->builtin_data_ptr;
4102 else if (regnum == ARM_PC_REGNUM)
4103 return builtin_type (gdbarch)->builtin_func_ptr;
4104 else if (regnum >= ARRAY_SIZE (arm_register_names))
4105 /* These registers are only supported on targets which supply
4106 an XML description. */
4107 return builtin_type (gdbarch)->builtin_int0;
4109 return builtin_type (gdbarch)->builtin_uint32;
4112 /* Map a DWARF register REGNUM onto the appropriate GDB register
4116 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4118 /* Core integer regs. */
4119 if (reg >= 0 && reg <= 15)
4122 /* Legacy FPA encoding. These were once used in a way which
4123 overlapped with VFP register numbering, so their use is
4124 discouraged, but GDB doesn't support the ARM toolchain
4125 which used them for VFP. */
4126 if (reg >= 16 && reg <= 23)
4127 return ARM_F0_REGNUM + reg - 16;
4129 /* New assignments for the FPA registers. */
4130 if (reg >= 96 && reg <= 103)
4131 return ARM_F0_REGNUM + reg - 96;
4133 /* WMMX register assignments. */
4134 if (reg >= 104 && reg <= 111)
4135 return ARM_WCGR0_REGNUM + reg - 104;
4137 if (reg >= 112 && reg <= 127)
4138 return ARM_WR0_REGNUM + reg - 112;
4140 if (reg >= 192 && reg <= 199)
4141 return ARM_WC0_REGNUM + reg - 192;
4143 /* VFP v2 registers. A double precision value is actually
4144 in d1 rather than s2, but the ABI only defines numbering
4145 for the single precision registers. This will "just work"
4146 in GDB for little endian targets (we'll read eight bytes,
4147 starting in s0 and then progressing to s1), but will be
4148 reversed on big endian targets with VFP. This won't
4149 be a problem for the new Neon quad registers; you're supposed
4150 to use DW_OP_piece for those. */
4151 if (reg >= 64 && reg <= 95)
4155 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4156 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4160 /* VFP v3 / Neon registers. This range is also used for VFP v2
4161 registers, except that it now describes d0 instead of s0. */
4162 if (reg >= 256 && reg <= 287)
4166 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4167 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4174 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4176 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4179 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4181 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4182 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4184 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4185 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4187 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4188 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4190 if (reg < NUM_GREGS)
4191 return SIM_ARM_R0_REGNUM + reg;
4194 if (reg < NUM_FREGS)
4195 return SIM_ARM_FP0_REGNUM + reg;
4198 if (reg < NUM_SREGS)
4199 return SIM_ARM_FPS_REGNUM + reg;
4202 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4205 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4206 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4207 It is thought that this is is the floating-point register format on
4208 little-endian systems. */
4211 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4212 void *dbl, int endianess)
4216 if (endianess == BFD_ENDIAN_BIG)
4217 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4219 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4221 floatformat_from_doublest (fmt, &d, dbl);
4225 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4230 floatformat_to_doublest (fmt, ptr, &d);
4231 if (endianess == BFD_ENDIAN_BIG)
4232 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4234 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4238 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4239 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4240 NULL if an error occurs. BUF is freed. */
4243 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4244 int old_len, int new_len)
4247 int bytes_to_read = new_len - old_len;
4249 new_buf = (gdb_byte *) xmalloc (new_len);
4250 memcpy (new_buf + bytes_to_read, buf, old_len);
4252 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4260 /* An IT block is at most the 2-byte IT instruction followed by
4261 four 4-byte instructions. The furthest back we must search to
4262 find an IT block that affects the current instruction is thus
4263 2 + 3 * 4 == 14 bytes. */
4264 #define MAX_IT_BLOCK_PREFIX 14
4266 /* Use a quick scan if there are more than this many bytes of
4268 #define IT_SCAN_THRESHOLD 32
4270 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4271 A breakpoint in an IT block may not be hit, depending on the
4274 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4278 CORE_ADDR boundary, func_start;
4280 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4281 int i, any, last_it, last_it_count;
4283 /* If we are using BKPT breakpoints, none of this is necessary. */
4284 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4287 /* ARM mode does not have this problem. */
4288 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4291 /* We are setting a breakpoint in Thumb code that could potentially
4292 contain an IT block. The first step is to find how much Thumb
4293 code there is; we do not need to read outside of known Thumb
4295 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4297 /* Thumb-2 code must have mapping symbols to have a chance. */
4300 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4302 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4303 && func_start > boundary)
4304 boundary = func_start;
4306 /* Search for a candidate IT instruction. We have to do some fancy
4307 footwork to distinguish a real IT instruction from the second
4308 half of a 32-bit instruction, but there is no need for that if
4309 there's no candidate. */
4310 buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX);
4312 /* No room for an IT instruction. */
4315 buf = (gdb_byte *) xmalloc (buf_len);
4316 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4319 for (i = 0; i < buf_len; i += 2)
4321 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4322 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4335 /* OK, the code bytes before this instruction contain at least one
4336 halfword which resembles an IT instruction. We know that it's
4337 Thumb code, but there are still two possibilities. Either the
4338 halfword really is an IT instruction, or it is the second half of
4339 a 32-bit Thumb instruction. The only way we can tell is to
4340 scan forwards from a known instruction boundary. */
4341 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
4345 /* There's a lot of code before this instruction. Start with an
4346 optimistic search; it's easy to recognize halfwords that can
4347 not be the start of a 32-bit instruction, and use that to
4348 lock on to the instruction boundaries. */
4349 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
4352 buf_len = IT_SCAN_THRESHOLD;
4355 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
4357 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4358 if (thumb_insn_size (inst1) == 2)
4365 /* At this point, if DEFINITE, BUF[I] is the first place we
4366 are sure that we know the instruction boundaries, and it is far
4367 enough from BPADDR that we could not miss an IT instruction
4368 affecting BPADDR. If ! DEFINITE, give up - start from a
4372 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
4376 buf_len = bpaddr - boundary;
4382 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4385 buf_len = bpaddr - boundary;
4389 /* Scan forwards. Find the last IT instruction before BPADDR. */
4394 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4396 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4401 else if (inst1 & 0x0002)
4403 else if (inst1 & 0x0004)
4408 i += thumb_insn_size (inst1);
4414 /* There wasn't really an IT instruction after all. */
4417 if (last_it_count < 1)
4418 /* It was too far away. */
4421 /* This really is a trouble spot. Move the breakpoint to the IT
4423 return bpaddr - buf_len + last_it;
4426 /* ARM displaced stepping support.
4428 Generally ARM displaced stepping works as follows:
4430 1. When an instruction is to be single-stepped, it is first decoded by
4431 arm_process_displaced_insn. Depending on the type of instruction, it is
4432 then copied to a scratch location, possibly in a modified form. The
4433 copy_* set of functions performs such modification, as necessary. A
4434 breakpoint is placed after the modified instruction in the scratch space
4435 to return control to GDB. Note in particular that instructions which
4436 modify the PC will no longer do so after modification.
4438 2. The instruction is single-stepped, by setting the PC to the scratch
4439 location address, and resuming. Control returns to GDB when the
4442 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4443 function used for the current instruction. This function's job is to
4444 put the CPU/memory state back to what it would have been if the
4445 instruction had been executed unmodified in its original location. */
4447 /* NOP instruction (mov r0, r0). */
4448 #define ARM_NOP 0xe1a00000
4449 #define THUMB_NOP 0x4600
4451 /* Helper for register reads for displaced stepping. In particular, this
4452 returns the PC as it would be seen by the instruction at its original
4456 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4460 CORE_ADDR from = dsc->insn_addr;
4462 if (regno == ARM_PC_REGNUM)
4464 /* Compute pipeline offset:
4465 - When executing an ARM instruction, PC reads as the address of the
4466 current instruction plus 8.
4467 - When executing a Thumb instruction, PC reads as the address of the
4468 current instruction plus 4. */
4475 if (debug_displaced)
4476 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
4477 (unsigned long) from);
4478 return (ULONGEST) from;
4482 regcache_cooked_read_unsigned (regs, regno, &ret);
4483 if (debug_displaced)
4484 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
4485 regno, (unsigned long) ret);
4491 displaced_in_arm_mode (struct regcache *regs)
4494 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4496 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4498 return (ps & t_bit) == 0;
4501 /* Write to the PC as from a branch instruction. */
4504 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4508 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4509 architecture versions < 6. */
4510 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4511 val & ~(ULONGEST) 0x3);
4513 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4514 val & ~(ULONGEST) 0x1);
4517 /* Write to the PC as from a branch-exchange instruction. */
4520 bx_write_pc (struct regcache *regs, ULONGEST val)
4523 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4525 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4529 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
4530 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
4532 else if ((val & 2) == 0)
4534 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4535 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
4539 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4540 mode, align dest to 4 bytes). */
4541 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4542 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4543 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
4547 /* Write to the PC as if from a load instruction. */
4550 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4553 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
4554 bx_write_pc (regs, val);
4556 branch_write_pc (regs, dsc, val);
4559 /* Write to the PC as if from an ALU instruction. */
4562 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4565 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
4566 bx_write_pc (regs, val);
4568 branch_write_pc (regs, dsc, val);
4571 /* Helper for writing to registers for displaced stepping. Writing to the PC
4572 has a varying effects depending on the instruction which does the write:
4573 this is controlled by the WRITE_PC argument. */
4576 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4577 int regno, ULONGEST val, enum pc_write_style write_pc)
4579 if (regno == ARM_PC_REGNUM)
4581 if (debug_displaced)
4582 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
4583 (unsigned long) val);
4586 case BRANCH_WRITE_PC:
4587 branch_write_pc (regs, dsc, val);
4591 bx_write_pc (regs, val);
4595 load_write_pc (regs, dsc, val);
4599 alu_write_pc (regs, dsc, val);
4602 case CANNOT_WRITE_PC:
4603 warning (_("Instruction wrote to PC in an unexpected way when "
4604 "single-stepping"));
4608 internal_error (__FILE__, __LINE__,
4609 _("Invalid argument to displaced_write_reg"));
4612 dsc->wrote_to_pc = 1;
4616 if (debug_displaced)
4617 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
4618 regno, (unsigned long) val);
4619 regcache_cooked_write_unsigned (regs, regno, val);
4623 /* This function is used to concisely determine if an instruction INSN
4624 references PC. Register fields of interest in INSN should have the
4625 corresponding fields of BITMASK set to 0b1111. The function
4626 returns return 1 if any of these fields in INSN reference the PC
4627 (also 0b1111, r15), else it returns 0. */
4630 insn_references_pc (uint32_t insn, uint32_t bitmask)
4632 uint32_t lowbit = 1;
4634 while (bitmask != 0)
4638 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
4644 mask = lowbit * 0xf;
4646 if ((insn & mask) == mask)
4655 /* The simplest copy function. Many instructions have the same effect no
4656 matter what address they are executed at: in those cases, use this. */
4659 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
4660 const char *iname, struct displaced_step_closure *dsc)
4662 if (debug_displaced)
4663 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
4664 "opcode/class '%s' unmodified\n", (unsigned long) insn,
4667 dsc->modinsn[0] = insn;
4673 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
4674 uint16_t insn2, const char *iname,
4675 struct displaced_step_closure *dsc)
4677 if (debug_displaced)
4678 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
4679 "opcode/class '%s' unmodified\n", insn1, insn2,
4682 dsc->modinsn[0] = insn1;
4683 dsc->modinsn[1] = insn2;
4689 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4692 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn,
4694 struct displaced_step_closure *dsc)
4696 if (debug_displaced)
4697 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
4698 "opcode/class '%s' unmodified\n", insn,
4701 dsc->modinsn[0] = insn;
4706 /* Preload instructions with immediate offset. */
4709 cleanup_preload (struct gdbarch *gdbarch,
4710 struct regcache *regs, struct displaced_step_closure *dsc)
4712 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4713 if (!dsc->u.preload.immed)
4714 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4718 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
4719 struct displaced_step_closure *dsc, unsigned int rn)
4722 /* Preload instructions:
4724 {pli/pld} [rn, #+/-imm]
4726 {pli/pld} [r0, #+/-imm]. */
4728 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4729 rn_val = displaced_read_reg (regs, dsc, rn);
4730 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4731 dsc->u.preload.immed = 1;
4733 dsc->cleanup = &cleanup_preload;
4737 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4738 struct displaced_step_closure *dsc)
4740 unsigned int rn = bits (insn, 16, 19);
4742 if (!insn_references_pc (insn, 0x000f0000ul))
4743 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
4745 if (debug_displaced)
4746 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4747 (unsigned long) insn);
4749 dsc->modinsn[0] = insn & 0xfff0ffff;
4751 install_preload (gdbarch, regs, dsc, rn);
4757 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
4758 struct regcache *regs, struct displaced_step_closure *dsc)
4760 unsigned int rn = bits (insn1, 0, 3);
4761 unsigned int u_bit = bit (insn1, 7);
4762 int imm12 = bits (insn2, 0, 11);
4765 if (rn != ARM_PC_REGNUM)
4766 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
4768 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4769 PLD (literal) Encoding T1. */
4770 if (debug_displaced)
4771 fprintf_unfiltered (gdb_stdlog,
4772 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4773 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
4779 /* Rewrite instruction {pli/pld} PC imm12 into:
4780 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4784 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4786 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4787 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4789 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
4791 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
4792 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
4793 dsc->u.preload.immed = 0;
4795 /* {pli/pld} [r0, r1] */
4796 dsc->modinsn[0] = insn1 & 0xfff0;
4797 dsc->modinsn[1] = 0xf001;
4800 dsc->cleanup = &cleanup_preload;
4804 /* Preload instructions with register offset. */
4807 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
4808 struct displaced_step_closure *dsc, unsigned int rn,
4811 ULONGEST rn_val, rm_val;
4813 /* Preload register-offset instructions:
4815 {pli/pld} [rn, rm {, shift}]
4817 {pli/pld} [r0, r1 {, shift}]. */
4819 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4820 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4821 rn_val = displaced_read_reg (regs, dsc, rn);
4822 rm_val = displaced_read_reg (regs, dsc, rm);
4823 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4824 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
4825 dsc->u.preload.immed = 0;
4827 dsc->cleanup = &cleanup_preload;
4831 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
4832 struct regcache *regs,
4833 struct displaced_step_closure *dsc)
4835 unsigned int rn = bits (insn, 16, 19);
4836 unsigned int rm = bits (insn, 0, 3);
4839 if (!insn_references_pc (insn, 0x000f000ful))
4840 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
4842 if (debug_displaced)
4843 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4844 (unsigned long) insn);
4846 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
4848 install_preload_reg (gdbarch, regs, dsc, rn, rm);
4852 /* Copy/cleanup coprocessor load and store instructions. */
4855 cleanup_copro_load_store (struct gdbarch *gdbarch,
4856 struct regcache *regs,
4857 struct displaced_step_closure *dsc)
4859 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
4861 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4863 if (dsc->u.ldst.writeback)
4864 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
4868 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
4869 struct displaced_step_closure *dsc,
4870 int writeback, unsigned int rn)
4874 /* Coprocessor load/store instructions:
4876 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4878 {stc/stc2} [r0, #+/-imm].
4880 ldc/ldc2 are handled identically. */
4882 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4883 rn_val = displaced_read_reg (regs, dsc, rn);
4884 /* PC should be 4-byte aligned. */
4885 rn_val = rn_val & 0xfffffffc;
4886 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4888 dsc->u.ldst.writeback = writeback;
4889 dsc->u.ldst.rn = rn;
4891 dsc->cleanup = &cleanup_copro_load_store;
4895 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
4896 struct regcache *regs,
4897 struct displaced_step_closure *dsc)
4899 unsigned int rn = bits (insn, 16, 19);
4901 if (!insn_references_pc (insn, 0x000f0000ul))
4902 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
4904 if (debug_displaced)
4905 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4906 "load/store insn %.8lx\n", (unsigned long) insn);
4908 dsc->modinsn[0] = insn & 0xfff0ffff;
4910 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
4916 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
4917 uint16_t insn2, struct regcache *regs,
4918 struct displaced_step_closure *dsc)
4920 unsigned int rn = bits (insn1, 0, 3);
4922 if (rn != ARM_PC_REGNUM)
4923 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
4924 "copro load/store", dsc);
4926 if (debug_displaced)
4927 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4928 "load/store insn %.4x%.4x\n", insn1, insn2);
4930 dsc->modinsn[0] = insn1 & 0xfff0;
4931 dsc->modinsn[1] = insn2;
4934 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4935 doesn't support writeback, so pass 0. */
4936 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
4941 /* Clean up branch instructions (actually perform the branch, by setting
4945 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
4946 struct displaced_step_closure *dsc)
4948 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
4949 int branch_taken = condition_true (dsc->u.branch.cond, status);
4950 enum pc_write_style write_pc = dsc->u.branch.exchange
4951 ? BX_WRITE_PC : BRANCH_WRITE_PC;
4956 if (dsc->u.branch.link)
4958 /* The value of LR should be the next insn of current one. In order
4959 not to confuse logic hanlding later insn `bx lr', if current insn mode
4960 is Thumb, the bit 0 of LR value should be set to 1. */
4961 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
4964 next_insn_addr |= 0x1;
4966 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
4970 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
4973 /* Copy B/BL/BLX instructions with immediate destinations. */
4976 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
4977 struct displaced_step_closure *dsc,
4978 unsigned int cond, int exchange, int link, long offset)
4980 /* Implement "BL<cond> <label>" as:
4982 Preparation: cond <- instruction condition
4983 Insn: mov r0, r0 (nop)
4984 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4986 B<cond> similar, but don't set r14 in cleanup. */
4988 dsc->u.branch.cond = cond;
4989 dsc->u.branch.link = link;
4990 dsc->u.branch.exchange = exchange;
4992 dsc->u.branch.dest = dsc->insn_addr;
4993 if (link && exchange)
4994 /* For BLX, offset is computed from the Align (PC, 4). */
4995 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
4998 dsc->u.branch.dest += 4 + offset;
5000 dsc->u.branch.dest += 8 + offset;
5002 dsc->cleanup = &cleanup_branch;
5005 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
5006 struct regcache *regs, struct displaced_step_closure *dsc)
5008 unsigned int cond = bits (insn, 28, 31);
5009 int exchange = (cond == 0xf);
5010 int link = exchange || bit (insn, 24);
5013 if (debug_displaced)
5014 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
5015 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
5016 (unsigned long) insn);
5018 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5019 then arrange the switch into Thumb mode. */
5020 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
5022 offset = bits (insn, 0, 23) << 2;
5024 if (bit (offset, 25))
5025 offset = offset | ~0x3ffffff;
5027 dsc->modinsn[0] = ARM_NOP;
5029 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5034 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
5035 uint16_t insn2, struct regcache *regs,
5036 struct displaced_step_closure *dsc)
5038 int link = bit (insn2, 14);
5039 int exchange = link && !bit (insn2, 12);
5042 int j1 = bit (insn2, 13);
5043 int j2 = bit (insn2, 11);
5044 int s = sbits (insn1, 10, 10);
5045 int i1 = !(j1 ^ bit (insn1, 10));
5046 int i2 = !(j2 ^ bit (insn1, 10));
5048 if (!link && !exchange) /* B */
5050 offset = (bits (insn2, 0, 10) << 1);
5051 if (bit (insn2, 12)) /* Encoding T4 */
5053 offset |= (bits (insn1, 0, 9) << 12)
5059 else /* Encoding T3 */
5061 offset |= (bits (insn1, 0, 5) << 12)
5065 cond = bits (insn1, 6, 9);
5070 offset = (bits (insn1, 0, 9) << 12);
5071 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
5072 offset |= exchange ?
5073 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
5076 if (debug_displaced)
5077 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
5078 "%.4x %.4x with offset %.8lx\n",
5079 link ? (exchange) ? "blx" : "bl" : "b",
5080 insn1, insn2, offset);
5082 dsc->modinsn[0] = THUMB_NOP;
5084 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5088 /* Copy B Thumb instructions. */
5090 thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn,
5091 struct displaced_step_closure *dsc)
5093 unsigned int cond = 0;
5095 unsigned short bit_12_15 = bits (insn, 12, 15);
5096 CORE_ADDR from = dsc->insn_addr;
5098 if (bit_12_15 == 0xd)
5100 /* offset = SignExtend (imm8:0, 32) */
5101 offset = sbits ((insn << 1), 0, 8);
5102 cond = bits (insn, 8, 11);
5104 else if (bit_12_15 == 0xe) /* Encoding T2 */
5106 offset = sbits ((insn << 1), 0, 11);
5110 if (debug_displaced)
5111 fprintf_unfiltered (gdb_stdlog,
5112 "displaced: copying b immediate insn %.4x "
5113 "with offset %d\n", insn, offset);
5115 dsc->u.branch.cond = cond;
5116 dsc->u.branch.link = 0;
5117 dsc->u.branch.exchange = 0;
5118 dsc->u.branch.dest = from + 4 + offset;
5120 dsc->modinsn[0] = THUMB_NOP;
5122 dsc->cleanup = &cleanup_branch;
5127 /* Copy BX/BLX with register-specified destinations. */
5130 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5131 struct displaced_step_closure *dsc, int link,
5132 unsigned int cond, unsigned int rm)
5134 /* Implement {BX,BLX}<cond> <reg>" as:
5136 Preparation: cond <- instruction condition
5137 Insn: mov r0, r0 (nop)
5138 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5140 Don't set r14 in cleanup for BX. */
5142 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5144 dsc->u.branch.cond = cond;
5145 dsc->u.branch.link = link;
5147 dsc->u.branch.exchange = 1;
5149 dsc->cleanup = &cleanup_branch;
5153 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5154 struct regcache *regs, struct displaced_step_closure *dsc)
5156 unsigned int cond = bits (insn, 28, 31);
5159 int link = bit (insn, 5);
5160 unsigned int rm = bits (insn, 0, 3);
5162 if (debug_displaced)
5163 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5164 (unsigned long) insn);
5166 dsc->modinsn[0] = ARM_NOP;
5168 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5173 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
5174 struct regcache *regs,
5175 struct displaced_step_closure *dsc)
5177 int link = bit (insn, 7);
5178 unsigned int rm = bits (insn, 3, 6);
5180 if (debug_displaced)
5181 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
5182 (unsigned short) insn);
5184 dsc->modinsn[0] = THUMB_NOP;
5186 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
5192 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5195 cleanup_alu_imm (struct gdbarch *gdbarch,
5196 struct regcache *regs, struct displaced_step_closure *dsc)
5198 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5199 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5200 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5201 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5205 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5206 struct displaced_step_closure *dsc)
5208 unsigned int rn = bits (insn, 16, 19);
5209 unsigned int rd = bits (insn, 12, 15);
5210 unsigned int op = bits (insn, 21, 24);
5211 int is_mov = (op == 0xd);
5212 ULONGEST rd_val, rn_val;
5214 if (!insn_references_pc (insn, 0x000ff000ul))
5215 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5217 if (debug_displaced)
5218 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5219 "%.8lx\n", is_mov ? "move" : "ALU",
5220 (unsigned long) insn);
5222 /* Instruction is of form:
5224 <op><cond> rd, [rn,] #imm
5228 Preparation: tmp1, tmp2 <- r0, r1;
5230 Insn: <op><cond> r0, r1, #imm
5231 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5234 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5235 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5236 rn_val = displaced_read_reg (regs, dsc, rn);
5237 rd_val = displaced_read_reg (regs, dsc, rd);
5238 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5239 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5243 dsc->modinsn[0] = insn & 0xfff00fff;
5245 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5247 dsc->cleanup = &cleanup_alu_imm;
5253 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
5254 uint16_t insn2, struct regcache *regs,
5255 struct displaced_step_closure *dsc)
5257 unsigned int op = bits (insn1, 5, 8);
5258 unsigned int rn, rm, rd;
5259 ULONGEST rd_val, rn_val;
5261 rn = bits (insn1, 0, 3); /* Rn */
5262 rm = bits (insn2, 0, 3); /* Rm */
5263 rd = bits (insn2, 8, 11); /* Rd */
5265 /* This routine is only called for instruction MOV. */
5266 gdb_assert (op == 0x2 && rn == 0xf);
5268 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
5269 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
5271 if (debug_displaced)
5272 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
5273 "ALU", insn1, insn2);
5275 /* Instruction is of form:
5277 <op><cond> rd, [rn,] #imm
5281 Preparation: tmp1, tmp2 <- r0, r1;
5283 Insn: <op><cond> r0, r1, #imm
5284 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5287 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5288 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5289 rn_val = displaced_read_reg (regs, dsc, rn);
5290 rd_val = displaced_read_reg (regs, dsc, rd);
5291 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5292 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5295 dsc->modinsn[0] = insn1;
5296 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
5299 dsc->cleanup = &cleanup_alu_imm;
5304 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5307 cleanup_alu_reg (struct gdbarch *gdbarch,
5308 struct regcache *regs, struct displaced_step_closure *dsc)
5313 rd_val = displaced_read_reg (regs, dsc, 0);
5315 for (i = 0; i < 3; i++)
5316 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5318 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5322 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
5323 struct displaced_step_closure *dsc,
5324 unsigned int rd, unsigned int rn, unsigned int rm)
5326 ULONGEST rd_val, rn_val, rm_val;
5328 /* Instruction is of form:
5330 <op><cond> rd, [rn,] rm [, <shift>]
5334 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5335 r0, r1, r2 <- rd, rn, rm
5336 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5337 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5340 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5341 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5342 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5343 rd_val = displaced_read_reg (regs, dsc, rd);
5344 rn_val = displaced_read_reg (regs, dsc, rn);
5345 rm_val = displaced_read_reg (regs, dsc, rm);
5346 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5347 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5348 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5351 dsc->cleanup = &cleanup_alu_reg;
5355 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5356 struct displaced_step_closure *dsc)
5358 unsigned int op = bits (insn, 21, 24);
5359 int is_mov = (op == 0xd);
5361 if (!insn_references_pc (insn, 0x000ff00ful))
5362 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
5364 if (debug_displaced)
5365 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
5366 is_mov ? "move" : "ALU", (unsigned long) insn);
5369 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
5371 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
5373 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
5379 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
5380 struct regcache *regs,
5381 struct displaced_step_closure *dsc)
5385 rm = bits (insn, 3, 6);
5386 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
5388 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
5389 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
5391 if (debug_displaced)
5392 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
5393 (unsigned short) insn);
5395 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
5397 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
5402 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5405 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
5406 struct regcache *regs,
5407 struct displaced_step_closure *dsc)
5409 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5412 for (i = 0; i < 4; i++)
5413 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5415 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5419 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
5420 struct displaced_step_closure *dsc,
5421 unsigned int rd, unsigned int rn, unsigned int rm,
5425 ULONGEST rd_val, rn_val, rm_val, rs_val;
5427 /* Instruction is of form:
5429 <op><cond> rd, [rn,] rm, <shift> rs
5433 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5434 r0, r1, r2, r3 <- rd, rn, rm, rs
5435 Insn: <op><cond> r0, r1, r2, <shift> r3
5437 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5441 for (i = 0; i < 4; i++)
5442 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5444 rd_val = displaced_read_reg (regs, dsc, rd);
5445 rn_val = displaced_read_reg (regs, dsc, rn);
5446 rm_val = displaced_read_reg (regs, dsc, rm);
5447 rs_val = displaced_read_reg (regs, dsc, rs);
5448 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5449 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5450 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5451 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
5453 dsc->cleanup = &cleanup_alu_shifted_reg;
5457 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
5458 struct regcache *regs,
5459 struct displaced_step_closure *dsc)
5461 unsigned int op = bits (insn, 21, 24);
5462 int is_mov = (op == 0xd);
5463 unsigned int rd, rn, rm, rs;
5465 if (!insn_references_pc (insn, 0x000fff0ful))
5466 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
5468 if (debug_displaced)
5469 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
5470 "%.8lx\n", is_mov ? "move" : "ALU",
5471 (unsigned long) insn);
5473 rn = bits (insn, 16, 19);
5474 rm = bits (insn, 0, 3);
5475 rs = bits (insn, 8, 11);
5476 rd = bits (insn, 12, 15);
5479 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
5481 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
5483 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
5488 /* Clean up load instructions. */
5491 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
5492 struct displaced_step_closure *dsc)
5494 ULONGEST rt_val, rt_val2 = 0, rn_val;
5496 rt_val = displaced_read_reg (regs, dsc, 0);
5497 if (dsc->u.ldst.xfersize == 8)
5498 rt_val2 = displaced_read_reg (regs, dsc, 1);
5499 rn_val = displaced_read_reg (regs, dsc, 2);
5501 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5502 if (dsc->u.ldst.xfersize > 4)
5503 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5504 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5505 if (!dsc->u.ldst.immed)
5506 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5508 /* Handle register writeback. */
5509 if (dsc->u.ldst.writeback)
5510 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5511 /* Put result in right place. */
5512 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
5513 if (dsc->u.ldst.xfersize == 8)
5514 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5517 /* Clean up store instructions. */
5520 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5521 struct displaced_step_closure *dsc)
5523 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
5525 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5526 if (dsc->u.ldst.xfersize > 4)
5527 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5528 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5529 if (!dsc->u.ldst.immed)
5530 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5531 if (!dsc->u.ldst.restore_r4)
5532 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5535 if (dsc->u.ldst.writeback)
5536 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5539 /* Copy "extra" load/store instructions. These are halfword/doubleword
5540 transfers, which have a different encoding to byte/word transfers. */
5543 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged,
5544 struct regcache *regs, struct displaced_step_closure *dsc)
5546 unsigned int op1 = bits (insn, 20, 24);
5547 unsigned int op2 = bits (insn, 5, 6);
5548 unsigned int rt = bits (insn, 12, 15);
5549 unsigned int rn = bits (insn, 16, 19);
5550 unsigned int rm = bits (insn, 0, 3);
5551 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5552 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5553 int immed = (op1 & 0x4) != 0;
5555 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5557 if (!insn_references_pc (insn, 0x000ff00ful))
5558 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5560 if (debug_displaced)
5561 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5562 "insn %.8lx\n", unprivileged ? "unprivileged " : "",
5563 (unsigned long) insn);
5565 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5568 internal_error (__FILE__, __LINE__,
5569 _("copy_extra_ld_st: instruction decode error"));
5571 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5572 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5573 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5575 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5577 rt_val = displaced_read_reg (regs, dsc, rt);
5578 if (bytesize[opcode] == 8)
5579 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
5580 rn_val = displaced_read_reg (regs, dsc, rn);
5582 rm_val = displaced_read_reg (regs, dsc, rm);
5584 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5585 if (bytesize[opcode] == 8)
5586 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5587 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5589 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5592 dsc->u.ldst.xfersize = bytesize[opcode];
5593 dsc->u.ldst.rn = rn;
5594 dsc->u.ldst.immed = immed;
5595 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5596 dsc->u.ldst.restore_r4 = 0;
5599 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5601 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5602 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5604 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5606 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5607 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5609 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5614 /* Copy byte/half word/word loads and stores. */
5617 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5618 struct displaced_step_closure *dsc, int load,
5619 int immed, int writeback, int size, int usermode,
5620 int rt, int rm, int rn)
5622 ULONGEST rt_val, rn_val, rm_val = 0;
5624 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5625 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5627 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5629 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
5631 rt_val = displaced_read_reg (regs, dsc, rt);
5632 rn_val = displaced_read_reg (regs, dsc, rn);
5634 rm_val = displaced_read_reg (regs, dsc, rm);
5636 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5637 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5639 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5641 dsc->u.ldst.xfersize = size;
5642 dsc->u.ldst.rn = rn;
5643 dsc->u.ldst.immed = immed;
5644 dsc->u.ldst.writeback = writeback;
5646 /* To write PC we can do:
5648 Before this sequence of instructions:
5649 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5650 r2 is the Rn value got from dispalced_read_reg.
5652 Insn1: push {pc} Write address of STR instruction + offset on stack
5653 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5654 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5655 = addr(Insn1) + offset - addr(Insn3) - 8
5657 Insn4: add r4, r4, #8 r4 = offset - 8
5658 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5660 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5662 Otherwise we don't know what value to write for PC, since the offset is
5663 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5664 of this can be found in Section "Saving from r15" in
5665 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5667 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5672 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
5673 uint16_t insn2, struct regcache *regs,
5674 struct displaced_step_closure *dsc, int size)
5676 unsigned int u_bit = bit (insn1, 7);
5677 unsigned int rt = bits (insn2, 12, 15);
5678 int imm12 = bits (insn2, 0, 11);
5681 if (debug_displaced)
5682 fprintf_unfiltered (gdb_stdlog,
5683 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5684 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
5690 /* Rewrite instruction LDR Rt imm12 into:
5692 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5696 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5699 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5700 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5701 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5703 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5705 pc_val = pc_val & 0xfffffffc;
5707 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
5708 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
5712 dsc->u.ldst.xfersize = size;
5713 dsc->u.ldst.immed = 0;
5714 dsc->u.ldst.writeback = 0;
5715 dsc->u.ldst.restore_r4 = 0;
5717 /* LDR R0, R2, R3 */
5718 dsc->modinsn[0] = 0xf852;
5719 dsc->modinsn[1] = 0x3;
5722 dsc->cleanup = &cleanup_load;
5728 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
5729 uint16_t insn2, struct regcache *regs,
5730 struct displaced_step_closure *dsc,
5731 int writeback, int immed)
5733 unsigned int rt = bits (insn2, 12, 15);
5734 unsigned int rn = bits (insn1, 0, 3);
5735 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
5736 /* In LDR (register), there is also a register Rm, which is not allowed to
5737 be PC, so we don't have to check it. */
5739 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
5740 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
5743 if (debug_displaced)
5744 fprintf_unfiltered (gdb_stdlog,
5745 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5746 rt, rn, insn1, insn2);
5748 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
5751 dsc->u.ldst.restore_r4 = 0;
5754 /* ldr[b]<cond> rt, [rn, #imm], etc.
5756 ldr[b]<cond> r0, [r2, #imm]. */
5758 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5759 dsc->modinsn[1] = insn2 & 0x0fff;
5762 /* ldr[b]<cond> rt, [rn, rm], etc.
5764 ldr[b]<cond> r0, [r2, r3]. */
5766 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5767 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
5777 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
5778 struct regcache *regs,
5779 struct displaced_step_closure *dsc,
5780 int load, int size, int usermode)
5782 int immed = !bit (insn, 25);
5783 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
5784 unsigned int rt = bits (insn, 12, 15);
5785 unsigned int rn = bits (insn, 16, 19);
5786 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
5788 if (!insn_references_pc (insn, 0x000ff00ful))
5789 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
5791 if (debug_displaced)
5792 fprintf_unfiltered (gdb_stdlog,
5793 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5794 load ? (size == 1 ? "ldrb" : "ldr")
5795 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
5797 (unsigned long) insn);
5799 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
5800 usermode, rt, rm, rn);
5802 if (load || rt != ARM_PC_REGNUM)
5804 dsc->u.ldst.restore_r4 = 0;
5807 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5809 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5810 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5812 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5814 {ldr,str}[b]<cond> r0, [r2, r3]. */
5815 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5819 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5820 dsc->u.ldst.restore_r4 = 1;
5821 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
5822 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
5823 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
5824 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
5825 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
5829 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
5831 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
5836 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5841 /* Cleanup LDM instructions with fully-populated register list. This is an
5842 unfortunate corner case: it's impossible to implement correctly by modifying
5843 the instruction. The issue is as follows: we have an instruction,
5847 which we must rewrite to avoid loading PC. A possible solution would be to
5848 do the load in two halves, something like (with suitable cleanup
5852 ldm[id][ab] r8!, {r0-r7}
5854 ldm[id][ab] r8, {r7-r14}
5857 but at present there's no suitable place for <temp>, since the scratch space
5858 is overwritten before the cleanup routine is called. For now, we simply
5859 emulate the instruction. */
5862 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
5863 struct displaced_step_closure *dsc)
5865 int inc = dsc->u.block.increment;
5866 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
5867 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
5868 uint32_t regmask = dsc->u.block.regmask;
5869 int regno = inc ? 0 : 15;
5870 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
5871 int exception_return = dsc->u.block.load && dsc->u.block.user
5872 && (regmask & 0x8000) != 0;
5873 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5874 int do_transfer = condition_true (dsc->u.block.cond, status);
5875 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5880 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5881 sensible we can do here. Complain loudly. */
5882 if (exception_return)
5883 error (_("Cannot single-step exception return"));
5885 /* We don't handle any stores here for now. */
5886 gdb_assert (dsc->u.block.load != 0);
5888 if (debug_displaced)
5889 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
5890 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
5891 dsc->u.block.increment ? "inc" : "dec",
5892 dsc->u.block.before ? "before" : "after");
5899 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
5902 while (regno >= 0 && (regmask & (1 << regno)) == 0)
5905 xfer_addr += bump_before;
5907 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
5908 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
5910 xfer_addr += bump_after;
5912 regmask &= ~(1 << regno);
5915 if (dsc->u.block.writeback)
5916 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
5920 /* Clean up an STM which included the PC in the register list. */
5923 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
5924 struct displaced_step_closure *dsc)
5926 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5927 int store_executed = condition_true (dsc->u.block.cond, status);
5928 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
5929 CORE_ADDR stm_insn_addr;
5932 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5934 /* If condition code fails, there's nothing else to do. */
5935 if (!store_executed)
5938 if (dsc->u.block.increment)
5940 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
5942 if (dsc->u.block.before)
5947 pc_stored_at = dsc->u.block.xfer_addr;
5949 if (dsc->u.block.before)
5953 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
5954 stm_insn_addr = dsc->scratch_base;
5955 offset = pc_val - stm_insn_addr;
5957 if (debug_displaced)
5958 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
5959 "STM instruction\n", offset);
5961 /* Rewrite the stored PC to the proper value for the non-displaced original
5963 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
5964 dsc->insn_addr + offset);
5967 /* Clean up an LDM which includes the PC in the register list. We clumped all
5968 the registers in the transferred list into a contiguous range r0...rX (to
5969 avoid loading PC directly and losing control of the debugged program), so we
5970 must undo that here. */
5973 cleanup_block_load_pc (struct gdbarch *gdbarch,
5974 struct regcache *regs,
5975 struct displaced_step_closure *dsc)
5977 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5978 int load_executed = condition_true (dsc->u.block.cond, status);
5979 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
5980 unsigned int regs_loaded = bitcount (mask);
5981 unsigned int num_to_shuffle = regs_loaded, clobbered;
5983 /* The method employed here will fail if the register list is fully populated
5984 (we need to avoid loading PC directly). */
5985 gdb_assert (num_to_shuffle < 16);
5990 clobbered = (1 << num_to_shuffle) - 1;
5992 while (num_to_shuffle > 0)
5994 if ((mask & (1 << write_reg)) != 0)
5996 unsigned int read_reg = num_to_shuffle - 1;
5998 if (read_reg != write_reg)
6000 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6001 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
6002 if (debug_displaced)
6003 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
6004 "loaded register r%d to r%d\n"), read_reg,
6007 else if (debug_displaced)
6008 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
6009 "r%d already in the right place\n"),
6012 clobbered &= ~(1 << write_reg);
6020 /* Restore any registers we scribbled over. */
6021 for (write_reg = 0; clobbered != 0; write_reg++)
6023 if ((clobbered & (1 << write_reg)) != 0)
6025 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
6027 if (debug_displaced)
6028 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
6029 "clobbered register r%d\n"), write_reg);
6030 clobbered &= ~(1 << write_reg);
6034 /* Perform register writeback manually. */
6035 if (dsc->u.block.writeback)
6037 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
6039 if (dsc->u.block.increment)
6040 new_rn_val += regs_loaded * 4;
6042 new_rn_val -= regs_loaded * 4;
6044 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
6049 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6050 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6053 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
6054 struct regcache *regs,
6055 struct displaced_step_closure *dsc)
6057 int load = bit (insn, 20);
6058 int user = bit (insn, 22);
6059 int increment = bit (insn, 23);
6060 int before = bit (insn, 24);
6061 int writeback = bit (insn, 21);
6062 int rn = bits (insn, 16, 19);
6064 /* Block transfers which don't mention PC can be run directly
6066 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
6067 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
6069 if (rn == ARM_PC_REGNUM)
6071 warning (_("displaced: Unpredictable LDM or STM with "
6072 "base register r15"));
6073 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
6076 if (debug_displaced)
6077 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6078 "%.8lx\n", (unsigned long) insn);
6080 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6081 dsc->u.block.rn = rn;
6083 dsc->u.block.load = load;
6084 dsc->u.block.user = user;
6085 dsc->u.block.increment = increment;
6086 dsc->u.block.before = before;
6087 dsc->u.block.writeback = writeback;
6088 dsc->u.block.cond = bits (insn, 28, 31);
6090 dsc->u.block.regmask = insn & 0xffff;
6094 if ((insn & 0xffff) == 0xffff)
6096 /* LDM with a fully-populated register list. This case is
6097 particularly tricky. Implement for now by fully emulating the
6098 instruction (which might not behave perfectly in all cases, but
6099 these instructions should be rare enough for that not to matter
6101 dsc->modinsn[0] = ARM_NOP;
6103 dsc->cleanup = &cleanup_block_load_all;
6107 /* LDM of a list of registers which includes PC. Implement by
6108 rewriting the list of registers to be transferred into a
6109 contiguous chunk r0...rX before doing the transfer, then shuffling
6110 registers into the correct places in the cleanup routine. */
6111 unsigned int regmask = insn & 0xffff;
6112 unsigned int num_in_list = bitcount (regmask), new_regmask;
6115 for (i = 0; i < num_in_list; i++)
6116 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6118 /* Writeback makes things complicated. We need to avoid clobbering
6119 the base register with one of the registers in our modified
6120 register list, but just using a different register can't work in
6123 ldm r14!, {r0-r13,pc}
6125 which would need to be rewritten as:
6129 but that can't work, because there's no free register for N.
6131 Solve this by turning off the writeback bit, and emulating
6132 writeback manually in the cleanup routine. */
6137 new_regmask = (1 << num_in_list) - 1;
6139 if (debug_displaced)
6140 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6141 "{..., pc}: original reg list %.4x, modified "
6142 "list %.4x\n"), rn, writeback ? "!" : "",
6143 (int) insn & 0xffff, new_regmask);
6145 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6147 dsc->cleanup = &cleanup_block_load_pc;
6152 /* STM of a list of registers which includes PC. Run the instruction
6153 as-is, but out of line: this will store the wrong value for the PC,
6154 so we must manually fix up the memory in the cleanup routine.
6155 Doing things this way has the advantage that we can auto-detect
6156 the offset of the PC write (which is architecture-dependent) in
6157 the cleanup routine. */
6158 dsc->modinsn[0] = insn;
6160 dsc->cleanup = &cleanup_block_store_pc;
6167 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6168 struct regcache *regs,
6169 struct displaced_step_closure *dsc)
6171 int rn = bits (insn1, 0, 3);
6172 int load = bit (insn1, 4);
6173 int writeback = bit (insn1, 5);
6175 /* Block transfers which don't mention PC can be run directly
6177 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
6178 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
6180 if (rn == ARM_PC_REGNUM)
6182 warning (_("displaced: Unpredictable LDM or STM with "
6183 "base register r15"));
6184 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6185 "unpredictable ldm/stm", dsc);
6188 if (debug_displaced)
6189 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6190 "%.4x%.4x\n", insn1, insn2);
6192 /* Clear bit 13, since it should be always zero. */
6193 dsc->u.block.regmask = (insn2 & 0xdfff);
6194 dsc->u.block.rn = rn;
6196 dsc->u.block.load = load;
6197 dsc->u.block.user = 0;
6198 dsc->u.block.increment = bit (insn1, 7);
6199 dsc->u.block.before = bit (insn1, 8);
6200 dsc->u.block.writeback = writeback;
6201 dsc->u.block.cond = INST_AL;
6202 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6206 if (dsc->u.block.regmask == 0xffff)
6208 /* This branch is impossible to happen. */
6213 unsigned int regmask = dsc->u.block.regmask;
6214 unsigned int num_in_list = bitcount (regmask), new_regmask;
6217 for (i = 0; i < num_in_list; i++)
6218 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6223 new_regmask = (1 << num_in_list) - 1;
6225 if (debug_displaced)
6226 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6227 "{..., pc}: original reg list %.4x, modified "
6228 "list %.4x\n"), rn, writeback ? "!" : "",
6229 (int) dsc->u.block.regmask, new_regmask);
6231 dsc->modinsn[0] = insn1;
6232 dsc->modinsn[1] = (new_regmask & 0xffff);
6235 dsc->cleanup = &cleanup_block_load_pc;
6240 dsc->modinsn[0] = insn1;
6241 dsc->modinsn[1] = insn2;
6243 dsc->cleanup = &cleanup_block_store_pc;
6248 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6249 This is used to avoid a dependency on BFD's bfd_endian enum. */
6252 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len,
6255 return read_memory_unsigned_integer (memaddr, len,
6256 (enum bfd_endian) byte_order);
6259 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6262 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
6265 return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val);
6268 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6271 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self)
6276 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6279 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self)
6281 return arm_is_thumb (self->regcache);
6284 /* single_step() is called just before we want to resume the inferior,
6285 if we want to single-step it but there is no hardware or kernel
6286 single-step support. We find the target of the coming instructions
6287 and breakpoint them. */
6290 arm_software_single_step (struct frame_info *frame)
6292 struct regcache *regcache = get_current_regcache ();
6293 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6294 struct address_space *aspace = get_regcache_aspace (regcache);
6295 struct arm_get_next_pcs next_pcs_ctx;
6298 VEC (CORE_ADDR) *next_pcs = NULL;
6299 struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
6301 arm_get_next_pcs_ctor (&next_pcs_ctx,
6302 &arm_get_next_pcs_ops,
6303 gdbarch_byte_order (gdbarch),
6304 gdbarch_byte_order_for_code (gdbarch),
6308 next_pcs = arm_get_next_pcs (&next_pcs_ctx);
6310 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
6312 pc = gdbarch_addr_bits_remove (gdbarch, pc);
6313 VEC_replace (CORE_ADDR, next_pcs, i, pc);
6316 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
6317 insert_single_step_breakpoint (gdbarch, aspace, pc);
6319 do_cleanups (old_chain);
6324 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6325 for Linux, where some SVC instructions must be treated specially. */
6328 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6329 struct displaced_step_closure *dsc)
6331 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6333 if (debug_displaced)
6334 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6335 "%.8lx\n", (unsigned long) resume_addr);
6337 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6341 /* Common copy routine for svc instruciton. */
6344 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
6345 struct displaced_step_closure *dsc)
6347 /* Preparation: none.
6348 Insn: unmodified svc.
6349 Cleanup: pc <- insn_addr + insn_size. */
6351 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6353 dsc->wrote_to_pc = 1;
6355 /* Allow OS-specific code to override SVC handling. */
6356 if (dsc->u.svc.copy_svc_os)
6357 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6360 dsc->cleanup = &cleanup_svc;
6366 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6367 struct regcache *regs, struct displaced_step_closure *dsc)
6370 if (debug_displaced)
6371 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6372 (unsigned long) insn);
6374 dsc->modinsn[0] = insn;
6376 return install_svc (gdbarch, regs, dsc);
6380 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
6381 struct regcache *regs, struct displaced_step_closure *dsc)
6384 if (debug_displaced)
6385 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
6388 dsc->modinsn[0] = insn;
6390 return install_svc (gdbarch, regs, dsc);
6393 /* Copy undefined instructions. */
6396 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6397 struct displaced_step_closure *dsc)
6399 if (debug_displaced)
6400 fprintf_unfiltered (gdb_stdlog,
6401 "displaced: copying undefined insn %.8lx\n",
6402 (unsigned long) insn);
6404 dsc->modinsn[0] = insn;
6410 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6411 struct displaced_step_closure *dsc)
6414 if (debug_displaced)
6415 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
6416 "%.4x %.4x\n", (unsigned short) insn1,
6417 (unsigned short) insn2);
6419 dsc->modinsn[0] = insn1;
6420 dsc->modinsn[1] = insn2;
6426 /* Copy unpredictable instructions. */
6429 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
6430 struct displaced_step_closure *dsc)
6432 if (debug_displaced)
6433 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
6434 "%.8lx\n", (unsigned long) insn);
6436 dsc->modinsn[0] = insn;
6441 /* The decode_* functions are instruction decoding helpers. They mostly follow
6442 the presentation in the ARM ARM. */
6445 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
6446 struct regcache *regs,
6447 struct displaced_step_closure *dsc)
6449 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
6450 unsigned int rn = bits (insn, 16, 19);
6452 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
6453 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
6454 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
6455 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
6456 else if ((op1 & 0x60) == 0x20)
6457 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
6458 else if ((op1 & 0x71) == 0x40)
6459 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
6461 else if ((op1 & 0x77) == 0x41)
6462 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6463 else if ((op1 & 0x77) == 0x45)
6464 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
6465 else if ((op1 & 0x77) == 0x51)
6468 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6470 return arm_copy_unpred (gdbarch, insn, dsc);
6472 else if ((op1 & 0x77) == 0x55)
6473 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6474 else if (op1 == 0x57)
6477 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
6478 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
6479 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
6480 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
6481 default: return arm_copy_unpred (gdbarch, insn, dsc);
6483 else if ((op1 & 0x63) == 0x43)
6484 return arm_copy_unpred (gdbarch, insn, dsc);
6485 else if ((op2 & 0x1) == 0x0)
6486 switch (op1 & ~0x80)
6489 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6491 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
6492 case 0x71: case 0x75:
6494 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
6495 case 0x63: case 0x67: case 0x73: case 0x77:
6496 return arm_copy_unpred (gdbarch, insn, dsc);
6498 return arm_copy_undef (gdbarch, insn, dsc);
6501 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
6505 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
6506 struct regcache *regs,
6507 struct displaced_step_closure *dsc)
6509 if (bit (insn, 27) == 0)
6510 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
6511 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6512 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
6515 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
6518 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
6520 case 0x4: case 0x5: case 0x6: case 0x7:
6521 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6524 switch ((insn & 0xe00000) >> 21)
6526 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6528 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6531 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6534 return arm_copy_undef (gdbarch, insn, dsc);
6539 int rn_f = (bits (insn, 16, 19) == 0xf);
6540 switch ((insn & 0xe00000) >> 21)
6543 /* ldc/ldc2 imm (undefined for rn == pc). */
6544 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
6545 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6548 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6550 case 0x4: case 0x5: case 0x6: case 0x7:
6551 /* ldc/ldc2 lit (undefined for rn != pc). */
6552 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
6553 : arm_copy_undef (gdbarch, insn, dsc);
6556 return arm_copy_undef (gdbarch, insn, dsc);
6561 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
6564 if (bits (insn, 16, 19) == 0xf)
6566 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6568 return arm_copy_undef (gdbarch, insn, dsc);
6572 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6574 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6578 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6580 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6583 return arm_copy_undef (gdbarch, insn, dsc);
6587 /* Decode miscellaneous instructions in dp/misc encoding space. */
6590 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
6591 struct regcache *regs,
6592 struct displaced_step_closure *dsc)
6594 unsigned int op2 = bits (insn, 4, 6);
6595 unsigned int op = bits (insn, 21, 22);
6600 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
6603 if (op == 0x1) /* bx. */
6604 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
6606 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
6608 return arm_copy_undef (gdbarch, insn, dsc);
6612 /* Not really supported. */
6613 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
6615 return arm_copy_undef (gdbarch, insn, dsc);
6619 return arm_copy_bx_blx_reg (gdbarch, insn,
6620 regs, dsc); /* blx register. */
6622 return arm_copy_undef (gdbarch, insn, dsc);
6625 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
6629 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
6631 /* Not really supported. */
6632 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
6635 return arm_copy_undef (gdbarch, insn, dsc);
6640 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
6641 struct regcache *regs,
6642 struct displaced_step_closure *dsc)
6645 switch (bits (insn, 20, 24))
6648 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
6651 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
6653 case 0x12: case 0x16:
6654 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
6657 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
6661 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
6663 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
6664 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
6665 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
6666 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
6667 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
6668 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
6669 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
6670 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
6671 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
6672 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
6673 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
6674 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
6675 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
6676 /* 2nd arg means "unprivileged". */
6677 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
6681 /* Should be unreachable. */
6686 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
6687 struct regcache *regs,
6688 struct displaced_step_closure *dsc)
6690 int a = bit (insn, 25), b = bit (insn, 4);
6691 uint32_t op1 = bits (insn, 20, 24);
6693 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
6694 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
6695 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
6696 else if ((!a && (op1 & 0x17) == 0x02)
6697 || (a && (op1 & 0x17) == 0x02 && !b))
6698 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
6699 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
6700 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
6701 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
6702 else if ((!a && (op1 & 0x17) == 0x03)
6703 || (a && (op1 & 0x17) == 0x03 && !b))
6704 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
6705 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
6706 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
6707 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
6708 else if ((!a && (op1 & 0x17) == 0x06)
6709 || (a && (op1 & 0x17) == 0x06 && !b))
6710 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
6711 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
6712 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
6713 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
6714 else if ((!a && (op1 & 0x17) == 0x07)
6715 || (a && (op1 & 0x17) == 0x07 && !b))
6716 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
6718 /* Should be unreachable. */
6723 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
6724 struct displaced_step_closure *dsc)
6726 switch (bits (insn, 20, 24))
6728 case 0x00: case 0x01: case 0x02: case 0x03:
6729 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
6731 case 0x04: case 0x05: case 0x06: case 0x07:
6732 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
6734 case 0x08: case 0x09: case 0x0a: case 0x0b:
6735 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6736 return arm_copy_unmodified (gdbarch, insn,
6737 "decode/pack/unpack/saturate/reverse", dsc);
6740 if (bits (insn, 5, 7) == 0) /* op2. */
6742 if (bits (insn, 12, 15) == 0xf)
6743 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
6745 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
6748 return arm_copy_undef (gdbarch, insn, dsc);
6750 case 0x1a: case 0x1b:
6751 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6752 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
6754 return arm_copy_undef (gdbarch, insn, dsc);
6756 case 0x1c: case 0x1d:
6757 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
6759 if (bits (insn, 0, 3) == 0xf)
6760 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
6762 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
6765 return arm_copy_undef (gdbarch, insn, dsc);
6767 case 0x1e: case 0x1f:
6768 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6769 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
6771 return arm_copy_undef (gdbarch, insn, dsc);
6774 /* Should be unreachable. */
6779 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn,
6780 struct regcache *regs,
6781 struct displaced_step_closure *dsc)
6784 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6786 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
6790 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
6791 struct regcache *regs,
6792 struct displaced_step_closure *dsc)
6794 unsigned int opcode = bits (insn, 20, 24);
6798 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6799 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
6801 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6802 case 0x12: case 0x16:
6803 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
6805 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6806 case 0x13: case 0x17:
6807 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
6809 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6810 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6811 /* Note: no writeback for these instructions. Bit 25 will always be
6812 zero though (via caller), so the following works OK. */
6813 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6816 /* Should be unreachable. */
6820 /* Decode shifted register instructions. */
6823 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
6824 uint16_t insn2, struct regcache *regs,
6825 struct displaced_step_closure *dsc)
6827 /* PC is only allowed to be used in instruction MOV. */
6829 unsigned int op = bits (insn1, 5, 8);
6830 unsigned int rn = bits (insn1, 0, 3);
6832 if (op == 0x2 && rn == 0xf) /* MOV */
6833 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
6835 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6836 "dp (shift reg)", dsc);
6840 /* Decode extension register load/store. Exactly the same as
6841 arm_decode_ext_reg_ld_st. */
6844 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
6845 uint16_t insn2, struct regcache *regs,
6846 struct displaced_step_closure *dsc)
6848 unsigned int opcode = bits (insn1, 4, 8);
6852 case 0x04: case 0x05:
6853 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6854 "vfp/neon vmov", dsc);
6856 case 0x08: case 0x0c: /* 01x00 */
6857 case 0x0a: case 0x0e: /* 01x10 */
6858 case 0x12: case 0x16: /* 10x10 */
6859 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6860 "vfp/neon vstm/vpush", dsc);
6862 case 0x09: case 0x0d: /* 01x01 */
6863 case 0x0b: case 0x0f: /* 01x11 */
6864 case 0x13: case 0x17: /* 10x11 */
6865 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6866 "vfp/neon vldm/vpop", dsc);
6868 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6869 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6871 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6872 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
6875 /* Should be unreachable. */
6880 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn,
6881 struct regcache *regs, struct displaced_step_closure *dsc)
6883 unsigned int op1 = bits (insn, 20, 25);
6884 int op = bit (insn, 4);
6885 unsigned int coproc = bits (insn, 8, 11);
6887 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
6888 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
6889 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
6890 && (coproc & 0xe) != 0xa)
6892 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6893 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
6894 && (coproc & 0xe) != 0xa)
6895 /* ldc/ldc2 imm/lit. */
6896 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6897 else if ((op1 & 0x3e) == 0x00)
6898 return arm_copy_undef (gdbarch, insn, dsc);
6899 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6900 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6901 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6902 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6903 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6904 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6905 else if ((op1 & 0x30) == 0x20 && !op)
6907 if ((coproc & 0xe) == 0xa)
6908 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6910 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6912 else if ((op1 & 0x30) == 0x20 && op)
6913 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6914 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6915 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6916 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6917 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6918 else if ((op1 & 0x30) == 0x30)
6919 return arm_copy_svc (gdbarch, insn, regs, dsc);
6921 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6925 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
6926 uint16_t insn2, struct regcache *regs,
6927 struct displaced_step_closure *dsc)
6929 unsigned int coproc = bits (insn2, 8, 11);
6930 unsigned int bit_5_8 = bits (insn1, 5, 8);
6931 unsigned int bit_9 = bit (insn1, 9);
6932 unsigned int bit_4 = bit (insn1, 4);
6937 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6938 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6940 else if (bit_5_8 == 0) /* UNDEFINED. */
6941 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
6944 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6945 if ((coproc & 0xe) == 0xa)
6946 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
6948 else /* coproc is not 101x. */
6950 if (bit_4 == 0) /* STC/STC2. */
6951 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6953 else /* LDC/LDC2 {literal, immeidate}. */
6954 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
6960 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
6966 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
6967 struct displaced_step_closure *dsc, int rd)
6973 Preparation: Rd <- PC
6979 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6980 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
6984 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
6985 struct displaced_step_closure *dsc,
6986 int rd, unsigned int imm)
6989 /* Encoding T2: ADDS Rd, #imm */
6990 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
6992 install_pc_relative (gdbarch, regs, dsc, rd);
6998 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
6999 struct regcache *regs,
7000 struct displaced_step_closure *dsc)
7002 unsigned int rd = bits (insn, 8, 10);
7003 unsigned int imm8 = bits (insn, 0, 7);
7005 if (debug_displaced)
7006 fprintf_unfiltered (gdb_stdlog,
7007 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7010 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7014 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7015 uint16_t insn2, struct regcache *regs,
7016 struct displaced_step_closure *dsc)
7018 unsigned int rd = bits (insn2, 8, 11);
7019 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7020 extract raw immediate encoding rather than computing immediate. When
7021 generating ADD or SUB instruction, we can simply perform OR operation to
7022 set immediate into ADD. */
7023 unsigned int imm_3_8 = insn2 & 0x70ff;
7024 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7026 if (debug_displaced)
7027 fprintf_unfiltered (gdb_stdlog,
7028 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7029 rd, imm_i, imm_3_8, insn1, insn2);
7031 if (bit (insn1, 7)) /* Encoding T2 */
7033 /* Encoding T3: SUB Rd, Rd, #imm */
7034 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7035 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7037 else /* Encoding T3 */
7039 /* Encoding T3: ADD Rd, Rd, #imm */
7040 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7041 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7045 install_pc_relative (gdbarch, regs, dsc, rd);
7051 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1,
7052 struct regcache *regs,
7053 struct displaced_step_closure *dsc)
7055 unsigned int rt = bits (insn1, 8, 10);
7057 int imm8 = (bits (insn1, 0, 7) << 2);
7063 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7065 Insn: LDR R0, [R2, R3];
7066 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7068 if (debug_displaced)
7069 fprintf_unfiltered (gdb_stdlog,
7070 "displaced: copying thumb ldr r%d [pc #%d]\n"
7073 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
7074 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
7075 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
7076 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7077 /* The assembler calculates the required value of the offset from the
7078 Align(PC,4) value of this instruction to the label. */
7079 pc = pc & 0xfffffffc;
7081 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
7082 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
7085 dsc->u.ldst.xfersize = 4;
7087 dsc->u.ldst.immed = 0;
7088 dsc->u.ldst.writeback = 0;
7089 dsc->u.ldst.restore_r4 = 0;
7091 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7093 dsc->cleanup = &cleanup_load;
7098 /* Copy Thumb cbnz/cbz insruction. */
7101 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
7102 struct regcache *regs,
7103 struct displaced_step_closure *dsc)
7105 int non_zero = bit (insn1, 11);
7106 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
7107 CORE_ADDR from = dsc->insn_addr;
7108 int rn = bits (insn1, 0, 2);
7109 int rn_val = displaced_read_reg (regs, dsc, rn);
7111 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
7112 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7113 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7114 condition is false, let it be, cleanup_branch will do nothing. */
7115 if (dsc->u.branch.cond)
7117 dsc->u.branch.cond = INST_AL;
7118 dsc->u.branch.dest = from + 4 + imm5;
7121 dsc->u.branch.dest = from + 2;
7123 dsc->u.branch.link = 0;
7124 dsc->u.branch.exchange = 0;
7126 if (debug_displaced)
7127 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
7128 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
7129 rn, rn_val, insn1, dsc->u.branch.dest);
7131 dsc->modinsn[0] = THUMB_NOP;
7133 dsc->cleanup = &cleanup_branch;
7137 /* Copy Table Branch Byte/Halfword */
7139 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7140 uint16_t insn2, struct regcache *regs,
7141 struct displaced_step_closure *dsc)
7143 ULONGEST rn_val, rm_val;
7144 int is_tbh = bit (insn2, 4);
7145 CORE_ADDR halfwords = 0;
7146 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7148 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7149 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7155 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7156 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7162 target_read_memory (rn_val + rm_val, buf, 1);
7163 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7166 if (debug_displaced)
7167 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7168 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7169 (unsigned int) rn_val, (unsigned int) rm_val,
7170 (unsigned int) halfwords);
7172 dsc->u.branch.cond = INST_AL;
7173 dsc->u.branch.link = 0;
7174 dsc->u.branch.exchange = 0;
7175 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7177 dsc->cleanup = &cleanup_branch;
7183 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
7184 struct displaced_step_closure *dsc)
7187 int val = displaced_read_reg (regs, dsc, 7);
7188 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
7191 val = displaced_read_reg (regs, dsc, 8);
7192 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
7195 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
7200 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1,
7201 struct regcache *regs,
7202 struct displaced_step_closure *dsc)
7204 dsc->u.block.regmask = insn1 & 0x00ff;
7206 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7209 (1) register list is full, that is, r0-r7 are used.
7210 Prepare: tmp[0] <- r8
7212 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7213 MOV r8, r7; Move value of r7 to r8;
7214 POP {r7}; Store PC value into r7.
7216 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7218 (2) register list is not full, supposing there are N registers in
7219 register list (except PC, 0 <= N <= 7).
7220 Prepare: for each i, 0 - N, tmp[i] <- ri.
7222 POP {r0, r1, ...., rN};
7224 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7225 from tmp[] properly.
7227 if (debug_displaced)
7228 fprintf_unfiltered (gdb_stdlog,
7229 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7230 dsc->u.block.regmask, insn1);
7232 if (dsc->u.block.regmask == 0xff)
7234 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
7236 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
7237 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
7238 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
7241 dsc->cleanup = &cleanup_pop_pc_16bit_all;
7245 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
7247 unsigned int new_regmask;
7249 for (i = 0; i < num_in_list + 1; i++)
7250 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7252 new_regmask = (1 << (num_in_list + 1)) - 1;
7254 if (debug_displaced)
7255 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
7256 "{..., pc}: original reg list %.4x,"
7257 " modified list %.4x\n"),
7258 (int) dsc->u.block.regmask, new_regmask);
7260 dsc->u.block.regmask |= 0x8000;
7261 dsc->u.block.writeback = 0;
7262 dsc->u.block.cond = INST_AL;
7264 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
7266 dsc->cleanup = &cleanup_block_load_pc;
7273 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7274 struct regcache *regs,
7275 struct displaced_step_closure *dsc)
7277 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
7278 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
7281 /* 16-bit thumb instructions. */
7282 switch (op_bit_12_15)
7284 /* Shift (imme), add, subtract, move and compare. */
7285 case 0: case 1: case 2: case 3:
7286 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7287 "shift/add/sub/mov/cmp",
7291 switch (op_bit_10_11)
7293 case 0: /* Data-processing */
7294 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7298 case 1: /* Special data instructions and branch and exchange. */
7300 unsigned short op = bits (insn1, 7, 9);
7301 if (op == 6 || op == 7) /* BX or BLX */
7302 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
7303 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7304 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
7306 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
7310 default: /* LDR (literal) */
7311 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
7314 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7315 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
7318 if (op_bit_10_11 < 2) /* Generate PC-relative address */
7319 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
7320 else /* Generate SP-relative address */
7321 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
7323 case 11: /* Misc 16-bit instructions */
7325 switch (bits (insn1, 8, 11))
7327 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7328 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
7330 case 12: case 13: /* POP */
7331 if (bit (insn1, 8)) /* PC is in register list. */
7332 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
7334 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
7336 case 15: /* If-Then, and hints */
7337 if (bits (insn1, 0, 3))
7338 /* If-Then makes up to four following instructions conditional.
7339 IT instruction itself is not conditional, so handle it as a
7340 common unmodified instruction. */
7341 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
7344 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
7347 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
7352 if (op_bit_10_11 < 2) /* Store multiple registers */
7353 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
7354 else /* Load multiple registers */
7355 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
7357 case 13: /* Conditional branch and supervisor call */
7358 if (bits (insn1, 9, 11) != 7) /* conditional branch */
7359 err = thumb_copy_b (gdbarch, insn1, dsc);
7361 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
7363 case 14: /* Unconditional branch */
7364 err = thumb_copy_b (gdbarch, insn1, dsc);
7371 internal_error (__FILE__, __LINE__,
7372 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7376 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
7377 uint16_t insn1, uint16_t insn2,
7378 struct regcache *regs,
7379 struct displaced_step_closure *dsc)
7381 int rt = bits (insn2, 12, 15);
7382 int rn = bits (insn1, 0, 3);
7383 int op1 = bits (insn1, 7, 8);
7385 switch (bits (insn1, 5, 6))
7387 case 0: /* Load byte and memory hints */
7388 if (rt == 0xf) /* PLD/PLI */
7391 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7392 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
7394 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7399 if (rn == 0xf) /* LDRB/LDRSB (literal) */
7400 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7403 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7404 "ldrb{reg, immediate}/ldrbt",
7409 case 1: /* Load halfword and memory hints. */
7410 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
7411 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7412 "pld/unalloc memhint", dsc);
7416 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7419 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7423 case 2: /* Load word */
7425 int insn2_bit_8_11 = bits (insn2, 8, 11);
7428 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
7429 else if (op1 == 0x1) /* Encoding T3 */
7430 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
7432 else /* op1 == 0x0 */
7434 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
7435 /* LDR (immediate) */
7436 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7437 dsc, bit (insn2, 8), 1);
7438 else if (insn2_bit_8_11 == 0xe) /* LDRT */
7439 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7442 /* LDR (register) */
7443 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7449 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7456 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7457 uint16_t insn2, struct regcache *regs,
7458 struct displaced_step_closure *dsc)
7461 unsigned short op = bit (insn2, 15);
7462 unsigned int op1 = bits (insn1, 11, 12);
7468 switch (bits (insn1, 9, 10))
7473 /* Load/store {dual, execlusive}, table branch. */
7474 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
7475 && bits (insn2, 5, 7) == 0)
7476 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
7479 /* PC is not allowed to use in load/store {dual, exclusive}
7481 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7482 "load/store dual/ex", dsc);
7484 else /* load/store multiple */
7486 switch (bits (insn1, 7, 8))
7488 case 0: case 3: /* SRS, RFE */
7489 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7492 case 1: case 2: /* LDM/STM/PUSH/POP */
7493 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
7500 /* Data-processing (shift register). */
7501 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
7504 default: /* Coprocessor instructions. */
7505 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7510 case 2: /* op1 = 2 */
7511 if (op) /* Branch and misc control. */
7513 if (bit (insn2, 14) /* BLX/BL */
7514 || bit (insn2, 12) /* Unconditional branch */
7515 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
7516 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
7518 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7523 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
7525 int op = bits (insn1, 4, 8);
7526 int rn = bits (insn1, 0, 3);
7527 if ((op == 0 || op == 0xa) && rn == 0xf)
7528 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
7531 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7534 else /* Data processing (modified immeidate) */
7535 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7539 case 3: /* op1 = 3 */
7540 switch (bits (insn1, 9, 10))
7544 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
7546 else /* NEON Load/Store and Store single data item */
7547 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7548 "neon elt/struct load/store",
7551 case 1: /* op1 = 3, bits (9, 10) == 1 */
7552 switch (bits (insn1, 7, 8))
7554 case 0: case 1: /* Data processing (register) */
7555 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7558 case 2: /* Multiply and absolute difference */
7559 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7560 "mul/mua/diff", dsc);
7562 case 3: /* Long multiply and divide */
7563 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7568 default: /* Coprocessor instructions */
7569 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7578 internal_error (__FILE__, __LINE__,
7579 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7584 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7585 struct regcache *regs,
7586 struct displaced_step_closure *dsc)
7588 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7590 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
7592 if (debug_displaced)
7593 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
7594 "at %.8lx\n", insn1, (unsigned long) from);
7597 dsc->insn_size = thumb_insn_size (insn1);
7598 if (thumb_insn_size (insn1) == 4)
7601 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
7602 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
7605 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
7609 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7610 CORE_ADDR to, struct regcache *regs,
7611 struct displaced_step_closure *dsc)
7614 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7617 /* Most displaced instructions use a 1-instruction scratch space, so set this
7618 here and override below if/when necessary. */
7620 dsc->insn_addr = from;
7621 dsc->scratch_base = to;
7622 dsc->cleanup = NULL;
7623 dsc->wrote_to_pc = 0;
7625 if (!displaced_in_arm_mode (regs))
7626 return thumb_process_displaced_insn (gdbarch, from, regs, dsc);
7630 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
7631 if (debug_displaced)
7632 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
7633 "at %.8lx\n", (unsigned long) insn,
7634 (unsigned long) from);
7636 if ((insn & 0xf0000000) == 0xf0000000)
7637 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
7638 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
7640 case 0x0: case 0x1: case 0x2: case 0x3:
7641 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
7644 case 0x4: case 0x5: case 0x6:
7645 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
7649 err = arm_decode_media (gdbarch, insn, dsc);
7652 case 0x8: case 0x9: case 0xa: case 0xb:
7653 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
7656 case 0xc: case 0xd: case 0xe: case 0xf:
7657 err = arm_decode_svc_copro (gdbarch, insn, regs, dsc);
7662 internal_error (__FILE__, __LINE__,
7663 _("arm_process_displaced_insn: Instruction decode error"));
7666 /* Actually set up the scratch space for a displaced instruction. */
7669 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
7670 CORE_ADDR to, struct displaced_step_closure *dsc)
7672 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7673 unsigned int i, len, offset;
7674 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7675 int size = dsc->is_thumb? 2 : 4;
7676 const gdb_byte *bkp_insn;
7679 /* Poke modified instruction(s). */
7680 for (i = 0; i < dsc->numinsns; i++)
7682 if (debug_displaced)
7684 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
7686 fprintf_unfiltered (gdb_stdlog, "%.8lx",
7689 fprintf_unfiltered (gdb_stdlog, "%.4x",
7690 (unsigned short)dsc->modinsn[i]);
7692 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
7693 (unsigned long) to + offset);
7696 write_memory_unsigned_integer (to + offset, size,
7697 byte_order_for_code,
7702 /* Choose the correct breakpoint instruction. */
7705 bkp_insn = tdep->thumb_breakpoint;
7706 len = tdep->thumb_breakpoint_size;
7710 bkp_insn = tdep->arm_breakpoint;
7711 len = tdep->arm_breakpoint_size;
7714 /* Put breakpoint afterwards. */
7715 write_memory (to + offset, bkp_insn, len);
7717 if (debug_displaced)
7718 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
7719 paddress (gdbarch, from), paddress (gdbarch, to));
7722 /* Entry point for cleaning things up after a displaced instruction has been
7726 arm_displaced_step_fixup (struct gdbarch *gdbarch,
7727 struct displaced_step_closure *dsc,
7728 CORE_ADDR from, CORE_ADDR to,
7729 struct regcache *regs)
7732 dsc->cleanup (gdbarch, regs, dsc);
7734 if (!dsc->wrote_to_pc)
7735 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
7736 dsc->insn_addr + dsc->insn_size);
7740 #include "bfd-in2.h"
7741 #include "libcoff.h"
7744 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
7746 struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
7748 if (arm_pc_is_thumb (gdbarch, memaddr))
7750 static asymbol *asym;
7751 static combined_entry_type ce;
7752 static struct coff_symbol_struct csym;
7753 static struct bfd fake_bfd;
7754 static bfd_target fake_target;
7756 if (csym.native == NULL)
7758 /* Create a fake symbol vector containing a Thumb symbol.
7759 This is solely so that the code in print_insn_little_arm()
7760 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7761 the presence of a Thumb symbol and switch to decoding
7762 Thumb instructions. */
7764 fake_target.flavour = bfd_target_coff_flavour;
7765 fake_bfd.xvec = &fake_target;
7766 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
7768 csym.symbol.the_bfd = &fake_bfd;
7769 csym.symbol.name = "fake";
7770 asym = (asymbol *) & csym;
7773 memaddr = UNMAKE_THUMB_ADDR (memaddr);
7774 info->symbols = &asym;
7777 info->symbols = NULL;
7779 if (info->endian == BFD_ENDIAN_BIG)
7780 return print_insn_big_arm (memaddr, info);
7782 return print_insn_little_arm (memaddr, info);
7785 /* The following define instruction sequences that will cause ARM
7786 cpu's to take an undefined instruction trap. These are used to
7787 signal a breakpoint to GDB.
7789 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7790 modes. A different instruction is required for each mode. The ARM
7791 cpu's can also be big or little endian. Thus four different
7792 instructions are needed to support all cases.
7794 Note: ARMv4 defines several new instructions that will take the
7795 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7796 not in fact add the new instructions. The new undefined
7797 instructions in ARMv4 are all instructions that had no defined
7798 behaviour in earlier chips. There is no guarantee that they will
7799 raise an exception, but may be treated as NOP's. In practice, it
7800 may only safe to rely on instructions matching:
7802 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7803 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7804 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7806 Even this may only true if the condition predicate is true. The
7807 following use a condition predicate of ALWAYS so it is always TRUE.
7809 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7810 and NetBSD all use a software interrupt rather than an undefined
7811 instruction to force a trap. This can be handled by by the
7812 abi-specific code during establishment of the gdbarch vector. */
7814 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7815 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7816 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7817 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7819 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
7820 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
7821 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
7822 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
7824 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7827 arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
7829 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7830 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7832 if (arm_pc_is_thumb (gdbarch, *pcptr))
7834 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
7836 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7837 check whether we are replacing a 32-bit instruction. */
7838 if (tdep->thumb2_breakpoint != NULL)
7842 if (target_read_memory (*pcptr, buf, 2) == 0)
7844 unsigned short inst1;
7846 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
7847 if (thumb_insn_size (inst1) == 4)
7848 return ARM_BP_KIND_THUMB2;
7852 return ARM_BP_KIND_THUMB;
7855 return ARM_BP_KIND_ARM;
7859 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7861 static const gdb_byte *
7862 arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
7864 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7868 case ARM_BP_KIND_ARM:
7869 *size = tdep->arm_breakpoint_size;
7870 return tdep->arm_breakpoint;
7871 case ARM_BP_KIND_THUMB:
7872 *size = tdep->thumb_breakpoint_size;
7873 return tdep->thumb_breakpoint;
7874 case ARM_BP_KIND_THUMB2:
7875 *size = tdep->thumb2_breakpoint_size;
7876 return tdep->thumb2_breakpoint;
7878 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7882 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7885 arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
7886 struct regcache *regcache,
7891 /* Check the memory pointed by PC is readable. */
7892 if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
7894 struct arm_get_next_pcs next_pcs_ctx;
7897 VEC (CORE_ADDR) *next_pcs = NULL;
7898 struct cleanup *old_chain
7899 = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
7901 arm_get_next_pcs_ctor (&next_pcs_ctx,
7902 &arm_get_next_pcs_ops,
7903 gdbarch_byte_order (gdbarch),
7904 gdbarch_byte_order_for_code (gdbarch),
7908 next_pcs = arm_get_next_pcs (&next_pcs_ctx);
7910 /* If MEMADDR is the next instruction of current pc, do the
7911 software single step computation, and get the thumb mode by
7912 the destination address. */
7913 for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
7915 if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
7917 do_cleanups (old_chain);
7919 if (IS_THUMB_ADDR (pc))
7921 *pcptr = MAKE_THUMB_ADDR (*pcptr);
7922 return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
7925 return ARM_BP_KIND_ARM;
7929 do_cleanups (old_chain);
7932 return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
7935 /* Extract from an array REGBUF containing the (raw) register state a
7936 function return value of type TYPE, and copy that, in virtual
7937 format, into VALBUF. */
7940 arm_extract_return_value (struct type *type, struct regcache *regs,
7943 struct gdbarch *gdbarch = get_regcache_arch (regs);
7944 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7946 if (TYPE_CODE_FLT == TYPE_CODE (type))
7948 switch (gdbarch_tdep (gdbarch)->fp_model)
7952 /* The value is in register F0 in internal format. We need to
7953 extract the raw value and then convert it to the desired
7955 bfd_byte tmpbuf[FP_REGISTER_SIZE];
7957 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
7958 convert_from_extended (floatformat_from_type (type), tmpbuf,
7959 valbuf, gdbarch_byte_order (gdbarch));
7963 case ARM_FLOAT_SOFT_FPA:
7964 case ARM_FLOAT_SOFT_VFP:
7965 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7966 not using the VFP ABI code. */
7968 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
7969 if (TYPE_LENGTH (type) > 4)
7970 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7971 valbuf + INT_REGISTER_SIZE);
7975 internal_error (__FILE__, __LINE__,
7976 _("arm_extract_return_value: "
7977 "Floating point model not supported"));
7981 else if (TYPE_CODE (type) == TYPE_CODE_INT
7982 || TYPE_CODE (type) == TYPE_CODE_CHAR
7983 || TYPE_CODE (type) == TYPE_CODE_BOOL
7984 || TYPE_CODE (type) == TYPE_CODE_PTR
7985 || TYPE_CODE (type) == TYPE_CODE_REF
7986 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7988 /* If the type is a plain integer, then the access is
7989 straight-forward. Otherwise we have to play around a bit
7991 int len = TYPE_LENGTH (type);
7992 int regno = ARM_A1_REGNUM;
7997 /* By using store_unsigned_integer we avoid having to do
7998 anything special for small big-endian values. */
7999 regcache_cooked_read_unsigned (regs, regno++, &tmp);
8000 store_unsigned_integer (valbuf,
8001 (len > INT_REGISTER_SIZE
8002 ? INT_REGISTER_SIZE : len),
8004 len -= INT_REGISTER_SIZE;
8005 valbuf += INT_REGISTER_SIZE;
8010 /* For a structure or union the behaviour is as if the value had
8011 been stored to word-aligned memory and then loaded into
8012 registers with 32-bit load instruction(s). */
8013 int len = TYPE_LENGTH (type);
8014 int regno = ARM_A1_REGNUM;
8015 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8019 regcache_cooked_read (regs, regno++, tmpbuf);
8020 memcpy (valbuf, tmpbuf,
8021 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8022 len -= INT_REGISTER_SIZE;
8023 valbuf += INT_REGISTER_SIZE;
8029 /* Will a function return an aggregate type in memory or in a
8030 register? Return 0 if an aggregate type can be returned in a
8031 register, 1 if it must be returned in memory. */
8034 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8036 enum type_code code;
8038 type = check_typedef (type);
8040 /* Simple, non-aggregate types (ie not including vectors and
8041 complex) are always returned in a register (or registers). */
8042 code = TYPE_CODE (type);
8043 if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code
8044 && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code)
8047 if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type))
8049 /* Vector values should be returned using ARM registers if they
8050 are not over 16 bytes. */
8051 return (TYPE_LENGTH (type) > 16);
8054 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8056 /* The AAPCS says all aggregates not larger than a word are returned
8058 if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
8067 /* All aggregate types that won't fit in a register must be returned
8069 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8072 /* In the ARM ABI, "integer" like aggregate types are returned in
8073 registers. For an aggregate type to be integer like, its size
8074 must be less than or equal to INT_REGISTER_SIZE and the
8075 offset of each addressable subfield must be zero. Note that bit
8076 fields are not addressable, and all addressable subfields of
8077 unions always start at offset zero.
8079 This function is based on the behaviour of GCC 2.95.1.
8080 See: gcc/arm.c: arm_return_in_memory() for details.
8082 Note: All versions of GCC before GCC 2.95.2 do not set up the
8083 parameters correctly for a function returning the following
8084 structure: struct { float f;}; This should be returned in memory,
8085 not a register. Richard Earnshaw sent me a patch, but I do not
8086 know of any way to detect if a function like the above has been
8087 compiled with the correct calling convention. */
8089 /* Assume all other aggregate types can be returned in a register.
8090 Run a check for structures, unions and arrays. */
8093 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8096 /* Need to check if this struct/union is "integer" like. For
8097 this to be true, its size must be less than or equal to
8098 INT_REGISTER_SIZE and the offset of each addressable
8099 subfield must be zero. Note that bit fields are not
8100 addressable, and unions always start at offset zero. If any
8101 of the subfields is a floating point type, the struct/union
8102 cannot be an integer type. */
8104 /* For each field in the object, check:
8105 1) Is it FP? --> yes, nRc = 1;
8106 2) Is it addressable (bitpos != 0) and
8107 not packed (bitsize == 0)?
8111 for (i = 0; i < TYPE_NFIELDS (type); i++)
8113 enum type_code field_type_code;
8116 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
8119 /* Is it a floating point type field? */
8120 if (field_type_code == TYPE_CODE_FLT)
8126 /* If bitpos != 0, then we have to care about it. */
8127 if (TYPE_FIELD_BITPOS (type, i) != 0)
8129 /* Bitfields are not addressable. If the field bitsize is
8130 zero, then the field is not packed. Hence it cannot be
8131 a bitfield or any other packed type. */
8132 if (TYPE_FIELD_BITSIZE (type, i) == 0)
8145 /* Write into appropriate registers a function return value of type
8146 TYPE, given in virtual format. */
8149 arm_store_return_value (struct type *type, struct regcache *regs,
8150 const gdb_byte *valbuf)
8152 struct gdbarch *gdbarch = get_regcache_arch (regs);
8153 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8155 if (TYPE_CODE (type) == TYPE_CODE_FLT)
8157 gdb_byte buf[MAX_REGISTER_SIZE];
8159 switch (gdbarch_tdep (gdbarch)->fp_model)
8163 convert_to_extended (floatformat_from_type (type), buf, valbuf,
8164 gdbarch_byte_order (gdbarch));
8165 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
8168 case ARM_FLOAT_SOFT_FPA:
8169 case ARM_FLOAT_SOFT_VFP:
8170 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8171 not using the VFP ABI code. */
8173 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
8174 if (TYPE_LENGTH (type) > 4)
8175 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
8176 valbuf + INT_REGISTER_SIZE);
8180 internal_error (__FILE__, __LINE__,
8181 _("arm_store_return_value: Floating "
8182 "point model not supported"));
8186 else if (TYPE_CODE (type) == TYPE_CODE_INT
8187 || TYPE_CODE (type) == TYPE_CODE_CHAR
8188 || TYPE_CODE (type) == TYPE_CODE_BOOL
8189 || TYPE_CODE (type) == TYPE_CODE_PTR
8190 || TYPE_CODE (type) == TYPE_CODE_REF
8191 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8193 if (TYPE_LENGTH (type) <= 4)
8195 /* Values of one word or less are zero/sign-extended and
8197 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8198 LONGEST val = unpack_long (type, valbuf);
8200 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8201 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8205 /* Integral values greater than one word are stored in consecutive
8206 registers starting with r0. This will always be a multiple of
8207 the regiser size. */
8208 int len = TYPE_LENGTH (type);
8209 int regno = ARM_A1_REGNUM;
8213 regcache_cooked_write (regs, regno++, valbuf);
8214 len -= INT_REGISTER_SIZE;
8215 valbuf += INT_REGISTER_SIZE;
8221 /* For a structure or union the behaviour is as if the value had
8222 been stored to word-aligned memory and then loaded into
8223 registers with 32-bit load instruction(s). */
8224 int len = TYPE_LENGTH (type);
8225 int regno = ARM_A1_REGNUM;
8226 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8230 memcpy (tmpbuf, valbuf,
8231 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8232 regcache_cooked_write (regs, regno++, tmpbuf);
8233 len -= INT_REGISTER_SIZE;
8234 valbuf += INT_REGISTER_SIZE;
8240 /* Handle function return values. */
8242 static enum return_value_convention
8243 arm_return_value (struct gdbarch *gdbarch, struct value *function,
8244 struct type *valtype, struct regcache *regcache,
8245 gdb_byte *readbuf, const gdb_byte *writebuf)
8247 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8248 struct type *func_type = function ? value_type (function) : NULL;
8249 enum arm_vfp_cprc_base_type vfp_base_type;
8252 if (arm_vfp_abi_for_function (gdbarch, func_type)
8253 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
8255 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
8256 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
8258 for (i = 0; i < vfp_base_count; i++)
8260 if (reg_char == 'q')
8263 arm_neon_quad_write (gdbarch, regcache, i,
8264 writebuf + i * unit_length);
8267 arm_neon_quad_read (gdbarch, regcache, i,
8268 readbuf + i * unit_length);
8275 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
8276 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8279 regcache_cooked_write (regcache, regnum,
8280 writebuf + i * unit_length);
8282 regcache_cooked_read (regcache, regnum,
8283 readbuf + i * unit_length);
8286 return RETURN_VALUE_REGISTER_CONVENTION;
8289 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
8290 || TYPE_CODE (valtype) == TYPE_CODE_UNION
8291 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
8293 if (tdep->struct_return == pcc_struct_return
8294 || arm_return_in_memory (gdbarch, valtype))
8295 return RETURN_VALUE_STRUCT_CONVENTION;
8297 else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX)
8299 if (arm_return_in_memory (gdbarch, valtype))
8300 return RETURN_VALUE_STRUCT_CONVENTION;
8304 arm_store_return_value (valtype, regcache, writebuf);
8307 arm_extract_return_value (valtype, regcache, readbuf);
8309 return RETURN_VALUE_REGISTER_CONVENTION;
8314 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
8316 struct gdbarch *gdbarch = get_frame_arch (frame);
8317 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8318 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8320 gdb_byte buf[INT_REGISTER_SIZE];
8322 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
8324 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
8328 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
8332 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8333 return the target PC. Otherwise return 0. */
8336 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
8340 CORE_ADDR start_addr;
8342 /* Find the starting address and name of the function containing the PC. */
8343 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
8345 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8347 start_addr = arm_skip_bx_reg (frame, pc);
8348 if (start_addr != 0)
8354 /* If PC is in a Thumb call or return stub, return the address of the
8355 target PC, which is in a register. The thunk functions are called
8356 _call_via_xx, where x is the register name. The possible names
8357 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8358 functions, named __ARM_call_via_r[0-7]. */
8359 if (startswith (name, "_call_via_")
8360 || startswith (name, "__ARM_call_via_"))
8362 /* Use the name suffix to determine which register contains the
8364 static char *table[15] =
8365 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8366 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8369 int offset = strlen (name) - 2;
8371 for (regno = 0; regno <= 14; regno++)
8372 if (strcmp (&name[offset], table[regno]) == 0)
8373 return get_frame_register_unsigned (frame, regno);
8376 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8377 non-interworking calls to foo. We could decode the stubs
8378 to find the target but it's easier to use the symbol table. */
8379 namelen = strlen (name);
8380 if (name[0] == '_' && name[1] == '_'
8381 && ((namelen > 2 + strlen ("_from_thumb")
8382 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
8383 || (namelen > 2 + strlen ("_from_arm")
8384 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
8387 int target_len = namelen - 2;
8388 struct bound_minimal_symbol minsym;
8389 struct objfile *objfile;
8390 struct obj_section *sec;
8392 if (name[namelen - 1] == 'b')
8393 target_len -= strlen ("_from_thumb");
8395 target_len -= strlen ("_from_arm");
8397 target_name = (char *) alloca (target_len + 1);
8398 memcpy (target_name, name + 2, target_len);
8399 target_name[target_len] = '\0';
8401 sec = find_pc_section (pc);
8402 objfile = (sec == NULL) ? NULL : sec->objfile;
8403 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
8404 if (minsym.minsym != NULL)
8405 return BMSYMBOL_VALUE_ADDRESS (minsym);
8410 return 0; /* not a stub */
8414 set_arm_command (char *args, int from_tty)
8416 printf_unfiltered (_("\
8417 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8418 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
8422 show_arm_command (char *args, int from_tty)
8424 cmd_show_list (showarmcmdlist, from_tty, "");
8428 arm_update_current_architecture (void)
8430 struct gdbarch_info info;
8432 /* If the current architecture is not ARM, we have nothing to do. */
8433 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
8436 /* Update the architecture. */
8437 gdbarch_info_init (&info);
8439 if (!gdbarch_update_p (info))
8440 internal_error (__FILE__, __LINE__, _("could not update architecture"));
8444 set_fp_model_sfunc (char *args, int from_tty,
8445 struct cmd_list_element *c)
8449 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
8450 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
8452 arm_fp_model = (enum arm_float_model) fp_model;
8456 if (fp_model == ARM_FLOAT_LAST)
8457 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
8460 arm_update_current_architecture ();
8464 show_fp_model (struct ui_file *file, int from_tty,
8465 struct cmd_list_element *c, const char *value)
8467 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8469 if (arm_fp_model == ARM_FLOAT_AUTO
8470 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8471 fprintf_filtered (file, _("\
8472 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8473 fp_model_strings[tdep->fp_model]);
8475 fprintf_filtered (file, _("\
8476 The current ARM floating point model is \"%s\".\n"),
8477 fp_model_strings[arm_fp_model]);
8481 arm_set_abi (char *args, int from_tty,
8482 struct cmd_list_element *c)
8486 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
8487 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
8489 arm_abi_global = (enum arm_abi_kind) arm_abi;
8493 if (arm_abi == ARM_ABI_LAST)
8494 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
8497 arm_update_current_architecture ();
8501 arm_show_abi (struct ui_file *file, int from_tty,
8502 struct cmd_list_element *c, const char *value)
8504 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8506 if (arm_abi_global == ARM_ABI_AUTO
8507 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8508 fprintf_filtered (file, _("\
8509 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8510 arm_abi_strings[tdep->arm_abi]);
8512 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
8517 arm_show_fallback_mode (struct ui_file *file, int from_tty,
8518 struct cmd_list_element *c, const char *value)
8520 fprintf_filtered (file,
8521 _("The current execution mode assumed "
8522 "(when symbols are unavailable) is \"%s\".\n"),
8523 arm_fallback_mode_string);
8527 arm_show_force_mode (struct ui_file *file, int from_tty,
8528 struct cmd_list_element *c, const char *value)
8530 fprintf_filtered (file,
8531 _("The current execution mode assumed "
8532 "(even when symbols are available) is \"%s\".\n"),
8533 arm_force_mode_string);
8536 /* If the user changes the register disassembly style used for info
8537 register and other commands, we have to also switch the style used
8538 in opcodes for disassembly output. This function is run in the "set
8539 arm disassembly" command, and does that. */
8542 set_disassembly_style_sfunc (char *args, int from_tty,
8543 struct cmd_list_element *c)
8545 set_disassembly_style ();
8548 /* Return the ARM register name corresponding to register I. */
8550 arm_register_name (struct gdbarch *gdbarch, int i)
8552 const int num_regs = gdbarch_num_regs (gdbarch);
8554 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
8555 && i >= num_regs && i < num_regs + 32)
8557 static const char *const vfp_pseudo_names[] = {
8558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8559 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8560 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8561 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8564 return vfp_pseudo_names[i - num_regs];
8567 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
8568 && i >= num_regs + 32 && i < num_regs + 32 + 16)
8570 static const char *const neon_pseudo_names[] = {
8571 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8572 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8575 return neon_pseudo_names[i - num_regs - 32];
8578 if (i >= ARRAY_SIZE (arm_register_names))
8579 /* These registers are only supported on targets which supply
8580 an XML description. */
8583 return arm_register_names[i];
8587 set_disassembly_style (void)
8591 /* Find the style that the user wants. */
8592 for (current = 0; current < num_disassembly_options; current++)
8593 if (disassembly_style == valid_disassembly_styles[current])
8595 gdb_assert (current < num_disassembly_options);
8597 /* Synchronize the disassembler. */
8598 set_arm_regname_option (current);
8601 /* Test whether the coff symbol specific value corresponds to a Thumb
8605 coff_sym_is_thumb (int val)
8607 return (val == C_THUMBEXT
8608 || val == C_THUMBSTAT
8609 || val == C_THUMBEXTFUNC
8610 || val == C_THUMBSTATFUNC
8611 || val == C_THUMBLABEL);
8614 /* arm_coff_make_msymbol_special()
8615 arm_elf_make_msymbol_special()
8617 These functions test whether the COFF or ELF symbol corresponds to
8618 an address in thumb code, and set a "special" bit in a minimal
8619 symbol to indicate that it does. */
8622 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
8624 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
8626 if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal)
8627 == ST_BRANCH_TO_THUMB)
8628 MSYMBOL_SET_SPECIAL (msym);
8632 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
8634 if (coff_sym_is_thumb (val))
8635 MSYMBOL_SET_SPECIAL (msym);
8639 arm_objfile_data_free (struct objfile *objfile, void *arg)
8641 struct arm_per_objfile *data = (struct arm_per_objfile *) arg;
8644 for (i = 0; i < objfile->obfd->section_count; i++)
8645 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
8649 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
8652 const char *name = bfd_asymbol_name (sym);
8653 struct arm_per_objfile *data;
8654 VEC(arm_mapping_symbol_s) **map_p;
8655 struct arm_mapping_symbol new_map_sym;
8657 gdb_assert (name[0] == '$');
8658 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
8661 data = (struct arm_per_objfile *) objfile_data (objfile,
8662 arm_objfile_data_key);
8665 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
8666 struct arm_per_objfile);
8667 set_objfile_data (objfile, arm_objfile_data_key, data);
8668 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
8669 objfile->obfd->section_count,
8670 VEC(arm_mapping_symbol_s) *);
8672 map_p = &data->section_maps[bfd_get_section (sym)->index];
8674 new_map_sym.value = sym->value;
8675 new_map_sym.type = name[1];
8677 /* Assume that most mapping symbols appear in order of increasing
8678 value. If they were randomly distributed, it would be faster to
8679 always push here and then sort at first use. */
8680 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
8682 struct arm_mapping_symbol *prev_map_sym;
8684 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
8685 if (prev_map_sym->value >= sym->value)
8688 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
8689 arm_compare_mapping_symbols);
8690 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
8695 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
8699 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
8701 struct gdbarch *gdbarch = get_regcache_arch (regcache);
8702 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
8704 /* If necessary, set the T bit. */
8707 ULONGEST val, t_bit;
8708 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
8709 t_bit = arm_psr_thumb_bit (gdbarch);
8710 if (arm_pc_is_thumb (gdbarch, pc))
8711 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8714 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8719 /* Read the contents of a NEON quad register, by reading from two
8720 double registers. This is used to implement the quad pseudo
8721 registers, and for argument passing in case the quad registers are
8722 missing; vectors are passed in quad registers when using the VFP
8723 ABI, even if a NEON unit is not present. REGNUM is the index of
8724 the quad register, in [0, 15]. */
8726 static enum register_status
8727 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
8728 int regnum, gdb_byte *buf)
8731 gdb_byte reg_buf[8];
8732 int offset, double_regnum;
8733 enum register_status status;
8735 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8736 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8739 /* d0 is always the least significant half of q0. */
8740 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8745 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8746 if (status != REG_VALID)
8748 memcpy (buf + offset, reg_buf, 8);
8750 offset = 8 - offset;
8751 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
8752 if (status != REG_VALID)
8754 memcpy (buf + offset, reg_buf, 8);
8759 static enum register_status
8760 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
8761 int regnum, gdb_byte *buf)
8763 const int num_regs = gdbarch_num_regs (gdbarch);
8765 gdb_byte reg_buf[8];
8766 int offset, double_regnum;
8768 gdb_assert (regnum >= num_regs);
8771 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8772 /* Quad-precision register. */
8773 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
8776 enum register_status status;
8778 /* Single-precision register. */
8779 gdb_assert (regnum < 32);
8781 /* s0 is always the least significant half of d0. */
8782 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8783 offset = (regnum & 1) ? 0 : 4;
8785 offset = (regnum & 1) ? 4 : 0;
8787 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8788 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8791 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8792 if (status == REG_VALID)
8793 memcpy (buf, reg_buf + offset, 4);
8798 /* Store the contents of BUF to a NEON quad register, by writing to
8799 two double registers. This is used to implement the quad pseudo
8800 registers, and for argument passing in case the quad registers are
8801 missing; vectors are passed in quad registers when using the VFP
8802 ABI, even if a NEON unit is not present. REGNUM is the index
8803 of the quad register, in [0, 15]. */
8806 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
8807 int regnum, const gdb_byte *buf)
8810 int offset, double_regnum;
8812 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8813 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8816 /* d0 is always the least significant half of q0. */
8817 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8822 regcache_raw_write (regcache, double_regnum, buf + offset);
8823 offset = 8 - offset;
8824 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
8828 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
8829 int regnum, const gdb_byte *buf)
8831 const int num_regs = gdbarch_num_regs (gdbarch);
8833 gdb_byte reg_buf[8];
8834 int offset, double_regnum;
8836 gdb_assert (regnum >= num_regs);
8839 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8840 /* Quad-precision register. */
8841 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
8844 /* Single-precision register. */
8845 gdb_assert (regnum < 32);
8847 /* s0 is always the least significant half of d0. */
8848 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8849 offset = (regnum & 1) ? 0 : 4;
8851 offset = (regnum & 1) ? 4 : 0;
8853 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8854 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8857 regcache_raw_read (regcache, double_regnum, reg_buf);
8858 memcpy (reg_buf + offset, buf, 4);
8859 regcache_raw_write (regcache, double_regnum, reg_buf);
8863 static struct value *
8864 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
8866 const int *reg_p = (const int *) baton;
8867 return value_of_register (*reg_p, frame);
8870 static enum gdb_osabi
8871 arm_elf_osabi_sniffer (bfd *abfd)
8873 unsigned int elfosabi;
8874 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
8876 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
8878 if (elfosabi == ELFOSABI_ARM)
8879 /* GNU tools use this value. Check note sections in this case,
8881 bfd_map_over_sections (abfd,
8882 generic_elf_osabi_sniff_abi_tag_sections,
8885 /* Anything else will be handled by the generic ELF sniffer. */
8890 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
8891 struct reggroup *group)
8893 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8894 this, FPS register belongs to save_regroup, restore_reggroup, and
8895 all_reggroup, of course. */
8896 if (regnum == ARM_FPS_REGNUM)
8897 return (group == float_reggroup
8898 || group == save_reggroup
8899 || group == restore_reggroup
8900 || group == all_reggroup);
8902 return default_register_reggroup_p (gdbarch, regnum, group);
8906 /* For backward-compatibility we allow two 'g' packet lengths with
8907 the remote protocol depending on whether FPA registers are
8908 supplied. M-profile targets do not have FPA registers, but some
8909 stubs already exist in the wild which use a 'g' packet which
8910 supplies them albeit with dummy values. The packet format which
8911 includes FPA registers should be considered deprecated for
8912 M-profile targets. */
8915 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
8917 if (gdbarch_tdep (gdbarch)->is_m)
8919 /* If we know from the executable this is an M-profile target,
8920 cater for remote targets whose register set layout is the
8921 same as the FPA layout. */
8922 register_remote_g_packet_guess (gdbarch,
8923 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8924 (16 * INT_REGISTER_SIZE)
8925 + (8 * FP_REGISTER_SIZE)
8926 + (2 * INT_REGISTER_SIZE),
8927 tdesc_arm_with_m_fpa_layout);
8929 /* The regular M-profile layout. */
8930 register_remote_g_packet_guess (gdbarch,
8931 /* r0-r12,sp,lr,pc; xpsr */
8932 (16 * INT_REGISTER_SIZE)
8933 + INT_REGISTER_SIZE,
8936 /* M-profile plus M4F VFP. */
8937 register_remote_g_packet_guess (gdbarch,
8938 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8939 (16 * INT_REGISTER_SIZE)
8940 + (16 * VFP_REGISTER_SIZE)
8941 + (2 * INT_REGISTER_SIZE),
8942 tdesc_arm_with_m_vfp_d16);
8945 /* Otherwise we don't have a useful guess. */
8948 /* Implement the code_of_frame_writable gdbarch method. */
8951 arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame)
8953 if (gdbarch_tdep (gdbarch)->is_m
8954 && get_frame_type (frame) == SIGTRAMP_FRAME)
8956 /* M-profile exception frames return to some magic PCs, where
8957 isn't writable at all. */
8965 /* Initialize the current architecture based on INFO. If possible,
8966 re-use an architecture from ARCHES, which is a list of
8967 architectures already created during this debugging session.
8969 Called e.g. at program startup, when reading a core file, and when
8970 reading a binary file. */
8972 static struct gdbarch *
8973 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8975 struct gdbarch_tdep *tdep;
8976 struct gdbarch *gdbarch;
8977 struct gdbarch_list *best_arch;
8978 enum arm_abi_kind arm_abi = arm_abi_global;
8979 enum arm_float_model fp_model = arm_fp_model;
8980 struct tdesc_arch_data *tdesc_data = NULL;
8982 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
8983 int have_wmmx_registers = 0;
8985 int have_fpa_registers = 1;
8986 const struct target_desc *tdesc = info.target_desc;
8988 /* If we have an object to base this architecture on, try to determine
8991 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
8993 int ei_osabi, e_flags;
8995 switch (bfd_get_flavour (info.abfd))
8997 case bfd_target_aout_flavour:
8998 /* Assume it's an old APCS-style ABI. */
8999 arm_abi = ARM_ABI_APCS;
9002 case bfd_target_coff_flavour:
9003 /* Assume it's an old APCS-style ABI. */
9005 arm_abi = ARM_ABI_APCS;
9008 case bfd_target_elf_flavour:
9009 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9010 e_flags = elf_elfheader (info.abfd)->e_flags;
9012 if (ei_osabi == ELFOSABI_ARM)
9014 /* GNU tools used to use this value, but do not for EABI
9015 objects. There's nowhere to tag an EABI version
9016 anyway, so assume APCS. */
9017 arm_abi = ARM_ABI_APCS;
9019 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
9021 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9022 int attr_arch, attr_profile;
9026 case EF_ARM_EABI_UNKNOWN:
9027 /* Assume GNU tools. */
9028 arm_abi = ARM_ABI_APCS;
9031 case EF_ARM_EABI_VER4:
9032 case EF_ARM_EABI_VER5:
9033 arm_abi = ARM_ABI_AAPCS;
9034 /* EABI binaries default to VFP float ordering.
9035 They may also contain build attributes that can
9036 be used to identify if the VFP argument-passing
9038 if (fp_model == ARM_FLOAT_AUTO)
9041 switch (bfd_elf_get_obj_attr_int (info.abfd,
9045 case AEABI_VFP_args_base:
9046 /* "The user intended FP parameter/result
9047 passing to conform to AAPCS, base
9049 fp_model = ARM_FLOAT_SOFT_VFP;
9051 case AEABI_VFP_args_vfp:
9052 /* "The user intended FP parameter/result
9053 passing to conform to AAPCS, VFP
9055 fp_model = ARM_FLOAT_VFP;
9057 case AEABI_VFP_args_toolchain:
9058 /* "The user intended FP parameter/result
9059 passing to conform to tool chain-specific
9060 conventions" - we don't know any such
9061 conventions, so leave it as "auto". */
9063 case AEABI_VFP_args_compatible:
9064 /* "Code is compatible with both the base
9065 and VFP variants; the user did not permit
9066 non-variadic functions to pass FP
9067 parameters/results" - leave it as
9071 /* Attribute value not mentioned in the
9072 November 2012 ABI, so leave it as
9077 fp_model = ARM_FLOAT_SOFT_VFP;
9083 /* Leave it as "auto". */
9084 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9089 /* Detect M-profile programs. This only works if the
9090 executable file includes build attributes; GCC does
9091 copy them to the executable, but e.g. RealView does
9093 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9095 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9097 Tag_CPU_arch_profile);
9098 /* GCC specifies the profile for v6-M; RealView only
9099 specifies the profile for architectures starting with
9100 V7 (as opposed to architectures with a tag
9101 numerically greater than TAG_CPU_ARCH_V7). */
9102 if (!tdesc_has_registers (tdesc)
9103 && (attr_arch == TAG_CPU_ARCH_V6_M
9104 || attr_arch == TAG_CPU_ARCH_V6S_M
9105 || attr_profile == 'M'))
9110 if (fp_model == ARM_FLOAT_AUTO)
9112 int e_flags = elf_elfheader (info.abfd)->e_flags;
9114 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9117 /* Leave it as "auto". Strictly speaking this case
9118 means FPA, but almost nobody uses that now, and
9119 many toolchains fail to set the appropriate bits
9120 for the floating-point model they use. */
9122 case EF_ARM_SOFT_FLOAT:
9123 fp_model = ARM_FLOAT_SOFT_FPA;
9125 case EF_ARM_VFP_FLOAT:
9126 fp_model = ARM_FLOAT_VFP;
9128 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9129 fp_model = ARM_FLOAT_SOFT_VFP;
9134 if (e_flags & EF_ARM_BE8)
9135 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
9140 /* Leave it as "auto". */
9145 /* Check any target description for validity. */
9146 if (tdesc_has_registers (tdesc))
9148 /* For most registers we require GDB's default names; but also allow
9149 the numeric names for sp / lr / pc, as a convenience. */
9150 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
9151 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
9152 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
9154 const struct tdesc_feature *feature;
9157 feature = tdesc_find_feature (tdesc,
9158 "org.gnu.gdb.arm.core");
9159 if (feature == NULL)
9161 feature = tdesc_find_feature (tdesc,
9162 "org.gnu.gdb.arm.m-profile");
9163 if (feature == NULL)
9169 tdesc_data = tdesc_data_alloc ();
9172 for (i = 0; i < ARM_SP_REGNUM; i++)
9173 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9174 arm_register_names[i]);
9175 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9178 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9181 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9185 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9186 ARM_PS_REGNUM, "xpsr");
9188 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9189 ARM_PS_REGNUM, "cpsr");
9193 tdesc_data_cleanup (tdesc_data);
9197 feature = tdesc_find_feature (tdesc,
9198 "org.gnu.gdb.arm.fpa");
9199 if (feature != NULL)
9202 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9203 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9204 arm_register_names[i]);
9207 tdesc_data_cleanup (tdesc_data);
9212 have_fpa_registers = 0;
9214 feature = tdesc_find_feature (tdesc,
9215 "org.gnu.gdb.xscale.iwmmxt");
9216 if (feature != NULL)
9218 static const char *const iwmmxt_names[] = {
9219 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9220 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9221 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9222 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9226 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9228 &= tdesc_numbered_register (feature, tdesc_data, i,
9229 iwmmxt_names[i - ARM_WR0_REGNUM]);
9231 /* Check for the control registers, but do not fail if they
9233 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9234 tdesc_numbered_register (feature, tdesc_data, i,
9235 iwmmxt_names[i - ARM_WR0_REGNUM]);
9237 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9239 &= tdesc_numbered_register (feature, tdesc_data, i,
9240 iwmmxt_names[i - ARM_WR0_REGNUM]);
9244 tdesc_data_cleanup (tdesc_data);
9248 have_wmmx_registers = 1;
9251 /* If we have a VFP unit, check whether the single precision registers
9252 are present. If not, then we will synthesize them as pseudo
9254 feature = tdesc_find_feature (tdesc,
9255 "org.gnu.gdb.arm.vfp");
9256 if (feature != NULL)
9258 static const char *const vfp_double_names[] = {
9259 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9260 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9261 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9262 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9265 /* Require the double precision registers. There must be either
9268 for (i = 0; i < 32; i++)
9270 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9272 vfp_double_names[i]);
9276 if (!valid_p && i == 16)
9279 /* Also require FPSCR. */
9280 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9281 ARM_FPSCR_REGNUM, "fpscr");
9284 tdesc_data_cleanup (tdesc_data);
9288 if (tdesc_unnumbered_register (feature, "s0") == 0)
9289 have_vfp_pseudos = 1;
9291 vfp_register_count = i;
9293 /* If we have VFP, also check for NEON. The architecture allows
9294 NEON without VFP (integer vector operations only), but GDB
9295 does not support that. */
9296 feature = tdesc_find_feature (tdesc,
9297 "org.gnu.gdb.arm.neon");
9298 if (feature != NULL)
9300 /* NEON requires 32 double-precision registers. */
9303 tdesc_data_cleanup (tdesc_data);
9307 /* If there are quad registers defined by the stub, use
9308 their type; otherwise (normally) provide them with
9309 the default type. */
9310 if (tdesc_unnumbered_register (feature, "q0") == 0)
9311 have_neon_pseudos = 1;
9318 /* If there is already a candidate, use it. */
9319 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
9321 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
9323 if (arm_abi != ARM_ABI_AUTO
9324 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
9327 if (fp_model != ARM_FLOAT_AUTO
9328 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
9331 /* There are various other properties in tdep that we do not
9332 need to check here: those derived from a target description,
9333 since gdbarches with a different target description are
9334 automatically disqualified. */
9336 /* Do check is_m, though, since it might come from the binary. */
9337 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
9340 /* Found a match. */
9344 if (best_arch != NULL)
9346 if (tdesc_data != NULL)
9347 tdesc_data_cleanup (tdesc_data);
9348 return best_arch->gdbarch;
9351 tdep = XCNEW (struct gdbarch_tdep);
9352 gdbarch = gdbarch_alloc (&info, tdep);
9354 /* Record additional information about the architecture we are defining.
9355 These are gdbarch discriminators, like the OSABI. */
9356 tdep->arm_abi = arm_abi;
9357 tdep->fp_model = fp_model;
9359 tdep->have_fpa_registers = have_fpa_registers;
9360 tdep->have_wmmx_registers = have_wmmx_registers;
9361 gdb_assert (vfp_register_count == 0
9362 || vfp_register_count == 16
9363 || vfp_register_count == 32);
9364 tdep->vfp_register_count = vfp_register_count;
9365 tdep->have_vfp_pseudos = have_vfp_pseudos;
9366 tdep->have_neon_pseudos = have_neon_pseudos;
9367 tdep->have_neon = have_neon;
9369 arm_register_g_packet_guesses (gdbarch);
9372 switch (info.byte_order_for_code)
9374 case BFD_ENDIAN_BIG:
9375 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
9376 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
9377 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
9378 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
9382 case BFD_ENDIAN_LITTLE:
9383 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
9384 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
9385 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
9386 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
9391 internal_error (__FILE__, __LINE__,
9392 _("arm_gdbarch_init: bad byte order for float format"));
9395 /* On ARM targets char defaults to unsigned. */
9396 set_gdbarch_char_signed (gdbarch, 0);
9398 /* Note: for displaced stepping, this includes the breakpoint, and one word
9399 of additional scratch space. This setting isn't used for anything beside
9400 displaced stepping at present. */
9401 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
9403 /* This should be low enough for everything. */
9404 tdep->lowest_pc = 0x20;
9405 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
9407 /* The default, for both APCS and AAPCS, is to return small
9408 structures in registers. */
9409 tdep->struct_return = reg_struct_return;
9411 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
9412 set_gdbarch_frame_align (gdbarch, arm_frame_align);
9415 set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable);
9417 set_gdbarch_write_pc (gdbarch, arm_write_pc);
9419 /* Frame handling. */
9420 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
9421 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
9422 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
9424 frame_base_set_default (gdbarch, &arm_normal_base);
9426 /* Address manipulation. */
9427 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
9429 /* Advance PC across function entry code. */
9430 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
9432 /* Detect whether PC is at a point where the stack has been destroyed. */
9433 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
9435 /* Skip trampolines. */
9436 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
9438 /* The stack grows downward. */
9439 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
9441 /* Breakpoint manipulation. */
9442 set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc);
9443 set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind);
9444 set_gdbarch_breakpoint_kind_from_current_state (gdbarch,
9445 arm_breakpoint_kind_from_current_state);
9447 /* Information about registers, etc. */
9448 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
9449 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
9450 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
9451 set_gdbarch_register_type (gdbarch, arm_register_type);
9452 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
9454 /* This "info float" is FPA-specific. Use the generic version if we
9456 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
9457 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
9459 /* Internal <-> external register number maps. */
9460 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
9461 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
9463 set_gdbarch_register_name (gdbarch, arm_register_name);
9465 /* Returning results. */
9466 set_gdbarch_return_value (gdbarch, arm_return_value);
9469 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
9471 /* Minsymbol frobbing. */
9472 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
9473 set_gdbarch_coff_make_msymbol_special (gdbarch,
9474 arm_coff_make_msymbol_special);
9475 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
9477 /* Thumb-2 IT block support. */
9478 set_gdbarch_adjust_breakpoint_address (gdbarch,
9479 arm_adjust_breakpoint_address);
9481 /* Virtual tables. */
9482 set_gdbarch_vbit_in_delta (gdbarch, 1);
9484 /* Hook in the ABI-specific overrides, if they have been registered. */
9485 gdbarch_init_osabi (info, gdbarch);
9487 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
9489 /* Add some default predicates. */
9491 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
9492 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
9493 dwarf2_append_unwinders (gdbarch);
9494 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
9495 frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind);
9496 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
9498 /* Now we have tuned the configuration, set a few final things,
9499 based on what the OS ABI has told us. */
9501 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9502 binaries are always marked. */
9503 if (tdep->arm_abi == ARM_ABI_AUTO)
9504 tdep->arm_abi = ARM_ABI_APCS;
9506 /* Watchpoints are not steppable. */
9507 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9509 /* We used to default to FPA for generic ARM, but almost nobody
9510 uses that now, and we now provide a way for the user to force
9511 the model. So default to the most useful variant. */
9512 if (tdep->fp_model == ARM_FLOAT_AUTO)
9513 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
9515 if (tdep->jb_pc >= 0)
9516 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
9518 /* Floating point sizes and format. */
9519 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
9520 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
9522 set_gdbarch_double_format
9523 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9524 set_gdbarch_long_double_format
9525 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9529 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
9530 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
9533 if (have_vfp_pseudos)
9535 /* NOTE: These are the only pseudo registers used by
9536 the ARM target at the moment. If more are added, a
9537 little more care in numbering will be needed. */
9539 int num_pseudos = 32;
9540 if (have_neon_pseudos)
9542 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
9543 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
9544 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
9549 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
9551 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
9553 /* Override tdesc_register_type to adjust the types of VFP
9554 registers for NEON. */
9555 set_gdbarch_register_type (gdbarch, arm_register_type);
9558 /* Add standard register aliases. We add aliases even for those
9559 nanes which are used by the current architecture - it's simpler,
9560 and does no harm, since nothing ever lists user registers. */
9561 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
9562 user_reg_add (gdbarch, arm_register_aliases[i].name,
9563 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
9569 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
9571 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9576 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9577 (unsigned long) tdep->lowest_pc);
9580 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
9583 _initialize_arm_tdep (void)
9585 struct ui_file *stb;
9587 const char *setname;
9588 const char *setdesc;
9589 const char *const *regnames;
9591 static char *helptext;
9592 char regdesc[1024], *rdptr = regdesc;
9593 size_t rest = sizeof (regdesc);
9595 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
9597 arm_objfile_data_key
9598 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
9600 /* Add ourselves to objfile event chain. */
9601 observer_attach_new_objfile (arm_exidx_new_objfile);
9603 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
9605 /* Register an ELF OS ABI sniffer for ARM binaries. */
9606 gdbarch_register_osabi_sniffer (bfd_arch_arm,
9607 bfd_target_elf_flavour,
9608 arm_elf_osabi_sniffer);
9610 /* Initialize the standard target descriptions. */
9611 initialize_tdesc_arm_with_m ();
9612 initialize_tdesc_arm_with_m_fpa_layout ();
9613 initialize_tdesc_arm_with_m_vfp_d16 ();
9614 initialize_tdesc_arm_with_iwmmxt ();
9615 initialize_tdesc_arm_with_vfpv2 ();
9616 initialize_tdesc_arm_with_vfpv3 ();
9617 initialize_tdesc_arm_with_neon ();
9619 /* Get the number of possible sets of register names defined in opcodes. */
9620 num_disassembly_options = get_arm_regname_num_options ();
9622 /* Add root prefix command for all "set arm"/"show arm" commands. */
9623 add_prefix_cmd ("arm", no_class, set_arm_command,
9624 _("Various ARM-specific commands."),
9625 &setarmcmdlist, "set arm ", 0, &setlist);
9627 add_prefix_cmd ("arm", no_class, show_arm_command,
9628 _("Various ARM-specific commands."),
9629 &showarmcmdlist, "show arm ", 0, &showlist);
9631 /* Sync the opcode insn printer with our register viewer. */
9632 parse_arm_disassembler_option ("reg-names-std");
9634 /* Initialize the array that will be passed to
9635 add_setshow_enum_cmd(). */
9636 valid_disassembly_styles = XNEWVEC (const char *,
9637 num_disassembly_options + 1);
9638 for (i = 0; i < num_disassembly_options; i++)
9640 get_arm_regnames (i, &setname, &setdesc, ®names);
9641 valid_disassembly_styles[i] = setname;
9642 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
9645 /* When we find the default names, tell the disassembler to use
9647 if (!strcmp (setname, "std"))
9649 disassembly_style = setname;
9650 set_arm_regname_option (i);
9653 /* Mark the end of valid options. */
9654 valid_disassembly_styles[num_disassembly_options] = NULL;
9656 /* Create the help text. */
9657 stb = mem_fileopen ();
9658 fprintf_unfiltered (stb, "%s%s%s",
9659 _("The valid values are:\n"),
9661 _("The default is \"std\"."));
9662 helptext = ui_file_xstrdup (stb, NULL);
9663 ui_file_delete (stb);
9665 add_setshow_enum_cmd("disassembler", no_class,
9666 valid_disassembly_styles, &disassembly_style,
9667 _("Set the disassembly style."),
9668 _("Show the disassembly style."),
9670 set_disassembly_style_sfunc,
9671 NULL, /* FIXME: i18n: The disassembly style is
9673 &setarmcmdlist, &showarmcmdlist);
9675 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
9676 _("Set usage of ARM 32-bit mode."),
9677 _("Show usage of ARM 32-bit mode."),
9678 _("When off, a 26-bit PC will be used."),
9680 NULL, /* FIXME: i18n: Usage of ARM 32-bit
9682 &setarmcmdlist, &showarmcmdlist);
9684 /* Add a command to allow the user to force the FPU model. */
9685 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
9686 _("Set the floating point type."),
9687 _("Show the floating point type."),
9688 _("auto - Determine the FP typefrom the OS-ABI.\n\
9689 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9690 fpa - FPA co-processor (GCC compiled).\n\
9691 softvfp - Software FP with pure-endian doubles.\n\
9692 vfp - VFP co-processor."),
9693 set_fp_model_sfunc, show_fp_model,
9694 &setarmcmdlist, &showarmcmdlist);
9696 /* Add a command to allow the user to force the ABI. */
9697 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
9700 NULL, arm_set_abi, arm_show_abi,
9701 &setarmcmdlist, &showarmcmdlist);
9703 /* Add two commands to allow the user to force the assumed
9705 add_setshow_enum_cmd ("fallback-mode", class_support,
9706 arm_mode_strings, &arm_fallback_mode_string,
9707 _("Set the mode assumed when symbols are unavailable."),
9708 _("Show the mode assumed when symbols are unavailable."),
9709 NULL, NULL, arm_show_fallback_mode,
9710 &setarmcmdlist, &showarmcmdlist);
9711 add_setshow_enum_cmd ("force-mode", class_support,
9712 arm_mode_strings, &arm_force_mode_string,
9713 _("Set the mode assumed even when symbols are available."),
9714 _("Show the mode assumed even when symbols are available."),
9715 NULL, NULL, arm_show_force_mode,
9716 &setarmcmdlist, &showarmcmdlist);
9718 /* Debugging flag. */
9719 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
9720 _("Set ARM debugging."),
9721 _("Show ARM debugging."),
9722 _("When on, arm-specific debugging is enabled."),
9724 NULL, /* FIXME: i18n: "ARM debugging is %s. */
9725 &setdebuglist, &showdebuglist);
9728 /* ARM-reversible process record data structures. */
9730 #define ARM_INSN_SIZE_BYTES 4
9731 #define THUMB_INSN_SIZE_BYTES 2
9732 #define THUMB2_INSN_SIZE_BYTES 4
9735 /* Position of the bit within a 32-bit ARM instruction
9736 that defines whether the instruction is a load or store. */
9737 #define INSN_S_L_BIT_NUM 20
9739 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9742 unsigned int reg_len = LENGTH; \
9745 REGS = XNEWVEC (uint32_t, reg_len); \
9746 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9751 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9754 unsigned int mem_len = LENGTH; \
9757 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9758 memcpy(&MEMS->len, &RECORD_BUF[0], \
9759 sizeof(struct arm_mem_r) * LENGTH); \
9764 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9765 #define INSN_RECORDED(ARM_RECORD) \
9766 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9768 /* ARM memory record structure. */
9771 uint32_t len; /* Record length. */
9772 uint32_t addr; /* Memory address. */
9775 /* ARM instruction record contains opcode of current insn
9776 and execution state (before entry to decode_insn()),
9777 contains list of to-be-modified registers and
9778 memory blocks (on return from decode_insn()). */
9780 typedef struct insn_decode_record_t
9782 struct gdbarch *gdbarch;
9783 struct regcache *regcache;
9784 CORE_ADDR this_addr; /* Address of the insn being decoded. */
9785 uint32_t arm_insn; /* Should accommodate thumb. */
9786 uint32_t cond; /* Condition code. */
9787 uint32_t opcode; /* Insn opcode. */
9788 uint32_t decode; /* Insn decode bits. */
9789 uint32_t mem_rec_count; /* No of mem records. */
9790 uint32_t reg_rec_count; /* No of reg records. */
9791 uint32_t *arm_regs; /* Registers to be saved for this record. */
9792 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
9793 } insn_decode_record;
9796 /* Checks ARM SBZ and SBO mandatory fields. */
9799 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
9801 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
9820 enum arm_record_result
9822 ARM_RECORD_SUCCESS = 0,
9823 ARM_RECORD_FAILURE = 1
9830 } arm_record_strx_t;
9841 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
9842 uint32_t *record_buf_mem, arm_record_strx_t str_type)
9845 struct regcache *reg_cache = arm_insn_r->regcache;
9846 ULONGEST u_regval[2]= {0};
9848 uint32_t reg_src1 = 0, reg_src2 = 0;
9849 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
9851 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
9852 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
9854 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
9856 /* 1) Handle misc store, immediate offset. */
9857 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9858 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9859 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9860 regcache_raw_read_unsigned (reg_cache, reg_src1,
9862 if (ARM_PC_REGNUM == reg_src1)
9864 /* If R15 was used as Rn, hence current PC+8. */
9865 u_regval[0] = u_regval[0] + 8;
9867 offset_8 = (immed_high << 4) | immed_low;
9868 /* Calculate target store address. */
9869 if (14 == arm_insn_r->opcode)
9871 tgt_mem_addr = u_regval[0] + offset_8;
9875 tgt_mem_addr = u_regval[0] - offset_8;
9877 if (ARM_RECORD_STRH == str_type)
9879 record_buf_mem[0] = 2;
9880 record_buf_mem[1] = tgt_mem_addr;
9881 arm_insn_r->mem_rec_count = 1;
9883 else if (ARM_RECORD_STRD == str_type)
9885 record_buf_mem[0] = 4;
9886 record_buf_mem[1] = tgt_mem_addr;
9887 record_buf_mem[2] = 4;
9888 record_buf_mem[3] = tgt_mem_addr + 4;
9889 arm_insn_r->mem_rec_count = 2;
9892 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
9894 /* 2) Store, register offset. */
9896 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9898 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9899 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9900 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9903 /* If R15 was used as Rn, hence current PC+8. */
9904 u_regval[0] = u_regval[0] + 8;
9906 /* Calculate target store address, Rn +/- Rm, register offset. */
9907 if (12 == arm_insn_r->opcode)
9909 tgt_mem_addr = u_regval[0] + u_regval[1];
9913 tgt_mem_addr = u_regval[1] - u_regval[0];
9915 if (ARM_RECORD_STRH == str_type)
9917 record_buf_mem[0] = 2;
9918 record_buf_mem[1] = tgt_mem_addr;
9919 arm_insn_r->mem_rec_count = 1;
9921 else if (ARM_RECORD_STRD == str_type)
9923 record_buf_mem[0] = 4;
9924 record_buf_mem[1] = tgt_mem_addr;
9925 record_buf_mem[2] = 4;
9926 record_buf_mem[3] = tgt_mem_addr + 4;
9927 arm_insn_r->mem_rec_count = 2;
9930 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
9931 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9933 /* 3) Store, immediate pre-indexed. */
9934 /* 5) Store, immediate post-indexed. */
9935 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9936 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9937 offset_8 = (immed_high << 4) | immed_low;
9938 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9939 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9940 /* Calculate target store address, Rn +/- Rm, register offset. */
9941 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9943 tgt_mem_addr = u_regval[0] + offset_8;
9947 tgt_mem_addr = u_regval[0] - offset_8;
9949 if (ARM_RECORD_STRH == str_type)
9951 record_buf_mem[0] = 2;
9952 record_buf_mem[1] = tgt_mem_addr;
9953 arm_insn_r->mem_rec_count = 1;
9955 else if (ARM_RECORD_STRD == str_type)
9957 record_buf_mem[0] = 4;
9958 record_buf_mem[1] = tgt_mem_addr;
9959 record_buf_mem[2] = 4;
9960 record_buf_mem[3] = tgt_mem_addr + 4;
9961 arm_insn_r->mem_rec_count = 2;
9963 /* Record Rn also as it changes. */
9964 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9965 arm_insn_r->reg_rec_count = 1;
9967 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
9968 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9970 /* 4) Store, register pre-indexed. */
9971 /* 6) Store, register post -indexed. */
9972 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9973 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9974 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9975 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9976 /* Calculate target store address, Rn +/- Rm, register offset. */
9977 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9979 tgt_mem_addr = u_regval[0] + u_regval[1];
9983 tgt_mem_addr = u_regval[1] - u_regval[0];
9985 if (ARM_RECORD_STRH == str_type)
9987 record_buf_mem[0] = 2;
9988 record_buf_mem[1] = tgt_mem_addr;
9989 arm_insn_r->mem_rec_count = 1;
9991 else if (ARM_RECORD_STRD == str_type)
9993 record_buf_mem[0] = 4;
9994 record_buf_mem[1] = tgt_mem_addr;
9995 record_buf_mem[2] = 4;
9996 record_buf_mem[3] = tgt_mem_addr + 4;
9997 arm_insn_r->mem_rec_count = 2;
9999 /* Record Rn also as it changes. */
10000 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10001 arm_insn_r->reg_rec_count = 1;
10006 /* Handling ARM extension space insns. */
10009 arm_record_extension_space (insn_decode_record *arm_insn_r)
10011 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10012 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10013 uint32_t record_buf[8], record_buf_mem[8];
10014 uint32_t reg_src1 = 0;
10015 struct regcache *reg_cache = arm_insn_r->regcache;
10016 ULONGEST u_regval = 0;
10018 gdb_assert (!INSN_RECORDED(arm_insn_r));
10019 /* Handle unconditional insn extension space. */
10021 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10022 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10023 if (arm_insn_r->cond)
10025 /* PLD has no affect on architectural state, it just affects
10027 if (5 == ((opcode1 & 0xE0) >> 5))
10030 record_buf[0] = ARM_PS_REGNUM;
10031 record_buf[1] = ARM_LR_REGNUM;
10032 arm_insn_r->reg_rec_count = 2;
10034 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10038 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10039 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10042 /* Undefined instruction on ARM V5; need to handle if later
10043 versions define it. */
10046 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10047 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10048 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10050 /* Handle arithmetic insn extension space. */
10051 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10052 && !INSN_RECORDED(arm_insn_r))
10054 /* Handle MLA(S) and MUL(S). */
10055 if (0 <= insn_op1 && 3 >= insn_op1)
10057 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10058 record_buf[1] = ARM_PS_REGNUM;
10059 arm_insn_r->reg_rec_count = 2;
10061 else if (4 <= insn_op1 && 15 >= insn_op1)
10063 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10064 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10065 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10066 record_buf[2] = ARM_PS_REGNUM;
10067 arm_insn_r->reg_rec_count = 3;
10071 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10072 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10073 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10075 /* Handle control insn extension space. */
10077 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10078 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10080 if (!bit (arm_insn_r->arm_insn,25))
10082 if (!bits (arm_insn_r->arm_insn, 4, 7))
10084 if ((0 == insn_op1) || (2 == insn_op1))
10087 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10088 arm_insn_r->reg_rec_count = 1;
10090 else if (1 == insn_op1)
10092 /* CSPR is going to be changed. */
10093 record_buf[0] = ARM_PS_REGNUM;
10094 arm_insn_r->reg_rec_count = 1;
10096 else if (3 == insn_op1)
10098 /* SPSR is going to be changed. */
10099 /* We need to get SPSR value, which is yet to be done. */
10103 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10108 record_buf[0] = ARM_PS_REGNUM;
10109 arm_insn_r->reg_rec_count = 1;
10111 else if (3 == insn_op1)
10114 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10115 arm_insn_r->reg_rec_count = 1;
10118 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10121 record_buf[0] = ARM_PS_REGNUM;
10122 record_buf[1] = ARM_LR_REGNUM;
10123 arm_insn_r->reg_rec_count = 2;
10125 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10127 /* QADD, QSUB, QDADD, QDSUB */
10128 record_buf[0] = ARM_PS_REGNUM;
10129 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10130 arm_insn_r->reg_rec_count = 2;
10132 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10135 record_buf[0] = ARM_PS_REGNUM;
10136 record_buf[1] = ARM_LR_REGNUM;
10137 arm_insn_r->reg_rec_count = 2;
10139 /* Save SPSR also;how? */
10142 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
10143 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
10144 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
10145 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
10148 if (0 == insn_op1 || 1 == insn_op1)
10150 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10151 /* We dont do optimization for SMULW<y> where we
10153 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10154 record_buf[1] = ARM_PS_REGNUM;
10155 arm_insn_r->reg_rec_count = 2;
10157 else if (2 == insn_op1)
10160 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10161 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
10162 arm_insn_r->reg_rec_count = 2;
10164 else if (3 == insn_op1)
10167 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10168 arm_insn_r->reg_rec_count = 1;
10174 /* MSR : immediate form. */
10177 /* CSPR is going to be changed. */
10178 record_buf[0] = ARM_PS_REGNUM;
10179 arm_insn_r->reg_rec_count = 1;
10181 else if (3 == insn_op1)
10183 /* SPSR is going to be changed. */
10184 /* we need to get SPSR value, which is yet to be done */
10190 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10191 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
10192 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
10194 /* Handle load/store insn extension space. */
10196 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
10197 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
10198 && !INSN_RECORDED(arm_insn_r))
10203 /* These insn, changes register and memory as well. */
10204 /* SWP or SWPB insn. */
10205 /* Get memory address given by Rn. */
10206 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10207 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
10208 /* SWP insn ?, swaps word. */
10209 if (8 == arm_insn_r->opcode)
10211 record_buf_mem[0] = 4;
10215 /* SWPB insn, swaps only byte. */
10216 record_buf_mem[0] = 1;
10218 record_buf_mem[1] = u_regval;
10219 arm_insn_r->mem_rec_count = 1;
10220 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10221 arm_insn_r->reg_rec_count = 1;
10223 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10226 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10229 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10232 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10233 record_buf[1] = record_buf[0] + 1;
10234 arm_insn_r->reg_rec_count = 2;
10236 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10239 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10242 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
10244 /* LDRH, LDRSB, LDRSH. */
10245 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10246 arm_insn_r->reg_rec_count = 1;
10251 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
10252 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
10253 && !INSN_RECORDED(arm_insn_r))
10256 /* Handle coprocessor insn extension space. */
10259 /* To be done for ARMv5 and later; as of now we return -1. */
10263 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10264 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10269 /* Handling opcode 000 insns. */
10272 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
10274 struct regcache *reg_cache = arm_insn_r->regcache;
10275 uint32_t record_buf[8], record_buf_mem[8];
10276 ULONGEST u_regval[2] = {0};
10278 uint32_t reg_src1 = 0, reg_dest = 0;
10279 uint32_t opcode1 = 0;
10281 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10282 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10283 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10285 /* Data processing insn /multiply insn. */
10286 if (9 == arm_insn_r->decode
10287 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10288 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
10290 /* Handle multiply instructions. */
10291 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10292 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
10294 /* Handle MLA and MUL. */
10295 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10296 record_buf[1] = ARM_PS_REGNUM;
10297 arm_insn_r->reg_rec_count = 2;
10299 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10301 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10302 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10303 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10304 record_buf[2] = ARM_PS_REGNUM;
10305 arm_insn_r->reg_rec_count = 3;
10308 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10309 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
10311 /* Handle misc load insns, as 20th bit (L = 1). */
10312 /* LDR insn has a capability to do branching, if
10313 MOV LR, PC is precceded by LDR insn having Rn as R15
10314 in that case, it emulates branch and link insn, and hence we
10315 need to save CSPR and PC as well. I am not sure this is right
10316 place; as opcode = 010 LDR insn make this happen, if R15 was
10318 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10319 if (15 != reg_dest)
10321 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10322 arm_insn_r->reg_rec_count = 1;
10326 record_buf[0] = reg_dest;
10327 record_buf[1] = ARM_PS_REGNUM;
10328 arm_insn_r->reg_rec_count = 2;
10331 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10332 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
10333 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10334 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
10336 /* Handle MSR insn. */
10337 if (9 == arm_insn_r->opcode)
10339 /* CSPR is going to be changed. */
10340 record_buf[0] = ARM_PS_REGNUM;
10341 arm_insn_r->reg_rec_count = 1;
10345 /* SPSR is going to be changed. */
10346 /* How to read SPSR value? */
10350 else if (9 == arm_insn_r->decode
10351 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10352 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10354 /* Handling SWP, SWPB. */
10355 /* These insn, changes register and memory as well. */
10356 /* SWP or SWPB insn. */
10358 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10359 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10360 /* SWP insn ?, swaps word. */
10361 if (8 == arm_insn_r->opcode)
10363 record_buf_mem[0] = 4;
10367 /* SWPB insn, swaps only byte. */
10368 record_buf_mem[0] = 1;
10370 record_buf_mem[1] = u_regval[0];
10371 arm_insn_r->mem_rec_count = 1;
10372 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10373 arm_insn_r->reg_rec_count = 1;
10375 else if (3 == arm_insn_r->decode && 0x12 == opcode1
10376 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10378 /* Handle BLX, branch and link/exchange. */
10379 if (9 == arm_insn_r->opcode)
10381 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10382 and R14 stores the return address. */
10383 record_buf[0] = ARM_PS_REGNUM;
10384 record_buf[1] = ARM_LR_REGNUM;
10385 arm_insn_r->reg_rec_count = 2;
10388 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
10390 /* Handle enhanced software breakpoint insn, BKPT. */
10391 /* CPSR is changed to be executed in ARM state, disabling normal
10392 interrupts, entering abort mode. */
10393 /* According to high vector configuration PC is set. */
10394 /* user hit breakpoint and type reverse, in
10395 that case, we need to go back with previous CPSR and
10396 Program Counter. */
10397 record_buf[0] = ARM_PS_REGNUM;
10398 record_buf[1] = ARM_LR_REGNUM;
10399 arm_insn_r->reg_rec_count = 2;
10401 /* Save SPSR also; how? */
10404 else if (11 == arm_insn_r->decode
10405 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10407 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10409 /* Handle str(x) insn */
10410 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10413 else if (1 == arm_insn_r->decode && 0x12 == opcode1
10414 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10416 /* Handle BX, branch and link/exchange. */
10417 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10418 record_buf[0] = ARM_PS_REGNUM;
10419 arm_insn_r->reg_rec_count = 1;
10421 else if (1 == arm_insn_r->decode && 0x16 == opcode1
10422 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
10423 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
10425 /* Count leading zeros: CLZ. */
10426 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10427 arm_insn_r->reg_rec_count = 1;
10429 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10430 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10431 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
10432 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
10435 /* Handle MRS insn. */
10436 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10437 arm_insn_r->reg_rec_count = 1;
10439 else if (arm_insn_r->opcode <= 15)
10441 /* Normal data processing insns. */
10442 /* Out of 11 shifter operands mode, all the insn modifies destination
10443 register, which is specified by 13-16 decode. */
10444 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10445 record_buf[1] = ARM_PS_REGNUM;
10446 arm_insn_r->reg_rec_count = 2;
10453 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10454 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10458 /* Handling opcode 001 insns. */
10461 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
10463 uint32_t record_buf[8], record_buf_mem[8];
10465 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10466 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10468 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10469 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
10470 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10473 /* Handle MSR insn. */
10474 if (9 == arm_insn_r->opcode)
10476 /* CSPR is going to be changed. */
10477 record_buf[0] = ARM_PS_REGNUM;
10478 arm_insn_r->reg_rec_count = 1;
10482 /* SPSR is going to be changed. */
10485 else if (arm_insn_r->opcode <= 15)
10487 /* Normal data processing insns. */
10488 /* Out of 11 shifter operands mode, all the insn modifies destination
10489 register, which is specified by 13-16 decode. */
10490 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10491 record_buf[1] = ARM_PS_REGNUM;
10492 arm_insn_r->reg_rec_count = 2;
10499 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10500 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10505 arm_record_media (insn_decode_record *arm_insn_r)
10507 uint32_t record_buf[8];
10509 switch (bits (arm_insn_r->arm_insn, 22, 24))
10512 /* Parallel addition and subtraction, signed */
10514 /* Parallel addition and subtraction, unsigned */
10517 /* Packing, unpacking, saturation and reversal */
10519 int rd = bits (arm_insn_r->arm_insn, 12, 15);
10521 record_buf[arm_insn_r->reg_rec_count++] = rd;
10527 /* Signed multiplies */
10529 int rd = bits (arm_insn_r->arm_insn, 16, 19);
10530 unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22);
10532 record_buf[arm_insn_r->reg_rec_count++] = rd;
10534 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10535 else if (op1 == 0x4)
10536 record_buf[arm_insn_r->reg_rec_count++]
10537 = bits (arm_insn_r->arm_insn, 12, 15);
10543 if (bit (arm_insn_r->arm_insn, 21)
10544 && bits (arm_insn_r->arm_insn, 5, 6) == 0x2)
10547 record_buf[arm_insn_r->reg_rec_count++]
10548 = bits (arm_insn_r->arm_insn, 12, 15);
10550 else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0
10551 && bits (arm_insn_r->arm_insn, 5, 7) == 0x0)
10553 /* USAD8 and USADA8 */
10554 record_buf[arm_insn_r->reg_rec_count++]
10555 = bits (arm_insn_r->arm_insn, 16, 19);
10562 if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3
10563 && bits (arm_insn_r->arm_insn, 5, 7) == 0x7)
10565 /* Permanently UNDEFINED */
10570 /* BFC, BFI and UBFX */
10571 record_buf[arm_insn_r->reg_rec_count++]
10572 = bits (arm_insn_r->arm_insn, 12, 15);
10581 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10586 /* Handle ARM mode instructions with opcode 010. */
10589 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
10591 struct regcache *reg_cache = arm_insn_r->regcache;
10593 uint32_t reg_base , reg_dest;
10594 uint32_t offset_12, tgt_mem_addr;
10595 uint32_t record_buf[8], record_buf_mem[8];
10596 unsigned char wback;
10599 /* Calculate wback. */
10600 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
10601 || (bit (arm_insn_r->arm_insn, 21) == 1);
10603 arm_insn_r->reg_rec_count = 0;
10604 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10606 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10608 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10611 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10612 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
10614 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10615 preceeds a LDR instruction having R15 as reg_base, it
10616 emulates a branch and link instruction, and hence we need to save
10617 CPSR and PC as well. */
10618 if (ARM_PC_REGNUM == reg_dest)
10619 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10621 /* If wback is true, also save the base register, which is going to be
10624 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10628 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10630 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
10631 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10633 /* Handle bit U. */
10634 if (bit (arm_insn_r->arm_insn, 23))
10636 /* U == 1: Add the offset. */
10637 tgt_mem_addr = (uint32_t) u_regval + offset_12;
10641 /* U == 0: subtract the offset. */
10642 tgt_mem_addr = (uint32_t) u_regval - offset_12;
10645 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10647 if (bit (arm_insn_r->arm_insn, 22))
10649 /* STRB and STRBT: 1 byte. */
10650 record_buf_mem[0] = 1;
10654 /* STR and STRT: 4 bytes. */
10655 record_buf_mem[0] = 4;
10658 /* Handle bit P. */
10659 if (bit (arm_insn_r->arm_insn, 24))
10660 record_buf_mem[1] = tgt_mem_addr;
10662 record_buf_mem[1] = (uint32_t) u_regval;
10664 arm_insn_r->mem_rec_count = 1;
10666 /* If wback is true, also save the base register, which is going to be
10669 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10672 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10673 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10677 /* Handling opcode 011 insns. */
10680 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
10682 struct regcache *reg_cache = arm_insn_r->regcache;
10684 uint32_t shift_imm = 0;
10685 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
10686 uint32_t offset_12 = 0, tgt_mem_addr = 0;
10687 uint32_t record_buf[8], record_buf_mem[8];
10690 ULONGEST u_regval[2];
10692 if (bit (arm_insn_r->arm_insn, 4))
10693 return arm_record_media (arm_insn_r);
10695 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10696 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10698 /* Handle enhanced store insns and LDRD DSP insn,
10699 order begins according to addressing modes for store insns
10703 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10705 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10706 /* LDR insn has a capability to do branching, if
10707 MOV LR, PC is precedded by LDR insn having Rn as R15
10708 in that case, it emulates branch and link insn, and hence we
10709 need to save CSPR and PC as well. */
10710 if (15 != reg_dest)
10712 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10713 arm_insn_r->reg_rec_count = 1;
10717 record_buf[0] = reg_dest;
10718 record_buf[1] = ARM_PS_REGNUM;
10719 arm_insn_r->reg_rec_count = 2;
10724 if (! bits (arm_insn_r->arm_insn, 4, 11))
10726 /* Store insn, register offset and register pre-indexed,
10727 register post-indexed. */
10729 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10731 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10732 regcache_raw_read_unsigned (reg_cache, reg_src1
10734 regcache_raw_read_unsigned (reg_cache, reg_src2
10736 if (15 == reg_src2)
10738 /* If R15 was used as Rn, hence current PC+8. */
10739 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10740 u_regval[0] = u_regval[0] + 8;
10742 /* Calculate target store address, Rn +/- Rm, register offset. */
10744 if (bit (arm_insn_r->arm_insn, 23))
10746 tgt_mem_addr = u_regval[0] + u_regval[1];
10750 tgt_mem_addr = u_regval[1] - u_regval[0];
10753 switch (arm_insn_r->opcode)
10767 record_buf_mem[0] = 4;
10782 record_buf_mem[0] = 1;
10786 gdb_assert_not_reached ("no decoding pattern found");
10789 record_buf_mem[1] = tgt_mem_addr;
10790 arm_insn_r->mem_rec_count = 1;
10792 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10793 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10794 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10795 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10796 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10797 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10800 /* Rn is going to be changed in pre-indexed mode and
10801 post-indexed mode as well. */
10802 record_buf[0] = reg_src2;
10803 arm_insn_r->reg_rec_count = 1;
10808 /* Store insn, scaled register offset; scaled pre-indexed. */
10809 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
10811 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10813 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10814 /* Get shift_imm. */
10815 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
10816 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10817 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
10818 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10819 /* Offset_12 used as shift. */
10823 /* Offset_12 used as index. */
10824 offset_12 = u_regval[0] << shift_imm;
10828 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
10834 if (bit (u_regval[0], 31))
10836 offset_12 = 0xFFFFFFFF;
10845 /* This is arithmetic shift. */
10846 offset_12 = s_word >> shift_imm;
10853 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
10855 /* Get C flag value and shift it by 31. */
10856 offset_12 = (((bit (u_regval[1], 29)) << 31) \
10857 | (u_regval[0]) >> 1);
10861 offset_12 = (u_regval[0] >> shift_imm) \
10863 (sizeof(uint32_t) - shift_imm));
10868 gdb_assert_not_reached ("no decoding pattern found");
10872 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10874 if (bit (arm_insn_r->arm_insn, 23))
10876 tgt_mem_addr = u_regval[1] + offset_12;
10880 tgt_mem_addr = u_regval[1] - offset_12;
10883 switch (arm_insn_r->opcode)
10897 record_buf_mem[0] = 4;
10912 record_buf_mem[0] = 1;
10916 gdb_assert_not_reached ("no decoding pattern found");
10919 record_buf_mem[1] = tgt_mem_addr;
10920 arm_insn_r->mem_rec_count = 1;
10922 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10923 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10924 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10925 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10926 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10927 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10930 /* Rn is going to be changed in register scaled pre-indexed
10931 mode,and scaled post indexed mode. */
10932 record_buf[0] = reg_src2;
10933 arm_insn_r->reg_rec_count = 1;
10938 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10939 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10943 /* Handle ARM mode instructions with opcode 100. */
10946 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
10948 struct regcache *reg_cache = arm_insn_r->regcache;
10949 uint32_t register_count = 0, register_bits;
10950 uint32_t reg_base, addr_mode;
10951 uint32_t record_buf[24], record_buf_mem[48];
10955 /* Fetch the list of registers. */
10956 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
10957 arm_insn_r->reg_rec_count = 0;
10959 /* Fetch the base register that contains the address we are loading data
10961 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10963 /* Calculate wback. */
10964 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
10966 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10968 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10970 /* Find out which registers are going to be loaded from memory. */
10971 while (register_bits)
10973 if (register_bits & 0x00000001)
10974 record_buf[arm_insn_r->reg_rec_count++] = register_count;
10975 register_bits = register_bits >> 1;
10980 /* If wback is true, also save the base register, which is going to be
10983 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10985 /* Save the CPSR register. */
10986 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10990 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10992 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
10994 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10996 /* Find out how many registers are going to be stored to memory. */
10997 while (register_bits)
10999 if (register_bits & 0x00000001)
11001 register_bits = register_bits >> 1;
11006 /* STMDA (STMED): Decrement after. */
11008 record_buf_mem[1] = (uint32_t) u_regval
11009 - register_count * INT_REGISTER_SIZE + 4;
11011 /* STM (STMIA, STMEA): Increment after. */
11013 record_buf_mem[1] = (uint32_t) u_regval;
11015 /* STMDB (STMFD): Decrement before. */
11017 record_buf_mem[1] = (uint32_t) u_regval
11018 - register_count * INT_REGISTER_SIZE;
11020 /* STMIB (STMFA): Increment before. */
11022 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
11025 gdb_assert_not_reached ("no decoding pattern found");
11029 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
11030 arm_insn_r->mem_rec_count = 1;
11032 /* If wback is true, also save the base register, which is going to be
11035 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11038 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11039 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11043 /* Handling opcode 101 insns. */
11046 arm_record_b_bl (insn_decode_record *arm_insn_r)
11048 uint32_t record_buf[8];
11050 /* Handle B, BL, BLX(1) insns. */
11051 /* B simply branches so we do nothing here. */
11052 /* Note: BLX(1) doesnt fall here but instead it falls into
11053 extension space. */
11054 if (bit (arm_insn_r->arm_insn, 24))
11056 record_buf[0] = ARM_LR_REGNUM;
11057 arm_insn_r->reg_rec_count = 1;
11060 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11066 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
11068 printf_unfiltered (_("Process record does not support instruction "
11069 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11070 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11075 /* Record handler for vector data transfer instructions. */
11078 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
11080 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
11081 uint32_t record_buf[4];
11083 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
11084 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
11085 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
11086 bit_l = bit (arm_insn_r->arm_insn, 20);
11087 bit_c = bit (arm_insn_r->arm_insn, 8);
11089 /* Handle VMOV instruction. */
11090 if (bit_l && bit_c)
11092 record_buf[0] = reg_t;
11093 arm_insn_r->reg_rec_count = 1;
11095 else if (bit_l && !bit_c)
11097 /* Handle VMOV instruction. */
11098 if (bits_a == 0x00)
11100 record_buf[0] = reg_t;
11101 arm_insn_r->reg_rec_count = 1;
11103 /* Handle VMRS instruction. */
11104 else if (bits_a == 0x07)
11107 reg_t = ARM_PS_REGNUM;
11109 record_buf[0] = reg_t;
11110 arm_insn_r->reg_rec_count = 1;
11113 else if (!bit_l && !bit_c)
11115 /* Handle VMOV instruction. */
11116 if (bits_a == 0x00)
11118 record_buf[0] = ARM_D0_REGNUM + reg_v;
11120 arm_insn_r->reg_rec_count = 1;
11122 /* Handle VMSR instruction. */
11123 else if (bits_a == 0x07)
11125 record_buf[0] = ARM_FPSCR_REGNUM;
11126 arm_insn_r->reg_rec_count = 1;
11129 else if (!bit_l && bit_c)
11131 /* Handle VMOV instruction. */
11132 if (!(bits_a & 0x04))
11134 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
11136 arm_insn_r->reg_rec_count = 1;
11138 /* Handle VDUP instruction. */
11141 if (bit (arm_insn_r->arm_insn, 21))
11143 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
11144 record_buf[0] = reg_v + ARM_D0_REGNUM;
11145 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
11146 arm_insn_r->reg_rec_count = 2;
11150 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
11151 record_buf[0] = reg_v + ARM_D0_REGNUM;
11152 arm_insn_r->reg_rec_count = 1;
11157 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11161 /* Record handler for extension register load/store instructions. */
11164 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
11166 uint32_t opcode, single_reg;
11167 uint8_t op_vldm_vstm;
11168 uint32_t record_buf[8], record_buf_mem[128];
11169 ULONGEST u_regval = 0;
11171 struct regcache *reg_cache = arm_insn_r->regcache;
11173 opcode = bits (arm_insn_r->arm_insn, 20, 24);
11174 single_reg = !bit (arm_insn_r->arm_insn, 8);
11175 op_vldm_vstm = opcode & 0x1b;
11177 /* Handle VMOV instructions. */
11178 if ((opcode & 0x1e) == 0x04)
11180 if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */
11182 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11183 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11184 arm_insn_r->reg_rec_count = 2;
11188 uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3);
11189 uint8_t bit_m = bit (arm_insn_r->arm_insn, 5);
11193 /* The first S register number m is REG_M:M (M is bit 5),
11194 the corresponding D register number is REG_M:M / 2, which
11196 record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m;
11197 /* The second S register number is REG_M:M + 1, the
11198 corresponding D register number is (REG_M:M + 1) / 2.
11199 IOW, if bit M is 1, the first and second S registers
11200 are mapped to different D registers, otherwise, they are
11201 in the same D register. */
11204 record_buf[arm_insn_r->reg_rec_count++]
11205 = ARM_D0_REGNUM + reg_m + 1;
11210 record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM);
11211 arm_insn_r->reg_rec_count = 1;
11215 /* Handle VSTM and VPUSH instructions. */
11216 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
11217 || op_vldm_vstm == 0x12)
11219 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
11220 uint32_t memory_index = 0;
11222 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11223 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11224 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11225 imm_off32 = imm_off8 << 2;
11226 memory_count = imm_off8;
11228 if (bit (arm_insn_r->arm_insn, 23))
11229 start_address = u_regval;
11231 start_address = u_regval - imm_off32;
11233 if (bit (arm_insn_r->arm_insn, 21))
11235 record_buf[0] = reg_rn;
11236 arm_insn_r->reg_rec_count = 1;
11239 while (memory_count > 0)
11243 record_buf_mem[memory_index] = 4;
11244 record_buf_mem[memory_index + 1] = start_address;
11245 start_address = start_address + 4;
11246 memory_index = memory_index + 2;
11250 record_buf_mem[memory_index] = 4;
11251 record_buf_mem[memory_index + 1] = start_address;
11252 record_buf_mem[memory_index + 2] = 4;
11253 record_buf_mem[memory_index + 3] = start_address + 4;
11254 start_address = start_address + 8;
11255 memory_index = memory_index + 4;
11259 arm_insn_r->mem_rec_count = (memory_index >> 1);
11261 /* Handle VLDM instructions. */
11262 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
11263 || op_vldm_vstm == 0x13)
11265 uint32_t reg_count, reg_vd;
11266 uint32_t reg_index = 0;
11267 uint32_t bit_d = bit (arm_insn_r->arm_insn, 22);
11269 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11270 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
11272 /* REG_VD is the first D register number. If the instruction
11273 loads memory to S registers (SINGLE_REG is TRUE), the register
11274 number is (REG_VD << 1 | bit D), so the corresponding D
11275 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11277 reg_vd = reg_vd | (bit_d << 4);
11279 if (bit (arm_insn_r->arm_insn, 21) /* write back */)
11280 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
11282 /* If the instruction loads memory to D register, REG_COUNT should
11283 be divided by 2, according to the ARM Architecture Reference
11284 Manual. If the instruction loads memory to S register, divide by
11285 2 as well because two S registers are mapped to D register. */
11286 reg_count = reg_count / 2;
11287 if (single_reg && bit_d)
11289 /* Increase the register count if S register list starts from
11290 an odd number (bit d is one). */
11294 while (reg_count > 0)
11296 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
11299 arm_insn_r->reg_rec_count = reg_index;
11301 /* VSTR Vector store register. */
11302 else if ((opcode & 0x13) == 0x10)
11304 uint32_t start_address, reg_rn, imm_off32, imm_off8;
11305 uint32_t memory_index = 0;
11307 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11308 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11309 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11310 imm_off32 = imm_off8 << 2;
11312 if (bit (arm_insn_r->arm_insn, 23))
11313 start_address = u_regval + imm_off32;
11315 start_address = u_regval - imm_off32;
11319 record_buf_mem[memory_index] = 4;
11320 record_buf_mem[memory_index + 1] = start_address;
11321 arm_insn_r->mem_rec_count = 1;
11325 record_buf_mem[memory_index] = 4;
11326 record_buf_mem[memory_index + 1] = start_address;
11327 record_buf_mem[memory_index + 2] = 4;
11328 record_buf_mem[memory_index + 3] = start_address + 4;
11329 arm_insn_r->mem_rec_count = 2;
11332 /* VLDR Vector load register. */
11333 else if ((opcode & 0x13) == 0x11)
11335 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11339 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
11340 record_buf[0] = ARM_D0_REGNUM + reg_vd;
11344 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
11345 /* Record register D rather than pseudo register S. */
11346 record_buf[0] = ARM_D0_REGNUM + reg_vd / 2;
11348 arm_insn_r->reg_rec_count = 1;
11351 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11352 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11356 /* Record handler for arm/thumb mode VFP data processing instructions. */
11359 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
11361 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
11362 uint32_t record_buf[4];
11363 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
11364 enum insn_types curr_insn_type = INSN_INV;
11366 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11367 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
11368 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
11369 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
11370 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
11371 bit_d = bit (arm_insn_r->arm_insn, 22);
11372 opc1 = opc1 & 0x04;
11374 /* Handle VMLA, VMLS. */
11377 if (bit (arm_insn_r->arm_insn, 10))
11379 if (bit (arm_insn_r->arm_insn, 6))
11380 curr_insn_type = INSN_T0;
11382 curr_insn_type = INSN_T1;
11387 curr_insn_type = INSN_T1;
11389 curr_insn_type = INSN_T2;
11392 /* Handle VNMLA, VNMLS, VNMUL. */
11393 else if (opc1 == 0x01)
11396 curr_insn_type = INSN_T1;
11398 curr_insn_type = INSN_T2;
11401 else if (opc1 == 0x02 && !(opc3 & 0x01))
11403 if (bit (arm_insn_r->arm_insn, 10))
11405 if (bit (arm_insn_r->arm_insn, 6))
11406 curr_insn_type = INSN_T0;
11408 curr_insn_type = INSN_T1;
11413 curr_insn_type = INSN_T1;
11415 curr_insn_type = INSN_T2;
11418 /* Handle VADD, VSUB. */
11419 else if (opc1 == 0x03)
11421 if (!bit (arm_insn_r->arm_insn, 9))
11423 if (bit (arm_insn_r->arm_insn, 6))
11424 curr_insn_type = INSN_T0;
11426 curr_insn_type = INSN_T1;
11431 curr_insn_type = INSN_T1;
11433 curr_insn_type = INSN_T2;
11437 else if (opc1 == 0x0b)
11440 curr_insn_type = INSN_T1;
11442 curr_insn_type = INSN_T2;
11444 /* Handle all other vfp data processing instructions. */
11445 else if (opc1 == 0x0b)
11448 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
11450 if (bit (arm_insn_r->arm_insn, 4))
11452 if (bit (arm_insn_r->arm_insn, 6))
11453 curr_insn_type = INSN_T0;
11455 curr_insn_type = INSN_T1;
11460 curr_insn_type = INSN_T1;
11462 curr_insn_type = INSN_T2;
11465 /* Handle VNEG and VABS. */
11466 else if ((opc2 == 0x01 && opc3 == 0x01)
11467 || (opc2 == 0x00 && opc3 == 0x03))
11469 if (!bit (arm_insn_r->arm_insn, 11))
11471 if (bit (arm_insn_r->arm_insn, 6))
11472 curr_insn_type = INSN_T0;
11474 curr_insn_type = INSN_T1;
11479 curr_insn_type = INSN_T1;
11481 curr_insn_type = INSN_T2;
11484 /* Handle VSQRT. */
11485 else if (opc2 == 0x01 && opc3 == 0x03)
11488 curr_insn_type = INSN_T1;
11490 curr_insn_type = INSN_T2;
11493 else if (opc2 == 0x07 && opc3 == 0x03)
11496 curr_insn_type = INSN_T1;
11498 curr_insn_type = INSN_T2;
11500 else if (opc3 & 0x01)
11503 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
11505 if (!bit (arm_insn_r->arm_insn, 18))
11506 curr_insn_type = INSN_T2;
11510 curr_insn_type = INSN_T1;
11512 curr_insn_type = INSN_T2;
11516 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
11519 curr_insn_type = INSN_T1;
11521 curr_insn_type = INSN_T2;
11523 /* Handle VCVTB, VCVTT. */
11524 else if ((opc2 & 0x0e) == 0x02)
11525 curr_insn_type = INSN_T2;
11526 /* Handle VCMP, VCMPE. */
11527 else if ((opc2 & 0x0e) == 0x04)
11528 curr_insn_type = INSN_T3;
11532 switch (curr_insn_type)
11535 reg_vd = reg_vd | (bit_d << 4);
11536 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11537 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
11538 arm_insn_r->reg_rec_count = 2;
11542 reg_vd = reg_vd | (bit_d << 4);
11543 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11544 arm_insn_r->reg_rec_count = 1;
11548 reg_vd = (reg_vd << 1) | bit_d;
11549 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11550 arm_insn_r->reg_rec_count = 1;
11554 record_buf[0] = ARM_FPSCR_REGNUM;
11555 arm_insn_r->reg_rec_count = 1;
11559 gdb_assert_not_reached ("no decoding pattern found");
11563 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11567 /* Handling opcode 110 insns. */
11570 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
11572 uint32_t op1, op1_ebit, coproc;
11574 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11575 op1 = bits (arm_insn_r->arm_insn, 20, 25);
11576 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11578 if ((coproc & 0x0e) == 0x0a)
11580 /* Handle extension register ld/st instructions. */
11582 return arm_record_exreg_ld_st_insn (arm_insn_r);
11584 /* 64-bit transfers between arm core and extension registers. */
11585 if ((op1 & 0x3e) == 0x04)
11586 return arm_record_exreg_ld_st_insn (arm_insn_r);
11590 /* Handle coprocessor ld/st instructions. */
11595 return arm_record_unsupported_insn (arm_insn_r);
11598 return arm_record_unsupported_insn (arm_insn_r);
11601 /* Move to coprocessor from two arm core registers. */
11603 return arm_record_unsupported_insn (arm_insn_r);
11605 /* Move to two arm core registers from coprocessor. */
11610 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
11611 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
11612 arm_insn_r->reg_rec_count = 2;
11614 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
11618 return arm_record_unsupported_insn (arm_insn_r);
11621 /* Handling opcode 111 insns. */
11624 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11626 uint32_t op, op1_sbit, op1_ebit, coproc;
11627 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11628 struct regcache *reg_cache = arm_insn_r->regcache;
11630 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11631 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11632 op1_sbit = bit (arm_insn_r->arm_insn, 24);
11633 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11634 op = bit (arm_insn_r->arm_insn, 4);
11636 /* Handle arm SWI/SVC system call instructions. */
11639 if (tdep->arm_syscall_record != NULL)
11641 ULONGEST svc_operand, svc_number;
11643 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
11645 if (svc_operand) /* OABI. */
11646 svc_number = svc_operand - 0x900000;
11648 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
11650 return tdep->arm_syscall_record (reg_cache, svc_number);
11654 printf_unfiltered (_("no syscall record support\n"));
11659 if ((coproc & 0x0e) == 0x0a)
11661 /* VFP data-processing instructions. */
11662 if (!op1_sbit && !op)
11663 return arm_record_vfp_data_proc_insn (arm_insn_r);
11665 /* Advanced SIMD, VFP instructions. */
11666 if (!op1_sbit && op)
11667 return arm_record_vdata_transfer_insn (arm_insn_r);
11671 /* Coprocessor data operations. */
11672 if (!op1_sbit && !op)
11673 return arm_record_unsupported_insn (arm_insn_r);
11675 /* Move to Coprocessor from ARM core register. */
11676 if (!op1_sbit && !op1_ebit && op)
11677 return arm_record_unsupported_insn (arm_insn_r);
11679 /* Move to arm core register from coprocessor. */
11680 if (!op1_sbit && op1_ebit && op)
11682 uint32_t record_buf[1];
11684 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11685 if (record_buf[0] == 15)
11686 record_buf[0] = ARM_PS_REGNUM;
11688 arm_insn_r->reg_rec_count = 1;
11689 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
11695 return arm_record_unsupported_insn (arm_insn_r);
11698 /* Handling opcode 000 insns. */
11701 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11703 uint32_t record_buf[8];
11704 uint32_t reg_src1 = 0;
11706 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11708 record_buf[0] = ARM_PS_REGNUM;
11709 record_buf[1] = reg_src1;
11710 thumb_insn_r->reg_rec_count = 2;
11712 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11718 /* Handling opcode 001 insns. */
11721 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11723 uint32_t record_buf[8];
11724 uint32_t reg_src1 = 0;
11726 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11728 record_buf[0] = ARM_PS_REGNUM;
11729 record_buf[1] = reg_src1;
11730 thumb_insn_r->reg_rec_count = 2;
11732 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11737 /* Handling opcode 010 insns. */
11740 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
11742 struct regcache *reg_cache = thumb_insn_r->regcache;
11743 uint32_t record_buf[8], record_buf_mem[8];
11745 uint32_t reg_src1 = 0, reg_src2 = 0;
11746 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
11748 ULONGEST u_regval[2] = {0};
11750 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
11752 if (bit (thumb_insn_r->arm_insn, 12))
11754 /* Handle load/store register offset. */
11755 opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
11756 if (opcode2 >= 12 && opcode2 <= 15)
11758 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11759 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
11760 record_buf[0] = reg_src1;
11761 thumb_insn_r->reg_rec_count = 1;
11763 else if (opcode2 >= 8 && opcode2 <= 10)
11765 /* STR(2), STRB(2), STRH(2) . */
11766 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11767 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
11768 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11769 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11771 record_buf_mem[0] = 4; /* STR (2). */
11772 else if (10 == opcode2)
11773 record_buf_mem[0] = 1; /* STRB (2). */
11774 else if (9 == opcode2)
11775 record_buf_mem[0] = 2; /* STRH (2). */
11776 record_buf_mem[1] = u_regval[0] + u_regval[1];
11777 thumb_insn_r->mem_rec_count = 1;
11780 else if (bit (thumb_insn_r->arm_insn, 11))
11782 /* Handle load from literal pool. */
11784 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11785 record_buf[0] = reg_src1;
11786 thumb_insn_r->reg_rec_count = 1;
11790 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
11791 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
11792 if ((3 == opcode2) && (!opcode3))
11794 /* Branch with exchange. */
11795 record_buf[0] = ARM_PS_REGNUM;
11796 thumb_insn_r->reg_rec_count = 1;
11800 /* Format 8; special data processing insns. */
11801 record_buf[0] = ARM_PS_REGNUM;
11802 record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3
11803 | bits (thumb_insn_r->arm_insn, 0, 2));
11804 thumb_insn_r->reg_rec_count = 2;
11809 /* Format 5; data processing insns. */
11810 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11811 if (bit (thumb_insn_r->arm_insn, 7))
11813 reg_src1 = reg_src1 + 8;
11815 record_buf[0] = ARM_PS_REGNUM;
11816 record_buf[1] = reg_src1;
11817 thumb_insn_r->reg_rec_count = 2;
11820 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11821 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11827 /* Handling opcode 001 insns. */
11830 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
11832 struct regcache *reg_cache = thumb_insn_r->regcache;
11833 uint32_t record_buf[8], record_buf_mem[8];
11835 uint32_t reg_src1 = 0;
11836 uint32_t opcode = 0, immed_5 = 0;
11838 ULONGEST u_regval = 0;
11840 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11845 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11846 record_buf[0] = reg_src1;
11847 thumb_insn_r->reg_rec_count = 1;
11852 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11853 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11854 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11855 record_buf_mem[0] = 4;
11856 record_buf_mem[1] = u_regval + (immed_5 * 4);
11857 thumb_insn_r->mem_rec_count = 1;
11860 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11861 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11867 /* Handling opcode 100 insns. */
11870 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
11872 struct regcache *reg_cache = thumb_insn_r->regcache;
11873 uint32_t record_buf[8], record_buf_mem[8];
11875 uint32_t reg_src1 = 0;
11876 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
11878 ULONGEST u_regval = 0;
11880 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11885 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11886 record_buf[0] = reg_src1;
11887 thumb_insn_r->reg_rec_count = 1;
11889 else if (1 == opcode)
11892 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11893 record_buf[0] = reg_src1;
11894 thumb_insn_r->reg_rec_count = 1;
11896 else if (2 == opcode)
11899 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
11900 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11901 record_buf_mem[0] = 4;
11902 record_buf_mem[1] = u_regval + (immed_8 * 4);
11903 thumb_insn_r->mem_rec_count = 1;
11905 else if (0 == opcode)
11908 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11909 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11910 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11911 record_buf_mem[0] = 2;
11912 record_buf_mem[1] = u_regval + (immed_5 * 2);
11913 thumb_insn_r->mem_rec_count = 1;
11916 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11917 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11923 /* Handling opcode 101 insns. */
11926 thumb_record_misc (insn_decode_record *thumb_insn_r)
11928 struct regcache *reg_cache = thumb_insn_r->regcache;
11930 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
11931 uint32_t register_bits = 0, register_count = 0;
11932 uint32_t index = 0, start_address = 0;
11933 uint32_t record_buf[24], record_buf_mem[48];
11936 ULONGEST u_regval = 0;
11938 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11939 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
11940 opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
11945 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11946 while (register_bits)
11948 if (register_bits & 0x00000001)
11949 record_buf[index++] = register_count;
11950 register_bits = register_bits >> 1;
11953 record_buf[index++] = ARM_PS_REGNUM;
11954 record_buf[index++] = ARM_SP_REGNUM;
11955 thumb_insn_r->reg_rec_count = index;
11957 else if (10 == opcode2)
11960 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11961 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11962 while (register_bits)
11964 if (register_bits & 0x00000001)
11966 register_bits = register_bits >> 1;
11968 start_address = u_regval - \
11969 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
11970 thumb_insn_r->mem_rec_count = register_count;
11971 while (register_count)
11973 record_buf_mem[(register_count * 2) - 1] = start_address;
11974 record_buf_mem[(register_count * 2) - 2] = 4;
11975 start_address = start_address + 4;
11978 record_buf[0] = ARM_SP_REGNUM;
11979 thumb_insn_r->reg_rec_count = 1;
11981 else if (0x1E == opcode1)
11984 /* Handle enhanced software breakpoint insn, BKPT. */
11985 /* CPSR is changed to be executed in ARM state, disabling normal
11986 interrupts, entering abort mode. */
11987 /* According to high vector configuration PC is set. */
11988 /* User hits breakpoint and type reverse, in that case, we need to go back with
11989 previous CPSR and Program Counter. */
11990 record_buf[0] = ARM_PS_REGNUM;
11991 record_buf[1] = ARM_LR_REGNUM;
11992 thumb_insn_r->reg_rec_count = 2;
11993 /* We need to save SPSR value, which is not yet done. */
11994 printf_unfiltered (_("Process record does not support instruction "
11995 "0x%0x at address %s.\n"),
11996 thumb_insn_r->arm_insn,
11997 paddress (thumb_insn_r->gdbarch,
11998 thumb_insn_r->this_addr));
12001 else if ((0 == opcode) || (1 == opcode))
12003 /* ADD(5), ADD(6). */
12004 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12005 record_buf[0] = reg_src1;
12006 thumb_insn_r->reg_rec_count = 1;
12008 else if (2 == opcode)
12010 /* ADD(7), SUB(4). */
12011 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12012 record_buf[0] = ARM_SP_REGNUM;
12013 thumb_insn_r->reg_rec_count = 1;
12016 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12017 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12023 /* Handling opcode 110 insns. */
12026 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12028 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12029 struct regcache *reg_cache = thumb_insn_r->regcache;
12031 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12032 uint32_t reg_src1 = 0;
12033 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12034 uint32_t index = 0, start_address = 0;
12035 uint32_t record_buf[24], record_buf_mem[48];
12037 ULONGEST u_regval = 0;
12039 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12040 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12046 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12048 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12049 while (register_bits)
12051 if (register_bits & 0x00000001)
12052 record_buf[index++] = register_count;
12053 register_bits = register_bits >> 1;
12056 record_buf[index++] = reg_src1;
12057 thumb_insn_r->reg_rec_count = index;
12059 else if (0 == opcode2)
12061 /* It handles both STMIA. */
12062 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12064 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12065 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12066 while (register_bits)
12068 if (register_bits & 0x00000001)
12070 register_bits = register_bits >> 1;
12072 start_address = u_regval;
12073 thumb_insn_r->mem_rec_count = register_count;
12074 while (register_count)
12076 record_buf_mem[(register_count * 2) - 1] = start_address;
12077 record_buf_mem[(register_count * 2) - 2] = 4;
12078 start_address = start_address + 4;
12082 else if (0x1F == opcode1)
12084 /* Handle arm syscall insn. */
12085 if (tdep->arm_syscall_record != NULL)
12087 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
12088 ret = tdep->arm_syscall_record (reg_cache, u_regval);
12092 printf_unfiltered (_("no syscall record support\n"));
12097 /* B (1), conditional branch is automatically taken care in process_record,
12098 as PC is saved there. */
12100 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12101 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12107 /* Handling opcode 111 insns. */
12110 thumb_record_branch (insn_decode_record *thumb_insn_r)
12112 uint32_t record_buf[8];
12113 uint32_t bits_h = 0;
12115 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12117 if (2 == bits_h || 3 == bits_h)
12120 record_buf[0] = ARM_LR_REGNUM;
12121 thumb_insn_r->reg_rec_count = 1;
12123 else if (1 == bits_h)
12126 record_buf[0] = ARM_PS_REGNUM;
12127 record_buf[1] = ARM_LR_REGNUM;
12128 thumb_insn_r->reg_rec_count = 2;
12131 /* B(2) is automatically taken care in process_record, as PC is
12134 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12139 /* Handler for thumb2 load/store multiple instructions. */
12142 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
12144 struct regcache *reg_cache = thumb2_insn_r->regcache;
12146 uint32_t reg_rn, op;
12147 uint32_t register_bits = 0, register_count = 0;
12148 uint32_t index = 0, start_address = 0;
12149 uint32_t record_buf[24], record_buf_mem[48];
12151 ULONGEST u_regval = 0;
12153 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12154 op = bits (thumb2_insn_r->arm_insn, 23, 24);
12156 if (0 == op || 3 == op)
12158 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12160 /* Handle RFE instruction. */
12161 record_buf[0] = ARM_PS_REGNUM;
12162 thumb2_insn_r->reg_rec_count = 1;
12166 /* Handle SRS instruction after reading banked SP. */
12167 return arm_record_unsupported_insn (thumb2_insn_r);
12170 else if (1 == op || 2 == op)
12172 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12174 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12175 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12176 while (register_bits)
12178 if (register_bits & 0x00000001)
12179 record_buf[index++] = register_count;
12182 register_bits = register_bits >> 1;
12184 record_buf[index++] = reg_rn;
12185 record_buf[index++] = ARM_PS_REGNUM;
12186 thumb2_insn_r->reg_rec_count = index;
12190 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12191 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12192 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12193 while (register_bits)
12195 if (register_bits & 0x00000001)
12198 register_bits = register_bits >> 1;
12203 /* Start address calculation for LDMDB/LDMEA. */
12204 start_address = u_regval;
12208 /* Start address calculation for LDMDB/LDMEA. */
12209 start_address = u_regval - register_count * 4;
12212 thumb2_insn_r->mem_rec_count = register_count;
12213 while (register_count)
12215 record_buf_mem[register_count * 2 - 1] = start_address;
12216 record_buf_mem[register_count * 2 - 2] = 4;
12217 start_address = start_address + 4;
12220 record_buf[0] = reg_rn;
12221 record_buf[1] = ARM_PS_REGNUM;
12222 thumb2_insn_r->reg_rec_count = 2;
12226 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12228 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12230 return ARM_RECORD_SUCCESS;
12233 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12237 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
12239 struct regcache *reg_cache = thumb2_insn_r->regcache;
12241 uint32_t reg_rd, reg_rn, offset_imm;
12242 uint32_t reg_dest1, reg_dest2;
12243 uint32_t address, offset_addr;
12244 uint32_t record_buf[8], record_buf_mem[8];
12245 uint32_t op1, op2, op3;
12247 ULONGEST u_regval[2];
12249 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
12250 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
12251 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
12253 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12255 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
12257 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
12258 record_buf[0] = reg_dest1;
12259 record_buf[1] = ARM_PS_REGNUM;
12260 thumb2_insn_r->reg_rec_count = 2;
12263 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
12265 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12266 record_buf[2] = reg_dest2;
12267 thumb2_insn_r->reg_rec_count = 3;
12272 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12273 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12275 if (0 == op1 && 0 == op2)
12277 /* Handle STREX. */
12278 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12279 address = u_regval[0] + (offset_imm * 4);
12280 record_buf_mem[0] = 4;
12281 record_buf_mem[1] = address;
12282 thumb2_insn_r->mem_rec_count = 1;
12283 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12284 record_buf[0] = reg_rd;
12285 thumb2_insn_r->reg_rec_count = 1;
12287 else if (1 == op1 && 0 == op2)
12289 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12290 record_buf[0] = reg_rd;
12291 thumb2_insn_r->reg_rec_count = 1;
12292 address = u_regval[0];
12293 record_buf_mem[1] = address;
12297 /* Handle STREXB. */
12298 record_buf_mem[0] = 1;
12299 thumb2_insn_r->mem_rec_count = 1;
12303 /* Handle STREXH. */
12304 record_buf_mem[0] = 2 ;
12305 thumb2_insn_r->mem_rec_count = 1;
12309 /* Handle STREXD. */
12310 address = u_regval[0];
12311 record_buf_mem[0] = 4;
12312 record_buf_mem[2] = 4;
12313 record_buf_mem[3] = address + 4;
12314 thumb2_insn_r->mem_rec_count = 2;
12319 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12321 if (bit (thumb2_insn_r->arm_insn, 24))
12323 if (bit (thumb2_insn_r->arm_insn, 23))
12324 offset_addr = u_regval[0] + (offset_imm * 4);
12326 offset_addr = u_regval[0] - (offset_imm * 4);
12328 address = offset_addr;
12331 address = u_regval[0];
12333 record_buf_mem[0] = 4;
12334 record_buf_mem[1] = address;
12335 record_buf_mem[2] = 4;
12336 record_buf_mem[3] = address + 4;
12337 thumb2_insn_r->mem_rec_count = 2;
12338 record_buf[0] = reg_rn;
12339 thumb2_insn_r->reg_rec_count = 1;
12343 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12345 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12347 return ARM_RECORD_SUCCESS;
12350 /* Handler for thumb2 data processing (shift register and modified immediate)
12354 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
12356 uint32_t reg_rd, op;
12357 uint32_t record_buf[8];
12359 op = bits (thumb2_insn_r->arm_insn, 21, 24);
12360 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12362 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
12364 record_buf[0] = ARM_PS_REGNUM;
12365 thumb2_insn_r->reg_rec_count = 1;
12369 record_buf[0] = reg_rd;
12370 record_buf[1] = ARM_PS_REGNUM;
12371 thumb2_insn_r->reg_rec_count = 2;
12374 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12376 return ARM_RECORD_SUCCESS;
12379 /* Generic handler for thumb2 instructions which effect destination and PS
12383 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
12386 uint32_t record_buf[8];
12388 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12390 record_buf[0] = reg_rd;
12391 record_buf[1] = ARM_PS_REGNUM;
12392 thumb2_insn_r->reg_rec_count = 2;
12394 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12396 return ARM_RECORD_SUCCESS;
12399 /* Handler for thumb2 branch and miscellaneous control instructions. */
12402 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
12404 uint32_t op, op1, op2;
12405 uint32_t record_buf[8];
12407 op = bits (thumb2_insn_r->arm_insn, 20, 26);
12408 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
12409 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12411 /* Handle MSR insn. */
12412 if (!(op1 & 0x2) && 0x38 == op)
12416 /* CPSR is going to be changed. */
12417 record_buf[0] = ARM_PS_REGNUM;
12418 thumb2_insn_r->reg_rec_count = 1;
12422 arm_record_unsupported_insn(thumb2_insn_r);
12426 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
12429 record_buf[0] = ARM_PS_REGNUM;
12430 record_buf[1] = ARM_LR_REGNUM;
12431 thumb2_insn_r->reg_rec_count = 2;
12434 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12436 return ARM_RECORD_SUCCESS;
12439 /* Handler for thumb2 store single data item instructions. */
12442 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
12444 struct regcache *reg_cache = thumb2_insn_r->regcache;
12446 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
12447 uint32_t address, offset_addr;
12448 uint32_t record_buf[8], record_buf_mem[8];
12451 ULONGEST u_regval[2];
12453 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
12454 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
12455 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12456 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12458 if (bit (thumb2_insn_r->arm_insn, 23))
12461 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
12462 offset_addr = u_regval[0] + offset_imm;
12463 address = offset_addr;
12468 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
12470 /* Handle STRB (register). */
12471 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
12472 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
12473 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
12474 offset_addr = u_regval[1] << shift_imm;
12475 address = u_regval[0] + offset_addr;
12479 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12480 if (bit (thumb2_insn_r->arm_insn, 10))
12482 if (bit (thumb2_insn_r->arm_insn, 9))
12483 offset_addr = u_regval[0] + offset_imm;
12485 offset_addr = u_regval[0] - offset_imm;
12487 address = offset_addr;
12490 address = u_regval[0];
12496 /* Store byte instructions. */
12499 record_buf_mem[0] = 1;
12501 /* Store half word instructions. */
12504 record_buf_mem[0] = 2;
12506 /* Store word instructions. */
12509 record_buf_mem[0] = 4;
12513 gdb_assert_not_reached ("no decoding pattern found");
12517 record_buf_mem[1] = address;
12518 thumb2_insn_r->mem_rec_count = 1;
12519 record_buf[0] = reg_rn;
12520 thumb2_insn_r->reg_rec_count = 1;
12522 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12524 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12526 return ARM_RECORD_SUCCESS;
12529 /* Handler for thumb2 load memory hints instructions. */
12532 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
12534 uint32_t record_buf[8];
12535 uint32_t reg_rt, reg_rn;
12537 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
12538 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12540 if (ARM_PC_REGNUM != reg_rt)
12542 record_buf[0] = reg_rt;
12543 record_buf[1] = reg_rn;
12544 record_buf[2] = ARM_PS_REGNUM;
12545 thumb2_insn_r->reg_rec_count = 3;
12547 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12549 return ARM_RECORD_SUCCESS;
12552 return ARM_RECORD_FAILURE;
12555 /* Handler for thumb2 load word instructions. */
12558 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
12560 uint32_t record_buf[8];
12562 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
12563 record_buf[1] = ARM_PS_REGNUM;
12564 thumb2_insn_r->reg_rec_count = 2;
12566 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12568 return ARM_RECORD_SUCCESS;
12571 /* Handler for thumb2 long multiply, long multiply accumulate, and
12572 divide instructions. */
12575 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
12577 uint32_t opcode1 = 0, opcode2 = 0;
12578 uint32_t record_buf[8];
12580 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
12581 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
12583 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
12585 /* Handle SMULL, UMULL, SMULAL. */
12586 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12587 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12588 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12589 record_buf[2] = ARM_PS_REGNUM;
12590 thumb2_insn_r->reg_rec_count = 3;
12592 else if (1 == opcode1 || 3 == opcode2)
12594 /* Handle SDIV and UDIV. */
12595 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12596 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12597 record_buf[2] = ARM_PS_REGNUM;
12598 thumb2_insn_r->reg_rec_count = 3;
12601 return ARM_RECORD_FAILURE;
12603 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12605 return ARM_RECORD_SUCCESS;
12608 /* Record handler for thumb32 coprocessor instructions. */
12611 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
12613 if (bit (thumb2_insn_r->arm_insn, 25))
12614 return arm_record_coproc_data_proc (thumb2_insn_r);
12616 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
12619 /* Record handler for advance SIMD structure load/store instructions. */
12622 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
12624 struct regcache *reg_cache = thumb2_insn_r->regcache;
12625 uint32_t l_bit, a_bit, b_bits;
12626 uint32_t record_buf[128], record_buf_mem[128];
12627 uint32_t reg_rn, reg_vd, address, f_elem;
12628 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
12631 l_bit = bit (thumb2_insn_r->arm_insn, 21);
12632 a_bit = bit (thumb2_insn_r->arm_insn, 23);
12633 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
12634 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12635 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
12636 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
12637 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
12638 f_elem = 8 / f_ebytes;
12642 ULONGEST u_regval = 0;
12643 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12644 address = u_regval;
12649 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12651 if (b_bits == 0x07)
12653 else if (b_bits == 0x0a)
12655 else if (b_bits == 0x06)
12657 else if (b_bits == 0x02)
12662 for (index_r = 0; index_r < bf_regs; index_r++)
12664 for (index_e = 0; index_e < f_elem; index_e++)
12666 record_buf_mem[index_m++] = f_ebytes;
12667 record_buf_mem[index_m++] = address;
12668 address = address + f_ebytes;
12669 thumb2_insn_r->mem_rec_count += 1;
12674 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12676 if (b_bits == 0x09 || b_bits == 0x08)
12678 else if (b_bits == 0x03)
12683 for (index_r = 0; index_r < bf_regs; index_r++)
12684 for (index_e = 0; index_e < f_elem; index_e++)
12686 for (loop_t = 0; loop_t < 2; loop_t++)
12688 record_buf_mem[index_m++] = f_ebytes;
12689 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12690 thumb2_insn_r->mem_rec_count += 1;
12692 address = address + (2 * f_ebytes);
12696 else if ((b_bits & 0x0e) == 0x04)
12698 for (index_e = 0; index_e < f_elem; index_e++)
12700 for (loop_t = 0; loop_t < 3; loop_t++)
12702 record_buf_mem[index_m++] = f_ebytes;
12703 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12704 thumb2_insn_r->mem_rec_count += 1;
12706 address = address + (3 * f_ebytes);
12710 else if (!(b_bits & 0x0e))
12712 for (index_e = 0; index_e < f_elem; index_e++)
12714 for (loop_t = 0; loop_t < 4; loop_t++)
12716 record_buf_mem[index_m++] = f_ebytes;
12717 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12718 thumb2_insn_r->mem_rec_count += 1;
12720 address = address + (4 * f_ebytes);
12726 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
12728 if (bft_size == 0x00)
12730 else if (bft_size == 0x01)
12732 else if (bft_size == 0x02)
12738 if (!(b_bits & 0x0b) || b_bits == 0x08)
12739 thumb2_insn_r->mem_rec_count = 1;
12741 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
12742 thumb2_insn_r->mem_rec_count = 2;
12744 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
12745 thumb2_insn_r->mem_rec_count = 3;
12747 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
12748 thumb2_insn_r->mem_rec_count = 4;
12750 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
12752 record_buf_mem[index_m] = f_ebytes;
12753 record_buf_mem[index_m] = address + (index_m * f_ebytes);
12762 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12763 thumb2_insn_r->reg_rec_count = 1;
12765 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12766 thumb2_insn_r->reg_rec_count = 2;
12768 else if ((b_bits & 0x0e) == 0x04)
12769 thumb2_insn_r->reg_rec_count = 3;
12771 else if (!(b_bits & 0x0e))
12772 thumb2_insn_r->reg_rec_count = 4;
12777 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
12778 thumb2_insn_r->reg_rec_count = 1;
12780 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
12781 thumb2_insn_r->reg_rec_count = 2;
12783 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
12784 thumb2_insn_r->reg_rec_count = 3;
12786 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
12787 thumb2_insn_r->reg_rec_count = 4;
12789 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
12790 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
12794 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
12796 record_buf[index_r] = reg_rn;
12797 thumb2_insn_r->reg_rec_count += 1;
12800 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12802 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12807 /* Decodes thumb2 instruction type and invokes its record handler. */
12809 static unsigned int
12810 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
12812 uint32_t op, op1, op2;
12814 op = bit (thumb2_insn_r->arm_insn, 15);
12815 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
12816 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
12820 if (!(op2 & 0x64 ))
12822 /* Load/store multiple instruction. */
12823 return thumb2_record_ld_st_multiple (thumb2_insn_r);
12825 else if (!((op2 & 0x64) ^ 0x04))
12827 /* Load/store (dual/exclusive) and table branch instruction. */
12828 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
12830 else if (!((op2 & 0x20) ^ 0x20))
12832 /* Data-processing (shifted register). */
12833 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12835 else if (op2 & 0x40)
12837 /* Co-processor instructions. */
12838 return thumb2_record_coproc_insn (thumb2_insn_r);
12841 else if (op1 == 0x02)
12845 /* Branches and miscellaneous control instructions. */
12846 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
12848 else if (op2 & 0x20)
12850 /* Data-processing (plain binary immediate) instruction. */
12851 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12855 /* Data-processing (modified immediate). */
12856 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12859 else if (op1 == 0x03)
12861 if (!(op2 & 0x71 ))
12863 /* Store single data item. */
12864 return thumb2_record_str_single_data (thumb2_insn_r);
12866 else if (!((op2 & 0x71) ^ 0x10))
12868 /* Advanced SIMD or structure load/store instructions. */
12869 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
12871 else if (!((op2 & 0x67) ^ 0x01))
12873 /* Load byte, memory hints instruction. */
12874 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12876 else if (!((op2 & 0x67) ^ 0x03))
12878 /* Load halfword, memory hints instruction. */
12879 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12881 else if (!((op2 & 0x67) ^ 0x05))
12883 /* Load word instruction. */
12884 return thumb2_record_ld_word (thumb2_insn_r);
12886 else if (!((op2 & 0x70) ^ 0x20))
12888 /* Data-processing (register) instruction. */
12889 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12891 else if (!((op2 & 0x78) ^ 0x30))
12893 /* Multiply, multiply accumulate, abs diff instruction. */
12894 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12896 else if (!((op2 & 0x78) ^ 0x38))
12898 /* Long multiply, long multiply accumulate, and divide. */
12899 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
12901 else if (op2 & 0x40)
12903 /* Co-processor instructions. */
12904 return thumb2_record_coproc_insn (thumb2_insn_r);
12911 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12912 and positive val on fauilure. */
12915 extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
12917 gdb_byte buf[insn_size];
12919 memset (&buf[0], 0, insn_size);
12921 if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
12923 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12925 gdbarch_byte_order_for_code (insn_record->gdbarch));
12929 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12931 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12935 decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12936 uint32_t insn_size)
12939 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12941 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
12943 arm_record_data_proc_misc_ld_str, /* 000. */
12944 arm_record_data_proc_imm, /* 001. */
12945 arm_record_ld_st_imm_offset, /* 010. */
12946 arm_record_ld_st_reg_offset, /* 011. */
12947 arm_record_ld_st_multiple, /* 100. */
12948 arm_record_b_bl, /* 101. */
12949 arm_record_asimd_vfp_coproc, /* 110. */
12950 arm_record_coproc_data_proc /* 111. */
12953 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12955 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
12957 thumb_record_shift_add_sub, /* 000. */
12958 thumb_record_add_sub_cmp_mov, /* 001. */
12959 thumb_record_ld_st_reg_offset, /* 010. */
12960 thumb_record_ld_st_imm_offset, /* 011. */
12961 thumb_record_ld_st_stack, /* 100. */
12962 thumb_record_misc, /* 101. */
12963 thumb_record_ldm_stm_swi, /* 110. */
12964 thumb_record_branch /* 111. */
12967 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12968 uint32_t insn_id = 0;
12970 if (extract_arm_insn (arm_record, insn_size))
12974 printf_unfiltered (_("Process record: error reading memory at "
12975 "addr %s len = %d.\n"),
12976 paddress (arm_record->gdbarch,
12977 arm_record->this_addr), insn_size);
12981 else if (ARM_RECORD == record_type)
12983 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
12984 insn_id = bits (arm_record->arm_insn, 25, 27);
12986 if (arm_record->cond == 0xf)
12987 ret = arm_record_extension_space (arm_record);
12990 /* If this insn has fallen into extension space
12991 then we need not decode it anymore. */
12992 ret = arm_handle_insn[insn_id] (arm_record);
12994 if (ret != ARM_RECORD_SUCCESS)
12996 arm_record_unsupported_insn (arm_record);
13000 else if (THUMB_RECORD == record_type)
13002 /* As thumb does not have condition codes, we set negative. */
13003 arm_record->cond = -1;
13004 insn_id = bits (arm_record->arm_insn, 13, 15);
13005 ret = thumb_handle_insn[insn_id] (arm_record);
13006 if (ret != ARM_RECORD_SUCCESS)
13008 arm_record_unsupported_insn (arm_record);
13012 else if (THUMB2_RECORD == record_type)
13014 /* As thumb does not have condition codes, we set negative. */
13015 arm_record->cond = -1;
13017 /* Swap first half of 32bit thumb instruction with second half. */
13018 arm_record->arm_insn
13019 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
13021 ret = thumb2_record_decode_insn_handler (arm_record);
13023 if (ret != ARM_RECORD_SUCCESS)
13025 arm_record_unsupported_insn (arm_record);
13031 /* Throw assertion. */
13032 gdb_assert_not_reached ("not a valid instruction, could not decode");
13039 /* Cleans up local record registers and memory allocations. */
13042 deallocate_reg_mem (insn_decode_record *record)
13044 xfree (record->arm_regs);
13045 xfree (record->arm_mems);
13049 /* Parse the current instruction and record the values of the registers and
13050 memory that will be changed in current instruction to record_arch_list".
13051 Return -1 if something is wrong. */
13054 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
13055 CORE_ADDR insn_addr)
13058 uint32_t no_of_rec = 0;
13059 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
13060 ULONGEST t_bit = 0, insn_id = 0;
13062 ULONGEST u_regval = 0;
13064 insn_decode_record arm_record;
13066 memset (&arm_record, 0, sizeof (insn_decode_record));
13067 arm_record.regcache = regcache;
13068 arm_record.this_addr = insn_addr;
13069 arm_record.gdbarch = gdbarch;
13072 if (record_debug > 1)
13074 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
13076 paddress (gdbarch, arm_record.this_addr));
13079 if (extract_arm_insn (&arm_record, 2))
13083 printf_unfiltered (_("Process record: error reading memory at "
13084 "addr %s len = %d.\n"),
13085 paddress (arm_record.gdbarch,
13086 arm_record.this_addr), 2);
13091 /* Check the insn, whether it is thumb or arm one. */
13093 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
13094 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
13097 if (!(u_regval & t_bit))
13099 /* We are decoding arm insn. */
13100 ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
13104 insn_id = bits (arm_record.arm_insn, 11, 15);
13105 /* is it thumb2 insn? */
13106 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13108 ret = decode_insn (&arm_record, THUMB2_RECORD,
13109 THUMB2_INSN_SIZE_BYTES);
13113 /* We are decoding thumb insn. */
13114 ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
13120 /* Record registers. */
13121 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
13122 if (arm_record.arm_regs)
13124 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
13126 if (record_full_arch_list_add_reg
13127 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
13131 /* Record memories. */
13132 if (arm_record.arm_mems)
13134 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
13136 if (record_full_arch_list_add_mem
13137 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
13138 arm_record.arm_mems[no_of_rec].len))
13143 if (record_full_arch_list_add_end ())
13148 deallocate_reg_mem (&arm_record);