1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
39 #include "gdb/sim-arm.h"
42 #include "coff/internal.h"
45 #include "gdb_assert.h"
49 /* Each OS has a different mechanism for accessing the various
50 registers stored in the sigcontext structure.
52 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
53 function pointer) which may be used to determine the addresses
54 of the various saved registers in the sigcontext structure.
56 For the ARM target, there are three parameters to this function.
57 The first is the pc value of the frame under consideration, the
58 second the stack pointer of this frame, and the last is the
59 register number to fetch.
61 If the tm.h file does not define this macro, then it's assumed that
62 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
65 When it comes time to multi-arching this code, see the identically
66 named machinery in ia64-tdep.c for an example of how it could be
67 done. It should not be necessary to modify the code below where
68 this macro is used. */
70 #ifdef SIGCONTEXT_REGISTER_ADDRESS
71 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
72 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
75 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
76 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
79 /* Macros for setting and testing a bit in a minimal symbol that marks
80 it as Thumb function. The MSB of the minimal symbol's "info" field
81 is used for this purpose. This field is already being used to store
82 the symbol size, so the assumption is that the symbol size cannot
85 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
86 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
87 MSYMBOL_SIZE Returns the size of the minimal symbol,
88 i.e. the "info" field with the "special" bit
91 #define MSYMBOL_SET_SPECIAL(msym) \
92 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
95 #define MSYMBOL_IS_SPECIAL(msym) \
96 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
98 #define MSYMBOL_SIZE(msym) \
99 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
101 /* Number of different reg name sets (options). */
102 static int num_flavor_options;
104 /* We have more registers than the disassembler as gdb can print the value
105 of special registers as well.
106 The general register names are overwritten by whatever is being used by
107 the disassembler at the moment. We also adjust the case of cpsr and fps. */
109 /* Initial value: Register names used in ARM's ISA documentation. */
110 static char * arm_register_name_strings[] =
111 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
112 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
113 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
114 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
115 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
116 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
117 "fps", "cpsr" }; /* 24 25 */
118 static char **arm_register_names = arm_register_name_strings;
120 /* Valid register name flavors. */
121 static const char **valid_flavors;
123 /* Disassembly flavor to use. Default to "std" register names. */
124 static const char *disassembly_flavor;
125 /* Index to that option in the opcodes table. */
126 static int current_option;
128 /* This is used to keep the bfd arch_info in sync with the disassembly
130 static void set_disassembly_flavor_sfunc(char *, int,
131 struct cmd_list_element *);
132 static void set_disassembly_flavor (void);
134 static void convert_from_extended (const struct floatformat *, const void *,
136 static void convert_to_extended (const struct floatformat *, void *,
139 /* Define other aspects of the stack frame. We keep the offsets of
140 all saved registers, 'cause we need 'em a lot! We also keep the
141 current size of the stack frame, and the offset of the frame
142 pointer from the stack pointer (for frameless functions, and when
143 we're still in the prologue of a function with a frame). */
145 struct frame_extra_info
152 /* Addresses for calling Thumb functions have the bit 0 set.
153 Here are some macros to test, set, or clear bit 0 of addresses. */
154 #define IS_THUMB_ADDR(addr) ((addr) & 1)
155 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
156 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
159 arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
161 return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
164 /* Set to true if the 32-bit mode is in use. */
168 /* Flag set by arm_fix_call_dummy that tells whether the target
169 function is a Thumb function. This flag is checked by
170 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
171 its use in valops.c) to pass the function address as an additional
174 static int target_is_thumb;
176 /* Flag set by arm_fix_call_dummy that tells whether the calling
177 function is a Thumb function. This flag is checked by
178 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
180 static int caller_is_thumb;
182 /* Determine if the program counter specified in MEMADDR is in a Thumb
186 arm_pc_is_thumb (CORE_ADDR memaddr)
188 struct minimal_symbol *sym;
190 /* If bit 0 of the address is set, assume this is a Thumb address. */
191 if (IS_THUMB_ADDR (memaddr))
194 /* Thumb functions have a "special" bit set in minimal symbols. */
195 sym = lookup_minimal_symbol_by_pc (memaddr);
198 return (MSYMBOL_IS_SPECIAL (sym));
206 /* Determine if the program counter specified in MEMADDR is in a call
207 dummy being called from a Thumb function. */
210 arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
212 CORE_ADDR sp = read_sp ();
214 /* FIXME: Until we switch for the new call dummy macros, this heuristic
215 is the best we can do. We are trying to determine if the pc is on
216 the stack, which (hopefully) will only happen in a call dummy.
217 We hope the current stack pointer is not so far alway from the dummy
218 frame location (true if we have not pushed large data structures or
219 gone too many levels deep) and that our 1024 is not enough to consider
220 code regions as part of the stack (true for most practical purposes). */
221 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
222 return caller_is_thumb;
227 /* Remove useless bits from addresses in a running program. */
229 arm_addr_bits_remove (CORE_ADDR val)
232 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
234 return (val & 0x03fffffc);
237 /* When reading symbols, we need to zap the low bit of the address,
238 which may be set to 1 for Thumb functions. */
240 arm_smash_text_address (CORE_ADDR val)
245 /* Immediately after a function call, return the saved pc. Can't
246 always go through the frames for this because on some machines the
247 new frame is not set up until the new function executes some
251 arm_saved_pc_after_call (struct frame_info *frame)
253 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
256 /* Determine whether the function invocation represented by FI has a
257 frame on the stack associated with it. If it does return zero,
258 otherwise return 1. */
261 arm_frameless_function_invocation (struct frame_info *fi)
263 CORE_ADDR func_start, after_prologue;
266 /* Sometimes we have functions that do a little setup (like saving the
267 vN registers with the stmdb instruction, but DO NOT set up a frame.
268 The symbol table will report this as a prologue. However, it is
269 important not to try to parse these partial frames as frames, or we
270 will get really confused.
272 So I will demand 3 instructions between the start & end of the
273 prologue before I call it a real prologue, i.e. at least
278 func_start = (get_pc_function_start (get_frame_pc (fi)) + FUNCTION_START_OFFSET);
279 after_prologue = SKIP_PROLOGUE (func_start);
281 /* There are some frameless functions whose first two instructions
282 follow the standard APCS form, in which case after_prologue will
283 be func_start + 8. */
285 frameless = (after_prologue < func_start + 12);
289 /* The address of the arguments in the frame. */
291 arm_frame_args_address (struct frame_info *fi)
296 /* The address of the local variables in the frame. */
298 arm_frame_locals_address (struct frame_info *fi)
303 /* The number of arguments being passed in the frame. */
305 arm_frame_num_args (struct frame_info *fi)
307 /* We have no way of knowing. */
311 /* A typical Thumb prologue looks like this:
315 Sometimes the latter instruction may be replaced by:
323 or, on tpcs, like this:
330 There is always one instruction of three classes:
335 When we have found at least one of each class we are done with the prolog.
336 Note that the "sub sp, #NN" before the push does not count.
340 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
342 CORE_ADDR current_pc;
344 bit 0 - push { rlist }
345 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
346 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
350 for (current_pc = pc;
351 current_pc + 2 < func_end && current_pc < pc + 40;
354 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
356 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
358 findmask |= 1; /* push found */
360 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
363 if ((findmask & 1) == 0) /* before push ? */
366 findmask |= 4; /* add/sub sp found */
368 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
370 findmask |= 2; /* setting of r7 found */
372 else if (insn == 0x466f) /* mov r7, sp */
374 findmask |= 2; /* setting of r7 found */
376 else if (findmask == (4+2+1))
378 /* We have found one of each type of prologue instruction */
382 /* Something in the prolog that we don't care about or some
383 instruction from outside the prolog scheduled here for
391 /* Advance the PC across any function entry prologue instructions to
392 reach some "real" code.
394 The APCS (ARM Procedure Call Standard) defines the following
398 [stmfd sp!, {a1,a2,a3,a4}]
399 stmfd sp!, {...,fp,ip,lr,pc}
400 [stfe f7, [sp, #-12]!]
401 [stfe f6, [sp, #-12]!]
402 [stfe f5, [sp, #-12]!]
403 [stfe f4, [sp, #-12]!]
404 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
407 arm_skip_prologue (CORE_ADDR pc)
411 CORE_ADDR func_addr, func_end = 0;
413 struct symtab_and_line sal;
415 /* If we're in a dummy frame, don't even try to skip the prologue. */
416 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
419 /* See what the symbol table says. */
421 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
425 /* Found a function. */
426 sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL);
427 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
429 /* Don't use this trick for assembly source files. */
430 sal = find_pc_line (func_addr, 0);
431 if ((sal.line != 0) && (sal.end < func_end))
436 /* Check if this is Thumb code. */
437 if (arm_pc_is_thumb (pc))
438 return thumb_skip_prologue (pc, func_end);
440 /* Can't find the prologue end in the symbol table, try it the hard way
441 by disassembling the instructions. */
443 /* Like arm_scan_prologue, stop no later than pc + 64. */
444 if (func_end == 0 || func_end > pc + 64)
447 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
449 inst = read_memory_integer (skip_pc, 4);
451 /* "mov ip, sp" is no longer a required part of the prologue. */
452 if (inst == 0xe1a0c00d) /* mov ip, sp */
455 /* Some prologues begin with "str lr, [sp, #-4]!". */
456 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
459 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
462 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
465 /* Any insns after this point may float into the code, if it makes
466 for better instruction scheduling, so we skip them only if we
467 find them, but still consider the function to be frame-ful. */
469 /* We may have either one sfmfd instruction here, or several stfe
470 insns, depending on the version of floating point code we
472 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
475 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
478 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
481 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
484 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
485 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
486 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
489 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
490 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
491 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
494 /* Un-recognized instruction; stop scanning. */
498 return skip_pc; /* End of prologue */
502 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
503 This function decodes a Thumb function prologue to determine:
504 1) the size of the stack frame
505 2) which registers are saved on it
506 3) the offsets of saved regs
507 4) the offset from the stack pointer to the frame pointer
508 This information is stored in the "extra" fields of the frame_info.
510 A typical Thumb function prologue would create this stack frame
511 (offsets relative to FP)
512 old SP -> 24 stack parameters
515 R7 -> 0 local variables (16 bytes)
516 SP -> -12 additional stack space (12 bytes)
517 The frame size would thus be 36 bytes, and the frame offset would be
518 12 bytes. The frame register is R7.
520 The comments for thumb_skip_prolog() describe the algorithm we use
521 to detect the end of the prolog. */
525 thumb_scan_prologue (struct frame_info *fi)
527 CORE_ADDR prologue_start;
528 CORE_ADDR prologue_end;
529 CORE_ADDR current_pc;
530 /* Which register has been copied to register n? */
533 bit 0 - push { rlist }
534 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
535 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
540 /* Don't try to scan dummy frames. */
542 && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
545 if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end))
547 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
549 if (sal.line == 0) /* no line info, use current PC */
550 prologue_end = get_frame_pc (fi);
551 else if (sal.end < prologue_end) /* next line begins after fn end */
552 prologue_end = sal.end; /* (probably means no prologue) */
555 /* We're in the boondocks: allow for
556 16 pushes, an add, and "mv fp,sp". */
557 prologue_end = prologue_start + 40;
559 prologue_end = min (prologue_end, get_frame_pc (fi));
561 /* Initialize the saved register map. When register H is copied to
562 register L, we will put H in saved_reg[L]. */
563 for (i = 0; i < 16; i++)
566 /* Search the prologue looking for instructions that set up the
567 frame pointer, adjust the stack pointer, and save registers.
568 Do this until all basic prolog instructions are found. */
570 fi->extra_info->framesize = 0;
571 for (current_pc = prologue_start;
572 (current_pc < prologue_end) && ((findmask & 7) != 7);
579 insn = read_memory_unsigned_integer (current_pc, 2);
581 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
584 findmask |= 1; /* push found */
585 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
586 whether to save LR (R14). */
587 mask = (insn & 0xff) | ((insn & 0x100) << 6);
589 /* Calculate offsets of saved R0-R7 and LR. */
590 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
591 if (mask & (1 << regno))
593 fi->extra_info->framesize += 4;
594 get_frame_saved_regs (fi)[saved_reg[regno]] =
595 -(fi->extra_info->framesize);
596 /* Reset saved register map. */
597 saved_reg[regno] = regno;
600 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
603 if ((findmask & 1) == 0) /* before push? */
606 findmask |= 4; /* add/sub sp found */
608 offset = (insn & 0x7f) << 2; /* get scaled offset */
609 if (insn & 0x80) /* is it signed? (==subtracting) */
611 fi->extra_info->frameoffset += offset;
614 fi->extra_info->framesize -= offset;
616 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
618 findmask |= 2; /* setting of r7 found */
619 fi->extra_info->framereg = THUMB_FP_REGNUM;
620 /* get scaled offset */
621 fi->extra_info->frameoffset = (insn & 0xff) << 2;
623 else if (insn == 0x466f) /* mov r7, sp */
625 findmask |= 2; /* setting of r7 found */
626 fi->extra_info->framereg = THUMB_FP_REGNUM;
627 fi->extra_info->frameoffset = 0;
628 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
630 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
632 int lo_reg = insn & 7; /* dest. register (r0-r7) */
633 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
634 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
637 /* Something in the prolog that we don't care about or some
638 instruction from outside the prolog scheduled here for
644 /* Check if prologue for this frame's PC has already been scanned. If
645 it has, copy the relevant information about that prologue and
646 return non-zero. Otherwise do not copy anything and return zero.
648 The information saved in the cache includes:
649 * the frame register number;
650 * the size of the stack frame;
651 * the offsets of saved regs (relative to the old SP); and
652 * the offset from the stack pointer to the frame pointer
654 The cache contains only one entry, since this is adequate for the
655 typical sequence of prologue scan requests we get. When performing
656 a backtrace, GDB will usually ask to scan the same function twice
657 in a row (once to get the frame chain, and once to fill in the
658 extra frame information). */
660 static struct frame_info prologue_cache;
663 check_prologue_cache (struct frame_info *fi)
667 if (get_frame_pc (fi) == get_frame_pc (&prologue_cache))
669 fi->extra_info->framereg = prologue_cache.extra_info->framereg;
670 fi->extra_info->framesize = prologue_cache.extra_info->framesize;
671 fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset;
672 for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
673 get_frame_saved_regs (fi)[i] = get_frame_saved_regs (&prologue_cache)[i];
681 /* Copy the prologue information from fi to the prologue cache. */
684 save_prologue_cache (struct frame_info *fi)
688 deprecated_update_frame_pc_hack (&prologue_cache, get_frame_pc (fi));
689 prologue_cache.extra_info->framereg = fi->extra_info->framereg;
690 prologue_cache.extra_info->framesize = fi->extra_info->framesize;
691 prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset;
693 for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
694 get_frame_saved_regs (&prologue_cache)[i] = get_frame_saved_regs (fi)[i];
698 /* This function decodes an ARM function prologue to determine:
699 1) the size of the stack frame
700 2) which registers are saved on it
701 3) the offsets of saved regs
702 4) the offset from the stack pointer to the frame pointer
703 This information is stored in the "extra" fields of the frame_info.
705 There are two basic forms for the ARM prologue. The fixed argument
706 function call will look like:
709 stmfd sp!, {fp, ip, lr, pc}
713 Which would create this stack frame (offsets relative to FP):
714 IP -> 4 (caller's stack)
715 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
716 -4 LR (return address in caller)
717 -8 IP (copy of caller's SP)
719 SP -> -28 Local variables
721 The frame size would thus be 32 bytes, and the frame offset would be
722 28 bytes. The stmfd call can also save any of the vN registers it
723 plans to use, which increases the frame size accordingly.
725 Note: The stored PC is 8 off of the STMFD instruction that stored it
726 because the ARM Store instructions always store PC + 8 when you read
729 A variable argument function call will look like:
732 stmfd sp!, {a1, a2, a3, a4}
733 stmfd sp!, {fp, ip, lr, pc}
736 Which would create this stack frame (offsets relative to FP):
737 IP -> 20 (caller's stack)
742 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
743 -4 LR (return address in caller)
744 -8 IP (copy of caller's SP)
746 SP -> -28 Local variables
748 The frame size would thus be 48 bytes, and the frame offset would be
751 There is another potential complication, which is that the optimizer
752 will try to separate the store of fp in the "stmfd" instruction from
753 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
754 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
756 Also, note, the original version of the ARM toolchain claimed that there
759 instruction at the end of the prologue. I have never seen GCC produce
760 this, and the ARM docs don't mention it. We still test for it below in
766 arm_scan_prologue (struct frame_info *fi)
768 int regno, sp_offset, fp_offset;
769 LONGEST return_value;
770 CORE_ADDR prologue_start, prologue_end, current_pc;
772 /* Check if this function is already in the cache of frame information. */
773 if (check_prologue_cache (fi))
776 /* Assume there is no frame until proven otherwise. */
777 fi->extra_info->framereg = ARM_SP_REGNUM;
778 fi->extra_info->framesize = 0;
779 fi->extra_info->frameoffset = 0;
781 /* Check for Thumb prologue. */
782 if (arm_pc_is_thumb (get_frame_pc (fi)))
784 thumb_scan_prologue (fi);
785 save_prologue_cache (fi);
789 /* Find the function prologue. If we can't find the function in
790 the symbol table, peek in the stack frame to find the PC. */
791 if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end))
793 /* One way to find the end of the prologue (which works well
794 for unoptimized code) is to do the following:
796 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
799 prologue_end = get_frame_pc (fi);
800 else if (sal.end < prologue_end)
801 prologue_end = sal.end;
803 This mechanism is very accurate so long as the optimizer
804 doesn't move any instructions from the function body into the
805 prologue. If this happens, sal.end will be the last
806 instruction in the first hunk of prologue code just before
807 the first instruction that the scheduler has moved from
808 the body to the prologue.
810 In order to make sure that we scan all of the prologue
811 instructions, we use a slightly less accurate mechanism which
812 may scan more than necessary. To help compensate for this
813 lack of accuracy, the prologue scanning loop below contains
814 several clauses which'll cause the loop to terminate early if
815 an implausible prologue instruction is encountered.
821 is a suitable endpoint since it accounts for the largest
822 possible prologue plus up to five instructions inserted by
825 if (prologue_end > prologue_start + 64)
827 prologue_end = prologue_start + 64; /* See above. */
832 /* Get address of the stmfd in the prologue of the callee;
833 the saved PC is the address of the stmfd + 8. */
834 if (!safe_read_memory_integer (fi->frame, 4, &return_value))
838 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
839 prologue_end = prologue_start + 64; /* See above. */
843 /* Now search the prologue looking for instructions that set up the
844 frame pointer, adjust the stack pointer, and save registers.
846 Be careful, however, and if it doesn't look like a prologue,
847 don't try to scan it. If, for instance, a frameless function
848 begins with stmfd sp!, then we will tell ourselves there is
849 a frame, which will confuse stack traceback, as well as "finish"
850 and other operations that rely on a knowledge of the stack
853 In the APCS, the prologue should start with "mov ip, sp" so
854 if we don't see this as the first insn, we will stop.
856 [Note: This doesn't seem to be true any longer, so it's now an
857 optional part of the prologue. - Kevin Buettner, 2001-11-20]
859 [Note further: The "mov ip,sp" only seems to be missing in
860 frameless functions at optimization level "-O2" or above,
861 in which case it is often (but not always) replaced by
862 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
864 sp_offset = fp_offset = 0;
866 for (current_pc = prologue_start;
867 current_pc < prologue_end;
870 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
872 if (insn == 0xe1a0c00d) /* mov ip, sp */
876 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
878 /* Function is frameless: extra_info defaults OK? */
881 else if ((insn & 0xffff0000) == 0xe92d0000)
882 /* stmfd sp!, {..., fp, ip, lr, pc}
884 stmfd sp!, {a1, a2, a3, a4} */
886 int mask = insn & 0xffff;
888 /* Calculate offsets of saved registers. */
889 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
890 if (mask & (1 << regno))
893 get_frame_saved_regs (fi)[regno] = sp_offset;
896 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
897 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
898 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
900 /* No need to add this to saved_regs -- it's just an arg reg. */
903 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
904 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
905 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
907 /* No need to add this to saved_regs -- it's just an arg reg. */
910 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
912 unsigned imm = insn & 0xff; /* immediate value */
913 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
914 imm = (imm >> rot) | (imm << (32 - rot));
916 fi->extra_info->framereg = ARM_FP_REGNUM;
918 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
920 unsigned imm = insn & 0xff; /* immediate value */
921 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
922 imm = (imm >> rot) | (imm << (32 - rot));
925 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
928 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
929 get_frame_saved_regs (fi)[regno] = sp_offset;
931 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
934 unsigned int fp_start_reg, fp_bound_reg;
936 if ((insn & 0x800) == 0x800) /* N0 is set */
938 if ((insn & 0x40000) == 0x40000) /* N1 is set */
945 if ((insn & 0x40000) == 0x40000) /* N1 is set */
951 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
952 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
953 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
956 get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset;
959 else if ((insn & 0xf0000000) != 0xe0000000)
960 break; /* Condition not true, exit early */
961 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
962 break; /* Don't scan past a block load */
964 /* The optimizer might shove anything into the prologue,
965 so we just skip what we don't recognize. */
969 /* The frame size is just the negative of the offset (from the
970 original SP) of the last thing thing we pushed on the stack.
971 The frame offset is [new FP] - [new SP]. */
972 fi->extra_info->framesize = -sp_offset;
973 if (fi->extra_info->framereg == ARM_FP_REGNUM)
974 fi->extra_info->frameoffset = fp_offset - sp_offset;
976 fi->extra_info->frameoffset = 0;
978 save_prologue_cache (fi);
981 /* Find REGNUM on the stack. Otherwise, it's in an active register.
982 One thing we might want to do here is to check REGNUM against the
983 clobber mask, and somehow flag it as invalid if it isn't saved on
984 the stack somewhere. This would provide a graceful failure mode
985 when trying to get the value of caller-saves registers for an inner
989 arm_find_callers_reg (struct frame_info *fi, int regnum)
991 /* NOTE: cagney/2002-05-03: This function really shouldn't be
992 needed. Instead the (still being written) register unwind
993 function could be called directly. */
994 for (; fi; fi = fi->next)
996 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
998 return deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, regnum);
1000 else if (get_frame_saved_regs (fi)[regnum] != 0)
1002 /* NOTE: cagney/2002-05-03: This would normally need to
1003 handle ARM_SP_REGNUM as a special case as, according to
1004 the frame.h comments, saved_regs[SP_REGNUM] contains the
1005 SP value not its address. It appears that the ARM isn't
1006 doing this though. */
1007 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
1008 REGISTER_RAW_SIZE (regnum));
1011 return read_register (regnum);
1013 /* Function: frame_chain Given a GDB frame, determine the address of
1014 the calling function's frame. This will be used to create a new
1015 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and
1016 DEPRECATED_INIT_FRAME_PC will be called for the new frame. For
1017 ARM, we save the frame size when we initialize the frame_info. */
1020 arm_frame_chain (struct frame_info *fi)
1022 CORE_ADDR caller_pc;
1023 int framereg = fi->extra_info->framereg;
1025 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
1026 /* A generic call dummy's frame is the same as caller's. */
1029 if (get_frame_pc (fi) < LOWEST_PC)
1032 /* If the caller is the startup code, we're at the end of the chain. */
1033 caller_pc = FRAME_SAVED_PC (fi);
1035 /* If the caller is Thumb and the caller is ARM, or vice versa,
1036 the frame register of the caller is different from ours.
1037 So we must scan the prologue of the caller to determine its
1038 frame register number. */
1039 /* XXX Fixme, we should try to do this without creating a temporary
1041 if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi)))
1043 struct frame_info caller_fi;
1044 struct cleanup *old_chain;
1046 /* Create a temporary frame suitable for scanning the caller's
1048 memset (&caller_fi, 0, sizeof (caller_fi));
1049 caller_fi.extra_info = (struct frame_extra_info *)
1050 xcalloc (1, sizeof (struct frame_extra_info));
1051 old_chain = make_cleanup (xfree, caller_fi.extra_info);
1052 caller_fi.saved_regs = (CORE_ADDR *)
1053 xcalloc (1, SIZEOF_FRAME_SAVED_REGS);
1054 make_cleanup (xfree, caller_fi.saved_regs);
1056 /* Now, scan the prologue and obtain the frame register. */
1057 deprecated_update_frame_pc_hack (&caller_fi, caller_pc);
1058 arm_scan_prologue (&caller_fi);
1059 framereg = caller_fi.extra_info->framereg;
1061 /* Deallocate the storage associated with the temporary frame
1063 do_cleanups (old_chain);
1066 /* If the caller used a frame register, return its value.
1067 Otherwise, return the caller's stack pointer. */
1068 if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM)
1069 return arm_find_callers_reg (fi, framereg);
1071 return fi->frame + fi->extra_info->framesize;
1074 /* This function actually figures out the frame address for a given pc
1075 and sp. This is tricky because we sometimes don't use an explicit
1076 frame pointer, and the previous stack pointer isn't necessarily
1077 recorded on the stack. The only reliable way to get this info is
1078 to examine the prologue. FROMLEAF is a little confusing, it means
1079 this is the next frame up the chain AFTER a frameless function. If
1080 this is true, then the frame value for this frame is still in the
1084 arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1089 if (get_frame_saved_regs (fi) == NULL)
1090 frame_saved_regs_zalloc (fi);
1092 fi->extra_info = (struct frame_extra_info *)
1093 frame_obstack_alloc (sizeof (struct frame_extra_info));
1095 fi->extra_info->framesize = 0;
1096 fi->extra_info->frameoffset = 0;
1097 fi->extra_info->framereg = 0;
1100 deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (fi->next));
1102 memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi));
1104 /* Compute stack pointer for this frame. We use this value for both
1105 the sigtramp and call dummy cases. */
1108 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi->next), 0, 0))
1109 /* For generic dummy frames, pull the value direct from the frame.
1110 Having an unwind function to do this would be nice. */
1111 sp = deprecated_read_register_dummy (get_frame_pc (fi->next), fi->next->frame,
1114 sp = (fi->next->frame - fi->next->extra_info->frameoffset
1115 + fi->next->extra_info->framesize);
1117 /* Determine whether or not we're in a sigtramp frame.
1118 Unfortunately, it isn't sufficient to test (get_frame_type (fi)
1119 == SIGTRAMP_FRAME) because this value is sometimes set after
1120 invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1121 (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to
1122 determine if we need to use the sigcontext addresses for the
1125 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1126 against the name of the function, the code below will have to be
1127 changed to first fetch the name of the function and then pass
1128 this name to PC_IN_SIGTRAMP. */
1130 /* FIXME: cagney/2002-11-18: This problem will go away once
1131 frame.c:get_prev_frame() is modified to set the frame's type
1132 before calling functions like this. */
1134 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1135 && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0)))
1137 for (reg = 0; reg < NUM_REGS; reg++)
1138 get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg);
1140 /* FIXME: What about thumb mode? */
1141 fi->extra_info->framereg = ARM_SP_REGNUM;
1143 read_memory_integer (get_frame_saved_regs (fi)[fi->extra_info->framereg],
1144 REGISTER_RAW_SIZE (fi->extra_info->framereg));
1145 fi->extra_info->framesize = 0;
1146 fi->extra_info->frameoffset = 0;
1151 arm_scan_prologue (fi);
1154 /* This is the innermost frame? */
1155 fi->frame = read_register (fi->extra_info->framereg);
1156 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi->next), 0, 0))
1157 /* Next inner most frame is a dummy, just grab its frame.
1158 Dummy frames always have the same FP as their caller. */
1159 fi->frame = fi->next->frame;
1160 else if (fi->extra_info->framereg == ARM_FP_REGNUM
1161 || fi->extra_info->framereg == THUMB_FP_REGNUM)
1163 /* not the innermost frame */
1164 /* If we have an FP, the callee saved it. */
1165 if (get_frame_saved_regs (get_next_frame (fi))[fi->extra_info->framereg] != 0)
1167 read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[fi->extra_info->framereg], 4);
1169 /* If we were called by a frameless fn. then our frame is
1170 still in the frame pointer register on the board... */
1171 fi->frame = read_fp ();
1174 /* Calculate actual addresses of saved registers using offsets
1175 determined by arm_scan_prologue. */
1176 for (reg = 0; reg < NUM_REGS; reg++)
1177 if (get_frame_saved_regs (fi)[reg] != 0)
1178 get_frame_saved_regs (fi)[reg] += (fi->frame + fi->extra_info->framesize
1179 - fi->extra_info->frameoffset);
1184 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1185 is saved in the stack anywhere, otherwise we get it from the
1188 The old definition of this function was a macro:
1189 #define FRAME_SAVED_PC(FRAME) \
1190 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1193 arm_frame_saved_pc (struct frame_info *fi)
1195 /* If a dummy frame, pull the PC out of the frame's register buffer. */
1196 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
1197 return deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, ARM_PC_REGNUM);
1199 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame - fi->extra_info->frameoffset,
1202 return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM],
1203 REGISTER_RAW_SIZE (ARM_PC_REGNUM));
1207 CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM);
1208 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1212 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1213 Examine the Program Status Register to decide which state we're in. */
1218 if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
1219 return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
1221 return read_register (ARM_FP_REGNUM); /* R11 if ARM */
1224 /* Store into a struct frame_saved_regs the addresses of the saved
1225 registers of frame described by FRAME_INFO. This includes special
1226 registers such as PC and FP saved in special ways in the stack
1227 frame. SP is even more special: the address we return for it IS
1228 the sp for the next frame. */
1231 arm_frame_init_saved_regs (struct frame_info *fip)
1234 if (get_frame_saved_regs (fip))
1237 arm_init_extra_frame_info (0, fip);
1240 /* Set the return address for a generic dummy frame. ARM uses the
1244 arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1246 write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ());
1250 /* Push an empty stack frame, to record the current PC, etc. */
1253 arm_push_dummy_frame (void)
1255 CORE_ADDR old_sp = read_register (ARM_SP_REGNUM);
1256 CORE_ADDR sp = old_sp;
1257 CORE_ADDR fp, prologue_start;
1260 /* Push the two dummy prologue instructions in reverse order,
1261 so that they'll be in the correct low-to-high order in memory. */
1262 /* sub fp, ip, #4 */
1263 sp = push_word (sp, 0xe24cb004);
1264 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1265 prologue_start = sp = push_word (sp, 0xe92ddfff);
1267 /* Push a pointer to the dummy prologue + 12, because when stm
1268 instruction stores the PC, it stores the address of the stm
1269 instruction itself plus 12. */
1270 fp = sp = push_word (sp, prologue_start + 12);
1272 /* Push the processor status. */
1273 sp = push_word (sp, read_register (ARM_PS_REGNUM));
1275 /* Push all 16 registers starting with r15. */
1276 for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--)
1277 sp = push_word (sp, read_register (regnum));
1279 /* Update fp (for both Thumb and ARM) and sp. */
1280 write_register (ARM_FP_REGNUM, fp);
1281 write_register (THUMB_FP_REGNUM, fp);
1282 write_register (ARM_SP_REGNUM, sp);
1285 /* CALL_DUMMY_WORDS:
1286 This sequence of words is the instructions
1292 Note this is 12 bytes. */
1294 static LONGEST arm_call_dummy_words[] =
1296 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1299 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1300 breakpoint to the proper address in the call dummy, so that
1301 `finish' after a stop in a call dummy works.
1303 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1304 optimal solution, but the call to arm_fix_call_dummy is immediately
1305 followed by a call to run_stack_dummy, which is the only function
1306 where call_dummy_breakpoint_offset is actually used. */
1310 arm_set_call_dummy_breakpoint_offset (void)
1312 if (caller_is_thumb)
1313 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4);
1315 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8);
1318 /* Fix up the call dummy, based on whether the processor is currently
1319 in Thumb or ARM mode, and whether the target function is Thumb or
1320 ARM. There are three different situations requiring three
1323 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1324 been copied into the dummy parameter to this function.
1325 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1326 "mov pc,r4" instruction patched to be a "bx r4" instead.
1327 * Thumb calling anything: uses the Thumb dummy defined below, which
1328 works for calling both ARM and Thumb functions.
1330 All three call dummies expect to receive the target function
1331 address in R4, with the low bit set if it's a Thumb function. */
1334 arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1335 struct value **args, struct type *type, int gcc_p)
1337 static short thumb_dummy[4] =
1339 0xf000, 0xf801, /* bl label */
1340 0xdf18, /* swi 24 */
1341 0x4720, /* label: bx r4 */
1343 static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
1345 /* Set flag indicating whether the current PC is in a Thumb function. */
1346 caller_is_thumb = arm_pc_is_thumb (read_pc ());
1347 arm_set_call_dummy_breakpoint_offset ();
1349 /* If the target function is Thumb, set the low bit of the function
1350 address. And if the CPU is currently in ARM mode, patch the
1351 second instruction of call dummy to use a BX instruction to
1352 switch to Thumb mode. */
1353 target_is_thumb = arm_pc_is_thumb (fun);
1354 if (target_is_thumb)
1357 if (!caller_is_thumb)
1358 store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
1361 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1362 instead of the ARM one that's already been copied. This will
1363 work for both Thumb and ARM target functions. */
1364 if (caller_is_thumb)
1368 int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
1370 for (i = 0; i < len; i++)
1372 store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
1373 p += sizeof (thumb_dummy[0]);
1377 /* Put the target address in r4; the call dummy will copy this to
1379 write_register (4, fun);
1384 This function does not support passing parameters using the FPA
1385 variant of the APCS. It passes any floating point arguments in the
1386 general registers and/or on the stack. */
1389 arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1390 int struct_return, CORE_ADDR struct_addr)
1398 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1400 /* Walk through the list of args and determine how large a temporary
1401 stack is required. Need to take care here as structs may be
1402 passed on the stack, and we have to to push them. On the second
1403 pass, do the store. */
1406 for (second_pass = 0; second_pass < 2; second_pass++)
1408 /* Compute the FP using the information computed during the
1414 argreg = ARM_A1_REGNUM;
1417 /* The struct_return pointer occupies the first parameter
1418 passing register. */
1424 fprintf_unfiltered (gdb_stdlog,
1425 "struct return in %s = 0x%s\n",
1426 REGISTER_NAME (argreg),
1427 paddr (struct_addr));
1428 write_register (argreg, struct_addr);
1433 for (argnum = 0; argnum < nargs; argnum++)
1436 struct type *arg_type;
1437 struct type *target_type;
1438 enum type_code typecode;
1441 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1442 len = TYPE_LENGTH (arg_type);
1443 target_type = TYPE_TARGET_TYPE (arg_type);
1444 typecode = TYPE_CODE (arg_type);
1445 val = VALUE_CONTENTS (args[argnum]);
1447 /* If the argument is a pointer to a function, and it is a
1448 Thumb function, create a LOCAL copy of the value and set
1449 the THUMB bit in it. */
1451 && TYPE_CODE_PTR == typecode
1452 && target_type != NULL
1453 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1455 CORE_ADDR regval = extract_address (val, len);
1456 if (arm_pc_is_thumb (regval))
1459 store_address (val, len, MAKE_THUMB_ADDR (regval));
1463 /* Copy the argument to general registers or the stack in
1464 register-sized pieces. Large arguments are split between
1465 registers and stack. */
1468 int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
1470 if (argreg <= ARM_LAST_ARG_REGNUM)
1472 /* The argument is being passed in a general purpose
1476 CORE_ADDR regval = extract_address (val,
1479 fprintf_unfiltered (gdb_stdlog,
1480 "arg %d in %s = 0x%s\n",
1482 REGISTER_NAME (argreg),
1483 phex (regval, REGISTER_SIZE));
1484 write_register (argreg, regval);
1492 /* Push the arguments onto the stack. */
1494 fprintf_unfiltered (gdb_stdlog,
1495 "arg %d @ 0x%s + %d\n",
1496 argnum, paddr (fp), nstack);
1497 write_memory (fp + nstack, val, REGISTER_SIZE);
1499 nstack += REGISTER_SIZE;
1509 /* Return the botom of the argument list (pointed to by fp). */
1513 /* Pop the current frame. So long as the frame info has been
1514 initialized properly (see arm_init_extra_frame_info), this code
1515 works for dummy frames as well as regular frames. I.e, there's no
1516 need to have a special case for dummy frames. */
1518 arm_pop_frame (void)
1521 struct frame_info *frame = get_current_frame ();
1522 CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset
1523 + frame->extra_info->framesize);
1525 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
1527 generic_pop_dummy_frame ();
1528 flush_cached_frames ();
1532 for (regnum = 0; regnum < NUM_REGS; regnum++)
1533 if (get_frame_saved_regs (frame)[regnum] != 0)
1534 write_register (regnum,
1535 read_memory_integer (get_frame_saved_regs (frame)[regnum],
1536 REGISTER_RAW_SIZE (regnum)));
1538 write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame));
1539 write_register (ARM_SP_REGNUM, old_SP);
1541 flush_cached_frames ();
1545 print_fpu_flags (int flags)
1547 if (flags & (1 << 0))
1548 fputs ("IVO ", stdout);
1549 if (flags & (1 << 1))
1550 fputs ("DVZ ", stdout);
1551 if (flags & (1 << 2))
1552 fputs ("OFL ", stdout);
1553 if (flags & (1 << 3))
1554 fputs ("UFL ", stdout);
1555 if (flags & (1 << 4))
1556 fputs ("INX ", stdout);
1560 /* Print interesting information about the floating point processor
1561 (if present) or emulator. */
1563 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1564 struct frame_info *frame, const char *args)
1566 register unsigned long status = read_register (ARM_FPS_REGNUM);
1569 type = (status >> 24) & 127;
1570 printf ("%s FPU type %d\n",
1571 (status & (1 << 31)) ? "Hardware" : "Software",
1573 fputs ("mask: ", stdout);
1574 print_fpu_flags (status >> 16);
1575 fputs ("flags: ", stdout);
1576 print_fpu_flags (status);
1579 /* Return the GDB type object for the "standard" data type of data in
1582 static struct type *
1583 arm_register_type (int regnum)
1585 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1587 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1588 return builtin_type_arm_ext_big;
1590 return builtin_type_arm_ext_littlebyte_bigword;
1593 return builtin_type_int32;
1596 /* Index within `registers' of the first byte of the space for
1600 arm_register_byte (int regnum)
1602 if (regnum < ARM_F0_REGNUM)
1603 return regnum * INT_REGISTER_RAW_SIZE;
1604 else if (regnum < ARM_PS_REGNUM)
1605 return (NUM_GREGS * INT_REGISTER_RAW_SIZE
1606 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE);
1608 return (NUM_GREGS * INT_REGISTER_RAW_SIZE
1609 + NUM_FREGS * FP_REGISTER_RAW_SIZE
1610 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1613 /* Number of bytes of storage in the actual machine representation for
1614 register N. All registers are 4 bytes, except fp0 - fp7, which are
1615 12 bytes in length. */
1618 arm_register_raw_size (int regnum)
1620 if (regnum < ARM_F0_REGNUM)
1621 return INT_REGISTER_RAW_SIZE;
1622 else if (regnum < ARM_FPS_REGNUM)
1623 return FP_REGISTER_RAW_SIZE;
1625 return STATUS_REGISTER_SIZE;
1628 /* Number of bytes of storage in a program's representation
1631 arm_register_virtual_size (int regnum)
1633 if (regnum < ARM_F0_REGNUM)
1634 return INT_REGISTER_VIRTUAL_SIZE;
1635 else if (regnum < ARM_FPS_REGNUM)
1636 return FP_REGISTER_VIRTUAL_SIZE;
1638 return STATUS_REGISTER_SIZE;
1641 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1643 arm_register_sim_regno (int regnum)
1646 gdb_assert (reg >= 0 && reg < NUM_REGS);
1648 if (reg < NUM_GREGS)
1649 return SIM_ARM_R0_REGNUM + reg;
1652 if (reg < NUM_FREGS)
1653 return SIM_ARM_FP0_REGNUM + reg;
1656 if (reg < NUM_SREGS)
1657 return SIM_ARM_FPS_REGNUM + reg;
1660 internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
1663 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1664 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1665 It is thought that this is is the floating-point register format on
1666 little-endian systems. */
1669 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1673 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1674 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1676 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1678 floatformat_from_doublest (fmt, &d, dbl);
1682 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1685 floatformat_to_doublest (fmt, ptr, &d);
1686 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1687 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1689 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1694 condition_true (unsigned long cond, unsigned long status_reg)
1696 if (cond == INST_AL || cond == INST_NV)
1702 return ((status_reg & FLAG_Z) != 0);
1704 return ((status_reg & FLAG_Z) == 0);
1706 return ((status_reg & FLAG_C) != 0);
1708 return ((status_reg & FLAG_C) == 0);
1710 return ((status_reg & FLAG_N) != 0);
1712 return ((status_reg & FLAG_N) == 0);
1714 return ((status_reg & FLAG_V) != 0);
1716 return ((status_reg & FLAG_V) == 0);
1718 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1720 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1722 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1724 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1726 return (((status_reg & FLAG_Z) == 0) &&
1727 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1729 return (((status_reg & FLAG_Z) != 0) ||
1730 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1735 /* Support routines for single stepping. Calculate the next PC value. */
1736 #define submask(x) ((1L << ((x) + 1)) - 1)
1737 #define bit(obj,st) (((obj) >> (st)) & 1)
1738 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1739 #define sbits(obj,st,fn) \
1740 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1741 #define BranchDest(addr,instr) \
1742 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1745 static unsigned long
1746 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1747 unsigned long status_reg)
1749 unsigned long res, shift;
1750 int rm = bits (inst, 0, 3);
1751 unsigned long shifttype = bits (inst, 5, 6);
1755 int rs = bits (inst, 8, 11);
1756 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1759 shift = bits (inst, 7, 11);
1762 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1763 + (bit (inst, 4) ? 12 : 8))
1764 : read_register (rm));
1769 res = shift >= 32 ? 0 : res << shift;
1773 res = shift >= 32 ? 0 : res >> shift;
1779 res = ((res & 0x80000000L)
1780 ? ~((~res) >> shift) : res >> shift);
1783 case 3: /* ROR/RRX */
1786 res = (res >> 1) | (carry ? 0x80000000L : 0);
1788 res = (res >> shift) | (res << (32 - shift));
1792 return res & 0xffffffff;
1795 /* Return number of 1-bits in VAL. */
1798 bitcount (unsigned long val)
1801 for (nbits = 0; val != 0; nbits++)
1802 val &= val - 1; /* delete rightmost 1-bit in val */
1807 thumb_get_next_pc (CORE_ADDR pc)
1809 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1810 unsigned short inst1 = read_memory_integer (pc, 2);
1811 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1812 unsigned long offset;
1814 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1818 /* Fetch the saved PC from the stack. It's stored above
1819 all of the other registers. */
1820 offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
1821 sp = read_register (ARM_SP_REGNUM);
1822 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1823 nextpc = ADDR_BITS_REMOVE (nextpc);
1825 error ("Infinite loop detected");
1827 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1829 unsigned long status = read_register (ARM_PS_REGNUM);
1830 unsigned long cond = bits (inst1, 8, 11);
1831 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1832 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1834 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1836 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1838 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
1840 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1841 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1842 nextpc = pc_val + offset;
1849 arm_get_next_pc (CORE_ADDR pc)
1851 unsigned long pc_val;
1852 unsigned long this_instr;
1853 unsigned long status;
1856 if (arm_pc_is_thumb (pc))
1857 return thumb_get_next_pc (pc);
1859 pc_val = (unsigned long) pc;
1860 this_instr = read_memory_integer (pc, 4);
1861 status = read_register (ARM_PS_REGNUM);
1862 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1864 if (condition_true (bits (this_instr, 28, 31), status))
1866 switch (bits (this_instr, 24, 27))
1869 case 0x1: /* data processing */
1873 unsigned long operand1, operand2, result = 0;
1877 if (bits (this_instr, 12, 15) != 15)
1880 if (bits (this_instr, 22, 25) == 0
1881 && bits (this_instr, 4, 7) == 9) /* multiply */
1882 error ("Illegal update to pc in instruction");
1884 /* Multiply into PC */
1885 c = (status & FLAG_C) ? 1 : 0;
1886 rn = bits (this_instr, 16, 19);
1887 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1889 if (bit (this_instr, 25))
1891 unsigned long immval = bits (this_instr, 0, 7);
1892 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1893 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1896 else /* operand 2 is a shifted register */
1897 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1899 switch (bits (this_instr, 21, 24))
1902 result = operand1 & operand2;
1906 result = operand1 ^ operand2;
1910 result = operand1 - operand2;
1914 result = operand2 - operand1;
1918 result = operand1 + operand2;
1922 result = operand1 + operand2 + c;
1926 result = operand1 - operand2 + c;
1930 result = operand2 - operand1 + c;
1936 case 0xb: /* tst, teq, cmp, cmn */
1937 result = (unsigned long) nextpc;
1941 result = operand1 | operand2;
1945 /* Always step into a function. */
1950 result = operand1 & ~operand2;
1957 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1960 error ("Infinite loop detected");
1965 case 0x5: /* data transfer */
1968 if (bit (this_instr, 20))
1971 if (bits (this_instr, 12, 15) == 15)
1977 if (bit (this_instr, 22))
1978 error ("Illegal update to pc in instruction");
1980 /* byte write to PC */
1981 rn = bits (this_instr, 16, 19);
1982 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1983 if (bit (this_instr, 24))
1986 int c = (status & FLAG_C) ? 1 : 0;
1987 unsigned long offset =
1988 (bit (this_instr, 25)
1989 ? shifted_reg_val (this_instr, c, pc_val, status)
1990 : bits (this_instr, 0, 11));
1992 if (bit (this_instr, 23))
1997 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
2000 nextpc = ADDR_BITS_REMOVE (nextpc);
2003 error ("Infinite loop detected");
2009 case 0x9: /* block transfer */
2010 if (bit (this_instr, 20))
2013 if (bit (this_instr, 15))
2018 if (bit (this_instr, 23))
2021 unsigned long reglist = bits (this_instr, 0, 14);
2022 offset = bitcount (reglist) * 4;
2023 if (bit (this_instr, 24)) /* pre */
2026 else if (bit (this_instr, 24))
2030 unsigned long rn_val =
2031 read_register (bits (this_instr, 16, 19));
2033 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2037 nextpc = ADDR_BITS_REMOVE (nextpc);
2039 error ("Infinite loop detected");
2044 case 0xb: /* branch & link */
2045 case 0xa: /* branch */
2047 nextpc = BranchDest (pc, this_instr);
2049 nextpc = ADDR_BITS_REMOVE (nextpc);
2051 error ("Infinite loop detected");
2057 case 0xe: /* coproc ops */
2062 fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
2070 /* single_step() is called just before we want to resume the inferior,
2071 if we want to single-step it but there is no hardware or kernel
2072 single-step support. We find the target of the coming instruction
2075 single_step() is also called just after the inferior stops. If we
2076 had set up a simulated single-step, we undo our damage. */
2079 arm_software_single_step (enum target_signal sig, int insert_bpt)
2081 static int next_pc; /* State between setting and unsetting. */
2082 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
2086 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
2087 target_insert_breakpoint (next_pc, break_mem);
2090 target_remove_breakpoint (next_pc, break_mem);
2093 #include "bfd-in2.h"
2094 #include "libcoff.h"
2097 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2099 if (arm_pc_is_thumb (memaddr))
2101 static asymbol *asym;
2102 static combined_entry_type ce;
2103 static struct coff_symbol_struct csym;
2104 static struct _bfd fake_bfd;
2105 static bfd_target fake_target;
2107 if (csym.native == NULL)
2109 /* Create a fake symbol vector containing a Thumb symbol.
2110 This is solely so that the code in print_insn_little_arm()
2111 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2112 the presence of a Thumb symbol and switch to decoding
2113 Thumb instructions. */
2115 fake_target.flavour = bfd_target_coff_flavour;
2116 fake_bfd.xvec = &fake_target;
2117 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2119 csym.symbol.the_bfd = &fake_bfd;
2120 csym.symbol.name = "fake";
2121 asym = (asymbol *) & csym;
2124 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2125 info->symbols = &asym;
2128 info->symbols = NULL;
2130 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2131 return print_insn_big_arm (memaddr, info);
2133 return print_insn_little_arm (memaddr, info);
2136 /* The following define instruction sequences that will cause ARM
2137 cpu's to take an undefined instruction trap. These are used to
2138 signal a breakpoint to GDB.
2140 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2141 modes. A different instruction is required for each mode. The ARM
2142 cpu's can also be big or little endian. Thus four different
2143 instructions are needed to support all cases.
2145 Note: ARMv4 defines several new instructions that will take the
2146 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2147 not in fact add the new instructions. The new undefined
2148 instructions in ARMv4 are all instructions that had no defined
2149 behaviour in earlier chips. There is no guarantee that they will
2150 raise an exception, but may be treated as NOP's. In practice, it
2151 may only safe to rely on instructions matching:
2153 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2154 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2155 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2157 Even this may only true if the condition predicate is true. The
2158 following use a condition predicate of ALWAYS so it is always TRUE.
2160 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2161 and NetBSD all use a software interrupt rather than an undefined
2162 instruction to force a trap. This can be handled by by the
2163 abi-specific code during establishment of the gdbarch vector. */
2166 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2167 override these definitions. */
2168 #ifndef ARM_LE_BREAKPOINT
2169 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2171 #ifndef ARM_BE_BREAKPOINT
2172 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2174 #ifndef THUMB_LE_BREAKPOINT
2175 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2177 #ifndef THUMB_BE_BREAKPOINT
2178 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2181 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2182 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2183 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2184 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2186 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2187 the program counter value to determine whether a 16-bit or 32-bit
2188 breakpoint should be used. It returns a pointer to a string of
2189 bytes that encode a breakpoint instruction, stores the length of
2190 the string to *lenptr, and adjusts the program counter (if
2191 necessary) to point to the actual memory location where the
2192 breakpoint should be inserted. */
2194 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2195 breakpoints and storing their handles instread of what was in
2196 memory. It is nice that this is the same size as a handle -
2197 otherwise remote-rdp will have to change. */
2199 static const unsigned char *
2200 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2202 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2204 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
2206 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2207 *lenptr = tdep->thumb_breakpoint_size;
2208 return tdep->thumb_breakpoint;
2212 *lenptr = tdep->arm_breakpoint_size;
2213 return tdep->arm_breakpoint;
2217 /* Extract from an array REGBUF containing the (raw) register state a
2218 function return value of type TYPE, and copy that, in virtual
2219 format, into VALBUF. */
2222 arm_extract_return_value (struct type *type,
2223 struct regcache *regs,
2226 bfd_byte *valbuf = dst;
2228 if (TYPE_CODE_FLT == TYPE_CODE (type))
2230 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2232 switch (tdep->fp_model)
2236 /* The value is in register F0 in internal format. We need to
2237 extract the raw value and then convert it to the desired
2239 bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE];
2241 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2242 convert_from_extended (floatformat_from_type (type), tmpbuf,
2247 case ARM_FLOAT_SOFT:
2248 case ARM_FLOAT_SOFT_VFP:
2249 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2250 if (TYPE_LENGTH (type) > 4)
2251 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2252 valbuf + INT_REGISTER_RAW_SIZE);
2257 (__FILE__, __LINE__,
2258 "arm_extract_return_value: Floating point model not supported");
2262 else if (TYPE_CODE (type) == TYPE_CODE_INT
2263 || TYPE_CODE (type) == TYPE_CODE_CHAR
2264 || TYPE_CODE (type) == TYPE_CODE_BOOL
2265 || TYPE_CODE (type) == TYPE_CODE_PTR
2266 || TYPE_CODE (type) == TYPE_CODE_REF
2267 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2269 /* If the the type is a plain integer, then the access is
2270 straight-forward. Otherwise we have to play around a bit more. */
2271 int len = TYPE_LENGTH (type);
2272 int regno = ARM_A1_REGNUM;
2277 /* By using store_unsigned_integer we avoid having to do
2278 anything special for small big-endian values. */
2279 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2280 store_unsigned_integer (valbuf,
2281 (len > INT_REGISTER_RAW_SIZE
2282 ? INT_REGISTER_RAW_SIZE : len),
2284 len -= INT_REGISTER_RAW_SIZE;
2285 valbuf += INT_REGISTER_RAW_SIZE;
2290 /* For a structure or union the behaviour is as if the value had
2291 been stored to word-aligned memory and then loaded into
2292 registers with 32-bit load instruction(s). */
2293 int len = TYPE_LENGTH (type);
2294 int regno = ARM_A1_REGNUM;
2295 bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
2299 regcache_cooked_read (regs, regno++, tmpbuf);
2300 memcpy (valbuf, tmpbuf,
2301 len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
2302 len -= INT_REGISTER_RAW_SIZE;
2303 valbuf += INT_REGISTER_RAW_SIZE;
2308 /* Extract from an array REGBUF containing the (raw) register state
2309 the address in which a function should return its structure value. */
2312 arm_extract_struct_value_address (struct regcache *regcache)
2316 regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
2320 /* Will a function return an aggregate type in memory or in a
2321 register? Return 0 if an aggregate type can be returned in a
2322 register, 1 if it must be returned in memory. */
2325 arm_use_struct_convention (int gcc_p, struct type *type)
2328 register enum type_code code;
2330 /* In the ARM ABI, "integer" like aggregate types are returned in
2331 registers. For an aggregate type to be integer like, its size
2332 must be less than or equal to REGISTER_SIZE and the offset of
2333 each addressable subfield must be zero. Note that bit fields are
2334 not addressable, and all addressable subfields of unions always
2335 start at offset zero.
2337 This function is based on the behaviour of GCC 2.95.1.
2338 See: gcc/arm.c: arm_return_in_memory() for details.
2340 Note: All versions of GCC before GCC 2.95.2 do not set up the
2341 parameters correctly for a function returning the following
2342 structure: struct { float f;}; This should be returned in memory,
2343 not a register. Richard Earnshaw sent me a patch, but I do not
2344 know of any way to detect if a function like the above has been
2345 compiled with the correct calling convention. */
2347 /* All aggregate types that won't fit in a register must be returned
2349 if (TYPE_LENGTH (type) > REGISTER_SIZE)
2354 /* The only aggregate types that can be returned in a register are
2355 structs and unions. Arrays must be returned in memory. */
2356 code = TYPE_CODE (type);
2357 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2362 /* Assume all other aggregate types can be returned in a register.
2363 Run a check for structures, unions and arrays. */
2366 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2369 /* Need to check if this struct/union is "integer" like. For
2370 this to be true, its size must be less than or equal to
2371 REGISTER_SIZE and the offset of each addressable subfield
2372 must be zero. Note that bit fields are not addressable, and
2373 unions always start at offset zero. If any of the subfields
2374 is a floating point type, the struct/union cannot be an
2377 /* For each field in the object, check:
2378 1) Is it FP? --> yes, nRc = 1;
2379 2) Is it addressable (bitpos != 0) and
2380 not packed (bitsize == 0)?
2384 for (i = 0; i < TYPE_NFIELDS (type); i++)
2386 enum type_code field_type_code;
2387 field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
2389 /* Is it a floating point type field? */
2390 if (field_type_code == TYPE_CODE_FLT)
2396 /* If bitpos != 0, then we have to care about it. */
2397 if (TYPE_FIELD_BITPOS (type, i) != 0)
2399 /* Bitfields are not addressable. If the field bitsize is
2400 zero, then the field is not packed. Hence it cannot be
2401 a bitfield or any other packed type. */
2402 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2414 /* Write into appropriate registers a function return value of type
2415 TYPE, given in virtual format. */
2418 arm_store_return_value (struct type *type, struct regcache *regs,
2421 const bfd_byte *valbuf = src;
2423 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2425 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2426 char buf[ARM_MAX_REGISTER_RAW_SIZE];
2428 switch (tdep->fp_model)
2432 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2433 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2436 case ARM_FLOAT_SOFT:
2437 case ARM_FLOAT_SOFT_VFP:
2438 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2439 if (TYPE_LENGTH (type) > 4)
2440 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2441 valbuf + INT_REGISTER_RAW_SIZE);
2446 (__FILE__, __LINE__,
2447 "arm_store_return_value: Floating point model not supported");
2451 else if (TYPE_CODE (type) == TYPE_CODE_INT
2452 || TYPE_CODE (type) == TYPE_CODE_CHAR
2453 || TYPE_CODE (type) == TYPE_CODE_BOOL
2454 || TYPE_CODE (type) == TYPE_CODE_PTR
2455 || TYPE_CODE (type) == TYPE_CODE_REF
2456 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2458 if (TYPE_LENGTH (type) <= 4)
2460 /* Values of one word or less are zero/sign-extended and
2462 bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
2463 LONGEST val = unpack_long (type, valbuf);
2465 store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val);
2466 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2470 /* Integral values greater than one word are stored in consecutive
2471 registers starting with r0. This will always be a multiple of
2472 the regiser size. */
2473 int len = TYPE_LENGTH (type);
2474 int regno = ARM_A1_REGNUM;
2478 regcache_cooked_write (regs, regno++, valbuf);
2479 len -= INT_REGISTER_RAW_SIZE;
2480 valbuf += INT_REGISTER_RAW_SIZE;
2486 /* For a structure or union the behaviour is as if the value had
2487 been stored to word-aligned memory and then loaded into
2488 registers with 32-bit load instruction(s). */
2489 int len = TYPE_LENGTH (type);
2490 int regno = ARM_A1_REGNUM;
2491 bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
2495 memcpy (tmpbuf, valbuf,
2496 len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
2497 regcache_cooked_write (regs, regno++, tmpbuf);
2498 len -= INT_REGISTER_RAW_SIZE;
2499 valbuf += INT_REGISTER_RAW_SIZE;
2504 /* Store the address of the place in which to copy the structure the
2505 subroutine will return. This is called from call_function. */
2508 arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
2510 write_register (ARM_A1_REGNUM, addr);
2514 arm_get_longjmp_target (CORE_ADDR *pc)
2517 char buf[INT_REGISTER_RAW_SIZE];
2518 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2520 jb_addr = read_register (ARM_A1_REGNUM);
2522 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2523 INT_REGISTER_RAW_SIZE))
2526 *pc = extract_address (buf, INT_REGISTER_RAW_SIZE);
2530 /* Return non-zero if the PC is inside a thumb call thunk. */
2533 arm_in_call_stub (CORE_ADDR pc, char *name)
2535 CORE_ADDR start_addr;
2537 /* Find the starting address of the function containing the PC. If
2538 the caller didn't give us a name, look it up at the same time. */
2539 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2543 return strncmp (name, "_call_via_r", 11) == 0;
2546 /* If PC is in a Thumb call or return stub, return the address of the
2547 target PC, which is in a register. The thunk functions are called
2548 _called_via_xx, where x is the register name. The possible names
2549 are r0-r9, sl, fp, ip, sp, and lr. */
2552 arm_skip_stub (CORE_ADDR pc)
2555 CORE_ADDR start_addr;
2557 /* Find the starting address and name of the function containing the PC. */
2558 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2561 /* Call thunks always start with "_call_via_". */
2562 if (strncmp (name, "_call_via_", 10) == 0)
2564 /* Use the name suffix to determine which register contains the
2566 static char *table[15] =
2567 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2568 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2572 for (regno = 0; regno <= 14; regno++)
2573 if (strcmp (&name[10], table[regno]) == 0)
2574 return read_register (regno);
2577 return 0; /* not a stub */
2580 /* If the user changes the register disassembly flavor used for info
2581 register and other commands, we have to also switch the flavor used
2582 in opcodes for disassembly output. This function is run in the set
2583 disassembly_flavor command, and does that. */
2586 set_disassembly_flavor_sfunc (char *args, int from_tty,
2587 struct cmd_list_element *c)
2589 set_disassembly_flavor ();
2592 /* Return the ARM register name corresponding to register I. */
2594 arm_register_name (int i)
2596 return arm_register_names[i];
2600 set_disassembly_flavor (void)
2602 const char *setname, *setdesc, **regnames;
2605 /* Find the flavor that the user wants in the opcodes table. */
2607 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2608 while ((disassembly_flavor != setname)
2609 && (current < num_flavor_options))
2610 get_arm_regnames (++current, &setname, &setdesc, ®names);
2611 current_option = current;
2613 /* Fill our copy. */
2614 for (j = 0; j < numregs; j++)
2615 arm_register_names[j] = (char *) regnames[j];
2618 if (isupper (*regnames[ARM_PC_REGNUM]))
2620 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2621 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2625 arm_register_names[ARM_FPS_REGNUM] = "fps";
2626 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2629 /* Synchronize the disassembler. */
2630 set_arm_regname_option (current);
2633 /* arm_othernames implements the "othernames" command. This is kind
2634 of hacky, and I prefer the set-show disassembly-flavor which is
2635 also used for the x86 gdb. I will keep this around, however, in
2636 case anyone is actually using it. */
2639 arm_othernames (char *names, int n)
2641 /* Circle through the various flavors. */
2642 current_option = (current_option + 1) % num_flavor_options;
2644 disassembly_flavor = valid_flavors[current_option];
2645 set_disassembly_flavor ();
2648 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2649 for ARM linux targets using the struct offsets defined in <link.h>.
2650 Note, however, that link.h is not actually referred to in this file.
2651 Instead, the relevant structs offsets were obtained from examining
2652 link.h. (We can't refer to link.h from this file because the host
2653 system won't necessarily have it, or if it does, the structs which
2654 it defines will refer to the host system, not the target). */
2656 struct link_map_offsets *
2657 arm_linux_svr4_fetch_link_map_offsets (void)
2659 static struct link_map_offsets lmo;
2660 static struct link_map_offsets *lmp = 0;
2666 lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
2669 lmo.r_map_offset = 4;
2672 lmo.link_map_size = 20; /* Actual size is 552, but this is all we
2675 lmo.l_addr_offset = 0;
2676 lmo.l_addr_size = 4;
2678 lmo.l_name_offset = 4;
2679 lmo.l_name_size = 4;
2681 lmo.l_next_offset = 12;
2682 lmo.l_next_size = 4;
2684 lmo.l_prev_offset = 16;
2685 lmo.l_prev_size = 4;
2691 /* Test whether the coff symbol specific value corresponds to a Thumb
2695 coff_sym_is_thumb (int val)
2697 return (val == C_THUMBEXT ||
2698 val == C_THUMBSTAT ||
2699 val == C_THUMBEXTFUNC ||
2700 val == C_THUMBSTATFUNC ||
2701 val == C_THUMBLABEL);
2704 /* arm_coff_make_msymbol_special()
2705 arm_elf_make_msymbol_special()
2707 These functions test whether the COFF or ELF symbol corresponds to
2708 an address in thumb code, and set a "special" bit in a minimal
2709 symbol to indicate that it does. */
2712 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2714 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2716 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2718 MSYMBOL_SET_SPECIAL (msym);
2722 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2724 if (coff_sym_is_thumb (val))
2725 MSYMBOL_SET_SPECIAL (msym);
2729 static enum gdb_osabi
2730 arm_elf_osabi_sniffer (bfd *abfd)
2732 unsigned int elfosabi, eflags;
2733 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2735 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2740 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2741 file are conforming to the base specification for that machine
2742 (there are no OS-specific extensions). In order to determine the
2743 real OS in use we must look for OS notes that have been added. */
2744 bfd_map_over_sections (abfd,
2745 generic_elf_osabi_sniff_abi_tag_sections,
2747 if (osabi == GDB_OSABI_UNKNOWN)
2749 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2750 field for more information. */
2751 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2754 case EF_ARM_EABI_VER1:
2755 osabi = GDB_OSABI_ARM_EABI_V1;
2758 case EF_ARM_EABI_VER2:
2759 osabi = GDB_OSABI_ARM_EABI_V2;
2762 case EF_ARM_EABI_UNKNOWN:
2763 /* Assume GNU tools. */
2764 osabi = GDB_OSABI_ARM_APCS;
2768 internal_error (__FILE__, __LINE__,
2769 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2770 "version 0x%x", eflags);
2776 /* GNU tools use this value. Check note sections in this case,
2778 bfd_map_over_sections (abfd,
2779 generic_elf_osabi_sniff_abi_tag_sections,
2781 if (osabi == GDB_OSABI_UNKNOWN)
2783 /* Assume APCS ABI. */
2784 osabi = GDB_OSABI_ARM_APCS;
2788 case ELFOSABI_FREEBSD:
2789 osabi = GDB_OSABI_FREEBSD_ELF;
2792 case ELFOSABI_NETBSD:
2793 osabi = GDB_OSABI_NETBSD_ELF;
2796 case ELFOSABI_LINUX:
2797 osabi = GDB_OSABI_LINUX;
2805 /* Initialize the current architecture based on INFO. If possible,
2806 re-use an architecture from ARCHES, which is a list of
2807 architectures already created during this debugging session.
2809 Called e.g. at program startup, when reading a core file, and when
2810 reading a binary file. */
2812 static struct gdbarch *
2813 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2815 struct gdbarch_tdep *tdep;
2816 struct gdbarch *gdbarch;
2817 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2819 /* Try to deterimine the ABI of the object we are loading. */
2821 if (info.abfd != NULL)
2823 osabi = gdbarch_lookup_osabi (info.abfd);
2824 if (osabi == GDB_OSABI_UNKNOWN)
2826 switch (bfd_get_flavour (info.abfd))
2828 case bfd_target_aout_flavour:
2829 /* Assume it's an old APCS-style ABI. */
2830 osabi = GDB_OSABI_ARM_APCS;
2833 case bfd_target_coff_flavour:
2834 /* Assume it's an old APCS-style ABI. */
2836 osabi = GDB_OSABI_ARM_APCS;
2840 /* Leave it as "unknown". */
2845 /* Find a candidate among extant architectures. */
2846 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2848 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2850 /* Make sure the ABI selection matches. */
2851 tdep = gdbarch_tdep (arches->gdbarch);
2852 if (tdep && tdep->osabi == osabi)
2853 return arches->gdbarch;
2856 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2857 gdbarch = gdbarch_alloc (&info, tdep);
2859 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2860 ready to unwind the PC first (see frame.c:get_prev_frame()). */
2861 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
2863 tdep->osabi = osabi;
2865 /* This is the way it has always defaulted. */
2866 tdep->fp_model = ARM_FLOAT_FPA;
2869 switch (info.byte_order)
2871 case BFD_ENDIAN_BIG:
2872 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2873 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2874 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2875 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2879 case BFD_ENDIAN_LITTLE:
2880 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2881 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2882 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2883 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2888 internal_error (__FILE__, __LINE__,
2889 "arm_gdbarch_init: bad byte order for float format");
2892 /* On ARM targets char defaults to unsigned. */
2893 set_gdbarch_char_signed (gdbarch, 0);
2895 /* This should be low enough for everything. */
2896 tdep->lowest_pc = 0x20;
2897 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2899 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
2900 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2902 set_gdbarch_call_dummy_p (gdbarch, 1);
2903 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2905 set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
2906 set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
2907 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2908 set_gdbarch_call_dummy_length (gdbarch, 0);
2910 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2912 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2913 set_gdbarch_push_return_address (gdbarch, arm_push_return_address);
2915 set_gdbarch_push_arguments (gdbarch, arm_push_arguments);
2916 set_gdbarch_coerce_float_to_double (gdbarch,
2917 standard_coerce_float_to_double);
2919 /* Frame handling. */
2920 set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid);
2921 set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info);
2922 set_gdbarch_read_fp (gdbarch, arm_read_fp);
2923 set_gdbarch_frame_chain (gdbarch, arm_frame_chain);
2924 set_gdbarch_frameless_function_invocation
2925 (gdbarch, arm_frameless_function_invocation);
2926 set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc);
2927 set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address);
2928 set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address);
2929 set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args);
2930 set_gdbarch_frame_args_skip (gdbarch, 0);
2931 set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs);
2932 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2933 set_gdbarch_pop_frame (gdbarch, arm_pop_frame);
2935 /* Address manipulation. */
2936 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2937 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2939 /* Offset from address of function to start of its code. */
2940 set_gdbarch_function_start_offset (gdbarch, 0);
2942 /* Advance PC across function entry code. */
2943 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2945 /* Get the PC when a frame might not be available. */
2946 set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2948 /* The stack grows downward. */
2949 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2951 /* Breakpoint manipulation. */
2952 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2953 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2955 /* Information about registers, etc. */
2956 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2957 set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2958 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2959 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2960 set_gdbarch_register_byte (gdbarch, arm_register_byte);
2961 set_gdbarch_register_bytes (gdbarch,
2962 (NUM_GREGS * INT_REGISTER_RAW_SIZE
2963 + NUM_FREGS * FP_REGISTER_RAW_SIZE
2964 + NUM_SREGS * STATUS_REGISTER_SIZE));
2965 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2966 set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size);
2967 set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size);
2968 set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
2969 set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
2970 set_gdbarch_register_virtual_type (gdbarch, arm_register_type);
2972 /* Internal <-> external register number maps. */
2973 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2975 /* Integer registers are 4 bytes. */
2976 set_gdbarch_register_size (gdbarch, 4);
2977 set_gdbarch_register_name (gdbarch, arm_register_name);
2979 /* Returning results. */
2980 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2981 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
2982 set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return);
2983 set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
2984 set_gdbarch_extract_struct_value_address (gdbarch,
2985 arm_extract_struct_value_address);
2987 /* Single stepping. */
2988 /* XXX For an RDI target we should ask the target if it can single-step. */
2989 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2991 /* Minsymbol frobbing. */
2992 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2993 set_gdbarch_coff_make_msymbol_special (gdbarch,
2994 arm_coff_make_msymbol_special);
2996 /* Hook in the ABI-specific overrides, if they have been registered. */
2997 gdbarch_init_osabi (info, gdbarch, osabi);
2999 /* Now we have tuned the configuration, set a few final things,
3000 based on what the OS ABI has told us. */
3002 if (tdep->jb_pc >= 0)
3003 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3005 /* Floating point sizes and format. */
3006 switch (info.byte_order)
3008 case BFD_ENDIAN_BIG:
3009 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
3010 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
3011 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
3015 case BFD_ENDIAN_LITTLE:
3016 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
3017 if (tdep->fp_model == ARM_FLOAT_VFP
3018 || tdep->fp_model == ARM_FLOAT_SOFT_VFP)
3020 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
3021 set_gdbarch_long_double_format (gdbarch,
3022 &floatformat_ieee_double_little);
3026 set_gdbarch_double_format
3027 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
3028 set_gdbarch_long_double_format
3029 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
3034 internal_error (__FILE__, __LINE__,
3035 "arm_gdbarch_init: bad byte order for float format");
3038 /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
3039 references the old architecture vector, not the one we are
3041 if (get_frame_saved_regs (&prologue_cache) != NULL)
3042 xfree (get_frame_saved_regs (&prologue_cache));
3044 /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
3045 references the old architecture vector, not the one we are
3047 prologue_cache.saved_regs = (CORE_ADDR *)
3048 xcalloc (1, (sizeof (CORE_ADDR)
3049 * (gdbarch_num_regs (gdbarch)
3050 + gdbarch_num_pseudo_regs (gdbarch))));
3056 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3058 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3063 fprintf_unfiltered (file, "arm_dump_tdep: OS ABI = %s\n",
3064 gdbarch_osabi_name (tdep->osabi));
3066 fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
3067 (unsigned long) tdep->lowest_pc);
3071 arm_init_abi_eabi_v1 (struct gdbarch_info info,
3072 struct gdbarch *gdbarch)
3078 arm_init_abi_eabi_v2 (struct gdbarch_info info,
3079 struct gdbarch *gdbarch)
3085 arm_init_abi_apcs (struct gdbarch_info info,
3086 struct gdbarch *gdbarch)
3092 _initialize_arm_tdep (void)
3094 struct ui_file *stb;
3096 struct cmd_list_element *new_cmd;
3097 const char *setname;
3098 const char *setdesc;
3099 const char **regnames;
3101 static char *helptext;
3104 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3106 /* Register an ELF OS ABI sniffer for ARM binaries. */
3107 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3108 bfd_target_elf_flavour,
3109 arm_elf_osabi_sniffer);
3111 /* Register some ABI variants for embedded systems. */
3112 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
3113 arm_init_abi_eabi_v1);
3114 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
3115 arm_init_abi_eabi_v2);
3116 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
3119 tm_print_insn = gdb_print_insn_arm;
3121 /* Get the number of possible sets of register names defined in opcodes. */
3122 num_flavor_options = get_arm_regname_num_options ();
3124 /* Sync the opcode insn printer with our register viewer. */
3125 parse_arm_disassembler_option ("reg-names-std");
3127 /* Begin creating the help text. */
3128 stb = mem_fileopen ();
3129 fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
3130 The valid values are:\n");
3132 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3133 valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
3134 for (i = 0; i < num_flavor_options; i++)
3136 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3137 valid_flavors[i] = setname;
3138 fprintf_unfiltered (stb, "%s - %s\n", setname,
3140 /* Copy the default names (if found) and synchronize disassembler. */
3141 if (!strcmp (setname, "std"))
3143 disassembly_flavor = setname;
3145 for (j = 0; j < numregs; j++)
3146 arm_register_names[j] = (char *) regnames[j];
3147 set_arm_regname_option (i);
3150 /* Mark the end of valid options. */
3151 valid_flavors[num_flavor_options] = NULL;
3153 /* Finish the creation of the help text. */
3154 fprintf_unfiltered (stb, "The default is \"std\".");
3155 helptext = ui_file_xstrdup (stb, &length);
3156 ui_file_delete (stb);
3158 /* Add the disassembly-flavor command. */
3159 new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
3161 &disassembly_flavor,
3164 set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc);
3165 add_show_from_set (new_cmd, &showlist);
3167 /* ??? Maybe this should be a boolean. */
3168 add_show_from_set (add_set_cmd ("apcs32", no_class,
3169 var_zinteger, (char *) &arm_apcs_32,
3170 "Set usage of ARM 32-bit mode.\n", &setlist),
3173 /* Add the deprecated "othernames" command. */
3175 add_com ("othernames", class_obscure, arm_othernames,
3176 "Switch to the next set of register names.");
3178 /* Fill in the prologue_cache fields. */
3179 prologue_cache.saved_regs = NULL;
3180 prologue_cache.extra_info = (struct frame_extra_info *)
3181 xcalloc (1, sizeof (struct frame_extra_info));
3183 /* Debugging flag. */
3184 add_show_from_set (add_set_cmd ("arm", class_maintenance, var_zinteger,
3185 &arm_debug, "Set arm debugging.\n\
3186 When non-zero, arm specific debugging is enabled.", &setdebuglist),