1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
41 #include "gdb/sim-arm.h"
44 #include "coff/internal.h"
47 #include "gdb_assert.h"
51 /* Each OS has a different mechanism for accessing the various
52 registers stored in the sigcontext structure.
54 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
55 function pointer) which may be used to determine the addresses
56 of the various saved registers in the sigcontext structure.
58 For the ARM target, there are three parameters to this function.
59 The first is the pc value of the frame under consideration, the
60 second the stack pointer of this frame, and the last is the
61 register number to fetch.
63 If the tm.h file does not define this macro, then it's assumed that
64 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
67 When it comes time to multi-arching this code, see the identically
68 named machinery in ia64-tdep.c for an example of how it could be
69 done. It should not be necessary to modify the code below where
70 this macro is used. */
72 #ifdef SIGCONTEXT_REGISTER_ADDRESS
73 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
74 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
77 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
78 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
81 /* Macros for setting and testing a bit in a minimal symbol that marks
82 it as Thumb function. The MSB of the minimal symbol's "info" field
83 is used for this purpose.
85 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
86 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
88 #define MSYMBOL_SET_SPECIAL(msym) \
89 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
92 #define MSYMBOL_IS_SPECIAL(msym) \
93 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
95 /* The list of available "set arm ..." and "show arm ..." commands. */
96 static struct cmd_list_element *setarmcmdlist = NULL;
97 static struct cmd_list_element *showarmcmdlist = NULL;
99 /* The type of floating-point to use. Keep this in sync with enum
100 arm_float_model, and the help string in _initialize_arm_tdep. */
101 static const char *fp_model_strings[] =
110 /* A variable that can be configured by the user. */
111 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
112 static const char *current_fp_model = "auto";
114 /* Number of different reg name sets (options). */
115 static int num_disassembly_options;
117 /* We have more registers than the disassembler as gdb can print the value
118 of special registers as well.
119 The general register names are overwritten by whatever is being used by
120 the disassembler at the moment. We also adjust the case of cpsr and fps. */
122 /* Initial value: Register names used in ARM's ISA documentation. */
123 static char * arm_register_name_strings[] =
124 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
125 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
126 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
127 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
128 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
129 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
130 "fps", "cpsr" }; /* 24 25 */
131 static char **arm_register_names = arm_register_name_strings;
133 /* Valid register name styles. */
134 static const char **valid_disassembly_styles;
136 /* Disassembly style to use. Default to "std" register names. */
137 static const char *disassembly_style;
138 /* Index to that option in the opcodes table. */
139 static int current_option;
141 /* This is used to keep the bfd arch_info in sync with the disassembly
143 static void set_disassembly_style_sfunc(char *, int,
144 struct cmd_list_element *);
145 static void set_disassembly_style (void);
147 static void convert_from_extended (const struct floatformat *, const void *,
149 static void convert_to_extended (const struct floatformat *, void *,
152 struct arm_prologue_cache
154 /* The stack pointer at the time this frame was created; i.e. the
155 caller's stack pointer when this function was called. It is used
156 to identify this frame. */
159 /* The frame base for this frame is just prev_sp + frame offset -
160 frame size. FRAMESIZE is the size of this stack frame, and
161 FRAMEOFFSET if the initial offset from the stack pointer (this
162 frame's stack pointer, not PREV_SP) to the frame base. */
167 /* The register used to hold the frame pointer for this frame. */
170 /* Saved register offsets. */
171 struct trad_frame_saved_reg *saved_regs;
174 /* Addresses for calling Thumb functions have the bit 0 set.
175 Here are some macros to test, set, or clear bit 0 of addresses. */
176 #define IS_THUMB_ADDR(addr) ((addr) & 1)
177 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
178 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
180 /* Set to true if the 32-bit mode is in use. */
184 /* Flag set by arm_fix_call_dummy that tells whether the target
185 function is a Thumb function. This flag is checked by
186 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
187 its use in valops.c) to pass the function address as an additional
190 static int target_is_thumb;
192 /* Flag set by arm_fix_call_dummy that tells whether the calling
193 function is a Thumb function. This flag is checked by
196 static int caller_is_thumb;
198 /* Determine if the program counter specified in MEMADDR is in a Thumb
202 arm_pc_is_thumb (CORE_ADDR memaddr)
204 struct minimal_symbol *sym;
206 /* If bit 0 of the address is set, assume this is a Thumb address. */
207 if (IS_THUMB_ADDR (memaddr))
210 /* Thumb functions have a "special" bit set in minimal symbols. */
211 sym = lookup_minimal_symbol_by_pc (memaddr);
214 return (MSYMBOL_IS_SPECIAL (sym));
222 /* Determine if the program counter specified in MEMADDR is in a call
223 dummy being called from a Thumb function. */
226 arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
228 CORE_ADDR sp = read_sp ();
230 /* FIXME: Until we switch for the new call dummy macros, this heuristic
231 is the best we can do. We are trying to determine if the pc is on
232 the stack, which (hopefully) will only happen in a call dummy.
233 We hope the current stack pointer is not so far alway from the dummy
234 frame location (true if we have not pushed large data structures or
235 gone too many levels deep) and that our 1024 is not enough to consider
236 code regions as part of the stack (true for most practical purposes). */
237 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
238 return caller_is_thumb;
243 /* Remove useless bits from addresses in a running program. */
245 arm_addr_bits_remove (CORE_ADDR val)
248 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
250 return (val & 0x03fffffc);
253 /* When reading symbols, we need to zap the low bit of the address,
254 which may be set to 1 for Thumb functions. */
256 arm_smash_text_address (CORE_ADDR val)
261 /* Immediately after a function call, return the saved pc. Can't
262 always go through the frames for this because on some machines the
263 new frame is not set up until the new function executes some
267 arm_saved_pc_after_call (struct frame_info *frame)
269 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
272 /* Determine whether the function invocation represented by FI has a
273 frame on the stack associated with it. If it does return zero,
274 otherwise return 1. */
277 arm_frameless_function_invocation (struct frame_info *fi)
279 CORE_ADDR func_start, after_prologue;
282 /* Sometimes we have functions that do a little setup (like saving the
283 vN registers with the stmdb instruction, but DO NOT set up a frame.
284 The symbol table will report this as a prologue. However, it is
285 important not to try to parse these partial frames as frames, or we
286 will get really confused.
288 So I will demand 3 instructions between the start & end of the
289 prologue before I call it a real prologue, i.e. at least
294 func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET);
295 after_prologue = SKIP_PROLOGUE (func_start);
297 /* There are some frameless functions whose first two instructions
298 follow the standard APCS form, in which case after_prologue will
299 be func_start + 8. */
301 frameless = (after_prologue < func_start + 12);
305 /* A typical Thumb prologue looks like this:
309 Sometimes the latter instruction may be replaced by:
317 or, on tpcs, like this:
324 There is always one instruction of three classes:
329 When we have found at least one of each class we are done with the prolog.
330 Note that the "sub sp, #NN" before the push does not count.
334 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
336 CORE_ADDR current_pc;
338 bit 0 - push { rlist }
339 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
340 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
344 for (current_pc = pc;
345 current_pc + 2 < func_end && current_pc < pc + 40;
348 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
350 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
352 findmask |= 1; /* push found */
354 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
357 if ((findmask & 1) == 0) /* before push ? */
360 findmask |= 4; /* add/sub sp found */
362 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
364 findmask |= 2; /* setting of r7 found */
366 else if (insn == 0x466f) /* mov r7, sp */
368 findmask |= 2; /* setting of r7 found */
370 else if (findmask == (4+2+1))
372 /* We have found one of each type of prologue instruction */
376 /* Something in the prolog that we don't care about or some
377 instruction from outside the prolog scheduled here for
385 /* Advance the PC across any function entry prologue instructions to
386 reach some "real" code.
388 The APCS (ARM Procedure Call Standard) defines the following
392 [stmfd sp!, {a1,a2,a3,a4}]
393 stmfd sp!, {...,fp,ip,lr,pc}
394 [stfe f7, [sp, #-12]!]
395 [stfe f6, [sp, #-12]!]
396 [stfe f5, [sp, #-12]!]
397 [stfe f4, [sp, #-12]!]
398 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
401 arm_skip_prologue (CORE_ADDR pc)
405 CORE_ADDR func_addr, func_end = 0;
407 struct symtab_and_line sal;
409 /* If we're in a dummy frame, don't even try to skip the prologue. */
410 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
413 /* See what the symbol table says. */
415 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
419 /* Found a function. */
420 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
421 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
423 /* Don't use this trick for assembly source files. */
424 sal = find_pc_line (func_addr, 0);
425 if ((sal.line != 0) && (sal.end < func_end))
430 /* Check if this is Thumb code. */
431 if (arm_pc_is_thumb (pc))
432 return thumb_skip_prologue (pc, func_end);
434 /* Can't find the prologue end in the symbol table, try it the hard way
435 by disassembling the instructions. */
437 /* Like arm_scan_prologue, stop no later than pc + 64. */
438 if (func_end == 0 || func_end > pc + 64)
441 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
443 inst = read_memory_integer (skip_pc, 4);
445 /* "mov ip, sp" is no longer a required part of the prologue. */
446 if (inst == 0xe1a0c00d) /* mov ip, sp */
449 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
452 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
455 /* Some prologues begin with "str lr, [sp, #-4]!". */
456 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
459 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
462 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
465 /* Any insns after this point may float into the code, if it makes
466 for better instruction scheduling, so we skip them only if we
467 find them, but still consider the function to be frame-ful. */
469 /* We may have either one sfmfd instruction here, or several stfe
470 insns, depending on the version of floating point code we
472 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
475 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
478 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
481 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
484 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
485 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
486 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
489 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
490 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
491 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
494 /* Un-recognized instruction; stop scanning. */
498 return skip_pc; /* End of prologue */
502 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
503 This function decodes a Thumb function prologue to determine:
504 1) the size of the stack frame
505 2) which registers are saved on it
506 3) the offsets of saved regs
507 4) the offset from the stack pointer to the frame pointer
509 A typical Thumb function prologue would create this stack frame
510 (offsets relative to FP)
511 old SP -> 24 stack parameters
514 R7 -> 0 local variables (16 bytes)
515 SP -> -12 additional stack space (12 bytes)
516 The frame size would thus be 36 bytes, and the frame offset would be
517 12 bytes. The frame register is R7.
519 The comments for thumb_skip_prolog() describe the algorithm we use
520 to detect the end of the prolog. */
524 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
526 CORE_ADDR prologue_start;
527 CORE_ADDR prologue_end;
528 CORE_ADDR current_pc;
529 /* Which register has been copied to register n? */
532 bit 0 - push { rlist }
533 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
534 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
539 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
541 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
543 if (sal.line == 0) /* no line info, use current PC */
544 prologue_end = prev_pc;
545 else if (sal.end < prologue_end) /* next line begins after fn end */
546 prologue_end = sal.end; /* (probably means no prologue) */
549 /* We're in the boondocks: allow for
550 16 pushes, an add, and "mv fp,sp". */
551 prologue_end = prologue_start + 40;
553 prologue_end = min (prologue_end, prev_pc);
555 /* Initialize the saved register map. When register H is copied to
556 register L, we will put H in saved_reg[L]. */
557 for (i = 0; i < 16; i++)
560 /* Search the prologue looking for instructions that set up the
561 frame pointer, adjust the stack pointer, and save registers.
562 Do this until all basic prolog instructions are found. */
564 cache->framesize = 0;
565 for (current_pc = prologue_start;
566 (current_pc < prologue_end) && ((findmask & 7) != 7);
573 insn = read_memory_unsigned_integer (current_pc, 2);
575 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
578 findmask |= 1; /* push found */
579 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
580 whether to save LR (R14). */
581 mask = (insn & 0xff) | ((insn & 0x100) << 6);
583 /* Calculate offsets of saved R0-R7 and LR. */
584 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
585 if (mask & (1 << regno))
587 cache->framesize += 4;
588 cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
589 /* Reset saved register map. */
590 saved_reg[regno] = regno;
593 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
596 if ((findmask & 1) == 0) /* before push? */
599 findmask |= 4; /* add/sub sp found */
601 offset = (insn & 0x7f) << 2; /* get scaled offset */
602 if (insn & 0x80) /* is it signed? (==subtracting) */
604 cache->frameoffset += offset;
607 cache->framesize -= offset;
609 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
611 findmask |= 2; /* setting of r7 found */
612 cache->framereg = THUMB_FP_REGNUM;
613 /* get scaled offset */
614 cache->frameoffset = (insn & 0xff) << 2;
616 else if (insn == 0x466f) /* mov r7, sp */
618 findmask |= 2; /* setting of r7 found */
619 cache->framereg = THUMB_FP_REGNUM;
620 cache->frameoffset = 0;
621 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
623 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
625 int lo_reg = insn & 7; /* dest. register (r0-r7) */
626 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
627 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
630 /* Something in the prolog that we don't care about or some
631 instruction from outside the prolog scheduled here for
637 /* This function decodes an ARM function prologue to determine:
638 1) the size of the stack frame
639 2) which registers are saved on it
640 3) the offsets of saved regs
641 4) the offset from the stack pointer to the frame pointer
642 This information is stored in the "extra" fields of the frame_info.
644 There are two basic forms for the ARM prologue. The fixed argument
645 function call will look like:
648 stmfd sp!, {fp, ip, lr, pc}
652 Which would create this stack frame (offsets relative to FP):
653 IP -> 4 (caller's stack)
654 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
655 -4 LR (return address in caller)
656 -8 IP (copy of caller's SP)
658 SP -> -28 Local variables
660 The frame size would thus be 32 bytes, and the frame offset would be
661 28 bytes. The stmfd call can also save any of the vN registers it
662 plans to use, which increases the frame size accordingly.
664 Note: The stored PC is 8 off of the STMFD instruction that stored it
665 because the ARM Store instructions always store PC + 8 when you read
668 A variable argument function call will look like:
671 stmfd sp!, {a1, a2, a3, a4}
672 stmfd sp!, {fp, ip, lr, pc}
675 Which would create this stack frame (offsets relative to FP):
676 IP -> 20 (caller's stack)
681 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
682 -4 LR (return address in caller)
683 -8 IP (copy of caller's SP)
685 SP -> -28 Local variables
687 The frame size would thus be 48 bytes, and the frame offset would be
690 There is another potential complication, which is that the optimizer
691 will try to separate the store of fp in the "stmfd" instruction from
692 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
693 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
695 Also, note, the original version of the ARM toolchain claimed that there
698 instruction at the end of the prologue. I have never seen GCC produce
699 this, and the ARM docs don't mention it. We still test for it below in
705 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
707 int regno, sp_offset, fp_offset, ip_offset;
708 CORE_ADDR prologue_start, prologue_end, current_pc;
709 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
711 /* Assume there is no frame until proven otherwise. */
712 cache->framereg = ARM_SP_REGNUM;
713 cache->framesize = 0;
714 cache->frameoffset = 0;
716 /* Check for Thumb prologue. */
717 if (arm_pc_is_thumb (prev_pc))
719 thumb_scan_prologue (prev_pc, cache);
723 /* Find the function prologue. If we can't find the function in
724 the symbol table, peek in the stack frame to find the PC. */
725 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
727 /* One way to find the end of the prologue (which works well
728 for unoptimized code) is to do the following:
730 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
733 prologue_end = prev_pc;
734 else if (sal.end < prologue_end)
735 prologue_end = sal.end;
737 This mechanism is very accurate so long as the optimizer
738 doesn't move any instructions from the function body into the
739 prologue. If this happens, sal.end will be the last
740 instruction in the first hunk of prologue code just before
741 the first instruction that the scheduler has moved from
742 the body to the prologue.
744 In order to make sure that we scan all of the prologue
745 instructions, we use a slightly less accurate mechanism which
746 may scan more than necessary. To help compensate for this
747 lack of accuracy, the prologue scanning loop below contains
748 several clauses which'll cause the loop to terminate early if
749 an implausible prologue instruction is encountered.
755 is a suitable endpoint since it accounts for the largest
756 possible prologue plus up to five instructions inserted by
759 if (prologue_end > prologue_start + 64)
761 prologue_end = prologue_start + 64; /* See above. */
766 /* We have no symbol information. Our only option is to assume this
767 function has a standard stack frame and the normal frame register.
768 Then, we can find the value of our frame pointer on entrance to
769 the callee (or at the present moment if this is the innermost frame).
770 The value stored there should be the address of the stmfd + 8. */
772 LONGEST return_value;
774 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
775 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
779 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
780 prologue_end = prologue_start + 64; /* See above. */
784 if (prev_pc < prologue_end)
785 prologue_end = prev_pc;
787 /* Now search the prologue looking for instructions that set up the
788 frame pointer, adjust the stack pointer, and save registers.
790 Be careful, however, and if it doesn't look like a prologue,
791 don't try to scan it. If, for instance, a frameless function
792 begins with stmfd sp!, then we will tell ourselves there is
793 a frame, which will confuse stack traceback, as well as "finish"
794 and other operations that rely on a knowledge of the stack
797 In the APCS, the prologue should start with "mov ip, sp" so
798 if we don't see this as the first insn, we will stop.
800 [Note: This doesn't seem to be true any longer, so it's now an
801 optional part of the prologue. - Kevin Buettner, 2001-11-20]
803 [Note further: The "mov ip,sp" only seems to be missing in
804 frameless functions at optimization level "-O2" or above,
805 in which case it is often (but not always) replaced by
806 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
808 sp_offset = fp_offset = ip_offset = 0;
810 for (current_pc = prologue_start;
811 current_pc < prologue_end;
814 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
816 if (insn == 0xe1a0c00d) /* mov ip, sp */
821 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
823 unsigned imm = insn & 0xff; /* immediate value */
824 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
825 imm = (imm >> rot) | (imm << (32 - rot));
829 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
831 unsigned imm = insn & 0xff; /* immediate value */
832 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
833 imm = (imm >> rot) | (imm << (32 - rot));
837 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
840 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
843 else if ((insn & 0xffff0000) == 0xe92d0000)
844 /* stmfd sp!, {..., fp, ip, lr, pc}
846 stmfd sp!, {a1, a2, a3, a4} */
848 int mask = insn & 0xffff;
850 /* Calculate offsets of saved registers. */
851 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
852 if (mask & (1 << regno))
855 cache->saved_regs[regno].addr = sp_offset;
858 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
859 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
860 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
862 /* No need to add this to saved_regs -- it's just an arg reg. */
865 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
866 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
867 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
869 /* No need to add this to saved_regs -- it's just an arg reg. */
872 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
874 unsigned imm = insn & 0xff; /* immediate value */
875 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
876 imm = (imm >> rot) | (imm << (32 - rot));
877 fp_offset = -imm + ip_offset;
878 cache->framereg = ARM_FP_REGNUM;
880 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
882 unsigned imm = insn & 0xff; /* immediate value */
883 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
884 imm = (imm >> rot) | (imm << (32 - rot));
887 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
890 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
891 cache->saved_regs[regno].addr = sp_offset;
893 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
896 unsigned int fp_start_reg, fp_bound_reg;
898 if ((insn & 0x800) == 0x800) /* N0 is set */
900 if ((insn & 0x40000) == 0x40000) /* N1 is set */
907 if ((insn & 0x40000) == 0x40000) /* N1 is set */
913 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
914 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
915 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
918 cache->saved_regs[fp_start_reg++].addr = sp_offset;
921 else if ((insn & 0xf0000000) != 0xe0000000)
922 break; /* Condition not true, exit early */
923 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
924 break; /* Don't scan past a block load */
926 /* The optimizer might shove anything into the prologue,
927 so we just skip what we don't recognize. */
931 /* The frame size is just the negative of the offset (from the
932 original SP) of the last thing thing we pushed on the stack.
933 The frame offset is [new FP] - [new SP]. */
934 cache->framesize = -sp_offset;
935 if (cache->framereg == ARM_FP_REGNUM)
936 cache->frameoffset = fp_offset - sp_offset;
938 cache->frameoffset = 0;
941 static struct arm_prologue_cache *
942 arm_make_prologue_cache (struct frame_info *next_frame)
945 struct arm_prologue_cache *cache;
946 CORE_ADDR unwound_fp;
948 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
949 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
951 arm_scan_prologue (next_frame, cache);
953 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
957 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
959 /* Calculate actual addresses of saved registers using offsets
960 determined by arm_scan_prologue. */
961 for (reg = 0; reg < NUM_REGS; reg++)
962 if (trad_frame_addr_p (cache->saved_regs, reg))
963 cache->saved_regs[reg].addr += cache->prev_sp;
968 /* Our frame ID for a normal frame is the current function's starting PC
969 and the caller's SP when we were called. */
972 arm_prologue_this_id (struct frame_info *next_frame,
974 struct frame_id *this_id)
976 struct arm_prologue_cache *cache;
980 if (*this_cache == NULL)
981 *this_cache = arm_make_prologue_cache (next_frame);
984 func = frame_func_unwind (next_frame);
986 /* This is meant to halt the backtrace at "_start". Make sure we
987 don't halt it at a generic dummy frame. */
988 if (func <= LOWEST_PC)
991 /* If we've hit a wall, stop. */
992 if (cache->prev_sp == 0)
995 id = frame_id_build (cache->prev_sp, func);
1000 arm_prologue_prev_register (struct frame_info *next_frame,
1004 enum lval_type *lvalp,
1009 struct arm_prologue_cache *cache;
1011 if (*this_cache == NULL)
1012 *this_cache = arm_make_prologue_cache (next_frame);
1013 cache = *this_cache;
1015 /* If we are asked to unwind the PC, then we need to return the LR
1016 instead. The saved value of PC points into this frame's
1017 prologue, not the next frame's resume location. */
1018 if (prev_regnum == ARM_PC_REGNUM)
1019 prev_regnum = ARM_LR_REGNUM;
1021 /* SP is generally not saved to the stack, but this frame is
1022 identified by NEXT_FRAME's stack pointer at the time of the call.
1023 The value was already reconstructed into PREV_SP. */
1024 if (prev_regnum == ARM_SP_REGNUM)
1028 store_unsigned_integer (valuep, 4, cache->prev_sp);
1032 trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
1033 optimized, lvalp, addrp, realnump, valuep);
1036 struct frame_unwind arm_prologue_unwind = {
1038 arm_prologue_this_id,
1039 arm_prologue_prev_register
1042 static const struct frame_unwind *
1043 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
1045 return &arm_prologue_unwind;
1049 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1051 struct arm_prologue_cache *cache;
1053 if (*this_cache == NULL)
1054 *this_cache = arm_make_prologue_cache (next_frame);
1055 cache = *this_cache;
1057 return cache->prev_sp + cache->frameoffset - cache->framesize;
1060 struct frame_base arm_normal_base = {
1061 &arm_prologue_unwind,
1062 arm_normal_frame_base,
1063 arm_normal_frame_base,
1064 arm_normal_frame_base
1067 static struct arm_prologue_cache *
1068 arm_make_sigtramp_cache (struct frame_info *next_frame)
1070 struct arm_prologue_cache *cache;
1073 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
1075 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1077 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1079 for (reg = 0; reg < NUM_REGS; reg++)
1080 cache->saved_regs[reg].addr
1081 = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp,
1082 frame_pc_unwind (next_frame), reg);
1084 /* FIXME: What about thumb mode? */
1085 cache->framereg = ARM_SP_REGNUM;
1087 = read_memory_integer (cache->saved_regs[cache->framereg].addr,
1088 register_size (current_gdbarch, cache->framereg));
1094 arm_sigtramp_this_id (struct frame_info *next_frame,
1096 struct frame_id *this_id)
1098 struct arm_prologue_cache *cache;
1100 if (*this_cache == NULL)
1101 *this_cache = arm_make_sigtramp_cache (next_frame);
1102 cache = *this_cache;
1104 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1105 the sigtramp frame; the PC should be the beginning of the trampoline. */
1106 *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame));
1110 arm_sigtramp_prev_register (struct frame_info *next_frame,
1114 enum lval_type *lvalp,
1119 struct arm_prologue_cache *cache;
1121 if (*this_cache == NULL)
1122 *this_cache = arm_make_sigtramp_cache (next_frame);
1123 cache = *this_cache;
1125 trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
1126 optimized, lvalp, addrp, realnump, valuep);
1129 struct frame_unwind arm_sigtramp_unwind = {
1131 arm_sigtramp_this_id,
1132 arm_sigtramp_prev_register
1135 static const struct frame_unwind *
1136 arm_sigtramp_unwind_sniffer (struct frame_info *next_frame)
1138 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1139 && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0))
1140 return &arm_sigtramp_unwind;
1145 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1146 dummy frame. The frame ID's base needs to match the TOS value
1147 saved by save_dummy_frame_tos() and returned from
1148 arm_push_dummy_call, and the PC needs to match the dummy frame's
1151 static struct frame_id
1152 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1154 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1155 frame_pc_unwind (next_frame));
1158 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1159 be used to construct the previous frame's ID, after looking up the
1160 containing function). */
1163 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1166 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1167 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1171 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1173 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1176 /* DEPRECATED_CALL_DUMMY_WORDS:
1177 This sequence of words is the instructions
1183 Note this is 12 bytes. */
1185 static LONGEST arm_call_dummy_words[] =
1187 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1190 /* When arguments must be pushed onto the stack, they go on in reverse
1191 order. The code below implements a FILO (stack) to do this. */
1196 struct stack_item *prev;
1200 static struct stack_item *
1201 push_stack_item (struct stack_item *prev, void *contents, int len)
1203 struct stack_item *si;
1204 si = xmalloc (sizeof (struct stack_item));
1205 si->data = xmalloc (len);
1208 memcpy (si->data, contents, len);
1212 static struct stack_item *
1213 pop_stack_item (struct stack_item *si)
1215 struct stack_item *dead = si;
1222 /* We currently only support passing parameters in integer registers. This
1223 conforms with GCC's default model. Several other variants exist and
1224 we should probably support some of them based on the selected ABI. */
1227 arm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1228 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1229 struct value **args, CORE_ADDR sp, int struct_return,
1230 CORE_ADDR struct_addr)
1235 struct stack_item *si = NULL;
1237 /* Set the return address. For the ARM, the return breakpoint is
1238 always at BP_ADDR. */
1239 /* XXX Fix for Thumb. */
1240 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1242 /* Walk through the list of args and determine how large a temporary
1243 stack is required. Need to take care here as structs may be
1244 passed on the stack, and we have to to push them. */
1247 argreg = ARM_A1_REGNUM;
1250 /* Some platforms require a double-word aligned stack. Make sure sp
1251 is correctly aligned before we start. We always do this even if
1252 it isn't really needed -- it can never hurt things. */
1253 sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1);
1255 /* The struct_return pointer occupies the first parameter
1256 passing register. */
1260 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1261 REGISTER_NAME (argreg), paddr (struct_addr));
1262 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1266 for (argnum = 0; argnum < nargs; argnum++)
1269 struct type *arg_type;
1270 struct type *target_type;
1271 enum type_code typecode;
1274 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1275 len = TYPE_LENGTH (arg_type);
1276 target_type = TYPE_TARGET_TYPE (arg_type);
1277 typecode = TYPE_CODE (arg_type);
1278 val = VALUE_CONTENTS (args[argnum]);
1280 /* If the argument is a pointer to a function, and it is a
1281 Thumb function, create a LOCAL copy of the value and set
1282 the THUMB bit in it. */
1283 if (TYPE_CODE_PTR == typecode
1284 && target_type != NULL
1285 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1287 CORE_ADDR regval = extract_unsigned_integer (val, len);
1288 if (arm_pc_is_thumb (regval))
1291 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1295 /* Copy the argument to general registers or the stack in
1296 register-sized pieces. Large arguments are split between
1297 registers and stack. */
1300 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1302 if (argreg <= ARM_LAST_ARG_REGNUM)
1304 /* The argument is being passed in a general purpose
1306 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1308 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1309 argnum, REGISTER_NAME (argreg),
1310 phex (regval, DEPRECATED_REGISTER_SIZE));
1311 regcache_cooked_write_unsigned (regcache, argreg, regval);
1316 /* Push the arguments onto the stack. */
1318 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1320 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1321 nstack += DEPRECATED_REGISTER_SIZE;
1328 /* If we have an odd number of words to push, then decrement the stack
1329 by one word now, so first stack argument will be dword aligned. */
1336 write_memory (sp, si->data, si->len);
1337 si = pop_stack_item (si);
1340 /* Finally, update teh SP register. */
1341 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1347 print_fpu_flags (int flags)
1349 if (flags & (1 << 0))
1350 fputs ("IVO ", stdout);
1351 if (flags & (1 << 1))
1352 fputs ("DVZ ", stdout);
1353 if (flags & (1 << 2))
1354 fputs ("OFL ", stdout);
1355 if (flags & (1 << 3))
1356 fputs ("UFL ", stdout);
1357 if (flags & (1 << 4))
1358 fputs ("INX ", stdout);
1362 /* Print interesting information about the floating point processor
1363 (if present) or emulator. */
1365 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1366 struct frame_info *frame, const char *args)
1368 unsigned long status = read_register (ARM_FPS_REGNUM);
1371 type = (status >> 24) & 127;
1372 printf ("%s FPU type %d\n",
1373 (status & (1 << 31)) ? "Hardware" : "Software",
1375 fputs ("mask: ", stdout);
1376 print_fpu_flags (status >> 16);
1377 fputs ("flags: ", stdout);
1378 print_fpu_flags (status);
1381 /* Return the GDB type object for the "standard" data type of data in
1384 static struct type *
1385 arm_register_type (struct gdbarch *gdbarch, int regnum)
1387 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1389 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1390 return builtin_type_arm_ext_big;
1392 return builtin_type_arm_ext_littlebyte_bigword;
1395 return builtin_type_int32;
1398 /* Index within `registers' of the first byte of the space for
1402 arm_register_byte (int regnum)
1404 if (regnum < ARM_F0_REGNUM)
1405 return regnum * INT_REGISTER_SIZE;
1406 else if (regnum < ARM_PS_REGNUM)
1407 return (NUM_GREGS * INT_REGISTER_SIZE
1408 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1410 return (NUM_GREGS * INT_REGISTER_SIZE
1411 + NUM_FREGS * FP_REGISTER_SIZE
1412 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1415 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1417 arm_register_sim_regno (int regnum)
1420 gdb_assert (reg >= 0 && reg < NUM_REGS);
1422 if (reg < NUM_GREGS)
1423 return SIM_ARM_R0_REGNUM + reg;
1426 if (reg < NUM_FREGS)
1427 return SIM_ARM_FP0_REGNUM + reg;
1430 if (reg < NUM_SREGS)
1431 return SIM_ARM_FPS_REGNUM + reg;
1434 internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
1437 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1438 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1439 It is thought that this is is the floating-point register format on
1440 little-endian systems. */
1443 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1447 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1448 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1450 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1452 floatformat_from_doublest (fmt, &d, dbl);
1456 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1459 floatformat_to_doublest (fmt, ptr, &d);
1460 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1461 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1463 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1468 condition_true (unsigned long cond, unsigned long status_reg)
1470 if (cond == INST_AL || cond == INST_NV)
1476 return ((status_reg & FLAG_Z) != 0);
1478 return ((status_reg & FLAG_Z) == 0);
1480 return ((status_reg & FLAG_C) != 0);
1482 return ((status_reg & FLAG_C) == 0);
1484 return ((status_reg & FLAG_N) != 0);
1486 return ((status_reg & FLAG_N) == 0);
1488 return ((status_reg & FLAG_V) != 0);
1490 return ((status_reg & FLAG_V) == 0);
1492 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1494 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1496 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1498 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1500 return (((status_reg & FLAG_Z) == 0) &&
1501 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1503 return (((status_reg & FLAG_Z) != 0) ||
1504 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1509 /* Support routines for single stepping. Calculate the next PC value. */
1510 #define submask(x) ((1L << ((x) + 1)) - 1)
1511 #define bit(obj,st) (((obj) >> (st)) & 1)
1512 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1513 #define sbits(obj,st,fn) \
1514 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1515 #define BranchDest(addr,instr) \
1516 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1519 static unsigned long
1520 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1521 unsigned long status_reg)
1523 unsigned long res, shift;
1524 int rm = bits (inst, 0, 3);
1525 unsigned long shifttype = bits (inst, 5, 6);
1529 int rs = bits (inst, 8, 11);
1530 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1533 shift = bits (inst, 7, 11);
1536 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1537 + (bit (inst, 4) ? 12 : 8))
1538 : read_register (rm));
1543 res = shift >= 32 ? 0 : res << shift;
1547 res = shift >= 32 ? 0 : res >> shift;
1553 res = ((res & 0x80000000L)
1554 ? ~((~res) >> shift) : res >> shift);
1557 case 3: /* ROR/RRX */
1560 res = (res >> 1) | (carry ? 0x80000000L : 0);
1562 res = (res >> shift) | (res << (32 - shift));
1566 return res & 0xffffffff;
1569 /* Return number of 1-bits in VAL. */
1572 bitcount (unsigned long val)
1575 for (nbits = 0; val != 0; nbits++)
1576 val &= val - 1; /* delete rightmost 1-bit in val */
1581 thumb_get_next_pc (CORE_ADDR pc)
1583 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1584 unsigned short inst1 = read_memory_integer (pc, 2);
1585 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1586 unsigned long offset;
1588 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1592 /* Fetch the saved PC from the stack. It's stored above
1593 all of the other registers. */
1594 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1595 sp = read_register (ARM_SP_REGNUM);
1596 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1597 nextpc = ADDR_BITS_REMOVE (nextpc);
1599 error ("Infinite loop detected");
1601 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1603 unsigned long status = read_register (ARM_PS_REGNUM);
1604 unsigned long cond = bits (inst1, 8, 11);
1605 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1606 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1608 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1610 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1612 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1614 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1615 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1616 nextpc = pc_val + offset;
1617 /* For BLX make sure to clear the low bits. */
1618 if (bits (inst2, 11, 12) == 1)
1619 nextpc = nextpc & 0xfffffffc;
1621 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1623 if (bits (inst1, 3, 6) == 0x0f)
1626 nextpc = read_register (bits (inst1, 3, 6));
1628 nextpc = ADDR_BITS_REMOVE (nextpc);
1630 error ("Infinite loop detected");
1637 arm_get_next_pc (CORE_ADDR pc)
1639 unsigned long pc_val;
1640 unsigned long this_instr;
1641 unsigned long status;
1644 if (arm_pc_is_thumb (pc))
1645 return thumb_get_next_pc (pc);
1647 pc_val = (unsigned long) pc;
1648 this_instr = read_memory_integer (pc, 4);
1649 status = read_register (ARM_PS_REGNUM);
1650 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1652 if (condition_true (bits (this_instr, 28, 31), status))
1654 switch (bits (this_instr, 24, 27))
1657 case 0x1: /* data processing */
1661 unsigned long operand1, operand2, result = 0;
1665 if (bits (this_instr, 12, 15) != 15)
1668 if (bits (this_instr, 22, 25) == 0
1669 && bits (this_instr, 4, 7) == 9) /* multiply */
1670 error ("Illegal update to pc in instruction");
1672 /* BX <reg>, BLX <reg> */
1673 if (bits (this_instr, 4, 28) == 0x12fff1
1674 || bits (this_instr, 4, 28) == 0x12fff3)
1676 rn = bits (this_instr, 0, 3);
1677 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1678 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1681 error ("Infinite loop detected");
1686 /* Multiply into PC */
1687 c = (status & FLAG_C) ? 1 : 0;
1688 rn = bits (this_instr, 16, 19);
1689 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1691 if (bit (this_instr, 25))
1693 unsigned long immval = bits (this_instr, 0, 7);
1694 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1695 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1698 else /* operand 2 is a shifted register */
1699 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1701 switch (bits (this_instr, 21, 24))
1704 result = operand1 & operand2;
1708 result = operand1 ^ operand2;
1712 result = operand1 - operand2;
1716 result = operand2 - operand1;
1720 result = operand1 + operand2;
1724 result = operand1 + operand2 + c;
1728 result = operand1 - operand2 + c;
1732 result = operand2 - operand1 + c;
1738 case 0xb: /* tst, teq, cmp, cmn */
1739 result = (unsigned long) nextpc;
1743 result = operand1 | operand2;
1747 /* Always step into a function. */
1752 result = operand1 & ~operand2;
1759 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1762 error ("Infinite loop detected");
1767 case 0x5: /* data transfer */
1770 if (bit (this_instr, 20))
1773 if (bits (this_instr, 12, 15) == 15)
1779 if (bit (this_instr, 22))
1780 error ("Illegal update to pc in instruction");
1782 /* byte write to PC */
1783 rn = bits (this_instr, 16, 19);
1784 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1785 if (bit (this_instr, 24))
1788 int c = (status & FLAG_C) ? 1 : 0;
1789 unsigned long offset =
1790 (bit (this_instr, 25)
1791 ? shifted_reg_val (this_instr, c, pc_val, status)
1792 : bits (this_instr, 0, 11));
1794 if (bit (this_instr, 23))
1799 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1802 nextpc = ADDR_BITS_REMOVE (nextpc);
1805 error ("Infinite loop detected");
1811 case 0x9: /* block transfer */
1812 if (bit (this_instr, 20))
1815 if (bit (this_instr, 15))
1820 if (bit (this_instr, 23))
1823 unsigned long reglist = bits (this_instr, 0, 14);
1824 offset = bitcount (reglist) * 4;
1825 if (bit (this_instr, 24)) /* pre */
1828 else if (bit (this_instr, 24))
1832 unsigned long rn_val =
1833 read_register (bits (this_instr, 16, 19));
1835 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1839 nextpc = ADDR_BITS_REMOVE (nextpc);
1841 error ("Infinite loop detected");
1846 case 0xb: /* branch & link */
1847 case 0xa: /* branch */
1849 nextpc = BranchDest (pc, this_instr);
1852 if (bits (this_instr, 28, 31) == INST_NV)
1853 nextpc |= bit (this_instr, 24) << 1;
1855 nextpc = ADDR_BITS_REMOVE (nextpc);
1857 error ("Infinite loop detected");
1863 case 0xe: /* coproc ops */
1868 fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
1876 /* single_step() is called just before we want to resume the inferior,
1877 if we want to single-step it but there is no hardware or kernel
1878 single-step support. We find the target of the coming instruction
1881 single_step() is also called just after the inferior stops. If we
1882 had set up a simulated single-step, we undo our damage. */
1885 arm_software_single_step (enum target_signal sig, int insert_bpt)
1887 static int next_pc; /* State between setting and unsetting. */
1888 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
1892 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1893 target_insert_breakpoint (next_pc, break_mem);
1896 target_remove_breakpoint (next_pc, break_mem);
1899 #include "bfd-in2.h"
1900 #include "libcoff.h"
1903 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1905 if (arm_pc_is_thumb (memaddr))
1907 static asymbol *asym;
1908 static combined_entry_type ce;
1909 static struct coff_symbol_struct csym;
1910 static struct bfd fake_bfd;
1911 static bfd_target fake_target;
1913 if (csym.native == NULL)
1915 /* Create a fake symbol vector containing a Thumb symbol.
1916 This is solely so that the code in print_insn_little_arm()
1917 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1918 the presence of a Thumb symbol and switch to decoding
1919 Thumb instructions. */
1921 fake_target.flavour = bfd_target_coff_flavour;
1922 fake_bfd.xvec = &fake_target;
1923 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1925 csym.symbol.the_bfd = &fake_bfd;
1926 csym.symbol.name = "fake";
1927 asym = (asymbol *) & csym;
1930 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1931 info->symbols = &asym;
1934 info->symbols = NULL;
1936 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1937 return print_insn_big_arm (memaddr, info);
1939 return print_insn_little_arm (memaddr, info);
1942 /* The following define instruction sequences that will cause ARM
1943 cpu's to take an undefined instruction trap. These are used to
1944 signal a breakpoint to GDB.
1946 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1947 modes. A different instruction is required for each mode. The ARM
1948 cpu's can also be big or little endian. Thus four different
1949 instructions are needed to support all cases.
1951 Note: ARMv4 defines several new instructions that will take the
1952 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1953 not in fact add the new instructions. The new undefined
1954 instructions in ARMv4 are all instructions that had no defined
1955 behaviour in earlier chips. There is no guarantee that they will
1956 raise an exception, but may be treated as NOP's. In practice, it
1957 may only safe to rely on instructions matching:
1959 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1960 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1961 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1963 Even this may only true if the condition predicate is true. The
1964 following use a condition predicate of ALWAYS so it is always TRUE.
1966 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1967 and NetBSD all use a software interrupt rather than an undefined
1968 instruction to force a trap. This can be handled by by the
1969 abi-specific code during establishment of the gdbarch vector. */
1972 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1973 override these definitions. */
1974 #ifndef ARM_LE_BREAKPOINT
1975 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1977 #ifndef ARM_BE_BREAKPOINT
1978 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1980 #ifndef THUMB_LE_BREAKPOINT
1981 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1983 #ifndef THUMB_BE_BREAKPOINT
1984 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1987 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1988 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1989 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1990 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1992 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1993 the program counter value to determine whether a 16-bit or 32-bit
1994 breakpoint should be used. It returns a pointer to a string of
1995 bytes that encode a breakpoint instruction, stores the length of
1996 the string to *lenptr, and adjusts the program counter (if
1997 necessary) to point to the actual memory location where the
1998 breakpoint should be inserted. */
2000 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2001 breakpoints and storing their handles instread of what was in
2002 memory. It is nice that this is the same size as a handle -
2003 otherwise remote-rdp will have to change. */
2005 static const unsigned char *
2006 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2008 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2010 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
2012 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2013 *lenptr = tdep->thumb_breakpoint_size;
2014 return tdep->thumb_breakpoint;
2018 *lenptr = tdep->arm_breakpoint_size;
2019 return tdep->arm_breakpoint;
2023 /* Extract from an array REGBUF containing the (raw) register state a
2024 function return value of type TYPE, and copy that, in virtual
2025 format, into VALBUF. */
2028 arm_extract_return_value (struct type *type,
2029 struct regcache *regs,
2032 bfd_byte *valbuf = dst;
2034 if (TYPE_CODE_FLT == TYPE_CODE (type))
2036 switch (arm_get_fp_model (current_gdbarch))
2040 /* The value is in register F0 in internal format. We need to
2041 extract the raw value and then convert it to the desired
2043 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2045 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2046 convert_from_extended (floatformat_from_type (type), tmpbuf,
2051 case ARM_FLOAT_SOFT_FPA:
2052 case ARM_FLOAT_SOFT_VFP:
2053 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2054 if (TYPE_LENGTH (type) > 4)
2055 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2056 valbuf + INT_REGISTER_SIZE);
2061 (__FILE__, __LINE__,
2062 "arm_extract_return_value: Floating point model not supported");
2066 else if (TYPE_CODE (type) == TYPE_CODE_INT
2067 || TYPE_CODE (type) == TYPE_CODE_CHAR
2068 || TYPE_CODE (type) == TYPE_CODE_BOOL
2069 || TYPE_CODE (type) == TYPE_CODE_PTR
2070 || TYPE_CODE (type) == TYPE_CODE_REF
2071 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2073 /* If the the type is a plain integer, then the access is
2074 straight-forward. Otherwise we have to play around a bit more. */
2075 int len = TYPE_LENGTH (type);
2076 int regno = ARM_A1_REGNUM;
2081 /* By using store_unsigned_integer we avoid having to do
2082 anything special for small big-endian values. */
2083 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2084 store_unsigned_integer (valbuf,
2085 (len > INT_REGISTER_SIZE
2086 ? INT_REGISTER_SIZE : len),
2088 len -= INT_REGISTER_SIZE;
2089 valbuf += INT_REGISTER_SIZE;
2094 /* For a structure or union the behaviour is as if the value had
2095 been stored to word-aligned memory and then loaded into
2096 registers with 32-bit load instruction(s). */
2097 int len = TYPE_LENGTH (type);
2098 int regno = ARM_A1_REGNUM;
2099 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2103 regcache_cooked_read (regs, regno++, tmpbuf);
2104 memcpy (valbuf, tmpbuf,
2105 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2106 len -= INT_REGISTER_SIZE;
2107 valbuf += INT_REGISTER_SIZE;
2112 /* Extract from an array REGBUF containing the (raw) register state
2113 the address in which a function should return its structure value. */
2116 arm_extract_struct_value_address (struct regcache *regcache)
2120 regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
2124 /* Will a function return an aggregate type in memory or in a
2125 register? Return 0 if an aggregate type can be returned in a
2126 register, 1 if it must be returned in memory. */
2129 arm_use_struct_convention (int gcc_p, struct type *type)
2132 enum type_code code;
2134 CHECK_TYPEDEF (type);
2136 /* In the ARM ABI, "integer" like aggregate types are returned in
2137 registers. For an aggregate type to be integer like, its size
2138 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2139 offset of each addressable subfield must be zero. Note that bit
2140 fields are not addressable, and all addressable subfields of
2141 unions always start at offset zero.
2143 This function is based on the behaviour of GCC 2.95.1.
2144 See: gcc/arm.c: arm_return_in_memory() for details.
2146 Note: All versions of GCC before GCC 2.95.2 do not set up the
2147 parameters correctly for a function returning the following
2148 structure: struct { float f;}; This should be returned in memory,
2149 not a register. Richard Earnshaw sent me a patch, but I do not
2150 know of any way to detect if a function like the above has been
2151 compiled with the correct calling convention. */
2153 /* All aggregate types that won't fit in a register must be returned
2155 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2160 /* The only aggregate types that can be returned in a register are
2161 structs and unions. Arrays must be returned in memory. */
2162 code = TYPE_CODE (type);
2163 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2168 /* Assume all other aggregate types can be returned in a register.
2169 Run a check for structures, unions and arrays. */
2172 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2175 /* Need to check if this struct/union is "integer" like. For
2176 this to be true, its size must be less than or equal to
2177 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2178 subfield must be zero. Note that bit fields are not
2179 addressable, and unions always start at offset zero. If any
2180 of the subfields is a floating point type, the struct/union
2181 cannot be an integer type. */
2183 /* For each field in the object, check:
2184 1) Is it FP? --> yes, nRc = 1;
2185 2) Is it addressable (bitpos != 0) and
2186 not packed (bitsize == 0)?
2190 for (i = 0; i < TYPE_NFIELDS (type); i++)
2192 enum type_code field_type_code;
2193 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2195 /* Is it a floating point type field? */
2196 if (field_type_code == TYPE_CODE_FLT)
2202 /* If bitpos != 0, then we have to care about it. */
2203 if (TYPE_FIELD_BITPOS (type, i) != 0)
2205 /* Bitfields are not addressable. If the field bitsize is
2206 zero, then the field is not packed. Hence it cannot be
2207 a bitfield or any other packed type. */
2208 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2220 /* Write into appropriate registers a function return value of type
2221 TYPE, given in virtual format. */
2224 arm_store_return_value (struct type *type, struct regcache *regs,
2227 const bfd_byte *valbuf = src;
2229 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2231 char buf[MAX_REGISTER_SIZE];
2233 switch (arm_get_fp_model (current_gdbarch))
2237 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2238 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2241 case ARM_FLOAT_SOFT_FPA:
2242 case ARM_FLOAT_SOFT_VFP:
2243 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2244 if (TYPE_LENGTH (type) > 4)
2245 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2246 valbuf + INT_REGISTER_SIZE);
2251 (__FILE__, __LINE__,
2252 "arm_store_return_value: Floating point model not supported");
2256 else if (TYPE_CODE (type) == TYPE_CODE_INT
2257 || TYPE_CODE (type) == TYPE_CODE_CHAR
2258 || TYPE_CODE (type) == TYPE_CODE_BOOL
2259 || TYPE_CODE (type) == TYPE_CODE_PTR
2260 || TYPE_CODE (type) == TYPE_CODE_REF
2261 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2263 if (TYPE_LENGTH (type) <= 4)
2265 /* Values of one word or less are zero/sign-extended and
2267 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2268 LONGEST val = unpack_long (type, valbuf);
2270 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2271 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2275 /* Integral values greater than one word are stored in consecutive
2276 registers starting with r0. This will always be a multiple of
2277 the regiser size. */
2278 int len = TYPE_LENGTH (type);
2279 int regno = ARM_A1_REGNUM;
2283 regcache_cooked_write (regs, regno++, valbuf);
2284 len -= INT_REGISTER_SIZE;
2285 valbuf += INT_REGISTER_SIZE;
2291 /* For a structure or union the behaviour is as if the value had
2292 been stored to word-aligned memory and then loaded into
2293 registers with 32-bit load instruction(s). */
2294 int len = TYPE_LENGTH (type);
2295 int regno = ARM_A1_REGNUM;
2296 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2300 memcpy (tmpbuf, valbuf,
2301 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2302 regcache_cooked_write (regs, regno++, tmpbuf);
2303 len -= INT_REGISTER_SIZE;
2304 valbuf += INT_REGISTER_SIZE;
2310 arm_get_longjmp_target (CORE_ADDR *pc)
2313 char buf[INT_REGISTER_SIZE];
2314 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2316 jb_addr = read_register (ARM_A1_REGNUM);
2318 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2322 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2326 /* Return non-zero if the PC is inside a thumb call thunk. */
2329 arm_in_call_stub (CORE_ADDR pc, char *name)
2331 CORE_ADDR start_addr;
2333 /* Find the starting address of the function containing the PC. If
2334 the caller didn't give us a name, look it up at the same time. */
2335 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2339 return strncmp (name, "_call_via_r", 11) == 0;
2342 /* If PC is in a Thumb call or return stub, return the address of the
2343 target PC, which is in a register. The thunk functions are called
2344 _called_via_xx, where x is the register name. The possible names
2345 are r0-r9, sl, fp, ip, sp, and lr. */
2348 arm_skip_stub (CORE_ADDR pc)
2351 CORE_ADDR start_addr;
2353 /* Find the starting address and name of the function containing the PC. */
2354 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2357 /* Call thunks always start with "_call_via_". */
2358 if (strncmp (name, "_call_via_", 10) == 0)
2360 /* Use the name suffix to determine which register contains the
2362 static char *table[15] =
2363 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2364 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2368 for (regno = 0; regno <= 14; regno++)
2369 if (strcmp (&name[10], table[regno]) == 0)
2370 return read_register (regno);
2373 return 0; /* not a stub */
2377 set_arm_command (char *args, int from_tty)
2379 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2380 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2384 show_arm_command (char *args, int from_tty)
2386 cmd_show_list (showarmcmdlist, from_tty, "");
2389 enum arm_float_model
2390 arm_get_fp_model (struct gdbarch *gdbarch)
2392 if (arm_fp_model == ARM_FLOAT_AUTO)
2393 return gdbarch_tdep (gdbarch)->fp_model;
2395 return arm_fp_model;
2399 arm_set_fp (struct gdbarch *gdbarch)
2401 enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
2403 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2404 && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
2406 set_gdbarch_double_format (gdbarch,
2407 &floatformat_ieee_double_littlebyte_bigword);
2408 set_gdbarch_long_double_format
2409 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2413 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2414 set_gdbarch_long_double_format (gdbarch,
2415 &floatformat_ieee_double_little);
2420 set_fp_model_sfunc (char *args, int from_tty,
2421 struct cmd_list_element *c)
2423 enum arm_float_model fp_model;
2425 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2426 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2428 arm_fp_model = fp_model;
2432 if (fp_model == ARM_FLOAT_LAST)
2433 internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.",
2436 if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2437 arm_set_fp (current_gdbarch);
2441 show_fp_model (char *args, int from_tty,
2442 struct cmd_list_element *c)
2444 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2446 if (arm_fp_model == ARM_FLOAT_AUTO
2447 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2448 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2449 fp_model_strings[tdep->fp_model]);
2452 /* If the user changes the register disassembly style used for info
2453 register and other commands, we have to also switch the style used
2454 in opcodes for disassembly output. This function is run in the "set
2455 arm disassembly" command, and does that. */
2458 set_disassembly_style_sfunc (char *args, int from_tty,
2459 struct cmd_list_element *c)
2461 set_disassembly_style ();
2464 /* Return the ARM register name corresponding to register I. */
2466 arm_register_name (int i)
2468 return arm_register_names[i];
2472 set_disassembly_style (void)
2474 const char *setname, *setdesc, **regnames;
2477 /* Find the style that the user wants in the opcodes table. */
2479 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2480 while ((disassembly_style != setname)
2481 && (current < num_disassembly_options))
2482 get_arm_regnames (++current, &setname, &setdesc, ®names);
2483 current_option = current;
2485 /* Fill our copy. */
2486 for (j = 0; j < numregs; j++)
2487 arm_register_names[j] = (char *) regnames[j];
2490 if (isupper (*regnames[ARM_PC_REGNUM]))
2492 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2493 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2497 arm_register_names[ARM_FPS_REGNUM] = "fps";
2498 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2501 /* Synchronize the disassembler. */
2502 set_arm_regname_option (current);
2505 /* arm_othernames implements the "othernames" command. This is deprecated
2506 by the "set arm disassembly" command. */
2509 arm_othernames (char *names, int n)
2511 /* Circle through the various flavors. */
2512 current_option = (current_option + 1) % num_disassembly_options;
2514 disassembly_style = valid_disassembly_styles[current_option];
2515 set_disassembly_style ();
2518 /* Test whether the coff symbol specific value corresponds to a Thumb
2522 coff_sym_is_thumb (int val)
2524 return (val == C_THUMBEXT ||
2525 val == C_THUMBSTAT ||
2526 val == C_THUMBEXTFUNC ||
2527 val == C_THUMBSTATFUNC ||
2528 val == C_THUMBLABEL);
2531 /* arm_coff_make_msymbol_special()
2532 arm_elf_make_msymbol_special()
2534 These functions test whether the COFF or ELF symbol corresponds to
2535 an address in thumb code, and set a "special" bit in a minimal
2536 symbol to indicate that it does. */
2539 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2541 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2543 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2545 MSYMBOL_SET_SPECIAL (msym);
2549 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2551 if (coff_sym_is_thumb (val))
2552 MSYMBOL_SET_SPECIAL (msym);
2556 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2558 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2560 /* If necessary, set the T bit. */
2563 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2564 if (arm_pc_is_thumb (pc))
2565 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2567 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2571 static enum gdb_osabi
2572 arm_elf_osabi_sniffer (bfd *abfd)
2574 unsigned int elfosabi, eflags;
2575 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2577 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2582 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2583 file are conforming to the base specification for that machine
2584 (there are no OS-specific extensions). In order to determine the
2585 real OS in use we must look for OS notes that have been added. */
2586 bfd_map_over_sections (abfd,
2587 generic_elf_osabi_sniff_abi_tag_sections,
2589 if (osabi == GDB_OSABI_UNKNOWN)
2591 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2592 field for more information. */
2593 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2596 case EF_ARM_EABI_VER1:
2597 osabi = GDB_OSABI_ARM_EABI_V1;
2600 case EF_ARM_EABI_VER2:
2601 osabi = GDB_OSABI_ARM_EABI_V2;
2604 case EF_ARM_EABI_UNKNOWN:
2605 /* Assume GNU tools. */
2606 osabi = GDB_OSABI_ARM_APCS;
2610 internal_error (__FILE__, __LINE__,
2611 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2612 "version 0x%x", eflags);
2618 /* GNU tools use this value. Check note sections in this case,
2620 bfd_map_over_sections (abfd,
2621 generic_elf_osabi_sniff_abi_tag_sections,
2623 if (osabi == GDB_OSABI_UNKNOWN)
2625 /* Assume APCS ABI. */
2626 osabi = GDB_OSABI_ARM_APCS;
2630 case ELFOSABI_FREEBSD:
2631 osabi = GDB_OSABI_FREEBSD_ELF;
2634 case ELFOSABI_NETBSD:
2635 osabi = GDB_OSABI_NETBSD_ELF;
2638 case ELFOSABI_LINUX:
2639 osabi = GDB_OSABI_LINUX;
2647 /* Initialize the current architecture based on INFO. If possible,
2648 re-use an architecture from ARCHES, which is a list of
2649 architectures already created during this debugging session.
2651 Called e.g. at program startup, when reading a core file, and when
2652 reading a binary file. */
2654 static struct gdbarch *
2655 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2657 struct gdbarch_tdep *tdep;
2658 struct gdbarch *gdbarch;
2660 /* Try to deterimine the ABI of the object we are loading. */
2662 if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
2664 switch (bfd_get_flavour (info.abfd))
2666 case bfd_target_aout_flavour:
2667 /* Assume it's an old APCS-style ABI. */
2668 info.osabi = GDB_OSABI_ARM_APCS;
2671 case bfd_target_coff_flavour:
2672 /* Assume it's an old APCS-style ABI. */
2674 info.osabi = GDB_OSABI_ARM_APCS;
2678 /* Leave it as "unknown". */
2683 /* If there is already a candidate, use it. */
2684 arches = gdbarch_list_lookup_by_info (arches, &info);
2686 return arches->gdbarch;
2688 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2689 gdbarch = gdbarch_alloc (&info, tdep);
2691 /* We used to default to FPA for generic ARM, but almost nobody uses that
2692 now, and we now provide a way for the user to force the model. So
2693 default to the most useful variant. */
2694 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
2697 switch (info.byte_order)
2699 case BFD_ENDIAN_BIG:
2700 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2701 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2702 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2703 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2707 case BFD_ENDIAN_LITTLE:
2708 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2709 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2710 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2711 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2716 internal_error (__FILE__, __LINE__,
2717 "arm_gdbarch_init: bad byte order for float format");
2720 /* On ARM targets char defaults to unsigned. */
2721 set_gdbarch_char_signed (gdbarch, 0);
2723 /* This should be low enough for everything. */
2724 tdep->lowest_pc = 0x20;
2725 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2727 set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words);
2728 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0);
2730 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2732 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2734 /* Frame handling. */
2735 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2736 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2737 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2739 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, arm_frameless_function_invocation);
2741 frame_base_set_default (gdbarch, &arm_normal_base);
2743 /* Address manipulation. */
2744 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2745 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2747 /* Advance PC across function entry code. */
2748 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2750 /* Get the PC when a frame might not be available. */
2751 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2753 /* The stack grows downward. */
2754 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2756 /* Breakpoint manipulation. */
2757 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2759 /* Information about registers, etc. */
2760 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2761 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2762 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2763 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2764 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2765 set_gdbarch_deprecated_register_bytes (gdbarch,
2766 (NUM_GREGS * INT_REGISTER_SIZE
2767 + NUM_FREGS * FP_REGISTER_SIZE
2768 + NUM_SREGS * STATUS_REGISTER_SIZE));
2769 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2770 set_gdbarch_register_type (gdbarch, arm_register_type);
2772 /* Internal <-> external register number maps. */
2773 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2775 /* Integer registers are 4 bytes. */
2776 set_gdbarch_deprecated_register_size (gdbarch, 4);
2777 set_gdbarch_register_name (gdbarch, arm_register_name);
2779 /* Returning results. */
2780 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2781 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
2782 set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
2783 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address);
2785 /* Single stepping. */
2786 /* XXX For an RDI target we should ask the target if it can single-step. */
2787 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2790 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2792 /* Minsymbol frobbing. */
2793 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2794 set_gdbarch_coff_make_msymbol_special (gdbarch,
2795 arm_coff_make_msymbol_special);
2797 /* Hook in the ABI-specific overrides, if they have been registered. */
2798 gdbarch_init_osabi (info, gdbarch);
2800 /* Add some default predicates. */
2801 frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer);
2802 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2804 /* Now we have tuned the configuration, set a few final things,
2805 based on what the OS ABI has told us. */
2807 if (tdep->jb_pc >= 0)
2808 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2810 /* Floating point sizes and format. */
2811 switch (info.byte_order)
2813 case BFD_ENDIAN_BIG:
2814 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2815 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2816 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2820 case BFD_ENDIAN_LITTLE:
2821 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2822 arm_set_fp (gdbarch);
2826 internal_error (__FILE__, __LINE__,
2827 "arm_gdbarch_init: bad byte order for float format");
2834 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2836 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2841 fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
2842 (unsigned long) tdep->lowest_pc);
2846 arm_init_abi_eabi_v1 (struct gdbarch_info info,
2847 struct gdbarch *gdbarch)
2853 arm_init_abi_eabi_v2 (struct gdbarch_info info,
2854 struct gdbarch *gdbarch)
2860 arm_init_abi_apcs (struct gdbarch_info info,
2861 struct gdbarch *gdbarch)
2866 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2869 _initialize_arm_tdep (void)
2871 struct ui_file *stb;
2873 struct cmd_list_element *new_set, *new_show;
2874 const char *setname;
2875 const char *setdesc;
2876 const char **regnames;
2878 static char *helptext;
2880 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2882 /* Register an ELF OS ABI sniffer for ARM binaries. */
2883 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2884 bfd_target_elf_flavour,
2885 arm_elf_osabi_sniffer);
2887 /* Register some ABI variants for embedded systems. */
2888 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
2889 arm_init_abi_eabi_v1);
2890 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
2891 arm_init_abi_eabi_v2);
2892 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
2895 /* Get the number of possible sets of register names defined in opcodes. */
2896 num_disassembly_options = get_arm_regname_num_options ();
2898 /* Add root prefix command for all "set arm"/"show arm" commands. */
2899 add_prefix_cmd ("arm", no_class, set_arm_command,
2900 "Various ARM-specific commands.",
2901 &setarmcmdlist, "set arm ", 0, &setlist);
2903 add_prefix_cmd ("arm", no_class, show_arm_command,
2904 "Various ARM-specific commands.",
2905 &showarmcmdlist, "show arm ", 0, &showlist);
2907 /* Sync the opcode insn printer with our register viewer. */
2908 parse_arm_disassembler_option ("reg-names-std");
2910 /* Begin creating the help text. */
2911 stb = mem_fileopen ();
2912 fprintf_unfiltered (stb, "Set the disassembly style.\n"
2913 "The valid values are:\n");
2915 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2916 valid_disassembly_styles
2917 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2918 for (i = 0; i < num_disassembly_options; i++)
2920 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2921 valid_disassembly_styles[i] = setname;
2922 fprintf_unfiltered (stb, "%s - %s\n", setname,
2924 /* Copy the default names (if found) and synchronize disassembler. */
2925 if (!strcmp (setname, "std"))
2927 disassembly_style = setname;
2929 for (j = 0; j < numregs; j++)
2930 arm_register_names[j] = (char *) regnames[j];
2931 set_arm_regname_option (i);
2934 /* Mark the end of valid options. */
2935 valid_disassembly_styles[num_disassembly_options] = NULL;
2937 /* Finish the creation of the help text. */
2938 fprintf_unfiltered (stb, "The default is \"std\".");
2939 helptext = ui_file_xstrdup (stb, &length);
2940 ui_file_delete (stb);
2942 /* Add the deprecated disassembly-flavor command. */
2943 new_set = add_set_enum_cmd ("disassembly-flavor", no_class,
2944 valid_disassembly_styles,
2948 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
2949 deprecate_cmd (new_set, "set arm disassembly");
2950 deprecate_cmd (add_show_from_set (new_set, &showlist),
2951 "show arm disassembly");
2953 /* And now add the new interface. */
2954 new_set = add_set_enum_cmd ("disassembler", no_class,
2955 valid_disassembly_styles, &disassembly_style,
2956 helptext, &setarmcmdlist);
2958 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
2959 add_show_from_set (new_set, &showarmcmdlist);
2961 add_setshow_cmd_full ("apcs32", no_class,
2962 var_boolean, (char *) &arm_apcs_32,
2963 "Set usage of ARM 32-bit mode.",
2964 "Show usage of ARM 32-bit mode.",
2966 &setlist, &showlist, &new_set, &new_show);
2967 deprecate_cmd (new_set, "set arm apcs32");
2968 deprecate_cmd (new_show, "show arm apcs32");
2970 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2971 "Set usage of ARM 32-bit mode. "
2972 "When off, a 26-bit PC will be used.",
2973 "Show usage of ARM 32-bit mode. "
2974 "When off, a 26-bit PC will be used.",
2976 &setarmcmdlist, &showarmcmdlist);
2978 /* Add a command to allow the user to force the FPU model. */
2979 new_set = add_set_enum_cmd
2980 ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2981 "Set the floating point type.\n"
2982 "auto - Determine the FP typefrom the OS-ABI.\n"
2983 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
2984 "fpa - FPA co-processor (GCC compiled).\n"
2985 "softvfp - Software FP with pure-endian doubles.\n"
2986 "vfp - VFP co-processor.",
2988 set_cmd_sfunc (new_set, set_fp_model_sfunc);
2989 set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model);
2991 /* Add the deprecated "othernames" command. */
2992 deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames,
2993 "Switch to the next set of register names."),
2994 "set arm disassembly");
2996 /* Debugging flag. */
2997 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2998 "Set ARM debugging. "
2999 "When on, arm-specific debugging is enabled.",
3000 "Show ARM debugging. "
3001 "When on, arm-specific debugging is enabled.",
3003 &setdebuglist, &showdebuglist);