1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
58 #include "features/arm-with-m.c"
62 /* Macros for setting and testing a bit in a minimal symbol that marks
63 it as Thumb function. The MSB of the minimal symbol's "info" field
64 is used for this purpose.
66 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
67 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
69 #define MSYMBOL_SET_SPECIAL(msym) \
70 MSYMBOL_TARGET_FLAG_1 (msym) = 1
72 #define MSYMBOL_IS_SPECIAL(msym) \
73 MSYMBOL_TARGET_FLAG_1 (msym)
75 /* Per-objfile data used for mapping symbols. */
76 static const struct objfile_data *arm_objfile_data_key;
78 struct arm_mapping_symbol
83 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
84 DEF_VEC_O(arm_mapping_symbol_s);
86 struct arm_per_objfile
88 VEC(arm_mapping_symbol_s) **section_maps;
91 /* The list of available "set arm ..." and "show arm ..." commands. */
92 static struct cmd_list_element *setarmcmdlist = NULL;
93 static struct cmd_list_element *showarmcmdlist = NULL;
95 /* The type of floating-point to use. Keep this in sync with enum
96 arm_float_model, and the help string in _initialize_arm_tdep. */
97 static const char *fp_model_strings[] =
107 /* A variable that can be configured by the user. */
108 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
109 static const char *current_fp_model = "auto";
111 /* The ABI to use. Keep this in sync with arm_abi_kind. */
112 static const char *arm_abi_strings[] =
120 /* A variable that can be configured by the user. */
121 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
122 static const char *arm_abi_string = "auto";
124 /* The execution mode to assume. */
125 static const char *arm_mode_strings[] =
133 static const char *arm_fallback_mode_string = "auto";
134 static const char *arm_force_mode_string = "auto";
136 /* Internal override of the execution mode. -1 means no override,
137 0 means override to ARM mode, 1 means override to Thumb mode.
138 The effect is the same as if arm_force_mode has been set by the
139 user (except the internal override has precedence over a user's
140 arm_force_mode override). */
141 static int arm_override_mode = -1;
143 /* Number of different reg name sets (options). */
144 static int num_disassembly_options;
146 /* The standard register names, and all the valid aliases for them. Note
147 that `fp', `sp' and `pc' are not added in this alias list, because they
148 have been added as builtin user registers in
149 std-regs.c:_initialize_frame_reg. */
154 } arm_register_aliases[] = {
155 /* Basic register numbers. */
172 /* Synonyms (argument and variable registers). */
185 /* Other platform-specific names for r9. */
191 /* Names used by GCC (not listed in the ARM EABI). */
193 /* A special name from the older ATPCS. */
197 static const char *const arm_register_names[] =
198 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
199 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
200 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
201 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
202 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
203 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
204 "fps", "cpsr" }; /* 24 25 */
206 /* Valid register name styles. */
207 static const char **valid_disassembly_styles;
209 /* Disassembly style to use. Default to "std" register names. */
210 static const char *disassembly_style;
212 /* This is used to keep the bfd arch_info in sync with the disassembly
214 static void set_disassembly_style_sfunc(char *, int,
215 struct cmd_list_element *);
216 static void set_disassembly_style (void);
218 static void convert_from_extended (const struct floatformat *, const void *,
220 static void convert_to_extended (const struct floatformat *, void *,
223 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
224 struct regcache *regcache,
225 int regnum, gdb_byte *buf);
226 static void arm_neon_quad_write (struct gdbarch *gdbarch,
227 struct regcache *regcache,
228 int regnum, const gdb_byte *buf);
230 struct arm_prologue_cache
232 /* The stack pointer at the time this frame was created; i.e. the
233 caller's stack pointer when this function was called. It is used
234 to identify this frame. */
237 /* The frame base for this frame is just prev_sp - frame size.
238 FRAMESIZE is the distance from the frame pointer to the
239 initial stack pointer. */
243 /* The register used to hold the frame pointer for this frame. */
246 /* Saved register offsets. */
247 struct trad_frame_saved_reg *saved_regs;
250 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
251 CORE_ADDR prologue_start,
252 CORE_ADDR prologue_end,
253 struct arm_prologue_cache *cache);
255 /* Architecture version for displaced stepping. This effects the behaviour of
256 certain instructions, and really should not be hard-wired. */
258 #define DISPLACED_STEPPING_ARCH_VERSION 5
260 /* Addresses for calling Thumb functions have the bit 0 set.
261 Here are some macros to test, set, or clear bit 0 of addresses. */
262 #define IS_THUMB_ADDR(addr) ((addr) & 1)
263 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
264 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
266 /* Set to true if the 32-bit mode is in use. */
270 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
273 arm_psr_thumb_bit (struct gdbarch *gdbarch)
275 if (gdbarch_tdep (gdbarch)->is_m)
281 /* Determine if FRAME is executing in Thumb mode. */
284 arm_frame_is_thumb (struct frame_info *frame)
287 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
289 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
290 directly (from a signal frame or dummy frame) or by interpreting
291 the saved LR (from a prologue or DWARF frame). So consult it and
292 trust the unwinders. */
293 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
295 return (cpsr & t_bit) != 0;
298 /* Callback for VEC_lower_bound. */
301 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
302 const struct arm_mapping_symbol *rhs)
304 return lhs->value < rhs->value;
307 /* Search for the mapping symbol covering MEMADDR. If one is found,
308 return its type. Otherwise, return 0. If START is non-NULL,
309 set *START to the location of the mapping symbol. */
312 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
314 struct obj_section *sec;
316 /* If there are mapping symbols, consult them. */
317 sec = find_pc_section (memaddr);
320 struct arm_per_objfile *data;
321 VEC(arm_mapping_symbol_s) *map;
322 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
326 data = objfile_data (sec->objfile, arm_objfile_data_key);
329 map = data->section_maps[sec->the_bfd_section->index];
330 if (!VEC_empty (arm_mapping_symbol_s, map))
332 struct arm_mapping_symbol *map_sym;
334 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
335 arm_compare_mapping_symbols);
337 /* VEC_lower_bound finds the earliest ordered insertion
338 point. If the following symbol starts at this exact
339 address, we use that; otherwise, the preceding
340 mapping symbol covers this address. */
341 if (idx < VEC_length (arm_mapping_symbol_s, map))
343 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
344 if (map_sym->value == map_key.value)
347 *start = map_sym->value + obj_section_addr (sec);
348 return map_sym->type;
354 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
356 *start = map_sym->value + obj_section_addr (sec);
357 return map_sym->type;
366 /* Determine if the program counter specified in MEMADDR is in a Thumb
367 function. This function should be called for addresses unrelated to
368 any executing frame; otherwise, prefer arm_frame_is_thumb. */
371 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
373 struct obj_section *sec;
374 struct minimal_symbol *sym;
376 struct displaced_step_closure* dsc
377 = get_displaced_step_closure_by_addr(memaddr);
379 /* If checking the mode of displaced instruction in copy area, the mode
380 should be determined by instruction on the original address. */
384 fprintf_unfiltered (gdb_stdlog,
385 "displaced: check mode of %.8lx instead of %.8lx\n",
386 (unsigned long) dsc->insn_addr,
387 (unsigned long) memaddr);
388 memaddr = dsc->insn_addr;
391 /* If bit 0 of the address is set, assume this is a Thumb address. */
392 if (IS_THUMB_ADDR (memaddr))
395 /* Respect internal mode override if active. */
396 if (arm_override_mode != -1)
397 return arm_override_mode;
399 /* If the user wants to override the symbol table, let him. */
400 if (strcmp (arm_force_mode_string, "arm") == 0)
402 if (strcmp (arm_force_mode_string, "thumb") == 0)
405 /* ARM v6-M and v7-M are always in Thumb mode. */
406 if (gdbarch_tdep (gdbarch)->is_m)
409 /* If there are mapping symbols, consult them. */
410 type = arm_find_mapping_symbol (memaddr, NULL);
414 /* Thumb functions have a "special" bit set in minimal symbols. */
415 sym = lookup_minimal_symbol_by_pc (memaddr);
417 return (MSYMBOL_IS_SPECIAL (sym));
419 /* If the user wants to override the fallback mode, let them. */
420 if (strcmp (arm_fallback_mode_string, "arm") == 0)
422 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
425 /* If we couldn't find any symbol, but we're talking to a running
426 target, then trust the current value of $cpsr. This lets
427 "display/i $pc" always show the correct mode (though if there is
428 a symbol table we will not reach here, so it still may not be
429 displayed in the mode it will be executed). */
430 if (target_has_registers)
431 return arm_frame_is_thumb (get_current_frame ());
433 /* Otherwise we're out of luck; we assume ARM. */
437 /* Remove useless bits from addresses in a running program. */
439 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
442 return UNMAKE_THUMB_ADDR (val);
444 return (val & 0x03fffffc);
447 /* When reading symbols, we need to zap the low bit of the address,
448 which may be set to 1 for Thumb functions. */
450 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
455 /* Return 1 if PC is the start of a compiler helper function which
456 can be safely ignored during prologue skipping. IS_THUMB is true
457 if the function is known to be a Thumb function due to the way it
460 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
462 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
463 struct minimal_symbol *msym;
465 msym = lookup_minimal_symbol_by_pc (pc);
467 && SYMBOL_VALUE_ADDRESS (msym) == pc
468 && SYMBOL_LINKAGE_NAME (msym) != NULL)
470 const char *name = SYMBOL_LINKAGE_NAME (msym);
472 /* The GNU linker's Thumb call stub to foo is named
474 if (strstr (name, "_from_thumb") != NULL)
477 /* On soft-float targets, __truncdfsf2 is called to convert promoted
478 arguments to their argument types in non-prototyped
480 if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
482 if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
485 /* Internal functions related to thread-local storage. */
486 if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
488 if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
493 /* If we run against a stripped glibc, we may be unable to identify
494 special functions by name. Check for one important case,
495 __aeabi_read_tp, by comparing the *code* against the default
496 implementation (this is hand-written ARM assembler in glibc). */
499 && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
500 == 0xe3e00a0f /* mov r0, #0xffff0fff */
501 && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
502 == 0xe240f01f) /* sub pc, r0, #31 */
509 /* Support routines for instruction parsing. */
510 #define submask(x) ((1L << ((x) + 1)) - 1)
511 #define bit(obj,st) (((obj) >> (st)) & 1)
512 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
513 #define sbits(obj,st,fn) \
514 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
515 #define BranchDest(addr,instr) \
516 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
518 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
519 the first 16-bit of instruction, and INSN2 is the second 16-bit of
521 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
522 ((bits ((insn1), 0, 3) << 12) \
523 | (bits ((insn1), 10, 10) << 11) \
524 | (bits ((insn2), 12, 14) << 8) \
525 | bits ((insn2), 0, 7))
527 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
528 the 32-bit instruction. */
529 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
530 ((bits ((insn), 16, 19) << 12) \
531 | bits ((insn), 0, 11))
533 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
536 thumb_expand_immediate (unsigned int imm)
538 unsigned int count = imm >> 7;
546 return (imm & 0xff) | ((imm & 0xff) << 16);
548 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
550 return (imm & 0xff) | ((imm & 0xff) << 8)
551 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
554 return (0x80 | (imm & 0x7f)) << (32 - count);
557 /* Return 1 if the 16-bit Thumb instruction INST might change
558 control flow, 0 otherwise. */
561 thumb_instruction_changes_pc (unsigned short inst)
563 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
566 if ((inst & 0xf000) == 0xd000) /* conditional branch */
569 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
572 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
575 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
578 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
584 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
585 might change control flow, 0 otherwise. */
588 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
590 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
592 /* Branches and miscellaneous control instructions. */
594 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
599 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
601 /* SUBS PC, LR, #imm8. */
604 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
606 /* Conditional branch. */
613 if ((inst1 & 0xfe50) == 0xe810)
615 /* Load multiple or RFE. */
617 if (bit (inst1, 7) && !bit (inst1, 8))
623 else if (!bit (inst1, 7) && bit (inst1, 8))
629 else if (bit (inst1, 7) && bit (inst1, 8))
634 else if (!bit (inst1, 7) && !bit (inst1, 8))
643 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
645 /* MOV PC or MOVS PC. */
649 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
652 if (bits (inst1, 0, 3) == 15)
658 if ((inst2 & 0x0fc0) == 0x0000)
664 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
670 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
679 /* Analyze a Thumb prologue, looking for a recognizable stack frame
680 and frame pointer. Scan until we encounter a store that could
681 clobber the stack frame unexpectedly, or an unknown instruction.
682 Return the last address which is definitely safe to skip for an
683 initial breakpoint. */
686 thumb_analyze_prologue (struct gdbarch *gdbarch,
687 CORE_ADDR start, CORE_ADDR limit,
688 struct arm_prologue_cache *cache)
690 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
691 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
694 struct pv_area *stack;
695 struct cleanup *back_to;
697 CORE_ADDR unrecognized_pc = 0;
699 for (i = 0; i < 16; i++)
700 regs[i] = pv_register (i, 0);
701 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
702 back_to = make_cleanup_free_pv_area (stack);
704 while (start < limit)
708 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
710 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
715 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
718 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
719 whether to save LR (R14). */
720 mask = (insn & 0xff) | ((insn & 0x100) << 6);
722 /* Calculate offsets of saved R0-R7 and LR. */
723 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
724 if (mask & (1 << regno))
726 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
728 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
731 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
734 offset = (insn & 0x7f) << 2; /* get scaled offset */
735 if (insn & 0x80) /* Check for SUB. */
736 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
739 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
742 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
743 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
745 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
746 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
747 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
749 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
750 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
751 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
753 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
754 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
755 && pv_is_constant (regs[bits (insn, 3, 5)]))
756 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
757 regs[bits (insn, 6, 8)]);
758 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
759 && pv_is_constant (regs[bits (insn, 3, 6)]))
761 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
762 int rm = bits (insn, 3, 6);
763 regs[rd] = pv_add (regs[rd], regs[rm]);
765 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
767 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
768 int src_reg = (insn & 0x78) >> 3;
769 regs[dst_reg] = regs[src_reg];
771 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
773 /* Handle stores to the stack. Normally pushes are used,
774 but with GCC -mtpcs-frame, there may be other stores
775 in the prologue to create the frame. */
776 int regno = (insn >> 8) & 0x7;
779 offset = (insn & 0xff) << 2;
780 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
782 if (pv_area_store_would_trash (stack, addr))
785 pv_area_store (stack, addr, 4, regs[regno]);
787 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
789 int rd = bits (insn, 0, 2);
790 int rn = bits (insn, 3, 5);
793 offset = bits (insn, 6, 10) << 2;
794 addr = pv_add_constant (regs[rn], offset);
796 if (pv_area_store_would_trash (stack, addr))
799 pv_area_store (stack, addr, 4, regs[rd]);
801 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
802 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
803 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
804 /* Ignore stores of argument registers to the stack. */
806 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
807 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
808 /* Ignore block loads from the stack, potentially copying
809 parameters from memory. */
811 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
812 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
813 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
814 /* Similarly ignore single loads from the stack. */
816 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
817 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
818 /* Skip register copies, i.e. saves to another register
819 instead of the stack. */
821 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
822 /* Recognize constant loads; even with small stacks these are necessary
824 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
825 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
827 /* Constant pool loads, for the same reason. */
828 unsigned int constant;
831 loc = start + 4 + bits (insn, 0, 7) * 4;
832 constant = read_memory_unsigned_integer (loc, 4, byte_order);
833 regs[bits (insn, 8, 10)] = pv_constant (constant);
835 else if ((insn & 0xe000) == 0xe000)
837 unsigned short inst2;
839 inst2 = read_memory_unsigned_integer (start + 2, 2,
840 byte_order_for_code);
842 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
844 /* BL, BLX. Allow some special function calls when
845 skipping the prologue; GCC generates these before
846 storing arguments to the stack. */
848 int j1, j2, imm1, imm2;
850 imm1 = sbits (insn, 0, 10);
851 imm2 = bits (inst2, 0, 10);
852 j1 = bit (inst2, 13);
853 j2 = bit (inst2, 11);
855 offset = ((imm1 << 12) + (imm2 << 1));
856 offset ^= ((!j2) << 22) | ((!j1) << 23);
858 nextpc = start + 4 + offset;
859 /* For BLX make sure to clear the low bits. */
860 if (bit (inst2, 12) == 0)
861 nextpc = nextpc & 0xfffffffc;
863 if (!skip_prologue_function (gdbarch, nextpc,
864 bit (inst2, 12) != 0))
868 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
870 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
872 pv_t addr = regs[bits (insn, 0, 3)];
875 if (pv_area_store_would_trash (stack, addr))
878 /* Calculate offsets of saved registers. */
879 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
880 if (inst2 & (1 << regno))
882 addr = pv_add_constant (addr, -4);
883 pv_area_store (stack, addr, 4, regs[regno]);
887 regs[bits (insn, 0, 3)] = addr;
890 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
892 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
894 int regno1 = bits (inst2, 12, 15);
895 int regno2 = bits (inst2, 8, 11);
896 pv_t addr = regs[bits (insn, 0, 3)];
898 offset = inst2 & 0xff;
900 addr = pv_add_constant (addr, offset);
902 addr = pv_add_constant (addr, -offset);
904 if (pv_area_store_would_trash (stack, addr))
907 pv_area_store (stack, addr, 4, regs[regno1]);
908 pv_area_store (stack, pv_add_constant (addr, 4),
912 regs[bits (insn, 0, 3)] = addr;
915 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
916 && (inst2 & 0x0c00) == 0x0c00
917 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
919 int regno = bits (inst2, 12, 15);
920 pv_t addr = regs[bits (insn, 0, 3)];
922 offset = inst2 & 0xff;
924 addr = pv_add_constant (addr, offset);
926 addr = pv_add_constant (addr, -offset);
928 if (pv_area_store_would_trash (stack, addr))
931 pv_area_store (stack, addr, 4, regs[regno]);
934 regs[bits (insn, 0, 3)] = addr;
937 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
938 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
940 int regno = bits (inst2, 12, 15);
943 offset = inst2 & 0xfff;
944 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
946 if (pv_area_store_would_trash (stack, addr))
949 pv_area_store (stack, addr, 4, regs[regno]);
952 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
953 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
954 /* Ignore stores of argument registers to the stack. */
957 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
958 && (inst2 & 0x0d00) == 0x0c00
959 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
960 /* Ignore stores of argument registers to the stack. */
963 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
965 && (inst2 & 0x8000) == 0x0000
966 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
967 /* Ignore block loads from the stack, potentially copying
968 parameters from memory. */
971 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
973 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
974 /* Similarly ignore dual loads from the stack. */
977 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
978 && (inst2 & 0x0d00) == 0x0c00
979 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
980 /* Similarly ignore single loads from the stack. */
983 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
984 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
985 /* Similarly ignore single loads from the stack. */
988 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
989 && (inst2 & 0x8000) == 0x0000)
991 unsigned int imm = ((bits (insn, 10, 10) << 11)
992 | (bits (inst2, 12, 14) << 8)
993 | bits (inst2, 0, 7));
995 regs[bits (inst2, 8, 11)]
996 = pv_add_constant (regs[bits (insn, 0, 3)],
997 thumb_expand_immediate (imm));
1000 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1001 && (inst2 & 0x8000) == 0x0000)
1003 unsigned int imm = ((bits (insn, 10, 10) << 11)
1004 | (bits (inst2, 12, 14) << 8)
1005 | bits (inst2, 0, 7));
1007 regs[bits (inst2, 8, 11)]
1008 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
1011 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1012 && (inst2 & 0x8000) == 0x0000)
1014 unsigned int imm = ((bits (insn, 10, 10) << 11)
1015 | (bits (inst2, 12, 14) << 8)
1016 | bits (inst2, 0, 7));
1018 regs[bits (inst2, 8, 11)]
1019 = pv_add_constant (regs[bits (insn, 0, 3)],
1020 - (CORE_ADDR) thumb_expand_immediate (imm));
1023 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1024 && (inst2 & 0x8000) == 0x0000)
1026 unsigned int imm = ((bits (insn, 10, 10) << 11)
1027 | (bits (inst2, 12, 14) << 8)
1028 | bits (inst2, 0, 7));
1030 regs[bits (inst2, 8, 11)]
1031 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1034 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1036 unsigned int imm = ((bits (insn, 10, 10) << 11)
1037 | (bits (inst2, 12, 14) << 8)
1038 | bits (inst2, 0, 7));
1040 regs[bits (inst2, 8, 11)]
1041 = pv_constant (thumb_expand_immediate (imm));
1044 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1047 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1049 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1052 else if (insn == 0xea5f /* mov.w Rd,Rm */
1053 && (inst2 & 0xf0f0) == 0)
1055 int dst_reg = (inst2 & 0x0f00) >> 8;
1056 int src_reg = inst2 & 0xf;
1057 regs[dst_reg] = regs[src_reg];
1060 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1062 /* Constant pool loads. */
1063 unsigned int constant;
1066 offset = bits (insn, 0, 11);
1068 loc = start + 4 + offset;
1070 loc = start + 4 - offset;
1072 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1073 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1076 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1078 /* Constant pool loads. */
1079 unsigned int constant;
1082 offset = bits (insn, 0, 7) << 2;
1084 loc = start + 4 + offset;
1086 loc = start + 4 - offset;
1088 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1089 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1091 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1092 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1095 else if (thumb2_instruction_changes_pc (insn, inst2))
1097 /* Don't scan past anything that might change control flow. */
1102 /* The optimizer might shove anything into the prologue,
1103 so we just skip what we don't recognize. */
1104 unrecognized_pc = start;
1109 else if (thumb_instruction_changes_pc (insn))
1111 /* Don't scan past anything that might change control flow. */
1116 /* The optimizer might shove anything into the prologue,
1117 so we just skip what we don't recognize. */
1118 unrecognized_pc = start;
1125 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1126 paddress (gdbarch, start));
1128 if (unrecognized_pc == 0)
1129 unrecognized_pc = start;
1133 do_cleanups (back_to);
1134 return unrecognized_pc;
1137 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1139 /* Frame pointer is fp. Frame size is constant. */
1140 cache->framereg = ARM_FP_REGNUM;
1141 cache->framesize = -regs[ARM_FP_REGNUM].k;
1143 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1145 /* Frame pointer is r7. Frame size is constant. */
1146 cache->framereg = THUMB_FP_REGNUM;
1147 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1149 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1151 /* Try the stack pointer... this is a bit desperate. */
1152 cache->framereg = ARM_SP_REGNUM;
1153 cache->framesize = -regs[ARM_SP_REGNUM].k;
1157 /* We're just out of luck. We don't know where the frame is. */
1158 cache->framereg = -1;
1159 cache->framesize = 0;
1162 for (i = 0; i < 16; i++)
1163 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1164 cache->saved_regs[i].addr = offset;
1166 do_cleanups (back_to);
1167 return unrecognized_pc;
1171 /* Try to analyze the instructions starting from PC, which load symbol
1172 __stack_chk_guard. Return the address of instruction after loading this
1173 symbol, set the dest register number to *BASEREG, and set the size of
1174 instructions for loading symbol in OFFSET. Return 0 if instructions are
1178 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1179 unsigned int *destreg, int *offset)
1181 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1182 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1183 unsigned int low, high, address;
1188 unsigned short insn1
1189 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1191 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1193 *destreg = bits (insn1, 8, 10);
1195 address = bits (insn1, 0, 7);
1197 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1199 unsigned short insn2
1200 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1202 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1205 = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1207 = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1209 /* movt Rd, #const */
1210 if ((insn1 & 0xfbc0) == 0xf2c0)
1212 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1213 *destreg = bits (insn2, 8, 11);
1215 address = (high << 16 | low);
1222 = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1224 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1226 address = bits (insn, 0, 11);
1227 *destreg = bits (insn, 12, 15);
1230 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1232 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1235 = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1237 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1239 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1240 *destreg = bits (insn, 12, 15);
1242 address = (high << 16 | low);
1250 /* Try to skip a sequence of instructions used for stack protector. If PC
1251 points to the first instruction of this sequence, return the address of
1252 first instruction after this sequence, otherwise, return original PC.
1254 On arm, this sequence of instructions is composed of mainly three steps,
1255 Step 1: load symbol __stack_chk_guard,
1256 Step 2: load from address of __stack_chk_guard,
1257 Step 3: store it to somewhere else.
1259 Usually, instructions on step 2 and step 3 are the same on various ARM
1260 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1261 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1262 instructions in step 1 vary from different ARM architectures. On ARMv7,
1265 movw Rn, #:lower16:__stack_chk_guard
1266 movt Rn, #:upper16:__stack_chk_guard
1273 .word __stack_chk_guard
1275 Since ldr/str is a very popular instruction, we can't use them as
1276 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1277 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1278 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1281 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1283 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1284 unsigned int address, basereg;
1285 struct minimal_symbol *stack_chk_guard;
1287 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1290 /* Try to parse the instructions in Step 1. */
1291 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1296 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1297 /* If name of symbol doesn't start with '__stack_chk_guard', this
1298 instruction sequence is not for stack protector. If symbol is
1299 removed, we conservatively think this sequence is for stack protector. */
1301 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
1302 strlen ("__stack_chk_guard")) != 0)
1307 unsigned int destreg;
1309 = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1311 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1312 if ((insn & 0xf800) != 0x6800)
1314 if (bits (insn, 3, 5) != basereg)
1316 destreg = bits (insn, 0, 2);
1318 insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1319 byte_order_for_code);
1320 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1321 if ((insn & 0xf800) != 0x6000)
1323 if (destreg != bits (insn, 0, 2))
1328 unsigned int destreg;
1330 = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1332 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1333 if ((insn & 0x0e500000) != 0x04100000)
1335 if (bits (insn, 16, 19) != basereg)
1337 destreg = bits (insn, 12, 15);
1338 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1339 insn = read_memory_unsigned_integer (pc + offset + 4,
1340 4, byte_order_for_code);
1341 if ((insn & 0x0e500000) != 0x04000000)
1343 if (bits (insn, 12, 15) != destreg)
1346 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1349 return pc + offset + 4;
1351 return pc + offset + 8;
1354 /* Advance the PC across any function entry prologue instructions to
1355 reach some "real" code.
1357 The APCS (ARM Procedure Call Standard) defines the following
1361 [stmfd sp!, {a1,a2,a3,a4}]
1362 stmfd sp!, {...,fp,ip,lr,pc}
1363 [stfe f7, [sp, #-12]!]
1364 [stfe f6, [sp, #-12]!]
1365 [stfe f5, [sp, #-12]!]
1366 [stfe f4, [sp, #-12]!]
1367 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1370 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1372 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1375 CORE_ADDR func_addr, limit_pc;
1376 struct symtab_and_line sal;
1378 /* See if we can determine the end of the prologue via the symbol table.
1379 If so, then return either PC, or the PC after the prologue, whichever
1381 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1383 CORE_ADDR post_prologue_pc
1384 = skip_prologue_using_sal (gdbarch, func_addr);
1385 struct symtab *s = find_pc_symtab (func_addr);
1387 if (post_prologue_pc)
1389 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1392 /* GCC always emits a line note before the prologue and another
1393 one after, even if the two are at the same address or on the
1394 same line. Take advantage of this so that we do not need to
1395 know every instruction that might appear in the prologue. We
1396 will have producer information for most binaries; if it is
1397 missing (e.g. for -gstabs), assuming the GNU tools. */
1398 if (post_prologue_pc
1400 || s->producer == NULL
1401 || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0))
1402 return post_prologue_pc;
1404 if (post_prologue_pc != 0)
1406 CORE_ADDR analyzed_limit;
1408 /* For non-GCC compilers, make sure the entire line is an
1409 acceptable prologue; GDB will round this function's
1410 return value up to the end of the following line so we
1411 can not skip just part of a line (and we do not want to).
1413 RealView does not treat the prologue specially, but does
1414 associate prologue code with the opening brace; so this
1415 lets us skip the first line if we think it is the opening
1417 if (arm_pc_is_thumb (gdbarch, func_addr))
1418 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1419 post_prologue_pc, NULL);
1421 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1422 post_prologue_pc, NULL);
1424 if (analyzed_limit != post_prologue_pc)
1427 return post_prologue_pc;
1431 /* Can't determine prologue from the symbol table, need to examine
1434 /* Find an upper limit on the function prologue using the debug
1435 information. If the debug information could not be used to provide
1436 that bound, then use an arbitrary large number as the upper bound. */
1437 /* Like arm_scan_prologue, stop no later than pc + 64. */
1438 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1440 limit_pc = pc + 64; /* Magic. */
1443 /* Check if this is Thumb code. */
1444 if (arm_pc_is_thumb (gdbarch, pc))
1445 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1447 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
1449 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
1451 /* "mov ip, sp" is no longer a required part of the prologue. */
1452 if (inst == 0xe1a0c00d) /* mov ip, sp */
1455 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1458 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1461 /* Some prologues begin with "str lr, [sp, #-4]!". */
1462 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
1465 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1468 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1471 /* Any insns after this point may float into the code, if it makes
1472 for better instruction scheduling, so we skip them only if we
1473 find them, but still consider the function to be frame-ful. */
1475 /* We may have either one sfmfd instruction here, or several stfe
1476 insns, depending on the version of floating point code we
1478 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1481 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1484 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1487 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1490 if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1491 || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1492 || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1495 if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1496 || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1497 || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1500 /* Un-recognized instruction; stop scanning. */
1504 return skip_pc; /* End of prologue. */
1508 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1509 This function decodes a Thumb function prologue to determine:
1510 1) the size of the stack frame
1511 2) which registers are saved on it
1512 3) the offsets of saved regs
1513 4) the offset from the stack pointer to the frame pointer
1515 A typical Thumb function prologue would create this stack frame
1516 (offsets relative to FP)
1517 old SP -> 24 stack parameters
1520 R7 -> 0 local variables (16 bytes)
1521 SP -> -12 additional stack space (12 bytes)
1522 The frame size would thus be 36 bytes, and the frame offset would be
1523 12 bytes. The frame register is R7.
1525 The comments for thumb_skip_prolog() describe the algorithm we use
1526 to detect the end of the prolog. */
1530 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1531 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1533 CORE_ADDR prologue_start;
1534 CORE_ADDR prologue_end;
1535 CORE_ADDR current_pc;
1537 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1540 /* See comment in arm_scan_prologue for an explanation of
1542 if (prologue_end > prologue_start + 64)
1544 prologue_end = prologue_start + 64;
1548 /* We're in the boondocks: we have no idea where the start of the
1552 prologue_end = min (prologue_end, prev_pc);
1554 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1557 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1560 arm_instruction_changes_pc (uint32_t this_instr)
1562 if (bits (this_instr, 28, 31) == INST_NV)
1563 /* Unconditional instructions. */
1564 switch (bits (this_instr, 24, 27))
1568 /* Branch with Link and change to Thumb. */
1573 /* Coprocessor register transfer. */
1574 if (bits (this_instr, 12, 15) == 15)
1575 error (_("Invalid update to pc in instruction"));
1581 switch (bits (this_instr, 25, 27))
1584 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
1586 /* Multiplies and extra load/stores. */
1587 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
1588 /* Neither multiplies nor extension load/stores are allowed
1592 /* Otherwise, miscellaneous instructions. */
1594 /* BX <reg>, BXJ <reg>, BLX <reg> */
1595 if (bits (this_instr, 4, 27) == 0x12fff1
1596 || bits (this_instr, 4, 27) == 0x12fff2
1597 || bits (this_instr, 4, 27) == 0x12fff3)
1600 /* Other miscellaneous instructions are unpredictable if they
1604 /* Data processing instruction. Fall through. */
1607 if (bits (this_instr, 12, 15) == 15)
1614 /* Media instructions and architecturally undefined instructions. */
1615 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
1619 if (bit (this_instr, 20) == 0)
1623 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
1629 /* Load/store multiple. */
1630 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
1636 /* Branch and branch with link. */
1641 /* Coprocessor transfers or SWIs can not affect PC. */
1645 internal_error (__FILE__, __LINE__, _("bad value in switch"));
1649 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1650 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1651 fill it in. Return the first address not recognized as a prologue
1654 We recognize all the instructions typically found in ARM prologues,
1655 plus harmless instructions which can be skipped (either for analysis
1656 purposes, or a more restrictive set that can be skipped when finding
1657 the end of the prologue). */
1660 arm_analyze_prologue (struct gdbarch *gdbarch,
1661 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1662 struct arm_prologue_cache *cache)
1664 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1665 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1667 CORE_ADDR offset, current_pc;
1668 pv_t regs[ARM_FPS_REGNUM];
1669 struct pv_area *stack;
1670 struct cleanup *back_to;
1671 int framereg, framesize;
1672 CORE_ADDR unrecognized_pc = 0;
1674 /* Search the prologue looking for instructions that set up the
1675 frame pointer, adjust the stack pointer, and save registers.
1677 Be careful, however, and if it doesn't look like a prologue,
1678 don't try to scan it. If, for instance, a frameless function
1679 begins with stmfd sp!, then we will tell ourselves there is
1680 a frame, which will confuse stack traceback, as well as "finish"
1681 and other operations that rely on a knowledge of the stack
1684 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1685 regs[regno] = pv_register (regno, 0);
1686 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1687 back_to = make_cleanup_free_pv_area (stack);
1689 for (current_pc = prologue_start;
1690 current_pc < prologue_end;
1694 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
1696 if (insn == 0xe1a0c00d) /* mov ip, sp */
1698 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1701 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1702 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1704 unsigned imm = insn & 0xff; /* immediate value */
1705 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1706 int rd = bits (insn, 12, 15);
1707 imm = (imm >> rot) | (imm << (32 - rot));
1708 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1711 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1712 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1714 unsigned imm = insn & 0xff; /* immediate value */
1715 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1716 int rd = bits (insn, 12, 15);
1717 imm = (imm >> rot) | (imm << (32 - rot));
1718 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1721 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1724 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1726 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1727 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1728 regs[bits (insn, 12, 15)]);
1731 else if ((insn & 0xffff0000) == 0xe92d0000)
1732 /* stmfd sp!, {..., fp, ip, lr, pc}
1734 stmfd sp!, {a1, a2, a3, a4} */
1736 int mask = insn & 0xffff;
1738 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1741 /* Calculate offsets of saved registers. */
1742 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1743 if (mask & (1 << regno))
1746 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1747 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1750 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1751 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1752 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1754 /* No need to add this to saved_regs -- it's just an arg reg. */
1757 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1758 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1759 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1761 /* No need to add this to saved_regs -- it's just an arg reg. */
1764 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1766 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1768 /* No need to add this to saved_regs -- it's just arg regs. */
1771 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1773 unsigned imm = insn & 0xff; /* immediate value */
1774 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1775 imm = (imm >> rot) | (imm << (32 - rot));
1776 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1778 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1780 unsigned imm = insn & 0xff; /* immediate value */
1781 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1782 imm = (imm >> rot) | (imm << (32 - rot));
1783 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1785 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1787 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1789 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1792 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1793 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1794 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1796 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1798 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1800 int n_saved_fp_regs;
1801 unsigned int fp_start_reg, fp_bound_reg;
1803 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1806 if ((insn & 0x800) == 0x800) /* N0 is set */
1808 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1809 n_saved_fp_regs = 3;
1811 n_saved_fp_regs = 1;
1815 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1816 n_saved_fp_regs = 2;
1818 n_saved_fp_regs = 4;
1821 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1822 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1823 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1825 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1826 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1827 regs[fp_start_reg++]);
1830 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1832 /* Allow some special function calls when skipping the
1833 prologue; GCC generates these before storing arguments to
1835 CORE_ADDR dest = BranchDest (current_pc, insn);
1837 if (skip_prologue_function (gdbarch, dest, 0))
1842 else if ((insn & 0xf0000000) != 0xe0000000)
1843 break; /* Condition not true, exit early. */
1844 else if (arm_instruction_changes_pc (insn))
1845 /* Don't scan past anything that might change control flow. */
1847 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1848 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1849 /* Ignore block loads from the stack, potentially copying
1850 parameters from memory. */
1852 else if ((insn & 0xfc500000) == 0xe4100000
1853 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1854 /* Similarly ignore single loads from the stack. */
1856 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1857 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1858 register instead of the stack. */
1862 /* The optimizer might shove anything into the prologue,
1863 so we just skip what we don't recognize. */
1864 unrecognized_pc = current_pc;
1869 if (unrecognized_pc == 0)
1870 unrecognized_pc = current_pc;
1872 /* The frame size is just the distance from the frame register
1873 to the original stack pointer. */
1874 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1876 /* Frame pointer is fp. */
1877 framereg = ARM_FP_REGNUM;
1878 framesize = -regs[ARM_FP_REGNUM].k;
1880 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1882 /* Try the stack pointer... this is a bit desperate. */
1883 framereg = ARM_SP_REGNUM;
1884 framesize = -regs[ARM_SP_REGNUM].k;
1888 /* We're just out of luck. We don't know where the frame is. */
1895 cache->framereg = framereg;
1896 cache->framesize = framesize;
1898 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1899 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1900 cache->saved_regs[regno].addr = offset;
1904 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1905 paddress (gdbarch, unrecognized_pc));
1907 do_cleanups (back_to);
1908 return unrecognized_pc;
1912 arm_scan_prologue (struct frame_info *this_frame,
1913 struct arm_prologue_cache *cache)
1915 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1916 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1918 CORE_ADDR prologue_start, prologue_end, current_pc;
1919 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1920 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1921 pv_t regs[ARM_FPS_REGNUM];
1922 struct pv_area *stack;
1923 struct cleanup *back_to;
1926 /* Assume there is no frame until proven otherwise. */
1927 cache->framereg = ARM_SP_REGNUM;
1928 cache->framesize = 0;
1930 /* Check for Thumb prologue. */
1931 if (arm_frame_is_thumb (this_frame))
1933 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1937 /* Find the function prologue. If we can't find the function in
1938 the symbol table, peek in the stack frame to find the PC. */
1939 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1942 /* One way to find the end of the prologue (which works well
1943 for unoptimized code) is to do the following:
1945 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1948 prologue_end = prev_pc;
1949 else if (sal.end < prologue_end)
1950 prologue_end = sal.end;
1952 This mechanism is very accurate so long as the optimizer
1953 doesn't move any instructions from the function body into the
1954 prologue. If this happens, sal.end will be the last
1955 instruction in the first hunk of prologue code just before
1956 the first instruction that the scheduler has moved from
1957 the body to the prologue.
1959 In order to make sure that we scan all of the prologue
1960 instructions, we use a slightly less accurate mechanism which
1961 may scan more than necessary. To help compensate for this
1962 lack of accuracy, the prologue scanning loop below contains
1963 several clauses which'll cause the loop to terminate early if
1964 an implausible prologue instruction is encountered.
1970 is a suitable endpoint since it accounts for the largest
1971 possible prologue plus up to five instructions inserted by
1974 if (prologue_end > prologue_start + 64)
1976 prologue_end = prologue_start + 64; /* See above. */
1981 /* We have no symbol information. Our only option is to assume this
1982 function has a standard stack frame and the normal frame register.
1983 Then, we can find the value of our frame pointer on entrance to
1984 the callee (or at the present moment if this is the innermost frame).
1985 The value stored there should be the address of the stmfd + 8. */
1986 CORE_ADDR frame_loc;
1987 LONGEST return_value;
1989 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1990 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
1994 prologue_start = gdbarch_addr_bits_remove
1995 (gdbarch, return_value) - 8;
1996 prologue_end = prologue_start + 64; /* See above. */
2000 if (prev_pc < prologue_end)
2001 prologue_end = prev_pc;
2003 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
2006 static struct arm_prologue_cache *
2007 arm_make_prologue_cache (struct frame_info *this_frame)
2010 struct arm_prologue_cache *cache;
2011 CORE_ADDR unwound_fp;
2013 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2014 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2016 arm_scan_prologue (this_frame, cache);
2018 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
2019 if (unwound_fp == 0)
2022 cache->prev_sp = unwound_fp + cache->framesize;
2024 /* Calculate actual addresses of saved registers using offsets
2025 determined by arm_scan_prologue. */
2026 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2027 if (trad_frame_addr_p (cache->saved_regs, reg))
2028 cache->saved_regs[reg].addr += cache->prev_sp;
2033 /* Our frame ID for a normal frame is the current function's starting PC
2034 and the caller's SP when we were called. */
2037 arm_prologue_this_id (struct frame_info *this_frame,
2039 struct frame_id *this_id)
2041 struct arm_prologue_cache *cache;
2045 if (*this_cache == NULL)
2046 *this_cache = arm_make_prologue_cache (this_frame);
2047 cache = *this_cache;
2049 /* This is meant to halt the backtrace at "_start". */
2050 pc = get_frame_pc (this_frame);
2051 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
2054 /* If we've hit a wall, stop. */
2055 if (cache->prev_sp == 0)
2058 /* Use function start address as part of the frame ID. If we cannot
2059 identify the start address (due to missing symbol information),
2060 fall back to just using the current PC. */
2061 func = get_frame_func (this_frame);
2065 id = frame_id_build (cache->prev_sp, func);
2069 static struct value *
2070 arm_prologue_prev_register (struct frame_info *this_frame,
2074 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2075 struct arm_prologue_cache *cache;
2077 if (*this_cache == NULL)
2078 *this_cache = arm_make_prologue_cache (this_frame);
2079 cache = *this_cache;
2081 /* If we are asked to unwind the PC, then we need to return the LR
2082 instead. The prologue may save PC, but it will point into this
2083 frame's prologue, not the next frame's resume location. Also
2084 strip the saved T bit. A valid LR may have the low bit set, but
2085 a valid PC never does. */
2086 if (prev_regnum == ARM_PC_REGNUM)
2090 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2091 return frame_unwind_got_constant (this_frame, prev_regnum,
2092 arm_addr_bits_remove (gdbarch, lr));
2095 /* SP is generally not saved to the stack, but this frame is
2096 identified by the next frame's stack pointer at the time of the call.
2097 The value was already reconstructed into PREV_SP. */
2098 if (prev_regnum == ARM_SP_REGNUM)
2099 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2101 /* The CPSR may have been changed by the call instruction and by the
2102 called function. The only bit we can reconstruct is the T bit,
2103 by checking the low bit of LR as of the call. This is a reliable
2104 indicator of Thumb-ness except for some ARM v4T pre-interworking
2105 Thumb code, which could get away with a clear low bit as long as
2106 the called function did not use bx. Guess that all other
2107 bits are unchanged; the condition flags are presumably lost,
2108 but the processor status is likely valid. */
2109 if (prev_regnum == ARM_PS_REGNUM)
2112 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2114 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
2115 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2116 if (IS_THUMB_ADDR (lr))
2120 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
2123 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2127 struct frame_unwind arm_prologue_unwind = {
2129 default_frame_unwind_stop_reason,
2130 arm_prologue_this_id,
2131 arm_prologue_prev_register,
2133 default_frame_sniffer
2136 /* Maintain a list of ARM exception table entries per objfile, similar to the
2137 list of mapping symbols. We only cache entries for standard ARM-defined
2138 personality routines; the cache will contain only the frame unwinding
2139 instructions associated with the entry (not the descriptors). */
2141 static const struct objfile_data *arm_exidx_data_key;
2143 struct arm_exidx_entry
2148 typedef struct arm_exidx_entry arm_exidx_entry_s;
2149 DEF_VEC_O(arm_exidx_entry_s);
2151 struct arm_exidx_data
2153 VEC(arm_exidx_entry_s) **section_maps;
2157 arm_exidx_data_free (struct objfile *objfile, void *arg)
2159 struct arm_exidx_data *data = arg;
2162 for (i = 0; i < objfile->obfd->section_count; i++)
2163 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2167 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2168 const struct arm_exidx_entry *rhs)
2170 return lhs->addr < rhs->addr;
2173 static struct obj_section *
2174 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2176 struct obj_section *osect;
2178 ALL_OBJFILE_OSECTIONS (objfile, osect)
2179 if (bfd_get_section_flags (objfile->obfd,
2180 osect->the_bfd_section) & SEC_ALLOC)
2182 bfd_vma start, size;
2183 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2184 size = bfd_get_section_size (osect->the_bfd_section);
2186 if (start <= vma && vma < start + size)
2193 /* Parse contents of exception table and exception index sections
2194 of OBJFILE, and fill in the exception table entry cache.
2196 For each entry that refers to a standard ARM-defined personality
2197 routine, extract the frame unwinding instructions (from either
2198 the index or the table section). The unwinding instructions
2200 - extracting them from the rest of the table data
2201 - converting to host endianness
2202 - appending the implicit 0xb0 ("Finish") code
2204 The extracted and normalized instructions are stored for later
2205 retrieval by the arm_find_exidx_entry routine. */
2208 arm_exidx_new_objfile (struct objfile *objfile)
2210 struct cleanup *cleanups = make_cleanup (null_cleanup, NULL);
2211 struct arm_exidx_data *data;
2212 asection *exidx, *extab;
2213 bfd_vma exidx_vma = 0, extab_vma = 0;
2214 bfd_size_type exidx_size = 0, extab_size = 0;
2215 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2218 /* If we've already touched this file, do nothing. */
2219 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2222 /* Read contents of exception table and index. */
2223 exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2226 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2227 exidx_size = bfd_get_section_size (exidx);
2228 exidx_data = xmalloc (exidx_size);
2229 make_cleanup (xfree, exidx_data);
2231 if (!bfd_get_section_contents (objfile->obfd, exidx,
2232 exidx_data, 0, exidx_size))
2234 do_cleanups (cleanups);
2239 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2242 extab_vma = bfd_section_vma (objfile->obfd, extab);
2243 extab_size = bfd_get_section_size (extab);
2244 extab_data = xmalloc (extab_size);
2245 make_cleanup (xfree, extab_data);
2247 if (!bfd_get_section_contents (objfile->obfd, extab,
2248 extab_data, 0, extab_size))
2250 do_cleanups (cleanups);
2255 /* Allocate exception table data structure. */
2256 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2257 set_objfile_data (objfile, arm_exidx_data_key, data);
2258 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2259 objfile->obfd->section_count,
2260 VEC(arm_exidx_entry_s) *);
2262 /* Fill in exception table. */
2263 for (i = 0; i < exidx_size / 8; i++)
2265 struct arm_exidx_entry new_exidx_entry;
2266 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2267 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2268 bfd_vma addr = 0, word = 0;
2269 int n_bytes = 0, n_words = 0;
2270 struct obj_section *sec;
2271 gdb_byte *entry = NULL;
2273 /* Extract address of start of function. */
2274 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2275 idx += exidx_vma + i * 8;
2277 /* Find section containing function and compute section offset. */
2278 sec = arm_obj_section_from_vma (objfile, idx);
2281 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2283 /* Determine address of exception table entry. */
2286 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2288 else if ((val & 0xff000000) == 0x80000000)
2290 /* Exception table entry embedded in .ARM.exidx
2291 -- must be short form. */
2295 else if (!(val & 0x80000000))
2297 /* Exception table entry in .ARM.extab. */
2298 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2299 addr += exidx_vma + i * 8 + 4;
2301 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2303 word = bfd_h_get_32 (objfile->obfd,
2304 extab_data + addr - extab_vma);
2307 if ((word & 0xff000000) == 0x80000000)
2312 else if ((word & 0xff000000) == 0x81000000
2313 || (word & 0xff000000) == 0x82000000)
2317 n_words = ((word >> 16) & 0xff);
2319 else if (!(word & 0x80000000))
2322 struct obj_section *pers_sec;
2323 int gnu_personality = 0;
2325 /* Custom personality routine. */
2326 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2327 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2329 /* Check whether we've got one of the variants of the
2330 GNU personality routines. */
2331 pers_sec = arm_obj_section_from_vma (objfile, pers);
2334 static const char *personality[] =
2336 "__gcc_personality_v0",
2337 "__gxx_personality_v0",
2338 "__gcj_personality_v0",
2339 "__gnu_objc_personality_v0",
2343 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2346 for (k = 0; personality[k]; k++)
2347 if (lookup_minimal_symbol_by_pc_name
2348 (pc, personality[k], objfile))
2350 gnu_personality = 1;
2355 /* If so, the next word contains a word count in the high
2356 byte, followed by the same unwind instructions as the
2357 pre-defined forms. */
2359 && addr + 4 <= extab_vma + extab_size)
2361 word = bfd_h_get_32 (objfile->obfd,
2362 extab_data + addr - extab_vma);
2365 n_words = ((word >> 24) & 0xff);
2371 /* Sanity check address. */
2373 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2374 n_words = n_bytes = 0;
2376 /* The unwind instructions reside in WORD (only the N_BYTES least
2377 significant bytes are valid), followed by N_WORDS words in the
2378 extab section starting at ADDR. */
2379 if (n_bytes || n_words)
2381 gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2382 n_bytes + n_words * 4 + 1);
2385 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2389 word = bfd_h_get_32 (objfile->obfd,
2390 extab_data + addr - extab_vma);
2393 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2394 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2395 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2396 *p++ = (gdb_byte) (word & 0xff);
2399 /* Implied "Finish" to terminate the list. */
2403 /* Push entry onto vector. They are guaranteed to always
2404 appear in order of increasing addresses. */
2405 new_exidx_entry.addr = idx;
2406 new_exidx_entry.entry = entry;
2407 VEC_safe_push (arm_exidx_entry_s,
2408 data->section_maps[sec->the_bfd_section->index],
2412 do_cleanups (cleanups);
2415 /* Search for the exception table entry covering MEMADDR. If one is found,
2416 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2417 set *START to the start of the region covered by this entry. */
2420 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2422 struct obj_section *sec;
2424 sec = find_pc_section (memaddr);
2427 struct arm_exidx_data *data;
2428 VEC(arm_exidx_entry_s) *map;
2429 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2432 data = objfile_data (sec->objfile, arm_exidx_data_key);
2435 map = data->section_maps[sec->the_bfd_section->index];
2436 if (!VEC_empty (arm_exidx_entry_s, map))
2438 struct arm_exidx_entry *map_sym;
2440 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2441 arm_compare_exidx_entries);
2443 /* VEC_lower_bound finds the earliest ordered insertion
2444 point. If the following symbol starts at this exact
2445 address, we use that; otherwise, the preceding
2446 exception table entry covers this address. */
2447 if (idx < VEC_length (arm_exidx_entry_s, map))
2449 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2450 if (map_sym->addr == map_key.addr)
2453 *start = map_sym->addr + obj_section_addr (sec);
2454 return map_sym->entry;
2460 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2462 *start = map_sym->addr + obj_section_addr (sec);
2463 return map_sym->entry;
2472 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2473 instruction list from the ARM exception table entry ENTRY, allocate and
2474 return a prologue cache structure describing how to unwind this frame.
2476 Return NULL if the unwinding instruction list contains a "spare",
2477 "reserved" or "refuse to unwind" instruction as defined in section
2478 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2479 for the ARM Architecture" document. */
2481 static struct arm_prologue_cache *
2482 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2487 struct arm_prologue_cache *cache;
2488 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2489 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2495 /* Whenever we reload SP, we actually have to retrieve its
2496 actual value in the current frame. */
2499 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2501 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2502 vsp = get_frame_register_unsigned (this_frame, reg);
2506 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2507 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2513 /* Decode next unwind instruction. */
2516 if ((insn & 0xc0) == 0)
2518 int offset = insn & 0x3f;
2519 vsp += (offset << 2) + 4;
2521 else if ((insn & 0xc0) == 0x40)
2523 int offset = insn & 0x3f;
2524 vsp -= (offset << 2) + 4;
2526 else if ((insn & 0xf0) == 0x80)
2528 int mask = ((insn & 0xf) << 8) | *entry++;
2531 /* The special case of an all-zero mask identifies
2532 "Refuse to unwind". We return NULL to fall back
2533 to the prologue analyzer. */
2537 /* Pop registers r4..r15 under mask. */
2538 for (i = 0; i < 12; i++)
2539 if (mask & (1 << i))
2541 cache->saved_regs[4 + i].addr = vsp;
2545 /* Special-case popping SP -- we need to reload vsp. */
2546 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2549 else if ((insn & 0xf0) == 0x90)
2551 int reg = insn & 0xf;
2553 /* Reserved cases. */
2554 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2557 /* Set SP from another register and mark VSP for reload. */
2558 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2561 else if ((insn & 0xf0) == 0xa0)
2563 int count = insn & 0x7;
2564 int pop_lr = (insn & 0x8) != 0;
2567 /* Pop r4..r[4+count]. */
2568 for (i = 0; i <= count; i++)
2570 cache->saved_regs[4 + i].addr = vsp;
2574 /* If indicated by flag, pop LR as well. */
2577 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2581 else if (insn == 0xb0)
2583 /* We could only have updated PC by popping into it; if so, it
2584 will show up as address. Otherwise, copy LR into PC. */
2585 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2586 cache->saved_regs[ARM_PC_REGNUM]
2587 = cache->saved_regs[ARM_LR_REGNUM];
2592 else if (insn == 0xb1)
2594 int mask = *entry++;
2597 /* All-zero mask and mask >= 16 is "spare". */
2598 if (mask == 0 || mask >= 16)
2601 /* Pop r0..r3 under mask. */
2602 for (i = 0; i < 4; i++)
2603 if (mask & (1 << i))
2605 cache->saved_regs[i].addr = vsp;
2609 else if (insn == 0xb2)
2611 ULONGEST offset = 0;
2616 offset |= (*entry & 0x7f) << shift;
2619 while (*entry++ & 0x80);
2621 vsp += 0x204 + (offset << 2);
2623 else if (insn == 0xb3)
2625 int start = *entry >> 4;
2626 int count = (*entry++) & 0xf;
2629 /* Only registers D0..D15 are valid here. */
2630 if (start + count >= 16)
2633 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2634 for (i = 0; i <= count; i++)
2636 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2640 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2643 else if ((insn & 0xf8) == 0xb8)
2645 int count = insn & 0x7;
2648 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2649 for (i = 0; i <= count; i++)
2651 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2655 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2658 else if (insn == 0xc6)
2660 int start = *entry >> 4;
2661 int count = (*entry++) & 0xf;
2664 /* Only registers WR0..WR15 are valid. */
2665 if (start + count >= 16)
2668 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2669 for (i = 0; i <= count; i++)
2671 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2675 else if (insn == 0xc7)
2677 int mask = *entry++;
2680 /* All-zero mask and mask >= 16 is "spare". */
2681 if (mask == 0 || mask >= 16)
2684 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2685 for (i = 0; i < 4; i++)
2686 if (mask & (1 << i))
2688 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2692 else if ((insn & 0xf8) == 0xc0)
2694 int count = insn & 0x7;
2697 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2698 for (i = 0; i <= count; i++)
2700 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2704 else if (insn == 0xc8)
2706 int start = *entry >> 4;
2707 int count = (*entry++) & 0xf;
2710 /* Only registers D0..D31 are valid. */
2711 if (start + count >= 16)
2714 /* Pop VFP double-precision registers
2715 D[16+start]..D[16+start+count]. */
2716 for (i = 0; i <= count; i++)
2718 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2722 else if (insn == 0xc9)
2724 int start = *entry >> 4;
2725 int count = (*entry++) & 0xf;
2728 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2729 for (i = 0; i <= count; i++)
2731 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2735 else if ((insn & 0xf8) == 0xd0)
2737 int count = insn & 0x7;
2740 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2741 for (i = 0; i <= count; i++)
2743 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2749 /* Everything else is "spare". */
2754 /* If we restore SP from a register, assume this was the frame register.
2755 Otherwise just fall back to SP as frame register. */
2756 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2757 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2759 cache->framereg = ARM_SP_REGNUM;
2761 /* Determine offset to previous frame. */
2763 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2765 /* We already got the previous SP. */
2766 cache->prev_sp = vsp;
2771 /* Unwinding via ARM exception table entries. Note that the sniffer
2772 already computes a filled-in prologue cache, which is then used
2773 with the same arm_prologue_this_id and arm_prologue_prev_register
2774 routines also used for prologue-parsing based unwinding. */
2777 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2778 struct frame_info *this_frame,
2779 void **this_prologue_cache)
2781 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2782 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2783 CORE_ADDR addr_in_block, exidx_region, func_start;
2784 struct arm_prologue_cache *cache;
2787 /* See if we have an ARM exception table entry covering this address. */
2788 addr_in_block = get_frame_address_in_block (this_frame);
2789 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2793 /* The ARM exception table does not describe unwind information
2794 for arbitrary PC values, but is guaranteed to be correct only
2795 at call sites. We have to decide here whether we want to use
2796 ARM exception table information for this frame, or fall back
2797 to using prologue parsing. (Note that if we have DWARF CFI,
2798 this sniffer isn't even called -- CFI is always preferred.)
2800 Before we make this decision, however, we check whether we
2801 actually have *symbol* information for the current frame.
2802 If not, prologue parsing would not work anyway, so we might
2803 as well use the exception table and hope for the best. */
2804 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2808 /* If the next frame is "normal", we are at a call site in this
2809 frame, so exception information is guaranteed to be valid. */
2810 if (get_next_frame (this_frame)
2811 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2814 /* We also assume exception information is valid if we're currently
2815 blocked in a system call. The system library is supposed to
2816 ensure this, so that e.g. pthread cancellation works. */
2817 if (arm_frame_is_thumb (this_frame))
2821 if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2822 byte_order_for_code, &insn)
2823 && (insn & 0xff00) == 0xdf00 /* svc */)
2830 if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2831 byte_order_for_code, &insn)
2832 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2836 /* Bail out if we don't know that exception information is valid. */
2840 /* The ARM exception index does not mark the *end* of the region
2841 covered by the entry, and some functions will not have any entry.
2842 To correctly recognize the end of the covered region, the linker
2843 should have inserted dummy records with a CANTUNWIND marker.
2845 Unfortunately, current versions of GNU ld do not reliably do
2846 this, and thus we may have found an incorrect entry above.
2847 As a (temporary) sanity check, we only use the entry if it
2848 lies *within* the bounds of the function. Note that this check
2849 might reject perfectly valid entries that just happen to cover
2850 multiple functions; therefore this check ought to be removed
2851 once the linker is fixed. */
2852 if (func_start > exidx_region)
2856 /* Decode the list of unwinding instructions into a prologue cache.
2857 Note that this may fail due to e.g. a "refuse to unwind" code. */
2858 cache = arm_exidx_fill_cache (this_frame, entry);
2862 *this_prologue_cache = cache;
2866 struct frame_unwind arm_exidx_unwind = {
2868 default_frame_unwind_stop_reason,
2869 arm_prologue_this_id,
2870 arm_prologue_prev_register,
2872 arm_exidx_unwind_sniffer
2875 static struct arm_prologue_cache *
2876 arm_make_stub_cache (struct frame_info *this_frame)
2878 struct arm_prologue_cache *cache;
2880 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2881 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2883 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2888 /* Our frame ID for a stub frame is the current SP and LR. */
2891 arm_stub_this_id (struct frame_info *this_frame,
2893 struct frame_id *this_id)
2895 struct arm_prologue_cache *cache;
2897 if (*this_cache == NULL)
2898 *this_cache = arm_make_stub_cache (this_frame);
2899 cache = *this_cache;
2901 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2905 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2906 struct frame_info *this_frame,
2907 void **this_prologue_cache)
2909 CORE_ADDR addr_in_block;
2912 addr_in_block = get_frame_address_in_block (this_frame);
2913 if (in_plt_section (addr_in_block, NULL)
2914 /* We also use the stub winder if the target memory is unreadable
2915 to avoid having the prologue unwinder trying to read it. */
2916 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2922 struct frame_unwind arm_stub_unwind = {
2924 default_frame_unwind_stop_reason,
2926 arm_prologue_prev_register,
2928 arm_stub_unwind_sniffer
2932 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
2934 struct arm_prologue_cache *cache;
2936 if (*this_cache == NULL)
2937 *this_cache = arm_make_prologue_cache (this_frame);
2938 cache = *this_cache;
2940 return cache->prev_sp - cache->framesize;
2943 struct frame_base arm_normal_base = {
2944 &arm_prologue_unwind,
2945 arm_normal_frame_base,
2946 arm_normal_frame_base,
2947 arm_normal_frame_base
2950 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2951 dummy frame. The frame ID's base needs to match the TOS value
2952 saved by save_dummy_frame_tos() and returned from
2953 arm_push_dummy_call, and the PC needs to match the dummy frame's
2956 static struct frame_id
2957 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2959 return frame_id_build (get_frame_register_unsigned (this_frame,
2961 get_frame_pc (this_frame));
2964 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2965 be used to construct the previous frame's ID, after looking up the
2966 containing function). */
2969 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
2972 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
2973 return arm_addr_bits_remove (gdbarch, pc);
2977 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
2979 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
2982 static struct value *
2983 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
2986 struct gdbarch * gdbarch = get_frame_arch (this_frame);
2988 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
2993 /* The PC is normally copied from the return column, which
2994 describes saves of LR. However, that version may have an
2995 extra bit set to indicate Thumb state. The bit is not
2997 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
2998 return frame_unwind_got_constant (this_frame, regnum,
2999 arm_addr_bits_remove (gdbarch, lr));
3002 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3003 cpsr = get_frame_register_unsigned (this_frame, regnum);
3004 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3005 if (IS_THUMB_ADDR (lr))
3009 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3012 internal_error (__FILE__, __LINE__,
3013 _("Unexpected register %d"), regnum);
3018 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3019 struct dwarf2_frame_state_reg *reg,
3020 struct frame_info *this_frame)
3026 reg->how = DWARF2_FRAME_REG_FN;
3027 reg->loc.fn = arm_dwarf2_prev_register;
3030 reg->how = DWARF2_FRAME_REG_CFA;
3035 /* Return true if we are in the function's epilogue, i.e. after the
3036 instruction that destroyed the function's stack frame. */
3039 thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3041 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3042 unsigned int insn, insn2;
3043 int found_return = 0, found_stack_adjust = 0;
3044 CORE_ADDR func_start, func_end;
3048 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3051 /* The epilogue is a sequence of instructions along the following lines:
3053 - add stack frame size to SP or FP
3054 - [if frame pointer used] restore SP from FP
3055 - restore registers from SP [may include PC]
3056 - a return-type instruction [if PC wasn't already restored]
3058 In a first pass, we scan forward from the current PC and verify the
3059 instructions we find as compatible with this sequence, ending in a
3062 However, this is not sufficient to distinguish indirect function calls
3063 within a function from indirect tail calls in the epilogue in some cases.
3064 Therefore, if we didn't already find any SP-changing instruction during
3065 forward scan, we add a backward scanning heuristic to ensure we actually
3066 are in the epilogue. */
3069 while (scan_pc < func_end && !found_return)
3071 if (target_read_memory (scan_pc, buf, 2))
3075 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3077 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3079 else if (insn == 0x46f7) /* mov pc, lr */
3081 else if (insn == 0x46bd) /* mov sp, r7 */
3082 found_stack_adjust = 1;
3083 else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3084 found_stack_adjust = 1;
3085 else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3087 found_stack_adjust = 1;
3088 if (insn & 0x0100) /* <registers> include PC. */
3091 else if ((insn & 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */
3093 if (target_read_memory (scan_pc, buf, 2))
3097 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3099 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3101 found_stack_adjust = 1;
3102 if (insn2 & 0x8000) /* <registers> include PC. */
3105 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3106 && (insn2 & 0x0fff) == 0x0b04)
3108 found_stack_adjust = 1;
3109 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3112 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3113 && (insn2 & 0x0e00) == 0x0a00)
3114 found_stack_adjust = 1;
3125 /* Since any instruction in the epilogue sequence, with the possible
3126 exception of return itself, updates the stack pointer, we need to
3127 scan backwards for at most one instruction. Try either a 16-bit or
3128 a 32-bit instruction. This is just a heuristic, so we do not worry
3129 too much about false positives. */
3131 if (!found_stack_adjust)
3133 if (pc - 4 < func_start)
3135 if (target_read_memory (pc - 4, buf, 4))
3138 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3139 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3141 if (insn2 == 0x46bd) /* mov sp, r7 */
3142 found_stack_adjust = 1;
3143 else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3144 found_stack_adjust = 1;
3145 else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3146 found_stack_adjust = 1;
3147 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3148 found_stack_adjust = 1;
3149 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3150 && (insn2 & 0x0fff) == 0x0b04)
3151 found_stack_adjust = 1;
3152 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3153 && (insn2 & 0x0e00) == 0x0a00)
3154 found_stack_adjust = 1;
3157 return found_stack_adjust;
3160 /* Return true if we are in the function's epilogue, i.e. after the
3161 instruction that destroyed the function's stack frame. */
3164 arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3166 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3168 int found_return, found_stack_adjust;
3169 CORE_ADDR func_start, func_end;
3171 if (arm_pc_is_thumb (gdbarch, pc))
3172 return thumb_in_function_epilogue_p (gdbarch, pc);
3174 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3177 /* We are in the epilogue if the previous instruction was a stack
3178 adjustment and the next instruction is a possible return (bx, mov
3179 pc, or pop). We could have to scan backwards to find the stack
3180 adjustment, or forwards to find the return, but this is a decent
3181 approximation. First scan forwards. */
3184 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3185 if (bits (insn, 28, 31) != INST_NV)
3187 if ((insn & 0x0ffffff0) == 0x012fff10)
3190 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3193 else if ((insn & 0x0fff0000) == 0x08bd0000
3194 && (insn & 0x0000c000) != 0)
3195 /* POP (LDMIA), including PC or LR. */
3202 /* Scan backwards. This is just a heuristic, so do not worry about
3203 false positives from mode changes. */
3205 if (pc < func_start + 4)
3208 found_stack_adjust = 0;
3209 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3210 if (bits (insn, 28, 31) != INST_NV)
3212 if ((insn & 0x0df0f000) == 0x0080d000)
3213 /* ADD SP (register or immediate). */
3214 found_stack_adjust = 1;
3215 else if ((insn & 0x0df0f000) == 0x0040d000)
3216 /* SUB SP (register or immediate). */
3217 found_stack_adjust = 1;
3218 else if ((insn & 0x0ffffff0) == 0x01a0d000)
3220 found_stack_adjust = 1;
3221 else if ((insn & 0x0fff0000) == 0x08bd0000)
3223 found_stack_adjust = 1;
3226 if (found_stack_adjust)
3233 /* When arguments must be pushed onto the stack, they go on in reverse
3234 order. The code below implements a FILO (stack) to do this. */
3239 struct stack_item *prev;
3243 static struct stack_item *
3244 push_stack_item (struct stack_item *prev, const void *contents, int len)
3246 struct stack_item *si;
3247 si = xmalloc (sizeof (struct stack_item));
3248 si->data = xmalloc (len);
3251 memcpy (si->data, contents, len);
3255 static struct stack_item *
3256 pop_stack_item (struct stack_item *si)
3258 struct stack_item *dead = si;
3266 /* Return the alignment (in bytes) of the given type. */
3269 arm_type_align (struct type *t)
3275 t = check_typedef (t);
3276 switch (TYPE_CODE (t))
3279 /* Should never happen. */
3280 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3284 case TYPE_CODE_ENUM:
3288 case TYPE_CODE_RANGE:
3289 case TYPE_CODE_BITSTRING:
3291 case TYPE_CODE_CHAR:
3292 case TYPE_CODE_BOOL:
3293 return TYPE_LENGTH (t);
3295 case TYPE_CODE_ARRAY:
3296 case TYPE_CODE_COMPLEX:
3297 /* TODO: What about vector types? */
3298 return arm_type_align (TYPE_TARGET_TYPE (t));
3300 case TYPE_CODE_STRUCT:
3301 case TYPE_CODE_UNION:
3303 for (n = 0; n < TYPE_NFIELDS (t); n++)
3305 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3313 /* Possible base types for a candidate for passing and returning in
3316 enum arm_vfp_cprc_base_type
3325 /* The length of one element of base type B. */
3328 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3332 case VFP_CPRC_SINGLE:
3334 case VFP_CPRC_DOUBLE:
3336 case VFP_CPRC_VEC64:
3338 case VFP_CPRC_VEC128:
3341 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3346 /* The character ('s', 'd' or 'q') for the type of VFP register used
3347 for passing base type B. */
3350 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3354 case VFP_CPRC_SINGLE:
3356 case VFP_CPRC_DOUBLE:
3358 case VFP_CPRC_VEC64:
3360 case VFP_CPRC_VEC128:
3363 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3368 /* Determine whether T may be part of a candidate for passing and
3369 returning in VFP registers, ignoring the limit on the total number
3370 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3371 classification of the first valid component found; if it is not
3372 VFP_CPRC_UNKNOWN, all components must have the same classification
3373 as *BASE_TYPE. If it is found that T contains a type not permitted
3374 for passing and returning in VFP registers, a type differently
3375 classified from *BASE_TYPE, or two types differently classified
3376 from each other, return -1, otherwise return the total number of
3377 base-type elements found (possibly 0 in an empty structure or
3378 array). Vectors and complex types are not currently supported,
3379 matching the generic AAPCS support. */
3382 arm_vfp_cprc_sub_candidate (struct type *t,
3383 enum arm_vfp_cprc_base_type *base_type)
3385 t = check_typedef (t);
3386 switch (TYPE_CODE (t))
3389 switch (TYPE_LENGTH (t))
3392 if (*base_type == VFP_CPRC_UNKNOWN)
3393 *base_type = VFP_CPRC_SINGLE;
3394 else if (*base_type != VFP_CPRC_SINGLE)
3399 if (*base_type == VFP_CPRC_UNKNOWN)
3400 *base_type = VFP_CPRC_DOUBLE;
3401 else if (*base_type != VFP_CPRC_DOUBLE)
3410 case TYPE_CODE_ARRAY:
3414 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
3417 if (TYPE_LENGTH (t) == 0)
3419 gdb_assert (count == 0);
3422 else if (count == 0)
3424 unitlen = arm_vfp_cprc_unit_length (*base_type);
3425 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3426 return TYPE_LENGTH (t) / unitlen;
3430 case TYPE_CODE_STRUCT:
3435 for (i = 0; i < TYPE_NFIELDS (t); i++)
3437 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3439 if (sub_count == -1)
3443 if (TYPE_LENGTH (t) == 0)
3445 gdb_assert (count == 0);
3448 else if (count == 0)
3450 unitlen = arm_vfp_cprc_unit_length (*base_type);
3451 if (TYPE_LENGTH (t) != unitlen * count)
3456 case TYPE_CODE_UNION:
3461 for (i = 0; i < TYPE_NFIELDS (t); i++)
3463 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3465 if (sub_count == -1)
3467 count = (count > sub_count ? count : sub_count);
3469 if (TYPE_LENGTH (t) == 0)
3471 gdb_assert (count == 0);
3474 else if (count == 0)
3476 unitlen = arm_vfp_cprc_unit_length (*base_type);
3477 if (TYPE_LENGTH (t) != unitlen * count)
3489 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3490 if passed to or returned from a non-variadic function with the VFP
3491 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3492 *BASE_TYPE to the base type for T and *COUNT to the number of
3493 elements of that base type before returning. */
3496 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3499 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3500 int c = arm_vfp_cprc_sub_candidate (t, &b);
3501 if (c <= 0 || c > 4)
3508 /* Return 1 if the VFP ABI should be used for passing arguments to and
3509 returning values from a function of type FUNC_TYPE, 0
3513 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3515 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3516 /* Variadic functions always use the base ABI. Assume that functions
3517 without debug info are not variadic. */
3518 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3520 /* The VFP ABI is only supported as a variant of AAPCS. */
3521 if (tdep->arm_abi != ARM_ABI_AAPCS)
3523 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3526 /* We currently only support passing parameters in integer registers, which
3527 conforms with GCC's default model, and VFP argument passing following
3528 the VFP variant of AAPCS. Several other variants exist and
3529 we should probably support some of them based on the selected ABI. */
3532 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3533 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3534 struct value **args, CORE_ADDR sp, int struct_return,
3535 CORE_ADDR struct_addr)
3537 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3541 struct stack_item *si = NULL;
3544 unsigned vfp_regs_free = (1 << 16) - 1;
3546 /* Determine the type of this function and whether the VFP ABI
3548 ftype = check_typedef (value_type (function));
3549 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3550 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3551 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3553 /* Set the return address. For the ARM, the return breakpoint is
3554 always at BP_ADDR. */
3555 if (arm_pc_is_thumb (gdbarch, bp_addr))
3557 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3559 /* Walk through the list of args and determine how large a temporary
3560 stack is required. Need to take care here as structs may be
3561 passed on the stack, and we have to push them. */
3564 argreg = ARM_A1_REGNUM;
3567 /* The struct_return pointer occupies the first parameter
3568 passing register. */
3572 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3573 gdbarch_register_name (gdbarch, argreg),
3574 paddress (gdbarch, struct_addr));
3575 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3579 for (argnum = 0; argnum < nargs; argnum++)
3582 struct type *arg_type;
3583 struct type *target_type;
3584 enum type_code typecode;
3585 const bfd_byte *val;
3587 enum arm_vfp_cprc_base_type vfp_base_type;
3589 int may_use_core_reg = 1;
3591 arg_type = check_typedef (value_type (args[argnum]));
3592 len = TYPE_LENGTH (arg_type);
3593 target_type = TYPE_TARGET_TYPE (arg_type);
3594 typecode = TYPE_CODE (arg_type);
3595 val = value_contents (args[argnum]);
3597 align = arm_type_align (arg_type);
3598 /* Round alignment up to a whole number of words. */
3599 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3600 /* Different ABIs have different maximum alignments. */
3601 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3603 /* The APCS ABI only requires word alignment. */
3604 align = INT_REGISTER_SIZE;
3608 /* The AAPCS requires at most doubleword alignment. */
3609 if (align > INT_REGISTER_SIZE * 2)
3610 align = INT_REGISTER_SIZE * 2;
3614 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3622 /* Because this is a CPRC it cannot go in a core register or
3623 cause a core register to be skipped for alignment.
3624 Either it goes in VFP registers and the rest of this loop
3625 iteration is skipped for this argument, or it goes on the
3626 stack (and the stack alignment code is correct for this
3628 may_use_core_reg = 0;
3630 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3631 shift = unit_length / 4;
3632 mask = (1 << (shift * vfp_base_count)) - 1;
3633 for (regno = 0; regno < 16; regno += shift)
3634 if (((vfp_regs_free >> regno) & mask) == mask)
3643 vfp_regs_free &= ~(mask << regno);
3644 reg_scaled = regno / shift;
3645 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3646 for (i = 0; i < vfp_base_count; i++)
3650 if (reg_char == 'q')
3651 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3652 val + i * unit_length);
3655 sprintf (name_buf, "%c%d", reg_char, reg_scaled + i);
3656 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3658 regcache_cooked_write (regcache, regnum,
3659 val + i * unit_length);
3666 /* This CPRC could not go in VFP registers, so all VFP
3667 registers are now marked as used. */
3672 /* Push stack padding for dowubleword alignment. */
3673 if (nstack & (align - 1))
3675 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3676 nstack += INT_REGISTER_SIZE;
3679 /* Doubleword aligned quantities must go in even register pairs. */
3680 if (may_use_core_reg
3681 && argreg <= ARM_LAST_ARG_REGNUM
3682 && align > INT_REGISTER_SIZE
3686 /* If the argument is a pointer to a function, and it is a
3687 Thumb function, create a LOCAL copy of the value and set
3688 the THUMB bit in it. */
3689 if (TYPE_CODE_PTR == typecode
3690 && target_type != NULL
3691 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3693 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3694 if (arm_pc_is_thumb (gdbarch, regval))
3696 bfd_byte *copy = alloca (len);
3697 store_unsigned_integer (copy, len, byte_order,
3698 MAKE_THUMB_ADDR (regval));
3703 /* Copy the argument to general registers or the stack in
3704 register-sized pieces. Large arguments are split between
3705 registers and stack. */
3708 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3710 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3712 /* The argument is being passed in a general purpose
3715 = extract_unsigned_integer (val, partial_len, byte_order);
3716 if (byte_order == BFD_ENDIAN_BIG)
3717 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3719 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3721 gdbarch_register_name
3723 phex (regval, INT_REGISTER_SIZE));
3724 regcache_cooked_write_unsigned (regcache, argreg, regval);
3729 /* Push the arguments onto the stack. */
3731 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3733 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3734 nstack += INT_REGISTER_SIZE;
3741 /* If we have an odd number of words to push, then decrement the stack
3742 by one word now, so first stack argument will be dword aligned. */
3749 write_memory (sp, si->data, si->len);
3750 si = pop_stack_item (si);
3753 /* Finally, update teh SP register. */
3754 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3760 /* Always align the frame to an 8-byte boundary. This is required on
3761 some platforms and harmless on the rest. */
3764 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3766 /* Align the stack to eight bytes. */
3767 return sp & ~ (CORE_ADDR) 7;
3771 print_fpu_flags (int flags)
3773 if (flags & (1 << 0))
3774 fputs ("IVO ", stdout);
3775 if (flags & (1 << 1))
3776 fputs ("DVZ ", stdout);
3777 if (flags & (1 << 2))
3778 fputs ("OFL ", stdout);
3779 if (flags & (1 << 3))
3780 fputs ("UFL ", stdout);
3781 if (flags & (1 << 4))
3782 fputs ("INX ", stdout);
3786 /* Print interesting information about the floating point processor
3787 (if present) or emulator. */
3789 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3790 struct frame_info *frame, const char *args)
3792 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3795 type = (status >> 24) & 127;
3796 if (status & (1 << 31))
3797 printf (_("Hardware FPU type %d\n"), type);
3799 printf (_("Software FPU type %d\n"), type);
3800 /* i18n: [floating point unit] mask */
3801 fputs (_("mask: "), stdout);
3802 print_fpu_flags (status >> 16);
3803 /* i18n: [floating point unit] flags */
3804 fputs (_("flags: "), stdout);
3805 print_fpu_flags (status);
3808 /* Construct the ARM extended floating point type. */
3809 static struct type *
3810 arm_ext_type (struct gdbarch *gdbarch)
3812 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3814 if (!tdep->arm_ext_type)
3816 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3817 floatformats_arm_ext);
3819 return tdep->arm_ext_type;
3822 static struct type *
3823 arm_neon_double_type (struct gdbarch *gdbarch)
3825 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3827 if (tdep->neon_double_type == NULL)
3829 struct type *t, *elem;
3831 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
3833 elem = builtin_type (gdbarch)->builtin_uint8;
3834 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
3835 elem = builtin_type (gdbarch)->builtin_uint16;
3836 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
3837 elem = builtin_type (gdbarch)->builtin_uint32;
3838 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
3839 elem = builtin_type (gdbarch)->builtin_uint64;
3840 append_composite_type_field (t, "u64", elem);
3841 elem = builtin_type (gdbarch)->builtin_float;
3842 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
3843 elem = builtin_type (gdbarch)->builtin_double;
3844 append_composite_type_field (t, "f64", elem);
3846 TYPE_VECTOR (t) = 1;
3847 TYPE_NAME (t) = "neon_d";
3848 tdep->neon_double_type = t;
3851 return tdep->neon_double_type;
3854 /* FIXME: The vector types are not correctly ordered on big-endian
3855 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3856 bits of d0 - regardless of what unit size is being held in d0. So
3857 the offset of the first uint8 in d0 is 7, but the offset of the
3858 first float is 4. This code works as-is for little-endian
3861 static struct type *
3862 arm_neon_quad_type (struct gdbarch *gdbarch)
3864 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3866 if (tdep->neon_quad_type == NULL)
3868 struct type *t, *elem;
3870 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
3872 elem = builtin_type (gdbarch)->builtin_uint8;
3873 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
3874 elem = builtin_type (gdbarch)->builtin_uint16;
3875 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
3876 elem = builtin_type (gdbarch)->builtin_uint32;
3877 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
3878 elem = builtin_type (gdbarch)->builtin_uint64;
3879 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
3880 elem = builtin_type (gdbarch)->builtin_float;
3881 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
3882 elem = builtin_type (gdbarch)->builtin_double;
3883 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
3885 TYPE_VECTOR (t) = 1;
3886 TYPE_NAME (t) = "neon_q";
3887 tdep->neon_quad_type = t;
3890 return tdep->neon_quad_type;
3893 /* Return the GDB type object for the "standard" data type of data in
3896 static struct type *
3897 arm_register_type (struct gdbarch *gdbarch, int regnum)
3899 int num_regs = gdbarch_num_regs (gdbarch);
3901 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
3902 && regnum >= num_regs && regnum < num_regs + 32)
3903 return builtin_type (gdbarch)->builtin_float;
3905 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
3906 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
3907 return arm_neon_quad_type (gdbarch);
3909 /* If the target description has register information, we are only
3910 in this function so that we can override the types of
3911 double-precision registers for NEON. */
3912 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
3914 struct type *t = tdesc_register_type (gdbarch, regnum);
3916 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
3917 && TYPE_CODE (t) == TYPE_CODE_FLT
3918 && gdbarch_tdep (gdbarch)->have_neon)
3919 return arm_neon_double_type (gdbarch);
3924 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
3926 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
3927 return builtin_type (gdbarch)->builtin_void;
3929 return arm_ext_type (gdbarch);
3931 else if (regnum == ARM_SP_REGNUM)
3932 return builtin_type (gdbarch)->builtin_data_ptr;
3933 else if (regnum == ARM_PC_REGNUM)
3934 return builtin_type (gdbarch)->builtin_func_ptr;
3935 else if (regnum >= ARRAY_SIZE (arm_register_names))
3936 /* These registers are only supported on targets which supply
3937 an XML description. */
3938 return builtin_type (gdbarch)->builtin_int0;
3940 return builtin_type (gdbarch)->builtin_uint32;
3943 /* Map a DWARF register REGNUM onto the appropriate GDB register
3947 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3949 /* Core integer regs. */
3950 if (reg >= 0 && reg <= 15)
3953 /* Legacy FPA encoding. These were once used in a way which
3954 overlapped with VFP register numbering, so their use is
3955 discouraged, but GDB doesn't support the ARM toolchain
3956 which used them for VFP. */
3957 if (reg >= 16 && reg <= 23)
3958 return ARM_F0_REGNUM + reg - 16;
3960 /* New assignments for the FPA registers. */
3961 if (reg >= 96 && reg <= 103)
3962 return ARM_F0_REGNUM + reg - 96;
3964 /* WMMX register assignments. */
3965 if (reg >= 104 && reg <= 111)
3966 return ARM_WCGR0_REGNUM + reg - 104;
3968 if (reg >= 112 && reg <= 127)
3969 return ARM_WR0_REGNUM + reg - 112;
3971 if (reg >= 192 && reg <= 199)
3972 return ARM_WC0_REGNUM + reg - 192;
3974 /* VFP v2 registers. A double precision value is actually
3975 in d1 rather than s2, but the ABI only defines numbering
3976 for the single precision registers. This will "just work"
3977 in GDB for little endian targets (we'll read eight bytes,
3978 starting in s0 and then progressing to s1), but will be
3979 reversed on big endian targets with VFP. This won't
3980 be a problem for the new Neon quad registers; you're supposed
3981 to use DW_OP_piece for those. */
3982 if (reg >= 64 && reg <= 95)
3986 sprintf (name_buf, "s%d", reg - 64);
3987 return user_reg_map_name_to_regnum (gdbarch, name_buf,
3991 /* VFP v3 / Neon registers. This range is also used for VFP v2
3992 registers, except that it now describes d0 instead of s0. */
3993 if (reg >= 256 && reg <= 287)
3997 sprintf (name_buf, "d%d", reg - 256);
3998 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4005 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4007 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4010 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4012 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4013 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4015 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4016 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4018 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4019 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4021 if (reg < NUM_GREGS)
4022 return SIM_ARM_R0_REGNUM + reg;
4025 if (reg < NUM_FREGS)
4026 return SIM_ARM_FP0_REGNUM + reg;
4029 if (reg < NUM_SREGS)
4030 return SIM_ARM_FPS_REGNUM + reg;
4033 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4036 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4037 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4038 It is thought that this is is the floating-point register format on
4039 little-endian systems. */
4042 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4043 void *dbl, int endianess)
4047 if (endianess == BFD_ENDIAN_BIG)
4048 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4050 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4052 floatformat_from_doublest (fmt, &d, dbl);
4056 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4061 floatformat_to_doublest (fmt, ptr, &d);
4062 if (endianess == BFD_ENDIAN_BIG)
4063 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4065 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4070 condition_true (unsigned long cond, unsigned long status_reg)
4072 if (cond == INST_AL || cond == INST_NV)
4078 return ((status_reg & FLAG_Z) != 0);
4080 return ((status_reg & FLAG_Z) == 0);
4082 return ((status_reg & FLAG_C) != 0);
4084 return ((status_reg & FLAG_C) == 0);
4086 return ((status_reg & FLAG_N) != 0);
4088 return ((status_reg & FLAG_N) == 0);
4090 return ((status_reg & FLAG_V) != 0);
4092 return ((status_reg & FLAG_V) == 0);
4094 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4096 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4098 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4100 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4102 return (((status_reg & FLAG_Z) == 0)
4103 && (((status_reg & FLAG_N) == 0)
4104 == ((status_reg & FLAG_V) == 0)));
4106 return (((status_reg & FLAG_Z) != 0)
4107 || (((status_reg & FLAG_N) == 0)
4108 != ((status_reg & FLAG_V) == 0)));
4113 static unsigned long
4114 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
4115 unsigned long pc_val, unsigned long status_reg)
4117 unsigned long res, shift;
4118 int rm = bits (inst, 0, 3);
4119 unsigned long shifttype = bits (inst, 5, 6);
4123 int rs = bits (inst, 8, 11);
4124 shift = (rs == 15 ? pc_val + 8
4125 : get_frame_register_unsigned (frame, rs)) & 0xFF;
4128 shift = bits (inst, 7, 11);
4130 res = (rm == ARM_PC_REGNUM
4131 ? (pc_val + (bit (inst, 4) ? 12 : 8))
4132 : get_frame_register_unsigned (frame, rm));
4137 res = shift >= 32 ? 0 : res << shift;
4141 res = shift >= 32 ? 0 : res >> shift;
4147 res = ((res & 0x80000000L)
4148 ? ~((~res) >> shift) : res >> shift);
4151 case 3: /* ROR/RRX */
4154 res = (res >> 1) | (carry ? 0x80000000L : 0);
4156 res = (res >> shift) | (res << (32 - shift));
4160 return res & 0xffffffff;
4163 /* Return number of 1-bits in VAL. */
4166 bitcount (unsigned long val)
4169 for (nbits = 0; val != 0; nbits++)
4170 val &= val - 1; /* Delete rightmost 1-bit in val. */
4174 /* Return the size in bytes of the complete Thumb instruction whose
4175 first halfword is INST1. */
4178 thumb_insn_size (unsigned short inst1)
4180 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4187 thumb_advance_itstate (unsigned int itstate)
4189 /* Preserve IT[7:5], the first three bits of the condition. Shift
4190 the upcoming condition flags left by one bit. */
4191 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4193 /* If we have finished the IT block, clear the state. */
4194 if ((itstate & 0x0f) == 0)
4200 /* Find the next PC after the current instruction executes. In some
4201 cases we can not statically determine the answer (see the IT state
4202 handling in this function); in that case, a breakpoint may be
4203 inserted in addition to the returned PC, which will be used to set
4204 another breakpoint by our caller. */
4207 thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4209 struct gdbarch *gdbarch = get_frame_arch (frame);
4210 struct address_space *aspace = get_frame_address_space (frame);
4211 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4212 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4213 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
4214 unsigned short inst1;
4215 CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
4216 unsigned long offset;
4217 ULONGEST status, itstate;
4219 nextpc = MAKE_THUMB_ADDR (nextpc);
4220 pc_val = MAKE_THUMB_ADDR (pc_val);
4222 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
4224 /* Thumb-2 conditional execution support. There are eight bits in
4225 the CPSR which describe conditional execution state. Once
4226 reconstructed (they're in a funny order), the low five bits
4227 describe the low bit of the condition for each instruction and
4228 how many instructions remain. The high three bits describe the
4229 base condition. One of the low four bits will be set if an IT
4230 block is active. These bits read as zero on earlier
4232 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4233 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4235 /* If-Then handling. On GNU/Linux, where this routine is used, we
4236 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4237 can disable execution of the undefined instruction. So we might
4238 miss the breakpoint if we set it on a skipped conditional
4239 instruction. Because conditional instructions can change the
4240 flags, affecting the execution of further instructions, we may
4241 need to set two breakpoints. */
4243 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL)
4245 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4247 /* An IT instruction. Because this instruction does not
4248 modify the flags, we can accurately predict the next
4249 executed instruction. */
4250 itstate = inst1 & 0x00ff;
4251 pc += thumb_insn_size (inst1);
4253 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4255 inst1 = read_memory_unsigned_integer (pc, 2,
4256 byte_order_for_code);
4257 pc += thumb_insn_size (inst1);
4258 itstate = thumb_advance_itstate (itstate);
4261 return MAKE_THUMB_ADDR (pc);
4263 else if (itstate != 0)
4265 /* We are in a conditional block. Check the condition. */
4266 if (! condition_true (itstate >> 4, status))
4268 /* Advance to the next executed instruction. */
4269 pc += thumb_insn_size (inst1);
4270 itstate = thumb_advance_itstate (itstate);
4272 while (itstate != 0 && ! condition_true (itstate >> 4, status))
4274 inst1 = read_memory_unsigned_integer (pc, 2,
4275 byte_order_for_code);
4276 pc += thumb_insn_size (inst1);
4277 itstate = thumb_advance_itstate (itstate);
4280 return MAKE_THUMB_ADDR (pc);
4282 else if ((itstate & 0x0f) == 0x08)
4284 /* This is the last instruction of the conditional
4285 block, and it is executed. We can handle it normally
4286 because the following instruction is not conditional,
4287 and we must handle it normally because it is
4288 permitted to branch. Fall through. */
4294 /* There are conditional instructions after this one.
4295 If this instruction modifies the flags, then we can
4296 not predict what the next executed instruction will
4297 be. Fortunately, this instruction is architecturally
4298 forbidden to branch; we know it will fall through.
4299 Start by skipping past it. */
4300 pc += thumb_insn_size (inst1);
4301 itstate = thumb_advance_itstate (itstate);
4303 /* Set a breakpoint on the following instruction. */
4304 gdb_assert ((itstate & 0x0f) != 0);
4305 arm_insert_single_step_breakpoint (gdbarch, aspace,
4306 MAKE_THUMB_ADDR (pc));
4307 cond_negated = (itstate >> 4) & 1;
4309 /* Skip all following instructions with the same
4310 condition. If there is a later instruction in the IT
4311 block with the opposite condition, set the other
4312 breakpoint there. If not, then set a breakpoint on
4313 the instruction after the IT block. */
4316 inst1 = read_memory_unsigned_integer (pc, 2,
4317 byte_order_for_code);
4318 pc += thumb_insn_size (inst1);
4319 itstate = thumb_advance_itstate (itstate);
4321 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4323 return MAKE_THUMB_ADDR (pc);
4327 else if (itstate & 0x0f)
4329 /* We are in a conditional block. Check the condition. */
4330 int cond = itstate >> 4;
4332 if (! condition_true (cond, status))
4334 /* Advance to the next instruction. All the 32-bit
4335 instructions share a common prefix. */
4336 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4337 return MAKE_THUMB_ADDR (pc + 4);
4339 return MAKE_THUMB_ADDR (pc + 2);
4342 /* Otherwise, handle the instruction normally. */
4345 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
4349 /* Fetch the saved PC from the stack. It's stored above
4350 all of the other registers. */
4351 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
4352 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
4353 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
4355 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
4357 unsigned long cond = bits (inst1, 8, 11);
4358 if (cond == 0x0f) /* 0x0f = SWI */
4360 struct gdbarch_tdep *tdep;
4361 tdep = gdbarch_tdep (gdbarch);
4363 if (tdep->syscall_next_pc != NULL)
4364 nextpc = tdep->syscall_next_pc (frame);
4367 else if (cond != 0x0f && condition_true (cond, status))
4368 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
4370 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
4372 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
4374 else if ((inst1 & 0xe000) == 0xe000) /* 32-bit instruction */
4376 unsigned short inst2;
4377 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
4379 /* Default to the next instruction. */
4381 nextpc = MAKE_THUMB_ADDR (nextpc);
4383 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4385 /* Branches and miscellaneous control instructions. */
4387 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4390 int j1, j2, imm1, imm2;
4392 imm1 = sbits (inst1, 0, 10);
4393 imm2 = bits (inst2, 0, 10);
4394 j1 = bit (inst2, 13);
4395 j2 = bit (inst2, 11);
4397 offset = ((imm1 << 12) + (imm2 << 1));
4398 offset ^= ((!j2) << 22) | ((!j1) << 23);
4400 nextpc = pc_val + offset;
4401 /* For BLX make sure to clear the low bits. */
4402 if (bit (inst2, 12) == 0)
4403 nextpc = nextpc & 0xfffffffc;
4405 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4407 /* SUBS PC, LR, #imm8. */
4408 nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM);
4409 nextpc -= inst2 & 0x00ff;
4411 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4413 /* Conditional branch. */
4414 if (condition_true (bits (inst1, 6, 9), status))
4416 int sign, j1, j2, imm1, imm2;
4418 sign = sbits (inst1, 10, 10);
4419 imm1 = bits (inst1, 0, 5);
4420 imm2 = bits (inst2, 0, 10);
4421 j1 = bit (inst2, 13);
4422 j2 = bit (inst2, 11);
4424 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4425 offset += (imm1 << 12) + (imm2 << 1);
4427 nextpc = pc_val + offset;
4431 else if ((inst1 & 0xfe50) == 0xe810)
4433 /* Load multiple or RFE. */
4434 int rn, offset, load_pc = 1;
4436 rn = bits (inst1, 0, 3);
4437 if (bit (inst1, 7) && !bit (inst1, 8))
4440 if (!bit (inst2, 15))
4442 offset = bitcount (inst2) * 4 - 4;
4444 else if (!bit (inst1, 7) && bit (inst1, 8))
4447 if (!bit (inst2, 15))
4451 else if (bit (inst1, 7) && bit (inst1, 8))
4456 else if (!bit (inst1, 7) && !bit (inst1, 8))
4466 CORE_ADDR addr = get_frame_register_unsigned (frame, rn);
4467 nextpc = get_frame_memory_unsigned (frame, addr + offset, 4);
4470 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4472 /* MOV PC or MOVS PC. */
4473 nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4474 nextpc = MAKE_THUMB_ADDR (nextpc);
4476 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4480 int rn, load_pc = 1;
4482 rn = bits (inst1, 0, 3);
4483 base = get_frame_register_unsigned (frame, rn);
4484 if (rn == ARM_PC_REGNUM)
4486 base = (base + 4) & ~(CORE_ADDR) 0x3;
4488 base += bits (inst2, 0, 11);
4490 base -= bits (inst2, 0, 11);
4492 else if (bit (inst1, 7))
4493 base += bits (inst2, 0, 11);
4494 else if (bit (inst2, 11))
4496 if (bit (inst2, 10))
4499 base += bits (inst2, 0, 7);
4501 base -= bits (inst2, 0, 7);
4504 else if ((inst2 & 0x0fc0) == 0x0000)
4506 int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3);
4507 base += get_frame_register_unsigned (frame, rm) << shift;
4514 nextpc = get_frame_memory_unsigned (frame, base, 4);
4516 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4519 CORE_ADDR tbl_reg, table, offset, length;
4521 tbl_reg = bits (inst1, 0, 3);
4522 if (tbl_reg == 0x0f)
4523 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4525 table = get_frame_register_unsigned (frame, tbl_reg);
4527 offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4528 length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
4529 nextpc = pc_val + length;
4531 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4534 CORE_ADDR tbl_reg, table, offset, length;
4536 tbl_reg = bits (inst1, 0, 3);
4537 if (tbl_reg == 0x0f)
4538 table = pc + 4; /* Regcache copy of PC isn't right yet. */
4540 table = get_frame_register_unsigned (frame, tbl_reg);
4542 offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
4543 length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
4544 nextpc = pc_val + length;
4547 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
4549 if (bits (inst1, 3, 6) == 0x0f)
4552 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4554 else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4556 if (bits (inst1, 3, 6) == 0x0f)
4559 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4561 nextpc = MAKE_THUMB_ADDR (nextpc);
4563 else if ((inst1 & 0xf500) == 0xb100)
4566 int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1);
4567 ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2));
4569 if (bit (inst1, 11) && reg != 0)
4570 nextpc = pc_val + imm;
4571 else if (!bit (inst1, 11) && reg == 0)
4572 nextpc = pc_val + imm;
4577 /* Get the raw next address. PC is the current program counter, in
4578 FRAME, which is assumed to be executing in ARM mode.
4580 The value returned has the execution state of the next instruction
4581 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4582 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4586 arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc)
4588 struct gdbarch *gdbarch = get_frame_arch (frame);
4589 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4590 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
4591 unsigned long pc_val;
4592 unsigned long this_instr;
4593 unsigned long status;
4596 pc_val = (unsigned long) pc;
4597 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
4599 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
4600 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
4602 if (bits (this_instr, 28, 31) == INST_NV)
4603 switch (bits (this_instr, 24, 27))
4608 /* Branch with Link and change to Thumb. */
4609 nextpc = BranchDest (pc, this_instr);
4610 nextpc |= bit (this_instr, 24) << 1;
4611 nextpc = MAKE_THUMB_ADDR (nextpc);
4617 /* Coprocessor register transfer. */
4618 if (bits (this_instr, 12, 15) == 15)
4619 error (_("Invalid update to pc in instruction"));
4622 else if (condition_true (bits (this_instr, 28, 31), status))
4624 switch (bits (this_instr, 24, 27))
4627 case 0x1: /* data processing */
4631 unsigned long operand1, operand2, result = 0;
4635 if (bits (this_instr, 12, 15) != 15)
4638 if (bits (this_instr, 22, 25) == 0
4639 && bits (this_instr, 4, 7) == 9) /* multiply */
4640 error (_("Invalid update to pc in instruction"));
4642 /* BX <reg>, BLX <reg> */
4643 if (bits (this_instr, 4, 27) == 0x12fff1
4644 || bits (this_instr, 4, 27) == 0x12fff3)
4646 rn = bits (this_instr, 0, 3);
4647 nextpc = ((rn == ARM_PC_REGNUM)
4649 : get_frame_register_unsigned (frame, rn));
4654 /* Multiply into PC. */
4655 c = (status & FLAG_C) ? 1 : 0;
4656 rn = bits (this_instr, 16, 19);
4657 operand1 = ((rn == ARM_PC_REGNUM)
4659 : get_frame_register_unsigned (frame, rn));
4661 if (bit (this_instr, 25))
4663 unsigned long immval = bits (this_instr, 0, 7);
4664 unsigned long rotate = 2 * bits (this_instr, 8, 11);
4665 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4668 else /* operand 2 is a shifted register. */
4669 operand2 = shifted_reg_val (frame, this_instr, c,
4672 switch (bits (this_instr, 21, 24))
4675 result = operand1 & operand2;
4679 result = operand1 ^ operand2;
4683 result = operand1 - operand2;
4687 result = operand2 - operand1;
4691 result = operand1 + operand2;
4695 result = operand1 + operand2 + c;
4699 result = operand1 - operand2 + c;
4703 result = operand2 - operand1 + c;
4709 case 0xb: /* tst, teq, cmp, cmn */
4710 result = (unsigned long) nextpc;
4714 result = operand1 | operand2;
4718 /* Always step into a function. */
4723 result = operand1 & ~operand2;
4731 /* In 26-bit APCS the bottom two bits of the result are
4732 ignored, and we always end up in ARM state. */
4734 nextpc = arm_addr_bits_remove (gdbarch, result);
4742 case 0x5: /* data transfer */
4745 if (bit (this_instr, 20))
4748 if (bits (this_instr, 12, 15) == 15)
4754 if (bit (this_instr, 22))
4755 error (_("Invalid update to pc in instruction"));
4757 /* byte write to PC */
4758 rn = bits (this_instr, 16, 19);
4759 base = ((rn == ARM_PC_REGNUM)
4761 : get_frame_register_unsigned (frame, rn));
4763 if (bit (this_instr, 24))
4766 int c = (status & FLAG_C) ? 1 : 0;
4767 unsigned long offset =
4768 (bit (this_instr, 25)
4769 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
4770 : bits (this_instr, 0, 11));
4772 if (bit (this_instr, 23))
4777 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
4784 case 0x9: /* block transfer */
4785 if (bit (this_instr, 20))
4788 if (bit (this_instr, 15))
4793 if (bit (this_instr, 23))
4796 unsigned long reglist = bits (this_instr, 0, 14);
4797 offset = bitcount (reglist) * 4;
4798 if (bit (this_instr, 24)) /* pre */
4801 else if (bit (this_instr, 24))
4805 unsigned long rn_val =
4806 get_frame_register_unsigned (frame,
4807 bits (this_instr, 16, 19));
4809 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
4817 case 0xb: /* branch & link */
4818 case 0xa: /* branch */
4820 nextpc = BranchDest (pc, this_instr);
4826 case 0xe: /* coproc ops */
4830 struct gdbarch_tdep *tdep;
4831 tdep = gdbarch_tdep (gdbarch);
4833 if (tdep->syscall_next_pc != NULL)
4834 nextpc = tdep->syscall_next_pc (frame);
4840 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
4848 /* Determine next PC after current instruction executes. Will call either
4849 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4850 loop is detected. */
4853 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
4857 if (arm_frame_is_thumb (frame))
4859 nextpc = thumb_get_next_pc_raw (frame, pc);
4860 if (nextpc == MAKE_THUMB_ADDR (pc))
4861 error (_("Infinite loop detected"));
4865 nextpc = arm_get_next_pc_raw (frame, pc);
4867 error (_("Infinite loop detected"));
4873 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4874 of the appropriate mode (as encoded in the PC value), even if this
4875 differs from what would be expected according to the symbol tables. */
4878 arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
4879 struct address_space *aspace,
4882 struct cleanup *old_chain
4883 = make_cleanup_restore_integer (&arm_override_mode);
4885 arm_override_mode = IS_THUMB_ADDR (pc);
4886 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4888 insert_single_step_breakpoint (gdbarch, aspace, pc);
4890 do_cleanups (old_chain);
4893 /* single_step() is called just before we want to resume the inferior,
4894 if we want to single-step it but there is no hardware or kernel
4895 single-step support. We find the target of the coming instruction
4896 and breakpoint it. */
4899 arm_software_single_step (struct frame_info *frame)
4901 struct gdbarch *gdbarch = get_frame_arch (frame);
4902 struct address_space *aspace = get_frame_address_space (frame);
4903 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
4905 arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc);
4910 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4911 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4912 NULL if an error occurs. BUF is freed. */
4915 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4916 int old_len, int new_len)
4918 gdb_byte *new_buf, *middle;
4919 int bytes_to_read = new_len - old_len;
4921 new_buf = xmalloc (new_len);
4922 memcpy (new_buf + bytes_to_read, buf, old_len);
4924 if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
4932 /* An IT block is at most the 2-byte IT instruction followed by
4933 four 4-byte instructions. The furthest back we must search to
4934 find an IT block that affects the current instruction is thus
4935 2 + 3 * 4 == 14 bytes. */
4936 #define MAX_IT_BLOCK_PREFIX 14
4938 /* Use a quick scan if there are more than this many bytes of
4940 #define IT_SCAN_THRESHOLD 32
4942 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4943 A breakpoint in an IT block may not be hit, depending on the
4946 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4950 CORE_ADDR boundary, func_start;
4951 int buf_len, buf2_len;
4952 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4953 int i, any, last_it, last_it_count;
4955 /* If we are using BKPT breakpoints, none of this is necessary. */
4956 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4959 /* ARM mode does not have this problem. */
4960 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4963 /* We are setting a breakpoint in Thumb code that could potentially
4964 contain an IT block. The first step is to find how much Thumb
4965 code there is; we do not need to read outside of known Thumb
4967 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4969 /* Thumb-2 code must have mapping symbols to have a chance. */
4972 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4974 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4975 && func_start > boundary)
4976 boundary = func_start;
4978 /* Search for a candidate IT instruction. We have to do some fancy
4979 footwork to distinguish a real IT instruction from the second
4980 half of a 32-bit instruction, but there is no need for that if
4981 there's no candidate. */
4982 buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX);
4984 /* No room for an IT instruction. */
4987 buf = xmalloc (buf_len);
4988 if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
4991 for (i = 0; i < buf_len; i += 2)
4993 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4994 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5006 /* OK, the code bytes before this instruction contain at least one
5007 halfword which resembles an IT instruction. We know that it's
5008 Thumb code, but there are still two possibilities. Either the
5009 halfword really is an IT instruction, or it is the second half of
5010 a 32-bit Thumb instruction. The only way we can tell is to
5011 scan forwards from a known instruction boundary. */
5012 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
5016 /* There's a lot of code before this instruction. Start with an
5017 optimistic search; it's easy to recognize halfwords that can
5018 not be the start of a 32-bit instruction, and use that to
5019 lock on to the instruction boundaries. */
5020 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
5023 buf_len = IT_SCAN_THRESHOLD;
5026 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
5028 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5029 if (thumb_insn_size (inst1) == 2)
5036 /* At this point, if DEFINITE, BUF[I] is the first place we
5037 are sure that we know the instruction boundaries, and it is far
5038 enough from BPADDR that we could not miss an IT instruction
5039 affecting BPADDR. If ! DEFINITE, give up - start from a
5043 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
5047 buf_len = bpaddr - boundary;
5053 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
5056 buf_len = bpaddr - boundary;
5060 /* Scan forwards. Find the last IT instruction before BPADDR. */
5065 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
5067 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5072 else if (inst1 & 0x0002)
5074 else if (inst1 & 0x0004)
5079 i += thumb_insn_size (inst1);
5085 /* There wasn't really an IT instruction after all. */
5088 if (last_it_count < 1)
5089 /* It was too far away. */
5092 /* This really is a trouble spot. Move the breakpoint to the IT
5094 return bpaddr - buf_len + last_it;
5097 /* ARM displaced stepping support.
5099 Generally ARM displaced stepping works as follows:
5101 1. When an instruction is to be single-stepped, it is first decoded by
5102 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5103 Depending on the type of instruction, it is then copied to a scratch
5104 location, possibly in a modified form. The copy_* set of functions
5105 performs such modification, as necessary. A breakpoint is placed after
5106 the modified instruction in the scratch space to return control to GDB.
5107 Note in particular that instructions which modify the PC will no longer
5108 do so after modification.
5110 2. The instruction is single-stepped, by setting the PC to the scratch
5111 location address, and resuming. Control returns to GDB when the
5114 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5115 function used for the current instruction. This function's job is to
5116 put the CPU/memory state back to what it would have been if the
5117 instruction had been executed unmodified in its original location. */
5119 /* NOP instruction (mov r0, r0). */
5120 #define ARM_NOP 0xe1a00000
5122 /* Helper for register reads for displaced stepping. In particular, this
5123 returns the PC as it would be seen by the instruction at its original
5127 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5131 CORE_ADDR from = dsc->insn_addr;
5133 if (regno == ARM_PC_REGNUM)
5135 /* Compute pipeline offset:
5136 - When executing an ARM instruction, PC reads as the address of the
5137 current instruction plus 8.
5138 - When executing a Thumb instruction, PC reads as the address of the
5139 current instruction plus 4. */
5146 if (debug_displaced)
5147 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
5148 (unsigned long) from);
5149 return (ULONGEST) from;
5153 regcache_cooked_read_unsigned (regs, regno, &ret);
5154 if (debug_displaced)
5155 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
5156 regno, (unsigned long) ret);
5162 displaced_in_arm_mode (struct regcache *regs)
5165 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5167 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5169 return (ps & t_bit) == 0;
5172 /* Write to the PC as from a branch instruction. */
5175 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5179 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5180 architecture versions < 6. */
5181 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5182 val & ~(ULONGEST) 0x3);
5184 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
5185 val & ~(ULONGEST) 0x1);
5188 /* Write to the PC as from a branch-exchange instruction. */
5191 bx_write_pc (struct regcache *regs, ULONGEST val)
5194 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
5196 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
5200 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
5201 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
5203 else if ((val & 2) == 0)
5205 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5206 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
5210 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5211 mode, align dest to 4 bytes). */
5212 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5213 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
5214 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
5218 /* Write to the PC as if from a load instruction. */
5221 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5224 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
5225 bx_write_pc (regs, val);
5227 branch_write_pc (regs, dsc, val);
5230 /* Write to the PC as if from an ALU instruction. */
5233 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
5236 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5237 bx_write_pc (regs, val);
5239 branch_write_pc (regs, dsc, val);
5242 /* Helper for writing to registers for displaced stepping. Writing to the PC
5243 has a varying effects depending on the instruction which does the write:
5244 this is controlled by the WRITE_PC argument. */
5247 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
5248 int regno, ULONGEST val, enum pc_write_style write_pc)
5250 if (regno == ARM_PC_REGNUM)
5252 if (debug_displaced)
5253 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
5254 (unsigned long) val);
5257 case BRANCH_WRITE_PC:
5258 branch_write_pc (regs, dsc, val);
5262 bx_write_pc (regs, val);
5266 load_write_pc (regs, dsc, val);
5270 alu_write_pc (regs, dsc, val);
5273 case CANNOT_WRITE_PC:
5274 warning (_("Instruction wrote to PC in an unexpected way when "
5275 "single-stepping"));
5279 internal_error (__FILE__, __LINE__,
5280 _("Invalid argument to displaced_write_reg"));
5283 dsc->wrote_to_pc = 1;
5287 if (debug_displaced)
5288 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
5289 regno, (unsigned long) val);
5290 regcache_cooked_write_unsigned (regs, regno, val);
5294 /* This function is used to concisely determine if an instruction INSN
5295 references PC. Register fields of interest in INSN should have the
5296 corresponding fields of BITMASK set to 0b1111. The function
5297 returns return 1 if any of these fields in INSN reference the PC
5298 (also 0b1111, r15), else it returns 0. */
5301 insn_references_pc (uint32_t insn, uint32_t bitmask)
5303 uint32_t lowbit = 1;
5305 while (bitmask != 0)
5309 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5315 mask = lowbit * 0xf;
5317 if ((insn & mask) == mask)
5326 /* The simplest copy function. Many instructions have the same effect no
5327 matter what address they are executed at: in those cases, use this. */
5330 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
5331 const char *iname, struct displaced_step_closure *dsc)
5333 if (debug_displaced)
5334 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
5335 "opcode/class '%s' unmodified\n", (unsigned long) insn,
5338 dsc->modinsn[0] = insn;
5343 /* Preload instructions with immediate offset. */
5346 cleanup_preload (struct gdbarch *gdbarch,
5347 struct regcache *regs, struct displaced_step_closure *dsc)
5349 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5350 if (!dsc->u.preload.immed)
5351 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5355 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
5356 struct displaced_step_closure *dsc, unsigned int rn)
5359 /* Preload instructions:
5361 {pli/pld} [rn, #+/-imm]
5363 {pli/pld} [r0, #+/-imm]. */
5365 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5366 rn_val = displaced_read_reg (regs, dsc, rn);
5367 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5368 dsc->u.preload.immed = 1;
5370 dsc->cleanup = &cleanup_preload;
5374 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5375 struct displaced_step_closure *dsc)
5377 unsigned int rn = bits (insn, 16, 19);
5379 if (!insn_references_pc (insn, 0x000f0000ul))
5380 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5382 if (debug_displaced)
5383 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5384 (unsigned long) insn);
5386 dsc->modinsn[0] = insn & 0xfff0ffff;
5388 install_preload (gdbarch, regs, dsc, rn);
5393 /* Preload instructions with register offset. */
5396 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
5397 struct displaced_step_closure *dsc, unsigned int rn,
5400 ULONGEST rn_val, rm_val;
5402 /* Preload register-offset instructions:
5404 {pli/pld} [rn, rm {, shift}]
5406 {pli/pld} [r0, r1 {, shift}]. */
5408 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5409 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5410 rn_val = displaced_read_reg (regs, dsc, rn);
5411 rm_val = displaced_read_reg (regs, dsc, rm);
5412 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5413 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5414 dsc->u.preload.immed = 0;
5416 dsc->cleanup = &cleanup_preload;
5420 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
5421 struct regcache *regs,
5422 struct displaced_step_closure *dsc)
5424 unsigned int rn = bits (insn, 16, 19);
5425 unsigned int rm = bits (insn, 0, 3);
5428 if (!insn_references_pc (insn, 0x000f000ful))
5429 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5431 if (debug_displaced)
5432 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
5433 (unsigned long) insn);
5435 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5437 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5441 /* Copy/cleanup coprocessor load and store instructions. */
5444 cleanup_copro_load_store (struct gdbarch *gdbarch,
5445 struct regcache *regs,
5446 struct displaced_step_closure *dsc)
5448 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5450 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5452 if (dsc->u.ldst.writeback)
5453 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5457 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5458 struct displaced_step_closure *dsc,
5459 int writeback, unsigned int rn)
5463 /* Coprocessor load/store instructions:
5465 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5467 {stc/stc2} [r0, #+/-imm].
5469 ldc/ldc2 are handled identically. */
5471 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5472 rn_val = displaced_read_reg (regs, dsc, rn);
5473 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5475 dsc->u.ldst.writeback = writeback;
5476 dsc->u.ldst.rn = rn;
5478 dsc->cleanup = &cleanup_copro_load_store;
5482 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
5483 struct regcache *regs,
5484 struct displaced_step_closure *dsc)
5486 unsigned int rn = bits (insn, 16, 19);
5488 if (!insn_references_pc (insn, 0x000f0000ul))
5489 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5491 if (debug_displaced)
5492 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
5493 "load/store insn %.8lx\n", (unsigned long) insn);
5495 dsc->modinsn[0] = insn & 0xfff0ffff;
5497 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5502 /* Clean up branch instructions (actually perform the branch, by setting
5506 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
5507 struct displaced_step_closure *dsc)
5509 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5510 int branch_taken = condition_true (dsc->u.branch.cond, status);
5511 enum pc_write_style write_pc = dsc->u.branch.exchange
5512 ? BX_WRITE_PC : BRANCH_WRITE_PC;
5517 if (dsc->u.branch.link)
5519 /* The value of LR should be the next insn of current one. In order
5520 not to confuse logic hanlding later insn `bx lr', if current insn mode
5521 is Thumb, the bit 0 of LR value should be set to 1. */
5522 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5525 next_insn_addr |= 0x1;
5527 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5531 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5534 /* Copy B/BL/BLX instructions with immediate destinations. */
5537 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
5538 struct displaced_step_closure *dsc,
5539 unsigned int cond, int exchange, int link, long offset)
5541 /* Implement "BL<cond> <label>" as:
5543 Preparation: cond <- instruction condition
5544 Insn: mov r0, r0 (nop)
5545 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5547 B<cond> similar, but don't set r14 in cleanup. */
5549 dsc->u.branch.cond = cond;
5550 dsc->u.branch.link = link;
5551 dsc->u.branch.exchange = exchange;
5554 dsc->u.branch.dest = dsc->insn_addr + 4 + offset;
5556 dsc->u.branch.dest = dsc->insn_addr + 8 + offset;
5558 dsc->cleanup = &cleanup_branch;
5561 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
5562 struct regcache *regs, struct displaced_step_closure *dsc)
5564 unsigned int cond = bits (insn, 28, 31);
5565 int exchange = (cond == 0xf);
5566 int link = exchange || bit (insn, 24);
5569 if (debug_displaced)
5570 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
5571 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
5572 (unsigned long) insn);
5574 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5575 then arrange the switch into Thumb mode. */
5576 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
5578 offset = bits (insn, 0, 23) << 2;
5580 if (bit (offset, 25))
5581 offset = offset | ~0x3ffffff;
5583 dsc->modinsn[0] = ARM_NOP;
5585 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5589 /* Copy BX/BLX with register-specified destinations. */
5592 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5593 struct displaced_step_closure *dsc, int link,
5594 unsigned int cond, unsigned int rm)
5596 /* Implement {BX,BLX}<cond> <reg>" as:
5598 Preparation: cond <- instruction condition
5599 Insn: mov r0, r0 (nop)
5600 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5602 Don't set r14 in cleanup for BX. */
5604 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5606 dsc->u.branch.cond = cond;
5607 dsc->u.branch.link = link;
5609 dsc->u.branch.exchange = 1;
5611 dsc->cleanup = &cleanup_branch;
5615 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5616 struct regcache *regs, struct displaced_step_closure *dsc)
5618 unsigned int cond = bits (insn, 28, 31);
5621 int link = bit (insn, 5);
5622 unsigned int rm = bits (insn, 0, 3);
5624 if (debug_displaced)
5625 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5626 (unsigned long) insn);
5628 dsc->modinsn[0] = ARM_NOP;
5630 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5634 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5637 cleanup_alu_imm (struct gdbarch *gdbarch,
5638 struct regcache *regs, struct displaced_step_closure *dsc)
5640 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5641 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5642 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5643 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5647 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5648 struct displaced_step_closure *dsc)
5650 unsigned int rn = bits (insn, 16, 19);
5651 unsigned int rd = bits (insn, 12, 15);
5652 unsigned int op = bits (insn, 21, 24);
5653 int is_mov = (op == 0xd);
5654 ULONGEST rd_val, rn_val;
5656 if (!insn_references_pc (insn, 0x000ff000ul))
5657 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5659 if (debug_displaced)
5660 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5661 "%.8lx\n", is_mov ? "move" : "ALU",
5662 (unsigned long) insn);
5664 /* Instruction is of form:
5666 <op><cond> rd, [rn,] #imm
5670 Preparation: tmp1, tmp2 <- r0, r1;
5672 Insn: <op><cond> r0, r1, #imm
5673 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5676 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5677 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5678 rn_val = displaced_read_reg (regs, dsc, rn);
5679 rd_val = displaced_read_reg (regs, dsc, rd);
5680 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5681 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5685 dsc->modinsn[0] = insn & 0xfff00fff;
5687 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5689 dsc->cleanup = &cleanup_alu_imm;
5694 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5697 cleanup_alu_reg (struct gdbarch *gdbarch,
5698 struct regcache *regs, struct displaced_step_closure *dsc)
5703 rd_val = displaced_read_reg (regs, dsc, 0);
5705 for (i = 0; i < 3; i++)
5706 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5708 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5712 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
5713 struct displaced_step_closure *dsc,
5714 unsigned int rd, unsigned int rn, unsigned int rm)
5716 ULONGEST rd_val, rn_val, rm_val;
5718 /* Instruction is of form:
5720 <op><cond> rd, [rn,] rm [, <shift>]
5724 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5725 r0, r1, r2 <- rd, rn, rm
5726 Insn: <op><cond> r0, r1, r2 [, <shift>]
5727 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5730 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5731 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5732 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5733 rd_val = displaced_read_reg (regs, dsc, rd);
5734 rn_val = displaced_read_reg (regs, dsc, rn);
5735 rm_val = displaced_read_reg (regs, dsc, rm);
5736 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5737 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5738 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5741 dsc->cleanup = &cleanup_alu_reg;
5745 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5746 struct displaced_step_closure *dsc)
5748 unsigned int op = bits (insn, 21, 24);
5749 int is_mov = (op == 0xd);
5751 if (!insn_references_pc (insn, 0x000ff00ful))
5752 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
5754 if (debug_displaced)
5755 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
5756 is_mov ? "move" : "ALU", (unsigned long) insn);
5759 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
5761 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
5763 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
5768 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5771 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
5772 struct regcache *regs,
5773 struct displaced_step_closure *dsc)
5775 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5778 for (i = 0; i < 4; i++)
5779 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5781 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5785 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
5786 struct displaced_step_closure *dsc,
5787 unsigned int rd, unsigned int rn, unsigned int rm,
5791 ULONGEST rd_val, rn_val, rm_val, rs_val;
5793 /* Instruction is of form:
5795 <op><cond> rd, [rn,] rm, <shift> rs
5799 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5800 r0, r1, r2, r3 <- rd, rn, rm, rs
5801 Insn: <op><cond> r0, r1, r2, <shift> r3
5803 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5807 for (i = 0; i < 4; i++)
5808 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5810 rd_val = displaced_read_reg (regs, dsc, rd);
5811 rn_val = displaced_read_reg (regs, dsc, rn);
5812 rm_val = displaced_read_reg (regs, dsc, rm);
5813 rs_val = displaced_read_reg (regs, dsc, rs);
5814 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5815 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5816 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5817 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
5819 dsc->cleanup = &cleanup_alu_shifted_reg;
5823 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
5824 struct regcache *regs,
5825 struct displaced_step_closure *dsc)
5827 unsigned int op = bits (insn, 21, 24);
5828 int is_mov = (op == 0xd);
5829 unsigned int rd, rn, rm, rs;
5831 if (!insn_references_pc (insn, 0x000fff0ful))
5832 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
5834 if (debug_displaced)
5835 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
5836 "%.8lx\n", is_mov ? "move" : "ALU",
5837 (unsigned long) insn);
5839 rn = bits (insn, 16, 19);
5840 rm = bits (insn, 0, 3);
5841 rs = bits (insn, 8, 11);
5842 rd = bits (insn, 12, 15);
5845 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
5847 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
5849 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
5854 /* Clean up load instructions. */
5857 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
5858 struct displaced_step_closure *dsc)
5860 ULONGEST rt_val, rt_val2 = 0, rn_val;
5862 rt_val = displaced_read_reg (regs, dsc, 0);
5863 if (dsc->u.ldst.xfersize == 8)
5864 rt_val2 = displaced_read_reg (regs, dsc, 1);
5865 rn_val = displaced_read_reg (regs, dsc, 2);
5867 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5868 if (dsc->u.ldst.xfersize > 4)
5869 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5870 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5871 if (!dsc->u.ldst.immed)
5872 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5874 /* Handle register writeback. */
5875 if (dsc->u.ldst.writeback)
5876 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5877 /* Put result in right place. */
5878 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
5879 if (dsc->u.ldst.xfersize == 8)
5880 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5883 /* Clean up store instructions. */
5886 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5887 struct displaced_step_closure *dsc)
5889 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
5891 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5892 if (dsc->u.ldst.xfersize > 4)
5893 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5894 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5895 if (!dsc->u.ldst.immed)
5896 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5897 if (!dsc->u.ldst.restore_r4)
5898 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5901 if (dsc->u.ldst.writeback)
5902 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5905 /* Copy "extra" load/store instructions. These are halfword/doubleword
5906 transfers, which have a different encoding to byte/word transfers. */
5909 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged,
5910 struct regcache *regs, struct displaced_step_closure *dsc)
5912 unsigned int op1 = bits (insn, 20, 24);
5913 unsigned int op2 = bits (insn, 5, 6);
5914 unsigned int rt = bits (insn, 12, 15);
5915 unsigned int rn = bits (insn, 16, 19);
5916 unsigned int rm = bits (insn, 0, 3);
5917 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5918 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5919 int immed = (op1 & 0x4) != 0;
5921 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5923 if (!insn_references_pc (insn, 0x000ff00ful))
5924 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5926 if (debug_displaced)
5927 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5928 "insn %.8lx\n", unpriveleged ? "unpriveleged " : "",
5929 (unsigned long) insn);
5931 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5934 internal_error (__FILE__, __LINE__,
5935 _("copy_extra_ld_st: instruction decode error"));
5937 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5938 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5939 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5941 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5943 rt_val = displaced_read_reg (regs, dsc, rt);
5944 if (bytesize[opcode] == 8)
5945 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
5946 rn_val = displaced_read_reg (regs, dsc, rn);
5948 rm_val = displaced_read_reg (regs, dsc, rm);
5950 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5951 if (bytesize[opcode] == 8)
5952 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5953 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5955 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5958 dsc->u.ldst.xfersize = bytesize[opcode];
5959 dsc->u.ldst.rn = rn;
5960 dsc->u.ldst.immed = immed;
5961 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5962 dsc->u.ldst.restore_r4 = 0;
5965 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5967 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5968 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5970 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5972 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5973 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5975 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5980 /* Copy byte/word loads and stores. */
5983 install_ldr_str_ldrb_strb (struct gdbarch *gdbarch, struct regcache *regs,
5984 struct displaced_step_closure *dsc, int load,
5985 int immed, int writeback, int byte, int usermode,
5986 int rt, int rm, int rn)
5988 ULONGEST rt_val, rn_val, rm_val = 0;
5990 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5991 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5993 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5995 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
5997 rt_val = displaced_read_reg (regs, dsc, rt);
5998 rn_val = displaced_read_reg (regs, dsc, rn);
6000 rm_val = displaced_read_reg (regs, dsc, rm);
6002 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6003 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6005 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6007 dsc->u.ldst.xfersize = byte ? 1 : 4;
6008 dsc->u.ldst.rn = rn;
6009 dsc->u.ldst.immed = immed;
6010 dsc->u.ldst.writeback = writeback;
6012 /* To write PC we can do:
6014 Before this sequence of instructions:
6015 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6016 r2 is the Rn value got from dispalced_read_reg.
6018 Insn1: push {pc} Write address of STR instruction + offset on stack
6019 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6020 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6021 = addr(Insn1) + offset - addr(Insn3) - 8
6023 Insn4: add r4, r4, #8 r4 = offset - 8
6024 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6026 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6028 Otherwise we don't know what value to write for PC, since the offset is
6029 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6030 of this can be found in Section "Saving from r15" in
6031 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6033 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6037 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
6038 struct regcache *regs,
6039 struct displaced_step_closure *dsc,
6040 int load, int byte, int usermode)
6042 int immed = !bit (insn, 25);
6043 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
6044 unsigned int rt = bits (insn, 12, 15);
6045 unsigned int rn = bits (insn, 16, 19);
6046 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
6048 if (!insn_references_pc (insn, 0x000ff00ful))
6049 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6051 if (debug_displaced)
6052 fprintf_unfiltered (gdb_stdlog,
6053 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6054 load ? (byte ? "ldrb" : "ldr")
6055 : (byte ? "strb" : "str"), usermode ? "t" : "",
6057 (unsigned long) insn);
6059 install_ldr_str_ldrb_strb (gdbarch, regs, dsc, load, immed, writeback, byte,
6060 usermode, rt, rm, rn);
6062 if (load || rt != ARM_PC_REGNUM)
6064 dsc->u.ldst.restore_r4 = 0;
6067 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6069 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6070 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6072 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6074 {ldr,str}[b]<cond> r0, [r2, r3]. */
6075 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6079 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6080 dsc->u.ldst.restore_r4 = 1;
6081 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6082 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6083 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6084 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6085 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6089 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6091 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6096 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6101 /* Cleanup LDM instructions with fully-populated register list. This is an
6102 unfortunate corner case: it's impossible to implement correctly by modifying
6103 the instruction. The issue is as follows: we have an instruction,
6107 which we must rewrite to avoid loading PC. A possible solution would be to
6108 do the load in two halves, something like (with suitable cleanup
6112 ldm[id][ab] r8!, {r0-r7}
6114 ldm[id][ab] r8, {r7-r14}
6117 but at present there's no suitable place for <temp>, since the scratch space
6118 is overwritten before the cleanup routine is called. For now, we simply
6119 emulate the instruction. */
6122 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
6123 struct displaced_step_closure *dsc)
6125 int inc = dsc->u.block.increment;
6126 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6127 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6128 uint32_t regmask = dsc->u.block.regmask;
6129 int regno = inc ? 0 : 15;
6130 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6131 int exception_return = dsc->u.block.load && dsc->u.block.user
6132 && (regmask & 0x8000) != 0;
6133 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6134 int do_transfer = condition_true (dsc->u.block.cond, status);
6135 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6140 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6141 sensible we can do here. Complain loudly. */
6142 if (exception_return)
6143 error (_("Cannot single-step exception return"));
6145 /* We don't handle any stores here for now. */
6146 gdb_assert (dsc->u.block.load != 0);
6148 if (debug_displaced)
6149 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
6150 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
6151 dsc->u.block.increment ? "inc" : "dec",
6152 dsc->u.block.before ? "before" : "after");
6159 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6162 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6165 xfer_addr += bump_before;
6167 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
6168 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6170 xfer_addr += bump_after;
6172 regmask &= ~(1 << regno);
6175 if (dsc->u.block.writeback)
6176 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6180 /* Clean up an STM which included the PC in the register list. */
6183 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
6184 struct displaced_step_closure *dsc)
6186 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6187 int store_executed = condition_true (dsc->u.block.cond, status);
6188 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
6189 CORE_ADDR stm_insn_addr;
6192 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6194 /* If condition code fails, there's nothing else to do. */
6195 if (!store_executed)
6198 if (dsc->u.block.increment)
6200 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6202 if (dsc->u.block.before)
6207 pc_stored_at = dsc->u.block.xfer_addr;
6209 if (dsc->u.block.before)
6213 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
6214 stm_insn_addr = dsc->scratch_base;
6215 offset = pc_val - stm_insn_addr;
6217 if (debug_displaced)
6218 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
6219 "STM instruction\n", offset);
6221 /* Rewrite the stored PC to the proper value for the non-displaced original
6223 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
6224 dsc->insn_addr + offset);
6227 /* Clean up an LDM which includes the PC in the register list. We clumped all
6228 the registers in the transferred list into a contiguous range r0...rX (to
6229 avoid loading PC directly and losing control of the debugged program), so we
6230 must undo that here. */
6233 cleanup_block_load_pc (struct gdbarch *gdbarch,
6234 struct regcache *regs,
6235 struct displaced_step_closure *dsc)
6237 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6238 int load_executed = condition_true (dsc->u.block.cond, status), i;
6239 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6240 unsigned int regs_loaded = bitcount (mask);
6241 unsigned int num_to_shuffle = regs_loaded, clobbered;
6243 /* The method employed here will fail if the register list is fully populated
6244 (we need to avoid loading PC directly). */
6245 gdb_assert (num_to_shuffle < 16);
6250 clobbered = (1 << num_to_shuffle) - 1;
6252 while (num_to_shuffle > 0)
6254 if ((mask & (1 << write_reg)) != 0)
6256 unsigned int read_reg = num_to_shuffle - 1;
6258 if (read_reg != write_reg)
6260 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6261 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
6262 if (debug_displaced)
6263 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
6264 "loaded register r%d to r%d\n"), read_reg,
6267 else if (debug_displaced)
6268 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
6269 "r%d already in the right place\n"),
6272 clobbered &= ~(1 << write_reg);
6280 /* Restore any registers we scribbled over. */
6281 for (write_reg = 0; clobbered != 0; write_reg++)
6283 if ((clobbered & (1 << write_reg)) != 0)
6285 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
6287 if (debug_displaced)
6288 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
6289 "clobbered register r%d\n"), write_reg);
6290 clobbered &= ~(1 << write_reg);
6294 /* Perform register writeback manually. */
6295 if (dsc->u.block.writeback)
6297 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
6299 if (dsc->u.block.increment)
6300 new_rn_val += regs_loaded * 4;
6302 new_rn_val -= regs_loaded * 4;
6304 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
6309 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6310 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6313 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
6314 struct regcache *regs,
6315 struct displaced_step_closure *dsc)
6317 int load = bit (insn, 20);
6318 int user = bit (insn, 22);
6319 int increment = bit (insn, 23);
6320 int before = bit (insn, 24);
6321 int writeback = bit (insn, 21);
6322 int rn = bits (insn, 16, 19);
6324 /* Block transfers which don't mention PC can be run directly
6326 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
6327 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
6329 if (rn == ARM_PC_REGNUM)
6331 warning (_("displaced: Unpredictable LDM or STM with "
6332 "base register r15"));
6333 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
6336 if (debug_displaced)
6337 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6338 "%.8lx\n", (unsigned long) insn);
6340 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6341 dsc->u.block.rn = rn;
6343 dsc->u.block.load = load;
6344 dsc->u.block.user = user;
6345 dsc->u.block.increment = increment;
6346 dsc->u.block.before = before;
6347 dsc->u.block.writeback = writeback;
6348 dsc->u.block.cond = bits (insn, 28, 31);
6350 dsc->u.block.regmask = insn & 0xffff;
6354 if ((insn & 0xffff) == 0xffff)
6356 /* LDM with a fully-populated register list. This case is
6357 particularly tricky. Implement for now by fully emulating the
6358 instruction (which might not behave perfectly in all cases, but
6359 these instructions should be rare enough for that not to matter
6361 dsc->modinsn[0] = ARM_NOP;
6363 dsc->cleanup = &cleanup_block_load_all;
6367 /* LDM of a list of registers which includes PC. Implement by
6368 rewriting the list of registers to be transferred into a
6369 contiguous chunk r0...rX before doing the transfer, then shuffling
6370 registers into the correct places in the cleanup routine. */
6371 unsigned int regmask = insn & 0xffff;
6372 unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1;
6373 unsigned int to = 0, from = 0, i, new_rn;
6375 for (i = 0; i < num_in_list; i++)
6376 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6378 /* Writeback makes things complicated. We need to avoid clobbering
6379 the base register with one of the registers in our modified
6380 register list, but just using a different register can't work in
6383 ldm r14!, {r0-r13,pc}
6385 which would need to be rewritten as:
6389 but that can't work, because there's no free register for N.
6391 Solve this by turning off the writeback bit, and emulating
6392 writeback manually in the cleanup routine. */
6397 new_regmask = (1 << num_in_list) - 1;
6399 if (debug_displaced)
6400 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6401 "{..., pc}: original reg list %.4x, modified "
6402 "list %.4x\n"), rn, writeback ? "!" : "",
6403 (int) insn & 0xffff, new_regmask);
6405 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6407 dsc->cleanup = &cleanup_block_load_pc;
6412 /* STM of a list of registers which includes PC. Run the instruction
6413 as-is, but out of line: this will store the wrong value for the PC,
6414 so we must manually fix up the memory in the cleanup routine.
6415 Doing things this way has the advantage that we can auto-detect
6416 the offset of the PC write (which is architecture-dependent) in
6417 the cleanup routine. */
6418 dsc->modinsn[0] = insn;
6420 dsc->cleanup = &cleanup_block_store_pc;
6426 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6427 for Linux, where some SVC instructions must be treated specially. */
6430 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6431 struct displaced_step_closure *dsc)
6433 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6435 if (debug_displaced)
6436 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6437 "%.8lx\n", (unsigned long) resume_addr);
6439 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6444 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6445 struct regcache *regs, struct displaced_step_closure *dsc)
6448 if (debug_displaced)
6449 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6450 (unsigned long) insn);
6452 /* Preparation: none.
6453 Insn: unmodified svc.
6454 Cleanup: pc <- insn_addr + 4. */
6456 dsc->modinsn[0] = insn;
6458 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6460 dsc->wrote_to_pc = 1;
6462 /* Allow OS-specific code to override SVC handling. */
6463 if (dsc->u.svc.copy_svc_os)
6464 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6467 dsc->cleanup = &cleanup_svc;
6473 /* Copy undefined instructions. */
6476 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6477 struct displaced_step_closure *dsc)
6479 if (debug_displaced)
6480 fprintf_unfiltered (gdb_stdlog,
6481 "displaced: copying undefined insn %.8lx\n",
6482 (unsigned long) insn);
6484 dsc->modinsn[0] = insn;
6489 /* Copy unpredictable instructions. */
6492 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
6493 struct displaced_step_closure *dsc)
6495 if (debug_displaced)
6496 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
6497 "%.8lx\n", (unsigned long) insn);
6499 dsc->modinsn[0] = insn;
6504 /* The decode_* functions are instruction decoding helpers. They mostly follow
6505 the presentation in the ARM ARM. */
6508 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
6509 struct regcache *regs,
6510 struct displaced_step_closure *dsc)
6512 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
6513 unsigned int rn = bits (insn, 16, 19);
6515 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
6516 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
6517 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
6518 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
6519 else if ((op1 & 0x60) == 0x20)
6520 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
6521 else if ((op1 & 0x71) == 0x40)
6522 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
6524 else if ((op1 & 0x77) == 0x41)
6525 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6526 else if ((op1 & 0x77) == 0x45)
6527 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
6528 else if ((op1 & 0x77) == 0x51)
6531 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6533 return arm_copy_unpred (gdbarch, insn, dsc);
6535 else if ((op1 & 0x77) == 0x55)
6536 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6537 else if (op1 == 0x57)
6540 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
6541 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
6542 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
6543 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
6544 default: return arm_copy_unpred (gdbarch, insn, dsc);
6546 else if ((op1 & 0x63) == 0x43)
6547 return arm_copy_unpred (gdbarch, insn, dsc);
6548 else if ((op2 & 0x1) == 0x0)
6549 switch (op1 & ~0x80)
6552 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6554 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
6555 case 0x71: case 0x75:
6557 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
6558 case 0x63: case 0x67: case 0x73: case 0x77:
6559 return arm_copy_unpred (gdbarch, insn, dsc);
6561 return arm_copy_undef (gdbarch, insn, dsc);
6564 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
6568 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
6569 struct regcache *regs,
6570 struct displaced_step_closure *dsc)
6572 if (bit (insn, 27) == 0)
6573 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
6574 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6575 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
6578 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
6581 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
6583 case 0x4: case 0x5: case 0x6: case 0x7:
6584 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6587 switch ((insn & 0xe00000) >> 21)
6589 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6591 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6594 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6597 return arm_copy_undef (gdbarch, insn, dsc);
6602 int rn_f = (bits (insn, 16, 19) == 0xf);
6603 switch ((insn & 0xe00000) >> 21)
6606 /* ldc/ldc2 imm (undefined for rn == pc). */
6607 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
6608 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6611 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6613 case 0x4: case 0x5: case 0x6: case 0x7:
6614 /* ldc/ldc2 lit (undefined for rn != pc). */
6615 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
6616 : arm_copy_undef (gdbarch, insn, dsc);
6619 return arm_copy_undef (gdbarch, insn, dsc);
6624 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
6627 if (bits (insn, 16, 19) == 0xf)
6629 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6631 return arm_copy_undef (gdbarch, insn, dsc);
6635 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6637 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6641 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6643 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6646 return arm_copy_undef (gdbarch, insn, dsc);
6650 /* Decode miscellaneous instructions in dp/misc encoding space. */
6653 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
6654 struct regcache *regs,
6655 struct displaced_step_closure *dsc)
6657 unsigned int op2 = bits (insn, 4, 6);
6658 unsigned int op = bits (insn, 21, 22);
6659 unsigned int op1 = bits (insn, 16, 19);
6664 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
6667 if (op == 0x1) /* bx. */
6668 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
6670 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
6672 return arm_copy_undef (gdbarch, insn, dsc);
6676 /* Not really supported. */
6677 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
6679 return arm_copy_undef (gdbarch, insn, dsc);
6683 return arm_copy_bx_blx_reg (gdbarch, insn,
6684 regs, dsc); /* blx register. */
6686 return arm_copy_undef (gdbarch, insn, dsc);
6689 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
6693 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
6695 /* Not really supported. */
6696 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
6699 return arm_copy_undef (gdbarch, insn, dsc);
6704 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
6705 struct regcache *regs,
6706 struct displaced_step_closure *dsc)
6709 switch (bits (insn, 20, 24))
6712 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
6715 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
6717 case 0x12: case 0x16:
6718 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
6721 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
6725 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
6727 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
6728 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
6729 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
6730 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
6731 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
6732 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
6733 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
6734 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
6735 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
6736 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
6737 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
6738 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
6739 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
6740 /* 2nd arg means "unpriveleged". */
6741 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
6745 /* Should be unreachable. */
6750 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
6751 struct regcache *regs,
6752 struct displaced_step_closure *dsc)
6754 int a = bit (insn, 25), b = bit (insn, 4);
6755 uint32_t op1 = bits (insn, 20, 24);
6756 int rn_f = bits (insn, 16, 19) == 0xf;
6758 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
6759 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
6760 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 0);
6761 else if ((!a && (op1 & 0x17) == 0x02)
6762 || (a && (op1 & 0x17) == 0x02 && !b))
6763 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 1);
6764 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
6765 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
6766 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 0);
6767 else if ((!a && (op1 & 0x17) == 0x03)
6768 || (a && (op1 & 0x17) == 0x03 && !b))
6769 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 1);
6770 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
6771 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
6772 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
6773 else if ((!a && (op1 & 0x17) == 0x06)
6774 || (a && (op1 & 0x17) == 0x06 && !b))
6775 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
6776 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
6777 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
6778 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
6779 else if ((!a && (op1 & 0x17) == 0x07)
6780 || (a && (op1 & 0x17) == 0x07 && !b))
6781 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
6783 /* Should be unreachable. */
6788 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
6789 struct displaced_step_closure *dsc)
6791 switch (bits (insn, 20, 24))
6793 case 0x00: case 0x01: case 0x02: case 0x03:
6794 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
6796 case 0x04: case 0x05: case 0x06: case 0x07:
6797 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
6799 case 0x08: case 0x09: case 0x0a: case 0x0b:
6800 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6801 return arm_copy_unmodified (gdbarch, insn,
6802 "decode/pack/unpack/saturate/reverse", dsc);
6805 if (bits (insn, 5, 7) == 0) /* op2. */
6807 if (bits (insn, 12, 15) == 0xf)
6808 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
6810 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
6813 return arm_copy_undef (gdbarch, insn, dsc);
6815 case 0x1a: case 0x1b:
6816 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6817 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
6819 return arm_copy_undef (gdbarch, insn, dsc);
6821 case 0x1c: case 0x1d:
6822 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
6824 if (bits (insn, 0, 3) == 0xf)
6825 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
6827 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
6830 return arm_copy_undef (gdbarch, insn, dsc);
6832 case 0x1e: case 0x1f:
6833 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6834 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
6836 return arm_copy_undef (gdbarch, insn, dsc);
6839 /* Should be unreachable. */
6844 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
6845 struct regcache *regs,
6846 struct displaced_step_closure *dsc)
6849 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6851 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
6855 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
6856 struct regcache *regs,
6857 struct displaced_step_closure *dsc)
6859 unsigned int opcode = bits (insn, 20, 24);
6863 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6864 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
6866 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6867 case 0x12: case 0x16:
6868 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
6870 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6871 case 0x13: case 0x17:
6872 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
6874 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6875 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6876 /* Note: no writeback for these instructions. Bit 25 will always be
6877 zero though (via caller), so the following works OK. */
6878 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6881 /* Should be unreachable. */
6886 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
6887 struct regcache *regs, struct displaced_step_closure *dsc)
6889 unsigned int op1 = bits (insn, 20, 25);
6890 int op = bit (insn, 4);
6891 unsigned int coproc = bits (insn, 8, 11);
6892 unsigned int rn = bits (insn, 16, 19);
6894 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
6895 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
6896 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
6897 && (coproc & 0xe) != 0xa)
6899 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6900 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
6901 && (coproc & 0xe) != 0xa)
6902 /* ldc/ldc2 imm/lit. */
6903 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6904 else if ((op1 & 0x3e) == 0x00)
6905 return arm_copy_undef (gdbarch, insn, dsc);
6906 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6907 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6908 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6909 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6910 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6911 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6912 else if ((op1 & 0x30) == 0x20 && !op)
6914 if ((coproc & 0xe) == 0xa)
6915 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6917 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6919 else if ((op1 & 0x30) == 0x20 && op)
6920 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6921 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6922 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6923 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6924 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6925 else if ((op1 & 0x30) == 0x30)
6926 return arm_copy_svc (gdbarch, insn, regs, dsc);
6928 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6932 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
6933 CORE_ADDR to, struct regcache *regs,
6934 struct displaced_step_closure *dsc)
6936 error (_("Displaced stepping is only supported in ARM mode"));
6940 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
6941 CORE_ADDR to, struct regcache *regs,
6942 struct displaced_step_closure *dsc)
6945 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
6948 /* Most displaced instructions use a 1-instruction scratch space, so set this
6949 here and override below if/when necessary. */
6951 dsc->insn_addr = from;
6952 dsc->scratch_base = to;
6953 dsc->cleanup = NULL;
6954 dsc->wrote_to_pc = 0;
6956 if (!displaced_in_arm_mode (regs))
6957 return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
6961 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
6962 if (debug_displaced)
6963 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
6964 "at %.8lx\n", (unsigned long) insn,
6965 (unsigned long) from);
6967 if ((insn & 0xf0000000) == 0xf0000000)
6968 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
6969 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
6971 case 0x0: case 0x1: case 0x2: case 0x3:
6972 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
6975 case 0x4: case 0x5: case 0x6:
6976 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
6980 err = arm_decode_media (gdbarch, insn, dsc);
6983 case 0x8: case 0x9: case 0xa: case 0xb:
6984 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
6987 case 0xc: case 0xd: case 0xe: case 0xf:
6988 err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
6993 internal_error (__FILE__, __LINE__,
6994 _("arm_process_displaced_insn: Instruction decode error"));
6997 /* Actually set up the scratch space for a displaced instruction. */
7000 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
7001 CORE_ADDR to, struct displaced_step_closure *dsc)
7003 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7004 unsigned int i, len, offset;
7005 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7006 int size = dsc->is_thumb? 2 : 4;
7007 const unsigned char *bkp_insn;
7010 /* Poke modified instruction(s). */
7011 for (i = 0; i < dsc->numinsns; i++)
7013 if (debug_displaced)
7015 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
7017 fprintf_unfiltered (gdb_stdlog, "%.8lx",
7020 fprintf_unfiltered (gdb_stdlog, "%.4x",
7021 (unsigned short)dsc->modinsn[i]);
7023 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
7024 (unsigned long) to + offset);
7027 write_memory_unsigned_integer (to + offset, size,
7028 byte_order_for_code,
7033 /* Choose the correct breakpoint instruction. */
7036 bkp_insn = tdep->thumb_breakpoint;
7037 len = tdep->thumb_breakpoint_size;
7041 bkp_insn = tdep->arm_breakpoint;
7042 len = tdep->arm_breakpoint_size;
7045 /* Put breakpoint afterwards. */
7046 write_memory (to + offset, bkp_insn, len);
7048 if (debug_displaced)
7049 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
7050 paddress (gdbarch, from), paddress (gdbarch, to));
7053 /* Entry point for copying an instruction into scratch space for displaced
7056 struct displaced_step_closure *
7057 arm_displaced_step_copy_insn (struct gdbarch *gdbarch,
7058 CORE_ADDR from, CORE_ADDR to,
7059 struct regcache *regs)
7061 struct displaced_step_closure *dsc
7062 = xmalloc (sizeof (struct displaced_step_closure));
7063 arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
7064 arm_displaced_init_closure (gdbarch, from, to, dsc);
7069 /* Entry point for cleaning things up after a displaced instruction has been
7073 arm_displaced_step_fixup (struct gdbarch *gdbarch,
7074 struct displaced_step_closure *dsc,
7075 CORE_ADDR from, CORE_ADDR to,
7076 struct regcache *regs)
7079 dsc->cleanup (gdbarch, regs, dsc);
7081 if (!dsc->wrote_to_pc)
7082 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
7083 dsc->insn_addr + dsc->insn_size);
7087 #include "bfd-in2.h"
7088 #include "libcoff.h"
7091 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
7093 struct gdbarch *gdbarch = info->application_data;
7095 if (arm_pc_is_thumb (gdbarch, memaddr))
7097 static asymbol *asym;
7098 static combined_entry_type ce;
7099 static struct coff_symbol_struct csym;
7100 static struct bfd fake_bfd;
7101 static bfd_target fake_target;
7103 if (csym.native == NULL)
7105 /* Create a fake symbol vector containing a Thumb symbol.
7106 This is solely so that the code in print_insn_little_arm()
7107 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7108 the presence of a Thumb symbol and switch to decoding
7109 Thumb instructions. */
7111 fake_target.flavour = bfd_target_coff_flavour;
7112 fake_bfd.xvec = &fake_target;
7113 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
7115 csym.symbol.the_bfd = &fake_bfd;
7116 csym.symbol.name = "fake";
7117 asym = (asymbol *) & csym;
7120 memaddr = UNMAKE_THUMB_ADDR (memaddr);
7121 info->symbols = &asym;
7124 info->symbols = NULL;
7126 if (info->endian == BFD_ENDIAN_BIG)
7127 return print_insn_big_arm (memaddr, info);
7129 return print_insn_little_arm (memaddr, info);
7132 /* The following define instruction sequences that will cause ARM
7133 cpu's to take an undefined instruction trap. These are used to
7134 signal a breakpoint to GDB.
7136 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7137 modes. A different instruction is required for each mode. The ARM
7138 cpu's can also be big or little endian. Thus four different
7139 instructions are needed to support all cases.
7141 Note: ARMv4 defines several new instructions that will take the
7142 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7143 not in fact add the new instructions. The new undefined
7144 instructions in ARMv4 are all instructions that had no defined
7145 behaviour in earlier chips. There is no guarantee that they will
7146 raise an exception, but may be treated as NOP's. In practice, it
7147 may only safe to rely on instructions matching:
7149 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7150 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7151 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7153 Even this may only true if the condition predicate is true. The
7154 following use a condition predicate of ALWAYS so it is always TRUE.
7156 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7157 and NetBSD all use a software interrupt rather than an undefined
7158 instruction to force a trap. This can be handled by by the
7159 abi-specific code during establishment of the gdbarch vector. */
7161 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7162 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7163 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7164 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7166 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
7167 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
7168 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
7169 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
7171 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7172 the program counter value to determine whether a 16-bit or 32-bit
7173 breakpoint should be used. It returns a pointer to a string of
7174 bytes that encode a breakpoint instruction, stores the length of
7175 the string to *lenptr, and adjusts the program counter (if
7176 necessary) to point to the actual memory location where the
7177 breakpoint should be inserted. */
7179 static const unsigned char *
7180 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
7182 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7183 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7185 if (arm_pc_is_thumb (gdbarch, *pcptr))
7187 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
7189 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7190 check whether we are replacing a 32-bit instruction. */
7191 if (tdep->thumb2_breakpoint != NULL)
7194 if (target_read_memory (*pcptr, buf, 2) == 0)
7196 unsigned short inst1;
7197 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
7198 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
7200 *lenptr = tdep->thumb2_breakpoint_size;
7201 return tdep->thumb2_breakpoint;
7206 *lenptr = tdep->thumb_breakpoint_size;
7207 return tdep->thumb_breakpoint;
7211 *lenptr = tdep->arm_breakpoint_size;
7212 return tdep->arm_breakpoint;
7217 arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
7220 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7222 arm_breakpoint_from_pc (gdbarch, pcptr, kindptr);
7224 if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4)
7225 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7226 that this is not confused with a 32-bit ARM breakpoint. */
7230 /* Extract from an array REGBUF containing the (raw) register state a
7231 function return value of type TYPE, and copy that, in virtual
7232 format, into VALBUF. */
7235 arm_extract_return_value (struct type *type, struct regcache *regs,
7238 struct gdbarch *gdbarch = get_regcache_arch (regs);
7239 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7241 if (TYPE_CODE_FLT == TYPE_CODE (type))
7243 switch (gdbarch_tdep (gdbarch)->fp_model)
7247 /* The value is in register F0 in internal format. We need to
7248 extract the raw value and then convert it to the desired
7250 bfd_byte tmpbuf[FP_REGISTER_SIZE];
7252 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
7253 convert_from_extended (floatformat_from_type (type), tmpbuf,
7254 valbuf, gdbarch_byte_order (gdbarch));
7258 case ARM_FLOAT_SOFT_FPA:
7259 case ARM_FLOAT_SOFT_VFP:
7260 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7261 not using the VFP ABI code. */
7263 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
7264 if (TYPE_LENGTH (type) > 4)
7265 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7266 valbuf + INT_REGISTER_SIZE);
7270 internal_error (__FILE__, __LINE__,
7271 _("arm_extract_return_value: "
7272 "Floating point model not supported"));
7276 else if (TYPE_CODE (type) == TYPE_CODE_INT
7277 || TYPE_CODE (type) == TYPE_CODE_CHAR
7278 || TYPE_CODE (type) == TYPE_CODE_BOOL
7279 || TYPE_CODE (type) == TYPE_CODE_PTR
7280 || TYPE_CODE (type) == TYPE_CODE_REF
7281 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7283 /* If the type is a plain integer, then the access is
7284 straight-forward. Otherwise we have to play around a bit
7286 int len = TYPE_LENGTH (type);
7287 int regno = ARM_A1_REGNUM;
7292 /* By using store_unsigned_integer we avoid having to do
7293 anything special for small big-endian values. */
7294 regcache_cooked_read_unsigned (regs, regno++, &tmp);
7295 store_unsigned_integer (valbuf,
7296 (len > INT_REGISTER_SIZE
7297 ? INT_REGISTER_SIZE : len),
7299 len -= INT_REGISTER_SIZE;
7300 valbuf += INT_REGISTER_SIZE;
7305 /* For a structure or union the behaviour is as if the value had
7306 been stored to word-aligned memory and then loaded into
7307 registers with 32-bit load instruction(s). */
7308 int len = TYPE_LENGTH (type);
7309 int regno = ARM_A1_REGNUM;
7310 bfd_byte tmpbuf[INT_REGISTER_SIZE];
7314 regcache_cooked_read (regs, regno++, tmpbuf);
7315 memcpy (valbuf, tmpbuf,
7316 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
7317 len -= INT_REGISTER_SIZE;
7318 valbuf += INT_REGISTER_SIZE;
7324 /* Will a function return an aggregate type in memory or in a
7325 register? Return 0 if an aggregate type can be returned in a
7326 register, 1 if it must be returned in memory. */
7329 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
7332 enum type_code code;
7334 CHECK_TYPEDEF (type);
7336 /* In the ARM ABI, "integer" like aggregate types are returned in
7337 registers. For an aggregate type to be integer like, its size
7338 must be less than or equal to INT_REGISTER_SIZE and the
7339 offset of each addressable subfield must be zero. Note that bit
7340 fields are not addressable, and all addressable subfields of
7341 unions always start at offset zero.
7343 This function is based on the behaviour of GCC 2.95.1.
7344 See: gcc/arm.c: arm_return_in_memory() for details.
7346 Note: All versions of GCC before GCC 2.95.2 do not set up the
7347 parameters correctly for a function returning the following
7348 structure: struct { float f;}; This should be returned in memory,
7349 not a register. Richard Earnshaw sent me a patch, but I do not
7350 know of any way to detect if a function like the above has been
7351 compiled with the correct calling convention. */
7353 /* All aggregate types that won't fit in a register must be returned
7355 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
7360 /* The AAPCS says all aggregates not larger than a word are returned
7362 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
7365 /* The only aggregate types that can be returned in a register are
7366 structs and unions. Arrays must be returned in memory. */
7367 code = TYPE_CODE (type);
7368 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
7373 /* Assume all other aggregate types can be returned in a register.
7374 Run a check for structures, unions and arrays. */
7377 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
7380 /* Need to check if this struct/union is "integer" like. For
7381 this to be true, its size must be less than or equal to
7382 INT_REGISTER_SIZE and the offset of each addressable
7383 subfield must be zero. Note that bit fields are not
7384 addressable, and unions always start at offset zero. If any
7385 of the subfields is a floating point type, the struct/union
7386 cannot be an integer type. */
7388 /* For each field in the object, check:
7389 1) Is it FP? --> yes, nRc = 1;
7390 2) Is it addressable (bitpos != 0) and
7391 not packed (bitsize == 0)?
7395 for (i = 0; i < TYPE_NFIELDS (type); i++)
7397 enum type_code field_type_code;
7398 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
7401 /* Is it a floating point type field? */
7402 if (field_type_code == TYPE_CODE_FLT)
7408 /* If bitpos != 0, then we have to care about it. */
7409 if (TYPE_FIELD_BITPOS (type, i) != 0)
7411 /* Bitfields are not addressable. If the field bitsize is
7412 zero, then the field is not packed. Hence it cannot be
7413 a bitfield or any other packed type. */
7414 if (TYPE_FIELD_BITSIZE (type, i) == 0)
7426 /* Write into appropriate registers a function return value of type
7427 TYPE, given in virtual format. */
7430 arm_store_return_value (struct type *type, struct regcache *regs,
7431 const gdb_byte *valbuf)
7433 struct gdbarch *gdbarch = get_regcache_arch (regs);
7434 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7436 if (TYPE_CODE (type) == TYPE_CODE_FLT)
7438 char buf[MAX_REGISTER_SIZE];
7440 switch (gdbarch_tdep (gdbarch)->fp_model)
7444 convert_to_extended (floatformat_from_type (type), buf, valbuf,
7445 gdbarch_byte_order (gdbarch));
7446 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
7449 case ARM_FLOAT_SOFT_FPA:
7450 case ARM_FLOAT_SOFT_VFP:
7451 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7452 not using the VFP ABI code. */
7454 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
7455 if (TYPE_LENGTH (type) > 4)
7456 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
7457 valbuf + INT_REGISTER_SIZE);
7461 internal_error (__FILE__, __LINE__,
7462 _("arm_store_return_value: Floating "
7463 "point model not supported"));
7467 else if (TYPE_CODE (type) == TYPE_CODE_INT
7468 || TYPE_CODE (type) == TYPE_CODE_CHAR
7469 || TYPE_CODE (type) == TYPE_CODE_BOOL
7470 || TYPE_CODE (type) == TYPE_CODE_PTR
7471 || TYPE_CODE (type) == TYPE_CODE_REF
7472 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7474 if (TYPE_LENGTH (type) <= 4)
7476 /* Values of one word or less are zero/sign-extended and
7478 bfd_byte tmpbuf[INT_REGISTER_SIZE];
7479 LONGEST val = unpack_long (type, valbuf);
7481 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
7482 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
7486 /* Integral values greater than one word are stored in consecutive
7487 registers starting with r0. This will always be a multiple of
7488 the regiser size. */
7489 int len = TYPE_LENGTH (type);
7490 int regno = ARM_A1_REGNUM;
7494 regcache_cooked_write (regs, regno++, valbuf);
7495 len -= INT_REGISTER_SIZE;
7496 valbuf += INT_REGISTER_SIZE;
7502 /* For a structure or union the behaviour is as if the value had
7503 been stored to word-aligned memory and then loaded into
7504 registers with 32-bit load instruction(s). */
7505 int len = TYPE_LENGTH (type);
7506 int regno = ARM_A1_REGNUM;
7507 bfd_byte tmpbuf[INT_REGISTER_SIZE];
7511 memcpy (tmpbuf, valbuf,
7512 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
7513 regcache_cooked_write (regs, regno++, tmpbuf);
7514 len -= INT_REGISTER_SIZE;
7515 valbuf += INT_REGISTER_SIZE;
7521 /* Handle function return values. */
7523 static enum return_value_convention
7524 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
7525 struct type *valtype, struct regcache *regcache,
7526 gdb_byte *readbuf, const gdb_byte *writebuf)
7528 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7529 enum arm_vfp_cprc_base_type vfp_base_type;
7532 if (arm_vfp_abi_for_function (gdbarch, func_type)
7533 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
7535 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
7536 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
7538 for (i = 0; i < vfp_base_count; i++)
7540 if (reg_char == 'q')
7543 arm_neon_quad_write (gdbarch, regcache, i,
7544 writebuf + i * unit_length);
7547 arm_neon_quad_read (gdbarch, regcache, i,
7548 readbuf + i * unit_length);
7555 sprintf (name_buf, "%c%d", reg_char, i);
7556 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
7559 regcache_cooked_write (regcache, regnum,
7560 writebuf + i * unit_length);
7562 regcache_cooked_read (regcache, regnum,
7563 readbuf + i * unit_length);
7566 return RETURN_VALUE_REGISTER_CONVENTION;
7569 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
7570 || TYPE_CODE (valtype) == TYPE_CODE_UNION
7571 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
7573 if (tdep->struct_return == pcc_struct_return
7574 || arm_return_in_memory (gdbarch, valtype))
7575 return RETURN_VALUE_STRUCT_CONVENTION;
7579 arm_store_return_value (valtype, regcache, writebuf);
7582 arm_extract_return_value (valtype, regcache, readbuf);
7584 return RETURN_VALUE_REGISTER_CONVENTION;
7589 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
7591 struct gdbarch *gdbarch = get_frame_arch (frame);
7592 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7593 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7595 char buf[INT_REGISTER_SIZE];
7597 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
7599 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
7603 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
7607 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
7608 return the target PC. Otherwise return 0. */
7611 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
7615 CORE_ADDR start_addr;
7617 /* Find the starting address and name of the function containing the PC. */
7618 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
7621 /* If PC is in a Thumb call or return stub, return the address of the
7622 target PC, which is in a register. The thunk functions are called
7623 _call_via_xx, where x is the register name. The possible names
7624 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
7625 functions, named __ARM_call_via_r[0-7]. */
7626 if (strncmp (name, "_call_via_", 10) == 0
7627 || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
7629 /* Use the name suffix to determine which register contains the
7631 static char *table[15] =
7632 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7633 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
7636 int offset = strlen (name) - 2;
7638 for (regno = 0; regno <= 14; regno++)
7639 if (strcmp (&name[offset], table[regno]) == 0)
7640 return get_frame_register_unsigned (frame, regno);
7643 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
7644 non-interworking calls to foo. We could decode the stubs
7645 to find the target but it's easier to use the symbol table. */
7646 namelen = strlen (name);
7647 if (name[0] == '_' && name[1] == '_'
7648 && ((namelen > 2 + strlen ("_from_thumb")
7649 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
7650 strlen ("_from_thumb")) == 0)
7651 || (namelen > 2 + strlen ("_from_arm")
7652 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
7653 strlen ("_from_arm")) == 0)))
7656 int target_len = namelen - 2;
7657 struct minimal_symbol *minsym;
7658 struct objfile *objfile;
7659 struct obj_section *sec;
7661 if (name[namelen - 1] == 'b')
7662 target_len -= strlen ("_from_thumb");
7664 target_len -= strlen ("_from_arm");
7666 target_name = alloca (target_len + 1);
7667 memcpy (target_name, name + 2, target_len);
7668 target_name[target_len] = '\0';
7670 sec = find_pc_section (pc);
7671 objfile = (sec == NULL) ? NULL : sec->objfile;
7672 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
7674 return SYMBOL_VALUE_ADDRESS (minsym);
7679 return 0; /* not a stub */
7683 set_arm_command (char *args, int from_tty)
7685 printf_unfiltered (_("\
7686 \"set arm\" must be followed by an apporpriate subcommand.\n"));
7687 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
7691 show_arm_command (char *args, int from_tty)
7693 cmd_show_list (showarmcmdlist, from_tty, "");
7697 arm_update_current_architecture (void)
7699 struct gdbarch_info info;
7701 /* If the current architecture is not ARM, we have nothing to do. */
7702 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
7705 /* Update the architecture. */
7706 gdbarch_info_init (&info);
7708 if (!gdbarch_update_p (info))
7709 internal_error (__FILE__, __LINE__, _("could not update architecture"));
7713 set_fp_model_sfunc (char *args, int from_tty,
7714 struct cmd_list_element *c)
7716 enum arm_float_model fp_model;
7718 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
7719 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
7721 arm_fp_model = fp_model;
7725 if (fp_model == ARM_FLOAT_LAST)
7726 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
7729 arm_update_current_architecture ();
7733 show_fp_model (struct ui_file *file, int from_tty,
7734 struct cmd_list_element *c, const char *value)
7736 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
7738 if (arm_fp_model == ARM_FLOAT_AUTO
7739 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
7740 fprintf_filtered (file, _("\
7741 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
7742 fp_model_strings[tdep->fp_model]);
7744 fprintf_filtered (file, _("\
7745 The current ARM floating point model is \"%s\".\n"),
7746 fp_model_strings[arm_fp_model]);
7750 arm_set_abi (char *args, int from_tty,
7751 struct cmd_list_element *c)
7753 enum arm_abi_kind arm_abi;
7755 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
7756 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
7758 arm_abi_global = arm_abi;
7762 if (arm_abi == ARM_ABI_LAST)
7763 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
7766 arm_update_current_architecture ();
7770 arm_show_abi (struct ui_file *file, int from_tty,
7771 struct cmd_list_element *c, const char *value)
7773 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
7775 if (arm_abi_global == ARM_ABI_AUTO
7776 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
7777 fprintf_filtered (file, _("\
7778 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
7779 arm_abi_strings[tdep->arm_abi]);
7781 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
7786 arm_show_fallback_mode (struct ui_file *file, int from_tty,
7787 struct cmd_list_element *c, const char *value)
7789 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
7791 fprintf_filtered (file,
7792 _("The current execution mode assumed "
7793 "(when symbols are unavailable) is \"%s\".\n"),
7794 arm_fallback_mode_string);
7798 arm_show_force_mode (struct ui_file *file, int from_tty,
7799 struct cmd_list_element *c, const char *value)
7801 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
7803 fprintf_filtered (file,
7804 _("The current execution mode assumed "
7805 "(even when symbols are available) is \"%s\".\n"),
7806 arm_force_mode_string);
7809 /* If the user changes the register disassembly style used for info
7810 register and other commands, we have to also switch the style used
7811 in opcodes for disassembly output. This function is run in the "set
7812 arm disassembly" command, and does that. */
7815 set_disassembly_style_sfunc (char *args, int from_tty,
7816 struct cmd_list_element *c)
7818 set_disassembly_style ();
7821 /* Return the ARM register name corresponding to register I. */
7823 arm_register_name (struct gdbarch *gdbarch, int i)
7825 const int num_regs = gdbarch_num_regs (gdbarch);
7827 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
7828 && i >= num_regs && i < num_regs + 32)
7830 static const char *const vfp_pseudo_names[] = {
7831 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
7832 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
7833 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
7834 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
7837 return vfp_pseudo_names[i - num_regs];
7840 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
7841 && i >= num_regs + 32 && i < num_regs + 32 + 16)
7843 static const char *const neon_pseudo_names[] = {
7844 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
7845 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
7848 return neon_pseudo_names[i - num_regs - 32];
7851 if (i >= ARRAY_SIZE (arm_register_names))
7852 /* These registers are only supported on targets which supply
7853 an XML description. */
7856 return arm_register_names[i];
7860 set_disassembly_style (void)
7864 /* Find the style that the user wants. */
7865 for (current = 0; current < num_disassembly_options; current++)
7866 if (disassembly_style == valid_disassembly_styles[current])
7868 gdb_assert (current < num_disassembly_options);
7870 /* Synchronize the disassembler. */
7871 set_arm_regname_option (current);
7874 /* Test whether the coff symbol specific value corresponds to a Thumb
7878 coff_sym_is_thumb (int val)
7880 return (val == C_THUMBEXT
7881 || val == C_THUMBSTAT
7882 || val == C_THUMBEXTFUNC
7883 || val == C_THUMBSTATFUNC
7884 || val == C_THUMBLABEL);
7887 /* arm_coff_make_msymbol_special()
7888 arm_elf_make_msymbol_special()
7890 These functions test whether the COFF or ELF symbol corresponds to
7891 an address in thumb code, and set a "special" bit in a minimal
7892 symbol to indicate that it does. */
7895 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
7897 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
7898 == ST_BRANCH_TO_THUMB)
7899 MSYMBOL_SET_SPECIAL (msym);
7903 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
7905 if (coff_sym_is_thumb (val))
7906 MSYMBOL_SET_SPECIAL (msym);
7910 arm_objfile_data_free (struct objfile *objfile, void *arg)
7912 struct arm_per_objfile *data = arg;
7915 for (i = 0; i < objfile->obfd->section_count; i++)
7916 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
7920 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
7923 const char *name = bfd_asymbol_name (sym);
7924 struct arm_per_objfile *data;
7925 VEC(arm_mapping_symbol_s) **map_p;
7926 struct arm_mapping_symbol new_map_sym;
7928 gdb_assert (name[0] == '$');
7929 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
7932 data = objfile_data (objfile, arm_objfile_data_key);
7935 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
7936 struct arm_per_objfile);
7937 set_objfile_data (objfile, arm_objfile_data_key, data);
7938 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
7939 objfile->obfd->section_count,
7940 VEC(arm_mapping_symbol_s) *);
7942 map_p = &data->section_maps[bfd_get_section (sym)->index];
7944 new_map_sym.value = sym->value;
7945 new_map_sym.type = name[1];
7947 /* Assume that most mapping symbols appear in order of increasing
7948 value. If they were randomly distributed, it would be faster to
7949 always push here and then sort at first use. */
7950 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
7952 struct arm_mapping_symbol *prev_map_sym;
7954 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
7955 if (prev_map_sym->value >= sym->value)
7958 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
7959 arm_compare_mapping_symbols);
7960 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
7965 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
7969 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
7971 struct gdbarch *gdbarch = get_regcache_arch (regcache);
7972 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
7974 /* If necessary, set the T bit. */
7977 ULONGEST val, t_bit;
7978 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
7979 t_bit = arm_psr_thumb_bit (gdbarch);
7980 if (arm_pc_is_thumb (gdbarch, pc))
7981 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
7984 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
7989 /* Read the contents of a NEON quad register, by reading from two
7990 double registers. This is used to implement the quad pseudo
7991 registers, and for argument passing in case the quad registers are
7992 missing; vectors are passed in quad registers when using the VFP
7993 ABI, even if a NEON unit is not present. REGNUM is the index of
7994 the quad register, in [0, 15]. */
7996 static enum register_status
7997 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
7998 int regnum, gdb_byte *buf)
8001 gdb_byte reg_buf[8];
8002 int offset, double_regnum;
8003 enum register_status status;
8005 sprintf (name_buf, "d%d", regnum << 1);
8006 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8009 /* d0 is always the least significant half of q0. */
8010 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8015 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8016 if (status != REG_VALID)
8018 memcpy (buf + offset, reg_buf, 8);
8020 offset = 8 - offset;
8021 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
8022 if (status != REG_VALID)
8024 memcpy (buf + offset, reg_buf, 8);
8029 static enum register_status
8030 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
8031 int regnum, gdb_byte *buf)
8033 const int num_regs = gdbarch_num_regs (gdbarch);
8035 gdb_byte reg_buf[8];
8036 int offset, double_regnum;
8038 gdb_assert (regnum >= num_regs);
8041 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8042 /* Quad-precision register. */
8043 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
8046 enum register_status status;
8048 /* Single-precision register. */
8049 gdb_assert (regnum < 32);
8051 /* s0 is always the least significant half of d0. */
8052 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8053 offset = (regnum & 1) ? 0 : 4;
8055 offset = (regnum & 1) ? 4 : 0;
8057 sprintf (name_buf, "d%d", regnum >> 1);
8058 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8061 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8062 if (status == REG_VALID)
8063 memcpy (buf, reg_buf + offset, 4);
8068 /* Store the contents of BUF to a NEON quad register, by writing to
8069 two double registers. This is used to implement the quad pseudo
8070 registers, and for argument passing in case the quad registers are
8071 missing; vectors are passed in quad registers when using the VFP
8072 ABI, even if a NEON unit is not present. REGNUM is the index
8073 of the quad register, in [0, 15]. */
8076 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
8077 int regnum, const gdb_byte *buf)
8080 gdb_byte reg_buf[8];
8081 int offset, double_regnum;
8083 sprintf (name_buf, "d%d", regnum << 1);
8084 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8087 /* d0 is always the least significant half of q0. */
8088 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8093 regcache_raw_write (regcache, double_regnum, buf + offset);
8094 offset = 8 - offset;
8095 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
8099 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
8100 int regnum, const gdb_byte *buf)
8102 const int num_regs = gdbarch_num_regs (gdbarch);
8104 gdb_byte reg_buf[8];
8105 int offset, double_regnum;
8107 gdb_assert (regnum >= num_regs);
8110 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8111 /* Quad-precision register. */
8112 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
8115 /* Single-precision register. */
8116 gdb_assert (regnum < 32);
8118 /* s0 is always the least significant half of d0. */
8119 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8120 offset = (regnum & 1) ? 0 : 4;
8122 offset = (regnum & 1) ? 4 : 0;
8124 sprintf (name_buf, "d%d", regnum >> 1);
8125 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8128 regcache_raw_read (regcache, double_regnum, reg_buf);
8129 memcpy (reg_buf + offset, buf, 4);
8130 regcache_raw_write (regcache, double_regnum, reg_buf);
8134 static struct value *
8135 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
8137 const int *reg_p = baton;
8138 return value_of_register (*reg_p, frame);
8141 static enum gdb_osabi
8142 arm_elf_osabi_sniffer (bfd *abfd)
8144 unsigned int elfosabi;
8145 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
8147 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
8149 if (elfosabi == ELFOSABI_ARM)
8150 /* GNU tools use this value. Check note sections in this case,
8152 bfd_map_over_sections (abfd,
8153 generic_elf_osabi_sniff_abi_tag_sections,
8156 /* Anything else will be handled by the generic ELF sniffer. */
8161 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
8162 struct reggroup *group)
8164 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8165 this, FPS register belongs to save_regroup, restore_reggroup, and
8166 all_reggroup, of course. */
8167 if (regnum == ARM_FPS_REGNUM)
8168 return (group == float_reggroup
8169 || group == save_reggroup
8170 || group == restore_reggroup
8171 || group == all_reggroup);
8173 return default_register_reggroup_p (gdbarch, regnum, group);
8177 /* Initialize the current architecture based on INFO. If possible,
8178 re-use an architecture from ARCHES, which is a list of
8179 architectures already created during this debugging session.
8181 Called e.g. at program startup, when reading a core file, and when
8182 reading a binary file. */
8184 static struct gdbarch *
8185 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8187 struct gdbarch_tdep *tdep;
8188 struct gdbarch *gdbarch;
8189 struct gdbarch_list *best_arch;
8190 enum arm_abi_kind arm_abi = arm_abi_global;
8191 enum arm_float_model fp_model = arm_fp_model;
8192 struct tdesc_arch_data *tdesc_data = NULL;
8194 int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
8196 int have_fpa_registers = 1;
8197 const struct target_desc *tdesc = info.target_desc;
8199 /* If we have an object to base this architecture on, try to determine
8202 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
8204 int ei_osabi, e_flags;
8206 switch (bfd_get_flavour (info.abfd))
8208 case bfd_target_aout_flavour:
8209 /* Assume it's an old APCS-style ABI. */
8210 arm_abi = ARM_ABI_APCS;
8213 case bfd_target_coff_flavour:
8214 /* Assume it's an old APCS-style ABI. */
8216 arm_abi = ARM_ABI_APCS;
8219 case bfd_target_elf_flavour:
8220 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
8221 e_flags = elf_elfheader (info.abfd)->e_flags;
8223 if (ei_osabi == ELFOSABI_ARM)
8225 /* GNU tools used to use this value, but do not for EABI
8226 objects. There's nowhere to tag an EABI version
8227 anyway, so assume APCS. */
8228 arm_abi = ARM_ABI_APCS;
8230 else if (ei_osabi == ELFOSABI_NONE)
8232 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
8233 int attr_arch, attr_profile;
8237 case EF_ARM_EABI_UNKNOWN:
8238 /* Assume GNU tools. */
8239 arm_abi = ARM_ABI_APCS;
8242 case EF_ARM_EABI_VER4:
8243 case EF_ARM_EABI_VER5:
8244 arm_abi = ARM_ABI_AAPCS;
8245 /* EABI binaries default to VFP float ordering.
8246 They may also contain build attributes that can
8247 be used to identify if the VFP argument-passing
8249 if (fp_model == ARM_FLOAT_AUTO)
8252 switch (bfd_elf_get_obj_attr_int (info.abfd,
8257 /* "The user intended FP parameter/result
8258 passing to conform to AAPCS, base
8260 fp_model = ARM_FLOAT_SOFT_VFP;
8263 /* "The user intended FP parameter/result
8264 passing to conform to AAPCS, VFP
8266 fp_model = ARM_FLOAT_VFP;
8269 /* "The user intended FP parameter/result
8270 passing to conform to tool chain-specific
8271 conventions" - we don't know any such
8272 conventions, so leave it as "auto". */
8275 /* Attribute value not mentioned in the
8276 October 2008 ABI, so leave it as
8281 fp_model = ARM_FLOAT_SOFT_VFP;
8287 /* Leave it as "auto". */
8288 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
8293 /* Detect M-profile programs. This only works if the
8294 executable file includes build attributes; GCC does
8295 copy them to the executable, but e.g. RealView does
8297 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
8299 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
8301 Tag_CPU_arch_profile);
8302 /* GCC specifies the profile for v6-M; RealView only
8303 specifies the profile for architectures starting with
8304 V7 (as opposed to architectures with a tag
8305 numerically greater than TAG_CPU_ARCH_V7). */
8306 if (!tdesc_has_registers (tdesc)
8307 && (attr_arch == TAG_CPU_ARCH_V6_M
8308 || attr_arch == TAG_CPU_ARCH_V6S_M
8309 || attr_profile == 'M'))
8310 tdesc = tdesc_arm_with_m;
8314 if (fp_model == ARM_FLOAT_AUTO)
8316 int e_flags = elf_elfheader (info.abfd)->e_flags;
8318 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
8321 /* Leave it as "auto". Strictly speaking this case
8322 means FPA, but almost nobody uses that now, and
8323 many toolchains fail to set the appropriate bits
8324 for the floating-point model they use. */
8326 case EF_ARM_SOFT_FLOAT:
8327 fp_model = ARM_FLOAT_SOFT_FPA;
8329 case EF_ARM_VFP_FLOAT:
8330 fp_model = ARM_FLOAT_VFP;
8332 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
8333 fp_model = ARM_FLOAT_SOFT_VFP;
8338 if (e_flags & EF_ARM_BE8)
8339 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
8344 /* Leave it as "auto". */
8349 /* Check any target description for validity. */
8350 if (tdesc_has_registers (tdesc))
8352 /* For most registers we require GDB's default names; but also allow
8353 the numeric names for sp / lr / pc, as a convenience. */
8354 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
8355 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
8356 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
8358 const struct tdesc_feature *feature;
8361 feature = tdesc_find_feature (tdesc,
8362 "org.gnu.gdb.arm.core");
8363 if (feature == NULL)
8365 feature = tdesc_find_feature (tdesc,
8366 "org.gnu.gdb.arm.m-profile");
8367 if (feature == NULL)
8373 tdesc_data = tdesc_data_alloc ();
8376 for (i = 0; i < ARM_SP_REGNUM; i++)
8377 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8378 arm_register_names[i]);
8379 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8382 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8385 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
8389 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8390 ARM_PS_REGNUM, "xpsr");
8392 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8393 ARM_PS_REGNUM, "cpsr");
8397 tdesc_data_cleanup (tdesc_data);
8401 feature = tdesc_find_feature (tdesc,
8402 "org.gnu.gdb.arm.fpa");
8403 if (feature != NULL)
8406 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
8407 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8408 arm_register_names[i]);
8411 tdesc_data_cleanup (tdesc_data);
8416 have_fpa_registers = 0;
8418 feature = tdesc_find_feature (tdesc,
8419 "org.gnu.gdb.xscale.iwmmxt");
8420 if (feature != NULL)
8422 static const char *const iwmmxt_names[] = {
8423 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
8424 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
8425 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
8426 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
8430 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
8432 &= tdesc_numbered_register (feature, tdesc_data, i,
8433 iwmmxt_names[i - ARM_WR0_REGNUM]);
8435 /* Check for the control registers, but do not fail if they
8437 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
8438 tdesc_numbered_register (feature, tdesc_data, i,
8439 iwmmxt_names[i - ARM_WR0_REGNUM]);
8441 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
8443 &= tdesc_numbered_register (feature, tdesc_data, i,
8444 iwmmxt_names[i - ARM_WR0_REGNUM]);
8448 tdesc_data_cleanup (tdesc_data);
8453 /* If we have a VFP unit, check whether the single precision registers
8454 are present. If not, then we will synthesize them as pseudo
8456 feature = tdesc_find_feature (tdesc,
8457 "org.gnu.gdb.arm.vfp");
8458 if (feature != NULL)
8460 static const char *const vfp_double_names[] = {
8461 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8462 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
8463 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
8464 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
8467 /* Require the double precision registers. There must be either
8470 for (i = 0; i < 32; i++)
8472 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8474 vfp_double_names[i]);
8478 if (!valid_p && i == 16)
8481 /* Also require FPSCR. */
8482 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8483 ARM_FPSCR_REGNUM, "fpscr");
8486 tdesc_data_cleanup (tdesc_data);
8490 if (tdesc_unnumbered_register (feature, "s0") == 0)
8491 have_vfp_pseudos = 1;
8493 have_vfp_registers = 1;
8495 /* If we have VFP, also check for NEON. The architecture allows
8496 NEON without VFP (integer vector operations only), but GDB
8497 does not support that. */
8498 feature = tdesc_find_feature (tdesc,
8499 "org.gnu.gdb.arm.neon");
8500 if (feature != NULL)
8502 /* NEON requires 32 double-precision registers. */
8505 tdesc_data_cleanup (tdesc_data);
8509 /* If there are quad registers defined by the stub, use
8510 their type; otherwise (normally) provide them with
8511 the default type. */
8512 if (tdesc_unnumbered_register (feature, "q0") == 0)
8513 have_neon_pseudos = 1;
8520 /* If there is already a candidate, use it. */
8521 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
8523 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
8525 if (arm_abi != ARM_ABI_AUTO
8526 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
8529 if (fp_model != ARM_FLOAT_AUTO
8530 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
8533 /* There are various other properties in tdep that we do not
8534 need to check here: those derived from a target description,
8535 since gdbarches with a different target description are
8536 automatically disqualified. */
8538 /* Do check is_m, though, since it might come from the binary. */
8539 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
8542 /* Found a match. */
8546 if (best_arch != NULL)
8548 if (tdesc_data != NULL)
8549 tdesc_data_cleanup (tdesc_data);
8550 return best_arch->gdbarch;
8553 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
8554 gdbarch = gdbarch_alloc (&info, tdep);
8556 /* Record additional information about the architecture we are defining.
8557 These are gdbarch discriminators, like the OSABI. */
8558 tdep->arm_abi = arm_abi;
8559 tdep->fp_model = fp_model;
8561 tdep->have_fpa_registers = have_fpa_registers;
8562 tdep->have_vfp_registers = have_vfp_registers;
8563 tdep->have_vfp_pseudos = have_vfp_pseudos;
8564 tdep->have_neon_pseudos = have_neon_pseudos;
8565 tdep->have_neon = have_neon;
8568 switch (info.byte_order_for_code)
8570 case BFD_ENDIAN_BIG:
8571 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
8572 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
8573 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
8574 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
8578 case BFD_ENDIAN_LITTLE:
8579 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
8580 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
8581 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
8582 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
8587 internal_error (__FILE__, __LINE__,
8588 _("arm_gdbarch_init: bad byte order for float format"));
8591 /* On ARM targets char defaults to unsigned. */
8592 set_gdbarch_char_signed (gdbarch, 0);
8594 /* Note: for displaced stepping, this includes the breakpoint, and one word
8595 of additional scratch space. This setting isn't used for anything beside
8596 displaced stepping at present. */
8597 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
8599 /* This should be low enough for everything. */
8600 tdep->lowest_pc = 0x20;
8601 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
8603 /* The default, for both APCS and AAPCS, is to return small
8604 structures in registers. */
8605 tdep->struct_return = reg_struct_return;
8607 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
8608 set_gdbarch_frame_align (gdbarch, arm_frame_align);
8610 set_gdbarch_write_pc (gdbarch, arm_write_pc);
8612 /* Frame handling. */
8613 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
8614 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
8615 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
8617 frame_base_set_default (gdbarch, &arm_normal_base);
8619 /* Address manipulation. */
8620 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
8621 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
8623 /* Advance PC across function entry code. */
8624 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
8626 /* Detect whether PC is in function epilogue. */
8627 set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
8629 /* Skip trampolines. */
8630 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
8632 /* The stack grows downward. */
8633 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8635 /* Breakpoint manipulation. */
8636 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
8637 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
8638 arm_remote_breakpoint_from_pc);
8640 /* Information about registers, etc. */
8641 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
8642 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
8643 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
8644 set_gdbarch_register_type (gdbarch, arm_register_type);
8645 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
8647 /* This "info float" is FPA-specific. Use the generic version if we
8649 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
8650 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
8652 /* Internal <-> external register number maps. */
8653 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
8654 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
8656 set_gdbarch_register_name (gdbarch, arm_register_name);
8658 /* Returning results. */
8659 set_gdbarch_return_value (gdbarch, arm_return_value);
8662 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
8664 /* Minsymbol frobbing. */
8665 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
8666 set_gdbarch_coff_make_msymbol_special (gdbarch,
8667 arm_coff_make_msymbol_special);
8668 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
8670 /* Thumb-2 IT block support. */
8671 set_gdbarch_adjust_breakpoint_address (gdbarch,
8672 arm_adjust_breakpoint_address);
8674 /* Virtual tables. */
8675 set_gdbarch_vbit_in_delta (gdbarch, 1);
8677 /* Hook in the ABI-specific overrides, if they have been registered. */
8678 gdbarch_init_osabi (info, gdbarch);
8680 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
8682 /* Add some default predicates. */
8683 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
8684 dwarf2_append_unwinders (gdbarch);
8685 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
8686 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
8688 /* Now we have tuned the configuration, set a few final things,
8689 based on what the OS ABI has told us. */
8691 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
8692 binaries are always marked. */
8693 if (tdep->arm_abi == ARM_ABI_AUTO)
8694 tdep->arm_abi = ARM_ABI_APCS;
8696 /* Watchpoints are not steppable. */
8697 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8699 /* We used to default to FPA for generic ARM, but almost nobody
8700 uses that now, and we now provide a way for the user to force
8701 the model. So default to the most useful variant. */
8702 if (tdep->fp_model == ARM_FLOAT_AUTO)
8703 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
8705 if (tdep->jb_pc >= 0)
8706 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
8708 /* Floating point sizes and format. */
8709 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
8710 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
8712 set_gdbarch_double_format
8713 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
8714 set_gdbarch_long_double_format
8715 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
8719 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
8720 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
8723 if (have_vfp_pseudos)
8725 /* NOTE: These are the only pseudo registers used by
8726 the ARM target at the moment. If more are added, a
8727 little more care in numbering will be needed. */
8729 int num_pseudos = 32;
8730 if (have_neon_pseudos)
8732 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
8733 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
8734 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
8739 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
8741 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8743 /* Override tdesc_register_type to adjust the types of VFP
8744 registers for NEON. */
8745 set_gdbarch_register_type (gdbarch, arm_register_type);
8748 /* Add standard register aliases. We add aliases even for those
8749 nanes which are used by the current architecture - it's simpler,
8750 and does no harm, since nothing ever lists user registers. */
8751 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
8752 user_reg_add (gdbarch, arm_register_aliases[i].name,
8753 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
8759 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
8761 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8766 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
8767 (unsigned long) tdep->lowest_pc);
8770 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
8773 _initialize_arm_tdep (void)
8775 struct ui_file *stb;
8777 struct cmd_list_element *new_set, *new_show;
8778 const char *setname;
8779 const char *setdesc;
8780 const char *const *regnames;
8782 static char *helptext;
8783 char regdesc[1024], *rdptr = regdesc;
8784 size_t rest = sizeof (regdesc);
8786 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
8788 arm_objfile_data_key
8789 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
8791 /* Add ourselves to objfile event chain. */
8792 observer_attach_new_objfile (arm_exidx_new_objfile);
8794 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
8796 /* Register an ELF OS ABI sniffer for ARM binaries. */
8797 gdbarch_register_osabi_sniffer (bfd_arch_arm,
8798 bfd_target_elf_flavour,
8799 arm_elf_osabi_sniffer);
8801 /* Initialize the standard target descriptions. */
8802 initialize_tdesc_arm_with_m ();
8804 /* Get the number of possible sets of register names defined in opcodes. */
8805 num_disassembly_options = get_arm_regname_num_options ();
8807 /* Add root prefix command for all "set arm"/"show arm" commands. */
8808 add_prefix_cmd ("arm", no_class, set_arm_command,
8809 _("Various ARM-specific commands."),
8810 &setarmcmdlist, "set arm ", 0, &setlist);
8812 add_prefix_cmd ("arm", no_class, show_arm_command,
8813 _("Various ARM-specific commands."),
8814 &showarmcmdlist, "show arm ", 0, &showlist);
8816 /* Sync the opcode insn printer with our register viewer. */
8817 parse_arm_disassembler_option ("reg-names-std");
8819 /* Initialize the array that will be passed to
8820 add_setshow_enum_cmd(). */
8821 valid_disassembly_styles
8822 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
8823 for (i = 0; i < num_disassembly_options; i++)
8825 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
8826 valid_disassembly_styles[i] = setname;
8827 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
8830 /* When we find the default names, tell the disassembler to use
8832 if (!strcmp (setname, "std"))
8834 disassembly_style = setname;
8835 set_arm_regname_option (i);
8838 /* Mark the end of valid options. */
8839 valid_disassembly_styles[num_disassembly_options] = NULL;
8841 /* Create the help text. */
8842 stb = mem_fileopen ();
8843 fprintf_unfiltered (stb, "%s%s%s",
8844 _("The valid values are:\n"),
8846 _("The default is \"std\"."));
8847 helptext = ui_file_xstrdup (stb, NULL);
8848 ui_file_delete (stb);
8850 add_setshow_enum_cmd("disassembler", no_class,
8851 valid_disassembly_styles, &disassembly_style,
8852 _("Set the disassembly style."),
8853 _("Show the disassembly style."),
8855 set_disassembly_style_sfunc,
8856 NULL, /* FIXME: i18n: The disassembly style is
8858 &setarmcmdlist, &showarmcmdlist);
8860 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
8861 _("Set usage of ARM 32-bit mode."),
8862 _("Show usage of ARM 32-bit mode."),
8863 _("When off, a 26-bit PC will be used."),
8865 NULL, /* FIXME: i18n: Usage of ARM 32-bit
8867 &setarmcmdlist, &showarmcmdlist);
8869 /* Add a command to allow the user to force the FPU model. */
8870 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
8871 _("Set the floating point type."),
8872 _("Show the floating point type."),
8873 _("auto - Determine the FP typefrom the OS-ABI.\n\
8874 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
8875 fpa - FPA co-processor (GCC compiled).\n\
8876 softvfp - Software FP with pure-endian doubles.\n\
8877 vfp - VFP co-processor."),
8878 set_fp_model_sfunc, show_fp_model,
8879 &setarmcmdlist, &showarmcmdlist);
8881 /* Add a command to allow the user to force the ABI. */
8882 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
8885 NULL, arm_set_abi, arm_show_abi,
8886 &setarmcmdlist, &showarmcmdlist);
8888 /* Add two commands to allow the user to force the assumed
8890 add_setshow_enum_cmd ("fallback-mode", class_support,
8891 arm_mode_strings, &arm_fallback_mode_string,
8892 _("Set the mode assumed when symbols are unavailable."),
8893 _("Show the mode assumed when symbols are unavailable."),
8894 NULL, NULL, arm_show_fallback_mode,
8895 &setarmcmdlist, &showarmcmdlist);
8896 add_setshow_enum_cmd ("force-mode", class_support,
8897 arm_mode_strings, &arm_force_mode_string,
8898 _("Set the mode assumed even when symbols are available."),
8899 _("Show the mode assumed even when symbols are available."),
8900 NULL, NULL, arm_show_force_mode,
8901 &setarmcmdlist, &showarmcmdlist);
8903 /* Debugging flag. */
8904 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
8905 _("Set ARM debugging."),
8906 _("Show ARM debugging."),
8907 _("When on, arm-specific debugging is enabled."),
8909 NULL, /* FIXME: i18n: "ARM debugging is %s. */
8910 &setdebuglist, &showdebuglist);