1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "arch/arm-get-next-pcs.h"
52 #include "gdb/sim-arm.h"
55 #include "coff/internal.h"
61 #include "record-full.h"
64 #include "features/arm/arm-with-m.c"
65 #include "features/arm/arm-with-m-fpa-layout.c"
66 #include "features/arm/arm-with-m-vfp-d16.c"
67 #include "features/arm/arm-with-iwmmxt.c"
68 #include "features/arm/arm-with-vfpv2.c"
69 #include "features/arm/arm-with-vfpv3.c"
70 #include "features/arm/arm-with-neon.c"
78 /* Macros for setting and testing a bit in a minimal symbol that marks
79 it as Thumb function. The MSB of the minimal symbol's "info" field
80 is used for this purpose.
82 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
83 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_TARGET_FLAG_1 (msym) = 1
88 #define MSYMBOL_IS_SPECIAL(msym) \
89 MSYMBOL_TARGET_FLAG_1 (msym)
91 /* Per-objfile data used for mapping symbols. */
92 static const struct objfile_data *arm_objfile_data_key;
94 struct arm_mapping_symbol
99 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
100 DEF_VEC_O(arm_mapping_symbol_s);
102 struct arm_per_objfile
104 VEC(arm_mapping_symbol_s) **section_maps;
107 /* The list of available "set arm ..." and "show arm ..." commands. */
108 static struct cmd_list_element *setarmcmdlist = NULL;
109 static struct cmd_list_element *showarmcmdlist = NULL;
111 /* The type of floating-point to use. Keep this in sync with enum
112 arm_float_model, and the help string in _initialize_arm_tdep. */
113 static const char *const fp_model_strings[] =
123 /* A variable that can be configured by the user. */
124 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
125 static const char *current_fp_model = "auto";
127 /* The ABI to use. Keep this in sync with arm_abi_kind. */
128 static const char *const arm_abi_strings[] =
136 /* A variable that can be configured by the user. */
137 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
138 static const char *arm_abi_string = "auto";
140 /* The execution mode to assume. */
141 static const char *const arm_mode_strings[] =
149 static const char *arm_fallback_mode_string = "auto";
150 static const char *arm_force_mode_string = "auto";
152 /* The standard register names, and all the valid aliases for them. Note
153 that `fp', `sp' and `pc' are not added in this alias list, because they
154 have been added as builtin user registers in
155 std-regs.c:_initialize_frame_reg. */
160 } arm_register_aliases[] = {
161 /* Basic register numbers. */
178 /* Synonyms (argument and variable registers). */
191 /* Other platform-specific names for r9. */
197 /* Names used by GCC (not listed in the ARM EABI). */
199 /* A special name from the older ATPCS. */
203 static const char *const arm_register_names[] =
204 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
205 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
206 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
207 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
208 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
209 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
210 "fps", "cpsr" }; /* 24 25 */
212 /* Holds the current set of options to be passed to the disassembler. */
213 static char *arm_disassembler_options;
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element *);
225 static void show_disassembly_style_sfunc (struct ui_file *, int,
226 struct cmd_list_element *,
229 static void convert_from_extended (const struct floatformat *, const void *,
231 static void convert_to_extended (const struct floatformat *, void *,
234 static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
235 struct regcache *regcache,
236 int regnum, gdb_byte *buf);
237 static void arm_neon_quad_write (struct gdbarch *gdbarch,
238 struct regcache *regcache,
239 int regnum, const gdb_byte *buf);
242 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self);
245 /* get_next_pcs operations. */
246 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = {
247 arm_get_next_pcs_read_memory_unsigned_integer,
248 arm_get_next_pcs_syscall_next_pc,
249 arm_get_next_pcs_addr_bits_remove,
250 arm_get_next_pcs_is_thumb,
254 struct arm_prologue_cache
256 /* The stack pointer at the time this frame was created; i.e. the
257 caller's stack pointer when this function was called. It is used
258 to identify this frame. */
261 /* The frame base for this frame is just prev_sp - frame size.
262 FRAMESIZE is the distance from the frame pointer to the
263 initial stack pointer. */
267 /* The register used to hold the frame pointer for this frame. */
270 /* Saved register offsets. */
271 struct trad_frame_saved_reg *saved_regs;
274 static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch,
275 CORE_ADDR prologue_start,
276 CORE_ADDR prologue_end,
277 struct arm_prologue_cache *cache);
279 /* Architecture version for displaced stepping. This effects the behaviour of
280 certain instructions, and really should not be hard-wired. */
282 #define DISPLACED_STEPPING_ARCH_VERSION 5
284 /* Set to true if the 32-bit mode is in use. */
288 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
291 arm_psr_thumb_bit (struct gdbarch *gdbarch)
293 if (gdbarch_tdep (gdbarch)->is_m)
299 /* Determine if the processor is currently executing in Thumb mode. */
302 arm_is_thumb (struct regcache *regcache)
305 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
307 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
309 return (cpsr & t_bit) != 0;
312 /* Determine if FRAME is executing in Thumb mode. */
315 arm_frame_is_thumb (struct frame_info *frame)
318 ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame));
320 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
321 directly (from a signal frame or dummy frame) or by interpreting
322 the saved LR (from a prologue or DWARF frame). So consult it and
323 trust the unwinders. */
324 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
326 return (cpsr & t_bit) != 0;
329 /* Callback for VEC_lower_bound. */
332 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
333 const struct arm_mapping_symbol *rhs)
335 return lhs->value < rhs->value;
338 /* Search for the mapping symbol covering MEMADDR. If one is found,
339 return its type. Otherwise, return 0. If START is non-NULL,
340 set *START to the location of the mapping symbol. */
343 arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start)
345 struct obj_section *sec;
347 /* If there are mapping symbols, consult them. */
348 sec = find_pc_section (memaddr);
351 struct arm_per_objfile *data;
352 VEC(arm_mapping_symbol_s) *map;
353 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
357 data = (struct arm_per_objfile *) objfile_data (sec->objfile,
358 arm_objfile_data_key);
361 map = data->section_maps[sec->the_bfd_section->index];
362 if (!VEC_empty (arm_mapping_symbol_s, map))
364 struct arm_mapping_symbol *map_sym;
366 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
367 arm_compare_mapping_symbols);
369 /* VEC_lower_bound finds the earliest ordered insertion
370 point. If the following symbol starts at this exact
371 address, we use that; otherwise, the preceding
372 mapping symbol covers this address. */
373 if (idx < VEC_length (arm_mapping_symbol_s, map))
375 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
376 if (map_sym->value == map_key.value)
379 *start = map_sym->value + obj_section_addr (sec);
380 return map_sym->type;
386 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
388 *start = map_sym->value + obj_section_addr (sec);
389 return map_sym->type;
398 /* Determine if the program counter specified in MEMADDR is in a Thumb
399 function. This function should be called for addresses unrelated to
400 any executing frame; otherwise, prefer arm_frame_is_thumb. */
403 arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr)
405 struct bound_minimal_symbol sym;
407 struct displaced_step_closure* dsc
408 = get_displaced_step_closure_by_addr(memaddr);
410 /* If checking the mode of displaced instruction in copy area, the mode
411 should be determined by instruction on the original address. */
415 fprintf_unfiltered (gdb_stdlog,
416 "displaced: check mode of %.8lx instead of %.8lx\n",
417 (unsigned long) dsc->insn_addr,
418 (unsigned long) memaddr);
419 memaddr = dsc->insn_addr;
422 /* If bit 0 of the address is set, assume this is a Thumb address. */
423 if (IS_THUMB_ADDR (memaddr))
426 /* If the user wants to override the symbol table, let him. */
427 if (strcmp (arm_force_mode_string, "arm") == 0)
429 if (strcmp (arm_force_mode_string, "thumb") == 0)
432 /* ARM v6-M and v7-M are always in Thumb mode. */
433 if (gdbarch_tdep (gdbarch)->is_m)
436 /* If there are mapping symbols, consult them. */
437 type = arm_find_mapping_symbol (memaddr, NULL);
441 /* Thumb functions have a "special" bit set in minimal symbols. */
442 sym = lookup_minimal_symbol_by_pc (memaddr);
444 return (MSYMBOL_IS_SPECIAL (sym.minsym));
446 /* If the user wants to override the fallback mode, let them. */
447 if (strcmp (arm_fallback_mode_string, "arm") == 0)
449 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
452 /* If we couldn't find any symbol, but we're talking to a running
453 target, then trust the current value of $cpsr. This lets
454 "display/i $pc" always show the correct mode (though if there is
455 a symbol table we will not reach here, so it still may not be
456 displayed in the mode it will be executed). */
457 if (target_has_registers)
458 return arm_frame_is_thumb (get_current_frame ());
460 /* Otherwise we're out of luck; we assume ARM. */
464 /* Determine if the address specified equals any of these magic return
465 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
468 From ARMv6-M Reference Manual B1.5.8
469 Table B1-5 Exception return behavior
471 EXC_RETURN Return To Return Stack
472 0xFFFFFFF1 Handler mode Main
473 0xFFFFFFF9 Thread mode Main
474 0xFFFFFFFD Thread mode Process
476 From ARMv7-M Reference Manual B1.5.8
477 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
479 EXC_RETURN Return To Return Stack
480 0xFFFFFFF1 Handler mode Main
481 0xFFFFFFF9 Thread mode Main
482 0xFFFFFFFD Thread mode Process
484 Table B1-9 EXC_RETURN definition of exception return behavior, with
487 EXC_RETURN Return To Return Stack Frame Type
488 0xFFFFFFE1 Handler mode Main Extended
489 0xFFFFFFE9 Thread mode Main Extended
490 0xFFFFFFED Thread mode Process Extended
491 0xFFFFFFF1 Handler mode Main Basic
492 0xFFFFFFF9 Thread mode Main Basic
493 0xFFFFFFFD Thread mode Process Basic
495 For more details see "B1.5.8 Exception return behavior"
496 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
499 arm_m_addr_is_magic (CORE_ADDR addr)
503 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
504 the exception return behavior. */
511 /* Address is magic. */
515 /* Address is not magic. */
520 /* Remove useless bits from addresses in a running program. */
522 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
524 /* On M-profile devices, do not strip the low bit from EXC_RETURN
525 (the magic exception return address). */
526 if (gdbarch_tdep (gdbarch)->is_m
527 && arm_m_addr_is_magic (val))
531 return UNMAKE_THUMB_ADDR (val);
533 return (val & 0x03fffffc);
536 /* Return 1 if PC is the start of a compiler helper function which
537 can be safely ignored during prologue skipping. IS_THUMB is true
538 if the function is known to be a Thumb function due to the way it
541 skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
543 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
544 struct bound_minimal_symbol msym;
546 msym = lookup_minimal_symbol_by_pc (pc);
547 if (msym.minsym != NULL
548 && BMSYMBOL_VALUE_ADDRESS (msym) == pc
549 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL)
551 const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym);
553 /* The GNU linker's Thumb call stub to foo is named
555 if (strstr (name, "_from_thumb") != NULL)
558 /* On soft-float targets, __truncdfsf2 is called to convert promoted
559 arguments to their argument types in non-prototyped
561 if (startswith (name, "__truncdfsf2"))
563 if (startswith (name, "__aeabi_d2f"))
566 /* Internal functions related to thread-local storage. */
567 if (startswith (name, "__tls_get_addr"))
569 if (startswith (name, "__aeabi_read_tp"))
574 /* If we run against a stripped glibc, we may be unable to identify
575 special functions by name. Check for one important case,
576 __aeabi_read_tp, by comparing the *code* against the default
577 implementation (this is hand-written ARM assembler in glibc). */
580 && read_code_unsigned_integer (pc, 4, byte_order_for_code)
581 == 0xe3e00a0f /* mov r0, #0xffff0fff */
582 && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code)
583 == 0xe240f01f) /* sub pc, r0, #31 */
590 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
591 the first 16-bit of instruction, and INSN2 is the second 16-bit of
593 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
594 ((bits ((insn1), 0, 3) << 12) \
595 | (bits ((insn1), 10, 10) << 11) \
596 | (bits ((insn2), 12, 14) << 8) \
597 | bits ((insn2), 0, 7))
599 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
600 the 32-bit instruction. */
601 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
602 ((bits ((insn), 16, 19) << 12) \
603 | bits ((insn), 0, 11))
605 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
608 thumb_expand_immediate (unsigned int imm)
610 unsigned int count = imm >> 7;
618 return (imm & 0xff) | ((imm & 0xff) << 16);
620 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
622 return (imm & 0xff) | ((imm & 0xff) << 8)
623 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
626 return (0x80 | (imm & 0x7f)) << (32 - count);
629 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
630 epilogue, 0 otherwise. */
633 thumb_instruction_restores_sp (unsigned short insn)
635 return (insn == 0x46bd /* mov sp, r7 */
636 || (insn & 0xff80) == 0xb000 /* add sp, imm */
637 || (insn & 0xfe00) == 0xbc00); /* pop <registers> */
640 /* Analyze a Thumb prologue, looking for a recognizable stack frame
641 and frame pointer. Scan until we encounter a store that could
642 clobber the stack frame unexpectedly, or an unknown instruction.
643 Return the last address which is definitely safe to skip for an
644 initial breakpoint. */
647 thumb_analyze_prologue (struct gdbarch *gdbarch,
648 CORE_ADDR start, CORE_ADDR limit,
649 struct arm_prologue_cache *cache)
651 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
652 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
655 struct pv_area *stack;
656 struct cleanup *back_to;
658 CORE_ADDR unrecognized_pc = 0;
660 for (i = 0; i < 16; i++)
661 regs[i] = pv_register (i, 0);
662 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
663 back_to = make_cleanup_free_pv_area (stack);
665 while (start < limit)
669 insn = read_code_unsigned_integer (start, 2, byte_order_for_code);
671 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
676 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
679 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
680 whether to save LR (R14). */
681 mask = (insn & 0xff) | ((insn & 0x100) << 6);
683 /* Calculate offsets of saved R0-R7 and LR. */
684 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
685 if (mask & (1 << regno))
687 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
689 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
692 else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
694 offset = (insn & 0x7f) << 2; /* get scaled offset */
695 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
698 else if (thumb_instruction_restores_sp (insn))
700 /* Don't scan past the epilogue. */
703 else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
704 regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
706 else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
707 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
708 regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)],
710 else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */
711 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
712 regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)],
714 else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
715 && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM)
716 && pv_is_constant (regs[bits (insn, 3, 5)]))
717 regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)],
718 regs[bits (insn, 6, 8)]);
719 else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */
720 && pv_is_constant (regs[bits (insn, 3, 6)]))
722 int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2);
723 int rm = bits (insn, 3, 6);
724 regs[rd] = pv_add (regs[rd], regs[rm]);
726 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
728 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
729 int src_reg = (insn & 0x78) >> 3;
730 regs[dst_reg] = regs[src_reg];
732 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
734 /* Handle stores to the stack. Normally pushes are used,
735 but with GCC -mtpcs-frame, there may be other stores
736 in the prologue to create the frame. */
737 int regno = (insn >> 8) & 0x7;
740 offset = (insn & 0xff) << 2;
741 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
743 if (pv_area_store_would_trash (stack, addr))
746 pv_area_store (stack, addr, 4, regs[regno]);
748 else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
750 int rd = bits (insn, 0, 2);
751 int rn = bits (insn, 3, 5);
754 offset = bits (insn, 6, 10) << 2;
755 addr = pv_add_constant (regs[rn], offset);
757 if (pv_area_store_would_trash (stack, addr))
760 pv_area_store (stack, addr, 4, regs[rd]);
762 else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
763 || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
764 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))
765 /* Ignore stores of argument registers to the stack. */
767 else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
768 && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM))
769 /* Ignore block loads from the stack, potentially copying
770 parameters from memory. */
772 else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
773 || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
774 && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)))
775 /* Similarly ignore single loads from the stack. */
777 else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
778 || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
779 /* Skip register copies, i.e. saves to another register
780 instead of the stack. */
782 else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */
783 /* Recognize constant loads; even with small stacks these are necessary
785 regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7));
786 else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
788 /* Constant pool loads, for the same reason. */
789 unsigned int constant;
792 loc = start + 4 + bits (insn, 0, 7) * 4;
793 constant = read_memory_unsigned_integer (loc, 4, byte_order);
794 regs[bits (insn, 8, 10)] = pv_constant (constant);
796 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */
798 unsigned short inst2;
800 inst2 = read_code_unsigned_integer (start + 2, 2,
801 byte_order_for_code);
803 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
805 /* BL, BLX. Allow some special function calls when
806 skipping the prologue; GCC generates these before
807 storing arguments to the stack. */
809 int j1, j2, imm1, imm2;
811 imm1 = sbits (insn, 0, 10);
812 imm2 = bits (inst2, 0, 10);
813 j1 = bit (inst2, 13);
814 j2 = bit (inst2, 11);
816 offset = ((imm1 << 12) + (imm2 << 1));
817 offset ^= ((!j2) << 22) | ((!j1) << 23);
819 nextpc = start + 4 + offset;
820 /* For BLX make sure to clear the low bits. */
821 if (bit (inst2, 12) == 0)
822 nextpc = nextpc & 0xfffffffc;
824 if (!skip_prologue_function (gdbarch, nextpc,
825 bit (inst2, 12) != 0))
829 else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
831 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
833 pv_t addr = regs[bits (insn, 0, 3)];
836 if (pv_area_store_would_trash (stack, addr))
839 /* Calculate offsets of saved registers. */
840 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
841 if (inst2 & (1 << regno))
843 addr = pv_add_constant (addr, -4);
844 pv_area_store (stack, addr, 4, regs[regno]);
848 regs[bits (insn, 0, 3)] = addr;
851 else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
853 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
855 int regno1 = bits (inst2, 12, 15);
856 int regno2 = bits (inst2, 8, 11);
857 pv_t addr = regs[bits (insn, 0, 3)];
859 offset = inst2 & 0xff;
861 addr = pv_add_constant (addr, offset);
863 addr = pv_add_constant (addr, -offset);
865 if (pv_area_store_would_trash (stack, addr))
868 pv_area_store (stack, addr, 4, regs[regno1]);
869 pv_area_store (stack, pv_add_constant (addr, 4),
873 regs[bits (insn, 0, 3)] = addr;
876 else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
877 && (inst2 & 0x0c00) == 0x0c00
878 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
880 int regno = bits (inst2, 12, 15);
881 pv_t addr = regs[bits (insn, 0, 3)];
883 offset = inst2 & 0xff;
885 addr = pv_add_constant (addr, offset);
887 addr = pv_add_constant (addr, -offset);
889 if (pv_area_store_would_trash (stack, addr))
892 pv_area_store (stack, addr, 4, regs[regno]);
895 regs[bits (insn, 0, 3)] = addr;
898 else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
899 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
901 int regno = bits (inst2, 12, 15);
904 offset = inst2 & 0xfff;
905 addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
907 if (pv_area_store_would_trash (stack, addr))
910 pv_area_store (stack, addr, 4, regs[regno]);
913 else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
914 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
915 /* Ignore stores of argument registers to the stack. */
918 else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
919 && (inst2 & 0x0d00) == 0x0c00
920 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
921 /* Ignore stores of argument registers to the stack. */
924 else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
926 && (inst2 & 0x8000) == 0x0000
927 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
928 /* Ignore block loads from the stack, potentially copying
929 parameters from memory. */
932 else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
934 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
935 /* Similarly ignore dual loads from the stack. */
938 else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
939 && (inst2 & 0x0d00) == 0x0c00
940 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
941 /* Similarly ignore single loads from the stack. */
944 else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
945 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
946 /* Similarly ignore single loads from the stack. */
949 else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
950 && (inst2 & 0x8000) == 0x0000)
952 unsigned int imm = ((bits (insn, 10, 10) << 11)
953 | (bits (inst2, 12, 14) << 8)
954 | bits (inst2, 0, 7));
956 regs[bits (inst2, 8, 11)]
957 = pv_add_constant (regs[bits (insn, 0, 3)],
958 thumb_expand_immediate (imm));
961 else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
962 && (inst2 & 0x8000) == 0x0000)
964 unsigned int imm = ((bits (insn, 10, 10) << 11)
965 | (bits (inst2, 12, 14) << 8)
966 | bits (inst2, 0, 7));
968 regs[bits (inst2, 8, 11)]
969 = pv_add_constant (regs[bits (insn, 0, 3)], imm);
972 else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
973 && (inst2 & 0x8000) == 0x0000)
975 unsigned int imm = ((bits (insn, 10, 10) << 11)
976 | (bits (inst2, 12, 14) << 8)
977 | bits (inst2, 0, 7));
979 regs[bits (inst2, 8, 11)]
980 = pv_add_constant (regs[bits (insn, 0, 3)],
981 - (CORE_ADDR) thumb_expand_immediate (imm));
984 else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
985 && (inst2 & 0x8000) == 0x0000)
987 unsigned int imm = ((bits (insn, 10, 10) << 11)
988 | (bits (inst2, 12, 14) << 8)
989 | bits (inst2, 0, 7));
991 regs[bits (inst2, 8, 11)]
992 = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
995 else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
997 unsigned int imm = ((bits (insn, 10, 10) << 11)
998 | (bits (inst2, 12, 14) << 8)
999 | bits (inst2, 0, 7));
1001 regs[bits (inst2, 8, 11)]
1002 = pv_constant (thumb_expand_immediate (imm));
1005 else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1008 = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1010 regs[bits (inst2, 8, 11)] = pv_constant (imm);
1013 else if (insn == 0xea5f /* mov.w Rd,Rm */
1014 && (inst2 & 0xf0f0) == 0)
1016 int dst_reg = (inst2 & 0x0f00) >> 8;
1017 int src_reg = inst2 & 0xf;
1018 regs[dst_reg] = regs[src_reg];
1021 else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1023 /* Constant pool loads. */
1024 unsigned int constant;
1027 offset = bits (inst2, 0, 11);
1029 loc = start + 4 + offset;
1031 loc = start + 4 - offset;
1033 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1034 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1037 else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1039 /* Constant pool loads. */
1040 unsigned int constant;
1043 offset = bits (inst2, 0, 7) << 2;
1045 loc = start + 4 + offset;
1047 loc = start + 4 - offset;
1049 constant = read_memory_unsigned_integer (loc, 4, byte_order);
1050 regs[bits (inst2, 12, 15)] = pv_constant (constant);
1052 constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1053 regs[bits (inst2, 8, 11)] = pv_constant (constant);
1056 else if (thumb2_instruction_changes_pc (insn, inst2))
1058 /* Don't scan past anything that might change control flow. */
1063 /* The optimizer might shove anything into the prologue,
1064 so we just skip what we don't recognize. */
1065 unrecognized_pc = start;
1070 else if (thumb_instruction_changes_pc (insn))
1072 /* Don't scan past anything that might change control flow. */
1077 /* The optimizer might shove anything into the prologue,
1078 so we just skip what we don't recognize. */
1079 unrecognized_pc = start;
1086 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1087 paddress (gdbarch, start));
1089 if (unrecognized_pc == 0)
1090 unrecognized_pc = start;
1094 do_cleanups (back_to);
1095 return unrecognized_pc;
1098 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1100 /* Frame pointer is fp. Frame size is constant. */
1101 cache->framereg = ARM_FP_REGNUM;
1102 cache->framesize = -regs[ARM_FP_REGNUM].k;
1104 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
1106 /* Frame pointer is r7. Frame size is constant. */
1107 cache->framereg = THUMB_FP_REGNUM;
1108 cache->framesize = -regs[THUMB_FP_REGNUM].k;
1112 /* Try the stack pointer... this is a bit desperate. */
1113 cache->framereg = ARM_SP_REGNUM;
1114 cache->framesize = -regs[ARM_SP_REGNUM].k;
1117 for (i = 0; i < 16; i++)
1118 if (pv_area_find_reg (stack, gdbarch, i, &offset))
1119 cache->saved_regs[i].addr = offset;
1121 do_cleanups (back_to);
1122 return unrecognized_pc;
1126 /* Try to analyze the instructions starting from PC, which load symbol
1127 __stack_chk_guard. Return the address of instruction after loading this
1128 symbol, set the dest register number to *BASEREG, and set the size of
1129 instructions for loading symbol in OFFSET. Return 0 if instructions are
1133 arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1134 unsigned int *destreg, int *offset)
1136 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1137 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1138 unsigned int low, high, address;
1143 unsigned short insn1
1144 = read_code_unsigned_integer (pc, 2, byte_order_for_code);
1146 if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1148 *destreg = bits (insn1, 8, 10);
1150 address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2);
1151 address = read_memory_unsigned_integer (address, 4,
1152 byte_order_for_code);
1154 else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1156 unsigned short insn2
1157 = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code);
1159 low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1162 = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code);
1164 = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code);
1166 /* movt Rd, #const */
1167 if ((insn1 & 0xfbc0) == 0xf2c0)
1169 high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1170 *destreg = bits (insn2, 8, 11);
1172 address = (high << 16 | low);
1179 = read_code_unsigned_integer (pc, 4, byte_order_for_code);
1181 if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1183 address = bits (insn, 0, 11) + pc + 8;
1184 address = read_memory_unsigned_integer (address, 4,
1185 byte_order_for_code);
1187 *destreg = bits (insn, 12, 15);
1190 else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1192 low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1195 = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code);
1197 if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1199 high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1200 *destreg = bits (insn, 12, 15);
1202 address = (high << 16 | low);
1210 /* Try to skip a sequence of instructions used for stack protector. If PC
1211 points to the first instruction of this sequence, return the address of
1212 first instruction after this sequence, otherwise, return original PC.
1214 On arm, this sequence of instructions is composed of mainly three steps,
1215 Step 1: load symbol __stack_chk_guard,
1216 Step 2: load from address of __stack_chk_guard,
1217 Step 3: store it to somewhere else.
1219 Usually, instructions on step 2 and step 3 are the same on various ARM
1220 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1221 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1222 instructions in step 1 vary from different ARM architectures. On ARMv7,
1225 movw Rn, #:lower16:__stack_chk_guard
1226 movt Rn, #:upper16:__stack_chk_guard
1233 .word __stack_chk_guard
1235 Since ldr/str is a very popular instruction, we can't use them as
1236 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1237 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1238 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1241 arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1243 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1244 unsigned int basereg;
1245 struct bound_minimal_symbol stack_chk_guard;
1247 int is_thumb = arm_pc_is_thumb (gdbarch, pc);
1250 /* Try to parse the instructions in Step 1. */
1251 addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1256 stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1257 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1258 Otherwise, this sequence cannot be for stack protector. */
1259 if (stack_chk_guard.minsym == NULL
1260 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard"))
1265 unsigned int destreg;
1267 = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code);
1269 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1270 if ((insn & 0xf800) != 0x6800)
1272 if (bits (insn, 3, 5) != basereg)
1274 destreg = bits (insn, 0, 2);
1276 insn = read_code_unsigned_integer (pc + offset + 2, 2,
1277 byte_order_for_code);
1278 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1279 if ((insn & 0xf800) != 0x6000)
1281 if (destreg != bits (insn, 0, 2))
1286 unsigned int destreg;
1288 = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code);
1290 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1291 if ((insn & 0x0e500000) != 0x04100000)
1293 if (bits (insn, 16, 19) != basereg)
1295 destreg = bits (insn, 12, 15);
1296 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1297 insn = read_code_unsigned_integer (pc + offset + 4,
1298 4, byte_order_for_code);
1299 if ((insn & 0x0e500000) != 0x04000000)
1301 if (bits (insn, 12, 15) != destreg)
1304 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1307 return pc + offset + 4;
1309 return pc + offset + 8;
1312 /* Advance the PC across any function entry prologue instructions to
1313 reach some "real" code.
1315 The APCS (ARM Procedure Call Standard) defines the following
1319 [stmfd sp!, {a1,a2,a3,a4}]
1320 stmfd sp!, {...,fp,ip,lr,pc}
1321 [stfe f7, [sp, #-12]!]
1322 [stfe f6, [sp, #-12]!]
1323 [stfe f5, [sp, #-12]!]
1324 [stfe f4, [sp, #-12]!]
1325 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1328 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1330 CORE_ADDR func_addr, limit_pc;
1332 /* See if we can determine the end of the prologue via the symbol table.
1333 If so, then return either PC, or the PC after the prologue, whichever
1335 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1337 CORE_ADDR post_prologue_pc
1338 = skip_prologue_using_sal (gdbarch, func_addr);
1339 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1341 if (post_prologue_pc)
1343 = arm_skip_stack_protector (post_prologue_pc, gdbarch);
1346 /* GCC always emits a line note before the prologue and another
1347 one after, even if the two are at the same address or on the
1348 same line. Take advantage of this so that we do not need to
1349 know every instruction that might appear in the prologue. We
1350 will have producer information for most binaries; if it is
1351 missing (e.g. for -gstabs), assuming the GNU tools. */
1352 if (post_prologue_pc
1354 || COMPUNIT_PRODUCER (cust) == NULL
1355 || startswith (COMPUNIT_PRODUCER (cust), "GNU ")
1356 || startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1357 return post_prologue_pc;
1359 if (post_prologue_pc != 0)
1361 CORE_ADDR analyzed_limit;
1363 /* For non-GCC compilers, make sure the entire line is an
1364 acceptable prologue; GDB will round this function's
1365 return value up to the end of the following line so we
1366 can not skip just part of a line (and we do not want to).
1368 RealView does not treat the prologue specially, but does
1369 associate prologue code with the opening brace; so this
1370 lets us skip the first line if we think it is the opening
1372 if (arm_pc_is_thumb (gdbarch, func_addr))
1373 analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr,
1374 post_prologue_pc, NULL);
1376 analyzed_limit = arm_analyze_prologue (gdbarch, func_addr,
1377 post_prologue_pc, NULL);
1379 if (analyzed_limit != post_prologue_pc)
1382 return post_prologue_pc;
1386 /* Can't determine prologue from the symbol table, need to examine
1389 /* Find an upper limit on the function prologue using the debug
1390 information. If the debug information could not be used to provide
1391 that bound, then use an arbitrary large number as the upper bound. */
1392 /* Like arm_scan_prologue, stop no later than pc + 64. */
1393 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1395 limit_pc = pc + 64; /* Magic. */
1398 /* Check if this is Thumb code. */
1399 if (arm_pc_is_thumb (gdbarch, pc))
1400 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1402 return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1406 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1407 This function decodes a Thumb function prologue to determine:
1408 1) the size of the stack frame
1409 2) which registers are saved on it
1410 3) the offsets of saved regs
1411 4) the offset from the stack pointer to the frame pointer
1413 A typical Thumb function prologue would create this stack frame
1414 (offsets relative to FP)
1415 old SP -> 24 stack parameters
1418 R7 -> 0 local variables (16 bytes)
1419 SP -> -12 additional stack space (12 bytes)
1420 The frame size would thus be 36 bytes, and the frame offset would be
1421 12 bytes. The frame register is R7.
1423 The comments for thumb_skip_prolog() describe the algorithm we use
1424 to detect the end of the prolog. */
1428 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
1429 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
1431 CORE_ADDR prologue_start;
1432 CORE_ADDR prologue_end;
1434 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1437 /* See comment in arm_scan_prologue for an explanation of
1439 if (prologue_end > prologue_start + 64)
1441 prologue_end = prologue_start + 64;
1445 /* We're in the boondocks: we have no idea where the start of the
1449 prologue_end = std::min (prologue_end, prev_pc);
1451 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1454 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1458 arm_instruction_restores_sp (unsigned int insn)
1460 if (bits (insn, 28, 31) != INST_NV)
1462 if ((insn & 0x0df0f000) == 0x0080d000
1463 /* ADD SP (register or immediate). */
1464 || (insn & 0x0df0f000) == 0x0040d000
1465 /* SUB SP (register or immediate). */
1466 || (insn & 0x0ffffff0) == 0x01a0d000
1468 || (insn & 0x0fff0000) == 0x08bd0000
1470 || (insn & 0x0fff0000) == 0x049d0000)
1471 /* POP of a single register. */
1478 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1479 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1480 fill it in. Return the first address not recognized as a prologue
1483 We recognize all the instructions typically found in ARM prologues,
1484 plus harmless instructions which can be skipped (either for analysis
1485 purposes, or a more restrictive set that can be skipped when finding
1486 the end of the prologue). */
1489 arm_analyze_prologue (struct gdbarch *gdbarch,
1490 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1491 struct arm_prologue_cache *cache)
1493 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1495 CORE_ADDR offset, current_pc;
1496 pv_t regs[ARM_FPS_REGNUM];
1497 struct pv_area *stack;
1498 struct cleanup *back_to;
1499 CORE_ADDR unrecognized_pc = 0;
1501 /* Search the prologue looking for instructions that set up the
1502 frame pointer, adjust the stack pointer, and save registers.
1504 Be careful, however, and if it doesn't look like a prologue,
1505 don't try to scan it. If, for instance, a frameless function
1506 begins with stmfd sp!, then we will tell ourselves there is
1507 a frame, which will confuse stack traceback, as well as "finish"
1508 and other operations that rely on a knowledge of the stack
1511 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1512 regs[regno] = pv_register (regno, 0);
1513 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1514 back_to = make_cleanup_free_pv_area (stack);
1516 for (current_pc = prologue_start;
1517 current_pc < prologue_end;
1521 = read_code_unsigned_integer (current_pc, 4, byte_order_for_code);
1523 if (insn == 0xe1a0c00d) /* mov ip, sp */
1525 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
1528 else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1529 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1531 unsigned imm = insn & 0xff; /* immediate value */
1532 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1533 int rd = bits (insn, 12, 15);
1534 imm = (imm >> rot) | (imm << (32 - rot));
1535 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm);
1538 else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1539 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1541 unsigned imm = insn & 0xff; /* immediate value */
1542 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1543 int rd = bits (insn, 12, 15);
1544 imm = (imm >> rot) | (imm << (32 - rot));
1545 regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
1548 else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
1551 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1553 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1554 pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
1555 regs[bits (insn, 12, 15)]);
1558 else if ((insn & 0xffff0000) == 0xe92d0000)
1559 /* stmfd sp!, {..., fp, ip, lr, pc}
1561 stmfd sp!, {a1, a2, a3, a4} */
1563 int mask = insn & 0xffff;
1565 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1568 /* Calculate offsets of saved registers. */
1569 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
1570 if (mask & (1 << regno))
1573 = pv_add_constant (regs[ARM_SP_REGNUM], -4);
1574 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
1577 else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1578 || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1579 || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1581 /* No need to add this to saved_regs -- it's just an arg reg. */
1584 else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1585 || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1586 || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1588 /* No need to add this to saved_regs -- it's just an arg reg. */
1591 else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
1593 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1595 /* No need to add this to saved_regs -- it's just arg regs. */
1598 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1600 unsigned imm = insn & 0xff; /* immediate value */
1601 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1602 imm = (imm >> rot) | (imm << (32 - rot));
1603 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
1605 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1607 unsigned imm = insn & 0xff; /* immediate value */
1608 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
1609 imm = (imm >> rot) | (imm << (32 - rot));
1610 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
1612 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
1614 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1616 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1619 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1620 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
1621 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1623 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1625 && gdbarch_tdep (gdbarch)->have_fpa_registers)
1627 int n_saved_fp_regs;
1628 unsigned int fp_start_reg, fp_bound_reg;
1630 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
1633 if ((insn & 0x800) == 0x800) /* N0 is set */
1635 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1636 n_saved_fp_regs = 3;
1638 n_saved_fp_regs = 1;
1642 if ((insn & 0x40000) == 0x40000) /* N1 is set */
1643 n_saved_fp_regs = 2;
1645 n_saved_fp_regs = 4;
1648 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
1649 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1650 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1652 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
1653 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
1654 regs[fp_start_reg++]);
1657 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
1659 /* Allow some special function calls when skipping the
1660 prologue; GCC generates these before storing arguments to
1662 CORE_ADDR dest = BranchDest (current_pc, insn);
1664 if (skip_prologue_function (gdbarch, dest, 0))
1669 else if ((insn & 0xf0000000) != 0xe0000000)
1670 break; /* Condition not true, exit early. */
1671 else if (arm_instruction_changes_pc (insn))
1672 /* Don't scan past anything that might change control flow. */
1674 else if (arm_instruction_restores_sp (insn))
1676 /* Don't scan past the epilogue. */
1679 else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
1680 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1681 /* Ignore block loads from the stack, potentially copying
1682 parameters from memory. */
1684 else if ((insn & 0xfc500000) == 0xe4100000
1685 && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
1686 /* Similarly ignore single loads from the stack. */
1688 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1689 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1690 register instead of the stack. */
1694 /* The optimizer might shove anything into the prologue, if
1695 we build up cache (cache != NULL) from scanning prologue,
1696 we just skip what we don't recognize and scan further to
1697 make cache as complete as possible. However, if we skip
1698 prologue, we'll stop immediately on unrecognized
1700 unrecognized_pc = current_pc;
1708 if (unrecognized_pc == 0)
1709 unrecognized_pc = current_pc;
1713 int framereg, framesize;
1715 /* The frame size is just the distance from the frame register
1716 to the original stack pointer. */
1717 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1719 /* Frame pointer is fp. */
1720 framereg = ARM_FP_REGNUM;
1721 framesize = -regs[ARM_FP_REGNUM].k;
1725 /* Try the stack pointer... this is a bit desperate. */
1726 framereg = ARM_SP_REGNUM;
1727 framesize = -regs[ARM_SP_REGNUM].k;
1730 cache->framereg = framereg;
1731 cache->framesize = framesize;
1733 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1734 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1735 cache->saved_regs[regno].addr = offset;
1739 fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
1740 paddress (gdbarch, unrecognized_pc));
1742 do_cleanups (back_to);
1743 return unrecognized_pc;
1747 arm_scan_prologue (struct frame_info *this_frame,
1748 struct arm_prologue_cache *cache)
1750 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1751 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1752 CORE_ADDR prologue_start, prologue_end;
1753 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1754 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1756 /* Assume there is no frame until proven otherwise. */
1757 cache->framereg = ARM_SP_REGNUM;
1758 cache->framesize = 0;
1760 /* Check for Thumb prologue. */
1761 if (arm_frame_is_thumb (this_frame))
1763 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
1767 /* Find the function prologue. If we can't find the function in
1768 the symbol table, peek in the stack frame to find the PC. */
1769 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
1772 /* One way to find the end of the prologue (which works well
1773 for unoptimized code) is to do the following:
1775 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1778 prologue_end = prev_pc;
1779 else if (sal.end < prologue_end)
1780 prologue_end = sal.end;
1782 This mechanism is very accurate so long as the optimizer
1783 doesn't move any instructions from the function body into the
1784 prologue. If this happens, sal.end will be the last
1785 instruction in the first hunk of prologue code just before
1786 the first instruction that the scheduler has moved from
1787 the body to the prologue.
1789 In order to make sure that we scan all of the prologue
1790 instructions, we use a slightly less accurate mechanism which
1791 may scan more than necessary. To help compensate for this
1792 lack of accuracy, the prologue scanning loop below contains
1793 several clauses which'll cause the loop to terminate early if
1794 an implausible prologue instruction is encountered.
1800 is a suitable endpoint since it accounts for the largest
1801 possible prologue plus up to five instructions inserted by
1804 if (prologue_end > prologue_start + 64)
1806 prologue_end = prologue_start + 64; /* See above. */
1811 /* We have no symbol information. Our only option is to assume this
1812 function has a standard stack frame and the normal frame register.
1813 Then, we can find the value of our frame pointer on entrance to
1814 the callee (or at the present moment if this is the innermost frame).
1815 The value stored there should be the address of the stmfd + 8. */
1816 CORE_ADDR frame_loc;
1817 ULONGEST return_value;
1819 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
1820 if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order,
1825 prologue_start = gdbarch_addr_bits_remove
1826 (gdbarch, return_value) - 8;
1827 prologue_end = prologue_start + 64; /* See above. */
1831 if (prev_pc < prologue_end)
1832 prologue_end = prev_pc;
1834 arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
1837 static struct arm_prologue_cache *
1838 arm_make_prologue_cache (struct frame_info *this_frame)
1841 struct arm_prologue_cache *cache;
1842 CORE_ADDR unwound_fp;
1844 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1845 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1847 arm_scan_prologue (this_frame, cache);
1849 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1850 if (unwound_fp == 0)
1853 cache->prev_sp = unwound_fp + cache->framesize;
1855 /* Calculate actual addresses of saved registers using offsets
1856 determined by arm_scan_prologue. */
1857 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1858 if (trad_frame_addr_p (cache->saved_regs, reg))
1859 cache->saved_regs[reg].addr += cache->prev_sp;
1864 /* Implementation of the stop_reason hook for arm_prologue frames. */
1866 static enum unwind_stop_reason
1867 arm_prologue_unwind_stop_reason (struct frame_info *this_frame,
1870 struct arm_prologue_cache *cache;
1873 if (*this_cache == NULL)
1874 *this_cache = arm_make_prologue_cache (this_frame);
1875 cache = (struct arm_prologue_cache *) *this_cache;
1877 /* This is meant to halt the backtrace at "_start". */
1878 pc = get_frame_pc (this_frame);
1879 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1880 return UNWIND_OUTERMOST;
1882 /* If we've hit a wall, stop. */
1883 if (cache->prev_sp == 0)
1884 return UNWIND_OUTERMOST;
1886 return UNWIND_NO_REASON;
1889 /* Our frame ID for a normal frame is the current function's starting PC
1890 and the caller's SP when we were called. */
1893 arm_prologue_this_id (struct frame_info *this_frame,
1895 struct frame_id *this_id)
1897 struct arm_prologue_cache *cache;
1901 if (*this_cache == NULL)
1902 *this_cache = arm_make_prologue_cache (this_frame);
1903 cache = (struct arm_prologue_cache *) *this_cache;
1905 /* Use function start address as part of the frame ID. If we cannot
1906 identify the start address (due to missing symbol information),
1907 fall back to just using the current PC. */
1908 pc = get_frame_pc (this_frame);
1909 func = get_frame_func (this_frame);
1913 id = frame_id_build (cache->prev_sp, func);
1917 static struct value *
1918 arm_prologue_prev_register (struct frame_info *this_frame,
1922 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1923 struct arm_prologue_cache *cache;
1925 if (*this_cache == NULL)
1926 *this_cache = arm_make_prologue_cache (this_frame);
1927 cache = (struct arm_prologue_cache *) *this_cache;
1929 /* If we are asked to unwind the PC, then we need to return the LR
1930 instead. The prologue may save PC, but it will point into this
1931 frame's prologue, not the next frame's resume location. Also
1932 strip the saved T bit. A valid LR may have the low bit set, but
1933 a valid PC never does. */
1934 if (prev_regnum == ARM_PC_REGNUM)
1938 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1939 return frame_unwind_got_constant (this_frame, prev_regnum,
1940 arm_addr_bits_remove (gdbarch, lr));
1943 /* SP is generally not saved to the stack, but this frame is
1944 identified by the next frame's stack pointer at the time of the call.
1945 The value was already reconstructed into PREV_SP. */
1946 if (prev_regnum == ARM_SP_REGNUM)
1947 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1949 /* The CPSR may have been changed by the call instruction and by the
1950 called function. The only bit we can reconstruct is the T bit,
1951 by checking the low bit of LR as of the call. This is a reliable
1952 indicator of Thumb-ness except for some ARM v4T pre-interworking
1953 Thumb code, which could get away with a clear low bit as long as
1954 the called function did not use bx. Guess that all other
1955 bits are unchanged; the condition flags are presumably lost,
1956 but the processor status is likely valid. */
1957 if (prev_regnum == ARM_PS_REGNUM)
1960 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
1962 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1963 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1964 if (IS_THUMB_ADDR (lr))
1968 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1971 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1975 struct frame_unwind arm_prologue_unwind = {
1977 arm_prologue_unwind_stop_reason,
1978 arm_prologue_this_id,
1979 arm_prologue_prev_register,
1981 default_frame_sniffer
1984 /* Maintain a list of ARM exception table entries per objfile, similar to the
1985 list of mapping symbols. We only cache entries for standard ARM-defined
1986 personality routines; the cache will contain only the frame unwinding
1987 instructions associated with the entry (not the descriptors). */
1989 static const struct objfile_data *arm_exidx_data_key;
1991 struct arm_exidx_entry
1996 typedef struct arm_exidx_entry arm_exidx_entry_s;
1997 DEF_VEC_O(arm_exidx_entry_s);
1999 struct arm_exidx_data
2001 VEC(arm_exidx_entry_s) **section_maps;
2005 arm_exidx_data_free (struct objfile *objfile, void *arg)
2007 struct arm_exidx_data *data = (struct arm_exidx_data *) arg;
2010 for (i = 0; i < objfile->obfd->section_count; i++)
2011 VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2015 arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2016 const struct arm_exidx_entry *rhs)
2018 return lhs->addr < rhs->addr;
2021 static struct obj_section *
2022 arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2024 struct obj_section *osect;
2026 ALL_OBJFILE_OSECTIONS (objfile, osect)
2027 if (bfd_get_section_flags (objfile->obfd,
2028 osect->the_bfd_section) & SEC_ALLOC)
2030 bfd_vma start, size;
2031 start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2032 size = bfd_get_section_size (osect->the_bfd_section);
2034 if (start <= vma && vma < start + size)
2041 /* Parse contents of exception table and exception index sections
2042 of OBJFILE, and fill in the exception table entry cache.
2044 For each entry that refers to a standard ARM-defined personality
2045 routine, extract the frame unwinding instructions (from either
2046 the index or the table section). The unwinding instructions
2048 - extracting them from the rest of the table data
2049 - converting to host endianness
2050 - appending the implicit 0xb0 ("Finish") code
2052 The extracted and normalized instructions are stored for later
2053 retrieval by the arm_find_exidx_entry routine. */
2056 arm_exidx_new_objfile (struct objfile *objfile)
2058 struct cleanup *cleanups;
2059 struct arm_exidx_data *data;
2060 asection *exidx, *extab;
2061 bfd_vma exidx_vma = 0, extab_vma = 0;
2062 bfd_size_type exidx_size = 0, extab_size = 0;
2063 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2066 /* If we've already touched this file, do nothing. */
2067 if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2069 cleanups = make_cleanup (null_cleanup, NULL);
2071 /* Read contents of exception table and index. */
2072 exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
2075 exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2076 exidx_size = bfd_get_section_size (exidx);
2077 exidx_data = (gdb_byte *) xmalloc (exidx_size);
2078 make_cleanup (xfree, exidx_data);
2080 if (!bfd_get_section_contents (objfile->obfd, exidx,
2081 exidx_data, 0, exidx_size))
2083 do_cleanups (cleanups);
2088 extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2091 extab_vma = bfd_section_vma (objfile->obfd, extab);
2092 extab_size = bfd_get_section_size (extab);
2093 extab_data = (gdb_byte *) xmalloc (extab_size);
2094 make_cleanup (xfree, extab_data);
2096 if (!bfd_get_section_contents (objfile->obfd, extab,
2097 extab_data, 0, extab_size))
2099 do_cleanups (cleanups);
2104 /* Allocate exception table data structure. */
2105 data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2106 set_objfile_data (objfile, arm_exidx_data_key, data);
2107 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2108 objfile->obfd->section_count,
2109 VEC(arm_exidx_entry_s) *);
2111 /* Fill in exception table. */
2112 for (i = 0; i < exidx_size / 8; i++)
2114 struct arm_exidx_entry new_exidx_entry;
2115 bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2116 bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2117 bfd_vma addr = 0, word = 0;
2118 int n_bytes = 0, n_words = 0;
2119 struct obj_section *sec;
2120 gdb_byte *entry = NULL;
2122 /* Extract address of start of function. */
2123 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2124 idx += exidx_vma + i * 8;
2126 /* Find section containing function and compute section offset. */
2127 sec = arm_obj_section_from_vma (objfile, idx);
2130 idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2132 /* Determine address of exception table entry. */
2135 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2137 else if ((val & 0xff000000) == 0x80000000)
2139 /* Exception table entry embedded in .ARM.exidx
2140 -- must be short form. */
2144 else if (!(val & 0x80000000))
2146 /* Exception table entry in .ARM.extab. */
2147 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2148 addr += exidx_vma + i * 8 + 4;
2150 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2152 word = bfd_h_get_32 (objfile->obfd,
2153 extab_data + addr - extab_vma);
2156 if ((word & 0xff000000) == 0x80000000)
2161 else if ((word & 0xff000000) == 0x81000000
2162 || (word & 0xff000000) == 0x82000000)
2166 n_words = ((word >> 16) & 0xff);
2168 else if (!(word & 0x80000000))
2171 struct obj_section *pers_sec;
2172 int gnu_personality = 0;
2174 /* Custom personality routine. */
2175 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2176 pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2178 /* Check whether we've got one of the variants of the
2179 GNU personality routines. */
2180 pers_sec = arm_obj_section_from_vma (objfile, pers);
2183 static const char *personality[] =
2185 "__gcc_personality_v0",
2186 "__gxx_personality_v0",
2187 "__gcj_personality_v0",
2188 "__gnu_objc_personality_v0",
2192 CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2195 for (k = 0; personality[k]; k++)
2196 if (lookup_minimal_symbol_by_pc_name
2197 (pc, personality[k], objfile))
2199 gnu_personality = 1;
2204 /* If so, the next word contains a word count in the high
2205 byte, followed by the same unwind instructions as the
2206 pre-defined forms. */
2208 && addr + 4 <= extab_vma + extab_size)
2210 word = bfd_h_get_32 (objfile->obfd,
2211 extab_data + addr - extab_vma);
2214 n_words = ((word >> 24) & 0xff);
2220 /* Sanity check address. */
2222 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2223 n_words = n_bytes = 0;
2225 /* The unwind instructions reside in WORD (only the N_BYTES least
2226 significant bytes are valid), followed by N_WORDS words in the
2227 extab section starting at ADDR. */
2228 if (n_bytes || n_words)
2231 = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack,
2232 n_bytes + n_words * 4 + 1);
2235 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2239 word = bfd_h_get_32 (objfile->obfd,
2240 extab_data + addr - extab_vma);
2243 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2244 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2245 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2246 *p++ = (gdb_byte) (word & 0xff);
2249 /* Implied "Finish" to terminate the list. */
2253 /* Push entry onto vector. They are guaranteed to always
2254 appear in order of increasing addresses. */
2255 new_exidx_entry.addr = idx;
2256 new_exidx_entry.entry = entry;
2257 VEC_safe_push (arm_exidx_entry_s,
2258 data->section_maps[sec->the_bfd_section->index],
2262 do_cleanups (cleanups);
2265 /* Search for the exception table entry covering MEMADDR. If one is found,
2266 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2267 set *START to the start of the region covered by this entry. */
2270 arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2272 struct obj_section *sec;
2274 sec = find_pc_section (memaddr);
2277 struct arm_exidx_data *data;
2278 VEC(arm_exidx_entry_s) *map;
2279 struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2282 data = ((struct arm_exidx_data *)
2283 objfile_data (sec->objfile, arm_exidx_data_key));
2286 map = data->section_maps[sec->the_bfd_section->index];
2287 if (!VEC_empty (arm_exidx_entry_s, map))
2289 struct arm_exidx_entry *map_sym;
2291 idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2292 arm_compare_exidx_entries);
2294 /* VEC_lower_bound finds the earliest ordered insertion
2295 point. If the following symbol starts at this exact
2296 address, we use that; otherwise, the preceding
2297 exception table entry covers this address. */
2298 if (idx < VEC_length (arm_exidx_entry_s, map))
2300 map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2301 if (map_sym->addr == map_key.addr)
2304 *start = map_sym->addr + obj_section_addr (sec);
2305 return map_sym->entry;
2311 map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2313 *start = map_sym->addr + obj_section_addr (sec);
2314 return map_sym->entry;
2323 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2324 instruction list from the ARM exception table entry ENTRY, allocate and
2325 return a prologue cache structure describing how to unwind this frame.
2327 Return NULL if the unwinding instruction list contains a "spare",
2328 "reserved" or "refuse to unwind" instruction as defined in section
2329 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2330 for the ARM Architecture" document. */
2332 static struct arm_prologue_cache *
2333 arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2338 struct arm_prologue_cache *cache;
2339 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2340 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2346 /* Whenever we reload SP, we actually have to retrieve its
2347 actual value in the current frame. */
2350 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2352 int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2353 vsp = get_frame_register_unsigned (this_frame, reg);
2357 CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2358 vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2364 /* Decode next unwind instruction. */
2367 if ((insn & 0xc0) == 0)
2369 int offset = insn & 0x3f;
2370 vsp += (offset << 2) + 4;
2372 else if ((insn & 0xc0) == 0x40)
2374 int offset = insn & 0x3f;
2375 vsp -= (offset << 2) + 4;
2377 else if ((insn & 0xf0) == 0x80)
2379 int mask = ((insn & 0xf) << 8) | *entry++;
2382 /* The special case of an all-zero mask identifies
2383 "Refuse to unwind". We return NULL to fall back
2384 to the prologue analyzer. */
2388 /* Pop registers r4..r15 under mask. */
2389 for (i = 0; i < 12; i++)
2390 if (mask & (1 << i))
2392 cache->saved_regs[4 + i].addr = vsp;
2396 /* Special-case popping SP -- we need to reload vsp. */
2397 if (mask & (1 << (ARM_SP_REGNUM - 4)))
2400 else if ((insn & 0xf0) == 0x90)
2402 int reg = insn & 0xf;
2404 /* Reserved cases. */
2405 if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2408 /* Set SP from another register and mark VSP for reload. */
2409 cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2412 else if ((insn & 0xf0) == 0xa0)
2414 int count = insn & 0x7;
2415 int pop_lr = (insn & 0x8) != 0;
2418 /* Pop r4..r[4+count]. */
2419 for (i = 0; i <= count; i++)
2421 cache->saved_regs[4 + i].addr = vsp;
2425 /* If indicated by flag, pop LR as well. */
2428 cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2432 else if (insn == 0xb0)
2434 /* We could only have updated PC by popping into it; if so, it
2435 will show up as address. Otherwise, copy LR into PC. */
2436 if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2437 cache->saved_regs[ARM_PC_REGNUM]
2438 = cache->saved_regs[ARM_LR_REGNUM];
2443 else if (insn == 0xb1)
2445 int mask = *entry++;
2448 /* All-zero mask and mask >= 16 is "spare". */
2449 if (mask == 0 || mask >= 16)
2452 /* Pop r0..r3 under mask. */
2453 for (i = 0; i < 4; i++)
2454 if (mask & (1 << i))
2456 cache->saved_regs[i].addr = vsp;
2460 else if (insn == 0xb2)
2462 ULONGEST offset = 0;
2467 offset |= (*entry & 0x7f) << shift;
2470 while (*entry++ & 0x80);
2472 vsp += 0x204 + (offset << 2);
2474 else if (insn == 0xb3)
2476 int start = *entry >> 4;
2477 int count = (*entry++) & 0xf;
2480 /* Only registers D0..D15 are valid here. */
2481 if (start + count >= 16)
2484 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2485 for (i = 0; i <= count; i++)
2487 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2491 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2494 else if ((insn & 0xf8) == 0xb8)
2496 int count = insn & 0x7;
2499 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2500 for (i = 0; i <= count; i++)
2502 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2506 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2509 else if (insn == 0xc6)
2511 int start = *entry >> 4;
2512 int count = (*entry++) & 0xf;
2515 /* Only registers WR0..WR15 are valid. */
2516 if (start + count >= 16)
2519 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2520 for (i = 0; i <= count; i++)
2522 cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2526 else if (insn == 0xc7)
2528 int mask = *entry++;
2531 /* All-zero mask and mask >= 16 is "spare". */
2532 if (mask == 0 || mask >= 16)
2535 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2536 for (i = 0; i < 4; i++)
2537 if (mask & (1 << i))
2539 cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2543 else if ((insn & 0xf8) == 0xc0)
2545 int count = insn & 0x7;
2548 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2549 for (i = 0; i <= count; i++)
2551 cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2555 else if (insn == 0xc8)
2557 int start = *entry >> 4;
2558 int count = (*entry++) & 0xf;
2561 /* Only registers D0..D31 are valid. */
2562 if (start + count >= 16)
2565 /* Pop VFP double-precision registers
2566 D[16+start]..D[16+start+count]. */
2567 for (i = 0; i <= count; i++)
2569 cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2573 else if (insn == 0xc9)
2575 int start = *entry >> 4;
2576 int count = (*entry++) & 0xf;
2579 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2580 for (i = 0; i <= count; i++)
2582 cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2586 else if ((insn & 0xf8) == 0xd0)
2588 int count = insn & 0x7;
2591 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2592 for (i = 0; i <= count; i++)
2594 cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2600 /* Everything else is "spare". */
2605 /* If we restore SP from a register, assume this was the frame register.
2606 Otherwise just fall back to SP as frame register. */
2607 if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2608 cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2610 cache->framereg = ARM_SP_REGNUM;
2612 /* Determine offset to previous frame. */
2614 = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2616 /* We already got the previous SP. */
2617 cache->prev_sp = vsp;
2622 /* Unwinding via ARM exception table entries. Note that the sniffer
2623 already computes a filled-in prologue cache, which is then used
2624 with the same arm_prologue_this_id and arm_prologue_prev_register
2625 routines also used for prologue-parsing based unwinding. */
2628 arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2629 struct frame_info *this_frame,
2630 void **this_prologue_cache)
2632 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2633 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2634 CORE_ADDR addr_in_block, exidx_region, func_start;
2635 struct arm_prologue_cache *cache;
2638 /* See if we have an ARM exception table entry covering this address. */
2639 addr_in_block = get_frame_address_in_block (this_frame);
2640 entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2644 /* The ARM exception table does not describe unwind information
2645 for arbitrary PC values, but is guaranteed to be correct only
2646 at call sites. We have to decide here whether we want to use
2647 ARM exception table information for this frame, or fall back
2648 to using prologue parsing. (Note that if we have DWARF CFI,
2649 this sniffer isn't even called -- CFI is always preferred.)
2651 Before we make this decision, however, we check whether we
2652 actually have *symbol* information for the current frame.
2653 If not, prologue parsing would not work anyway, so we might
2654 as well use the exception table and hope for the best. */
2655 if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2659 /* If the next frame is "normal", we are at a call site in this
2660 frame, so exception information is guaranteed to be valid. */
2661 if (get_next_frame (this_frame)
2662 && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2665 /* We also assume exception information is valid if we're currently
2666 blocked in a system call. The system library is supposed to
2667 ensure this, so that e.g. pthread cancellation works. */
2668 if (arm_frame_is_thumb (this_frame))
2672 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2,
2673 2, byte_order_for_code, &insn)
2674 && (insn & 0xff00) == 0xdf00 /* svc */)
2681 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4,
2682 4, byte_order_for_code, &insn)
2683 && (insn & 0x0f000000) == 0x0f000000 /* svc */)
2687 /* Bail out if we don't know that exception information is valid. */
2691 /* The ARM exception index does not mark the *end* of the region
2692 covered by the entry, and some functions will not have any entry.
2693 To correctly recognize the end of the covered region, the linker
2694 should have inserted dummy records with a CANTUNWIND marker.
2696 Unfortunately, current versions of GNU ld do not reliably do
2697 this, and thus we may have found an incorrect entry above.
2698 As a (temporary) sanity check, we only use the entry if it
2699 lies *within* the bounds of the function. Note that this check
2700 might reject perfectly valid entries that just happen to cover
2701 multiple functions; therefore this check ought to be removed
2702 once the linker is fixed. */
2703 if (func_start > exidx_region)
2707 /* Decode the list of unwinding instructions into a prologue cache.
2708 Note that this may fail due to e.g. a "refuse to unwind" code. */
2709 cache = arm_exidx_fill_cache (this_frame, entry);
2713 *this_prologue_cache = cache;
2717 struct frame_unwind arm_exidx_unwind = {
2719 default_frame_unwind_stop_reason,
2720 arm_prologue_this_id,
2721 arm_prologue_prev_register,
2723 arm_exidx_unwind_sniffer
2726 static struct arm_prologue_cache *
2727 arm_make_epilogue_frame_cache (struct frame_info *this_frame)
2729 struct arm_prologue_cache *cache;
2732 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2733 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2735 /* Still rely on the offset calculated from prologue. */
2736 arm_scan_prologue (this_frame, cache);
2738 /* Since we are in epilogue, the SP has been restored. */
2739 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2741 /* Calculate actual addresses of saved registers using offsets
2742 determined by arm_scan_prologue. */
2743 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
2744 if (trad_frame_addr_p (cache->saved_regs, reg))
2745 cache->saved_regs[reg].addr += cache->prev_sp;
2750 /* Implementation of function hook 'this_id' in
2751 'struct frame_uwnind' for epilogue unwinder. */
2754 arm_epilogue_frame_this_id (struct frame_info *this_frame,
2756 struct frame_id *this_id)
2758 struct arm_prologue_cache *cache;
2761 if (*this_cache == NULL)
2762 *this_cache = arm_make_epilogue_frame_cache (this_frame);
2763 cache = (struct arm_prologue_cache *) *this_cache;
2765 /* Use function start address as part of the frame ID. If we cannot
2766 identify the start address (due to missing symbol information),
2767 fall back to just using the current PC. */
2768 pc = get_frame_pc (this_frame);
2769 func = get_frame_func (this_frame);
2773 (*this_id) = frame_id_build (cache->prev_sp, pc);
2776 /* Implementation of function hook 'prev_register' in
2777 'struct frame_uwnind' for epilogue unwinder. */
2779 static struct value *
2780 arm_epilogue_frame_prev_register (struct frame_info *this_frame,
2781 void **this_cache, int regnum)
2783 if (*this_cache == NULL)
2784 *this_cache = arm_make_epilogue_frame_cache (this_frame);
2786 return arm_prologue_prev_register (this_frame, this_cache, regnum);
2789 static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch,
2791 static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch,
2794 /* Implementation of function hook 'sniffer' in
2795 'struct frame_uwnind' for epilogue unwinder. */
2798 arm_epilogue_frame_sniffer (const struct frame_unwind *self,
2799 struct frame_info *this_frame,
2800 void **this_prologue_cache)
2802 if (frame_relative_level (this_frame) == 0)
2804 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2805 CORE_ADDR pc = get_frame_pc (this_frame);
2807 if (arm_frame_is_thumb (this_frame))
2808 return thumb_stack_frame_destroyed_p (gdbarch, pc);
2810 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
2816 /* Frame unwinder from epilogue. */
2818 static const struct frame_unwind arm_epilogue_frame_unwind =
2821 default_frame_unwind_stop_reason,
2822 arm_epilogue_frame_this_id,
2823 arm_epilogue_frame_prev_register,
2825 arm_epilogue_frame_sniffer,
2828 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2829 trampoline, return the target PC. Otherwise return 0.
2831 void call0a (char c, short s, int i, long l) {}
2835 (*pointer_to_call0a) (c, s, i, l);
2838 Instead of calling a stub library function _call_via_xx (xx is
2839 the register name), GCC may inline the trampoline in the object
2840 file as below (register r2 has the address of call0a).
2843 .type main, %function
2852 The trampoline 'bx r2' doesn't belong to main. */
2855 arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc)
2857 /* The heuristics of recognizing such trampoline is that FRAME is
2858 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2859 if (arm_frame_is_thumb (frame))
2863 if (target_read_memory (pc, buf, 2) == 0)
2865 struct gdbarch *gdbarch = get_frame_arch (frame);
2866 enum bfd_endian byte_order_for_code
2867 = gdbarch_byte_order_for_code (gdbarch);
2869 = extract_unsigned_integer (buf, 2, byte_order_for_code);
2871 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
2874 = get_frame_register_unsigned (frame, bits (insn, 3, 6));
2876 /* Clear the LSB so that gdb core sets step-resume
2877 breakpoint at the right address. */
2878 return UNMAKE_THUMB_ADDR (dest);
2886 static struct arm_prologue_cache *
2887 arm_make_stub_cache (struct frame_info *this_frame)
2889 struct arm_prologue_cache *cache;
2891 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2892 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2894 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
2899 /* Our frame ID for a stub frame is the current SP and LR. */
2902 arm_stub_this_id (struct frame_info *this_frame,
2904 struct frame_id *this_id)
2906 struct arm_prologue_cache *cache;
2908 if (*this_cache == NULL)
2909 *this_cache = arm_make_stub_cache (this_frame);
2910 cache = (struct arm_prologue_cache *) *this_cache;
2912 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2916 arm_stub_unwind_sniffer (const struct frame_unwind *self,
2917 struct frame_info *this_frame,
2918 void **this_prologue_cache)
2920 CORE_ADDR addr_in_block;
2922 CORE_ADDR pc, start_addr;
2925 addr_in_block = get_frame_address_in_block (this_frame);
2926 pc = get_frame_pc (this_frame);
2927 if (in_plt_section (addr_in_block)
2928 /* We also use the stub winder if the target memory is unreadable
2929 to avoid having the prologue unwinder trying to read it. */
2930 || target_read_memory (pc, dummy, 4) != 0)
2933 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0
2934 && arm_skip_bx_reg (this_frame, pc) != 0)
2940 struct frame_unwind arm_stub_unwind = {
2942 default_frame_unwind_stop_reason,
2944 arm_prologue_prev_register,
2946 arm_stub_unwind_sniffer
2949 /* Put here the code to store, into CACHE->saved_regs, the addresses
2950 of the saved registers of frame described by THIS_FRAME. CACHE is
2953 static struct arm_prologue_cache *
2954 arm_m_exception_cache (struct frame_info *this_frame)
2956 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2957 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2958 struct arm_prologue_cache *cache;
2959 CORE_ADDR unwound_sp;
2962 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2963 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2965 unwound_sp = get_frame_register_unsigned (this_frame,
2968 /* The hardware saves eight 32-bit words, comprising xPSR,
2969 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2970 "B1.5.6 Exception entry behavior" in
2971 "ARMv7-M Architecture Reference Manual". */
2972 cache->saved_regs[0].addr = unwound_sp;
2973 cache->saved_regs[1].addr = unwound_sp + 4;
2974 cache->saved_regs[2].addr = unwound_sp + 8;
2975 cache->saved_regs[3].addr = unwound_sp + 12;
2976 cache->saved_regs[12].addr = unwound_sp + 16;
2977 cache->saved_regs[14].addr = unwound_sp + 20;
2978 cache->saved_regs[15].addr = unwound_sp + 24;
2979 cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28;
2981 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2982 aligner between the top of the 32-byte stack frame and the
2983 previous context's stack pointer. */
2984 cache->prev_sp = unwound_sp + 32;
2985 if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr)
2986 && (xpsr & (1 << 9)) != 0)
2987 cache->prev_sp += 4;
2992 /* Implementation of function hook 'this_id' in
2993 'struct frame_uwnind'. */
2996 arm_m_exception_this_id (struct frame_info *this_frame,
2998 struct frame_id *this_id)
3000 struct arm_prologue_cache *cache;
3002 if (*this_cache == NULL)
3003 *this_cache = arm_m_exception_cache (this_frame);
3004 cache = (struct arm_prologue_cache *) *this_cache;
3006 /* Our frame ID for a stub frame is the current SP and LR. */
3007 *this_id = frame_id_build (cache->prev_sp,
3008 get_frame_pc (this_frame));
3011 /* Implementation of function hook 'prev_register' in
3012 'struct frame_uwnind'. */
3014 static struct value *
3015 arm_m_exception_prev_register (struct frame_info *this_frame,
3019 struct arm_prologue_cache *cache;
3021 if (*this_cache == NULL)
3022 *this_cache = arm_m_exception_cache (this_frame);
3023 cache = (struct arm_prologue_cache *) *this_cache;
3025 /* The value was already reconstructed into PREV_SP. */
3026 if (prev_regnum == ARM_SP_REGNUM)
3027 return frame_unwind_got_constant (this_frame, prev_regnum,
3030 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
3034 /* Implementation of function hook 'sniffer' in
3035 'struct frame_uwnind'. */
3038 arm_m_exception_unwind_sniffer (const struct frame_unwind *self,
3039 struct frame_info *this_frame,
3040 void **this_prologue_cache)
3042 CORE_ADDR this_pc = get_frame_pc (this_frame);
3044 /* No need to check is_m; this sniffer is only registered for
3045 M-profile architectures. */
3047 /* Check if exception frame returns to a magic PC value. */
3048 return arm_m_addr_is_magic (this_pc);
3051 /* Frame unwinder for M-profile exceptions. */
3053 struct frame_unwind arm_m_exception_unwind =
3056 default_frame_unwind_stop_reason,
3057 arm_m_exception_this_id,
3058 arm_m_exception_prev_register,
3060 arm_m_exception_unwind_sniffer
3064 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
3066 struct arm_prologue_cache *cache;
3068 if (*this_cache == NULL)
3069 *this_cache = arm_make_prologue_cache (this_frame);
3070 cache = (struct arm_prologue_cache *) *this_cache;
3072 return cache->prev_sp - cache->framesize;
3075 struct frame_base arm_normal_base = {
3076 &arm_prologue_unwind,
3077 arm_normal_frame_base,
3078 arm_normal_frame_base,
3079 arm_normal_frame_base
3082 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3083 dummy frame. The frame ID's base needs to match the TOS value
3084 saved by save_dummy_frame_tos() and returned from
3085 arm_push_dummy_call, and the PC needs to match the dummy frame's
3088 static struct frame_id
3089 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3091 return frame_id_build (get_frame_register_unsigned (this_frame,
3093 get_frame_pc (this_frame));
3096 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3097 be used to construct the previous frame's ID, after looking up the
3098 containing function). */
3101 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
3104 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
3105 return arm_addr_bits_remove (gdbarch, pc);
3109 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
3111 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
3114 static struct value *
3115 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
3118 struct gdbarch * gdbarch = get_frame_arch (this_frame);
3120 ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
3125 /* The PC is normally copied from the return column, which
3126 describes saves of LR. However, that version may have an
3127 extra bit set to indicate Thumb state. The bit is not
3129 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3130 return frame_unwind_got_constant (this_frame, regnum,
3131 arm_addr_bits_remove (gdbarch, lr));
3134 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3135 cpsr = get_frame_register_unsigned (this_frame, regnum);
3136 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
3137 if (IS_THUMB_ADDR (lr))
3141 return frame_unwind_got_constant (this_frame, regnum, cpsr);
3144 internal_error (__FILE__, __LINE__,
3145 _("Unexpected register %d"), regnum);
3150 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3151 struct dwarf2_frame_state_reg *reg,
3152 struct frame_info *this_frame)
3158 reg->how = DWARF2_FRAME_REG_FN;
3159 reg->loc.fn = arm_dwarf2_prev_register;
3162 reg->how = DWARF2_FRAME_REG_CFA;
3167 /* Implement the stack_frame_destroyed_p gdbarch method. */
3170 thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3172 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3173 unsigned int insn, insn2;
3174 int found_return = 0, found_stack_adjust = 0;
3175 CORE_ADDR func_start, func_end;
3179 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3182 /* The epilogue is a sequence of instructions along the following lines:
3184 - add stack frame size to SP or FP
3185 - [if frame pointer used] restore SP from FP
3186 - restore registers from SP [may include PC]
3187 - a return-type instruction [if PC wasn't already restored]
3189 In a first pass, we scan forward from the current PC and verify the
3190 instructions we find as compatible with this sequence, ending in a
3193 However, this is not sufficient to distinguish indirect function calls
3194 within a function from indirect tail calls in the epilogue in some cases.
3195 Therefore, if we didn't already find any SP-changing instruction during
3196 forward scan, we add a backward scanning heuristic to ensure we actually
3197 are in the epilogue. */
3200 while (scan_pc < func_end && !found_return)
3202 if (target_read_memory (scan_pc, buf, 2))
3206 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3208 if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3210 else if (insn == 0x46f7) /* mov pc, lr */
3212 else if (thumb_instruction_restores_sp (insn))
3214 if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */
3217 else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */
3219 if (target_read_memory (scan_pc, buf, 2))
3223 insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3225 if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3227 if (insn2 & 0x8000) /* <registers> include PC. */
3230 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3231 && (insn2 & 0x0fff) == 0x0b04)
3233 if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3236 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3237 && (insn2 & 0x0e00) == 0x0a00)
3249 /* Since any instruction in the epilogue sequence, with the possible
3250 exception of return itself, updates the stack pointer, we need to
3251 scan backwards for at most one instruction. Try either a 16-bit or
3252 a 32-bit instruction. This is just a heuristic, so we do not worry
3253 too much about false positives. */
3255 if (pc - 4 < func_start)
3257 if (target_read_memory (pc - 4, buf, 4))
3260 insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3261 insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3263 if (thumb_instruction_restores_sp (insn2))
3264 found_stack_adjust = 1;
3265 else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3266 found_stack_adjust = 1;
3267 else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3268 && (insn2 & 0x0fff) == 0x0b04)
3269 found_stack_adjust = 1;
3270 else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3271 && (insn2 & 0x0e00) == 0x0a00)
3272 found_stack_adjust = 1;
3274 return found_stack_adjust;
3278 arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc)
3280 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3283 CORE_ADDR func_start, func_end;
3285 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3288 /* We are in the epilogue if the previous instruction was a stack
3289 adjustment and the next instruction is a possible return (bx, mov
3290 pc, or pop). We could have to scan backwards to find the stack
3291 adjustment, or forwards to find the return, but this is a decent
3292 approximation. First scan forwards. */
3295 insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3296 if (bits (insn, 28, 31) != INST_NV)
3298 if ((insn & 0x0ffffff0) == 0x012fff10)
3301 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3304 else if ((insn & 0x0fff0000) == 0x08bd0000
3305 && (insn & 0x0000c000) != 0)
3306 /* POP (LDMIA), including PC or LR. */
3313 /* Scan backwards. This is just a heuristic, so do not worry about
3314 false positives from mode changes. */
3316 if (pc < func_start + 4)
3319 insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3320 if (arm_instruction_restores_sp (insn))
3326 /* Implement the stack_frame_destroyed_p gdbarch method. */
3329 arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3331 if (arm_pc_is_thumb (gdbarch, pc))
3332 return thumb_stack_frame_destroyed_p (gdbarch, pc);
3334 return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
3337 /* When arguments must be pushed onto the stack, they go on in reverse
3338 order. The code below implements a FILO (stack) to do this. */
3343 struct stack_item *prev;
3347 static struct stack_item *
3348 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
3350 struct stack_item *si;
3351 si = XNEW (struct stack_item);
3352 si->data = (gdb_byte *) xmalloc (len);
3355 memcpy (si->data, contents, len);
3359 static struct stack_item *
3360 pop_stack_item (struct stack_item *si)
3362 struct stack_item *dead = si;
3370 /* Return the alignment (in bytes) of the given type. */
3373 arm_type_align (struct type *t)
3379 t = check_typedef (t);
3380 switch (TYPE_CODE (t))
3383 /* Should never happen. */
3384 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
3388 case TYPE_CODE_ENUM:
3392 case TYPE_CODE_RANGE:
3394 case TYPE_CODE_RVALUE_REF:
3395 case TYPE_CODE_CHAR:
3396 case TYPE_CODE_BOOL:
3397 return TYPE_LENGTH (t);
3399 case TYPE_CODE_ARRAY:
3400 if (TYPE_VECTOR (t))
3402 /* Use the natural alignment for vector types (the same for
3403 scalar type), but the maximum alignment is 64-bit. */
3404 if (TYPE_LENGTH (t) > 8)
3407 return TYPE_LENGTH (t);
3410 return arm_type_align (TYPE_TARGET_TYPE (t));
3411 case TYPE_CODE_COMPLEX:
3412 return arm_type_align (TYPE_TARGET_TYPE (t));
3414 case TYPE_CODE_STRUCT:
3415 case TYPE_CODE_UNION:
3417 for (n = 0; n < TYPE_NFIELDS (t); n++)
3419 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
3427 /* Possible base types for a candidate for passing and returning in
3430 enum arm_vfp_cprc_base_type
3439 /* The length of one element of base type B. */
3442 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
3446 case VFP_CPRC_SINGLE:
3448 case VFP_CPRC_DOUBLE:
3450 case VFP_CPRC_VEC64:
3452 case VFP_CPRC_VEC128:
3455 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3460 /* The character ('s', 'd' or 'q') for the type of VFP register used
3461 for passing base type B. */
3464 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
3468 case VFP_CPRC_SINGLE:
3470 case VFP_CPRC_DOUBLE:
3472 case VFP_CPRC_VEC64:
3474 case VFP_CPRC_VEC128:
3477 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
3482 /* Determine whether T may be part of a candidate for passing and
3483 returning in VFP registers, ignoring the limit on the total number
3484 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3485 classification of the first valid component found; if it is not
3486 VFP_CPRC_UNKNOWN, all components must have the same classification
3487 as *BASE_TYPE. If it is found that T contains a type not permitted
3488 for passing and returning in VFP registers, a type differently
3489 classified from *BASE_TYPE, or two types differently classified
3490 from each other, return -1, otherwise return the total number of
3491 base-type elements found (possibly 0 in an empty structure or
3492 array). Vector types are not currently supported, matching the
3493 generic AAPCS support. */
3496 arm_vfp_cprc_sub_candidate (struct type *t,
3497 enum arm_vfp_cprc_base_type *base_type)
3499 t = check_typedef (t);
3500 switch (TYPE_CODE (t))
3503 switch (TYPE_LENGTH (t))
3506 if (*base_type == VFP_CPRC_UNKNOWN)
3507 *base_type = VFP_CPRC_SINGLE;
3508 else if (*base_type != VFP_CPRC_SINGLE)
3513 if (*base_type == VFP_CPRC_UNKNOWN)
3514 *base_type = VFP_CPRC_DOUBLE;
3515 else if (*base_type != VFP_CPRC_DOUBLE)
3524 case TYPE_CODE_COMPLEX:
3525 /* Arguments of complex T where T is one of the types float or
3526 double get treated as if they are implemented as:
3535 switch (TYPE_LENGTH (t))
3538 if (*base_type == VFP_CPRC_UNKNOWN)
3539 *base_type = VFP_CPRC_SINGLE;
3540 else if (*base_type != VFP_CPRC_SINGLE)
3545 if (*base_type == VFP_CPRC_UNKNOWN)
3546 *base_type = VFP_CPRC_DOUBLE;
3547 else if (*base_type != VFP_CPRC_DOUBLE)
3556 case TYPE_CODE_ARRAY:
3558 if (TYPE_VECTOR (t))
3560 /* A 64-bit or 128-bit containerized vector type are VFP
3562 switch (TYPE_LENGTH (t))
3565 if (*base_type == VFP_CPRC_UNKNOWN)
3566 *base_type = VFP_CPRC_VEC64;
3569 if (*base_type == VFP_CPRC_UNKNOWN)
3570 *base_type = VFP_CPRC_VEC128;
3581 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t),
3585 if (TYPE_LENGTH (t) == 0)
3587 gdb_assert (count == 0);
3590 else if (count == 0)
3592 unitlen = arm_vfp_cprc_unit_length (*base_type);
3593 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
3594 return TYPE_LENGTH (t) / unitlen;
3599 case TYPE_CODE_STRUCT:
3604 for (i = 0; i < TYPE_NFIELDS (t); i++)
3608 if (!field_is_static (&TYPE_FIELD (t, i)))
3609 sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3611 if (sub_count == -1)
3615 if (TYPE_LENGTH (t) == 0)
3617 gdb_assert (count == 0);
3620 else if (count == 0)
3622 unitlen = arm_vfp_cprc_unit_length (*base_type);
3623 if (TYPE_LENGTH (t) != unitlen * count)
3628 case TYPE_CODE_UNION:
3633 for (i = 0; i < TYPE_NFIELDS (t); i++)
3635 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
3637 if (sub_count == -1)
3639 count = (count > sub_count ? count : sub_count);
3641 if (TYPE_LENGTH (t) == 0)
3643 gdb_assert (count == 0);
3646 else if (count == 0)
3648 unitlen = arm_vfp_cprc_unit_length (*base_type);
3649 if (TYPE_LENGTH (t) != unitlen * count)
3661 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3662 if passed to or returned from a non-variadic function with the VFP
3663 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3664 *BASE_TYPE to the base type for T and *COUNT to the number of
3665 elements of that base type before returning. */
3668 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
3671 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
3672 int c = arm_vfp_cprc_sub_candidate (t, &b);
3673 if (c <= 0 || c > 4)
3680 /* Return 1 if the VFP ABI should be used for passing arguments to and
3681 returning values from a function of type FUNC_TYPE, 0
3685 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
3687 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3688 /* Variadic functions always use the base ABI. Assume that functions
3689 without debug info are not variadic. */
3690 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
3692 /* The VFP ABI is only supported as a variant of AAPCS. */
3693 if (tdep->arm_abi != ARM_ABI_AAPCS)
3695 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
3698 /* We currently only support passing parameters in integer registers, which
3699 conforms with GCC's default model, and VFP argument passing following
3700 the VFP variant of AAPCS. Several other variants exist and
3701 we should probably support some of them based on the selected ABI. */
3704 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3705 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3706 struct value **args, CORE_ADDR sp, int struct_return,
3707 CORE_ADDR struct_addr)
3709 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3713 struct stack_item *si = NULL;
3716 unsigned vfp_regs_free = (1 << 16) - 1;
3718 /* Determine the type of this function and whether the VFP ABI
3720 ftype = check_typedef (value_type (function));
3721 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
3722 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
3723 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
3725 /* Set the return address. For the ARM, the return breakpoint is
3726 always at BP_ADDR. */
3727 if (arm_pc_is_thumb (gdbarch, bp_addr))
3729 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
3731 /* Walk through the list of args and determine how large a temporary
3732 stack is required. Need to take care here as structs may be
3733 passed on the stack, and we have to push them. */
3736 argreg = ARM_A1_REGNUM;
3739 /* The struct_return pointer occupies the first parameter
3740 passing register. */
3744 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
3745 gdbarch_register_name (gdbarch, argreg),
3746 paddress (gdbarch, struct_addr));
3747 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
3751 for (argnum = 0; argnum < nargs; argnum++)
3754 struct type *arg_type;
3755 struct type *target_type;
3756 enum type_code typecode;
3757 const bfd_byte *val;
3759 enum arm_vfp_cprc_base_type vfp_base_type;
3761 int may_use_core_reg = 1;
3763 arg_type = check_typedef (value_type (args[argnum]));
3764 len = TYPE_LENGTH (arg_type);
3765 target_type = TYPE_TARGET_TYPE (arg_type);
3766 typecode = TYPE_CODE (arg_type);
3767 val = value_contents (args[argnum]);
3769 align = arm_type_align (arg_type);
3770 /* Round alignment up to a whole number of words. */
3771 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
3772 /* Different ABIs have different maximum alignments. */
3773 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
3775 /* The APCS ABI only requires word alignment. */
3776 align = INT_REGISTER_SIZE;
3780 /* The AAPCS requires at most doubleword alignment. */
3781 if (align > INT_REGISTER_SIZE * 2)
3782 align = INT_REGISTER_SIZE * 2;
3786 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
3794 /* Because this is a CPRC it cannot go in a core register or
3795 cause a core register to be skipped for alignment.
3796 Either it goes in VFP registers and the rest of this loop
3797 iteration is skipped for this argument, or it goes on the
3798 stack (and the stack alignment code is correct for this
3800 may_use_core_reg = 0;
3802 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
3803 shift = unit_length / 4;
3804 mask = (1 << (shift * vfp_base_count)) - 1;
3805 for (regno = 0; regno < 16; regno += shift)
3806 if (((vfp_regs_free >> regno) & mask) == mask)
3815 vfp_regs_free &= ~(mask << regno);
3816 reg_scaled = regno / shift;
3817 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
3818 for (i = 0; i < vfp_base_count; i++)
3822 if (reg_char == 'q')
3823 arm_neon_quad_write (gdbarch, regcache, reg_scaled + i,
3824 val + i * unit_length);
3827 xsnprintf (name_buf, sizeof (name_buf), "%c%d",
3828 reg_char, reg_scaled + i);
3829 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
3831 regcache_cooked_write (regcache, regnum,
3832 val + i * unit_length);
3839 /* This CPRC could not go in VFP registers, so all VFP
3840 registers are now marked as used. */
3845 /* Push stack padding for dowubleword alignment. */
3846 if (nstack & (align - 1))
3848 si = push_stack_item (si, val, INT_REGISTER_SIZE);
3849 nstack += INT_REGISTER_SIZE;
3852 /* Doubleword aligned quantities must go in even register pairs. */
3853 if (may_use_core_reg
3854 && argreg <= ARM_LAST_ARG_REGNUM
3855 && align > INT_REGISTER_SIZE
3859 /* If the argument is a pointer to a function, and it is a
3860 Thumb function, create a LOCAL copy of the value and set
3861 the THUMB bit in it. */
3862 if (TYPE_CODE_PTR == typecode
3863 && target_type != NULL
3864 && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type)))
3866 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
3867 if (arm_pc_is_thumb (gdbarch, regval))
3869 bfd_byte *copy = (bfd_byte *) alloca (len);
3870 store_unsigned_integer (copy, len, byte_order,
3871 MAKE_THUMB_ADDR (regval));
3876 /* Copy the argument to general registers or the stack in
3877 register-sized pieces. Large arguments are split between
3878 registers and stack. */
3881 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
3883 = extract_unsigned_integer (val, partial_len, byte_order);
3885 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
3887 /* The argument is being passed in a general purpose
3889 if (byte_order == BFD_ENDIAN_BIG)
3890 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
3892 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
3894 gdbarch_register_name
3896 phex (regval, INT_REGISTER_SIZE));
3897 regcache_cooked_write_unsigned (regcache, argreg, regval);
3902 gdb_byte buf[INT_REGISTER_SIZE];
3904 memset (buf, 0, sizeof (buf));
3905 store_unsigned_integer (buf, partial_len, byte_order, regval);
3907 /* Push the arguments onto the stack. */
3909 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
3911 si = push_stack_item (si, buf, INT_REGISTER_SIZE);
3912 nstack += INT_REGISTER_SIZE;
3919 /* If we have an odd number of words to push, then decrement the stack
3920 by one word now, so first stack argument will be dword aligned. */
3927 write_memory (sp, si->data, si->len);
3928 si = pop_stack_item (si);
3931 /* Finally, update teh SP register. */
3932 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
3938 /* Always align the frame to an 8-byte boundary. This is required on
3939 some platforms and harmless on the rest. */
3942 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3944 /* Align the stack to eight bytes. */
3945 return sp & ~ (CORE_ADDR) 7;
3949 print_fpu_flags (struct ui_file *file, int flags)
3951 if (flags & (1 << 0))
3952 fputs_filtered ("IVO ", file);
3953 if (flags & (1 << 1))
3954 fputs_filtered ("DVZ ", file);
3955 if (flags & (1 << 2))
3956 fputs_filtered ("OFL ", file);
3957 if (flags & (1 << 3))
3958 fputs_filtered ("UFL ", file);
3959 if (flags & (1 << 4))
3960 fputs_filtered ("INX ", file);
3961 fputc_filtered ('\n', file);
3964 /* Print interesting information about the floating point processor
3965 (if present) or emulator. */
3967 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
3968 struct frame_info *frame, const char *args)
3970 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
3973 type = (status >> 24) & 127;
3974 if (status & (1 << 31))
3975 fprintf_filtered (file, _("Hardware FPU type %d\n"), type);
3977 fprintf_filtered (file, _("Software FPU type %d\n"), type);
3978 /* i18n: [floating point unit] mask */
3979 fputs_filtered (_("mask: "), file);
3980 print_fpu_flags (file, status >> 16);
3981 /* i18n: [floating point unit] flags */
3982 fputs_filtered (_("flags: "), file);
3983 print_fpu_flags (file, status);
3986 /* Construct the ARM extended floating point type. */
3987 static struct type *
3988 arm_ext_type (struct gdbarch *gdbarch)
3990 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3992 if (!tdep->arm_ext_type)
3994 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
3995 floatformats_arm_ext);
3997 return tdep->arm_ext_type;
4000 static struct type *
4001 arm_neon_double_type (struct gdbarch *gdbarch)
4003 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4005 if (tdep->neon_double_type == NULL)
4007 struct type *t, *elem;
4009 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d",
4011 elem = builtin_type (gdbarch)->builtin_uint8;
4012 append_composite_type_field (t, "u8", init_vector_type (elem, 8));
4013 elem = builtin_type (gdbarch)->builtin_uint16;
4014 append_composite_type_field (t, "u16", init_vector_type (elem, 4));
4015 elem = builtin_type (gdbarch)->builtin_uint32;
4016 append_composite_type_field (t, "u32", init_vector_type (elem, 2));
4017 elem = builtin_type (gdbarch)->builtin_uint64;
4018 append_composite_type_field (t, "u64", elem);
4019 elem = builtin_type (gdbarch)->builtin_float;
4020 append_composite_type_field (t, "f32", init_vector_type (elem, 2));
4021 elem = builtin_type (gdbarch)->builtin_double;
4022 append_composite_type_field (t, "f64", elem);
4024 TYPE_VECTOR (t) = 1;
4025 TYPE_NAME (t) = "neon_d";
4026 tdep->neon_double_type = t;
4029 return tdep->neon_double_type;
4032 /* FIXME: The vector types are not correctly ordered on big-endian
4033 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4034 bits of d0 - regardless of what unit size is being held in d0. So
4035 the offset of the first uint8 in d0 is 7, but the offset of the
4036 first float is 4. This code works as-is for little-endian
4039 static struct type *
4040 arm_neon_quad_type (struct gdbarch *gdbarch)
4042 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4044 if (tdep->neon_quad_type == NULL)
4046 struct type *t, *elem;
4048 t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q",
4050 elem = builtin_type (gdbarch)->builtin_uint8;
4051 append_composite_type_field (t, "u8", init_vector_type (elem, 16));
4052 elem = builtin_type (gdbarch)->builtin_uint16;
4053 append_composite_type_field (t, "u16", init_vector_type (elem, 8));
4054 elem = builtin_type (gdbarch)->builtin_uint32;
4055 append_composite_type_field (t, "u32", init_vector_type (elem, 4));
4056 elem = builtin_type (gdbarch)->builtin_uint64;
4057 append_composite_type_field (t, "u64", init_vector_type (elem, 2));
4058 elem = builtin_type (gdbarch)->builtin_float;
4059 append_composite_type_field (t, "f32", init_vector_type (elem, 4));
4060 elem = builtin_type (gdbarch)->builtin_double;
4061 append_composite_type_field (t, "f64", init_vector_type (elem, 2));
4063 TYPE_VECTOR (t) = 1;
4064 TYPE_NAME (t) = "neon_q";
4065 tdep->neon_quad_type = t;
4068 return tdep->neon_quad_type;
4071 /* Return the GDB type object for the "standard" data type of data in
4074 static struct type *
4075 arm_register_type (struct gdbarch *gdbarch, int regnum)
4077 int num_regs = gdbarch_num_regs (gdbarch);
4079 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
4080 && regnum >= num_regs && regnum < num_regs + 32)
4081 return builtin_type (gdbarch)->builtin_float;
4083 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
4084 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4085 return arm_neon_quad_type (gdbarch);
4087 /* If the target description has register information, we are only
4088 in this function so that we can override the types of
4089 double-precision registers for NEON. */
4090 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
4092 struct type *t = tdesc_register_type (gdbarch, regnum);
4094 if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32
4095 && TYPE_CODE (t) == TYPE_CODE_FLT
4096 && gdbarch_tdep (gdbarch)->have_neon)
4097 return arm_neon_double_type (gdbarch);
4102 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
4104 if (!gdbarch_tdep (gdbarch)->have_fpa_registers)
4105 return builtin_type (gdbarch)->builtin_void;
4107 return arm_ext_type (gdbarch);
4109 else if (regnum == ARM_SP_REGNUM)
4110 return builtin_type (gdbarch)->builtin_data_ptr;
4111 else if (regnum == ARM_PC_REGNUM)
4112 return builtin_type (gdbarch)->builtin_func_ptr;
4113 else if (regnum >= ARRAY_SIZE (arm_register_names))
4114 /* These registers are only supported on targets which supply
4115 an XML description. */
4116 return builtin_type (gdbarch)->builtin_int0;
4118 return builtin_type (gdbarch)->builtin_uint32;
4121 /* Map a DWARF register REGNUM onto the appropriate GDB register
4125 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
4127 /* Core integer regs. */
4128 if (reg >= 0 && reg <= 15)
4131 /* Legacy FPA encoding. These were once used in a way which
4132 overlapped with VFP register numbering, so their use is
4133 discouraged, but GDB doesn't support the ARM toolchain
4134 which used them for VFP. */
4135 if (reg >= 16 && reg <= 23)
4136 return ARM_F0_REGNUM + reg - 16;
4138 /* New assignments for the FPA registers. */
4139 if (reg >= 96 && reg <= 103)
4140 return ARM_F0_REGNUM + reg - 96;
4142 /* WMMX register assignments. */
4143 if (reg >= 104 && reg <= 111)
4144 return ARM_WCGR0_REGNUM + reg - 104;
4146 if (reg >= 112 && reg <= 127)
4147 return ARM_WR0_REGNUM + reg - 112;
4149 if (reg >= 192 && reg <= 199)
4150 return ARM_WC0_REGNUM + reg - 192;
4152 /* VFP v2 registers. A double precision value is actually
4153 in d1 rather than s2, but the ABI only defines numbering
4154 for the single precision registers. This will "just work"
4155 in GDB for little endian targets (we'll read eight bytes,
4156 starting in s0 and then progressing to s1), but will be
4157 reversed on big endian targets with VFP. This won't
4158 be a problem for the new Neon quad registers; you're supposed
4159 to use DW_OP_piece for those. */
4160 if (reg >= 64 && reg <= 95)
4164 xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64);
4165 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4169 /* VFP v3 / Neon registers. This range is also used for VFP v2
4170 registers, except that it now describes d0 instead of s0. */
4171 if (reg >= 256 && reg <= 287)
4175 xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256);
4176 return user_reg_map_name_to_regnum (gdbarch, name_buf,
4183 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4185 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
4188 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
4190 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
4191 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
4193 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
4194 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
4196 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
4197 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
4199 if (reg < NUM_GREGS)
4200 return SIM_ARM_R0_REGNUM + reg;
4203 if (reg < NUM_FREGS)
4204 return SIM_ARM_FP0_REGNUM + reg;
4207 if (reg < NUM_SREGS)
4208 return SIM_ARM_FPS_REGNUM + reg;
4211 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
4214 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4215 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4216 It is thought that this is is the floating-point register format on
4217 little-endian systems. */
4220 convert_from_extended (const struct floatformat *fmt, const void *ptr,
4221 void *dbl, int endianess)
4225 if (endianess == BFD_ENDIAN_BIG)
4226 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
4228 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
4230 floatformat_from_doublest (fmt, &d, dbl);
4234 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
4239 floatformat_to_doublest (fmt, ptr, &d);
4240 if (endianess == BFD_ENDIAN_BIG)
4241 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
4243 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
4247 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4248 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4249 NULL if an error occurs. BUF is freed. */
4252 extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr,
4253 int old_len, int new_len)
4256 int bytes_to_read = new_len - old_len;
4258 new_buf = (gdb_byte *) xmalloc (new_len);
4259 memcpy (new_buf + bytes_to_read, buf, old_len);
4261 if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0)
4269 /* An IT block is at most the 2-byte IT instruction followed by
4270 four 4-byte instructions. The furthest back we must search to
4271 find an IT block that affects the current instruction is thus
4272 2 + 3 * 4 == 14 bytes. */
4273 #define MAX_IT_BLOCK_PREFIX 14
4275 /* Use a quick scan if there are more than this many bytes of
4277 #define IT_SCAN_THRESHOLD 32
4279 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4280 A breakpoint in an IT block may not be hit, depending on the
4283 arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
4287 CORE_ADDR boundary, func_start;
4289 enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch);
4290 int i, any, last_it, last_it_count;
4292 /* If we are using BKPT breakpoints, none of this is necessary. */
4293 if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL)
4296 /* ARM mode does not have this problem. */
4297 if (!arm_pc_is_thumb (gdbarch, bpaddr))
4300 /* We are setting a breakpoint in Thumb code that could potentially
4301 contain an IT block. The first step is to find how much Thumb
4302 code there is; we do not need to read outside of known Thumb
4304 map_type = arm_find_mapping_symbol (bpaddr, &boundary);
4306 /* Thumb-2 code must have mapping symbols to have a chance. */
4309 bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr);
4311 if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL)
4312 && func_start > boundary)
4313 boundary = func_start;
4315 /* Search for a candidate IT instruction. We have to do some fancy
4316 footwork to distinguish a real IT instruction from the second
4317 half of a 32-bit instruction, but there is no need for that if
4318 there's no candidate. */
4319 buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX);
4321 /* No room for an IT instruction. */
4324 buf = (gdb_byte *) xmalloc (buf_len);
4325 if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0)
4328 for (i = 0; i < buf_len; i += 2)
4330 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4331 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4344 /* OK, the code bytes before this instruction contain at least one
4345 halfword which resembles an IT instruction. We know that it's
4346 Thumb code, but there are still two possibilities. Either the
4347 halfword really is an IT instruction, or it is the second half of
4348 a 32-bit Thumb instruction. The only way we can tell is to
4349 scan forwards from a known instruction boundary. */
4350 if (bpaddr - boundary > IT_SCAN_THRESHOLD)
4354 /* There's a lot of code before this instruction. Start with an
4355 optimistic search; it's easy to recognize halfwords that can
4356 not be the start of a 32-bit instruction, and use that to
4357 lock on to the instruction boundaries. */
4358 buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD);
4361 buf_len = IT_SCAN_THRESHOLD;
4364 for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2)
4366 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4367 if (thumb_insn_size (inst1) == 2)
4374 /* At this point, if DEFINITE, BUF[I] is the first place we
4375 are sure that we know the instruction boundaries, and it is far
4376 enough from BPADDR that we could not miss an IT instruction
4377 affecting BPADDR. If ! DEFINITE, give up - start from a
4381 buf = extend_buffer_earlier (buf, bpaddr, buf_len,
4385 buf_len = bpaddr - boundary;
4391 buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
4394 buf_len = bpaddr - boundary;
4398 /* Scan forwards. Find the last IT instruction before BPADDR. */
4403 unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order);
4405 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4410 else if (inst1 & 0x0002)
4412 else if (inst1 & 0x0004)
4417 i += thumb_insn_size (inst1);
4423 /* There wasn't really an IT instruction after all. */
4426 if (last_it_count < 1)
4427 /* It was too far away. */
4430 /* This really is a trouble spot. Move the breakpoint to the IT
4432 return bpaddr - buf_len + last_it;
4435 /* ARM displaced stepping support.
4437 Generally ARM displaced stepping works as follows:
4439 1. When an instruction is to be single-stepped, it is first decoded by
4440 arm_process_displaced_insn. Depending on the type of instruction, it is
4441 then copied to a scratch location, possibly in a modified form. The
4442 copy_* set of functions performs such modification, as necessary. A
4443 breakpoint is placed after the modified instruction in the scratch space
4444 to return control to GDB. Note in particular that instructions which
4445 modify the PC will no longer do so after modification.
4447 2. The instruction is single-stepped, by setting the PC to the scratch
4448 location address, and resuming. Control returns to GDB when the
4451 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4452 function used for the current instruction. This function's job is to
4453 put the CPU/memory state back to what it would have been if the
4454 instruction had been executed unmodified in its original location. */
4456 /* NOP instruction (mov r0, r0). */
4457 #define ARM_NOP 0xe1a00000
4458 #define THUMB_NOP 0x4600
4460 /* Helper for register reads for displaced stepping. In particular, this
4461 returns the PC as it would be seen by the instruction at its original
4465 displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4469 CORE_ADDR from = dsc->insn_addr;
4471 if (regno == ARM_PC_REGNUM)
4473 /* Compute pipeline offset:
4474 - When executing an ARM instruction, PC reads as the address of the
4475 current instruction plus 8.
4476 - When executing a Thumb instruction, PC reads as the address of the
4477 current instruction plus 4. */
4484 if (debug_displaced)
4485 fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n",
4486 (unsigned long) from);
4487 return (ULONGEST) from;
4491 regcache_cooked_read_unsigned (regs, regno, &ret);
4492 if (debug_displaced)
4493 fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n",
4494 regno, (unsigned long) ret);
4500 displaced_in_arm_mode (struct regcache *regs)
4503 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4505 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4507 return (ps & t_bit) == 0;
4510 /* Write to the PC as from a branch instruction. */
4513 branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4517 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4518 architecture versions < 6. */
4519 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4520 val & ~(ULONGEST) 0x3);
4522 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
4523 val & ~(ULONGEST) 0x1);
4526 /* Write to the PC as from a branch-exchange instruction. */
4529 bx_write_pc (struct regcache *regs, ULONGEST val)
4532 ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
4534 regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
4538 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit);
4539 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe);
4541 else if ((val & 2) == 0)
4543 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4544 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val);
4548 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4549 mode, align dest to 4 bytes). */
4550 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4551 regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit);
4552 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc);
4556 /* Write to the PC as if from a load instruction. */
4559 load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4562 if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
4563 bx_write_pc (regs, val);
4565 branch_write_pc (regs, dsc, val);
4568 /* Write to the PC as if from an ALU instruction. */
4571 alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
4574 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
4575 bx_write_pc (regs, val);
4577 branch_write_pc (regs, dsc, val);
4580 /* Helper for writing to registers for displaced stepping. Writing to the PC
4581 has a varying effects depending on the instruction which does the write:
4582 this is controlled by the WRITE_PC argument. */
4585 displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
4586 int regno, ULONGEST val, enum pc_write_style write_pc)
4588 if (regno == ARM_PC_REGNUM)
4590 if (debug_displaced)
4591 fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n",
4592 (unsigned long) val);
4595 case BRANCH_WRITE_PC:
4596 branch_write_pc (regs, dsc, val);
4600 bx_write_pc (regs, val);
4604 load_write_pc (regs, dsc, val);
4608 alu_write_pc (regs, dsc, val);
4611 case CANNOT_WRITE_PC:
4612 warning (_("Instruction wrote to PC in an unexpected way when "
4613 "single-stepping"));
4617 internal_error (__FILE__, __LINE__,
4618 _("Invalid argument to displaced_write_reg"));
4621 dsc->wrote_to_pc = 1;
4625 if (debug_displaced)
4626 fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n",
4627 regno, (unsigned long) val);
4628 regcache_cooked_write_unsigned (regs, regno, val);
4632 /* This function is used to concisely determine if an instruction INSN
4633 references PC. Register fields of interest in INSN should have the
4634 corresponding fields of BITMASK set to 0b1111. The function
4635 returns return 1 if any of these fields in INSN reference the PC
4636 (also 0b1111, r15), else it returns 0. */
4639 insn_references_pc (uint32_t insn, uint32_t bitmask)
4641 uint32_t lowbit = 1;
4643 while (bitmask != 0)
4647 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
4653 mask = lowbit * 0xf;
4655 if ((insn & mask) == mask)
4664 /* The simplest copy function. Many instructions have the same effect no
4665 matter what address they are executed at: in those cases, use this. */
4668 arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
4669 const char *iname, struct displaced_step_closure *dsc)
4671 if (debug_displaced)
4672 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
4673 "opcode/class '%s' unmodified\n", (unsigned long) insn,
4676 dsc->modinsn[0] = insn;
4682 thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
4683 uint16_t insn2, const char *iname,
4684 struct displaced_step_closure *dsc)
4686 if (debug_displaced)
4687 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
4688 "opcode/class '%s' unmodified\n", insn1, insn2,
4691 dsc->modinsn[0] = insn1;
4692 dsc->modinsn[1] = insn2;
4698 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4701 thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn,
4703 struct displaced_step_closure *dsc)
4705 if (debug_displaced)
4706 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
4707 "opcode/class '%s' unmodified\n", insn,
4710 dsc->modinsn[0] = insn;
4715 /* Preload instructions with immediate offset. */
4718 cleanup_preload (struct gdbarch *gdbarch,
4719 struct regcache *regs, struct displaced_step_closure *dsc)
4721 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4722 if (!dsc->u.preload.immed)
4723 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
4727 install_preload (struct gdbarch *gdbarch, struct regcache *regs,
4728 struct displaced_step_closure *dsc, unsigned int rn)
4731 /* Preload instructions:
4733 {pli/pld} [rn, #+/-imm]
4735 {pli/pld} [r0, #+/-imm]. */
4737 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4738 rn_val = displaced_read_reg (regs, dsc, rn);
4739 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4740 dsc->u.preload.immed = 1;
4742 dsc->cleanup = &cleanup_preload;
4746 arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
4747 struct displaced_step_closure *dsc)
4749 unsigned int rn = bits (insn, 16, 19);
4751 if (!insn_references_pc (insn, 0x000f0000ul))
4752 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
4754 if (debug_displaced)
4755 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4756 (unsigned long) insn);
4758 dsc->modinsn[0] = insn & 0xfff0ffff;
4760 install_preload (gdbarch, regs, dsc, rn);
4766 thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
4767 struct regcache *regs, struct displaced_step_closure *dsc)
4769 unsigned int rn = bits (insn1, 0, 3);
4770 unsigned int u_bit = bit (insn1, 7);
4771 int imm12 = bits (insn2, 0, 11);
4774 if (rn != ARM_PC_REGNUM)
4775 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
4777 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4778 PLD (literal) Encoding T1. */
4779 if (debug_displaced)
4780 fprintf_unfiltered (gdb_stdlog,
4781 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4782 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
4788 /* Rewrite instruction {pli/pld} PC imm12 into:
4789 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4793 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4795 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4796 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4798 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
4800 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
4801 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
4802 dsc->u.preload.immed = 0;
4804 /* {pli/pld} [r0, r1] */
4805 dsc->modinsn[0] = insn1 & 0xfff0;
4806 dsc->modinsn[1] = 0xf001;
4809 dsc->cleanup = &cleanup_preload;
4813 /* Preload instructions with register offset. */
4816 install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
4817 struct displaced_step_closure *dsc, unsigned int rn,
4820 ULONGEST rn_val, rm_val;
4822 /* Preload register-offset instructions:
4824 {pli/pld} [rn, rm {, shift}]
4826 {pli/pld} [r0, r1 {, shift}]. */
4828 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4829 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
4830 rn_val = displaced_read_reg (regs, dsc, rn);
4831 rm_val = displaced_read_reg (regs, dsc, rm);
4832 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4833 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
4834 dsc->u.preload.immed = 0;
4836 dsc->cleanup = &cleanup_preload;
4840 arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
4841 struct regcache *regs,
4842 struct displaced_step_closure *dsc)
4844 unsigned int rn = bits (insn, 16, 19);
4845 unsigned int rm = bits (insn, 0, 3);
4848 if (!insn_references_pc (insn, 0x000f000ful))
4849 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
4851 if (debug_displaced)
4852 fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n",
4853 (unsigned long) insn);
4855 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
4857 install_preload_reg (gdbarch, regs, dsc, rn, rm);
4861 /* Copy/cleanup coprocessor load and store instructions. */
4864 cleanup_copro_load_store (struct gdbarch *gdbarch,
4865 struct regcache *regs,
4866 struct displaced_step_closure *dsc)
4868 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
4870 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
4872 if (dsc->u.ldst.writeback)
4873 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
4877 install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
4878 struct displaced_step_closure *dsc,
4879 int writeback, unsigned int rn)
4883 /* Coprocessor load/store instructions:
4885 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4887 {stc/stc2} [r0, #+/-imm].
4889 ldc/ldc2 are handled identically. */
4891 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
4892 rn_val = displaced_read_reg (regs, dsc, rn);
4893 /* PC should be 4-byte aligned. */
4894 rn_val = rn_val & 0xfffffffc;
4895 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
4897 dsc->u.ldst.writeback = writeback;
4898 dsc->u.ldst.rn = rn;
4900 dsc->cleanup = &cleanup_copro_load_store;
4904 arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
4905 struct regcache *regs,
4906 struct displaced_step_closure *dsc)
4908 unsigned int rn = bits (insn, 16, 19);
4910 if (!insn_references_pc (insn, 0x000f0000ul))
4911 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
4913 if (debug_displaced)
4914 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4915 "load/store insn %.8lx\n", (unsigned long) insn);
4917 dsc->modinsn[0] = insn & 0xfff0ffff;
4919 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
4925 thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
4926 uint16_t insn2, struct regcache *regs,
4927 struct displaced_step_closure *dsc)
4929 unsigned int rn = bits (insn1, 0, 3);
4931 if (rn != ARM_PC_REGNUM)
4932 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
4933 "copro load/store", dsc);
4935 if (debug_displaced)
4936 fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
4937 "load/store insn %.4x%.4x\n", insn1, insn2);
4939 dsc->modinsn[0] = insn1 & 0xfff0;
4940 dsc->modinsn[1] = insn2;
4943 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4944 doesn't support writeback, so pass 0. */
4945 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
4950 /* Clean up branch instructions (actually perform the branch, by setting
4954 cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
4955 struct displaced_step_closure *dsc)
4957 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
4958 int branch_taken = condition_true (dsc->u.branch.cond, status);
4959 enum pc_write_style write_pc = dsc->u.branch.exchange
4960 ? BX_WRITE_PC : BRANCH_WRITE_PC;
4965 if (dsc->u.branch.link)
4967 /* The value of LR should be the next insn of current one. In order
4968 not to confuse logic hanlding later insn `bx lr', if current insn mode
4969 is Thumb, the bit 0 of LR value should be set to 1. */
4970 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
4973 next_insn_addr |= 0x1;
4975 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
4979 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
4982 /* Copy B/BL/BLX instructions with immediate destinations. */
4985 install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
4986 struct displaced_step_closure *dsc,
4987 unsigned int cond, int exchange, int link, long offset)
4989 /* Implement "BL<cond> <label>" as:
4991 Preparation: cond <- instruction condition
4992 Insn: mov r0, r0 (nop)
4993 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4995 B<cond> similar, but don't set r14 in cleanup. */
4997 dsc->u.branch.cond = cond;
4998 dsc->u.branch.link = link;
4999 dsc->u.branch.exchange = exchange;
5001 dsc->u.branch.dest = dsc->insn_addr;
5002 if (link && exchange)
5003 /* For BLX, offset is computed from the Align (PC, 4). */
5004 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
5007 dsc->u.branch.dest += 4 + offset;
5009 dsc->u.branch.dest += 8 + offset;
5011 dsc->cleanup = &cleanup_branch;
5014 arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
5015 struct regcache *regs, struct displaced_step_closure *dsc)
5017 unsigned int cond = bits (insn, 28, 31);
5018 int exchange = (cond == 0xf);
5019 int link = exchange || bit (insn, 24);
5022 if (debug_displaced)
5023 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn "
5024 "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b",
5025 (unsigned long) insn);
5027 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5028 then arrange the switch into Thumb mode. */
5029 offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1;
5031 offset = bits (insn, 0, 23) << 2;
5033 if (bit (offset, 25))
5034 offset = offset | ~0x3ffffff;
5036 dsc->modinsn[0] = ARM_NOP;
5038 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5043 thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
5044 uint16_t insn2, struct regcache *regs,
5045 struct displaced_step_closure *dsc)
5047 int link = bit (insn2, 14);
5048 int exchange = link && !bit (insn2, 12);
5051 int j1 = bit (insn2, 13);
5052 int j2 = bit (insn2, 11);
5053 int s = sbits (insn1, 10, 10);
5054 int i1 = !(j1 ^ bit (insn1, 10));
5055 int i2 = !(j2 ^ bit (insn1, 10));
5057 if (!link && !exchange) /* B */
5059 offset = (bits (insn2, 0, 10) << 1);
5060 if (bit (insn2, 12)) /* Encoding T4 */
5062 offset |= (bits (insn1, 0, 9) << 12)
5068 else /* Encoding T3 */
5070 offset |= (bits (insn1, 0, 5) << 12)
5074 cond = bits (insn1, 6, 9);
5079 offset = (bits (insn1, 0, 9) << 12);
5080 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
5081 offset |= exchange ?
5082 (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1);
5085 if (debug_displaced)
5086 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn "
5087 "%.4x %.4x with offset %.8lx\n",
5088 link ? (exchange) ? "blx" : "bl" : "b",
5089 insn1, insn2, offset);
5091 dsc->modinsn[0] = THUMB_NOP;
5093 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
5097 /* Copy B Thumb instructions. */
5099 thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn,
5100 struct displaced_step_closure *dsc)
5102 unsigned int cond = 0;
5104 unsigned short bit_12_15 = bits (insn, 12, 15);
5105 CORE_ADDR from = dsc->insn_addr;
5107 if (bit_12_15 == 0xd)
5109 /* offset = SignExtend (imm8:0, 32) */
5110 offset = sbits ((insn << 1), 0, 8);
5111 cond = bits (insn, 8, 11);
5113 else if (bit_12_15 == 0xe) /* Encoding T2 */
5115 offset = sbits ((insn << 1), 0, 11);
5119 if (debug_displaced)
5120 fprintf_unfiltered (gdb_stdlog,
5121 "displaced: copying b immediate insn %.4x "
5122 "with offset %d\n", insn, offset);
5124 dsc->u.branch.cond = cond;
5125 dsc->u.branch.link = 0;
5126 dsc->u.branch.exchange = 0;
5127 dsc->u.branch.dest = from + 4 + offset;
5129 dsc->modinsn[0] = THUMB_NOP;
5131 dsc->cleanup = &cleanup_branch;
5136 /* Copy BX/BLX with register-specified destinations. */
5139 install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
5140 struct displaced_step_closure *dsc, int link,
5141 unsigned int cond, unsigned int rm)
5143 /* Implement {BX,BLX}<cond> <reg>" as:
5145 Preparation: cond <- instruction condition
5146 Insn: mov r0, r0 (nop)
5147 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5149 Don't set r14 in cleanup for BX. */
5151 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
5153 dsc->u.branch.cond = cond;
5154 dsc->u.branch.link = link;
5156 dsc->u.branch.exchange = 1;
5158 dsc->cleanup = &cleanup_branch;
5162 arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
5163 struct regcache *regs, struct displaced_step_closure *dsc)
5165 unsigned int cond = bits (insn, 28, 31);
5168 int link = bit (insn, 5);
5169 unsigned int rm = bits (insn, 0, 3);
5171 if (debug_displaced)
5172 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx",
5173 (unsigned long) insn);
5175 dsc->modinsn[0] = ARM_NOP;
5177 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
5182 thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
5183 struct regcache *regs,
5184 struct displaced_step_closure *dsc)
5186 int link = bit (insn, 7);
5187 unsigned int rm = bits (insn, 3, 6);
5189 if (debug_displaced)
5190 fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x",
5191 (unsigned short) insn);
5193 dsc->modinsn[0] = THUMB_NOP;
5195 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
5201 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5204 cleanup_alu_imm (struct gdbarch *gdbarch,
5205 struct regcache *regs, struct displaced_step_closure *dsc)
5207 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5208 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5209 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5210 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5214 arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5215 struct displaced_step_closure *dsc)
5217 unsigned int rn = bits (insn, 16, 19);
5218 unsigned int rd = bits (insn, 12, 15);
5219 unsigned int op = bits (insn, 21, 24);
5220 int is_mov = (op == 0xd);
5221 ULONGEST rd_val, rn_val;
5223 if (!insn_references_pc (insn, 0x000ff000ul))
5224 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
5226 if (debug_displaced)
5227 fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn "
5228 "%.8lx\n", is_mov ? "move" : "ALU",
5229 (unsigned long) insn);
5231 /* Instruction is of form:
5233 <op><cond> rd, [rn,] #imm
5237 Preparation: tmp1, tmp2 <- r0, r1;
5239 Insn: <op><cond> r0, r1, #imm
5240 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5243 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5244 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5245 rn_val = displaced_read_reg (regs, dsc, rn);
5246 rd_val = displaced_read_reg (regs, dsc, rd);
5247 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5248 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5252 dsc->modinsn[0] = insn & 0xfff00fff;
5254 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
5256 dsc->cleanup = &cleanup_alu_imm;
5262 thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
5263 uint16_t insn2, struct regcache *regs,
5264 struct displaced_step_closure *dsc)
5266 unsigned int op = bits (insn1, 5, 8);
5267 unsigned int rn, rm, rd;
5268 ULONGEST rd_val, rn_val;
5270 rn = bits (insn1, 0, 3); /* Rn */
5271 rm = bits (insn2, 0, 3); /* Rm */
5272 rd = bits (insn2, 8, 11); /* Rd */
5274 /* This routine is only called for instruction MOV. */
5275 gdb_assert (op == 0x2 && rn == 0xf);
5277 if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM)
5278 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
5280 if (debug_displaced)
5281 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n",
5282 "ALU", insn1, insn2);
5284 /* Instruction is of form:
5286 <op><cond> rd, [rn,] #imm
5290 Preparation: tmp1, tmp2 <- r0, r1;
5292 Insn: <op><cond> r0, r1, #imm
5293 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5296 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5297 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5298 rn_val = displaced_read_reg (regs, dsc, rn);
5299 rd_val = displaced_read_reg (regs, dsc, rd);
5300 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5301 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5304 dsc->modinsn[0] = insn1;
5305 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
5308 dsc->cleanup = &cleanup_alu_imm;
5313 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5316 cleanup_alu_reg (struct gdbarch *gdbarch,
5317 struct regcache *regs, struct displaced_step_closure *dsc)
5322 rd_val = displaced_read_reg (regs, dsc, 0);
5324 for (i = 0; i < 3; i++)
5325 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5327 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5331 install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
5332 struct displaced_step_closure *dsc,
5333 unsigned int rd, unsigned int rn, unsigned int rm)
5335 ULONGEST rd_val, rn_val, rm_val;
5337 /* Instruction is of form:
5339 <op><cond> rd, [rn,] rm [, <shift>]
5343 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5344 r0, r1, r2 <- rd, rn, rm
5345 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5346 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5349 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5350 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5351 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5352 rd_val = displaced_read_reg (regs, dsc, rd);
5353 rn_val = displaced_read_reg (regs, dsc, rn);
5354 rm_val = displaced_read_reg (regs, dsc, rm);
5355 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5356 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5357 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5360 dsc->cleanup = &cleanup_alu_reg;
5364 arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
5365 struct displaced_step_closure *dsc)
5367 unsigned int op = bits (insn, 21, 24);
5368 int is_mov = (op == 0xd);
5370 if (!insn_references_pc (insn, 0x000ff00ful))
5371 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
5373 if (debug_displaced)
5374 fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n",
5375 is_mov ? "move" : "ALU", (unsigned long) insn);
5378 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
5380 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
5382 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
5388 thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
5389 struct regcache *regs,
5390 struct displaced_step_closure *dsc)
5394 rm = bits (insn, 3, 6);
5395 rd = (bit (insn, 7) << 3) | bits (insn, 0, 2);
5397 if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM)
5398 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
5400 if (debug_displaced)
5401 fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n",
5402 (unsigned short) insn);
5404 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
5406 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
5411 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5414 cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
5415 struct regcache *regs,
5416 struct displaced_step_closure *dsc)
5418 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
5421 for (i = 0; i < 4; i++)
5422 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
5424 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
5428 install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
5429 struct displaced_step_closure *dsc,
5430 unsigned int rd, unsigned int rn, unsigned int rm,
5434 ULONGEST rd_val, rn_val, rm_val, rs_val;
5436 /* Instruction is of form:
5438 <op><cond> rd, [rn,] rm, <shift> rs
5442 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5443 r0, r1, r2, r3 <- rd, rn, rm, rs
5444 Insn: <op><cond> r0, r1, r2, <shift> r3
5446 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5450 for (i = 0; i < 4; i++)
5451 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
5453 rd_val = displaced_read_reg (regs, dsc, rd);
5454 rn_val = displaced_read_reg (regs, dsc, rn);
5455 rm_val = displaced_read_reg (regs, dsc, rm);
5456 rs_val = displaced_read_reg (regs, dsc, rs);
5457 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
5458 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
5459 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
5460 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
5462 dsc->cleanup = &cleanup_alu_shifted_reg;
5466 arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
5467 struct regcache *regs,
5468 struct displaced_step_closure *dsc)
5470 unsigned int op = bits (insn, 21, 24);
5471 int is_mov = (op == 0xd);
5472 unsigned int rd, rn, rm, rs;
5474 if (!insn_references_pc (insn, 0x000fff0ful))
5475 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
5477 if (debug_displaced)
5478 fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn "
5479 "%.8lx\n", is_mov ? "move" : "ALU",
5480 (unsigned long) insn);
5482 rn = bits (insn, 16, 19);
5483 rm = bits (insn, 0, 3);
5484 rs = bits (insn, 8, 11);
5485 rd = bits (insn, 12, 15);
5488 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
5490 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
5492 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
5497 /* Clean up load instructions. */
5500 cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
5501 struct displaced_step_closure *dsc)
5503 ULONGEST rt_val, rt_val2 = 0, rn_val;
5505 rt_val = displaced_read_reg (regs, dsc, 0);
5506 if (dsc->u.ldst.xfersize == 8)
5507 rt_val2 = displaced_read_reg (regs, dsc, 1);
5508 rn_val = displaced_read_reg (regs, dsc, 2);
5510 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5511 if (dsc->u.ldst.xfersize > 4)
5512 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5513 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5514 if (!dsc->u.ldst.immed)
5515 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5517 /* Handle register writeback. */
5518 if (dsc->u.ldst.writeback)
5519 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5520 /* Put result in right place. */
5521 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
5522 if (dsc->u.ldst.xfersize == 8)
5523 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
5526 /* Clean up store instructions. */
5529 cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
5530 struct displaced_step_closure *dsc)
5532 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
5534 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5535 if (dsc->u.ldst.xfersize > 4)
5536 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5537 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
5538 if (!dsc->u.ldst.immed)
5539 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
5540 if (!dsc->u.ldst.restore_r4)
5541 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
5544 if (dsc->u.ldst.writeback)
5545 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
5548 /* Copy "extra" load/store instructions. These are halfword/doubleword
5549 transfers, which have a different encoding to byte/word transfers. */
5552 arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged,
5553 struct regcache *regs, struct displaced_step_closure *dsc)
5555 unsigned int op1 = bits (insn, 20, 24);
5556 unsigned int op2 = bits (insn, 5, 6);
5557 unsigned int rt = bits (insn, 12, 15);
5558 unsigned int rn = bits (insn, 16, 19);
5559 unsigned int rm = bits (insn, 0, 3);
5560 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5561 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5562 int immed = (op1 & 0x4) != 0;
5564 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
5566 if (!insn_references_pc (insn, 0x000ff00ful))
5567 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
5569 if (debug_displaced)
5570 fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store "
5571 "insn %.8lx\n", unprivileged ? "unprivileged " : "",
5572 (unsigned long) insn);
5574 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
5577 internal_error (__FILE__, __LINE__,
5578 _("copy_extra_ld_st: instruction decode error"));
5580 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5581 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5582 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5584 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5586 rt_val = displaced_read_reg (regs, dsc, rt);
5587 if (bytesize[opcode] == 8)
5588 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
5589 rn_val = displaced_read_reg (regs, dsc, rn);
5591 rm_val = displaced_read_reg (regs, dsc, rm);
5593 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5594 if (bytesize[opcode] == 8)
5595 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
5596 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5598 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5601 dsc->u.ldst.xfersize = bytesize[opcode];
5602 dsc->u.ldst.rn = rn;
5603 dsc->u.ldst.immed = immed;
5604 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
5605 dsc->u.ldst.restore_r4 = 0;
5608 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5610 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5611 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5613 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5615 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5616 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5618 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
5623 /* Copy byte/half word/word loads and stores. */
5626 install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
5627 struct displaced_step_closure *dsc, int load,
5628 int immed, int writeback, int size, int usermode,
5629 int rt, int rm, int rn)
5631 ULONGEST rt_val, rn_val, rm_val = 0;
5633 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5634 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5636 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5638 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
5640 rt_val = displaced_read_reg (regs, dsc, rt);
5641 rn_val = displaced_read_reg (regs, dsc, rn);
5643 rm_val = displaced_read_reg (regs, dsc, rm);
5645 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
5646 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
5648 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
5650 dsc->u.ldst.xfersize = size;
5651 dsc->u.ldst.rn = rn;
5652 dsc->u.ldst.immed = immed;
5653 dsc->u.ldst.writeback = writeback;
5655 /* To write PC we can do:
5657 Before this sequence of instructions:
5658 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5659 r2 is the Rn value got from dispalced_read_reg.
5661 Insn1: push {pc} Write address of STR instruction + offset on stack
5662 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5663 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5664 = addr(Insn1) + offset - addr(Insn3) - 8
5666 Insn4: add r4, r4, #8 r4 = offset - 8
5667 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5669 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5671 Otherwise we don't know what value to write for PC, since the offset is
5672 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5673 of this can be found in Section "Saving from r15" in
5674 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5676 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5681 thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
5682 uint16_t insn2, struct regcache *regs,
5683 struct displaced_step_closure *dsc, int size)
5685 unsigned int u_bit = bit (insn1, 7);
5686 unsigned int rt = bits (insn2, 12, 15);
5687 int imm12 = bits (insn2, 0, 11);
5690 if (debug_displaced)
5691 fprintf_unfiltered (gdb_stdlog,
5692 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5693 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
5699 /* Rewrite instruction LDR Rt imm12 into:
5701 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5705 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5708 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5709 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
5710 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
5712 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5714 pc_val = pc_val & 0xfffffffc;
5716 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
5717 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
5721 dsc->u.ldst.xfersize = size;
5722 dsc->u.ldst.immed = 0;
5723 dsc->u.ldst.writeback = 0;
5724 dsc->u.ldst.restore_r4 = 0;
5726 /* LDR R0, R2, R3 */
5727 dsc->modinsn[0] = 0xf852;
5728 dsc->modinsn[1] = 0x3;
5731 dsc->cleanup = &cleanup_load;
5737 thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
5738 uint16_t insn2, struct regcache *regs,
5739 struct displaced_step_closure *dsc,
5740 int writeback, int immed)
5742 unsigned int rt = bits (insn2, 12, 15);
5743 unsigned int rn = bits (insn1, 0, 3);
5744 unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */
5745 /* In LDR (register), there is also a register Rm, which is not allowed to
5746 be PC, so we don't have to check it. */
5748 if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM)
5749 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load",
5752 if (debug_displaced)
5753 fprintf_unfiltered (gdb_stdlog,
5754 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5755 rt, rn, insn1, insn2);
5757 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
5760 dsc->u.ldst.restore_r4 = 0;
5763 /* ldr[b]<cond> rt, [rn, #imm], etc.
5765 ldr[b]<cond> r0, [r2, #imm]. */
5767 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5768 dsc->modinsn[1] = insn2 & 0x0fff;
5771 /* ldr[b]<cond> rt, [rn, rm], etc.
5773 ldr[b]<cond> r0, [r2, r3]. */
5775 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
5776 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
5786 arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
5787 struct regcache *regs,
5788 struct displaced_step_closure *dsc,
5789 int load, int size, int usermode)
5791 int immed = !bit (insn, 25);
5792 int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0);
5793 unsigned int rt = bits (insn, 12, 15);
5794 unsigned int rn = bits (insn, 16, 19);
5795 unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */
5797 if (!insn_references_pc (insn, 0x000ff00ful))
5798 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
5800 if (debug_displaced)
5801 fprintf_unfiltered (gdb_stdlog,
5802 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5803 load ? (size == 1 ? "ldrb" : "ldr")
5804 : (size == 1 ? "strb" : "str"), usermode ? "t" : "",
5806 (unsigned long) insn);
5808 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
5809 usermode, rt, rm, rn);
5811 if (load || rt != ARM_PC_REGNUM)
5813 dsc->u.ldst.restore_r4 = 0;
5816 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5818 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5819 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
5821 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5823 {ldr,str}[b]<cond> r0, [r2, r3]. */
5824 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
5828 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5829 dsc->u.ldst.restore_r4 = 1;
5830 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
5831 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
5832 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
5833 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
5834 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
5838 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
5840 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
5845 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
5850 /* Cleanup LDM instructions with fully-populated register list. This is an
5851 unfortunate corner case: it's impossible to implement correctly by modifying
5852 the instruction. The issue is as follows: we have an instruction,
5856 which we must rewrite to avoid loading PC. A possible solution would be to
5857 do the load in two halves, something like (with suitable cleanup
5861 ldm[id][ab] r8!, {r0-r7}
5863 ldm[id][ab] r8, {r7-r14}
5866 but at present there's no suitable place for <temp>, since the scratch space
5867 is overwritten before the cleanup routine is called. For now, we simply
5868 emulate the instruction. */
5871 cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
5872 struct displaced_step_closure *dsc)
5874 int inc = dsc->u.block.increment;
5875 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
5876 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
5877 uint32_t regmask = dsc->u.block.regmask;
5878 int regno = inc ? 0 : 15;
5879 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
5880 int exception_return = dsc->u.block.load && dsc->u.block.user
5881 && (regmask & 0x8000) != 0;
5882 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5883 int do_transfer = condition_true (dsc->u.block.cond, status);
5884 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5889 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5890 sensible we can do here. Complain loudly. */
5891 if (exception_return)
5892 error (_("Cannot single-step exception return"));
5894 /* We don't handle any stores here for now. */
5895 gdb_assert (dsc->u.block.load != 0);
5897 if (debug_displaced)
5898 fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: "
5899 "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm",
5900 dsc->u.block.increment ? "inc" : "dec",
5901 dsc->u.block.before ? "before" : "after");
5908 while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
5911 while (regno >= 0 && (regmask & (1 << regno)) == 0)
5914 xfer_addr += bump_before;
5916 memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order);
5917 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
5919 xfer_addr += bump_after;
5921 regmask &= ~(1 << regno);
5924 if (dsc->u.block.writeback)
5925 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
5929 /* Clean up an STM which included the PC in the register list. */
5932 cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
5933 struct displaced_step_closure *dsc)
5935 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5936 int store_executed = condition_true (dsc->u.block.cond, status);
5937 CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask);
5938 CORE_ADDR stm_insn_addr;
5941 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5943 /* If condition code fails, there's nothing else to do. */
5944 if (!store_executed)
5947 if (dsc->u.block.increment)
5949 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
5951 if (dsc->u.block.before)
5956 pc_stored_at = dsc->u.block.xfer_addr;
5958 if (dsc->u.block.before)
5962 pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order);
5963 stm_insn_addr = dsc->scratch_base;
5964 offset = pc_val - stm_insn_addr;
5966 if (debug_displaced)
5967 fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for "
5968 "STM instruction\n", offset);
5970 /* Rewrite the stored PC to the proper value for the non-displaced original
5972 write_memory_unsigned_integer (pc_stored_at, 4, byte_order,
5973 dsc->insn_addr + offset);
5976 /* Clean up an LDM which includes the PC in the register list. We clumped all
5977 the registers in the transferred list into a contiguous range r0...rX (to
5978 avoid loading PC directly and losing control of the debugged program), so we
5979 must undo that here. */
5982 cleanup_block_load_pc (struct gdbarch *gdbarch,
5983 struct regcache *regs,
5984 struct displaced_step_closure *dsc)
5986 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5987 int load_executed = condition_true (dsc->u.block.cond, status);
5988 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
5989 unsigned int regs_loaded = bitcount (mask);
5990 unsigned int num_to_shuffle = regs_loaded, clobbered;
5992 /* The method employed here will fail if the register list is fully populated
5993 (we need to avoid loading PC directly). */
5994 gdb_assert (num_to_shuffle < 16);
5999 clobbered = (1 << num_to_shuffle) - 1;
6001 while (num_to_shuffle > 0)
6003 if ((mask & (1 << write_reg)) != 0)
6005 unsigned int read_reg = num_to_shuffle - 1;
6007 if (read_reg != write_reg)
6009 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6010 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
6011 if (debug_displaced)
6012 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move "
6013 "loaded register r%d to r%d\n"), read_reg,
6016 else if (debug_displaced)
6017 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register "
6018 "r%d already in the right place\n"),
6021 clobbered &= ~(1 << write_reg);
6029 /* Restore any registers we scribbled over. */
6030 for (write_reg = 0; clobbered != 0; write_reg++)
6032 if ((clobbered & (1 << write_reg)) != 0)
6034 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
6036 if (debug_displaced)
6037 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored "
6038 "clobbered register r%d\n"), write_reg);
6039 clobbered &= ~(1 << write_reg);
6043 /* Perform register writeback manually. */
6044 if (dsc->u.block.writeback)
6046 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
6048 if (dsc->u.block.increment)
6049 new_rn_val += regs_loaded * 4;
6051 new_rn_val -= regs_loaded * 4;
6053 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
6058 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6059 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6062 arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
6063 struct regcache *regs,
6064 struct displaced_step_closure *dsc)
6066 int load = bit (insn, 20);
6067 int user = bit (insn, 22);
6068 int increment = bit (insn, 23);
6069 int before = bit (insn, 24);
6070 int writeback = bit (insn, 21);
6071 int rn = bits (insn, 16, 19);
6073 /* Block transfers which don't mention PC can be run directly
6075 if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0)
6076 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
6078 if (rn == ARM_PC_REGNUM)
6080 warning (_("displaced: Unpredictable LDM or STM with "
6081 "base register r15"));
6082 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
6085 if (debug_displaced)
6086 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6087 "%.8lx\n", (unsigned long) insn);
6089 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6090 dsc->u.block.rn = rn;
6092 dsc->u.block.load = load;
6093 dsc->u.block.user = user;
6094 dsc->u.block.increment = increment;
6095 dsc->u.block.before = before;
6096 dsc->u.block.writeback = writeback;
6097 dsc->u.block.cond = bits (insn, 28, 31);
6099 dsc->u.block.regmask = insn & 0xffff;
6103 if ((insn & 0xffff) == 0xffff)
6105 /* LDM with a fully-populated register list. This case is
6106 particularly tricky. Implement for now by fully emulating the
6107 instruction (which might not behave perfectly in all cases, but
6108 these instructions should be rare enough for that not to matter
6110 dsc->modinsn[0] = ARM_NOP;
6112 dsc->cleanup = &cleanup_block_load_all;
6116 /* LDM of a list of registers which includes PC. Implement by
6117 rewriting the list of registers to be transferred into a
6118 contiguous chunk r0...rX before doing the transfer, then shuffling
6119 registers into the correct places in the cleanup routine. */
6120 unsigned int regmask = insn & 0xffff;
6121 unsigned int num_in_list = bitcount (regmask), new_regmask;
6124 for (i = 0; i < num_in_list; i++)
6125 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6127 /* Writeback makes things complicated. We need to avoid clobbering
6128 the base register with one of the registers in our modified
6129 register list, but just using a different register can't work in
6132 ldm r14!, {r0-r13,pc}
6134 which would need to be rewritten as:
6138 but that can't work, because there's no free register for N.
6140 Solve this by turning off the writeback bit, and emulating
6141 writeback manually in the cleanup routine. */
6146 new_regmask = (1 << num_in_list) - 1;
6148 if (debug_displaced)
6149 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6150 "{..., pc}: original reg list %.4x, modified "
6151 "list %.4x\n"), rn, writeback ? "!" : "",
6152 (int) insn & 0xffff, new_regmask);
6154 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
6156 dsc->cleanup = &cleanup_block_load_pc;
6161 /* STM of a list of registers which includes PC. Run the instruction
6162 as-is, but out of line: this will store the wrong value for the PC,
6163 so we must manually fix up the memory in the cleanup routine.
6164 Doing things this way has the advantage that we can auto-detect
6165 the offset of the PC write (which is architecture-dependent) in
6166 the cleanup routine. */
6167 dsc->modinsn[0] = insn;
6169 dsc->cleanup = &cleanup_block_store_pc;
6176 thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6177 struct regcache *regs,
6178 struct displaced_step_closure *dsc)
6180 int rn = bits (insn1, 0, 3);
6181 int load = bit (insn1, 4);
6182 int writeback = bit (insn1, 5);
6184 /* Block transfers which don't mention PC can be run directly
6186 if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0)
6187 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
6189 if (rn == ARM_PC_REGNUM)
6191 warning (_("displaced: Unpredictable LDM or STM with "
6192 "base register r15"));
6193 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6194 "unpredictable ldm/stm", dsc);
6197 if (debug_displaced)
6198 fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn "
6199 "%.4x%.4x\n", insn1, insn2);
6201 /* Clear bit 13, since it should be always zero. */
6202 dsc->u.block.regmask = (insn2 & 0xdfff);
6203 dsc->u.block.rn = rn;
6205 dsc->u.block.load = load;
6206 dsc->u.block.user = 0;
6207 dsc->u.block.increment = bit (insn1, 7);
6208 dsc->u.block.before = bit (insn1, 8);
6209 dsc->u.block.writeback = writeback;
6210 dsc->u.block.cond = INST_AL;
6211 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
6215 if (dsc->u.block.regmask == 0xffff)
6217 /* This branch is impossible to happen. */
6222 unsigned int regmask = dsc->u.block.regmask;
6223 unsigned int num_in_list = bitcount (regmask), new_regmask;
6226 for (i = 0; i < num_in_list; i++)
6227 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6232 new_regmask = (1 << num_in_list) - 1;
6234 if (debug_displaced)
6235 fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, "
6236 "{..., pc}: original reg list %.4x, modified "
6237 "list %.4x\n"), rn, writeback ? "!" : "",
6238 (int) dsc->u.block.regmask, new_regmask);
6240 dsc->modinsn[0] = insn1;
6241 dsc->modinsn[1] = (new_regmask & 0xffff);
6244 dsc->cleanup = &cleanup_block_load_pc;
6249 dsc->modinsn[0] = insn1;
6250 dsc->modinsn[1] = insn2;
6252 dsc->cleanup = &cleanup_block_store_pc;
6257 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6258 This is used to avoid a dependency on BFD's bfd_endian enum. */
6261 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len,
6264 return read_memory_unsigned_integer (memaddr, len,
6265 (enum bfd_endian) byte_order);
6268 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6271 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
6274 return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val);
6277 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6280 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self)
6285 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6288 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self)
6290 return arm_is_thumb (self->regcache);
6293 /* single_step() is called just before we want to resume the inferior,
6294 if we want to single-step it but there is no hardware or kernel
6295 single-step support. We find the target of the coming instructions
6296 and breakpoint them. */
6298 std::vector<CORE_ADDR>
6299 arm_software_single_step (struct regcache *regcache)
6301 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6302 struct arm_get_next_pcs next_pcs_ctx;
6304 arm_get_next_pcs_ctor (&next_pcs_ctx,
6305 &arm_get_next_pcs_ops,
6306 gdbarch_byte_order (gdbarch),
6307 gdbarch_byte_order_for_code (gdbarch),
6311 std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
6313 for (CORE_ADDR &pc_ref : next_pcs)
6314 pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
6319 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6320 for Linux, where some SVC instructions must be treated specially. */
6323 cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
6324 struct displaced_step_closure *dsc)
6326 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
6328 if (debug_displaced)
6329 fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at "
6330 "%.8lx\n", (unsigned long) resume_addr);
6332 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
6336 /* Common copy routine for svc instruciton. */
6339 install_svc (struct gdbarch *gdbarch, struct regcache *regs,
6340 struct displaced_step_closure *dsc)
6342 /* Preparation: none.
6343 Insn: unmodified svc.
6344 Cleanup: pc <- insn_addr + insn_size. */
6346 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6348 dsc->wrote_to_pc = 1;
6350 /* Allow OS-specific code to override SVC handling. */
6351 if (dsc->u.svc.copy_svc_os)
6352 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
6355 dsc->cleanup = &cleanup_svc;
6361 arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
6362 struct regcache *regs, struct displaced_step_closure *dsc)
6365 if (debug_displaced)
6366 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n",
6367 (unsigned long) insn);
6369 dsc->modinsn[0] = insn;
6371 return install_svc (gdbarch, regs, dsc);
6375 thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
6376 struct regcache *regs, struct displaced_step_closure *dsc)
6379 if (debug_displaced)
6380 fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n",
6383 dsc->modinsn[0] = insn;
6385 return install_svc (gdbarch, regs, dsc);
6388 /* Copy undefined instructions. */
6391 arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
6392 struct displaced_step_closure *dsc)
6394 if (debug_displaced)
6395 fprintf_unfiltered (gdb_stdlog,
6396 "displaced: copying undefined insn %.8lx\n",
6397 (unsigned long) insn);
6399 dsc->modinsn[0] = insn;
6405 thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
6406 struct displaced_step_closure *dsc)
6409 if (debug_displaced)
6410 fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn "
6411 "%.4x %.4x\n", (unsigned short) insn1,
6412 (unsigned short) insn2);
6414 dsc->modinsn[0] = insn1;
6415 dsc->modinsn[1] = insn2;
6421 /* Copy unpredictable instructions. */
6424 arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
6425 struct displaced_step_closure *dsc)
6427 if (debug_displaced)
6428 fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
6429 "%.8lx\n", (unsigned long) insn);
6431 dsc->modinsn[0] = insn;
6436 /* The decode_* functions are instruction decoding helpers. They mostly follow
6437 the presentation in the ARM ARM. */
6440 arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
6441 struct regcache *regs,
6442 struct displaced_step_closure *dsc)
6444 unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
6445 unsigned int rn = bits (insn, 16, 19);
6447 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
6448 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
6449 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
6450 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
6451 else if ((op1 & 0x60) == 0x20)
6452 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
6453 else if ((op1 & 0x71) == 0x40)
6454 return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store",
6456 else if ((op1 & 0x77) == 0x41)
6457 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6458 else if ((op1 & 0x77) == 0x45)
6459 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
6460 else if ((op1 & 0x77) == 0x51)
6463 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6465 return arm_copy_unpred (gdbarch, insn, dsc);
6467 else if ((op1 & 0x77) == 0x55)
6468 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
6469 else if (op1 == 0x57)
6472 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
6473 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
6474 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
6475 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
6476 default: return arm_copy_unpred (gdbarch, insn, dsc);
6478 else if ((op1 & 0x63) == 0x43)
6479 return arm_copy_unpred (gdbarch, insn, dsc);
6480 else if ((op2 & 0x1) == 0x0)
6481 switch (op1 & ~0x80)
6484 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
6486 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
6487 case 0x71: case 0x75:
6489 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
6490 case 0x63: case 0x67: case 0x73: case 0x77:
6491 return arm_copy_unpred (gdbarch, insn, dsc);
6493 return arm_copy_undef (gdbarch, insn, dsc);
6496 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
6500 arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
6501 struct regcache *regs,
6502 struct displaced_step_closure *dsc)
6504 if (bit (insn, 27) == 0)
6505 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
6506 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6507 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
6510 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
6513 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
6515 case 0x4: case 0x5: case 0x6: case 0x7:
6516 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6519 switch ((insn & 0xe00000) >> 21)
6521 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6523 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6526 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6529 return arm_copy_undef (gdbarch, insn, dsc);
6534 int rn_f = (bits (insn, 16, 19) == 0xf);
6535 switch ((insn & 0xe00000) >> 21)
6538 /* ldc/ldc2 imm (undefined for rn == pc). */
6539 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
6540 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6543 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6545 case 0x4: case 0x5: case 0x6: case 0x7:
6546 /* ldc/ldc2 lit (undefined for rn != pc). */
6547 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
6548 : arm_copy_undef (gdbarch, insn, dsc);
6551 return arm_copy_undef (gdbarch, insn, dsc);
6556 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
6559 if (bits (insn, 16, 19) == 0xf)
6561 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6563 return arm_copy_undef (gdbarch, insn, dsc);
6567 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6569 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6573 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6575 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6578 return arm_copy_undef (gdbarch, insn, dsc);
6582 /* Decode miscellaneous instructions in dp/misc encoding space. */
6585 arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
6586 struct regcache *regs,
6587 struct displaced_step_closure *dsc)
6589 unsigned int op2 = bits (insn, 4, 6);
6590 unsigned int op = bits (insn, 21, 22);
6595 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
6598 if (op == 0x1) /* bx. */
6599 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
6601 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
6603 return arm_copy_undef (gdbarch, insn, dsc);
6607 /* Not really supported. */
6608 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
6610 return arm_copy_undef (gdbarch, insn, dsc);
6614 return arm_copy_bx_blx_reg (gdbarch, insn,
6615 regs, dsc); /* blx register. */
6617 return arm_copy_undef (gdbarch, insn, dsc);
6620 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
6624 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
6626 /* Not really supported. */
6627 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
6630 return arm_copy_undef (gdbarch, insn, dsc);
6635 arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
6636 struct regcache *regs,
6637 struct displaced_step_closure *dsc)
6640 switch (bits (insn, 20, 24))
6643 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
6646 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
6648 case 0x12: case 0x16:
6649 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
6652 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
6656 uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7);
6658 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
6659 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
6660 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
6661 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
6662 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
6663 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
6664 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
6665 return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc);
6666 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
6667 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
6668 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
6669 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
6670 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
6671 /* 2nd arg means "unprivileged". */
6672 return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs,
6676 /* Should be unreachable. */
6681 arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
6682 struct regcache *regs,
6683 struct displaced_step_closure *dsc)
6685 int a = bit (insn, 25), b = bit (insn, 4);
6686 uint32_t op1 = bits (insn, 20, 24);
6688 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
6689 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
6690 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
6691 else if ((!a && (op1 & 0x17) == 0x02)
6692 || (a && (op1 & 0x17) == 0x02 && !b))
6693 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
6694 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
6695 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
6696 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
6697 else if ((!a && (op1 & 0x17) == 0x03)
6698 || (a && (op1 & 0x17) == 0x03 && !b))
6699 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
6700 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
6701 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
6702 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
6703 else if ((!a && (op1 & 0x17) == 0x06)
6704 || (a && (op1 & 0x17) == 0x06 && !b))
6705 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
6706 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
6707 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
6708 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
6709 else if ((!a && (op1 & 0x17) == 0x07)
6710 || (a && (op1 & 0x17) == 0x07 && !b))
6711 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
6713 /* Should be unreachable. */
6718 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
6719 struct displaced_step_closure *dsc)
6721 switch (bits (insn, 20, 24))
6723 case 0x00: case 0x01: case 0x02: case 0x03:
6724 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
6726 case 0x04: case 0x05: case 0x06: case 0x07:
6727 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
6729 case 0x08: case 0x09: case 0x0a: case 0x0b:
6730 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6731 return arm_copy_unmodified (gdbarch, insn,
6732 "decode/pack/unpack/saturate/reverse", dsc);
6735 if (bits (insn, 5, 7) == 0) /* op2. */
6737 if (bits (insn, 12, 15) == 0xf)
6738 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
6740 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
6743 return arm_copy_undef (gdbarch, insn, dsc);
6745 case 0x1a: case 0x1b:
6746 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6747 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
6749 return arm_copy_undef (gdbarch, insn, dsc);
6751 case 0x1c: case 0x1d:
6752 if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */
6754 if (bits (insn, 0, 3) == 0xf)
6755 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
6757 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
6760 return arm_copy_undef (gdbarch, insn, dsc);
6762 case 0x1e: case 0x1f:
6763 if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */
6764 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
6766 return arm_copy_undef (gdbarch, insn, dsc);
6769 /* Should be unreachable. */
6774 arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn,
6775 struct regcache *regs,
6776 struct displaced_step_closure *dsc)
6779 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
6781 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
6785 arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
6786 struct regcache *regs,
6787 struct displaced_step_closure *dsc)
6789 unsigned int opcode = bits (insn, 20, 24);
6793 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6794 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
6796 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6797 case 0x12: case 0x16:
6798 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
6800 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6801 case 0x13: case 0x17:
6802 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
6804 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6805 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6806 /* Note: no writeback for these instructions. Bit 25 will always be
6807 zero though (via caller), so the following works OK. */
6808 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6811 /* Should be unreachable. */
6815 /* Decode shifted register instructions. */
6818 thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
6819 uint16_t insn2, struct regcache *regs,
6820 struct displaced_step_closure *dsc)
6822 /* PC is only allowed to be used in instruction MOV. */
6824 unsigned int op = bits (insn1, 5, 8);
6825 unsigned int rn = bits (insn1, 0, 3);
6827 if (op == 0x2 && rn == 0xf) /* MOV */
6828 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
6830 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6831 "dp (shift reg)", dsc);
6835 /* Decode extension register load/store. Exactly the same as
6836 arm_decode_ext_reg_ld_st. */
6839 thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
6840 uint16_t insn2, struct regcache *regs,
6841 struct displaced_step_closure *dsc)
6843 unsigned int opcode = bits (insn1, 4, 8);
6847 case 0x04: case 0x05:
6848 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6849 "vfp/neon vmov", dsc);
6851 case 0x08: case 0x0c: /* 01x00 */
6852 case 0x0a: case 0x0e: /* 01x10 */
6853 case 0x12: case 0x16: /* 10x10 */
6854 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6855 "vfp/neon vstm/vpush", dsc);
6857 case 0x09: case 0x0d: /* 01x01 */
6858 case 0x0b: case 0x0f: /* 01x11 */
6859 case 0x13: case 0x17: /* 10x11 */
6860 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6861 "vfp/neon vldm/vpop", dsc);
6863 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6864 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6866 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6867 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
6870 /* Should be unreachable. */
6875 arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn,
6876 struct regcache *regs, struct displaced_step_closure *dsc)
6878 unsigned int op1 = bits (insn, 20, 25);
6879 int op = bit (insn, 4);
6880 unsigned int coproc = bits (insn, 8, 11);
6882 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
6883 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
6884 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
6885 && (coproc & 0xe) != 0xa)
6887 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6888 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
6889 && (coproc & 0xe) != 0xa)
6890 /* ldc/ldc2 imm/lit. */
6891 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
6892 else if ((op1 & 0x3e) == 0x00)
6893 return arm_copy_undef (gdbarch, insn, dsc);
6894 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
6895 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
6896 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
6897 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
6898 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
6899 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
6900 else if ((op1 & 0x30) == 0x20 && !op)
6902 if ((coproc & 0xe) == 0xa)
6903 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
6905 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
6907 else if ((op1 & 0x30) == 0x20 && op)
6908 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
6909 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
6910 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
6911 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
6912 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
6913 else if ((op1 & 0x30) == 0x30)
6914 return arm_copy_svc (gdbarch, insn, regs, dsc);
6916 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
6920 thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
6921 uint16_t insn2, struct regcache *regs,
6922 struct displaced_step_closure *dsc)
6924 unsigned int coproc = bits (insn2, 8, 11);
6925 unsigned int bit_5_8 = bits (insn1, 5, 8);
6926 unsigned int bit_9 = bit (insn1, 9);
6927 unsigned int bit_4 = bit (insn1, 4);
6932 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6933 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6935 else if (bit_5_8 == 0) /* UNDEFINED. */
6936 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
6939 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6940 if ((coproc & 0xe) == 0xa)
6941 return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs,
6943 else /* coproc is not 101x. */
6945 if (bit_4 == 0) /* STC/STC2. */
6946 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
6948 else /* LDC/LDC2 {literal, immeidate}. */
6949 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2,
6955 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
6961 install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
6962 struct displaced_step_closure *dsc, int rd)
6968 Preparation: Rd <- PC
6974 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6975 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
6979 thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
6980 struct displaced_step_closure *dsc,
6981 int rd, unsigned int imm)
6984 /* Encoding T2: ADDS Rd, #imm */
6985 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
6987 install_pc_relative (gdbarch, regs, dsc, rd);
6993 thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
6994 struct regcache *regs,
6995 struct displaced_step_closure *dsc)
6997 unsigned int rd = bits (insn, 8, 10);
6998 unsigned int imm8 = bits (insn, 0, 7);
7000 if (debug_displaced)
7001 fprintf_unfiltered (gdb_stdlog,
7002 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7005 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7009 thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
7010 uint16_t insn2, struct regcache *regs,
7011 struct displaced_step_closure *dsc)
7013 unsigned int rd = bits (insn2, 8, 11);
7014 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7015 extract raw immediate encoding rather than computing immediate. When
7016 generating ADD or SUB instruction, we can simply perform OR operation to
7017 set immediate into ADD. */
7018 unsigned int imm_3_8 = insn2 & 0x70ff;
7019 unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */
7021 if (debug_displaced)
7022 fprintf_unfiltered (gdb_stdlog,
7023 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7024 rd, imm_i, imm_3_8, insn1, insn2);
7026 if (bit (insn1, 7)) /* Encoding T2 */
7028 /* Encoding T3: SUB Rd, Rd, #imm */
7029 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
7030 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7032 else /* Encoding T3 */
7034 /* Encoding T3: ADD Rd, Rd, #imm */
7035 dsc->modinsn[0] = (0xf100 | rd | imm_i);
7036 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
7040 install_pc_relative (gdbarch, regs, dsc, rd);
7046 thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1,
7047 struct regcache *regs,
7048 struct displaced_step_closure *dsc)
7050 unsigned int rt = bits (insn1, 8, 10);
7052 int imm8 = (bits (insn1, 0, 7) << 2);
7058 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7060 Insn: LDR R0, [R2, R3];
7061 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7063 if (debug_displaced)
7064 fprintf_unfiltered (gdb_stdlog,
7065 "displaced: copying thumb ldr r%d [pc #%d]\n"
7068 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
7069 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
7070 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
7071 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7072 /* The assembler calculates the required value of the offset from the
7073 Align(PC,4) value of this instruction to the label. */
7074 pc = pc & 0xfffffffc;
7076 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
7077 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
7080 dsc->u.ldst.xfersize = 4;
7082 dsc->u.ldst.immed = 0;
7083 dsc->u.ldst.writeback = 0;
7084 dsc->u.ldst.restore_r4 = 0;
7086 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7088 dsc->cleanup = &cleanup_load;
7093 /* Copy Thumb cbnz/cbz insruction. */
7096 thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
7097 struct regcache *regs,
7098 struct displaced_step_closure *dsc)
7100 int non_zero = bit (insn1, 11);
7101 unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
7102 CORE_ADDR from = dsc->insn_addr;
7103 int rn = bits (insn1, 0, 2);
7104 int rn_val = displaced_read_reg (regs, dsc, rn);
7106 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
7107 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7108 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7109 condition is false, let it be, cleanup_branch will do nothing. */
7110 if (dsc->u.branch.cond)
7112 dsc->u.branch.cond = INST_AL;
7113 dsc->u.branch.dest = from + 4 + imm5;
7116 dsc->u.branch.dest = from + 2;
7118 dsc->u.branch.link = 0;
7119 dsc->u.branch.exchange = 0;
7121 if (debug_displaced)
7122 fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]"
7123 " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz",
7124 rn, rn_val, insn1, dsc->u.branch.dest);
7126 dsc->modinsn[0] = THUMB_NOP;
7128 dsc->cleanup = &cleanup_branch;
7132 /* Copy Table Branch Byte/Halfword */
7134 thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
7135 uint16_t insn2, struct regcache *regs,
7136 struct displaced_step_closure *dsc)
7138 ULONGEST rn_val, rm_val;
7139 int is_tbh = bit (insn2, 4);
7140 CORE_ADDR halfwords = 0;
7141 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7143 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
7144 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
7150 target_read_memory (rn_val + 2 * rm_val, buf, 2);
7151 halfwords = extract_unsigned_integer (buf, 2, byte_order);
7157 target_read_memory (rn_val + rm_val, buf, 1);
7158 halfwords = extract_unsigned_integer (buf, 1, byte_order);
7161 if (debug_displaced)
7162 fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x"
7163 " offset 0x%x\n", is_tbh ? "tbh" : "tbb",
7164 (unsigned int) rn_val, (unsigned int) rm_val,
7165 (unsigned int) halfwords);
7167 dsc->u.branch.cond = INST_AL;
7168 dsc->u.branch.link = 0;
7169 dsc->u.branch.exchange = 0;
7170 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
7172 dsc->cleanup = &cleanup_branch;
7178 cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
7179 struct displaced_step_closure *dsc)
7182 int val = displaced_read_reg (regs, dsc, 7);
7183 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
7186 val = displaced_read_reg (regs, dsc, 8);
7187 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
7190 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
7195 thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1,
7196 struct regcache *regs,
7197 struct displaced_step_closure *dsc)
7199 dsc->u.block.regmask = insn1 & 0x00ff;
7201 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7204 (1) register list is full, that is, r0-r7 are used.
7205 Prepare: tmp[0] <- r8
7207 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7208 MOV r8, r7; Move value of r7 to r8;
7209 POP {r7}; Store PC value into r7.
7211 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7213 (2) register list is not full, supposing there are N registers in
7214 register list (except PC, 0 <= N <= 7).
7215 Prepare: for each i, 0 - N, tmp[i] <- ri.
7217 POP {r0, r1, ...., rN};
7219 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7220 from tmp[] properly.
7222 if (debug_displaced)
7223 fprintf_unfiltered (gdb_stdlog,
7224 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7225 dsc->u.block.regmask, insn1);
7227 if (dsc->u.block.regmask == 0xff)
7229 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
7231 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
7232 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
7233 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
7236 dsc->cleanup = &cleanup_pop_pc_16bit_all;
7240 unsigned int num_in_list = bitcount (dsc->u.block.regmask);
7242 unsigned int new_regmask;
7244 for (i = 0; i < num_in_list + 1; i++)
7245 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7247 new_regmask = (1 << (num_in_list + 1)) - 1;
7249 if (debug_displaced)
7250 fprintf_unfiltered (gdb_stdlog, _("displaced: POP "
7251 "{..., pc}: original reg list %.4x,"
7252 " modified list %.4x\n"),
7253 (int) dsc->u.block.regmask, new_regmask);
7255 dsc->u.block.regmask |= 0x8000;
7256 dsc->u.block.writeback = 0;
7257 dsc->u.block.cond = INST_AL;
7259 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
7261 dsc->cleanup = &cleanup_block_load_pc;
7268 thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7269 struct regcache *regs,
7270 struct displaced_step_closure *dsc)
7272 unsigned short op_bit_12_15 = bits (insn1, 12, 15);
7273 unsigned short op_bit_10_11 = bits (insn1, 10, 11);
7276 /* 16-bit thumb instructions. */
7277 switch (op_bit_12_15)
7279 /* Shift (imme), add, subtract, move and compare. */
7280 case 0: case 1: case 2: case 3:
7281 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7282 "shift/add/sub/mov/cmp",
7286 switch (op_bit_10_11)
7288 case 0: /* Data-processing */
7289 err = thumb_copy_unmodified_16bit (gdbarch, insn1,
7293 case 1: /* Special data instructions and branch and exchange. */
7295 unsigned short op = bits (insn1, 7, 9);
7296 if (op == 6 || op == 7) /* BX or BLX */
7297 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
7298 else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7299 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
7301 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data",
7305 default: /* LDR (literal) */
7306 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
7309 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7310 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
7313 if (op_bit_10_11 < 2) /* Generate PC-relative address */
7314 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
7315 else /* Generate SP-relative address */
7316 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
7318 case 11: /* Misc 16-bit instructions */
7320 switch (bits (insn1, 8, 11))
7322 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7323 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
7325 case 12: case 13: /* POP */
7326 if (bit (insn1, 8)) /* PC is in register list. */
7327 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
7329 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
7331 case 15: /* If-Then, and hints */
7332 if (bits (insn1, 0, 3))
7333 /* If-Then makes up to four following instructions conditional.
7334 IT instruction itself is not conditional, so handle it as a
7335 common unmodified instruction. */
7336 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then",
7339 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
7342 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
7347 if (op_bit_10_11 < 2) /* Store multiple registers */
7348 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
7349 else /* Load multiple registers */
7350 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
7352 case 13: /* Conditional branch and supervisor call */
7353 if (bits (insn1, 9, 11) != 7) /* conditional branch */
7354 err = thumb_copy_b (gdbarch, insn1, dsc);
7356 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
7358 case 14: /* Unconditional branch */
7359 err = thumb_copy_b (gdbarch, insn1, dsc);
7366 internal_error (__FILE__, __LINE__,
7367 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7371 decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
7372 uint16_t insn1, uint16_t insn2,
7373 struct regcache *regs,
7374 struct displaced_step_closure *dsc)
7376 int rt = bits (insn2, 12, 15);
7377 int rn = bits (insn1, 0, 3);
7378 int op1 = bits (insn1, 7, 8);
7380 switch (bits (insn1, 5, 6))
7382 case 0: /* Load byte and memory hints */
7383 if (rt == 0xf) /* PLD/PLI */
7386 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7387 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
7389 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7394 if (rn == 0xf) /* LDRB/LDRSB (literal) */
7395 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7398 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7399 "ldrb{reg, immediate}/ldrbt",
7404 case 1: /* Load halfword and memory hints. */
7405 if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */
7406 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7407 "pld/unalloc memhint", dsc);
7411 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
7414 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7418 case 2: /* Load word */
7420 int insn2_bit_8_11 = bits (insn2, 8, 11);
7423 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
7424 else if (op1 == 0x1) /* Encoding T3 */
7425 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
7427 else /* op1 == 0x0 */
7429 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
7430 /* LDR (immediate) */
7431 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7432 dsc, bit (insn2, 8), 1);
7433 else if (insn2_bit_8_11 == 0xe) /* LDRT */
7434 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7437 /* LDR (register) */
7438 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs,
7444 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7451 thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
7452 uint16_t insn2, struct regcache *regs,
7453 struct displaced_step_closure *dsc)
7456 unsigned short op = bit (insn2, 15);
7457 unsigned int op1 = bits (insn1, 11, 12);
7463 switch (bits (insn1, 9, 10))
7468 /* Load/store {dual, execlusive}, table branch. */
7469 if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1
7470 && bits (insn2, 5, 7) == 0)
7471 err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs,
7474 /* PC is not allowed to use in load/store {dual, exclusive}
7476 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7477 "load/store dual/ex", dsc);
7479 else /* load/store multiple */
7481 switch (bits (insn1, 7, 8))
7483 case 0: case 3: /* SRS, RFE */
7484 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7487 case 1: case 2: /* LDM/STM/PUSH/POP */
7488 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
7495 /* Data-processing (shift register). */
7496 err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs,
7499 default: /* Coprocessor instructions. */
7500 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7505 case 2: /* op1 = 2 */
7506 if (op) /* Branch and misc control. */
7508 if (bit (insn2, 14) /* BLX/BL */
7509 || bit (insn2, 12) /* Unconditional branch */
7510 || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */
7511 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
7513 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7518 if (bit (insn1, 9)) /* Data processing (plain binary imm). */
7520 int op = bits (insn1, 4, 8);
7521 int rn = bits (insn1, 0, 3);
7522 if ((op == 0 || op == 0xa) && rn == 0xf)
7523 err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
7526 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7529 else /* Data processing (modified immeidate) */
7530 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7534 case 3: /* op1 = 3 */
7535 switch (bits (insn1, 9, 10))
7539 err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2,
7541 else /* NEON Load/Store and Store single data item */
7542 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7543 "neon elt/struct load/store",
7546 case 1: /* op1 = 3, bits (9, 10) == 1 */
7547 switch (bits (insn1, 7, 8))
7549 case 0: case 1: /* Data processing (register) */
7550 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7553 case 2: /* Multiply and absolute difference */
7554 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7555 "mul/mua/diff", dsc);
7557 case 3: /* Long multiply and divide */
7558 err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
7563 default: /* Coprocessor instructions */
7564 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
7573 internal_error (__FILE__, __LINE__,
7574 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7579 thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7580 struct regcache *regs,
7581 struct displaced_step_closure *dsc)
7583 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7585 = read_memory_unsigned_integer (from, 2, byte_order_for_code);
7587 if (debug_displaced)
7588 fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x "
7589 "at %.8lx\n", insn1, (unsigned long) from);
7592 dsc->insn_size = thumb_insn_size (insn1);
7593 if (thumb_insn_size (insn1) == 4)
7596 = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code);
7597 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
7600 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
7604 arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
7605 CORE_ADDR to, struct regcache *regs,
7606 struct displaced_step_closure *dsc)
7609 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7612 /* Most displaced instructions use a 1-instruction scratch space, so set this
7613 here and override below if/when necessary. */
7615 dsc->insn_addr = from;
7616 dsc->scratch_base = to;
7617 dsc->cleanup = NULL;
7618 dsc->wrote_to_pc = 0;
7620 if (!displaced_in_arm_mode (regs))
7621 return thumb_process_displaced_insn (gdbarch, from, regs, dsc);
7625 insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
7626 if (debug_displaced)
7627 fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
7628 "at %.8lx\n", (unsigned long) insn,
7629 (unsigned long) from);
7631 if ((insn & 0xf0000000) == 0xf0000000)
7632 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
7633 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
7635 case 0x0: case 0x1: case 0x2: case 0x3:
7636 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
7639 case 0x4: case 0x5: case 0x6:
7640 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
7644 err = arm_decode_media (gdbarch, insn, dsc);
7647 case 0x8: case 0x9: case 0xa: case 0xb:
7648 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
7651 case 0xc: case 0xd: case 0xe: case 0xf:
7652 err = arm_decode_svc_copro (gdbarch, insn, regs, dsc);
7657 internal_error (__FILE__, __LINE__,
7658 _("arm_process_displaced_insn: Instruction decode error"));
7661 /* Actually set up the scratch space for a displaced instruction. */
7664 arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
7665 CORE_ADDR to, struct displaced_step_closure *dsc)
7667 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7668 unsigned int i, len, offset;
7669 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7670 int size = dsc->is_thumb? 2 : 4;
7671 const gdb_byte *bkp_insn;
7674 /* Poke modified instruction(s). */
7675 for (i = 0; i < dsc->numinsns; i++)
7677 if (debug_displaced)
7679 fprintf_unfiltered (gdb_stdlog, "displaced: writing insn ");
7681 fprintf_unfiltered (gdb_stdlog, "%.8lx",
7684 fprintf_unfiltered (gdb_stdlog, "%.4x",
7685 (unsigned short)dsc->modinsn[i]);
7687 fprintf_unfiltered (gdb_stdlog, " at %.8lx\n",
7688 (unsigned long) to + offset);
7691 write_memory_unsigned_integer (to + offset, size,
7692 byte_order_for_code,
7697 /* Choose the correct breakpoint instruction. */
7700 bkp_insn = tdep->thumb_breakpoint;
7701 len = tdep->thumb_breakpoint_size;
7705 bkp_insn = tdep->arm_breakpoint;
7706 len = tdep->arm_breakpoint_size;
7709 /* Put breakpoint afterwards. */
7710 write_memory (to + offset, bkp_insn, len);
7712 if (debug_displaced)
7713 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
7714 paddress (gdbarch, from), paddress (gdbarch, to));
7717 /* Entry point for cleaning things up after a displaced instruction has been
7721 arm_displaced_step_fixup (struct gdbarch *gdbarch,
7722 struct displaced_step_closure *dsc,
7723 CORE_ADDR from, CORE_ADDR to,
7724 struct regcache *regs)
7727 dsc->cleanup (gdbarch, regs, dsc);
7729 if (!dsc->wrote_to_pc)
7730 regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
7731 dsc->insn_addr + dsc->insn_size);
7735 #include "bfd-in2.h"
7736 #include "libcoff.h"
7739 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
7741 gdb_disassembler *di
7742 = static_cast<gdb_disassembler *>(info->application_data);
7743 struct gdbarch *gdbarch = di->arch ();
7745 if (arm_pc_is_thumb (gdbarch, memaddr))
7747 static asymbol *asym;
7748 static combined_entry_type ce;
7749 static struct coff_symbol_struct csym;
7750 static struct bfd fake_bfd;
7751 static bfd_target fake_target;
7753 if (csym.native == NULL)
7755 /* Create a fake symbol vector containing a Thumb symbol.
7756 This is solely so that the code in print_insn_little_arm()
7757 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7758 the presence of a Thumb symbol and switch to decoding
7759 Thumb instructions. */
7761 fake_target.flavour = bfd_target_coff_flavour;
7762 fake_bfd.xvec = &fake_target;
7763 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
7765 csym.symbol.the_bfd = &fake_bfd;
7766 csym.symbol.name = "fake";
7767 asym = (asymbol *) & csym;
7770 memaddr = UNMAKE_THUMB_ADDR (memaddr);
7771 info->symbols = &asym;
7774 info->symbols = NULL;
7776 /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
7777 accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
7778 opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
7779 the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
7780 in default_print_insn. */
7781 if (exec_bfd != NULL)
7782 info->flags |= USER_SPECIFIED_MACHINE_TYPE;
7784 return default_print_insn (memaddr, info);
7787 /* The following define instruction sequences that will cause ARM
7788 cpu's to take an undefined instruction trap. These are used to
7789 signal a breakpoint to GDB.
7791 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7792 modes. A different instruction is required for each mode. The ARM
7793 cpu's can also be big or little endian. Thus four different
7794 instructions are needed to support all cases.
7796 Note: ARMv4 defines several new instructions that will take the
7797 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7798 not in fact add the new instructions. The new undefined
7799 instructions in ARMv4 are all instructions that had no defined
7800 behaviour in earlier chips. There is no guarantee that they will
7801 raise an exception, but may be treated as NOP's. In practice, it
7802 may only safe to rely on instructions matching:
7804 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7805 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7806 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7808 Even this may only true if the condition predicate is true. The
7809 following use a condition predicate of ALWAYS so it is always TRUE.
7811 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7812 and NetBSD all use a software interrupt rather than an undefined
7813 instruction to force a trap. This can be handled by by the
7814 abi-specific code during establishment of the gdbarch vector. */
7816 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7817 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7818 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7819 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7821 static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
7822 static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
7823 static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
7824 static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
7826 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7829 arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
7831 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7832 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7834 if (arm_pc_is_thumb (gdbarch, *pcptr))
7836 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
7838 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7839 check whether we are replacing a 32-bit instruction. */
7840 if (tdep->thumb2_breakpoint != NULL)
7844 if (target_read_memory (*pcptr, buf, 2) == 0)
7846 unsigned short inst1;
7848 inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code);
7849 if (thumb_insn_size (inst1) == 4)
7850 return ARM_BP_KIND_THUMB2;
7854 return ARM_BP_KIND_THUMB;
7857 return ARM_BP_KIND_ARM;
7861 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7863 static const gdb_byte *
7864 arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
7866 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7870 case ARM_BP_KIND_ARM:
7871 *size = tdep->arm_breakpoint_size;
7872 return tdep->arm_breakpoint;
7873 case ARM_BP_KIND_THUMB:
7874 *size = tdep->thumb_breakpoint_size;
7875 return tdep->thumb_breakpoint;
7876 case ARM_BP_KIND_THUMB2:
7877 *size = tdep->thumb2_breakpoint_size;
7878 return tdep->thumb2_breakpoint;
7880 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7884 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7887 arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
7888 struct regcache *regcache,
7893 /* Check the memory pointed by PC is readable. */
7894 if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
7896 struct arm_get_next_pcs next_pcs_ctx;
7898 arm_get_next_pcs_ctor (&next_pcs_ctx,
7899 &arm_get_next_pcs_ops,
7900 gdbarch_byte_order (gdbarch),
7901 gdbarch_byte_order_for_code (gdbarch),
7905 std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
7907 /* If MEMADDR is the next instruction of current pc, do the
7908 software single step computation, and get the thumb mode by
7909 the destination address. */
7910 for (CORE_ADDR pc : next_pcs)
7912 if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
7914 if (IS_THUMB_ADDR (pc))
7916 *pcptr = MAKE_THUMB_ADDR (*pcptr);
7917 return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
7920 return ARM_BP_KIND_ARM;
7925 return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
7928 /* Extract from an array REGBUF containing the (raw) register state a
7929 function return value of type TYPE, and copy that, in virtual
7930 format, into VALBUF. */
7933 arm_extract_return_value (struct type *type, struct regcache *regs,
7936 struct gdbarch *gdbarch = get_regcache_arch (regs);
7937 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7939 if (TYPE_CODE_FLT == TYPE_CODE (type))
7941 switch (gdbarch_tdep (gdbarch)->fp_model)
7945 /* The value is in register F0 in internal format. We need to
7946 extract the raw value and then convert it to the desired
7948 bfd_byte tmpbuf[FP_REGISTER_SIZE];
7950 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
7951 convert_from_extended (floatformat_from_type (type), tmpbuf,
7952 valbuf, gdbarch_byte_order (gdbarch));
7956 case ARM_FLOAT_SOFT_FPA:
7957 case ARM_FLOAT_SOFT_VFP:
7958 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7959 not using the VFP ABI code. */
7961 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
7962 if (TYPE_LENGTH (type) > 4)
7963 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7964 valbuf + INT_REGISTER_SIZE);
7968 internal_error (__FILE__, __LINE__,
7969 _("arm_extract_return_value: "
7970 "Floating point model not supported"));
7974 else if (TYPE_CODE (type) == TYPE_CODE_INT
7975 || TYPE_CODE (type) == TYPE_CODE_CHAR
7976 || TYPE_CODE (type) == TYPE_CODE_BOOL
7977 || TYPE_CODE (type) == TYPE_CODE_PTR
7978 || TYPE_IS_REFERENCE (type)
7979 || TYPE_CODE (type) == TYPE_CODE_ENUM)
7981 /* If the type is a plain integer, then the access is
7982 straight-forward. Otherwise we have to play around a bit
7984 int len = TYPE_LENGTH (type);
7985 int regno = ARM_A1_REGNUM;
7990 /* By using store_unsigned_integer we avoid having to do
7991 anything special for small big-endian values. */
7992 regcache_cooked_read_unsigned (regs, regno++, &tmp);
7993 store_unsigned_integer (valbuf,
7994 (len > INT_REGISTER_SIZE
7995 ? INT_REGISTER_SIZE : len),
7997 len -= INT_REGISTER_SIZE;
7998 valbuf += INT_REGISTER_SIZE;
8003 /* For a structure or union the behaviour is as if the value had
8004 been stored to word-aligned memory and then loaded into
8005 registers with 32-bit load instruction(s). */
8006 int len = TYPE_LENGTH (type);
8007 int regno = ARM_A1_REGNUM;
8008 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8012 regcache_cooked_read (regs, regno++, tmpbuf);
8013 memcpy (valbuf, tmpbuf,
8014 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8015 len -= INT_REGISTER_SIZE;
8016 valbuf += INT_REGISTER_SIZE;
8022 /* Will a function return an aggregate type in memory or in a
8023 register? Return 0 if an aggregate type can be returned in a
8024 register, 1 if it must be returned in memory. */
8027 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
8029 enum type_code code;
8031 type = check_typedef (type);
8033 /* Simple, non-aggregate types (ie not including vectors and
8034 complex) are always returned in a register (or registers). */
8035 code = TYPE_CODE (type);
8036 if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code
8037 && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code)
8040 if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type))
8042 /* Vector values should be returned using ARM registers if they
8043 are not over 16 bytes. */
8044 return (TYPE_LENGTH (type) > 16);
8047 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
8049 /* The AAPCS says all aggregates not larger than a word are returned
8051 if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
8060 /* All aggregate types that won't fit in a register must be returned
8062 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
8065 /* In the ARM ABI, "integer" like aggregate types are returned in
8066 registers. For an aggregate type to be integer like, its size
8067 must be less than or equal to INT_REGISTER_SIZE and the
8068 offset of each addressable subfield must be zero. Note that bit
8069 fields are not addressable, and all addressable subfields of
8070 unions always start at offset zero.
8072 This function is based on the behaviour of GCC 2.95.1.
8073 See: gcc/arm.c: arm_return_in_memory() for details.
8075 Note: All versions of GCC before GCC 2.95.2 do not set up the
8076 parameters correctly for a function returning the following
8077 structure: struct { float f;}; This should be returned in memory,
8078 not a register. Richard Earnshaw sent me a patch, but I do not
8079 know of any way to detect if a function like the above has been
8080 compiled with the correct calling convention. */
8082 /* Assume all other aggregate types can be returned in a register.
8083 Run a check for structures, unions and arrays. */
8086 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
8089 /* Need to check if this struct/union is "integer" like. For
8090 this to be true, its size must be less than or equal to
8091 INT_REGISTER_SIZE and the offset of each addressable
8092 subfield must be zero. Note that bit fields are not
8093 addressable, and unions always start at offset zero. If any
8094 of the subfields is a floating point type, the struct/union
8095 cannot be an integer type. */
8097 /* For each field in the object, check:
8098 1) Is it FP? --> yes, nRc = 1;
8099 2) Is it addressable (bitpos != 0) and
8100 not packed (bitsize == 0)?
8104 for (i = 0; i < TYPE_NFIELDS (type); i++)
8106 enum type_code field_type_code;
8109 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
8112 /* Is it a floating point type field? */
8113 if (field_type_code == TYPE_CODE_FLT)
8119 /* If bitpos != 0, then we have to care about it. */
8120 if (TYPE_FIELD_BITPOS (type, i) != 0)
8122 /* Bitfields are not addressable. If the field bitsize is
8123 zero, then the field is not packed. Hence it cannot be
8124 a bitfield or any other packed type. */
8125 if (TYPE_FIELD_BITSIZE (type, i) == 0)
8138 /* Write into appropriate registers a function return value of type
8139 TYPE, given in virtual format. */
8142 arm_store_return_value (struct type *type, struct regcache *regs,
8143 const gdb_byte *valbuf)
8145 struct gdbarch *gdbarch = get_regcache_arch (regs);
8146 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8148 if (TYPE_CODE (type) == TYPE_CODE_FLT)
8150 gdb_byte buf[FP_REGISTER_SIZE];
8152 switch (gdbarch_tdep (gdbarch)->fp_model)
8156 convert_to_extended (floatformat_from_type (type), buf, valbuf,
8157 gdbarch_byte_order (gdbarch));
8158 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
8161 case ARM_FLOAT_SOFT_FPA:
8162 case ARM_FLOAT_SOFT_VFP:
8163 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8164 not using the VFP ABI code. */
8166 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
8167 if (TYPE_LENGTH (type) > 4)
8168 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
8169 valbuf + INT_REGISTER_SIZE);
8173 internal_error (__FILE__, __LINE__,
8174 _("arm_store_return_value: Floating "
8175 "point model not supported"));
8179 else if (TYPE_CODE (type) == TYPE_CODE_INT
8180 || TYPE_CODE (type) == TYPE_CODE_CHAR
8181 || TYPE_CODE (type) == TYPE_CODE_BOOL
8182 || TYPE_CODE (type) == TYPE_CODE_PTR
8183 || TYPE_IS_REFERENCE (type)
8184 || TYPE_CODE (type) == TYPE_CODE_ENUM)
8186 if (TYPE_LENGTH (type) <= 4)
8188 /* Values of one word or less are zero/sign-extended and
8190 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8191 LONGEST val = unpack_long (type, valbuf);
8193 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
8194 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
8198 /* Integral values greater than one word are stored in consecutive
8199 registers starting with r0. This will always be a multiple of
8200 the regiser size. */
8201 int len = TYPE_LENGTH (type);
8202 int regno = ARM_A1_REGNUM;
8206 regcache_cooked_write (regs, regno++, valbuf);
8207 len -= INT_REGISTER_SIZE;
8208 valbuf += INT_REGISTER_SIZE;
8214 /* For a structure or union the behaviour is as if the value had
8215 been stored to word-aligned memory and then loaded into
8216 registers with 32-bit load instruction(s). */
8217 int len = TYPE_LENGTH (type);
8218 int regno = ARM_A1_REGNUM;
8219 bfd_byte tmpbuf[INT_REGISTER_SIZE];
8223 memcpy (tmpbuf, valbuf,
8224 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
8225 regcache_cooked_write (regs, regno++, tmpbuf);
8226 len -= INT_REGISTER_SIZE;
8227 valbuf += INT_REGISTER_SIZE;
8233 /* Handle function return values. */
8235 static enum return_value_convention
8236 arm_return_value (struct gdbarch *gdbarch, struct value *function,
8237 struct type *valtype, struct regcache *regcache,
8238 gdb_byte *readbuf, const gdb_byte *writebuf)
8240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8241 struct type *func_type = function ? value_type (function) : NULL;
8242 enum arm_vfp_cprc_base_type vfp_base_type;
8245 if (arm_vfp_abi_for_function (gdbarch, func_type)
8246 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
8248 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
8249 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
8251 for (i = 0; i < vfp_base_count; i++)
8253 if (reg_char == 'q')
8256 arm_neon_quad_write (gdbarch, regcache, i,
8257 writebuf + i * unit_length);
8260 arm_neon_quad_read (gdbarch, regcache, i,
8261 readbuf + i * unit_length);
8268 xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i);
8269 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8272 regcache_cooked_write (regcache, regnum,
8273 writebuf + i * unit_length);
8275 regcache_cooked_read (regcache, regnum,
8276 readbuf + i * unit_length);
8279 return RETURN_VALUE_REGISTER_CONVENTION;
8282 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
8283 || TYPE_CODE (valtype) == TYPE_CODE_UNION
8284 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
8286 if (tdep->struct_return == pcc_struct_return
8287 || arm_return_in_memory (gdbarch, valtype))
8288 return RETURN_VALUE_STRUCT_CONVENTION;
8290 else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX)
8292 if (arm_return_in_memory (gdbarch, valtype))
8293 return RETURN_VALUE_STRUCT_CONVENTION;
8297 arm_store_return_value (valtype, regcache, writebuf);
8300 arm_extract_return_value (valtype, regcache, readbuf);
8302 return RETURN_VALUE_REGISTER_CONVENTION;
8307 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
8309 struct gdbarch *gdbarch = get_frame_arch (frame);
8310 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8311 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8313 gdb_byte buf[INT_REGISTER_SIZE];
8315 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
8317 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
8321 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
8325 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8326 return the target PC. Otherwise return 0. */
8329 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
8333 CORE_ADDR start_addr;
8335 /* Find the starting address and name of the function containing the PC. */
8336 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
8338 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8340 start_addr = arm_skip_bx_reg (frame, pc);
8341 if (start_addr != 0)
8347 /* If PC is in a Thumb call or return stub, return the address of the
8348 target PC, which is in a register. The thunk functions are called
8349 _call_via_xx, where x is the register name. The possible names
8350 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8351 functions, named __ARM_call_via_r[0-7]. */
8352 if (startswith (name, "_call_via_")
8353 || startswith (name, "__ARM_call_via_"))
8355 /* Use the name suffix to determine which register contains the
8357 static const char *table[15] =
8358 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8359 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8362 int offset = strlen (name) - 2;
8364 for (regno = 0; regno <= 14; regno++)
8365 if (strcmp (&name[offset], table[regno]) == 0)
8366 return get_frame_register_unsigned (frame, regno);
8369 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8370 non-interworking calls to foo. We could decode the stubs
8371 to find the target but it's easier to use the symbol table. */
8372 namelen = strlen (name);
8373 if (name[0] == '_' && name[1] == '_'
8374 && ((namelen > 2 + strlen ("_from_thumb")
8375 && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb"))
8376 || (namelen > 2 + strlen ("_from_arm")
8377 && startswith (name + namelen - strlen ("_from_arm"), "_from_arm"))))
8380 int target_len = namelen - 2;
8381 struct bound_minimal_symbol minsym;
8382 struct objfile *objfile;
8383 struct obj_section *sec;
8385 if (name[namelen - 1] == 'b')
8386 target_len -= strlen ("_from_thumb");
8388 target_len -= strlen ("_from_arm");
8390 target_name = (char *) alloca (target_len + 1);
8391 memcpy (target_name, name + 2, target_len);
8392 target_name[target_len] = '\0';
8394 sec = find_pc_section (pc);
8395 objfile = (sec == NULL) ? NULL : sec->objfile;
8396 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
8397 if (minsym.minsym != NULL)
8398 return BMSYMBOL_VALUE_ADDRESS (minsym);
8403 return 0; /* not a stub */
8407 set_arm_command (char *args, int from_tty)
8409 printf_unfiltered (_("\
8410 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8411 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
8415 show_arm_command (char *args, int from_tty)
8417 cmd_show_list (showarmcmdlist, from_tty, "");
8421 arm_update_current_architecture (void)
8423 struct gdbarch_info info;
8425 /* If the current architecture is not ARM, we have nothing to do. */
8426 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm)
8429 /* Update the architecture. */
8430 gdbarch_info_init (&info);
8432 if (!gdbarch_update_p (info))
8433 internal_error (__FILE__, __LINE__, _("could not update architecture"));
8437 set_fp_model_sfunc (char *args, int from_tty,
8438 struct cmd_list_element *c)
8442 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
8443 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
8445 arm_fp_model = (enum arm_float_model) fp_model;
8449 if (fp_model == ARM_FLOAT_LAST)
8450 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
8453 arm_update_current_architecture ();
8457 show_fp_model (struct ui_file *file, int from_tty,
8458 struct cmd_list_element *c, const char *value)
8460 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8462 if (arm_fp_model == ARM_FLOAT_AUTO
8463 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8464 fprintf_filtered (file, _("\
8465 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8466 fp_model_strings[tdep->fp_model]);
8468 fprintf_filtered (file, _("\
8469 The current ARM floating point model is \"%s\".\n"),
8470 fp_model_strings[arm_fp_model]);
8474 arm_set_abi (char *args, int from_tty,
8475 struct cmd_list_element *c)
8479 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
8480 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
8482 arm_abi_global = (enum arm_abi_kind) arm_abi;
8486 if (arm_abi == ARM_ABI_LAST)
8487 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
8490 arm_update_current_architecture ();
8494 arm_show_abi (struct ui_file *file, int from_tty,
8495 struct cmd_list_element *c, const char *value)
8497 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
8499 if (arm_abi_global == ARM_ABI_AUTO
8500 && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm)
8501 fprintf_filtered (file, _("\
8502 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8503 arm_abi_strings[tdep->arm_abi]);
8505 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
8510 arm_show_fallback_mode (struct ui_file *file, int from_tty,
8511 struct cmd_list_element *c, const char *value)
8513 fprintf_filtered (file,
8514 _("The current execution mode assumed "
8515 "(when symbols are unavailable) is \"%s\".\n"),
8516 arm_fallback_mode_string);
8520 arm_show_force_mode (struct ui_file *file, int from_tty,
8521 struct cmd_list_element *c, const char *value)
8523 fprintf_filtered (file,
8524 _("The current execution mode assumed "
8525 "(even when symbols are available) is \"%s\".\n"),
8526 arm_force_mode_string);
8529 /* If the user changes the register disassembly style used for info
8530 register and other commands, we have to also switch the style used
8531 in opcodes for disassembly output. This function is run in the "set
8532 arm disassembly" command, and does that. */
8535 set_disassembly_style_sfunc (char *args, int from_tty,
8536 struct cmd_list_element *c)
8538 /* Convert the short style name into the long style name (eg, reg-names-*)
8539 before calling the generic set_disassembler_options() function. */
8540 std::string long_name = std::string ("reg-names-") + disassembly_style;
8541 set_disassembler_options (&long_name[0]);
8545 show_disassembly_style_sfunc (struct ui_file *file, int from_tty,
8546 struct cmd_list_element *c, const char *value)
8548 struct gdbarch *gdbarch = get_current_arch ();
8549 char *options = get_disassembler_options (gdbarch);
8550 const char *style = "";
8554 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
8555 if (CONST_STRNEQ (opt, "reg-names-"))
8557 style = &opt[strlen ("reg-names-")];
8558 len = strcspn (style, ",");
8561 fprintf_unfiltered (file, "The disassembly style is \"%.*s\".\n", len, style);
8564 /* Return the ARM register name corresponding to register I. */
8566 arm_register_name (struct gdbarch *gdbarch, int i)
8568 const int num_regs = gdbarch_num_regs (gdbarch);
8570 if (gdbarch_tdep (gdbarch)->have_vfp_pseudos
8571 && i >= num_regs && i < num_regs + 32)
8573 static const char *const vfp_pseudo_names[] = {
8574 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8575 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8576 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8577 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8580 return vfp_pseudo_names[i - num_regs];
8583 if (gdbarch_tdep (gdbarch)->have_neon_pseudos
8584 && i >= num_regs + 32 && i < num_regs + 32 + 16)
8586 static const char *const neon_pseudo_names[] = {
8587 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8588 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8591 return neon_pseudo_names[i - num_regs - 32];
8594 if (i >= ARRAY_SIZE (arm_register_names))
8595 /* These registers are only supported on targets which supply
8596 an XML description. */
8599 return arm_register_names[i];
8602 /* Test whether the coff symbol specific value corresponds to a Thumb
8606 coff_sym_is_thumb (int val)
8608 return (val == C_THUMBEXT
8609 || val == C_THUMBSTAT
8610 || val == C_THUMBEXTFUNC
8611 || val == C_THUMBSTATFUNC
8612 || val == C_THUMBLABEL);
8615 /* arm_coff_make_msymbol_special()
8616 arm_elf_make_msymbol_special()
8618 These functions test whether the COFF or ELF symbol corresponds to
8619 an address in thumb code, and set a "special" bit in a minimal
8620 symbol to indicate that it does. */
8623 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
8625 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
8627 if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal)
8628 == ST_BRANCH_TO_THUMB)
8629 MSYMBOL_SET_SPECIAL (msym);
8633 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
8635 if (coff_sym_is_thumb (val))
8636 MSYMBOL_SET_SPECIAL (msym);
8640 arm_objfile_data_free (struct objfile *objfile, void *arg)
8642 struct arm_per_objfile *data = (struct arm_per_objfile *) arg;
8645 for (i = 0; i < objfile->obfd->section_count; i++)
8646 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
8650 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
8653 const char *name = bfd_asymbol_name (sym);
8654 struct arm_per_objfile *data;
8655 VEC(arm_mapping_symbol_s) **map_p;
8656 struct arm_mapping_symbol new_map_sym;
8658 gdb_assert (name[0] == '$');
8659 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
8662 data = (struct arm_per_objfile *) objfile_data (objfile,
8663 arm_objfile_data_key);
8666 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
8667 struct arm_per_objfile);
8668 set_objfile_data (objfile, arm_objfile_data_key, data);
8669 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
8670 objfile->obfd->section_count,
8671 VEC(arm_mapping_symbol_s) *);
8673 map_p = &data->section_maps[bfd_get_section (sym)->index];
8675 new_map_sym.value = sym->value;
8676 new_map_sym.type = name[1];
8678 /* Assume that most mapping symbols appear in order of increasing
8679 value. If they were randomly distributed, it would be faster to
8680 always push here and then sort at first use. */
8681 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
8683 struct arm_mapping_symbol *prev_map_sym;
8685 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
8686 if (prev_map_sym->value >= sym->value)
8689 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
8690 arm_compare_mapping_symbols);
8691 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
8696 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
8700 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
8702 struct gdbarch *gdbarch = get_regcache_arch (regcache);
8703 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
8705 /* If necessary, set the T bit. */
8708 ULONGEST val, t_bit;
8709 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
8710 t_bit = arm_psr_thumb_bit (gdbarch);
8711 if (arm_pc_is_thumb (gdbarch, pc))
8712 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8715 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
8720 /* Read the contents of a NEON quad register, by reading from two
8721 double registers. This is used to implement the quad pseudo
8722 registers, and for argument passing in case the quad registers are
8723 missing; vectors are passed in quad registers when using the VFP
8724 ABI, even if a NEON unit is not present. REGNUM is the index of
8725 the quad register, in [0, 15]. */
8727 static enum register_status
8728 arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
8729 int regnum, gdb_byte *buf)
8732 gdb_byte reg_buf[8];
8733 int offset, double_regnum;
8734 enum register_status status;
8736 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8737 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8740 /* d0 is always the least significant half of q0. */
8741 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8746 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8747 if (status != REG_VALID)
8749 memcpy (buf + offset, reg_buf, 8);
8751 offset = 8 - offset;
8752 status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
8753 if (status != REG_VALID)
8755 memcpy (buf + offset, reg_buf, 8);
8760 static enum register_status
8761 arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
8762 int regnum, gdb_byte *buf)
8764 const int num_regs = gdbarch_num_regs (gdbarch);
8766 gdb_byte reg_buf[8];
8767 int offset, double_regnum;
8769 gdb_assert (regnum >= num_regs);
8772 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8773 /* Quad-precision register. */
8774 return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf);
8777 enum register_status status;
8779 /* Single-precision register. */
8780 gdb_assert (regnum < 32);
8782 /* s0 is always the least significant half of d0. */
8783 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8784 offset = (regnum & 1) ? 0 : 4;
8786 offset = (regnum & 1) ? 4 : 0;
8788 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8789 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8792 status = regcache_raw_read (regcache, double_regnum, reg_buf);
8793 if (status == REG_VALID)
8794 memcpy (buf, reg_buf + offset, 4);
8799 /* Store the contents of BUF to a NEON quad register, by writing to
8800 two double registers. This is used to implement the quad pseudo
8801 registers, and for argument passing in case the quad registers are
8802 missing; vectors are passed in quad registers when using the VFP
8803 ABI, even if a NEON unit is not present. REGNUM is the index
8804 of the quad register, in [0, 15]. */
8807 arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
8808 int regnum, const gdb_byte *buf)
8811 int offset, double_regnum;
8813 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1);
8814 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8817 /* d0 is always the least significant half of q0. */
8818 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8823 regcache_raw_write (regcache, double_regnum, buf + offset);
8824 offset = 8 - offset;
8825 regcache_raw_write (regcache, double_regnum + 1, buf + offset);
8829 arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
8830 int regnum, const gdb_byte *buf)
8832 const int num_regs = gdbarch_num_regs (gdbarch);
8834 gdb_byte reg_buf[8];
8835 int offset, double_regnum;
8837 gdb_assert (regnum >= num_regs);
8840 if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
8841 /* Quad-precision register. */
8842 arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf);
8845 /* Single-precision register. */
8846 gdb_assert (regnum < 32);
8848 /* s0 is always the least significant half of d0. */
8849 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8850 offset = (regnum & 1) ? 0 : 4;
8852 offset = (regnum & 1) ? 4 : 0;
8854 xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1);
8855 double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
8858 regcache_raw_read (regcache, double_regnum, reg_buf);
8859 memcpy (reg_buf + offset, buf, 4);
8860 regcache_raw_write (regcache, double_regnum, reg_buf);
8864 static struct value *
8865 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
8867 const int *reg_p = (const int *) baton;
8868 return value_of_register (*reg_p, frame);
8871 static enum gdb_osabi
8872 arm_elf_osabi_sniffer (bfd *abfd)
8874 unsigned int elfosabi;
8875 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
8877 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
8879 if (elfosabi == ELFOSABI_ARM)
8880 /* GNU tools use this value. Check note sections in this case,
8882 bfd_map_over_sections (abfd,
8883 generic_elf_osabi_sniff_abi_tag_sections,
8886 /* Anything else will be handled by the generic ELF sniffer. */
8891 arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
8892 struct reggroup *group)
8894 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8895 this, FPS register belongs to save_regroup, restore_reggroup, and
8896 all_reggroup, of course. */
8897 if (regnum == ARM_FPS_REGNUM)
8898 return (group == float_reggroup
8899 || group == save_reggroup
8900 || group == restore_reggroup
8901 || group == all_reggroup);
8903 return default_register_reggroup_p (gdbarch, regnum, group);
8907 /* For backward-compatibility we allow two 'g' packet lengths with
8908 the remote protocol depending on whether FPA registers are
8909 supplied. M-profile targets do not have FPA registers, but some
8910 stubs already exist in the wild which use a 'g' packet which
8911 supplies them albeit with dummy values. The packet format which
8912 includes FPA registers should be considered deprecated for
8913 M-profile targets. */
8916 arm_register_g_packet_guesses (struct gdbarch *gdbarch)
8918 if (gdbarch_tdep (gdbarch)->is_m)
8920 /* If we know from the executable this is an M-profile target,
8921 cater for remote targets whose register set layout is the
8922 same as the FPA layout. */
8923 register_remote_g_packet_guess (gdbarch,
8924 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8925 (16 * INT_REGISTER_SIZE)
8926 + (8 * FP_REGISTER_SIZE)
8927 + (2 * INT_REGISTER_SIZE),
8928 tdesc_arm_with_m_fpa_layout);
8930 /* The regular M-profile layout. */
8931 register_remote_g_packet_guess (gdbarch,
8932 /* r0-r12,sp,lr,pc; xpsr */
8933 (16 * INT_REGISTER_SIZE)
8934 + INT_REGISTER_SIZE,
8937 /* M-profile plus M4F VFP. */
8938 register_remote_g_packet_guess (gdbarch,
8939 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8940 (16 * INT_REGISTER_SIZE)
8941 + (16 * VFP_REGISTER_SIZE)
8942 + (2 * INT_REGISTER_SIZE),
8943 tdesc_arm_with_m_vfp_d16);
8946 /* Otherwise we don't have a useful guess. */
8949 /* Implement the code_of_frame_writable gdbarch method. */
8952 arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame)
8954 if (gdbarch_tdep (gdbarch)->is_m
8955 && get_frame_type (frame) == SIGTRAMP_FRAME)
8957 /* M-profile exception frames return to some magic PCs, where
8958 isn't writable at all. */
8966 /* Initialize the current architecture based on INFO. If possible,
8967 re-use an architecture from ARCHES, which is a list of
8968 architectures already created during this debugging session.
8970 Called e.g. at program startup, when reading a core file, and when
8971 reading a binary file. */
8973 static struct gdbarch *
8974 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8976 struct gdbarch_tdep *tdep;
8977 struct gdbarch *gdbarch;
8978 struct gdbarch_list *best_arch;
8979 enum arm_abi_kind arm_abi = arm_abi_global;
8980 enum arm_float_model fp_model = arm_fp_model;
8981 struct tdesc_arch_data *tdesc_data = NULL;
8983 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
8984 int have_wmmx_registers = 0;
8986 int have_fpa_registers = 1;
8987 const struct target_desc *tdesc = info.target_desc;
8989 /* If we have an object to base this architecture on, try to determine
8992 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
8994 int ei_osabi, e_flags;
8996 switch (bfd_get_flavour (info.abfd))
8998 case bfd_target_coff_flavour:
8999 /* Assume it's an old APCS-style ABI. */
9001 arm_abi = ARM_ABI_APCS;
9004 case bfd_target_elf_flavour:
9005 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
9006 e_flags = elf_elfheader (info.abfd)->e_flags;
9008 if (ei_osabi == ELFOSABI_ARM)
9010 /* GNU tools used to use this value, but do not for EABI
9011 objects. There's nowhere to tag an EABI version
9012 anyway, so assume APCS. */
9013 arm_abi = ARM_ABI_APCS;
9015 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
9017 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9018 int attr_arch, attr_profile;
9022 case EF_ARM_EABI_UNKNOWN:
9023 /* Assume GNU tools. */
9024 arm_abi = ARM_ABI_APCS;
9027 case EF_ARM_EABI_VER4:
9028 case EF_ARM_EABI_VER5:
9029 arm_abi = ARM_ABI_AAPCS;
9030 /* EABI binaries default to VFP float ordering.
9031 They may also contain build attributes that can
9032 be used to identify if the VFP argument-passing
9034 if (fp_model == ARM_FLOAT_AUTO)
9037 switch (bfd_elf_get_obj_attr_int (info.abfd,
9041 case AEABI_VFP_args_base:
9042 /* "The user intended FP parameter/result
9043 passing to conform to AAPCS, base
9045 fp_model = ARM_FLOAT_SOFT_VFP;
9047 case AEABI_VFP_args_vfp:
9048 /* "The user intended FP parameter/result
9049 passing to conform to AAPCS, VFP
9051 fp_model = ARM_FLOAT_VFP;
9053 case AEABI_VFP_args_toolchain:
9054 /* "The user intended FP parameter/result
9055 passing to conform to tool chain-specific
9056 conventions" - we don't know any such
9057 conventions, so leave it as "auto". */
9059 case AEABI_VFP_args_compatible:
9060 /* "Code is compatible with both the base
9061 and VFP variants; the user did not permit
9062 non-variadic functions to pass FP
9063 parameters/results" - leave it as
9067 /* Attribute value not mentioned in the
9068 November 2012 ABI, so leave it as
9073 fp_model = ARM_FLOAT_SOFT_VFP;
9079 /* Leave it as "auto". */
9080 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
9085 /* Detect M-profile programs. This only works if the
9086 executable file includes build attributes; GCC does
9087 copy them to the executable, but e.g. RealView does
9089 attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
9091 attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
9093 Tag_CPU_arch_profile);
9094 /* GCC specifies the profile for v6-M; RealView only
9095 specifies the profile for architectures starting with
9096 V7 (as opposed to architectures with a tag
9097 numerically greater than TAG_CPU_ARCH_V7). */
9098 if (!tdesc_has_registers (tdesc)
9099 && (attr_arch == TAG_CPU_ARCH_V6_M
9100 || attr_arch == TAG_CPU_ARCH_V6S_M
9101 || attr_profile == 'M'))
9106 if (fp_model == ARM_FLOAT_AUTO)
9108 int e_flags = elf_elfheader (info.abfd)->e_flags;
9110 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
9113 /* Leave it as "auto". Strictly speaking this case
9114 means FPA, but almost nobody uses that now, and
9115 many toolchains fail to set the appropriate bits
9116 for the floating-point model they use. */
9118 case EF_ARM_SOFT_FLOAT:
9119 fp_model = ARM_FLOAT_SOFT_FPA;
9121 case EF_ARM_VFP_FLOAT:
9122 fp_model = ARM_FLOAT_VFP;
9124 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
9125 fp_model = ARM_FLOAT_SOFT_VFP;
9130 if (e_flags & EF_ARM_BE8)
9131 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
9136 /* Leave it as "auto". */
9141 /* Check any target description for validity. */
9142 if (tdesc_has_registers (tdesc))
9144 /* For most registers we require GDB's default names; but also allow
9145 the numeric names for sp / lr / pc, as a convenience. */
9146 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
9147 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
9148 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
9150 const struct tdesc_feature *feature;
9153 feature = tdesc_find_feature (tdesc,
9154 "org.gnu.gdb.arm.core");
9155 if (feature == NULL)
9157 feature = tdesc_find_feature (tdesc,
9158 "org.gnu.gdb.arm.m-profile");
9159 if (feature == NULL)
9165 tdesc_data = tdesc_data_alloc ();
9168 for (i = 0; i < ARM_SP_REGNUM; i++)
9169 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9170 arm_register_names[i]);
9171 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9174 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9177 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
9181 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9182 ARM_PS_REGNUM, "xpsr");
9184 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9185 ARM_PS_REGNUM, "cpsr");
9189 tdesc_data_cleanup (tdesc_data);
9193 feature = tdesc_find_feature (tdesc,
9194 "org.gnu.gdb.arm.fpa");
9195 if (feature != NULL)
9198 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
9199 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
9200 arm_register_names[i]);
9203 tdesc_data_cleanup (tdesc_data);
9208 have_fpa_registers = 0;
9210 feature = tdesc_find_feature (tdesc,
9211 "org.gnu.gdb.xscale.iwmmxt");
9212 if (feature != NULL)
9214 static const char *const iwmmxt_names[] = {
9215 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9216 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9217 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9218 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9222 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
9224 &= tdesc_numbered_register (feature, tdesc_data, i,
9225 iwmmxt_names[i - ARM_WR0_REGNUM]);
9227 /* Check for the control registers, but do not fail if they
9229 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
9230 tdesc_numbered_register (feature, tdesc_data, i,
9231 iwmmxt_names[i - ARM_WR0_REGNUM]);
9233 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
9235 &= tdesc_numbered_register (feature, tdesc_data, i,
9236 iwmmxt_names[i - ARM_WR0_REGNUM]);
9240 tdesc_data_cleanup (tdesc_data);
9244 have_wmmx_registers = 1;
9247 /* If we have a VFP unit, check whether the single precision registers
9248 are present. If not, then we will synthesize them as pseudo
9250 feature = tdesc_find_feature (tdesc,
9251 "org.gnu.gdb.arm.vfp");
9252 if (feature != NULL)
9254 static const char *const vfp_double_names[] = {
9255 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9256 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9257 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9258 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9261 /* Require the double precision registers. There must be either
9264 for (i = 0; i < 32; i++)
9266 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9268 vfp_double_names[i]);
9272 if (!valid_p && i == 16)
9275 /* Also require FPSCR. */
9276 valid_p &= tdesc_numbered_register (feature, tdesc_data,
9277 ARM_FPSCR_REGNUM, "fpscr");
9280 tdesc_data_cleanup (tdesc_data);
9284 if (tdesc_unnumbered_register (feature, "s0") == 0)
9285 have_vfp_pseudos = 1;
9287 vfp_register_count = i;
9289 /* If we have VFP, also check for NEON. The architecture allows
9290 NEON without VFP (integer vector operations only), but GDB
9291 does not support that. */
9292 feature = tdesc_find_feature (tdesc,
9293 "org.gnu.gdb.arm.neon");
9294 if (feature != NULL)
9296 /* NEON requires 32 double-precision registers. */
9299 tdesc_data_cleanup (tdesc_data);
9303 /* If there are quad registers defined by the stub, use
9304 their type; otherwise (normally) provide them with
9305 the default type. */
9306 if (tdesc_unnumbered_register (feature, "q0") == 0)
9307 have_neon_pseudos = 1;
9314 /* If there is already a candidate, use it. */
9315 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
9317 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
9319 if (arm_abi != ARM_ABI_AUTO
9320 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
9323 if (fp_model != ARM_FLOAT_AUTO
9324 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
9327 /* There are various other properties in tdep that we do not
9328 need to check here: those derived from a target description,
9329 since gdbarches with a different target description are
9330 automatically disqualified. */
9332 /* Do check is_m, though, since it might come from the binary. */
9333 if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m)
9336 /* Found a match. */
9340 if (best_arch != NULL)
9342 if (tdesc_data != NULL)
9343 tdesc_data_cleanup (tdesc_data);
9344 return best_arch->gdbarch;
9347 tdep = XCNEW (struct gdbarch_tdep);
9348 gdbarch = gdbarch_alloc (&info, tdep);
9350 /* Record additional information about the architecture we are defining.
9351 These are gdbarch discriminators, like the OSABI. */
9352 tdep->arm_abi = arm_abi;
9353 tdep->fp_model = fp_model;
9355 tdep->have_fpa_registers = have_fpa_registers;
9356 tdep->have_wmmx_registers = have_wmmx_registers;
9357 gdb_assert (vfp_register_count == 0
9358 || vfp_register_count == 16
9359 || vfp_register_count == 32);
9360 tdep->vfp_register_count = vfp_register_count;
9361 tdep->have_vfp_pseudos = have_vfp_pseudos;
9362 tdep->have_neon_pseudos = have_neon_pseudos;
9363 tdep->have_neon = have_neon;
9365 arm_register_g_packet_guesses (gdbarch);
9368 switch (info.byte_order_for_code)
9370 case BFD_ENDIAN_BIG:
9371 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
9372 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
9373 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
9374 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
9378 case BFD_ENDIAN_LITTLE:
9379 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
9380 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
9381 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
9382 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
9387 internal_error (__FILE__, __LINE__,
9388 _("arm_gdbarch_init: bad byte order for float format"));
9391 /* On ARM targets char defaults to unsigned. */
9392 set_gdbarch_char_signed (gdbarch, 0);
9394 /* wchar_t is unsigned under the AAPCS. */
9395 if (tdep->arm_abi == ARM_ABI_AAPCS)
9396 set_gdbarch_wchar_signed (gdbarch, 0);
9398 set_gdbarch_wchar_signed (gdbarch, 1);
9400 /* Note: for displaced stepping, this includes the breakpoint, and one word
9401 of additional scratch space. This setting isn't used for anything beside
9402 displaced stepping at present. */
9403 set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
9405 /* This should be low enough for everything. */
9406 tdep->lowest_pc = 0x20;
9407 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
9409 /* The default, for both APCS and AAPCS, is to return small
9410 structures in registers. */
9411 tdep->struct_return = reg_struct_return;
9413 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
9414 set_gdbarch_frame_align (gdbarch, arm_frame_align);
9417 set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable);
9419 set_gdbarch_write_pc (gdbarch, arm_write_pc);
9421 /* Frame handling. */
9422 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
9423 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
9424 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
9426 frame_base_set_default (gdbarch, &arm_normal_base);
9428 /* Address manipulation. */
9429 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
9431 /* Advance PC across function entry code. */
9432 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
9434 /* Detect whether PC is at a point where the stack has been destroyed. */
9435 set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p);
9437 /* Skip trampolines. */
9438 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
9440 /* The stack grows downward. */
9441 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
9443 /* Breakpoint manipulation. */
9444 set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc);
9445 set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind);
9446 set_gdbarch_breakpoint_kind_from_current_state (gdbarch,
9447 arm_breakpoint_kind_from_current_state);
9449 /* Information about registers, etc. */
9450 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
9451 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
9452 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
9453 set_gdbarch_register_type (gdbarch, arm_register_type);
9454 set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
9456 /* This "info float" is FPA-specific. Use the generic version if we
9458 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
9459 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
9461 /* Internal <-> external register number maps. */
9462 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
9463 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
9465 set_gdbarch_register_name (gdbarch, arm_register_name);
9467 /* Returning results. */
9468 set_gdbarch_return_value (gdbarch, arm_return_value);
9471 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
9473 /* Minsymbol frobbing. */
9474 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
9475 set_gdbarch_coff_make_msymbol_special (gdbarch,
9476 arm_coff_make_msymbol_special);
9477 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
9479 /* Thumb-2 IT block support. */
9480 set_gdbarch_adjust_breakpoint_address (gdbarch,
9481 arm_adjust_breakpoint_address);
9483 /* Virtual tables. */
9484 set_gdbarch_vbit_in_delta (gdbarch, 1);
9486 /* Hook in the ABI-specific overrides, if they have been registered. */
9487 gdbarch_init_osabi (info, gdbarch);
9489 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
9491 /* Add some default predicates. */
9493 frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind);
9494 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
9495 dwarf2_append_unwinders (gdbarch);
9496 frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
9497 frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind);
9498 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
9500 /* Now we have tuned the configuration, set a few final things,
9501 based on what the OS ABI has told us. */
9503 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9504 binaries are always marked. */
9505 if (tdep->arm_abi == ARM_ABI_AUTO)
9506 tdep->arm_abi = ARM_ABI_APCS;
9508 /* Watchpoints are not steppable. */
9509 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9511 /* We used to default to FPA for generic ARM, but almost nobody
9512 uses that now, and we now provide a way for the user to force
9513 the model. So default to the most useful variant. */
9514 if (tdep->fp_model == ARM_FLOAT_AUTO)
9515 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
9517 if (tdep->jb_pc >= 0)
9518 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
9520 /* Floating point sizes and format. */
9521 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
9522 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
9524 set_gdbarch_double_format
9525 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9526 set_gdbarch_long_double_format
9527 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
9531 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
9532 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
9535 if (have_vfp_pseudos)
9537 /* NOTE: These are the only pseudo registers used by
9538 the ARM target at the moment. If more are added, a
9539 little more care in numbering will be needed. */
9541 int num_pseudos = 32;
9542 if (have_neon_pseudos)
9544 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
9545 set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
9546 set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
9551 set_tdesc_pseudo_register_name (gdbarch, arm_register_name);
9553 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
9555 /* Override tdesc_register_type to adjust the types of VFP
9556 registers for NEON. */
9557 set_gdbarch_register_type (gdbarch, arm_register_type);
9560 /* Add standard register aliases. We add aliases even for those
9561 nanes which are used by the current architecture - it's simpler,
9562 and does no harm, since nothing ever lists user registers. */
9563 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
9564 user_reg_add (gdbarch, arm_register_aliases[i].name,
9565 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
9567 set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options);
9568 set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ());
9574 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
9576 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9581 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9582 (unsigned long) tdep->lowest_pc);
9588 static void arm_record_test (void);
9592 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
9595 _initialize_arm_tdep (void)
9598 const char *setname;
9599 const char *setdesc;
9601 char regdesc[1024], *rdptr = regdesc;
9602 size_t rest = sizeof (regdesc);
9604 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
9606 arm_objfile_data_key
9607 = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
9609 /* Add ourselves to objfile event chain. */
9610 observer_attach_new_objfile (arm_exidx_new_objfile);
9612 = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
9614 /* Register an ELF OS ABI sniffer for ARM binaries. */
9615 gdbarch_register_osabi_sniffer (bfd_arch_arm,
9616 bfd_target_elf_flavour,
9617 arm_elf_osabi_sniffer);
9619 /* Initialize the standard target descriptions. */
9620 initialize_tdesc_arm_with_m ();
9621 initialize_tdesc_arm_with_m_fpa_layout ();
9622 initialize_tdesc_arm_with_m_vfp_d16 ();
9623 initialize_tdesc_arm_with_iwmmxt ();
9624 initialize_tdesc_arm_with_vfpv2 ();
9625 initialize_tdesc_arm_with_vfpv3 ();
9626 initialize_tdesc_arm_with_neon ();
9628 /* Add root prefix command for all "set arm"/"show arm" commands. */
9629 add_prefix_cmd ("arm", no_class, set_arm_command,
9630 _("Various ARM-specific commands."),
9631 &setarmcmdlist, "set arm ", 0, &setlist);
9633 add_prefix_cmd ("arm", no_class, show_arm_command,
9634 _("Various ARM-specific commands."),
9635 &showarmcmdlist, "show arm ", 0, &showlist);
9638 arm_disassembler_options = xstrdup ("reg-names-std");
9639 const disasm_options_t *disasm_options = disassembler_options_arm ();
9640 int num_disassembly_styles = 0;
9641 for (i = 0; disasm_options->name[i] != NULL; i++)
9642 if (CONST_STRNEQ (disasm_options->name[i], "reg-names-"))
9643 num_disassembly_styles++;
9645 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
9646 valid_disassembly_styles = XNEWVEC (const char *,
9647 num_disassembly_styles + 1);
9648 for (i = j = 0; disasm_options->name[i] != NULL; i++)
9649 if (CONST_STRNEQ (disasm_options->name[i], "reg-names-"))
9651 size_t offset = strlen ("reg-names-");
9652 const char *style = disasm_options->name[i];
9653 valid_disassembly_styles[j++] = &style[offset];
9654 length = snprintf (rdptr, rest, "%s - %s\n", &style[offset],
9655 disasm_options->description[i]);
9659 /* Mark the end of valid options. */
9660 valid_disassembly_styles[num_disassembly_styles] = NULL;
9662 /* Create the help text. */
9663 std::string helptext = string_printf ("%s%s%s",
9664 _("The valid values are:\n"),
9666 _("The default is \"std\"."));
9668 add_setshow_enum_cmd("disassembler", no_class,
9669 valid_disassembly_styles, &disassembly_style,
9670 _("Set the disassembly style."),
9671 _("Show the disassembly style."),
9673 set_disassembly_style_sfunc,
9674 show_disassembly_style_sfunc,
9675 &setarmcmdlist, &showarmcmdlist);
9677 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
9678 _("Set usage of ARM 32-bit mode."),
9679 _("Show usage of ARM 32-bit mode."),
9680 _("When off, a 26-bit PC will be used."),
9682 NULL, /* FIXME: i18n: Usage of ARM 32-bit
9684 &setarmcmdlist, &showarmcmdlist);
9686 /* Add a command to allow the user to force the FPU model. */
9687 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
9688 _("Set the floating point type."),
9689 _("Show the floating point type."),
9690 _("auto - Determine the FP typefrom the OS-ABI.\n\
9691 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9692 fpa - FPA co-processor (GCC compiled).\n\
9693 softvfp - Software FP with pure-endian doubles.\n\
9694 vfp - VFP co-processor."),
9695 set_fp_model_sfunc, show_fp_model,
9696 &setarmcmdlist, &showarmcmdlist);
9698 /* Add a command to allow the user to force the ABI. */
9699 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
9702 NULL, arm_set_abi, arm_show_abi,
9703 &setarmcmdlist, &showarmcmdlist);
9705 /* Add two commands to allow the user to force the assumed
9707 add_setshow_enum_cmd ("fallback-mode", class_support,
9708 arm_mode_strings, &arm_fallback_mode_string,
9709 _("Set the mode assumed when symbols are unavailable."),
9710 _("Show the mode assumed when symbols are unavailable."),
9711 NULL, NULL, arm_show_fallback_mode,
9712 &setarmcmdlist, &showarmcmdlist);
9713 add_setshow_enum_cmd ("force-mode", class_support,
9714 arm_mode_strings, &arm_force_mode_string,
9715 _("Set the mode assumed even when symbols are available."),
9716 _("Show the mode assumed even when symbols are available."),
9717 NULL, NULL, arm_show_force_mode,
9718 &setarmcmdlist, &showarmcmdlist);
9720 /* Debugging flag. */
9721 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
9722 _("Set ARM debugging."),
9723 _("Show ARM debugging."),
9724 _("When on, arm-specific debugging is enabled."),
9726 NULL, /* FIXME: i18n: "ARM debugging is %s. */
9727 &setdebuglist, &showdebuglist);
9730 selftests::register_test (selftests::arm_record_test);
9735 /* ARM-reversible process record data structures. */
9737 #define ARM_INSN_SIZE_BYTES 4
9738 #define THUMB_INSN_SIZE_BYTES 2
9739 #define THUMB2_INSN_SIZE_BYTES 4
9742 /* Position of the bit within a 32-bit ARM instruction
9743 that defines whether the instruction is a load or store. */
9744 #define INSN_S_L_BIT_NUM 20
9746 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9749 unsigned int reg_len = LENGTH; \
9752 REGS = XNEWVEC (uint32_t, reg_len); \
9753 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9758 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9761 unsigned int mem_len = LENGTH; \
9764 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9765 memcpy(&MEMS->len, &RECORD_BUF[0], \
9766 sizeof(struct arm_mem_r) * LENGTH); \
9771 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9772 #define INSN_RECORDED(ARM_RECORD) \
9773 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9775 /* ARM memory record structure. */
9778 uint32_t len; /* Record length. */
9779 uint32_t addr; /* Memory address. */
9782 /* ARM instruction record contains opcode of current insn
9783 and execution state (before entry to decode_insn()),
9784 contains list of to-be-modified registers and
9785 memory blocks (on return from decode_insn()). */
9787 typedef struct insn_decode_record_t
9789 struct gdbarch *gdbarch;
9790 struct regcache *regcache;
9791 CORE_ADDR this_addr; /* Address of the insn being decoded. */
9792 uint32_t arm_insn; /* Should accommodate thumb. */
9793 uint32_t cond; /* Condition code. */
9794 uint32_t opcode; /* Insn opcode. */
9795 uint32_t decode; /* Insn decode bits. */
9796 uint32_t mem_rec_count; /* No of mem records. */
9797 uint32_t reg_rec_count; /* No of reg records. */
9798 uint32_t *arm_regs; /* Registers to be saved for this record. */
9799 struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
9800 } insn_decode_record;
9803 /* Checks ARM SBZ and SBO mandatory fields. */
9806 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
9808 uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
9827 enum arm_record_result
9829 ARM_RECORD_SUCCESS = 0,
9830 ARM_RECORD_FAILURE = 1
9837 } arm_record_strx_t;
9848 arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
9849 uint32_t *record_buf_mem, arm_record_strx_t str_type)
9852 struct regcache *reg_cache = arm_insn_r->regcache;
9853 ULONGEST u_regval[2]= {0};
9855 uint32_t reg_src1 = 0, reg_src2 = 0;
9856 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
9858 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
9859 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
9861 if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
9863 /* 1) Handle misc store, immediate offset. */
9864 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9865 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9866 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9867 regcache_raw_read_unsigned (reg_cache, reg_src1,
9869 if (ARM_PC_REGNUM == reg_src1)
9871 /* If R15 was used as Rn, hence current PC+8. */
9872 u_regval[0] = u_regval[0] + 8;
9874 offset_8 = (immed_high << 4) | immed_low;
9875 /* Calculate target store address. */
9876 if (14 == arm_insn_r->opcode)
9878 tgt_mem_addr = u_regval[0] + offset_8;
9882 tgt_mem_addr = u_regval[0] - offset_8;
9884 if (ARM_RECORD_STRH == str_type)
9886 record_buf_mem[0] = 2;
9887 record_buf_mem[1] = tgt_mem_addr;
9888 arm_insn_r->mem_rec_count = 1;
9890 else if (ARM_RECORD_STRD == str_type)
9892 record_buf_mem[0] = 4;
9893 record_buf_mem[1] = tgt_mem_addr;
9894 record_buf_mem[2] = 4;
9895 record_buf_mem[3] = tgt_mem_addr + 4;
9896 arm_insn_r->mem_rec_count = 2;
9899 else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
9901 /* 2) Store, register offset. */
9903 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9905 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9906 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9907 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9910 /* If R15 was used as Rn, hence current PC+8. */
9911 u_regval[0] = u_regval[0] + 8;
9913 /* Calculate target store address, Rn +/- Rm, register offset. */
9914 if (12 == arm_insn_r->opcode)
9916 tgt_mem_addr = u_regval[0] + u_regval[1];
9920 tgt_mem_addr = u_regval[1] - u_regval[0];
9922 if (ARM_RECORD_STRH == str_type)
9924 record_buf_mem[0] = 2;
9925 record_buf_mem[1] = tgt_mem_addr;
9926 arm_insn_r->mem_rec_count = 1;
9928 else if (ARM_RECORD_STRD == str_type)
9930 record_buf_mem[0] = 4;
9931 record_buf_mem[1] = tgt_mem_addr;
9932 record_buf_mem[2] = 4;
9933 record_buf_mem[3] = tgt_mem_addr + 4;
9934 arm_insn_r->mem_rec_count = 2;
9937 else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
9938 || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9940 /* 3) Store, immediate pre-indexed. */
9941 /* 5) Store, immediate post-indexed. */
9942 immed_low = bits (arm_insn_r->arm_insn, 0, 3);
9943 immed_high = bits (arm_insn_r->arm_insn, 8, 11);
9944 offset_8 = (immed_high << 4) | immed_low;
9945 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
9946 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9947 /* Calculate target store address, Rn +/- Rm, register offset. */
9948 if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
9950 tgt_mem_addr = u_regval[0] + offset_8;
9954 tgt_mem_addr = u_regval[0] - offset_8;
9956 if (ARM_RECORD_STRH == str_type)
9958 record_buf_mem[0] = 2;
9959 record_buf_mem[1] = tgt_mem_addr;
9960 arm_insn_r->mem_rec_count = 1;
9962 else if (ARM_RECORD_STRD == str_type)
9964 record_buf_mem[0] = 4;
9965 record_buf_mem[1] = tgt_mem_addr;
9966 record_buf_mem[2] = 4;
9967 record_buf_mem[3] = tgt_mem_addr + 4;
9968 arm_insn_r->mem_rec_count = 2;
9970 /* Record Rn also as it changes. */
9971 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
9972 arm_insn_r->reg_rec_count = 1;
9974 else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
9975 || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9977 /* 4) Store, register pre-indexed. */
9978 /* 6) Store, register post -indexed. */
9979 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
9980 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
9981 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
9982 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
9983 /* Calculate target store address, Rn +/- Rm, register offset. */
9984 if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
9986 tgt_mem_addr = u_regval[0] + u_regval[1];
9990 tgt_mem_addr = u_regval[1] - u_regval[0];
9992 if (ARM_RECORD_STRH == str_type)
9994 record_buf_mem[0] = 2;
9995 record_buf_mem[1] = tgt_mem_addr;
9996 arm_insn_r->mem_rec_count = 1;
9998 else if (ARM_RECORD_STRD == str_type)
10000 record_buf_mem[0] = 4;
10001 record_buf_mem[1] = tgt_mem_addr;
10002 record_buf_mem[2] = 4;
10003 record_buf_mem[3] = tgt_mem_addr + 4;
10004 arm_insn_r->mem_rec_count = 2;
10006 /* Record Rn also as it changes. */
10007 *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
10008 arm_insn_r->reg_rec_count = 1;
10013 /* Handling ARM extension space insns. */
10016 arm_record_extension_space (insn_decode_record *arm_insn_r)
10018 uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
10019 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10020 uint32_t record_buf[8], record_buf_mem[8];
10021 uint32_t reg_src1 = 0;
10022 struct regcache *reg_cache = arm_insn_r->regcache;
10023 ULONGEST u_regval = 0;
10025 gdb_assert (!INSN_RECORDED(arm_insn_r));
10026 /* Handle unconditional insn extension space. */
10028 opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
10029 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10030 if (arm_insn_r->cond)
10032 /* PLD has no affect on architectural state, it just affects
10034 if (5 == ((opcode1 & 0xE0) >> 5))
10037 record_buf[0] = ARM_PS_REGNUM;
10038 record_buf[1] = ARM_LR_REGNUM;
10039 arm_insn_r->reg_rec_count = 2;
10041 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10045 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10046 if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
10049 /* Undefined instruction on ARM V5; need to handle if later
10050 versions define it. */
10053 opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
10054 opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
10055 insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
10057 /* Handle arithmetic insn extension space. */
10058 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
10059 && !INSN_RECORDED(arm_insn_r))
10061 /* Handle MLA(S) and MUL(S). */
10062 if (0 <= insn_op1 && 3 >= insn_op1)
10064 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10065 record_buf[1] = ARM_PS_REGNUM;
10066 arm_insn_r->reg_rec_count = 2;
10068 else if (4 <= insn_op1 && 15 >= insn_op1)
10070 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10071 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10072 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10073 record_buf[2] = ARM_PS_REGNUM;
10074 arm_insn_r->reg_rec_count = 3;
10078 opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
10079 opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
10080 insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
10082 /* Handle control insn extension space. */
10084 if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
10085 && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
10087 if (!bit (arm_insn_r->arm_insn,25))
10089 if (!bits (arm_insn_r->arm_insn, 4, 7))
10091 if ((0 == insn_op1) || (2 == insn_op1))
10094 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10095 arm_insn_r->reg_rec_count = 1;
10097 else if (1 == insn_op1)
10099 /* CSPR is going to be changed. */
10100 record_buf[0] = ARM_PS_REGNUM;
10101 arm_insn_r->reg_rec_count = 1;
10103 else if (3 == insn_op1)
10105 /* SPSR is going to be changed. */
10106 /* We need to get SPSR value, which is yet to be done. */
10110 else if (1 == bits (arm_insn_r->arm_insn, 4, 7))
10115 record_buf[0] = ARM_PS_REGNUM;
10116 arm_insn_r->reg_rec_count = 1;
10118 else if (3 == insn_op1)
10121 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10122 arm_insn_r->reg_rec_count = 1;
10125 else if (3 == bits (arm_insn_r->arm_insn, 4, 7))
10128 record_buf[0] = ARM_PS_REGNUM;
10129 record_buf[1] = ARM_LR_REGNUM;
10130 arm_insn_r->reg_rec_count = 2;
10132 else if (5 == bits (arm_insn_r->arm_insn, 4, 7))
10134 /* QADD, QSUB, QDADD, QDSUB */
10135 record_buf[0] = ARM_PS_REGNUM;
10136 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10137 arm_insn_r->reg_rec_count = 2;
10139 else if (7 == bits (arm_insn_r->arm_insn, 4, 7))
10142 record_buf[0] = ARM_PS_REGNUM;
10143 record_buf[1] = ARM_LR_REGNUM;
10144 arm_insn_r->reg_rec_count = 2;
10146 /* Save SPSR also;how? */
10149 else if(8 == bits (arm_insn_r->arm_insn, 4, 7)
10150 || 10 == bits (arm_insn_r->arm_insn, 4, 7)
10151 || 12 == bits (arm_insn_r->arm_insn, 4, 7)
10152 || 14 == bits (arm_insn_r->arm_insn, 4, 7)
10155 if (0 == insn_op1 || 1 == insn_op1)
10157 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10158 /* We dont do optimization for SMULW<y> where we
10160 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10161 record_buf[1] = ARM_PS_REGNUM;
10162 arm_insn_r->reg_rec_count = 2;
10164 else if (2 == insn_op1)
10167 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10168 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
10169 arm_insn_r->reg_rec_count = 2;
10171 else if (3 == insn_op1)
10174 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10175 arm_insn_r->reg_rec_count = 1;
10181 /* MSR : immediate form. */
10184 /* CSPR is going to be changed. */
10185 record_buf[0] = ARM_PS_REGNUM;
10186 arm_insn_r->reg_rec_count = 1;
10188 else if (3 == insn_op1)
10190 /* SPSR is going to be changed. */
10191 /* we need to get SPSR value, which is yet to be done */
10197 opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
10198 opcode2 = bits (arm_insn_r->arm_insn, 20, 24);
10199 insn_op1 = bits (arm_insn_r->arm_insn, 5, 6);
10201 /* Handle load/store insn extension space. */
10203 if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
10204 && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond
10205 && !INSN_RECORDED(arm_insn_r))
10210 /* These insn, changes register and memory as well. */
10211 /* SWP or SWPB insn. */
10212 /* Get memory address given by Rn. */
10213 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10214 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
10215 /* SWP insn ?, swaps word. */
10216 if (8 == arm_insn_r->opcode)
10218 record_buf_mem[0] = 4;
10222 /* SWPB insn, swaps only byte. */
10223 record_buf_mem[0] = 1;
10225 record_buf_mem[1] = u_regval;
10226 arm_insn_r->mem_rec_count = 1;
10227 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10228 arm_insn_r->reg_rec_count = 1;
10230 else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10233 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10236 else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10239 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10240 record_buf[1] = record_buf[0] + 1;
10241 arm_insn_r->reg_rec_count = 2;
10243 else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20))
10246 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10249 else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3)
10251 /* LDRH, LDRSB, LDRSH. */
10252 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10253 arm_insn_r->reg_rec_count = 1;
10258 opcode1 = bits (arm_insn_r->arm_insn, 23, 27);
10259 if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21)
10260 && !INSN_RECORDED(arm_insn_r))
10263 /* Handle coprocessor insn extension space. */
10266 /* To be done for ARMv5 and later; as of now we return -1. */
10270 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10271 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10276 /* Handling opcode 000 insns. */
10279 arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
10281 struct regcache *reg_cache = arm_insn_r->regcache;
10282 uint32_t record_buf[8], record_buf_mem[8];
10283 ULONGEST u_regval[2] = {0};
10285 uint32_t reg_src1 = 0, reg_dest = 0;
10286 uint32_t opcode1 = 0;
10288 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10289 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10290 opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
10292 /* Data processing insn /multiply insn. */
10293 if (9 == arm_insn_r->decode
10294 && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10295 || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
10297 /* Handle multiply instructions. */
10298 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10299 if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
10301 /* Handle MLA and MUL. */
10302 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10303 record_buf[1] = ARM_PS_REGNUM;
10304 arm_insn_r->reg_rec_count = 2;
10306 else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
10308 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10309 record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
10310 record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
10311 record_buf[2] = ARM_PS_REGNUM;
10312 arm_insn_r->reg_rec_count = 3;
10315 else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10316 && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
10318 /* Handle misc load insns, as 20th bit (L = 1). */
10319 /* LDR insn has a capability to do branching, if
10320 MOV LR, PC is precceded by LDR insn having Rn as R15
10321 in that case, it emulates branch and link insn, and hence we
10322 need to save CSPR and PC as well. I am not sure this is right
10323 place; as opcode = 010 LDR insn make this happen, if R15 was
10325 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10326 if (15 != reg_dest)
10328 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10329 arm_insn_r->reg_rec_count = 1;
10333 record_buf[0] = reg_dest;
10334 record_buf[1] = ARM_PS_REGNUM;
10335 arm_insn_r->reg_rec_count = 2;
10338 else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10339 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
10340 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10341 && 2 == bits (arm_insn_r->arm_insn, 20, 21))
10343 /* Handle MSR insn. */
10344 if (9 == arm_insn_r->opcode)
10346 /* CSPR is going to be changed. */
10347 record_buf[0] = ARM_PS_REGNUM;
10348 arm_insn_r->reg_rec_count = 1;
10352 /* SPSR is going to be changed. */
10353 /* How to read SPSR value? */
10357 else if (9 == arm_insn_r->decode
10358 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10359 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10361 /* Handling SWP, SWPB. */
10362 /* These insn, changes register and memory as well. */
10363 /* SWP or SWPB insn. */
10365 reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
10366 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10367 /* SWP insn ?, swaps word. */
10368 if (8 == arm_insn_r->opcode)
10370 record_buf_mem[0] = 4;
10374 /* SWPB insn, swaps only byte. */
10375 record_buf_mem[0] = 1;
10377 record_buf_mem[1] = u_regval[0];
10378 arm_insn_r->mem_rec_count = 1;
10379 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10380 arm_insn_r->reg_rec_count = 1;
10382 else if (3 == arm_insn_r->decode && 0x12 == opcode1
10383 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10385 /* Handle BLX, branch and link/exchange. */
10386 if (9 == arm_insn_r->opcode)
10388 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10389 and R14 stores the return address. */
10390 record_buf[0] = ARM_PS_REGNUM;
10391 record_buf[1] = ARM_LR_REGNUM;
10392 arm_insn_r->reg_rec_count = 2;
10395 else if (7 == arm_insn_r->decode && 0x12 == opcode1)
10397 /* Handle enhanced software breakpoint insn, BKPT. */
10398 /* CPSR is changed to be executed in ARM state, disabling normal
10399 interrupts, entering abort mode. */
10400 /* According to high vector configuration PC is set. */
10401 /* user hit breakpoint and type reverse, in
10402 that case, we need to go back with previous CPSR and
10403 Program Counter. */
10404 record_buf[0] = ARM_PS_REGNUM;
10405 record_buf[1] = ARM_LR_REGNUM;
10406 arm_insn_r->reg_rec_count = 2;
10408 /* Save SPSR also; how? */
10411 else if (11 == arm_insn_r->decode
10412 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10414 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10416 /* Handle str(x) insn */
10417 arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
10420 else if (1 == arm_insn_r->decode && 0x12 == opcode1
10421 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
10423 /* Handle BX, branch and link/exchange. */
10424 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10425 record_buf[0] = ARM_PS_REGNUM;
10426 arm_insn_r->reg_rec_count = 1;
10428 else if (1 == arm_insn_r->decode && 0x16 == opcode1
10429 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
10430 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
10432 /* Count leading zeros: CLZ. */
10433 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10434 arm_insn_r->reg_rec_count = 1;
10436 else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
10437 && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
10438 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
10439 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
10442 /* Handle MRS insn. */
10443 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10444 arm_insn_r->reg_rec_count = 1;
10446 else if (arm_insn_r->opcode <= 15)
10448 /* Normal data processing insns. */
10449 /* Out of 11 shifter operands mode, all the insn modifies destination
10450 register, which is specified by 13-16 decode. */
10451 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10452 record_buf[1] = ARM_PS_REGNUM;
10453 arm_insn_r->reg_rec_count = 2;
10460 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10461 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10465 /* Handling opcode 001 insns. */
10468 arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
10470 uint32_t record_buf[8], record_buf_mem[8];
10472 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10473 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10475 if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
10476 && 2 == bits (arm_insn_r->arm_insn, 20, 21)
10477 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
10480 /* Handle MSR insn. */
10481 if (9 == arm_insn_r->opcode)
10483 /* CSPR is going to be changed. */
10484 record_buf[0] = ARM_PS_REGNUM;
10485 arm_insn_r->reg_rec_count = 1;
10489 /* SPSR is going to be changed. */
10492 else if (arm_insn_r->opcode <= 15)
10494 /* Normal data processing insns. */
10495 /* Out of 11 shifter operands mode, all the insn modifies destination
10496 register, which is specified by 13-16 decode. */
10497 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10498 record_buf[1] = ARM_PS_REGNUM;
10499 arm_insn_r->reg_rec_count = 2;
10506 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10507 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10512 arm_record_media (insn_decode_record *arm_insn_r)
10514 uint32_t record_buf[8];
10516 switch (bits (arm_insn_r->arm_insn, 22, 24))
10519 /* Parallel addition and subtraction, signed */
10521 /* Parallel addition and subtraction, unsigned */
10524 /* Packing, unpacking, saturation and reversal */
10526 int rd = bits (arm_insn_r->arm_insn, 12, 15);
10528 record_buf[arm_insn_r->reg_rec_count++] = rd;
10534 /* Signed multiplies */
10536 int rd = bits (arm_insn_r->arm_insn, 16, 19);
10537 unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22);
10539 record_buf[arm_insn_r->reg_rec_count++] = rd;
10541 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10542 else if (op1 == 0x4)
10543 record_buf[arm_insn_r->reg_rec_count++]
10544 = bits (arm_insn_r->arm_insn, 12, 15);
10550 if (bit (arm_insn_r->arm_insn, 21)
10551 && bits (arm_insn_r->arm_insn, 5, 6) == 0x2)
10554 record_buf[arm_insn_r->reg_rec_count++]
10555 = bits (arm_insn_r->arm_insn, 12, 15);
10557 else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0
10558 && bits (arm_insn_r->arm_insn, 5, 7) == 0x0)
10560 /* USAD8 and USADA8 */
10561 record_buf[arm_insn_r->reg_rec_count++]
10562 = bits (arm_insn_r->arm_insn, 16, 19);
10569 if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3
10570 && bits (arm_insn_r->arm_insn, 5, 7) == 0x7)
10572 /* Permanently UNDEFINED */
10577 /* BFC, BFI and UBFX */
10578 record_buf[arm_insn_r->reg_rec_count++]
10579 = bits (arm_insn_r->arm_insn, 12, 15);
10588 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10593 /* Handle ARM mode instructions with opcode 010. */
10596 arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
10598 struct regcache *reg_cache = arm_insn_r->regcache;
10600 uint32_t reg_base , reg_dest;
10601 uint32_t offset_12, tgt_mem_addr;
10602 uint32_t record_buf[8], record_buf_mem[8];
10603 unsigned char wback;
10606 /* Calculate wback. */
10607 wback = (bit (arm_insn_r->arm_insn, 24) == 0)
10608 || (bit (arm_insn_r->arm_insn, 21) == 1);
10610 arm_insn_r->reg_rec_count = 0;
10611 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10613 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10615 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10618 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10619 record_buf[arm_insn_r->reg_rec_count++] = reg_dest;
10621 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10622 preceeds a LDR instruction having R15 as reg_base, it
10623 emulates a branch and link instruction, and hence we need to save
10624 CPSR and PC as well. */
10625 if (ARM_PC_REGNUM == reg_dest)
10626 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10628 /* If wback is true, also save the base register, which is going to be
10631 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10635 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10637 offset_12 = bits (arm_insn_r->arm_insn, 0, 11);
10638 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
10640 /* Handle bit U. */
10641 if (bit (arm_insn_r->arm_insn, 23))
10643 /* U == 1: Add the offset. */
10644 tgt_mem_addr = (uint32_t) u_regval + offset_12;
10648 /* U == 0: subtract the offset. */
10649 tgt_mem_addr = (uint32_t) u_regval - offset_12;
10652 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10654 if (bit (arm_insn_r->arm_insn, 22))
10656 /* STRB and STRBT: 1 byte. */
10657 record_buf_mem[0] = 1;
10661 /* STR and STRT: 4 bytes. */
10662 record_buf_mem[0] = 4;
10665 /* Handle bit P. */
10666 if (bit (arm_insn_r->arm_insn, 24))
10667 record_buf_mem[1] = tgt_mem_addr;
10669 record_buf_mem[1] = (uint32_t) u_regval;
10671 arm_insn_r->mem_rec_count = 1;
10673 /* If wback is true, also save the base register, which is going to be
10676 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10679 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10680 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10684 /* Handling opcode 011 insns. */
10687 arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
10689 struct regcache *reg_cache = arm_insn_r->regcache;
10691 uint32_t shift_imm = 0;
10692 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
10693 uint32_t offset_12 = 0, tgt_mem_addr = 0;
10694 uint32_t record_buf[8], record_buf_mem[8];
10697 ULONGEST u_regval[2];
10699 if (bit (arm_insn_r->arm_insn, 4))
10700 return arm_record_media (arm_insn_r);
10702 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
10703 arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
10705 /* Handle enhanced store insns and LDRD DSP insn,
10706 order begins according to addressing modes for store insns
10710 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10712 reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
10713 /* LDR insn has a capability to do branching, if
10714 MOV LR, PC is precedded by LDR insn having Rn as R15
10715 in that case, it emulates branch and link insn, and hence we
10716 need to save CSPR and PC as well. */
10717 if (15 != reg_dest)
10719 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
10720 arm_insn_r->reg_rec_count = 1;
10724 record_buf[0] = reg_dest;
10725 record_buf[1] = ARM_PS_REGNUM;
10726 arm_insn_r->reg_rec_count = 2;
10731 if (! bits (arm_insn_r->arm_insn, 4, 11))
10733 /* Store insn, register offset and register pre-indexed,
10734 register post-indexed. */
10736 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10738 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10739 regcache_raw_read_unsigned (reg_cache, reg_src1
10741 regcache_raw_read_unsigned (reg_cache, reg_src2
10743 if (15 == reg_src2)
10745 /* If R15 was used as Rn, hence current PC+8. */
10746 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10747 u_regval[0] = u_regval[0] + 8;
10749 /* Calculate target store address, Rn +/- Rm, register offset. */
10751 if (bit (arm_insn_r->arm_insn, 23))
10753 tgt_mem_addr = u_regval[0] + u_regval[1];
10757 tgt_mem_addr = u_regval[1] - u_regval[0];
10760 switch (arm_insn_r->opcode)
10774 record_buf_mem[0] = 4;
10789 record_buf_mem[0] = 1;
10793 gdb_assert_not_reached ("no decoding pattern found");
10796 record_buf_mem[1] = tgt_mem_addr;
10797 arm_insn_r->mem_rec_count = 1;
10799 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10800 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10801 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10802 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10803 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10804 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10807 /* Rn is going to be changed in pre-indexed mode and
10808 post-indexed mode as well. */
10809 record_buf[0] = reg_src2;
10810 arm_insn_r->reg_rec_count = 1;
10815 /* Store insn, scaled register offset; scaled pre-indexed. */
10816 offset_12 = bits (arm_insn_r->arm_insn, 5, 6);
10818 reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
10820 reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
10821 /* Get shift_imm. */
10822 shift_imm = bits (arm_insn_r->arm_insn, 7, 11);
10823 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
10824 regcache_raw_read_signed (reg_cache, reg_src1, &s_word);
10825 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10826 /* Offset_12 used as shift. */
10830 /* Offset_12 used as index. */
10831 offset_12 = u_regval[0] << shift_imm;
10835 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
10841 if (bit (u_regval[0], 31))
10843 offset_12 = 0xFFFFFFFF;
10852 /* This is arithmetic shift. */
10853 offset_12 = s_word >> shift_imm;
10860 regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM,
10862 /* Get C flag value and shift it by 31. */
10863 offset_12 = (((bit (u_regval[1], 29)) << 31) \
10864 | (u_regval[0]) >> 1);
10868 offset_12 = (u_regval[0] >> shift_imm) \
10870 (sizeof(uint32_t) - shift_imm));
10875 gdb_assert_not_reached ("no decoding pattern found");
10879 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
10881 if (bit (arm_insn_r->arm_insn, 23))
10883 tgt_mem_addr = u_regval[1] + offset_12;
10887 tgt_mem_addr = u_regval[1] - offset_12;
10890 switch (arm_insn_r->opcode)
10904 record_buf_mem[0] = 4;
10919 record_buf_mem[0] = 1;
10923 gdb_assert_not_reached ("no decoding pattern found");
10926 record_buf_mem[1] = tgt_mem_addr;
10927 arm_insn_r->mem_rec_count = 1;
10929 if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode
10930 || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
10931 || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode
10932 || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode
10933 || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode
10934 || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode
10937 /* Rn is going to be changed in register scaled pre-indexed
10938 mode,and scaled post indexed mode. */
10939 record_buf[0] = reg_src2;
10940 arm_insn_r->reg_rec_count = 1;
10945 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
10946 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
10950 /* Handle ARM mode instructions with opcode 100. */
10953 arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
10955 struct regcache *reg_cache = arm_insn_r->regcache;
10956 uint32_t register_count = 0, register_bits;
10957 uint32_t reg_base, addr_mode;
10958 uint32_t record_buf[24], record_buf_mem[48];
10962 /* Fetch the list of registers. */
10963 register_bits = bits (arm_insn_r->arm_insn, 0, 15);
10964 arm_insn_r->reg_rec_count = 0;
10966 /* Fetch the base register that contains the address we are loading data
10968 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
10970 /* Calculate wback. */
10971 wback = (bit (arm_insn_r->arm_insn, 21) == 1);
10973 if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
10975 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10977 /* Find out which registers are going to be loaded from memory. */
10978 while (register_bits)
10980 if (register_bits & 0x00000001)
10981 record_buf[arm_insn_r->reg_rec_count++] = register_count;
10982 register_bits = register_bits >> 1;
10987 /* If wback is true, also save the base register, which is going to be
10990 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
10992 /* Save the CPSR register. */
10993 record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
10997 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10999 addr_mode = bits (arm_insn_r->arm_insn, 23, 24);
11001 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
11003 /* Find out how many registers are going to be stored to memory. */
11004 while (register_bits)
11006 if (register_bits & 0x00000001)
11008 register_bits = register_bits >> 1;
11013 /* STMDA (STMED): Decrement after. */
11015 record_buf_mem[1] = (uint32_t) u_regval
11016 - register_count * INT_REGISTER_SIZE + 4;
11018 /* STM (STMIA, STMEA): Increment after. */
11020 record_buf_mem[1] = (uint32_t) u_regval;
11022 /* STMDB (STMFD): Decrement before. */
11024 record_buf_mem[1] = (uint32_t) u_regval
11025 - register_count * INT_REGISTER_SIZE;
11027 /* STMIB (STMFA): Increment before. */
11029 record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
11032 gdb_assert_not_reached ("no decoding pattern found");
11036 record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
11037 arm_insn_r->mem_rec_count = 1;
11039 /* If wback is true, also save the base register, which is going to be
11042 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
11045 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11046 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11050 /* Handling opcode 101 insns. */
11053 arm_record_b_bl (insn_decode_record *arm_insn_r)
11055 uint32_t record_buf[8];
11057 /* Handle B, BL, BLX(1) insns. */
11058 /* B simply branches so we do nothing here. */
11059 /* Note: BLX(1) doesnt fall here but instead it falls into
11060 extension space. */
11061 if (bit (arm_insn_r->arm_insn, 24))
11063 record_buf[0] = ARM_LR_REGNUM;
11064 arm_insn_r->reg_rec_count = 1;
11067 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11073 arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
11075 printf_unfiltered (_("Process record does not support instruction "
11076 "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
11077 paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
11082 /* Record handler for vector data transfer instructions. */
11085 arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
11087 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
11088 uint32_t record_buf[4];
11090 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
11091 reg_v = bits (arm_insn_r->arm_insn, 21, 23);
11092 bits_a = bits (arm_insn_r->arm_insn, 21, 23);
11093 bit_l = bit (arm_insn_r->arm_insn, 20);
11094 bit_c = bit (arm_insn_r->arm_insn, 8);
11096 /* Handle VMOV instruction. */
11097 if (bit_l && bit_c)
11099 record_buf[0] = reg_t;
11100 arm_insn_r->reg_rec_count = 1;
11102 else if (bit_l && !bit_c)
11104 /* Handle VMOV instruction. */
11105 if (bits_a == 0x00)
11107 record_buf[0] = reg_t;
11108 arm_insn_r->reg_rec_count = 1;
11110 /* Handle VMRS instruction. */
11111 else if (bits_a == 0x07)
11114 reg_t = ARM_PS_REGNUM;
11116 record_buf[0] = reg_t;
11117 arm_insn_r->reg_rec_count = 1;
11120 else if (!bit_l && !bit_c)
11122 /* Handle VMOV instruction. */
11123 if (bits_a == 0x00)
11125 record_buf[0] = ARM_D0_REGNUM + reg_v;
11127 arm_insn_r->reg_rec_count = 1;
11129 /* Handle VMSR instruction. */
11130 else if (bits_a == 0x07)
11132 record_buf[0] = ARM_FPSCR_REGNUM;
11133 arm_insn_r->reg_rec_count = 1;
11136 else if (!bit_l && bit_c)
11138 /* Handle VMOV instruction. */
11139 if (!(bits_a & 0x04))
11141 record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
11143 arm_insn_r->reg_rec_count = 1;
11145 /* Handle VDUP instruction. */
11148 if (bit (arm_insn_r->arm_insn, 21))
11150 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
11151 record_buf[0] = reg_v + ARM_D0_REGNUM;
11152 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
11153 arm_insn_r->reg_rec_count = 2;
11157 reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
11158 record_buf[0] = reg_v + ARM_D0_REGNUM;
11159 arm_insn_r->reg_rec_count = 1;
11164 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11168 /* Record handler for extension register load/store instructions. */
11171 arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
11173 uint32_t opcode, single_reg;
11174 uint8_t op_vldm_vstm;
11175 uint32_t record_buf[8], record_buf_mem[128];
11176 ULONGEST u_regval = 0;
11178 struct regcache *reg_cache = arm_insn_r->regcache;
11180 opcode = bits (arm_insn_r->arm_insn, 20, 24);
11181 single_reg = !bit (arm_insn_r->arm_insn, 8);
11182 op_vldm_vstm = opcode & 0x1b;
11184 /* Handle VMOV instructions. */
11185 if ((opcode & 0x1e) == 0x04)
11187 if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */
11189 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11190 record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19);
11191 arm_insn_r->reg_rec_count = 2;
11195 uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3);
11196 uint8_t bit_m = bit (arm_insn_r->arm_insn, 5);
11200 /* The first S register number m is REG_M:M (M is bit 5),
11201 the corresponding D register number is REG_M:M / 2, which
11203 record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m;
11204 /* The second S register number is REG_M:M + 1, the
11205 corresponding D register number is (REG_M:M + 1) / 2.
11206 IOW, if bit M is 1, the first and second S registers
11207 are mapped to different D registers, otherwise, they are
11208 in the same D register. */
11211 record_buf[arm_insn_r->reg_rec_count++]
11212 = ARM_D0_REGNUM + reg_m + 1;
11217 record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM);
11218 arm_insn_r->reg_rec_count = 1;
11222 /* Handle VSTM and VPUSH instructions. */
11223 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
11224 || op_vldm_vstm == 0x12)
11226 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
11227 uint32_t memory_index = 0;
11229 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11230 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11231 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11232 imm_off32 = imm_off8 << 2;
11233 memory_count = imm_off8;
11235 if (bit (arm_insn_r->arm_insn, 23))
11236 start_address = u_regval;
11238 start_address = u_regval - imm_off32;
11240 if (bit (arm_insn_r->arm_insn, 21))
11242 record_buf[0] = reg_rn;
11243 arm_insn_r->reg_rec_count = 1;
11246 while (memory_count > 0)
11250 record_buf_mem[memory_index] = 4;
11251 record_buf_mem[memory_index + 1] = start_address;
11252 start_address = start_address + 4;
11253 memory_index = memory_index + 2;
11257 record_buf_mem[memory_index] = 4;
11258 record_buf_mem[memory_index + 1] = start_address;
11259 record_buf_mem[memory_index + 2] = 4;
11260 record_buf_mem[memory_index + 3] = start_address + 4;
11261 start_address = start_address + 8;
11262 memory_index = memory_index + 4;
11266 arm_insn_r->mem_rec_count = (memory_index >> 1);
11268 /* Handle VLDM instructions. */
11269 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
11270 || op_vldm_vstm == 0x13)
11272 uint32_t reg_count, reg_vd;
11273 uint32_t reg_index = 0;
11274 uint32_t bit_d = bit (arm_insn_r->arm_insn, 22);
11276 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11277 reg_count = bits (arm_insn_r->arm_insn, 0, 7);
11279 /* REG_VD is the first D register number. If the instruction
11280 loads memory to S registers (SINGLE_REG is TRUE), the register
11281 number is (REG_VD << 1 | bit D), so the corresponding D
11282 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11284 reg_vd = reg_vd | (bit_d << 4);
11286 if (bit (arm_insn_r->arm_insn, 21) /* write back */)
11287 record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19);
11289 /* If the instruction loads memory to D register, REG_COUNT should
11290 be divided by 2, according to the ARM Architecture Reference
11291 Manual. If the instruction loads memory to S register, divide by
11292 2 as well because two S registers are mapped to D register. */
11293 reg_count = reg_count / 2;
11294 if (single_reg && bit_d)
11296 /* Increase the register count if S register list starts from
11297 an odd number (bit d is one). */
11301 while (reg_count > 0)
11303 record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
11306 arm_insn_r->reg_rec_count = reg_index;
11308 /* VSTR Vector store register. */
11309 else if ((opcode & 0x13) == 0x10)
11311 uint32_t start_address, reg_rn, imm_off32, imm_off8;
11312 uint32_t memory_index = 0;
11314 reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
11315 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
11316 imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
11317 imm_off32 = imm_off8 << 2;
11319 if (bit (arm_insn_r->arm_insn, 23))
11320 start_address = u_regval + imm_off32;
11322 start_address = u_regval - imm_off32;
11326 record_buf_mem[memory_index] = 4;
11327 record_buf_mem[memory_index + 1] = start_address;
11328 arm_insn_r->mem_rec_count = 1;
11332 record_buf_mem[memory_index] = 4;
11333 record_buf_mem[memory_index + 1] = start_address;
11334 record_buf_mem[memory_index + 2] = 4;
11335 record_buf_mem[memory_index + 3] = start_address + 4;
11336 arm_insn_r->mem_rec_count = 2;
11339 /* VLDR Vector load register. */
11340 else if ((opcode & 0x13) == 0x11)
11342 uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11346 reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
11347 record_buf[0] = ARM_D0_REGNUM + reg_vd;
11351 reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
11352 /* Record register D rather than pseudo register S. */
11353 record_buf[0] = ARM_D0_REGNUM + reg_vd / 2;
11355 arm_insn_r->reg_rec_count = 1;
11358 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11359 MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem);
11363 /* Record handler for arm/thumb mode VFP data processing instructions. */
11366 arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
11368 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
11369 uint32_t record_buf[4];
11370 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
11371 enum insn_types curr_insn_type = INSN_INV;
11373 reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
11374 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
11375 opc2 = bits (arm_insn_r->arm_insn, 16, 19);
11376 opc3 = bits (arm_insn_r->arm_insn, 6, 7);
11377 dp_op_sz = bit (arm_insn_r->arm_insn, 8);
11378 bit_d = bit (arm_insn_r->arm_insn, 22);
11379 opc1 = opc1 & 0x04;
11381 /* Handle VMLA, VMLS. */
11384 if (bit (arm_insn_r->arm_insn, 10))
11386 if (bit (arm_insn_r->arm_insn, 6))
11387 curr_insn_type = INSN_T0;
11389 curr_insn_type = INSN_T1;
11394 curr_insn_type = INSN_T1;
11396 curr_insn_type = INSN_T2;
11399 /* Handle VNMLA, VNMLS, VNMUL. */
11400 else if (opc1 == 0x01)
11403 curr_insn_type = INSN_T1;
11405 curr_insn_type = INSN_T2;
11408 else if (opc1 == 0x02 && !(opc3 & 0x01))
11410 if (bit (arm_insn_r->arm_insn, 10))
11412 if (bit (arm_insn_r->arm_insn, 6))
11413 curr_insn_type = INSN_T0;
11415 curr_insn_type = INSN_T1;
11420 curr_insn_type = INSN_T1;
11422 curr_insn_type = INSN_T2;
11425 /* Handle VADD, VSUB. */
11426 else if (opc1 == 0x03)
11428 if (!bit (arm_insn_r->arm_insn, 9))
11430 if (bit (arm_insn_r->arm_insn, 6))
11431 curr_insn_type = INSN_T0;
11433 curr_insn_type = INSN_T1;
11438 curr_insn_type = INSN_T1;
11440 curr_insn_type = INSN_T2;
11444 else if (opc1 == 0x0b)
11447 curr_insn_type = INSN_T1;
11449 curr_insn_type = INSN_T2;
11451 /* Handle all other vfp data processing instructions. */
11452 else if (opc1 == 0x0b)
11455 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
11457 if (bit (arm_insn_r->arm_insn, 4))
11459 if (bit (arm_insn_r->arm_insn, 6))
11460 curr_insn_type = INSN_T0;
11462 curr_insn_type = INSN_T1;
11467 curr_insn_type = INSN_T1;
11469 curr_insn_type = INSN_T2;
11472 /* Handle VNEG and VABS. */
11473 else if ((opc2 == 0x01 && opc3 == 0x01)
11474 || (opc2 == 0x00 && opc3 == 0x03))
11476 if (!bit (arm_insn_r->arm_insn, 11))
11478 if (bit (arm_insn_r->arm_insn, 6))
11479 curr_insn_type = INSN_T0;
11481 curr_insn_type = INSN_T1;
11486 curr_insn_type = INSN_T1;
11488 curr_insn_type = INSN_T2;
11491 /* Handle VSQRT. */
11492 else if (opc2 == 0x01 && opc3 == 0x03)
11495 curr_insn_type = INSN_T1;
11497 curr_insn_type = INSN_T2;
11500 else if (opc2 == 0x07 && opc3 == 0x03)
11503 curr_insn_type = INSN_T1;
11505 curr_insn_type = INSN_T2;
11507 else if (opc3 & 0x01)
11510 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
11512 if (!bit (arm_insn_r->arm_insn, 18))
11513 curr_insn_type = INSN_T2;
11517 curr_insn_type = INSN_T1;
11519 curr_insn_type = INSN_T2;
11523 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
11526 curr_insn_type = INSN_T1;
11528 curr_insn_type = INSN_T2;
11530 /* Handle VCVTB, VCVTT. */
11531 else if ((opc2 & 0x0e) == 0x02)
11532 curr_insn_type = INSN_T2;
11533 /* Handle VCMP, VCMPE. */
11534 else if ((opc2 & 0x0e) == 0x04)
11535 curr_insn_type = INSN_T3;
11539 switch (curr_insn_type)
11542 reg_vd = reg_vd | (bit_d << 4);
11543 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11544 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
11545 arm_insn_r->reg_rec_count = 2;
11549 reg_vd = reg_vd | (bit_d << 4);
11550 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11551 arm_insn_r->reg_rec_count = 1;
11555 reg_vd = (reg_vd << 1) | bit_d;
11556 record_buf[0] = reg_vd + ARM_D0_REGNUM;
11557 arm_insn_r->reg_rec_count = 1;
11561 record_buf[0] = ARM_FPSCR_REGNUM;
11562 arm_insn_r->reg_rec_count = 1;
11566 gdb_assert_not_reached ("no decoding pattern found");
11570 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
11574 /* Handling opcode 110 insns. */
11577 arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
11579 uint32_t op1, op1_ebit, coproc;
11581 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11582 op1 = bits (arm_insn_r->arm_insn, 20, 25);
11583 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11585 if ((coproc & 0x0e) == 0x0a)
11587 /* Handle extension register ld/st instructions. */
11589 return arm_record_exreg_ld_st_insn (arm_insn_r);
11591 /* 64-bit transfers between arm core and extension registers. */
11592 if ((op1 & 0x3e) == 0x04)
11593 return arm_record_exreg_ld_st_insn (arm_insn_r);
11597 /* Handle coprocessor ld/st instructions. */
11602 return arm_record_unsupported_insn (arm_insn_r);
11605 return arm_record_unsupported_insn (arm_insn_r);
11608 /* Move to coprocessor from two arm core registers. */
11610 return arm_record_unsupported_insn (arm_insn_r);
11612 /* Move to two arm core registers from coprocessor. */
11617 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
11618 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19);
11619 arm_insn_r->reg_rec_count = 2;
11621 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t);
11625 return arm_record_unsupported_insn (arm_insn_r);
11628 /* Handling opcode 111 insns. */
11631 arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
11633 uint32_t op, op1_sbit, op1_ebit, coproc;
11634 struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
11635 struct regcache *reg_cache = arm_insn_r->regcache;
11637 arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
11638 coproc = bits (arm_insn_r->arm_insn, 8, 11);
11639 op1_sbit = bit (arm_insn_r->arm_insn, 24);
11640 op1_ebit = bit (arm_insn_r->arm_insn, 20);
11641 op = bit (arm_insn_r->arm_insn, 4);
11643 /* Handle arm SWI/SVC system call instructions. */
11646 if (tdep->arm_syscall_record != NULL)
11648 ULONGEST svc_operand, svc_number;
11650 svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
11652 if (svc_operand) /* OABI. */
11653 svc_number = svc_operand - 0x900000;
11655 regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
11657 return tdep->arm_syscall_record (reg_cache, svc_number);
11661 printf_unfiltered (_("no syscall record support\n"));
11666 if ((coproc & 0x0e) == 0x0a)
11668 /* VFP data-processing instructions. */
11669 if (!op1_sbit && !op)
11670 return arm_record_vfp_data_proc_insn (arm_insn_r);
11672 /* Advanced SIMD, VFP instructions. */
11673 if (!op1_sbit && op)
11674 return arm_record_vdata_transfer_insn (arm_insn_r);
11678 /* Coprocessor data operations. */
11679 if (!op1_sbit && !op)
11680 return arm_record_unsupported_insn (arm_insn_r);
11682 /* Move to Coprocessor from ARM core register. */
11683 if (!op1_sbit && !op1_ebit && op)
11684 return arm_record_unsupported_insn (arm_insn_r);
11686 /* Move to arm core register from coprocessor. */
11687 if (!op1_sbit && op1_ebit && op)
11689 uint32_t record_buf[1];
11691 record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
11692 if (record_buf[0] == 15)
11693 record_buf[0] = ARM_PS_REGNUM;
11695 arm_insn_r->reg_rec_count = 1;
11696 REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
11702 return arm_record_unsupported_insn (arm_insn_r);
11705 /* Handling opcode 000 insns. */
11708 thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
11710 uint32_t record_buf[8];
11711 uint32_t reg_src1 = 0;
11713 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11715 record_buf[0] = ARM_PS_REGNUM;
11716 record_buf[1] = reg_src1;
11717 thumb_insn_r->reg_rec_count = 2;
11719 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11725 /* Handling opcode 001 insns. */
11728 thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
11730 uint32_t record_buf[8];
11731 uint32_t reg_src1 = 0;
11733 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11735 record_buf[0] = ARM_PS_REGNUM;
11736 record_buf[1] = reg_src1;
11737 thumb_insn_r->reg_rec_count = 2;
11739 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11744 /* Handling opcode 010 insns. */
11747 thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
11749 struct regcache *reg_cache = thumb_insn_r->regcache;
11750 uint32_t record_buf[8], record_buf_mem[8];
11752 uint32_t reg_src1 = 0, reg_src2 = 0;
11753 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
11755 ULONGEST u_regval[2] = {0};
11757 opcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
11759 if (bit (thumb_insn_r->arm_insn, 12))
11761 /* Handle load/store register offset. */
11762 uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11);
11764 if (opB >= 4 && opB <= 7)
11766 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11767 reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
11768 record_buf[0] = reg_src1;
11769 thumb_insn_r->reg_rec_count = 1;
11771 else if (opB >= 0 && opB <= 2)
11773 /* STR(2), STRB(2), STRH(2) . */
11774 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11775 reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
11776 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
11777 regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
11779 record_buf_mem[0] = 4; /* STR (2). */
11781 record_buf_mem[0] = 1; /* STRB (2). */
11783 record_buf_mem[0] = 2; /* STRH (2). */
11784 record_buf_mem[1] = u_regval[0] + u_regval[1];
11785 thumb_insn_r->mem_rec_count = 1;
11788 else if (bit (thumb_insn_r->arm_insn, 11))
11790 /* Handle load from literal pool. */
11792 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11793 record_buf[0] = reg_src1;
11794 thumb_insn_r->reg_rec_count = 1;
11798 /* Special data instructions and branch and exchange */
11799 opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
11800 opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
11801 if ((3 == opcode2) && (!opcode3))
11803 /* Branch with exchange. */
11804 record_buf[0] = ARM_PS_REGNUM;
11805 thumb_insn_r->reg_rec_count = 1;
11809 /* Format 8; special data processing insns. */
11810 record_buf[0] = ARM_PS_REGNUM;
11811 record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3
11812 | bits (thumb_insn_r->arm_insn, 0, 2));
11813 thumb_insn_r->reg_rec_count = 2;
11818 /* Format 5; data processing insns. */
11819 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11820 if (bit (thumb_insn_r->arm_insn, 7))
11822 reg_src1 = reg_src1 + 8;
11824 record_buf[0] = ARM_PS_REGNUM;
11825 record_buf[1] = reg_src1;
11826 thumb_insn_r->reg_rec_count = 2;
11829 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11830 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11836 /* Handling opcode 001 insns. */
11839 thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
11841 struct regcache *reg_cache = thumb_insn_r->regcache;
11842 uint32_t record_buf[8], record_buf_mem[8];
11844 uint32_t reg_src1 = 0;
11845 uint32_t opcode = 0, immed_5 = 0;
11847 ULONGEST u_regval = 0;
11849 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11854 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11855 record_buf[0] = reg_src1;
11856 thumb_insn_r->reg_rec_count = 1;
11861 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11862 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11863 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11864 record_buf_mem[0] = 4;
11865 record_buf_mem[1] = u_regval + (immed_5 * 4);
11866 thumb_insn_r->mem_rec_count = 1;
11869 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11870 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11876 /* Handling opcode 100 insns. */
11879 thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
11881 struct regcache *reg_cache = thumb_insn_r->regcache;
11882 uint32_t record_buf[8], record_buf_mem[8];
11884 uint32_t reg_src1 = 0;
11885 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
11887 ULONGEST u_regval = 0;
11889 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11894 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11895 record_buf[0] = reg_src1;
11896 thumb_insn_r->reg_rec_count = 1;
11898 else if (1 == opcode)
11901 reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
11902 record_buf[0] = reg_src1;
11903 thumb_insn_r->reg_rec_count = 1;
11905 else if (2 == opcode)
11908 immed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
11909 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11910 record_buf_mem[0] = 4;
11911 record_buf_mem[1] = u_regval + (immed_8 * 4);
11912 thumb_insn_r->mem_rec_count = 1;
11914 else if (0 == opcode)
11917 immed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
11918 reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
11919 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
11920 record_buf_mem[0] = 2;
11921 record_buf_mem[1] = u_regval + (immed_5 * 2);
11922 thumb_insn_r->mem_rec_count = 1;
11925 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
11926 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
11932 /* Handling opcode 101 insns. */
11935 thumb_record_misc (insn_decode_record *thumb_insn_r)
11937 struct regcache *reg_cache = thumb_insn_r->regcache;
11939 uint32_t opcode = 0;
11940 uint32_t register_bits = 0, register_count = 0;
11941 uint32_t index = 0, start_address = 0;
11942 uint32_t record_buf[24], record_buf_mem[48];
11945 ULONGEST u_regval = 0;
11947 opcode = bits (thumb_insn_r->arm_insn, 11, 12);
11949 if (opcode == 0 || opcode == 1)
11951 /* ADR and ADD (SP plus immediate) */
11953 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11954 record_buf[0] = reg_src1;
11955 thumb_insn_r->reg_rec_count = 1;
11959 /* Miscellaneous 16-bit instructions */
11960 uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11);
11965 /* SETEND and CPS */
11968 /* ADD/SUB (SP plus immediate) */
11969 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
11970 record_buf[0] = ARM_SP_REGNUM;
11971 thumb_insn_r->reg_rec_count = 1;
11973 case 1: /* fall through */
11974 case 3: /* fall through */
11975 case 9: /* fall through */
11980 /* SXTH, SXTB, UXTH, UXTB */
11981 record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
11982 thumb_insn_r->reg_rec_count = 1;
11984 case 4: /* fall through */
11987 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
11988 regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
11989 while (register_bits)
11991 if (register_bits & 0x00000001)
11993 register_bits = register_bits >> 1;
11995 start_address = u_regval - \
11996 (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
11997 thumb_insn_r->mem_rec_count = register_count;
11998 while (register_count)
12000 record_buf_mem[(register_count * 2) - 1] = start_address;
12001 record_buf_mem[(register_count * 2) - 2] = 4;
12002 start_address = start_address + 4;
12005 record_buf[0] = ARM_SP_REGNUM;
12006 thumb_insn_r->reg_rec_count = 1;
12009 /* REV, REV16, REVSH */
12010 record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
12011 thumb_insn_r->reg_rec_count = 1;
12013 case 12: /* fall through */
12016 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12017 while (register_bits)
12019 if (register_bits & 0x00000001)
12020 record_buf[index++] = register_count;
12021 register_bits = register_bits >> 1;
12024 record_buf[index++] = ARM_PS_REGNUM;
12025 record_buf[index++] = ARM_SP_REGNUM;
12026 thumb_insn_r->reg_rec_count = index;
12030 /* Handle enhanced software breakpoint insn, BKPT. */
12031 /* CPSR is changed to be executed in ARM state, disabling normal
12032 interrupts, entering abort mode. */
12033 /* According to high vector configuration PC is set. */
12034 /* User hits breakpoint and type reverse, in that case, we need to go back with
12035 previous CPSR and Program Counter. */
12036 record_buf[0] = ARM_PS_REGNUM;
12037 record_buf[1] = ARM_LR_REGNUM;
12038 thumb_insn_r->reg_rec_count = 2;
12039 /* We need to save SPSR value, which is not yet done. */
12040 printf_unfiltered (_("Process record does not support instruction "
12041 "0x%0x at address %s.\n"),
12042 thumb_insn_r->arm_insn,
12043 paddress (thumb_insn_r->gdbarch,
12044 thumb_insn_r->this_addr));
12048 /* If-Then, and hints */
12055 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12056 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12062 /* Handling opcode 110 insns. */
12065 thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
12067 struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
12068 struct regcache *reg_cache = thumb_insn_r->regcache;
12070 uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */
12071 uint32_t reg_src1 = 0;
12072 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12073 uint32_t index = 0, start_address = 0;
12074 uint32_t record_buf[24], record_buf_mem[48];
12076 ULONGEST u_regval = 0;
12078 opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
12079 opcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
12085 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12087 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12088 while (register_bits)
12090 if (register_bits & 0x00000001)
12091 record_buf[index++] = register_count;
12092 register_bits = register_bits >> 1;
12095 record_buf[index++] = reg_src1;
12096 thumb_insn_r->reg_rec_count = index;
12098 else if (0 == opcode2)
12100 /* It handles both STMIA. */
12101 register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
12103 reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
12104 regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
12105 while (register_bits)
12107 if (register_bits & 0x00000001)
12109 register_bits = register_bits >> 1;
12111 start_address = u_regval;
12112 thumb_insn_r->mem_rec_count = register_count;
12113 while (register_count)
12115 record_buf_mem[(register_count * 2) - 1] = start_address;
12116 record_buf_mem[(register_count * 2) - 2] = 4;
12117 start_address = start_address + 4;
12121 else if (0x1F == opcode1)
12123 /* Handle arm syscall insn. */
12124 if (tdep->arm_syscall_record != NULL)
12126 regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
12127 ret = tdep->arm_syscall_record (reg_cache, u_regval);
12131 printf_unfiltered (_("no syscall record support\n"));
12136 /* B (1), conditional branch is automatically taken care in process_record,
12137 as PC is saved there. */
12139 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12140 MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
12146 /* Handling opcode 111 insns. */
12149 thumb_record_branch (insn_decode_record *thumb_insn_r)
12151 uint32_t record_buf[8];
12152 uint32_t bits_h = 0;
12154 bits_h = bits (thumb_insn_r->arm_insn, 11, 12);
12156 if (2 == bits_h || 3 == bits_h)
12159 record_buf[0] = ARM_LR_REGNUM;
12160 thumb_insn_r->reg_rec_count = 1;
12162 else if (1 == bits_h)
12165 record_buf[0] = ARM_PS_REGNUM;
12166 record_buf[1] = ARM_LR_REGNUM;
12167 thumb_insn_r->reg_rec_count = 2;
12170 /* B(2) is automatically taken care in process_record, as PC is
12173 REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
12178 /* Handler for thumb2 load/store multiple instructions. */
12181 thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
12183 struct regcache *reg_cache = thumb2_insn_r->regcache;
12185 uint32_t reg_rn, op;
12186 uint32_t register_bits = 0, register_count = 0;
12187 uint32_t index = 0, start_address = 0;
12188 uint32_t record_buf[24], record_buf_mem[48];
12190 ULONGEST u_regval = 0;
12192 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12193 op = bits (thumb2_insn_r->arm_insn, 23, 24);
12195 if (0 == op || 3 == op)
12197 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12199 /* Handle RFE instruction. */
12200 record_buf[0] = ARM_PS_REGNUM;
12201 thumb2_insn_r->reg_rec_count = 1;
12205 /* Handle SRS instruction after reading banked SP. */
12206 return arm_record_unsupported_insn (thumb2_insn_r);
12209 else if (1 == op || 2 == op)
12211 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12213 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12214 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12215 while (register_bits)
12217 if (register_bits & 0x00000001)
12218 record_buf[index++] = register_count;
12221 register_bits = register_bits >> 1;
12223 record_buf[index++] = reg_rn;
12224 record_buf[index++] = ARM_PS_REGNUM;
12225 thumb2_insn_r->reg_rec_count = index;
12229 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12230 register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
12231 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12232 while (register_bits)
12234 if (register_bits & 0x00000001)
12237 register_bits = register_bits >> 1;
12242 /* Start address calculation for LDMDB/LDMEA. */
12243 start_address = u_regval;
12247 /* Start address calculation for LDMDB/LDMEA. */
12248 start_address = u_regval - register_count * 4;
12251 thumb2_insn_r->mem_rec_count = register_count;
12252 while (register_count)
12254 record_buf_mem[register_count * 2 - 1] = start_address;
12255 record_buf_mem[register_count * 2 - 2] = 4;
12256 start_address = start_address + 4;
12259 record_buf[0] = reg_rn;
12260 record_buf[1] = ARM_PS_REGNUM;
12261 thumb2_insn_r->reg_rec_count = 2;
12265 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12267 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12269 return ARM_RECORD_SUCCESS;
12272 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12276 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
12278 struct regcache *reg_cache = thumb2_insn_r->regcache;
12280 uint32_t reg_rd, reg_rn, offset_imm;
12281 uint32_t reg_dest1, reg_dest2;
12282 uint32_t address, offset_addr;
12283 uint32_t record_buf[8], record_buf_mem[8];
12284 uint32_t op1, op2, op3;
12286 ULONGEST u_regval[2];
12288 op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
12289 op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
12290 op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
12292 if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
12294 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
12296 reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
12297 record_buf[0] = reg_dest1;
12298 record_buf[1] = ARM_PS_REGNUM;
12299 thumb2_insn_r->reg_rec_count = 2;
12302 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
12304 reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12305 record_buf[2] = reg_dest2;
12306 thumb2_insn_r->reg_rec_count = 3;
12311 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12312 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12314 if (0 == op1 && 0 == op2)
12316 /* Handle STREX. */
12317 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12318 address = u_regval[0] + (offset_imm * 4);
12319 record_buf_mem[0] = 4;
12320 record_buf_mem[1] = address;
12321 thumb2_insn_r->mem_rec_count = 1;
12322 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12323 record_buf[0] = reg_rd;
12324 thumb2_insn_r->reg_rec_count = 1;
12326 else if (1 == op1 && 0 == op2)
12328 reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
12329 record_buf[0] = reg_rd;
12330 thumb2_insn_r->reg_rec_count = 1;
12331 address = u_regval[0];
12332 record_buf_mem[1] = address;
12336 /* Handle STREXB. */
12337 record_buf_mem[0] = 1;
12338 thumb2_insn_r->mem_rec_count = 1;
12342 /* Handle STREXH. */
12343 record_buf_mem[0] = 2 ;
12344 thumb2_insn_r->mem_rec_count = 1;
12348 /* Handle STREXD. */
12349 address = u_regval[0];
12350 record_buf_mem[0] = 4;
12351 record_buf_mem[2] = 4;
12352 record_buf_mem[3] = address + 4;
12353 thumb2_insn_r->mem_rec_count = 2;
12358 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12360 if (bit (thumb2_insn_r->arm_insn, 24))
12362 if (bit (thumb2_insn_r->arm_insn, 23))
12363 offset_addr = u_regval[0] + (offset_imm * 4);
12365 offset_addr = u_regval[0] - (offset_imm * 4);
12367 address = offset_addr;
12370 address = u_regval[0];
12372 record_buf_mem[0] = 4;
12373 record_buf_mem[1] = address;
12374 record_buf_mem[2] = 4;
12375 record_buf_mem[3] = address + 4;
12376 thumb2_insn_r->mem_rec_count = 2;
12377 record_buf[0] = reg_rn;
12378 thumb2_insn_r->reg_rec_count = 1;
12382 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12384 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12386 return ARM_RECORD_SUCCESS;
12389 /* Handler for thumb2 data processing (shift register and modified immediate)
12393 thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
12395 uint32_t reg_rd, op;
12396 uint32_t record_buf[8];
12398 op = bits (thumb2_insn_r->arm_insn, 21, 24);
12399 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12401 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
12403 record_buf[0] = ARM_PS_REGNUM;
12404 thumb2_insn_r->reg_rec_count = 1;
12408 record_buf[0] = reg_rd;
12409 record_buf[1] = ARM_PS_REGNUM;
12410 thumb2_insn_r->reg_rec_count = 2;
12413 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12415 return ARM_RECORD_SUCCESS;
12418 /* Generic handler for thumb2 instructions which effect destination and PS
12422 thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
12425 uint32_t record_buf[8];
12427 reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
12429 record_buf[0] = reg_rd;
12430 record_buf[1] = ARM_PS_REGNUM;
12431 thumb2_insn_r->reg_rec_count = 2;
12433 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12435 return ARM_RECORD_SUCCESS;
12438 /* Handler for thumb2 branch and miscellaneous control instructions. */
12441 thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
12443 uint32_t op, op1, op2;
12444 uint32_t record_buf[8];
12446 op = bits (thumb2_insn_r->arm_insn, 20, 26);
12447 op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
12448 op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
12450 /* Handle MSR insn. */
12451 if (!(op1 & 0x2) && 0x38 == op)
12455 /* CPSR is going to be changed. */
12456 record_buf[0] = ARM_PS_REGNUM;
12457 thumb2_insn_r->reg_rec_count = 1;
12461 arm_record_unsupported_insn(thumb2_insn_r);
12465 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
12468 record_buf[0] = ARM_PS_REGNUM;
12469 record_buf[1] = ARM_LR_REGNUM;
12470 thumb2_insn_r->reg_rec_count = 2;
12473 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12475 return ARM_RECORD_SUCCESS;
12478 /* Handler for thumb2 store single data item instructions. */
12481 thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
12483 struct regcache *reg_cache = thumb2_insn_r->regcache;
12485 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
12486 uint32_t address, offset_addr;
12487 uint32_t record_buf[8], record_buf_mem[8];
12490 ULONGEST u_regval[2];
12492 op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
12493 op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
12494 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12495 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
12497 if (bit (thumb2_insn_r->arm_insn, 23))
12500 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
12501 offset_addr = u_regval[0] + offset_imm;
12502 address = offset_addr;
12507 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
12509 /* Handle STRB (register). */
12510 reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
12511 regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
12512 shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
12513 offset_addr = u_regval[1] << shift_imm;
12514 address = u_regval[0] + offset_addr;
12518 offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
12519 if (bit (thumb2_insn_r->arm_insn, 10))
12521 if (bit (thumb2_insn_r->arm_insn, 9))
12522 offset_addr = u_regval[0] + offset_imm;
12524 offset_addr = u_regval[0] - offset_imm;
12526 address = offset_addr;
12529 address = u_regval[0];
12535 /* Store byte instructions. */
12538 record_buf_mem[0] = 1;
12540 /* Store half word instructions. */
12543 record_buf_mem[0] = 2;
12545 /* Store word instructions. */
12548 record_buf_mem[0] = 4;
12552 gdb_assert_not_reached ("no decoding pattern found");
12556 record_buf_mem[1] = address;
12557 thumb2_insn_r->mem_rec_count = 1;
12558 record_buf[0] = reg_rn;
12559 thumb2_insn_r->reg_rec_count = 1;
12561 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12563 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12565 return ARM_RECORD_SUCCESS;
12568 /* Handler for thumb2 load memory hints instructions. */
12571 thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
12573 uint32_t record_buf[8];
12574 uint32_t reg_rt, reg_rn;
12576 reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
12577 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12579 if (ARM_PC_REGNUM != reg_rt)
12581 record_buf[0] = reg_rt;
12582 record_buf[1] = reg_rn;
12583 record_buf[2] = ARM_PS_REGNUM;
12584 thumb2_insn_r->reg_rec_count = 3;
12586 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12588 return ARM_RECORD_SUCCESS;
12591 return ARM_RECORD_FAILURE;
12594 /* Handler for thumb2 load word instructions. */
12597 thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
12599 uint32_t record_buf[8];
12601 record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
12602 record_buf[1] = ARM_PS_REGNUM;
12603 thumb2_insn_r->reg_rec_count = 2;
12605 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12607 return ARM_RECORD_SUCCESS;
12610 /* Handler for thumb2 long multiply, long multiply accumulate, and
12611 divide instructions. */
12614 thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
12616 uint32_t opcode1 = 0, opcode2 = 0;
12617 uint32_t record_buf[8];
12619 opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
12620 opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
12622 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
12624 /* Handle SMULL, UMULL, SMULAL. */
12625 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12626 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12627 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12628 record_buf[2] = ARM_PS_REGNUM;
12629 thumb2_insn_r->reg_rec_count = 3;
12631 else if (1 == opcode1 || 3 == opcode2)
12633 /* Handle SDIV and UDIV. */
12634 record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
12635 record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
12636 record_buf[2] = ARM_PS_REGNUM;
12637 thumb2_insn_r->reg_rec_count = 3;
12640 return ARM_RECORD_FAILURE;
12642 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12644 return ARM_RECORD_SUCCESS;
12647 /* Record handler for thumb32 coprocessor instructions. */
12650 thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
12652 if (bit (thumb2_insn_r->arm_insn, 25))
12653 return arm_record_coproc_data_proc (thumb2_insn_r);
12655 return arm_record_asimd_vfp_coproc (thumb2_insn_r);
12658 /* Record handler for advance SIMD structure load/store instructions. */
12661 thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
12663 struct regcache *reg_cache = thumb2_insn_r->regcache;
12664 uint32_t l_bit, a_bit, b_bits;
12665 uint32_t record_buf[128], record_buf_mem[128];
12666 uint32_t reg_rn, reg_vd, address, f_elem;
12667 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
12670 l_bit = bit (thumb2_insn_r->arm_insn, 21);
12671 a_bit = bit (thumb2_insn_r->arm_insn, 23);
12672 b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
12673 reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
12674 reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
12675 reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
12676 f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
12677 f_elem = 8 / f_ebytes;
12681 ULONGEST u_regval = 0;
12682 regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
12683 address = u_regval;
12688 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12690 if (b_bits == 0x07)
12692 else if (b_bits == 0x0a)
12694 else if (b_bits == 0x06)
12696 else if (b_bits == 0x02)
12701 for (index_r = 0; index_r < bf_regs; index_r++)
12703 for (index_e = 0; index_e < f_elem; index_e++)
12705 record_buf_mem[index_m++] = f_ebytes;
12706 record_buf_mem[index_m++] = address;
12707 address = address + f_ebytes;
12708 thumb2_insn_r->mem_rec_count += 1;
12713 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12715 if (b_bits == 0x09 || b_bits == 0x08)
12717 else if (b_bits == 0x03)
12722 for (index_r = 0; index_r < bf_regs; index_r++)
12723 for (index_e = 0; index_e < f_elem; index_e++)
12725 for (loop_t = 0; loop_t < 2; loop_t++)
12727 record_buf_mem[index_m++] = f_ebytes;
12728 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12729 thumb2_insn_r->mem_rec_count += 1;
12731 address = address + (2 * f_ebytes);
12735 else if ((b_bits & 0x0e) == 0x04)
12737 for (index_e = 0; index_e < f_elem; index_e++)
12739 for (loop_t = 0; loop_t < 3; loop_t++)
12741 record_buf_mem[index_m++] = f_ebytes;
12742 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12743 thumb2_insn_r->mem_rec_count += 1;
12745 address = address + (3 * f_ebytes);
12749 else if (!(b_bits & 0x0e))
12751 for (index_e = 0; index_e < f_elem; index_e++)
12753 for (loop_t = 0; loop_t < 4; loop_t++)
12755 record_buf_mem[index_m++] = f_ebytes;
12756 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
12757 thumb2_insn_r->mem_rec_count += 1;
12759 address = address + (4 * f_ebytes);
12765 uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
12767 if (bft_size == 0x00)
12769 else if (bft_size == 0x01)
12771 else if (bft_size == 0x02)
12777 if (!(b_bits & 0x0b) || b_bits == 0x08)
12778 thumb2_insn_r->mem_rec_count = 1;
12780 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
12781 thumb2_insn_r->mem_rec_count = 2;
12783 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
12784 thumb2_insn_r->mem_rec_count = 3;
12786 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
12787 thumb2_insn_r->mem_rec_count = 4;
12789 for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
12791 record_buf_mem[index_m] = f_ebytes;
12792 record_buf_mem[index_m] = address + (index_m * f_ebytes);
12801 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
12802 thumb2_insn_r->reg_rec_count = 1;
12804 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
12805 thumb2_insn_r->reg_rec_count = 2;
12807 else if ((b_bits & 0x0e) == 0x04)
12808 thumb2_insn_r->reg_rec_count = 3;
12810 else if (!(b_bits & 0x0e))
12811 thumb2_insn_r->reg_rec_count = 4;
12816 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
12817 thumb2_insn_r->reg_rec_count = 1;
12819 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
12820 thumb2_insn_r->reg_rec_count = 2;
12822 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
12823 thumb2_insn_r->reg_rec_count = 3;
12825 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
12826 thumb2_insn_r->reg_rec_count = 4;
12828 for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
12829 record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
12833 if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
12835 record_buf[index_r] = reg_rn;
12836 thumb2_insn_r->reg_rec_count += 1;
12839 REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
12841 MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
12846 /* Decodes thumb2 instruction type and invokes its record handler. */
12848 static unsigned int
12849 thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
12851 uint32_t op, op1, op2;
12853 op = bit (thumb2_insn_r->arm_insn, 15);
12854 op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
12855 op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
12859 if (!(op2 & 0x64 ))
12861 /* Load/store multiple instruction. */
12862 return thumb2_record_ld_st_multiple (thumb2_insn_r);
12864 else if ((op2 & 0x64) == 0x4)
12866 /* Load/store (dual/exclusive) and table branch instruction. */
12867 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
12869 else if ((op2 & 0x60) == 0x20)
12871 /* Data-processing (shifted register). */
12872 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12874 else if (op2 & 0x40)
12876 /* Co-processor instructions. */
12877 return thumb2_record_coproc_insn (thumb2_insn_r);
12880 else if (op1 == 0x02)
12884 /* Branches and miscellaneous control instructions. */
12885 return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
12887 else if (op2 & 0x20)
12889 /* Data-processing (plain binary immediate) instruction. */
12890 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12894 /* Data-processing (modified immediate). */
12895 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
12898 else if (op1 == 0x03)
12900 if (!(op2 & 0x71 ))
12902 /* Store single data item. */
12903 return thumb2_record_str_single_data (thumb2_insn_r);
12905 else if (!((op2 & 0x71) ^ 0x10))
12907 /* Advanced SIMD or structure load/store instructions. */
12908 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
12910 else if (!((op2 & 0x67) ^ 0x01))
12912 /* Load byte, memory hints instruction. */
12913 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12915 else if (!((op2 & 0x67) ^ 0x03))
12917 /* Load halfword, memory hints instruction. */
12918 return thumb2_record_ld_mem_hints (thumb2_insn_r);
12920 else if (!((op2 & 0x67) ^ 0x05))
12922 /* Load word instruction. */
12923 return thumb2_record_ld_word (thumb2_insn_r);
12925 else if (!((op2 & 0x70) ^ 0x20))
12927 /* Data-processing (register) instruction. */
12928 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12930 else if (!((op2 & 0x78) ^ 0x30))
12932 /* Multiply, multiply accumulate, abs diff instruction. */
12933 return thumb2_record_ps_dest_generic (thumb2_insn_r);
12935 else if (!((op2 & 0x78) ^ 0x38))
12937 /* Long multiply, long multiply accumulate, and divide. */
12938 return thumb2_record_lmul_lmla_div (thumb2_insn_r);
12940 else if (op2 & 0x40)
12942 /* Co-processor instructions. */
12943 return thumb2_record_coproc_insn (thumb2_insn_r);
12951 /* Abstract memory reader. */
12953 class abstract_memory_reader
12956 /* Read LEN bytes of target memory at address MEMADDR, placing the
12957 results in GDB's memory at BUF. Return true on success. */
12959 virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0;
12962 /* Instruction reader from real target. */
12964 class instruction_reader : public abstract_memory_reader
12967 bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len)
12969 if (target_read_memory (memaddr, buf, len))
12978 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12979 and positive val on fauilure. */
12982 extract_arm_insn (abstract_memory_reader& reader,
12983 insn_decode_record *insn_record, uint32_t insn_size)
12985 gdb_byte buf[insn_size];
12987 memset (&buf[0], 0, insn_size);
12989 if (!reader.read (insn_record->this_addr, buf, insn_size))
12991 insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
12993 gdbarch_byte_order_for_code (insn_record->gdbarch));
12997 typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12999 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13003 decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record,
13004 record_type_t record_type, uint32_t insn_size)
13007 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
13009 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
13011 arm_record_data_proc_misc_ld_str, /* 000. */
13012 arm_record_data_proc_imm, /* 001. */
13013 arm_record_ld_st_imm_offset, /* 010. */
13014 arm_record_ld_st_reg_offset, /* 011. */
13015 arm_record_ld_st_multiple, /* 100. */
13016 arm_record_b_bl, /* 101. */
13017 arm_record_asimd_vfp_coproc, /* 110. */
13018 arm_record_coproc_data_proc /* 111. */
13021 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
13023 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
13025 thumb_record_shift_add_sub, /* 000. */
13026 thumb_record_add_sub_cmp_mov, /* 001. */
13027 thumb_record_ld_st_reg_offset, /* 010. */
13028 thumb_record_ld_st_imm_offset, /* 011. */
13029 thumb_record_ld_st_stack, /* 100. */
13030 thumb_record_misc, /* 101. */
13031 thumb_record_ldm_stm_swi, /* 110. */
13032 thumb_record_branch /* 111. */
13035 uint32_t ret = 0; /* return value: negative:failure 0:success. */
13036 uint32_t insn_id = 0;
13038 if (extract_arm_insn (reader, arm_record, insn_size))
13042 printf_unfiltered (_("Process record: error reading memory at "
13043 "addr %s len = %d.\n"),
13044 paddress (arm_record->gdbarch,
13045 arm_record->this_addr), insn_size);
13049 else if (ARM_RECORD == record_type)
13051 arm_record->cond = bits (arm_record->arm_insn, 28, 31);
13052 insn_id = bits (arm_record->arm_insn, 25, 27);
13054 if (arm_record->cond == 0xf)
13055 ret = arm_record_extension_space (arm_record);
13058 /* If this insn has fallen into extension space
13059 then we need not decode it anymore. */
13060 ret = arm_handle_insn[insn_id] (arm_record);
13062 if (ret != ARM_RECORD_SUCCESS)
13064 arm_record_unsupported_insn (arm_record);
13068 else if (THUMB_RECORD == record_type)
13070 /* As thumb does not have condition codes, we set negative. */
13071 arm_record->cond = -1;
13072 insn_id = bits (arm_record->arm_insn, 13, 15);
13073 ret = thumb_handle_insn[insn_id] (arm_record);
13074 if (ret != ARM_RECORD_SUCCESS)
13076 arm_record_unsupported_insn (arm_record);
13080 else if (THUMB2_RECORD == record_type)
13082 /* As thumb does not have condition codes, we set negative. */
13083 arm_record->cond = -1;
13085 /* Swap first half of 32bit thumb instruction with second half. */
13086 arm_record->arm_insn
13087 = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
13089 ret = thumb2_record_decode_insn_handler (arm_record);
13091 if (ret != ARM_RECORD_SUCCESS)
13093 arm_record_unsupported_insn (arm_record);
13099 /* Throw assertion. */
13100 gdb_assert_not_reached ("not a valid instruction, could not decode");
13107 namespace selftests {
13109 /* Provide both 16-bit and 32-bit thumb instructions. */
13111 class instruction_reader_thumb : public abstract_memory_reader
13114 template<size_t SIZE>
13115 instruction_reader_thumb (enum bfd_endian endian,
13116 const uint16_t (&insns)[SIZE])
13117 : m_endian (endian), m_insns (insns), m_insns_size (SIZE)
13120 bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len)
13122 SELF_CHECK (len == 4 || len == 2);
13123 SELF_CHECK (memaddr % 2 == 0);
13124 SELF_CHECK ((memaddr / 2) < m_insns_size);
13126 store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]);
13129 store_unsigned_integer (&buf[2], 2, m_endian,
13130 m_insns[memaddr / 2 + 1]);
13136 enum bfd_endian m_endian;
13137 const uint16_t *m_insns;
13138 size_t m_insns_size;
13142 arm_record_test (void)
13144 struct gdbarch_info info;
13145 gdbarch_info_init (&info);
13146 info.bfd_arch_info = bfd_scan_arch ("arm");
13148 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
13150 SELF_CHECK (gdbarch != NULL);
13152 /* 16-bit Thumb instructions. */
13154 insn_decode_record arm_record;
13156 memset (&arm_record, 0, sizeof (insn_decode_record));
13157 arm_record.gdbarch = gdbarch;
13159 static const uint16_t insns[] = {
13160 /* db b2 uxtb r3, r3 */
13162 /* cd 58 ldr r5, [r1, r3] */
13166 enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
13167 instruction_reader_thumb reader (endian, insns);
13168 int ret = decode_insn (reader, &arm_record, THUMB_RECORD,
13169 THUMB_INSN_SIZE_BYTES);
13171 SELF_CHECK (ret == 0);
13172 SELF_CHECK (arm_record.mem_rec_count == 0);
13173 SELF_CHECK (arm_record.reg_rec_count == 1);
13174 SELF_CHECK (arm_record.arm_regs[0] == 3);
13176 arm_record.this_addr += 2;
13177 ret = decode_insn (reader, &arm_record, THUMB_RECORD,
13178 THUMB_INSN_SIZE_BYTES);
13180 SELF_CHECK (ret == 0);
13181 SELF_CHECK (arm_record.mem_rec_count == 0);
13182 SELF_CHECK (arm_record.reg_rec_count == 1);
13183 SELF_CHECK (arm_record.arm_regs[0] == 5);
13186 /* 32-bit Thumb-2 instructions. */
13188 insn_decode_record arm_record;
13190 memset (&arm_record, 0, sizeof (insn_decode_record));
13191 arm_record.gdbarch = gdbarch;
13193 static const uint16_t insns[] = {
13194 /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
13198 enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
13199 instruction_reader_thumb reader (endian, insns);
13200 int ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
13201 THUMB2_INSN_SIZE_BYTES);
13203 SELF_CHECK (ret == 0);
13204 SELF_CHECK (arm_record.mem_rec_count == 0);
13205 SELF_CHECK (arm_record.reg_rec_count == 1);
13206 SELF_CHECK (arm_record.arm_regs[0] == 7);
13209 } // namespace selftests
13210 #endif /* GDB_SELF_TEST */
13212 /* Cleans up local record registers and memory allocations. */
13215 deallocate_reg_mem (insn_decode_record *record)
13217 xfree (record->arm_regs);
13218 xfree (record->arm_mems);
13222 /* Parse the current instruction and record the values of the registers and
13223 memory that will be changed in current instruction to record_arch_list".
13224 Return -1 if something is wrong. */
13227 arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
13228 CORE_ADDR insn_addr)
13231 uint32_t no_of_rec = 0;
13232 uint32_t ret = 0; /* return value: -1:record failure ; 0:success */
13233 ULONGEST t_bit = 0, insn_id = 0;
13235 ULONGEST u_regval = 0;
13237 insn_decode_record arm_record;
13239 memset (&arm_record, 0, sizeof (insn_decode_record));
13240 arm_record.regcache = regcache;
13241 arm_record.this_addr = insn_addr;
13242 arm_record.gdbarch = gdbarch;
13245 if (record_debug > 1)
13247 fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
13249 paddress (gdbarch, arm_record.this_addr));
13252 instruction_reader reader;
13253 if (extract_arm_insn (reader, &arm_record, 2))
13257 printf_unfiltered (_("Process record: error reading memory at "
13258 "addr %s len = %d.\n"),
13259 paddress (arm_record.gdbarch,
13260 arm_record.this_addr), 2);
13265 /* Check the insn, whether it is thumb or arm one. */
13267 t_bit = arm_psr_thumb_bit (arm_record.gdbarch);
13268 regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval);
13271 if (!(u_regval & t_bit))
13273 /* We are decoding arm insn. */
13274 ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
13278 insn_id = bits (arm_record.arm_insn, 11, 15);
13279 /* is it thumb2 insn? */
13280 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13282 ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
13283 THUMB2_INSN_SIZE_BYTES);
13287 /* We are decoding thumb insn. */
13288 ret = decode_insn (reader, &arm_record, THUMB_RECORD,
13289 THUMB_INSN_SIZE_BYTES);
13295 /* Record registers. */
13296 record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM);
13297 if (arm_record.arm_regs)
13299 for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++)
13301 if (record_full_arch_list_add_reg
13302 (arm_record.regcache , arm_record.arm_regs[no_of_rec]))
13306 /* Record memories. */
13307 if (arm_record.arm_mems)
13309 for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++)
13311 if (record_full_arch_list_add_mem
13312 ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
13313 arm_record.arm_mems[no_of_rec].len))
13318 if (record_full_arch_list_add_end ())
13323 deallocate_reg_mem (&arm_record);