1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Register numbers of various important registers. */
25 ARM_A1_REGNUM = 0, /* first integer-like argument */
26 ARM_A4_REGNUM = 3, /* last integer-like argument */
29 ARM_SP_REGNUM = 13, /* Contains address of top of stack */
30 ARM_LR_REGNUM = 14, /* address to return to from a function call */
31 ARM_PC_REGNUM = 15, /* Contains program counter */
32 ARM_F0_REGNUM = 16, /* first floating point register */
33 ARM_F3_REGNUM = 19, /* last floating point argument register */
34 ARM_F7_REGNUM = 23, /* last floating point register */
35 ARM_FPS_REGNUM = 24, /* floating point status register */
36 ARM_PS_REGNUM = 25, /* Contains processor status */
37 ARM_WR0_REGNUM, /* WMMX data registers. */
38 ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
39 ARM_WC0_REGNUM, /* WMMX control registers. */
40 ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
41 ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
42 ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
43 ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
44 ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
45 ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
46 ARM_D0_REGNUM, /* VFP double-precision registers. */
47 ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
52 /* Other useful registers. */
53 ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
54 THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
56 ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
57 ARM_NUM_FP_ARG_REGS = 4,
58 ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
61 /* Instruction condition field values. */
79 #define FLAG_N 0x80000000
80 #define FLAG_Z 0x40000000
81 #define FLAG_C 0x20000000
82 #define FLAG_V 0x10000000
86 #define XPSR_T 0x01000000
88 /* Size of integer registers. */
89 #define INT_REGISTER_SIZE 4
91 /* Addresses for calling Thumb functions have the bit 0 set.
92 Here are some macros to test, set, or clear bit 0 of addresses. */
93 #define IS_THUMB_ADDR(addr) ((addr) & 1)
94 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
95 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
97 /* Return the size in bytes of the complete Thumb instruction whose
98 first halfword is INST1. */
99 int thumb_insn_size (unsigned short inst1);
101 /* Returns true if the condition evaluates to true. */
102 int condition_true (unsigned long cond, unsigned long status_reg);
104 /* Return number of 1-bits in VAL. */
105 int bitcount (unsigned long val);