1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "gdbsupport/common-defs.h"
21 #include "gdbsupport/common-regcache.h"
24 #include "../features/arm/arm-core.c"
25 #include "../features/arm/arm-vfpv2.c"
26 #include "../features/arm/arm-vfpv3.c"
27 #include "../features/arm/xscale-iwmmxt.c"
28 #include "../features/arm/arm-m-profile.c"
29 #include "../features/arm/arm-m-profile-with-fpa.c"
34 thumb_insn_size (unsigned short inst1)
36 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
45 bitcount (unsigned long val)
48 for (nbits = 0; val != 0; nbits++)
49 val &= val - 1; /* Delete rightmost 1-bit in val. */
56 condition_true (unsigned long cond, unsigned long status_reg)
58 if (cond == INST_AL || cond == INST_NV)
64 return ((status_reg & FLAG_Z) != 0);
66 return ((status_reg & FLAG_Z) == 0);
68 return ((status_reg & FLAG_C) != 0);
70 return ((status_reg & FLAG_C) == 0);
72 return ((status_reg & FLAG_N) != 0);
74 return ((status_reg & FLAG_N) == 0);
76 return ((status_reg & FLAG_V) != 0);
78 return ((status_reg & FLAG_V) == 0);
80 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
82 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
84 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
86 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
88 return (((status_reg & FLAG_Z) == 0)
89 && (((status_reg & FLAG_N) == 0)
90 == ((status_reg & FLAG_V) == 0)));
92 return (((status_reg & FLAG_Z) != 0)
93 || (((status_reg & FLAG_N) == 0)
94 != ((status_reg & FLAG_V) == 0)));
103 thumb_advance_itstate (unsigned int itstate)
105 /* Preserve IT[7:5], the first three bits of the condition. Shift
106 the upcoming condition flags left by one bit. */
107 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
109 /* If we have finished the IT block, clear the state. */
110 if ((itstate & 0x0f) == 0)
119 arm_instruction_changes_pc (uint32_t this_instr)
121 if (bits (this_instr, 28, 31) == INST_NV)
122 /* Unconditional instructions. */
123 switch (bits (this_instr, 24, 27))
127 /* Branch with Link and change to Thumb. */
132 /* Coprocessor register transfer. */
133 if (bits (this_instr, 12, 15) == 15)
134 error (_("Invalid update to pc in instruction"));
140 switch (bits (this_instr, 25, 27))
143 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
145 /* Multiplies and extra load/stores. */
146 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
147 /* Neither multiplies nor extension load/stores are allowed
151 /* Otherwise, miscellaneous instructions. */
153 /* BX <reg>, BXJ <reg>, BLX <reg> */
154 if (bits (this_instr, 4, 27) == 0x12fff1
155 || bits (this_instr, 4, 27) == 0x12fff2
156 || bits (this_instr, 4, 27) == 0x12fff3)
159 /* Other miscellaneous instructions are unpredictable if they
163 /* Data processing instruction. */
167 if (bits (this_instr, 12, 15) == 15)
174 /* Media instructions and architecturally undefined instructions. */
175 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
179 if (bit (this_instr, 20) == 0)
183 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
189 /* Load/store multiple. */
190 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
196 /* Branch and branch with link. */
201 /* Coprocessor transfers or SWIs can not affect PC. */
205 internal_error (__FILE__, __LINE__, _("bad value in switch"));
212 thumb_instruction_changes_pc (unsigned short inst)
214 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
217 if ((inst & 0xf000) == 0xd000) /* conditional branch */
220 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
223 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
226 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
229 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
239 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
241 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
243 /* Branches and miscellaneous control instructions. */
245 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
250 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
252 /* SUBS PC, LR, #imm8. */
255 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
257 /* Conditional branch. */
264 if ((inst1 & 0xfe50) == 0xe810)
266 /* Load multiple or RFE. */
268 if (bit (inst1, 7) && !bit (inst1, 8))
274 else if (!bit (inst1, 7) && bit (inst1, 8))
280 else if (bit (inst1, 7) && bit (inst1, 8))
285 else if (!bit (inst1, 7) && !bit (inst1, 8))
294 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
296 /* MOV PC or MOVS PC. */
300 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
303 if (bits (inst1, 0, 3) == 15)
309 if ((inst2 & 0x0fc0) == 0x0000)
315 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
321 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
333 shifted_reg_val (struct regcache *regcache, unsigned long inst,
334 int carry, unsigned long pc_val, unsigned long status_reg)
336 unsigned long res, shift;
337 int rm = bits (inst, 0, 3);
338 unsigned long shifttype = bits (inst, 5, 6);
342 int rs = bits (inst, 8, 11);
345 : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
348 shift = bits (inst, 7, 11);
350 res = (rm == ARM_PC_REGNUM
351 ? (pc_val + (bit (inst, 4) ? 12 : 8))
352 : regcache_raw_get_unsigned (regcache, rm));
357 res = shift >= 32 ? 0 : res << shift;
361 res = shift >= 32 ? 0 : res >> shift;
367 res = ((res & 0x80000000L)
368 ? ~((~res) >> shift) : res >> shift);
371 case 3: /* ROR/RRX */
374 res = (res >> 1) | (carry ? 0x80000000L : 0);
376 res = (res >> shift) | (res << (32 - shift));
380 return res & 0xffffffff;
383 /* See arch/arm.h. */
386 arm_create_target_description (arm_fp_type fp_type)
388 target_desc *tdesc = allocate_target_description ();
390 #ifndef IN_PROCESS_AGENT
391 if (fp_type == ARM_FP_TYPE_IWMMXT)
392 set_tdesc_architecture (tdesc, "iwmmxt");
394 set_tdesc_architecture (tdesc, "arm");
399 regnum = create_feature_arm_arm_core (tdesc, regnum);
403 case ARM_FP_TYPE_NONE:
406 case ARM_FP_TYPE_VFPV2:
407 regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
410 case ARM_FP_TYPE_VFPV3:
411 regnum = create_feature_arm_arm_vfpv3 (tdesc, regnum);
414 case ARM_FP_TYPE_IWMMXT:
415 regnum = create_feature_arm_xscale_iwmmxt (tdesc, regnum);
419 error (_("Invalid Arm FP type: %d"), fp_type);
425 /* See arch/arm.h. */
428 arm_create_mprofile_target_description (arm_m_profile_type m_type)
430 target_desc *tdesc = allocate_target_description ();
432 #ifndef IN_PROCESS_AGENT
433 set_tdesc_architecture (tdesc, "arm");
440 case ARM_M_TYPE_M_PROFILE:
441 regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
444 case ARM_M_TYPE_VFP_D16:
445 regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
446 regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
449 case ARM_M_TYPE_WITH_FPA:
450 regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum);
454 error (_("Invalid Arm M type: %d"), m_type);