1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "gdbsupport/common-defs.h"
21 #include "gdbsupport/common-regcache.h"
27 thumb_insn_size (unsigned short inst1)
29 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
38 bitcount (unsigned long val)
41 for (nbits = 0; val != 0; nbits++)
42 val &= val - 1; /* Delete rightmost 1-bit in val. */
49 condition_true (unsigned long cond, unsigned long status_reg)
51 if (cond == INST_AL || cond == INST_NV)
57 return ((status_reg & FLAG_Z) != 0);
59 return ((status_reg & FLAG_Z) == 0);
61 return ((status_reg & FLAG_C) != 0);
63 return ((status_reg & FLAG_C) == 0);
65 return ((status_reg & FLAG_N) != 0);
67 return ((status_reg & FLAG_N) == 0);
69 return ((status_reg & FLAG_V) != 0);
71 return ((status_reg & FLAG_V) == 0);
73 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
75 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
77 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
79 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
81 return (((status_reg & FLAG_Z) == 0)
82 && (((status_reg & FLAG_N) == 0)
83 == ((status_reg & FLAG_V) == 0)));
85 return (((status_reg & FLAG_Z) != 0)
86 || (((status_reg & FLAG_N) == 0)
87 != ((status_reg & FLAG_V) == 0)));
96 thumb_advance_itstate (unsigned int itstate)
98 /* Preserve IT[7:5], the first three bits of the condition. Shift
99 the upcoming condition flags left by one bit. */
100 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
102 /* If we have finished the IT block, clear the state. */
103 if ((itstate & 0x0f) == 0)
112 arm_instruction_changes_pc (uint32_t this_instr)
114 if (bits (this_instr, 28, 31) == INST_NV)
115 /* Unconditional instructions. */
116 switch (bits (this_instr, 24, 27))
120 /* Branch with Link and change to Thumb. */
125 /* Coprocessor register transfer. */
126 if (bits (this_instr, 12, 15) == 15)
127 error (_("Invalid update to pc in instruction"));
133 switch (bits (this_instr, 25, 27))
136 if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
138 /* Multiplies and extra load/stores. */
139 if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
140 /* Neither multiplies nor extension load/stores are allowed
144 /* Otherwise, miscellaneous instructions. */
146 /* BX <reg>, BXJ <reg>, BLX <reg> */
147 if (bits (this_instr, 4, 27) == 0x12fff1
148 || bits (this_instr, 4, 27) == 0x12fff2
149 || bits (this_instr, 4, 27) == 0x12fff3)
152 /* Other miscellaneous instructions are unpredictable if they
156 /* Data processing instruction. */
160 if (bits (this_instr, 12, 15) == 15)
167 /* Media instructions and architecturally undefined instructions. */
168 if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
172 if (bit (this_instr, 20) == 0)
176 if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
182 /* Load/store multiple. */
183 if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
189 /* Branch and branch with link. */
194 /* Coprocessor transfers or SWIs can not affect PC. */
198 internal_error (__FILE__, __LINE__, _("bad value in switch"));
205 thumb_instruction_changes_pc (unsigned short inst)
207 if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
210 if ((inst & 0xf000) == 0xd000) /* conditional branch */
213 if ((inst & 0xf800) == 0xe000) /* unconditional branch */
216 if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
219 if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
222 if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
232 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
234 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
236 /* Branches and miscellaneous control instructions. */
238 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
243 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
245 /* SUBS PC, LR, #imm8. */
248 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
250 /* Conditional branch. */
257 if ((inst1 & 0xfe50) == 0xe810)
259 /* Load multiple or RFE. */
261 if (bit (inst1, 7) && !bit (inst1, 8))
267 else if (!bit (inst1, 7) && bit (inst1, 8))
273 else if (bit (inst1, 7) && bit (inst1, 8))
278 else if (!bit (inst1, 7) && !bit (inst1, 8))
287 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
289 /* MOV PC or MOVS PC. */
293 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
296 if (bits (inst1, 0, 3) == 15)
302 if ((inst2 & 0x0fc0) == 0x0000)
308 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
314 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
326 shifted_reg_val (struct regcache *regcache, unsigned long inst,
327 int carry, unsigned long pc_val, unsigned long status_reg)
329 unsigned long res, shift;
330 int rm = bits (inst, 0, 3);
331 unsigned long shifttype = bits (inst, 5, 6);
335 int rs = bits (inst, 8, 11);
338 : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
341 shift = bits (inst, 7, 11);
343 res = (rm == ARM_PC_REGNUM
344 ? (pc_val + (bit (inst, 4) ? 12 : 8))
345 : regcache_raw_get_unsigned (regcache, rm));
350 res = shift >= 32 ? 0 : res << shift;
354 res = shift >= 32 ? 0 : res >> shift;
360 res = ((res & 0x80000000L)
361 ? ~((~res) >> shift) : res >> shift);
364 case 3: /* ROR/RRX */
367 res = (res >> 1) | (carry ? 0x80000000L : 0);
369 res = (res >> shift) | (res << (32 - shift));
373 return res & 0xffffffff;