1 /* Target dependent code for ARC arhitecture, for GDB.
3 Copyright 2005-2018 Free Software Foundation, Inc.
4 Contributed by Synopsys Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* GDB header files. */
23 #include "arch-utils.h"
25 #include "dwarf2-frame.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
31 #include "prologue-value.h"
32 #include "trad-frame.h"
34 /* ARC header files. */
35 #include "opcode/arc.h"
36 #include "../opcodes/arc-dis.h"
39 /* Standard headers. */
42 /* Default target descriptions. */
43 #include "features/arc-v2.c"
44 #include "features/arc-arcompact.c"
46 /* The frame unwind cache for ARC. */
48 struct arc_frame_cache
50 /* The stack pointer at the time this frame was created; i.e. the caller's
51 stack pointer when this function was called. It is used to identify this
55 /* Register that is a base for this frame - FP for normal frame, SP for
59 /* Offset from the previous SP to the current frame base. If GCC uses
60 `SUB SP,SP,offset` to allocate space for local variables, then it will be
61 done after setting up a frame pointer, but it still will be considered
62 part of prologue, therefore SP will be lesser than FP at the end of the
63 prologue analysis. In this case that would be an offset from old SP to a
64 new FP. But in case of non-FP frames, frame base is an SP and thus that
65 would be an offset from old SP to new SP. What is important is that this
66 is an offset from old SP to a known register, so it can be used to find
69 Using FP is preferable, when possible, because SP can change in function
70 body after prologue due to alloca, variadic arguments or other shenanigans.
71 If that is the case in the caller frame, then PREV_SP will point to SP at
72 the moment of function call, but it will be different from SP value at the
73 end of the caller prologue. As a result it will not be possible to
74 reconstruct caller's frame and go past it in the backtrace. Those things
75 are unlikely to happen to FP - FP value at the moment of function call (as
76 stored on stack in callee prologue) is also an FP value at the end of the
79 LONGEST frame_base_offset;
81 /* Store addresses for registers saved in prologue. During prologue analysis
82 GDB stores offsets relatively to "old SP", then after old SP is evaluated,
83 offsets are replaced with absolute addresses. */
84 struct trad_frame_saved_reg *saved_regs;
87 /* Global debug flag. */
91 /* List of "maintenance print arc" commands. */
93 static struct cmd_list_element *maintenance_print_arc_list = NULL;
95 /* XML target description features. */
97 static const char core_v2_feature_name[] = "org.gnu.gdb.arc.core.v2";
99 core_reduced_v2_feature_name[] = "org.gnu.gdb.arc.core-reduced.v2";
101 core_arcompact_feature_name[] = "org.gnu.gdb.arc.core.arcompact";
102 static const char aux_minimal_feature_name[] = "org.gnu.gdb.arc.aux-minimal";
104 /* XML target description known registers. */
106 static const char *const core_v2_register_names[] = {
107 "r0", "r1", "r2", "r3",
108 "r4", "r5", "r6", "r7",
109 "r8", "r9", "r10", "r11",
110 "r12", "r13", "r14", "r15",
111 "r16", "r17", "r18", "r19",
112 "r20", "r21", "r22", "r23",
113 "r24", "r25", "gp", "fp",
114 "sp", "ilink", "r30", "blink",
115 "r32", "r33", "r34", "r35",
116 "r36", "r37", "r38", "r39",
117 "r40", "r41", "r42", "r43",
118 "r44", "r45", "r46", "r47",
119 "r48", "r49", "r50", "r51",
120 "r52", "r53", "r54", "r55",
121 "r56", "r57", "accl", "acch",
122 "lp_count", "reserved", "limm", "pcl",
125 static const char *const aux_minimal_register_names[] = {
129 static const char *const core_arcompact_register_names[] = {
130 "r0", "r1", "r2", "r3",
131 "r4", "r5", "r6", "r7",
132 "r8", "r9", "r10", "r11",
133 "r12", "r13", "r14", "r15",
134 "r16", "r17", "r18", "r19",
135 "r20", "r21", "r22", "r23",
136 "r24", "r25", "gp", "fp",
137 "sp", "ilink1", "ilink2", "blink",
138 "r32", "r33", "r34", "r35",
139 "r36", "r37", "r38", "r39",
140 "r40", "r41", "r42", "r43",
141 "r44", "r45", "r46", "r47",
142 "r48", "r49", "r50", "r51",
143 "r52", "r53", "r54", "r55",
144 "r56", "r57", "r58", "r59",
145 "lp_count", "reserved", "limm", "pcl",
148 static char *arc_disassembler_options = NULL;
150 /* Functions are sorted in the order as they are used in the
151 _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static
152 functions are defined before the first invocation. */
154 /* Returns an unsigned value of OPERAND_NUM in instruction INSN.
155 For relative branch instructions returned value is an offset, not an actual
159 arc_insn_get_operand_value (const struct arc_instruction &insn,
160 unsigned int operand_num)
162 switch (insn.operands[operand_num].kind)
164 case ARC_OPERAND_KIND_LIMM:
165 gdb_assert (insn.limm_p);
166 return insn.limm_value;
167 case ARC_OPERAND_KIND_SHIMM:
168 return insn.operands[operand_num].value;
170 /* Value in instruction is a register number. */
171 struct regcache *regcache = get_current_regcache ();
173 regcache_cooked_read_unsigned (regcache,
174 insn.operands[operand_num].value,
180 /* Like arc_insn_get_operand_value, but returns a signed value. */
183 arc_insn_get_operand_value_signed (const struct arc_instruction &insn,
184 unsigned int operand_num)
186 switch (insn.operands[operand_num].kind)
188 case ARC_OPERAND_KIND_LIMM:
189 gdb_assert (insn.limm_p);
190 /* Convert unsigned raw value to signed one. This assumes 2's
191 complement arithmetic, but so is the LONG_MIN value from generic
192 defs.h and that assumption is true for ARC. */
193 gdb_static_assert (sizeof (insn.limm_value) == sizeof (int));
194 return (((LONGEST) insn.limm_value) ^ INT_MIN) - INT_MIN;
195 case ARC_OPERAND_KIND_SHIMM:
196 /* Sign conversion has been done by binutils. */
197 return insn.operands[operand_num].value;
199 /* Value in instruction is a register number. */
200 struct regcache *regcache = get_current_regcache ();
202 regcache_cooked_read_signed (regcache,
203 insn.operands[operand_num].value,
209 /* Get register with base address of memory operation. */
212 arc_insn_get_memory_base_reg (const struct arc_instruction &insn)
214 /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */
215 if (insn.insn_class == PUSH || insn.insn_class == POP)
216 return ARC_SP_REGNUM;
218 gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE);
220 /* Other instructions all have at least two operands: operand 0 is data,
221 operand 1 is address. Operand 2 is offset from address. However, see
222 comment to arc_instruction.operands - in some cases, third operand may be
223 missing, namely if it is 0. */
224 gdb_assert (insn.operands_count >= 2);
225 return insn.operands[1].value;
228 /* Get offset of a memory operation INSN. */
231 arc_insn_get_memory_offset (const struct arc_instruction &insn)
233 /* POP_S and PUSH_S have offset as an implicit argument in a
235 if (insn.insn_class == POP)
237 else if (insn.insn_class == PUSH)
240 gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE);
242 /* Other instructions all have at least two operands: operand 0 is data,
243 operand 1 is address. Operand 2 is offset from address. However, see
244 comment to arc_instruction.operands - in some cases, third operand may be
245 missing, namely if it is 0. */
246 if (insn.operands_count < 3)
249 CORE_ADDR value = arc_insn_get_operand_value (insn, 2);
250 /* Handle scaling. */
251 if (insn.writeback_mode == ARC_WRITEBACK_AS)
253 /* Byte data size is not valid for AS. Halfword means shift by 1 bit.
254 Word and double word means shift by 2 bits. */
255 gdb_assert (insn.data_size_mode != ARC_SCALING_B);
256 if (insn.data_size_mode == ARC_SCALING_H)
265 arc_insn_get_branch_target (const struct arc_instruction &insn)
267 gdb_assert (insn.is_control_flow);
269 /* BI [c]: PC = nextPC + (c << 2). */
270 if (insn.insn_class == BI)
272 ULONGEST reg_value = arc_insn_get_operand_value (insn, 0);
273 return arc_insn_get_linear_next_pc (insn) + (reg_value << 2);
275 /* BIH [c]: PC = nextPC + (c << 1). */
276 else if (insn.insn_class == BIH)
278 ULONGEST reg_value = arc_insn_get_operand_value (insn, 0);
279 return arc_insn_get_linear_next_pc (insn) + (reg_value << 1);
282 /* JLI and EI depend on optional AUX registers. Not supported right now. */
283 else if (insn.insn_class == JLI)
285 fprintf_unfiltered (gdb_stderr,
286 "JLI_S instruction is not supported by the GDB.");
289 else if (insn.insn_class == EI)
291 fprintf_unfiltered (gdb_stderr,
292 "EI_S instruction is not supported by the GDB.");
295 /* LEAVE_S: PC = BLINK. */
296 else if (insn.insn_class == LEAVE)
298 struct regcache *regcache = get_current_regcache ();
300 regcache_cooked_read_unsigned (regcache, ARC_BLINK_REGNUM, &value);
303 /* BBIT0/1, BRcc: PC = currentPC + operand. */
304 else if (insn.insn_class == BBIT0 || insn.insn_class == BBIT1
305 || insn.insn_class == BRCC)
307 /* Most instructions has branch target as their sole argument. However
308 conditional brcc/bbit has it as a third operand. */
309 CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 2);
311 /* Offset is relative to the 4-byte aligned address of the current
312 instruction, hence last two bits should be truncated. */
313 return pcrel_addr + align_down (insn.address, 4);
315 /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */
316 else if (insn.insn_class == BRANCH || insn.insn_class == LOOP)
318 CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 0);
320 /* Offset is relative to the 4-byte aligned address of the current
321 instruction, hence last two bits should be truncated. */
322 return pcrel_addr + align_down (insn.address, 4);
324 /* J, Jcc, JL, JLcc: PC = operand. */
325 else if (insn.insn_class == JUMP)
327 /* All jumps are single-operand. */
328 return arc_insn_get_operand_value (insn, 0);
331 /* This is some new and unknown instruction. */
332 gdb_assert_not_reached ("Unknown branch instruction.");
335 /* Dump INSN into gdb_stdlog. */
338 arc_insn_dump (const struct arc_instruction &insn)
340 struct gdbarch *gdbarch = target_gdbarch ();
342 arc_print ("Dumping arc_instruction at %s\n",
343 paddress (gdbarch, insn.address));
344 arc_print ("\tlength = %u\n", insn.length);
348 arc_print ("\tThis is not a valid ARC instruction.\n");
352 arc_print ("\tlength_with_limm = %u\n", insn.length + (insn.limm_p ? 4 : 0));
353 arc_print ("\tcc = 0x%x\n", insn.condition_code);
354 arc_print ("\tinsn_class = %u\n", insn.insn_class);
355 arc_print ("\tis_control_flow = %i\n", insn.is_control_flow);
356 arc_print ("\thas_delay_slot = %i\n", insn.has_delay_slot);
358 CORE_ADDR next_pc = arc_insn_get_linear_next_pc (insn);
359 arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch, next_pc));
361 if (insn.is_control_flow)
363 CORE_ADDR t = arc_insn_get_branch_target (insn);
364 arc_print ("\tbranch_target = %s\n", paddress (gdbarch, t));
367 arc_print ("\tlimm_p = %i\n", insn.limm_p);
369 arc_print ("\tlimm_value = 0x%08x\n", insn.limm_value);
371 if (insn.insn_class == STORE || insn.insn_class == LOAD
372 || insn.insn_class == PUSH || insn.insn_class == POP)
374 arc_print ("\twriteback_mode = %u\n", insn.writeback_mode);
375 arc_print ("\tdata_size_mode = %u\n", insn.data_size_mode);
376 arc_print ("\tmemory_base_register = %s\n",
377 gdbarch_register_name (gdbarch,
378 arc_insn_get_memory_base_reg (insn)));
379 /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a
380 LONGEST for a nicer representation. */
381 arc_print ("\taddr_offset = %s\n",
382 plongest (arc_insn_get_memory_offset (insn)));
385 arc_print ("\toperands_count = %u\n", insn.operands_count);
386 for (unsigned int i = 0; i < insn.operands_count; ++i)
388 int is_reg = (insn.operands[i].kind == ARC_OPERAND_KIND_REG);
390 arc_print ("\toperand[%u] = {\n", i);
391 arc_print ("\t\tis_reg = %i\n", is_reg);
393 arc_print ("\t\tregister = %s\n",
394 gdbarch_register_name (gdbarch, insn.operands[i].value));
395 /* Don't know if this value is signed or not, so print both
396 representations. This tends to look quite ugly, especially for big
398 arc_print ("\t\tunsigned value = %s\n",
399 pulongest (arc_insn_get_operand_value (insn, i)));
400 arc_print ("\t\tsigned value = %s\n",
401 plongest (arc_insn_get_operand_value_signed (insn, i)));
407 arc_insn_get_linear_next_pc (const struct arc_instruction &insn)
409 /* In ARC long immediate is always 4 bytes. */
410 return (insn.address + insn.length + (insn.limm_p ? 4 : 0));
413 /* Implement the "write_pc" gdbarch method.
415 In ARC PC register is a normal register so in most cases setting PC value
416 is a straightforward process: debugger just writes PC value. However it
417 gets trickier in case when current instruction is an instruction in delay
418 slot. In this case CPU will execute instruction at current PC value, then
419 will set PC to the current value of BTA register; also current instruction
420 cannot be branch/jump and some of the other instruction types. Thus if
421 debugger would try to just change PC value in this case, this instruction
422 will get executed, but then core will "jump" to the original branch target.
424 Whether current instruction is a delay-slot instruction or not is indicated
425 by DE bit in STATUS32 register indicates if current instruction is a delay
426 slot instruction. This bit is writable by debug host, which allows debug
427 host to prevent core from jumping after the delay slot instruction. It
428 also works in another direction: setting this bit will make core to treat
429 any current instructions as a delay slot instruction and to set PC to the
430 current value of BTA register.
432 To workaround issues with changing PC register while in delay slot
433 instruction, debugger should check for the STATUS32.DE bit and reset it if
434 it is set. No other change is required in this function. Most common
435 case, where this function might be required is calling inferior functions
436 from debugger. Generic GDB logic handles this pretty well: current values
437 of registers are stored, value of PC is changed (that is the job of this
438 function), and after inferior function is executed, GDB restores all
439 registers, include BTA and STATUS32, which also means that core is returned
440 to its original state of being halted on delay slot instructions.
442 This method is useless for ARC 600, because it doesn't have externally
443 exposed BTA register. In the case of ARC 600 it is impossible to restore
444 core to its state in all occasions thus core should never be halted (from
445 the perspective of debugger host) in the delay slot. */
448 arc_write_pc (struct regcache *regcache, CORE_ADDR new_pc)
450 struct gdbarch *gdbarch = regcache->arch ();
453 debug_printf ("arc: Writing PC, new value=%s\n",
454 paddress (gdbarch, new_pc));
456 regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch),
460 regcache_cooked_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch),
463 /* Mask for DE bit is 0x40. */
468 debug_printf ("arc: Changing PC while in delay slot. Will "
469 "reset STATUS32.DE bit to zero. Value of STATUS32 "
470 "register is 0x%s\n",
471 phex (status32, ARC_REGISTER_SIZE));
474 /* Reset bit and write to the cache. */
476 regcache_cooked_write_unsigned (regcache, gdbarch_ps_regnum (gdbarch),
481 /* Implement the "virtual_frame_pointer" gdbarch method.
483 According to ABI the FP (r27) is used to point to the middle of the current
484 stack frame, just below the saved FP and before local variables, register
485 spill area and outgoing args. However for optimization levels above O2 and
486 in any case in leaf functions, the frame pointer is usually not set at all.
487 The exception being when handling nested functions.
489 We use this function to return a "virtual" frame pointer, marking the start
490 of the current stack frame as a register-offset pair. If the FP is not
491 being used, then it should return SP, with an offset of the frame size.
493 The current implementation doesn't actually know the frame size, nor
494 whether the FP is actually being used, so for now we just return SP and an
495 offset of zero. This is no worse than other architectures, but is needed
496 to avoid assertion failures.
498 TODO: Can we determine the frame size to get a correct offset?
500 PC is a program counter where we need the virtual FP. REG_PTR is the base
501 register used for the virtual FP. OFFSET_PTR is the offset used for the
505 arc_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
506 int *reg_ptr, LONGEST *offset_ptr)
508 *reg_ptr = gdbarch_sp_regnum (gdbarch);
512 /* Implement the "dummy_id" gdbarch method.
514 Tear down a dummy frame created by arc_push_dummy_call (). This data has
515 to be constructed manually from the data in our hand. The stack pointer
516 and program counter can be obtained from the frame info. */
518 static struct frame_id
519 arc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
521 return frame_id_build (get_frame_sp (this_frame),
522 get_frame_pc (this_frame));
525 /* Implement the "push_dummy_call" gdbarch method.
529 This shows the layout of the stack frame for the general case of a
530 function call; a given function might not have a variable number of
531 arguments or local variables, or might not save any registers, so it would
532 not have the corresponding frame areas. Additionally, a leaf function
533 (i.e. one which calls no other functions) does not need to save the
534 contents of the BLINK register (which holds its return address), and a
535 function might not have a frame pointer.
537 The stack grows downward, so SP points below FP in memory; SP always
538 points to the last used word on the stack, not the first one.
541 | arg word N | | caller's
545 old SP ---> +-----------------------+ --+
549 | including fp, blink | |
551 new FP ---> +-----------------------+ | frame
561 new SP ---> +-----------------------+ --+
570 The list of arguments to be passed to a function is considered to be a
571 sequence of _N_ words (as though all the parameters were stored in order in
572 memory with each parameter occupying an integral number of words). Words
573 1..8 are passed in registers 0..7; if the function has more than 8 words of
574 arguments then words 9..@em N are passed on the stack in the caller's frame.
576 If the function has a variable number of arguments, e.g. it has a form such
577 as `function (p1, p2, ...);' and _P_ words are required to hold the values
578 of the named parameters (which are passed in registers 0..@em P -1), then
579 the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the
580 top of the frame so that the anonymous parameter words occupy a continuous
583 Any arguments are already in target byte order. We just need to store
586 BP_ADDR is the return address where breakpoint must be placed. NARGS is
587 the number of arguments to the function. ARGS is the arguments values (in
588 target byte order). SP is the Current value of SP register. STRUCT_RETURN
589 is TRUE if structures are returned by the function. STRUCT_ADDR is the
590 hidden address for returning a struct. Returns SP of a new frame. */
593 arc_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
594 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
595 struct value **args, CORE_ADDR sp, int struct_return,
596 CORE_ADDR struct_addr)
599 debug_printf ("arc: push_dummy_call (nargs = %d)\n", nargs);
601 int arg_reg = ARC_FIRST_ARG_REGNUM;
603 /* Push the return address. */
604 regcache_cooked_write_unsigned (regcache, ARC_BLINK_REGNUM, bp_addr);
606 /* Are we returning a value using a structure return instead of a normal
607 value return? If so, struct_addr is the address of the reserved space for
608 the return structure to be written on the stack, and that address is
609 passed to that function as a hidden first argument. */
612 /* Pass the return address in the first argument register. */
613 regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr);
616 debug_printf ("arc: struct return address %s passed in R%d",
617 print_core_address (gdbarch, struct_addr), arg_reg);
624 unsigned int total_space = 0;
626 /* How much space do the arguments occupy in total? Must round each
627 argument's size up to an integral number of words. */
628 for (int i = 0; i < nargs; i++)
630 unsigned int len = TYPE_LENGTH (value_type (args[i]));
631 unsigned int space = align_up (len, 4);
633 total_space += space;
636 debug_printf ("arc: arg %d: %u bytes -> %u\n", i, len, space);
639 /* Allocate a buffer to hold a memory image of the arguments. */
640 gdb_byte *memory_image = XCNEWVEC (gdb_byte, total_space);
642 /* Now copy all of the arguments into the buffer, correctly aligned. */
643 gdb_byte *data = memory_image;
644 for (int i = 0; i < nargs; i++)
646 unsigned int len = TYPE_LENGTH (value_type (args[i]));
647 unsigned int space = align_up (len, 4);
649 memcpy (data, value_contents (args[i]), (size_t) len);
651 debug_printf ("arc: copying arg %d, val 0x%08x, len %d to mem\n",
652 i, *((int *) value_contents (args[i])), len);
657 /* Now load as much as possible of the memory image into registers. */
659 while (arg_reg <= ARC_LAST_ARG_REGNUM)
662 debug_printf ("arc: passing 0x%02x%02x%02x%02x in register R%d\n",
663 data[0], data[1], data[2], data[3], arg_reg);
665 /* Note we don't use write_unsigned here, since that would convert
666 the byte order, but we are already in the correct byte order. */
667 regcache->cooked_write (arg_reg, data);
669 data += ARC_REGISTER_SIZE;
670 total_space -= ARC_REGISTER_SIZE;
672 /* All the data is now in registers. */
673 if (total_space == 0)
679 /* If there is any data left, push it onto the stack (in a single write
684 debug_printf ("arc: passing %d bytes on stack\n", total_space);
687 write_memory (sp, data, (int) total_space);
690 xfree (memory_image);
693 /* Finally, update the SP register. */
694 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
699 /* Implement the "push_dummy_code" gdbarch method.
701 We don't actually push any code. We just identify where a breakpoint can
702 be inserted to which we are can return and the resume address where we
705 ARC does not necessarily have an executable stack, so we can't put the
706 return breakpoint there. Instead we put it at the entry point of the
707 function. This means the SP is unchanged.
709 SP is a current stack pointer FUNADDR is an address of the function to be
710 called. ARGS is arguments to pass. NARGS is a number of args to pass.
711 VALUE_TYPE is a type of value returned. REAL_PC is a resume address when
712 the function is called. BP_ADDR is an address where breakpoint should be
713 set. Returns the updated stack pointer. */
716 arc_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
717 struct value **args, int nargs, struct type *value_type,
718 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
719 struct regcache *regcache)
722 *bp_addr = entry_point_address ();
726 /* Implement the "cannot_fetch_register" gdbarch method. */
729 arc_cannot_fetch_register (struct gdbarch *gdbarch, int regnum)
731 /* Assume that register is readable if it is unknown. LIMM and RESERVED are
732 not real registers, but specific register numbers. They are available as
733 regnums to align architectural register numbers with GDB internal regnums,
734 but they shouldn't appear in target descriptions generated by
738 case ARC_RESERVED_REGNUM:
739 case ARC_LIMM_REGNUM:
746 /* Implement the "cannot_store_register" gdbarch method. */
749 arc_cannot_store_register (struct gdbarch *gdbarch, int regnum)
751 /* Assume that register is writable if it is unknown. See comment in
752 arc_cannot_fetch_register about LIMM and RESERVED. */
755 case ARC_RESERVED_REGNUM:
756 case ARC_LIMM_REGNUM:
764 /* Get the return value of a function from the registers/memory used to
765 return it, according to the convention used by the ABI - 4-bytes values are
766 in the R0, while 8-byte values are in the R0-R1.
768 TODO: This implementation ignores the case of "complex double", where
769 according to ABI, value is returned in the R0-R3 registers.
771 TYPE is a returned value's type. VALBUF is a buffer for the returned
775 arc_extract_return_value (struct gdbarch *gdbarch, struct type *type,
776 struct regcache *regcache, gdb_byte *valbuf)
778 unsigned int len = TYPE_LENGTH (type);
781 debug_printf ("arc: extract_return_value\n");
783 if (len <= ARC_REGISTER_SIZE)
787 /* Get the return value from one register. */
788 regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &val);
789 store_unsigned_integer (valbuf, (int) len,
790 gdbarch_byte_order (gdbarch), val);
793 debug_printf ("arc: returning 0x%s\n", phex (val, ARC_REGISTER_SIZE));
795 else if (len <= ARC_REGISTER_SIZE * 2)
799 /* Get the return value from two registers. */
800 regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &low);
801 regcache_cooked_read_unsigned (regcache, ARC_R1_REGNUM, &high);
803 store_unsigned_integer (valbuf, ARC_REGISTER_SIZE,
804 gdbarch_byte_order (gdbarch), low);
805 store_unsigned_integer (valbuf + ARC_REGISTER_SIZE,
806 (int) len - ARC_REGISTER_SIZE,
807 gdbarch_byte_order (gdbarch), high);
810 debug_printf ("arc: returning 0x%s%s\n",
811 phex (high, ARC_REGISTER_SIZE),
812 phex (low, ARC_REGISTER_SIZE));
815 error (_("arc: extract_return_value: type length %u too large"), len);
819 /* Store the return value of a function into the registers/memory used to
820 return it, according to the convention used by the ABI.
822 TODO: This implementation ignores the case of "complex double", where
823 according to ABI, value is returned in the R0-R3 registers.
825 TYPE is a returned value's type. VALBUF is a buffer with the value to
829 arc_store_return_value (struct gdbarch *gdbarch, struct type *type,
830 struct regcache *regcache, const gdb_byte *valbuf)
832 unsigned int len = TYPE_LENGTH (type);
835 debug_printf ("arc: store_return_value\n");
837 if (len <= ARC_REGISTER_SIZE)
841 /* Put the return value into one register. */
842 val = extract_unsigned_integer (valbuf, (int) len,
843 gdbarch_byte_order (gdbarch));
844 regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, val);
847 debug_printf ("arc: storing 0x%s\n", phex (val, ARC_REGISTER_SIZE));
849 else if (len <= ARC_REGISTER_SIZE * 2)
853 /* Put the return value into two registers. */
854 low = extract_unsigned_integer (valbuf, ARC_REGISTER_SIZE,
855 gdbarch_byte_order (gdbarch));
856 high = extract_unsigned_integer (valbuf + ARC_REGISTER_SIZE,
857 (int) len - ARC_REGISTER_SIZE,
858 gdbarch_byte_order (gdbarch));
860 regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, low);
861 regcache_cooked_write_unsigned (regcache, ARC_R1_REGNUM, high);
864 debug_printf ("arc: storing 0x%s%s\n",
865 phex (high, ARC_REGISTER_SIZE),
866 phex (low, ARC_REGISTER_SIZE));
869 error (_("arc_store_return_value: type length too large."));
872 /* Implement the "get_longjmp_target" gdbarch method. */
875 arc_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
878 debug_printf ("arc: get_longjmp_target\n");
880 struct gdbarch *gdbarch = get_frame_arch (frame);
881 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
882 int pc_offset = tdep->jb_pc * ARC_REGISTER_SIZE;
883 gdb_byte buf[ARC_REGISTER_SIZE];
884 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, ARC_FIRST_ARG_REGNUM);
886 if (target_read_memory (jb_addr + pc_offset, buf, ARC_REGISTER_SIZE))
887 return 0; /* Failed to read from memory. */
889 *pc = extract_unsigned_integer (buf, ARC_REGISTER_SIZE,
890 gdbarch_byte_order (gdbarch));
894 /* Implement the "return_value" gdbarch method. */
896 static enum return_value_convention
897 arc_return_value (struct gdbarch *gdbarch, struct value *function,
898 struct type *valtype, struct regcache *regcache,
899 gdb_byte *readbuf, const gdb_byte *writebuf)
901 /* If the return type is a struct, or a union, or would occupy more than two
902 registers, the ABI uses the "struct return convention": the calling
903 function passes a hidden first parameter to the callee (in R0). That
904 parameter is the address at which the value being returned should be
905 stored. Otherwise, the result is returned in registers. */
906 int is_struct_return = (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
907 || TYPE_CODE (valtype) == TYPE_CODE_UNION
908 || TYPE_LENGTH (valtype) > 2 * ARC_REGISTER_SIZE);
911 debug_printf ("arc: return_value (readbuf = %s, writebuf = %s)\n",
912 host_address_to_string (readbuf),
913 host_address_to_string (writebuf));
915 if (writebuf != NULL)
917 /* Case 1. GDB should not ask us to set a struct return value: it
918 should know the struct return location and write the value there
920 gdb_assert (!is_struct_return);
921 arc_store_return_value (gdbarch, valtype, regcache, writebuf);
923 else if (readbuf != NULL)
925 /* Case 2. GDB should not ask us to get a struct return value: it
926 should know the struct return location and read the value from there
928 gdb_assert (!is_struct_return);
929 arc_extract_return_value (gdbarch, valtype, regcache, readbuf);
932 return (is_struct_return
933 ? RETURN_VALUE_STRUCT_CONVENTION
934 : RETURN_VALUE_REGISTER_CONVENTION);
937 /* Return the base address of the frame. For ARC, the base address is the
941 arc_frame_base_address (struct frame_info *this_frame, void **prologue_cache)
943 return (CORE_ADDR) get_frame_register_unsigned (this_frame, ARC_FP_REGNUM);
946 /* Helper function that returns valid pv_t for an instruction operand:
947 either a register or a constant. */
950 arc_pv_get_operand (pv_t *regs, const struct arc_instruction &insn, int operand)
952 if (insn.operands[operand].kind == ARC_OPERAND_KIND_REG)
953 return regs[insn.operands[operand].value];
955 return pv_constant (arc_insn_get_operand_value (insn, operand));
958 /* Determine whether the given disassembled instruction may be part of a
959 function prologue. If it is, the information in the frame unwind cache will
963 arc_is_in_prologue (struct gdbarch *gdbarch, const struct arc_instruction &insn,
964 pv_t *regs, struct pv_area *stack)
966 /* It might be that currently analyzed address doesn't contain an
967 instruction, hence INSN is not valid. It likely means that address points
968 to a data, non-initialized memory, or middle of a 32-bit instruction. In
969 practice this may happen if GDB connects to a remote target that has
970 non-zeroed memory. GDB would read PC value and would try to analyze
971 prologue, but there is no guarantee that memory contents at the address
972 specified in PC is address is a valid instruction. There is not much that
973 that can be done about that. */
977 /* Branch/jump or a predicated instruction. */
978 if (insn.is_control_flow || insn.condition_code != ARC_CC_AL)
981 /* Store of some register. May or may not update base address register. */
982 if (insn.insn_class == STORE || insn.insn_class == PUSH)
984 /* There is definetely at least one operand - register/value being
986 gdb_assert (insn.operands_count > 0);
988 /* Store at some constant address. */
989 if (insn.operands_count > 1
990 && insn.operands[1].kind != ARC_OPERAND_KIND_REG)
994 Mode Address used Writeback value
995 --------------------------------------------------
997 A/AW reg + offset reg + offset
999 AS reg + (offset << scaling) no
1001 "PUSH reg" is an alias to "ST.AW reg, [SP, -4]" encoding. However
1002 16-bit PUSH_S is a distinct instruction encoding, where offset and
1003 base register are implied through opcode. */
1005 /* Register with base memory address. */
1006 int base_reg = arc_insn_get_memory_base_reg (insn);
1008 /* Address where to write. arc_insn_get_memory_offset returns scaled
1009 value for ARC_WRITEBACK_AS. */
1011 if (insn.writeback_mode == ARC_WRITEBACK_AB)
1012 addr = regs[base_reg];
1014 addr = pv_add_constant (regs[base_reg],
1015 arc_insn_get_memory_offset (insn));
1017 if (stack->store_would_trash (addr))
1020 if (insn.data_size_mode != ARC_SCALING_D)
1022 /* Find the value being stored. */
1023 pv_t store_value = arc_pv_get_operand (regs, insn, 0);
1025 /* What is the size of a the stored value? */
1027 if (insn.data_size_mode == ARC_SCALING_B)
1029 else if (insn.data_size_mode == ARC_SCALING_H)
1032 size = ARC_REGISTER_SIZE;
1034 stack->store (addr, size, store_value);
1038 if (insn.operands[0].kind == ARC_OPERAND_KIND_REG)
1040 /* If this is a double store, than write N+1 register as well. */
1041 pv_t store_value1 = regs[insn.operands[0].value];
1042 pv_t store_value2 = regs[insn.operands[0].value + 1];
1043 stack->store (addr, ARC_REGISTER_SIZE, store_value1);
1044 stack->store (pv_add_constant (addr, ARC_REGISTER_SIZE),
1045 ARC_REGISTER_SIZE, store_value2);
1050 = pv_constant (arc_insn_get_operand_value (insn, 0));
1051 stack->store (addr, ARC_REGISTER_SIZE * 2, store_value);
1055 /* Is base register updated? */
1056 if (insn.writeback_mode == ARC_WRITEBACK_A
1057 || insn.writeback_mode == ARC_WRITEBACK_AB)
1058 regs[base_reg] = pv_add_constant (regs[base_reg],
1059 arc_insn_get_memory_offset (insn));
1063 else if (insn.insn_class == MOVE)
1065 gdb_assert (insn.operands_count == 2);
1067 /* Destination argument can be "0", so nothing will happen. */
1068 if (insn.operands[0].kind == ARC_OPERAND_KIND_REG)
1070 int dst_regnum = insn.operands[0].value;
1071 regs[dst_regnum] = arc_pv_get_operand (regs, insn, 1);
1075 else if (insn.insn_class == SUB)
1077 gdb_assert (insn.operands_count == 3);
1080 if (insn.operands[0].kind != ARC_OPERAND_KIND_REG)
1083 int dst_regnum = insn.operands[0].value;
1084 regs[dst_regnum] = pv_subtract (arc_pv_get_operand (regs, insn, 1),
1085 arc_pv_get_operand (regs, insn, 2));
1088 else if (insn.insn_class == ENTER)
1090 /* ENTER_S is a prologue-in-instruction - it saves all callee-saved
1091 registers according to given arguments thus greatly reducing code
1092 size. Which registers will be actually saved depends on arguments.
1094 ENTER_S {R13-...,FP,BLINK} stores registers in following order:
1105 There are up to three arguments for this opcode, as presented by ARC
1107 1) amount of general-purpose registers to be saved - this argument is
1108 always present even when it is 0;
1109 2) FP register number (27) if FP has to be stored, otherwise argument
1111 3) BLINK register number (31) if BLINK has to be stored, otherwise
1112 argument is not present. If both FP and BLINK are stored, then FP
1113 is present before BLINK in argument list. */
1114 gdb_assert (insn.operands_count > 0);
1116 int regs_saved = arc_insn_get_operand_value (insn, 0);
1119 if (insn.operands_count > 1)
1120 is_fp_saved = (insn.operands[1].value == ARC_FP_REGNUM);
1122 is_fp_saved = false;
1124 bool is_blink_saved;
1125 if (insn.operands_count > 1)
1126 is_blink_saved = (insn.operands[insn.operands_count - 1].value
1127 == ARC_BLINK_REGNUM);
1129 is_blink_saved = false;
1131 /* Amount of bytes to be allocated to store specified registers. */
1132 CORE_ADDR st_size = ((regs_saved + is_fp_saved + is_blink_saved)
1133 * ARC_REGISTER_SIZE);
1134 pv_t new_sp = pv_add_constant (regs[ARC_SP_REGNUM], -st_size);
1136 /* Assume that if the last register (closest to new SP) can be written,
1137 then it is possible to write all of them. */
1138 if (stack->store_would_trash (new_sp))
1141 /* Current store address. */
1142 pv_t addr = regs[ARC_SP_REGNUM];
1146 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE);
1147 stack->store (addr, ARC_REGISTER_SIZE, regs[ARC_FP_REGNUM]);
1150 /* Registers are stored in backward order: from GP (R26) to R13. */
1151 for (int i = ARC_R13_REGNUM + regs_saved - 1; i >= ARC_R13_REGNUM; i--)
1153 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE);
1154 stack->store (addr, ARC_REGISTER_SIZE, regs[i]);
1159 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE);
1160 stack->store (addr, ARC_REGISTER_SIZE,
1161 regs[ARC_BLINK_REGNUM]);
1164 gdb_assert (pv_is_identical (addr, new_sp));
1166 regs[ARC_SP_REGNUM] = new_sp;
1169 regs[ARC_FP_REGNUM] = regs[ARC_SP_REGNUM];
1174 /* Some other architectures, like nds32 or arm, try to continue as far as
1175 possible when building a prologue cache (as opposed to when skipping
1176 prologue), so that cache will be as full as possible. However current
1177 code for ARC doesn't recognize some instructions that may modify SP, like
1178 ADD, AND, OR, etc, hence there is no way to guarantee that SP wasn't
1179 clobbered by the skipped instruction. Potential existence of extension
1180 instruction, which may do anything they want makes this even more complex,
1181 so it is just better to halt on a first unrecognized instruction. */
1186 /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */
1188 static int ATTRIBUTE_PRINTF (2, 3)
1189 arc_fprintf_disasm (void *stream, const char *format, ...)
1194 struct disassemble_info
1195 arc_disassemble_info (struct gdbarch *gdbarch)
1197 struct disassemble_info di;
1198 init_disassemble_info (&di, &null_stream, arc_fprintf_disasm);
1199 di.arch = gdbarch_bfd_arch_info (gdbarch)->arch;
1200 di.mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1201 di.endian = gdbarch_byte_order (gdbarch);
1202 di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr,
1203 unsigned int len, struct disassemble_info *info)
1205 return target_read_code (memaddr, myaddr, len);
1210 /* Analyze the prologue and update the corresponding frame cache for the frame
1211 unwinder for unwinding frames that doesn't have debug info. In such
1212 situation GDB attempts to parse instructions in the prologue to understand
1213 where each register is saved.
1215 If CACHE is not NULL, then it will be filled with information about saved
1218 There are several variations of prologue which GDB may encouter. "Full"
1219 prologue looks like this:
1221 sub sp,sp,<imm> ; Space for variadic arguments.
1222 push blink ; Store return address.
1223 push r13 ; Store callee saved registers (up to R26/GP).
1225 push fp ; Store frame pointer.
1226 mov fp,sp ; Update frame pointer.
1227 sub sp,sp,<imm> ; Create space for local vars on the stack.
1229 Depending on compiler options lots of things may change:
1231 1) BLINK is not saved in leaf functions.
1232 2) Frame pointer is not saved and updated if -fomit-frame-pointer is used.
1233 3) 16-bit versions of those instructions may be used.
1234 4) Instead of a sequence of several push'es, compiler may instead prefer to
1235 do one subtract on stack pointer and then store registers using normal
1236 store, that doesn't update SP. Like this:
1239 sub sp,sp,8 ; Create space for calee-saved registers.
1240 st r13,[sp,4] ; Store callee saved registers (up to R26/GP).
1243 5) ENTER_S instruction can encode most of prologue sequence in one
1244 instruction (except for those subtracts for variadic arguments and local
1246 6) GCC may use "millicode" functions from libgcc to store callee-saved
1247 registers with minimal code-size requirements. This function currently
1248 doesn't support this.
1250 ENTRYPOINT is a function entry point where prologue starts.
1252 LIMIT_PC is a maximum possible end address of prologue (meaning address
1253 of first instruction after the prologue). It might also point to the middle
1254 of prologue if execution has been stopped by the breakpoint at this address
1255 - in this case debugger should analyze prologue only up to this address,
1256 because further instructions haven't been executed yet.
1258 Returns address of the first instruction after the prologue. */
1261 arc_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR entrypoint,
1262 const CORE_ADDR limit_pc, struct arc_frame_cache *cache)
1265 debug_printf ("arc: analyze_prologue (entrypoint=%s, limit_pc=%s)\n",
1266 paddress (gdbarch, entrypoint),
1267 paddress (gdbarch, limit_pc));
1269 /* Prologue values. Only core registers can be stored. */
1270 pv_t regs[ARC_LAST_CORE_REGNUM + 1];
1271 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1272 regs[i] = pv_register (i, 0);
1273 pv_area stack (ARC_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1275 CORE_ADDR current_prologue_end = entrypoint;
1277 /* Look at each instruction in the prologue. */
1278 while (current_prologue_end < limit_pc)
1280 struct arc_instruction insn;
1281 struct disassemble_info di = arc_disassemble_info (gdbarch);
1282 arc_insn_decode (current_prologue_end, &di, arc_delayed_print_insn,
1286 arc_insn_dump (insn);
1288 /* If this instruction is in the prologue, fields in the cache will be
1289 updated, and the saved registers mask may be updated. */
1290 if (!arc_is_in_prologue (gdbarch, insn, regs, &stack))
1292 /* Found an instruction that is not in the prologue. */
1294 debug_printf ("arc: End of prologue reached at address %s\n",
1295 paddress (gdbarch, insn.address));
1299 current_prologue_end = arc_insn_get_linear_next_pc (insn);
1304 /* Figure out if it is a frame pointer or just a stack pointer. */
1305 if (pv_is_register (regs[ARC_FP_REGNUM], ARC_SP_REGNUM))
1307 cache->frame_base_reg = ARC_FP_REGNUM;
1308 cache->frame_base_offset = -regs[ARC_FP_REGNUM].k;
1312 cache->frame_base_reg = ARC_SP_REGNUM;
1313 cache->frame_base_offset = -regs[ARC_SP_REGNUM].k;
1316 /* Assign offset from old SP to all saved registers. */
1317 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1320 if (stack.find_reg (gdbarch, i, &offset))
1321 cache->saved_regs[i].addr = offset;
1325 return current_prologue_end;
1328 /* Estimated maximum prologue length in bytes. This should include:
1329 1) Store instruction for each callee-saved register (R25 - R13 + 1)
1330 2) Two instructions for FP
1332 4) Three substract instructions for SP (for variadic args, for
1333 callee saved regs and for local vars) and assuming that those SUB use
1334 long-immediate (hence double length).
1335 5) Stores of arguments registers are considered part of prologue too
1337 This is quite an extreme case, because even with -O0 GCC will collapse first
1338 two SUBs into one and long immediate values are quite unlikely to appear in
1339 this case, but still better to overshoot a bit - prologue analysis will
1340 anyway stop at the first instruction that doesn't fit prologue, so this
1341 limit will be rarely reached. */
1343 const static int MAX_PROLOGUE_LENGTH
1344 = 4 * (ARC_R25_REGNUM - ARC_R13_REGNUM + 1 + 2 + 1 + 6
1345 + ARC_LAST_ARG_REGNUM - ARC_FIRST_ARG_REGNUM + 1);
1347 /* Implement the "skip_prologue" gdbarch method.
1349 Skip the prologue for the function at PC. This is done by checking from
1350 the line information read from the DWARF, if possible; otherwise, we scan
1351 the function prologue to find its end. */
1354 arc_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1357 debug_printf ("arc: skip_prologue\n");
1359 CORE_ADDR func_addr;
1360 const char *func_name;
1362 /* See what the symbol table says. */
1363 if (find_pc_partial_function (pc, &func_name, &func_addr, NULL))
1365 /* Found a function. */
1366 CORE_ADDR postprologue_pc
1367 = skip_prologue_using_sal (gdbarch, func_addr);
1369 if (postprologue_pc != 0)
1370 return std::max (pc, postprologue_pc);
1373 /* No prologue info in symbol table, have to analyze prologue. */
1375 /* Find an upper limit on the function prologue using the debug
1376 information. If there is no debug information about prologue end, then
1377 skip_prologue_using_sal will return 0. */
1378 CORE_ADDR limit_pc = skip_prologue_using_sal (gdbarch, pc);
1380 /* If there is no debug information at all, it is required to give some
1381 semi-arbitrary hard limit on amount of bytes to scan during prologue
1384 limit_pc = pc + MAX_PROLOGUE_LENGTH;
1386 /* Find the address of the first instruction after the prologue by scanning
1387 through it - no other information is needed, so pass NULL as a cache. */
1388 return arc_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1391 /* Implement the "print_insn" gdbarch method.
1393 arc_get_disassembler () may return different functions depending on bfd
1394 type, so it is not possible to pass print_insn directly to
1395 set_gdbarch_print_insn (). Instead this wrapper function is used. It also
1396 may be used by other functions to get disassemble_info for address. It is
1397 important to note, that those print_insn from opcodes always print
1398 instruction to the stream specified in the INFO. If this is not desired,
1399 then either `print_insn` function in INFO should be set to some function
1400 that will not print, or `stream` should be different from standard
1404 arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info)
1406 /* Standard BFD "machine number" field allows libocodes disassembler to
1407 distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM
1408 and HS, which have some difference between. There are two ways to specify
1409 what is the target core:
1410 1) via the disassemble_info->disassembler_options;
1411 2) otherwise libopcodes will use private (architecture-specific) ELF
1414 Using disassembler_options is preferable, because it comes directly from
1415 GDBserver which scanned an actual ARC core identification info. However,
1416 not all GDBservers report core architecture, so as a fallback GDB still
1417 should support analysis of ELF header. The libopcodes disassembly code
1418 uses the section to find the BFD and the BFD to find the ELF header,
1419 therefore this function should set disassemble_info->section properly.
1421 disassembler_options was already set by non-target specific code with
1422 proper options obtained via gdbarch_disassembler_options ().
1424 This function might be called multiple times in a sequence, reusing same
1425 disassemble_info. */
1426 if ((info->disassembler_options == NULL) && (info->section == NULL))
1428 struct obj_section *s = find_pc_section (addr);
1430 info->section = s->the_bfd_section;
1433 return default_print_insn (addr, info);
1436 /* Baremetal breakpoint instructions.
1438 ARC supports both big- and little-endian. However, instructions for
1439 little-endian processors are encoded in the middle-endian: half-words are
1440 in big-endian, while bytes inside the half-words are in little-endian; data
1441 is represented in the "normal" little-endian. Big-endian processors treat
1442 data and code identically.
1444 Assuming the number 0x01020304, it will be presented this way:
1446 Address : N N+1 N+2 N+3
1447 little-endian : 0x04 0x03 0x02 0x01
1448 big-endian : 0x01 0x02 0x03 0x04
1449 ARC middle-endian : 0x02 0x01 0x04 0x03
1452 static const gdb_byte arc_brk_s_be[] = { 0x7f, 0xff };
1453 static const gdb_byte arc_brk_s_le[] = { 0xff, 0x7f };
1454 static const gdb_byte arc_brk_be[] = { 0x25, 0x6f, 0x00, 0x3f };
1455 static const gdb_byte arc_brk_le[] = { 0x6f, 0x25, 0x3f, 0x00 };
1457 /* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff
1458 (little endian) or 0xff7f (big endian). We used to insert BRK_S even
1459 instead of 32-bit instructions, which works mostly ok, unless breakpoint is
1460 inserted into delay slot instruction. In this case if branch is taken
1461 BLINK value will be set to address of instruction after delay slot, however
1462 if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S,
1463 then BLINK value will have an invalid value - it will point to the address
1464 after the BRK_S (which was there at the moment of branch execution) while
1465 it should point to the address after the 32-bit long instruction. To avoid
1466 such issues this function disassembles instruction at target location and
1469 ARC 600 supports only 16-bit BRK_S.
1471 NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S]
1472 is much better because it doesn't commit unlike TRAP_S, so it can be set in
1473 delay slots; however it cannot be used in user-mode, hence usage of TRAP_S
1474 in GDB for user-space. */
1476 /* Implement the "breakpoint_kind_from_pc" gdbarch method. */
1479 arc_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1481 size_t length_with_limm = gdb_insn_length (gdbarch, *pcptr);
1483 /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with
1484 BRK. LIMM is part of instruction length, so it can be either 4 or 8
1485 bytes for 32-bit instructions. */
1486 if ((length_with_limm == 4 || length_with_limm == 8)
1487 && !arc_mach_is_arc600 (gdbarch))
1488 return sizeof (arc_brk_le);
1490 return sizeof (arc_brk_s_le);
1493 /* Implement the "sw_breakpoint_from_kind" gdbarch method. */
1495 static const gdb_byte *
1496 arc_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1500 if (kind == sizeof (arc_brk_le))
1502 return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1508 return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1514 /* Implement the "unwind_pc" gdbarch method. */
1517 arc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1519 int pc_regnum = gdbarch_pc_regnum (gdbarch);
1520 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, pc_regnum);
1523 debug_printf ("arc: unwind PC: %s\n", paddress (gdbarch, pc));
1528 /* Implement the "unwind_sp" gdbarch method. */
1531 arc_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1533 int sp_regnum = gdbarch_sp_regnum (gdbarch);
1534 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, sp_regnum);
1537 debug_printf ("arc: unwind SP: %s\n", paddress (gdbarch, sp));
1542 /* Implement the "frame_align" gdbarch method. */
1545 arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1547 return align_down (sp, 4);
1550 /* Dump the frame info. Used for internal debugging only. */
1553 arc_print_frame_cache (struct gdbarch *gdbarch, const char *message,
1554 struct arc_frame_cache *cache, int addresses_known)
1556 debug_printf ("arc: frame_info %s\n", message);
1557 debug_printf ("arc: prev_sp = %s\n", paddress (gdbarch, cache->prev_sp));
1558 debug_printf ("arc: frame_base_reg = %i\n", cache->frame_base_reg);
1559 debug_printf ("arc: frame_base_offset = %s\n",
1560 plongest (cache->frame_base_offset));
1562 for (int i = 0; i <= ARC_BLINK_REGNUM; i++)
1564 if (trad_frame_addr_p (cache->saved_regs, i))
1565 debug_printf ("arc: saved register %s at %s %s\n",
1566 gdbarch_register_name (gdbarch, i),
1567 (addresses_known) ? "address" : "offset",
1568 paddress (gdbarch, cache->saved_regs[i].addr));
1572 /* Frame unwinder for normal frames. */
1574 static struct arc_frame_cache *
1575 arc_make_frame_cache (struct frame_info *this_frame)
1578 debug_printf ("arc: frame_cache\n");
1580 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1582 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1583 CORE_ADDR entrypoint, prologue_end;
1584 if (find_pc_partial_function (block_addr, NULL, &entrypoint, &prologue_end))
1586 struct symtab_and_line sal = find_pc_line (entrypoint, 0);
1587 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1589 /* No line info so use current PC. */
1590 prologue_end = prev_pc;
1591 else if (sal.end < prologue_end)
1592 /* The next line begins after the function end. */
1593 prologue_end = sal.end;
1595 prologue_end = std::min (prologue_end, prev_pc);
1599 /* If find_pc_partial_function returned nothing then there is no symbol
1600 information at all for this PC. Currently it is assumed in this case
1601 that current PC is entrypoint to function and try to construct the
1602 frame from that. This is, probably, suboptimal, for example ARM
1603 assumes in this case that program is inside the normal frame (with
1604 frame pointer). ARC, perhaps, should try to do the same. */
1605 entrypoint = get_frame_register_unsigned (this_frame,
1606 gdbarch_pc_regnum (gdbarch));
1607 prologue_end = entrypoint + MAX_PROLOGUE_LENGTH;
1610 /* Allocate new frame cache instance and space for saved register info.
1611 FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */
1612 struct arc_frame_cache *cache
1613 = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache);
1614 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1616 arc_analyze_prologue (gdbarch, entrypoint, prologue_end, cache);
1619 arc_print_frame_cache (gdbarch, "after prologue", cache, false);
1621 CORE_ADDR unwound_fb = get_frame_register_unsigned (this_frame,
1622 cache->frame_base_reg);
1623 if (unwound_fb == 0)
1625 cache->prev_sp = unwound_fb + cache->frame_base_offset;
1627 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1629 if (trad_frame_addr_p (cache->saved_regs, i))
1630 cache->saved_regs[i].addr += cache->prev_sp;
1634 arc_print_frame_cache (gdbarch, "after previous SP found", cache, true);
1639 /* Implement the "this_id" frame_unwind method. */
1642 arc_frame_this_id (struct frame_info *this_frame, void **this_cache,
1643 struct frame_id *this_id)
1646 debug_printf ("arc: frame_this_id\n");
1648 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1650 if (*this_cache == NULL)
1651 *this_cache = arc_make_frame_cache (this_frame);
1652 struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache);
1654 CORE_ADDR stack_addr = cache->prev_sp;
1656 /* There are 4 possible situation which decide how frame_id->code_addr is
1659 1) Function is compiled with option -g. Then frame_id will be created
1660 in dwarf_* function and not in this function. NB: even if target
1661 binary is compiled with -g, some std functions like __start and _init
1662 are not, so they still will follow one of the following choices.
1664 2) Function is compiled without -g and binary hasn't been stripped in
1665 any way. In this case GDB still has enough information to evaluate
1666 frame code_addr properly. This case is covered by call to
1669 3) Binary has been striped with option -g (strip debug symbols). In
1670 this case there is still enough symbols for get_frame_func () to work
1671 properly, so this case is also covered by it.
1673 4) Binary has been striped with option -s (strip all symbols). In this
1674 case GDB cannot get function start address properly, so we return current
1677 CORE_ADDR code_addr = get_frame_func (this_frame);
1679 code_addr = get_frame_register_unsigned (this_frame,
1680 gdbarch_pc_regnum (gdbarch));
1682 *this_id = frame_id_build (stack_addr, code_addr);
1685 /* Implement the "prev_register" frame_unwind method. */
1687 static struct value *
1688 arc_frame_prev_register (struct frame_info *this_frame,
1689 void **this_cache, int regnum)
1691 if (*this_cache == NULL)
1692 *this_cache = arc_make_frame_cache (this_frame);
1693 struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache);
1695 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1697 /* If we are asked to unwind the PC, then we need to return BLINK instead:
1698 the saved value of PC points into this frame's function's prologue, not
1699 the next frame's function's resume location. */
1700 if (regnum == gdbarch_pc_regnum (gdbarch))
1701 regnum = ARC_BLINK_REGNUM;
1703 /* SP is a special case - we should return prev_sp, because
1704 trad_frame_get_prev_register will return _current_ SP value.
1705 Alternatively we could have stored cache->prev_sp in the cache->saved
1706 regs, but here we follow the lead of AArch64, ARM and Xtensa and will
1707 leave that logic in this function, instead of prologue analyzers. That I
1708 think is a bit more clear as `saved_regs` should contain saved regs, not
1711 Because value has been computed, "got_constant" should be used, so that
1712 returned value will be a "not_lval" - immutable. */
1714 if (regnum == gdbarch_sp_regnum (gdbarch))
1715 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1717 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
1720 /* Implement the "init_reg" dwarf2_frame method. */
1723 arc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1724 struct dwarf2_frame_state_reg *reg,
1725 struct frame_info *info)
1727 if (regnum == gdbarch_pc_regnum (gdbarch))
1728 /* The return address column. */
1729 reg->how = DWARF2_FRAME_REG_RA;
1730 else if (regnum == gdbarch_sp_regnum (gdbarch))
1731 /* The call frame address. */
1732 reg->how = DWARF2_FRAME_REG_CFA;
1735 /* Structure defining the ARC ordinary frame unwind functions. Since we are
1736 the fallback unwinder, we use the default frame sniffer, which always
1737 accepts the frame. */
1739 static const struct frame_unwind arc_frame_unwind = {
1741 default_frame_unwind_stop_reason,
1743 arc_frame_prev_register,
1745 default_frame_sniffer,
1751 static const struct frame_base arc_normal_base = {
1753 arc_frame_base_address,
1754 arc_frame_base_address,
1755 arc_frame_base_address
1758 /* Initialize target description for the ARC.
1760 Returns TRUE if input tdesc was valid and in this case it will assign TDESC
1761 and TDESC_DATA output parameters. */
1764 arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
1765 struct tdesc_arch_data **tdesc_data)
1768 debug_printf ("arc: Target description initialization.\n");
1770 const struct target_desc *tdesc_loc = info.target_desc;
1772 /* Depending on whether this is ARCompact or ARCv2 we will assign
1773 different default registers sets (which will differ in exactly two core
1774 registers). GDB will also refuse to accept register feature from invalid
1775 ISA - v2 features can be used only with v2 ARChitecture. We read
1776 bfd_arch_info, which looks like to be a safe bet here, as it looks like it
1777 is always initialized even when we don't pass any elf file to GDB at all
1778 (it uses default arch in this case). Also GDB will call this function
1779 multiple times, and if XML target description file contains architecture
1780 specifications, then GDB will set this architecture to info.bfd_arch_info,
1781 overriding value from ELF file if they are different. That means that,
1782 where matters, this value is always our best guess on what CPU we are
1783 debugging. It has been noted that architecture specified in tdesc file
1784 has higher precedence over ELF and even "set architecture" - that is,
1785 using "set architecture" command will have no effect when tdesc has "arch"
1787 /* Cannot use arc_mach_is_arcv2 (), because gdbarch is not created yet. */
1788 const int is_arcv2 = (info.bfd_arch_info->mach == bfd_mach_arc_arcv2);
1790 const char *const *core_regs;
1791 const char *core_feature_name;
1793 /* If target doesn't provide a description - use default one. */
1794 if (!tdesc_has_registers (tdesc_loc))
1798 tdesc_loc = tdesc_arc_v2;
1800 debug_printf ("arc: Using default register set for ARC v2.\n");
1804 tdesc_loc = tdesc_arc_arcompact;
1806 debug_printf ("arc: Using default register set for ARCompact.\n");
1812 debug_printf ("arc: Using provided register set.\n");
1814 gdb_assert (tdesc_loc != NULL);
1816 /* Now we can search for base registers. Core registers can be either full
1817 or reduced. Summary:
1819 - core.v2 + aux-minimal
1820 - core-reduced.v2 + aux-minimal
1821 - core.arcompact + aux-minimal
1823 NB: It is entirely feasible to have ARCompact with reduced core regs, but
1824 we ignore that because GCC doesn't support that and at the same time
1825 ARCompact is considered obsolete, so there is not much reason to support
1827 const struct tdesc_feature *feature
1828 = tdesc_find_feature (tdesc_loc, core_v2_feature_name);
1829 if (feature != NULL)
1831 /* Confirm that register and architecture match, to prevent accidents in
1832 some situations. This code will trigger an error if:
1834 1. XML tdesc doesn't specify arch explicitly, registers are for arch
1835 X, but ELF specifies arch Y.
1837 2. XML tdesc specifies arch X, but contains registers for arch Y.
1839 It will not protect from case where XML or ELF specify arch X,
1840 registers are for the same arch X, but the real target is arch Y. To
1841 detect this case we need to check IDENTITY register. */
1844 arc_print (_("Error: ARC v2 target description supplied for "
1845 "non-ARCv2 target.\n"));
1849 is_reduced_rf = FALSE;
1850 core_feature_name = core_v2_feature_name;
1851 core_regs = core_v2_register_names;
1855 feature = tdesc_find_feature (tdesc_loc, core_reduced_v2_feature_name);
1856 if (feature != NULL)
1860 arc_print (_("Error: ARC v2 target description supplied for "
1861 "non-ARCv2 target.\n"));
1865 is_reduced_rf = TRUE;
1866 core_feature_name = core_reduced_v2_feature_name;
1867 core_regs = core_v2_register_names;
1871 feature = tdesc_find_feature (tdesc_loc,
1872 core_arcompact_feature_name);
1873 if (feature != NULL)
1877 arc_print (_("Error: ARCompact target description supplied "
1878 "for non-ARCompact target.\n"));
1882 is_reduced_rf = FALSE;
1883 core_feature_name = core_arcompact_feature_name;
1884 core_regs = core_arcompact_register_names;
1888 arc_print (_("Error: Couldn't find core register feature in "
1889 "supplied target description."));
1895 struct tdesc_arch_data *tdesc_data_loc = tdesc_data_alloc ();
1897 gdb_assert (feature != NULL);
1900 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1902 /* If rf16, then skip extra registers. */
1903 if (is_reduced_rf && ((i >= ARC_R4_REGNUM && i <= ARC_R9_REGNUM)
1904 || (i >= ARC_R16_REGNUM && i <= ARC_R25_REGNUM)))
1907 valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i,
1910 /* - Ignore errors in extension registers - they are optional.
1911 - Ignore missing ILINK because it doesn't make sense for Linux.
1912 - Ignore missing ILINK2 when architecture is ARCompact, because it
1913 doesn't make sense for Linux targets.
1915 In theory those optional registers should be in separate features, but
1916 that would create numerous but tiny features, which looks like an
1917 overengineering of a rather simple task. */
1918 if (!valid_p && (i <= ARC_SP_REGNUM || i == ARC_BLINK_REGNUM
1919 || i == ARC_LP_COUNT_REGNUM || i == ARC_PCL_REGNUM
1920 || (i == ARC_R30_REGNUM && is_arcv2)))
1922 arc_print (_("Error: Cannot find required register `%s' in "
1923 "feature `%s'.\n"), core_regs[i], core_feature_name);
1924 tdesc_data_cleanup (tdesc_data_loc);
1929 /* Mandatory AUX registeres are intentionally few and are common between
1930 ARCompact and ARC v2, so same code can be used for both. */
1931 feature = tdesc_find_feature (tdesc_loc, aux_minimal_feature_name);
1932 if (feature == NULL)
1934 arc_print (_("Error: Cannot find required feature `%s' in supplied "
1935 "target description.\n"), aux_minimal_feature_name);
1936 tdesc_data_cleanup (tdesc_data_loc);
1940 for (int i = ARC_FIRST_AUX_REGNUM; i <= ARC_LAST_AUX_REGNUM; i++)
1942 const char *name = aux_minimal_register_names[i - ARC_FIRST_AUX_REGNUM];
1943 valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, name);
1946 arc_print (_("Error: Cannot find required register `%s' "
1947 "in feature `%s'.\n"),
1948 name, tdesc_feature_name (feature));
1949 tdesc_data_cleanup (tdesc_data_loc);
1955 *tdesc_data = tdesc_data_loc;
1960 /* Implement the type_align gdbarch function. */
1963 arc_type_align (struct gdbarch *gdbarch, struct type *type)
1965 type = check_typedef (type);
1966 return std::min<ULONGEST> (4, TYPE_LENGTH (type));
1969 /* Implement the "init" gdbarch method. */
1971 static struct gdbarch *
1972 arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1974 const struct target_desc *tdesc;
1975 struct tdesc_arch_data *tdesc_data;
1978 debug_printf ("arc: Architecture initialization.\n");
1980 if (!arc_tdesc_init (info, &tdesc, &tdesc_data))
1983 /* Allocate the ARC-private target-dependent information structure, and the
1984 GDB target-independent information structure. */
1985 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
1986 tdep->jb_pc = -1; /* No longjmp support by default. */
1987 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
1990 set_gdbarch_short_bit (gdbarch, 16);
1991 set_gdbarch_int_bit (gdbarch, 32);
1992 set_gdbarch_long_bit (gdbarch, 32);
1993 set_gdbarch_long_long_bit (gdbarch, 64);
1994 set_gdbarch_type_align (gdbarch, arc_type_align);
1995 set_gdbarch_float_bit (gdbarch, 32);
1996 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1997 set_gdbarch_double_bit (gdbarch, 64);
1998 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1999 set_gdbarch_ptr_bit (gdbarch, 32);
2000 set_gdbarch_addr_bit (gdbarch, 32);
2001 set_gdbarch_char_signed (gdbarch, 0);
2003 set_gdbarch_write_pc (gdbarch, arc_write_pc);
2005 set_gdbarch_virtual_frame_pointer (gdbarch, arc_virtual_frame_pointer);
2007 /* tdesc_use_registers expects gdbarch_num_regs to return number of registers
2008 parsed by gdbarch_init, and then it will add all of the remaining
2009 registers and will increase number of registers. */
2010 set_gdbarch_num_regs (gdbarch, ARC_LAST_REGNUM + 1);
2011 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2012 set_gdbarch_sp_regnum (gdbarch, ARC_SP_REGNUM);
2013 set_gdbarch_pc_regnum (gdbarch, ARC_PC_REGNUM);
2014 set_gdbarch_ps_regnum (gdbarch, ARC_STATUS32_REGNUM);
2015 set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */
2017 set_gdbarch_dummy_id (gdbarch, arc_dummy_id);
2018 set_gdbarch_push_dummy_call (gdbarch, arc_push_dummy_call);
2019 set_gdbarch_push_dummy_code (gdbarch, arc_push_dummy_code);
2021 set_gdbarch_cannot_fetch_register (gdbarch, arc_cannot_fetch_register);
2022 set_gdbarch_cannot_store_register (gdbarch, arc_cannot_store_register);
2024 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2026 set_gdbarch_return_value (gdbarch, arc_return_value);
2028 set_gdbarch_skip_prologue (gdbarch, arc_skip_prologue);
2029 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2031 set_gdbarch_breakpoint_kind_from_pc (gdbarch, arc_breakpoint_kind_from_pc);
2032 set_gdbarch_sw_breakpoint_from_kind (gdbarch, arc_sw_breakpoint_from_kind);
2034 /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */
2035 if (!arc_mach_is_arc600 (gdbarch))
2036 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2038 set_gdbarch_decr_pc_after_break (gdbarch, 2);
2040 set_gdbarch_unwind_pc (gdbarch, arc_unwind_pc);
2041 set_gdbarch_unwind_sp (gdbarch, arc_unwind_sp);
2043 set_gdbarch_frame_align (gdbarch, arc_frame_align);
2045 set_gdbarch_print_insn (gdbarch, arc_delayed_print_insn);
2047 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2049 /* "nonsteppable" watchpoint means that watchpoint triggers before
2050 instruction is committed, therefore it is required to remove watchpoint
2051 to step though instruction that triggers it. ARC watchpoints trigger
2052 only after instruction is committed, thus there is no need to remove
2053 them. In fact on ARC watchpoint for memory writes may trigger with more
2054 significant delay, like one or two instructions, depending on type of
2055 memory where write is performed (CCM or external) and next instruction
2056 after the memory write. */
2057 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 0);
2059 /* This doesn't include possible long-immediate value. */
2060 set_gdbarch_max_insn_length (gdbarch, 4);
2062 /* Frame unwinders and sniffers. */
2063 dwarf2_frame_set_init_reg (gdbarch, arc_dwarf2_frame_init_reg);
2064 dwarf2_append_unwinders (gdbarch);
2065 frame_unwind_append_unwinder (gdbarch, &arc_frame_unwind);
2066 frame_base_set_default (gdbarch, &arc_normal_base);
2068 /* Setup stuff specific to a particular environment (baremetal or Linux).
2069 It can override functions set earlier. */
2070 gdbarch_init_osabi (info, gdbarch);
2072 if (tdep->jb_pc >= 0)
2073 set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target);
2075 /* Disassembler options. Enforce CPU if it was specified in XML target
2076 description, otherwise use default method of determining CPU (ELF private
2078 if (info.target_desc != NULL)
2080 const struct bfd_arch_info *tdesc_arch
2081 = tdesc_architecture (info.target_desc);
2082 if (tdesc_arch != NULL)
2084 xfree (arc_disassembler_options);
2085 /* FIXME: It is not really good to change disassembler options
2086 behind the scene, because that might override options
2087 specified by the user. However as of now ARC doesn't support
2088 `set disassembler-options' hence this code is the only place
2089 where options are changed. It also changes options for all
2090 existing gdbarches, which also can be problematic, if
2091 arc_gdbarch_init will start reusing existing gdbarch
2093 /* Target description specifies a BFD architecture, which is
2094 different from ARC cpu, as accepted by disassembler (and most
2095 other ARC tools), because cpu values are much more fine grained -
2096 there can be multiple cpu values per single BFD architecture. As
2097 a result this code should translate architecture to some cpu
2098 value. Since there is no info on exact cpu configuration, it is
2099 best to use the most feature-rich CPU, so that disassembler will
2100 recognize all instructions available to the specified
2102 switch (tdesc_arch->mach)
2104 case bfd_mach_arc_arc601:
2105 arc_disassembler_options = xstrdup ("cpu=arc601");
2107 case bfd_mach_arc_arc600:
2108 arc_disassembler_options = xstrdup ("cpu=arc600");
2110 case bfd_mach_arc_arc700:
2111 arc_disassembler_options = xstrdup ("cpu=arc700");
2113 case bfd_mach_arc_arcv2:
2114 /* Machine arcv2 has three arches: ARCv2, EM and HS; where ARCv2
2115 is treated as EM. */
2116 if (arc_arch_is_hs (tdesc_arch))
2117 arc_disassembler_options = xstrdup ("cpu=hs38_linux");
2119 arc_disassembler_options = xstrdup ("cpu=em4_fpuda");
2122 arc_disassembler_options = NULL;
2125 set_gdbarch_disassembler_options (gdbarch,
2126 &arc_disassembler_options);
2130 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2135 /* Implement the "dump_tdep" gdbarch method. */
2138 arc_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2140 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2142 fprintf_unfiltered (file, "arc_dump_tdep: jb_pc = %i\n", tdep->jb_pc);
2145 /* Wrapper for "maintenance print arc" list of commands. */
2148 maintenance_print_arc_command (const char *args, int from_tty)
2150 cmd_show_list (maintenance_print_arc_list, from_tty, "");
2153 /* This command accepts single argument - address of instruction to
2157 dump_arc_instruction_command (const char *args, int from_tty)
2160 if (args != NULL && strlen (args) > 0)
2161 val = evaluate_expression (parse_expression (args).get ());
2163 val = access_value_history (0);
2164 record_latest_value (val);
2166 CORE_ADDR address = value_as_address (val);
2167 struct arc_instruction insn;
2168 struct disassemble_info di = arc_disassemble_info (target_gdbarch ());
2169 arc_insn_decode (address, &di, arc_delayed_print_insn, &insn);
2170 arc_insn_dump (insn);
2174 _initialize_arc_tdep (void)
2176 gdbarch_register (bfd_arch_arc, arc_gdbarch_init, arc_dump_tdep);
2178 initialize_tdesc_arc_v2 ();
2179 initialize_tdesc_arc_arcompact ();
2181 /* Register ARC-specific commands with gdb. */
2183 /* Add root prefix command for "maintenance print arc" commands. */
2184 add_prefix_cmd ("arc", class_maintenance, maintenance_print_arc_command,
2185 _("ARC-specific maintenance commands for printing GDB "
2187 &maintenance_print_arc_list, "maintenance print arc ", 0,
2188 &maintenanceprintlist);
2190 add_cmd ("arc-instruction", class_maintenance,
2191 dump_arc_instruction_command,
2192 _("Dump arc_instruction structure for specified address."),
2193 &maintenance_print_arc_list);
2195 /* Debug internals for ARC GDB. */
2196 add_setshow_zinteger_cmd ("arc", class_maintenance,
2198 _("Set ARC specific debugging."),
2199 _("Show ARC specific debugging."),
2200 _("Non-zero enables ARC specific debugging."),
2201 NULL, NULL, &setdebuglist, &showdebuglist);