1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2012 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
52 /* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
54 returned by config.guess, and used as the name for the AMD64 port
55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
59 /* Register information. */
61 static const char *amd64_register_names[] =
63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
65 /* %r8 is indeed register number 8. */
66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
69 /* %st0 is register number 24. */
70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
73 /* %xmm0 is register number 40. */
74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
79 static const char *amd64_ymm_names[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
87 static const char *amd64_ymmh_names[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
95 /* The registers used to pass integer arguments during a function call. */
96 static int amd64_dummy_call_integer_regs[] =
98 AMD64_RDI_REGNUM, /* %rdi */
99 AMD64_RSI_REGNUM, /* %rsi */
100 AMD64_RDX_REGNUM, /* %rdx */
101 AMD64_RCX_REGNUM, /* %rcx */
106 /* DWARF Register Number Mapping as defined in the System V psABI,
109 static int amd64_dwarf_regmap[] =
111 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
112 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
113 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
114 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
116 /* Frame Pointer Register RBP. */
119 /* Stack Pointer Register RSP. */
122 /* Extended Integer Registers 8 - 15. */
123 8, 9, 10, 11, 12, 13, 14, 15,
125 /* Return Address RA. Mapped to RIP. */
128 /* SSE Registers 0 - 7. */
129 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
130 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
131 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
132 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
134 /* Extended SSE Registers 8 - 15. */
135 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
136 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
137 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
138 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
140 /* Floating Point Registers 0-7. */
141 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
142 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
143 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
144 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
146 /* Control and Status Flags Register. */
149 /* Selector Registers. */
159 /* Segment Base Address Registers. */
165 /* Special Selector Registers. */
169 /* Floating Point Control Registers. */
175 static const int amd64_dwarf_regmap_len =
176 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
178 /* Convert DWARF register number REG to the appropriate register
179 number used by GDB. */
182 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
185 int ymm0_regnum = tdep->ymm0_regnum;
188 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
189 regnum = amd64_dwarf_regmap[reg];
192 warning (_("Unmapped DWARF Register #%d encountered."), reg);
193 else if (ymm0_regnum >= 0
194 && i386_xmm_regnum_p (gdbarch, regnum))
195 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
200 /* Map architectural register numbers to gdb register numbers. */
202 static const int amd64_arch_regmap[16] =
204 AMD64_RAX_REGNUM, /* %rax */
205 AMD64_RCX_REGNUM, /* %rcx */
206 AMD64_RDX_REGNUM, /* %rdx */
207 AMD64_RBX_REGNUM, /* %rbx */
208 AMD64_RSP_REGNUM, /* %rsp */
209 AMD64_RBP_REGNUM, /* %rbp */
210 AMD64_RSI_REGNUM, /* %rsi */
211 AMD64_RDI_REGNUM, /* %rdi */
212 AMD64_R8_REGNUM, /* %r8 */
213 AMD64_R9_REGNUM, /* %r9 */
214 AMD64_R10_REGNUM, /* %r10 */
215 AMD64_R11_REGNUM, /* %r11 */
216 AMD64_R12_REGNUM, /* %r12 */
217 AMD64_R13_REGNUM, /* %r13 */
218 AMD64_R14_REGNUM, /* %r14 */
219 AMD64_R15_REGNUM /* %r15 */
222 static const int amd64_arch_regmap_len =
223 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
225 /* Convert architectural register number REG to the appropriate register
226 number used by GDB. */
229 amd64_arch_reg_to_regnum (int reg)
231 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
233 return amd64_arch_regmap[reg];
236 /* Register names for byte pseudo-registers. */
238 static const char *amd64_byte_names[] =
240 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
241 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
242 "ah", "bh", "ch", "dh"
245 /* Number of lower byte registers. */
246 #define AMD64_NUM_LOWER_BYTE_REGS 16
248 /* Register names for word pseudo-registers. */
250 static const char *amd64_word_names[] =
252 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
253 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
256 /* Register names for dword pseudo-registers. */
258 static const char *amd64_dword_names[] =
260 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
261 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
265 /* Return the name of register REGNUM. */
268 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
270 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
271 if (i386_byte_regnum_p (gdbarch, regnum))
272 return amd64_byte_names[regnum - tdep->al_regnum];
273 else if (i386_ymm_regnum_p (gdbarch, regnum))
274 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
275 else if (i386_word_regnum_p (gdbarch, regnum))
276 return amd64_word_names[regnum - tdep->ax_regnum];
277 else if (i386_dword_regnum_p (gdbarch, regnum))
278 return amd64_dword_names[regnum - tdep->eax_regnum];
280 return i386_pseudo_register_name (gdbarch, regnum);
283 static struct value *
284 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
285 struct regcache *regcache,
288 gdb_byte raw_buf[MAX_REGISTER_SIZE];
289 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
290 enum register_status status;
291 struct value *result_value;
294 result_value = allocate_value (register_type (gdbarch, regnum));
295 VALUE_LVAL (result_value) = lval_register;
296 VALUE_REGNUM (result_value) = regnum;
297 buf = value_contents_raw (result_value);
299 if (i386_byte_regnum_p (gdbarch, regnum))
301 int gpnum = regnum - tdep->al_regnum;
303 /* Extract (always little endian). */
304 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
306 /* Special handling for AH, BH, CH, DH. */
307 status = regcache_raw_read (regcache,
308 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
310 if (status == REG_VALID)
311 memcpy (buf, raw_buf + 1, 1);
313 mark_value_bytes_unavailable (result_value, 0,
314 TYPE_LENGTH (value_type (result_value)));
318 status = regcache_raw_read (regcache, gpnum, raw_buf);
319 if (status == REG_VALID)
320 memcpy (buf, raw_buf, 1);
322 mark_value_bytes_unavailable (result_value, 0,
323 TYPE_LENGTH (value_type (result_value)));
326 else if (i386_dword_regnum_p (gdbarch, regnum))
328 int gpnum = regnum - tdep->eax_regnum;
329 /* Extract (always little endian). */
330 status = regcache_raw_read (regcache, gpnum, raw_buf);
331 if (status == REG_VALID)
332 memcpy (buf, raw_buf, 4);
334 mark_value_bytes_unavailable (result_value, 0,
335 TYPE_LENGTH (value_type (result_value)));
338 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
345 amd64_pseudo_register_write (struct gdbarch *gdbarch,
346 struct regcache *regcache,
347 int regnum, const gdb_byte *buf)
349 gdb_byte raw_buf[MAX_REGISTER_SIZE];
350 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
352 if (i386_byte_regnum_p (gdbarch, regnum))
354 int gpnum = regnum - tdep->al_regnum;
356 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
358 /* Read ... AH, BH, CH, DH. */
359 regcache_raw_read (regcache,
360 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
361 /* ... Modify ... (always little endian). */
362 memcpy (raw_buf + 1, buf, 1);
364 regcache_raw_write (regcache,
365 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
370 regcache_raw_read (regcache, gpnum, raw_buf);
371 /* ... Modify ... (always little endian). */
372 memcpy (raw_buf, buf, 1);
374 regcache_raw_write (regcache, gpnum, raw_buf);
377 else if (i386_dword_regnum_p (gdbarch, regnum))
379 int gpnum = regnum - tdep->eax_regnum;
382 regcache_raw_read (regcache, gpnum, raw_buf);
383 /* ... Modify ... (always little endian). */
384 memcpy (raw_buf, buf, 4);
386 regcache_raw_write (regcache, gpnum, raw_buf);
389 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
394 /* Return the union class of CLASS1 and CLASS2. See the psABI for
397 static enum amd64_reg_class
398 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
400 /* Rule (a): If both classes are equal, this is the resulting class. */
401 if (class1 == class2)
404 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
405 is the other class. */
406 if (class1 == AMD64_NO_CLASS)
408 if (class2 == AMD64_NO_CLASS)
411 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
412 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
415 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
416 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
417 return AMD64_INTEGER;
419 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
420 MEMORY is used as class. */
421 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
422 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
423 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
426 /* Rule (f): Otherwise class SSE is used. */
430 /* Return non-zero if TYPE is a non-POD structure or union type. */
433 amd64_non_pod_p (struct type *type)
435 /* ??? A class with a base class certainly isn't POD, but does this
436 catch all non-POD structure types? */
437 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
443 /* Classify TYPE according to the rules for aggregate (structures and
444 arrays) and union types, and store the result in CLASS. */
447 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
449 int len = TYPE_LENGTH (type);
451 /* 1. If the size of an object is larger than two eightbytes, or in
452 C++, is a non-POD structure or union type, or contains
453 unaligned fields, it has class memory. */
454 if (len > 16 || amd64_non_pod_p (type))
456 class[0] = class[1] = AMD64_MEMORY;
460 /* 2. Both eightbytes get initialized to class NO_CLASS. */
461 class[0] = class[1] = AMD64_NO_CLASS;
463 /* 3. Each field of an object is classified recursively so that
464 always two fields are considered. The resulting class is
465 calculated according to the classes of the fields in the
468 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
470 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
472 /* All fields in an array have the same type. */
473 amd64_classify (subtype, class);
474 if (len > 8 && class[1] == AMD64_NO_CLASS)
481 /* Structure or union. */
482 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
483 || TYPE_CODE (type) == TYPE_CODE_UNION);
485 for (i = 0; i < TYPE_NFIELDS (type); i++)
487 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
488 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
489 enum amd64_reg_class subclass[2];
490 int bitsize = TYPE_FIELD_BITSIZE (type, i);
494 bitsize = TYPE_LENGTH (subtype) * 8;
495 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
497 /* Ignore static fields. */
498 if (field_is_static (&TYPE_FIELD (type, i)))
501 gdb_assert (pos == 0 || pos == 1);
503 amd64_classify (subtype, subclass);
504 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
505 if (bitsize <= 64 && pos == 0 && endpos == 1)
506 /* This is a bit of an odd case: We have a field that would
507 normally fit in one of the two eightbytes, except that
508 it is placed in a way that this field straddles them.
509 This has been seen with a structure containing an array.
511 The ABI is a bit unclear in this case, but we assume that
512 this field's class (stored in subclass[0]) must also be merged
513 into class[1]. In other words, our field has a piece stored
514 in the second eight-byte, and thus its class applies to
515 the second eight-byte as well.
517 In the case where the field length exceeds 8 bytes,
518 it should not be necessary to merge the field class
519 into class[1]. As LEN > 8, subclass[1] is necessarily
520 different from AMD64_NO_CLASS. If subclass[1] is equal
521 to subclass[0], then the normal class[1]/subclass[1]
522 merging will take care of everything. For subclass[1]
523 to be different from subclass[0], I can only see the case
524 where we have a SSE/SSEUP or X87/X87UP pair, which both
525 use up all 16 bytes of the aggregate, and are already
526 handled just fine (because each portion sits on its own
528 class[1] = amd64_merge_classes (class[1], subclass[0]);
530 class[1] = amd64_merge_classes (class[1], subclass[1]);
534 /* 4. Then a post merger cleanup is done: */
536 /* Rule (a): If one of the classes is MEMORY, the whole argument is
538 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
539 class[0] = class[1] = AMD64_MEMORY;
541 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
543 if (class[0] == AMD64_SSEUP)
544 class[0] = AMD64_SSE;
545 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
546 class[1] = AMD64_SSE;
549 /* Classify TYPE, and store the result in CLASS. */
552 amd64_classify (struct type *type, enum amd64_reg_class class[2])
554 enum type_code code = TYPE_CODE (type);
555 int len = TYPE_LENGTH (type);
557 class[0] = class[1] = AMD64_NO_CLASS;
559 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
560 long, long long, and pointers are in the INTEGER class. Similarly,
561 range types, used by languages such as Ada, are also in the INTEGER
563 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
564 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
565 || code == TYPE_CODE_CHAR
566 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
567 && (len == 1 || len == 2 || len == 4 || len == 8))
568 class[0] = AMD64_INTEGER;
570 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
572 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
573 && (len == 4 || len == 8))
575 class[0] = AMD64_SSE;
577 /* Arguments of types __float128, _Decimal128 and __m128 are split into
578 two halves. The least significant ones belong to class SSE, the most
579 significant one to class SSEUP. */
580 else if (code == TYPE_CODE_DECFLOAT && len == 16)
581 /* FIXME: __float128, __m128. */
582 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
584 /* The 64-bit mantissa of arguments of type long double belongs to
585 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
587 else if (code == TYPE_CODE_FLT && len == 16)
588 /* Class X87 and X87UP. */
589 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
592 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
593 || code == TYPE_CODE_UNION)
594 amd64_classify_aggregate (type, class);
597 static enum return_value_convention
598 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
599 struct type *type, struct regcache *regcache,
600 gdb_byte *readbuf, const gdb_byte *writebuf)
602 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
603 enum amd64_reg_class class[2];
604 int len = TYPE_LENGTH (type);
605 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
606 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
611 gdb_assert (!(readbuf && writebuf));
612 gdb_assert (tdep->classify);
614 /* 1. Classify the return type with the classification algorithm. */
615 tdep->classify (type, class);
617 /* 2. If the type has class MEMORY, then the caller provides space
618 for the return value and passes the address of this storage in
619 %rdi as if it were the first argument to the function. In effect,
620 this address becomes a hidden first argument.
622 On return %rax will contain the address that has been passed in
623 by the caller in %rdi. */
624 if (class[0] == AMD64_MEMORY)
626 /* As indicated by the comment above, the ABI guarantees that we
627 can always find the return value just after the function has
634 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
635 read_memory (addr, readbuf, TYPE_LENGTH (type));
638 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
641 gdb_assert (class[1] != AMD64_MEMORY);
642 gdb_assert (len <= 16);
644 for (i = 0; len > 0; i++, len -= 8)
652 /* 3. If the class is INTEGER, the next available register
653 of the sequence %rax, %rdx is used. */
654 regnum = integer_regnum[integer_reg++];
658 /* 4. If the class is SSE, the next available SSE register
659 of the sequence %xmm0, %xmm1 is used. */
660 regnum = sse_regnum[sse_reg++];
664 /* 5. If the class is SSEUP, the eightbyte is passed in the
665 upper half of the last used SSE register. */
666 gdb_assert (sse_reg > 0);
667 regnum = sse_regnum[sse_reg - 1];
672 /* 6. If the class is X87, the value is returned on the X87
673 stack in %st0 as 80-bit x87 number. */
674 regnum = AMD64_ST0_REGNUM;
676 i387_return_value (gdbarch, regcache);
680 /* 7. If the class is X87UP, the value is returned together
681 with the previous X87 value in %st0. */
682 gdb_assert (i > 0 && class[0] == AMD64_X87);
683 regnum = AMD64_ST0_REGNUM;
692 gdb_assert (!"Unexpected register class.");
695 gdb_assert (regnum != -1);
698 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
701 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
705 return RETURN_VALUE_REGISTER_CONVENTION;
710 amd64_push_arguments (struct regcache *regcache, int nargs,
711 struct value **args, CORE_ADDR sp, int struct_return)
713 struct gdbarch *gdbarch = get_regcache_arch (regcache);
714 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
715 int *integer_regs = tdep->call_dummy_integer_regs;
716 int num_integer_regs = tdep->call_dummy_num_integer_regs;
718 static int sse_regnum[] =
720 /* %xmm0 ... %xmm7 */
721 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
722 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
723 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
724 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
726 struct value **stack_args = alloca (nargs * sizeof (struct value *));
727 /* An array that mirrors the stack_args array. For all arguments
728 that are passed by MEMORY, if that argument's address also needs
729 to be stored in a register, the ARG_ADDR_REGNO array will contain
730 that register number (or a negative value otherwise). */
731 int *arg_addr_regno = alloca (nargs * sizeof (int));
732 int num_stack_args = 0;
733 int num_elements = 0;
739 gdb_assert (tdep->classify);
741 /* Reserve a register for the "hidden" argument. */
745 for (i = 0; i < nargs; i++)
747 struct type *type = value_type (args[i]);
748 int len = TYPE_LENGTH (type);
749 enum amd64_reg_class class[2];
750 int needed_integer_regs = 0;
751 int needed_sse_regs = 0;
754 /* Classify argument. */
755 tdep->classify (type, class);
757 /* Calculate the number of integer and SSE registers needed for
759 for (j = 0; j < 2; j++)
761 if (class[j] == AMD64_INTEGER)
762 needed_integer_regs++;
763 else if (class[j] == AMD64_SSE)
767 /* Check whether enough registers are available, and if the
768 argument should be passed in registers at all. */
769 if (integer_reg + needed_integer_regs > num_integer_regs
770 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
771 || (needed_integer_regs == 0 && needed_sse_regs == 0))
773 /* The argument will be passed on the stack. */
774 num_elements += ((len + 7) / 8);
775 stack_args[num_stack_args] = args[i];
776 /* If this is an AMD64_MEMORY argument whose address must also
777 be passed in one of the integer registers, reserve that
778 register and associate this value to that register so that
779 we can store the argument address as soon as we know it. */
780 if (class[0] == AMD64_MEMORY
781 && tdep->memory_args_by_pointer
782 && integer_reg < tdep->call_dummy_num_integer_regs)
783 arg_addr_regno[num_stack_args] =
784 tdep->call_dummy_integer_regs[integer_reg++];
786 arg_addr_regno[num_stack_args] = -1;
791 /* The argument will be passed in registers. */
792 const gdb_byte *valbuf = value_contents (args[i]);
795 gdb_assert (len <= 16);
797 for (j = 0; len > 0; j++, len -= 8)
805 regnum = integer_regs[integer_reg++];
809 regnum = sse_regnum[sse_reg++];
813 gdb_assert (sse_reg > 0);
814 regnum = sse_regnum[sse_reg - 1];
819 gdb_assert (!"Unexpected register class.");
822 gdb_assert (regnum != -1);
823 memset (buf, 0, sizeof buf);
824 memcpy (buf, valbuf + j * 8, min (len, 8));
825 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
830 /* Allocate space for the arguments on the stack. */
831 sp -= num_elements * 8;
833 /* The psABI says that "The end of the input argument area shall be
834 aligned on a 16 byte boundary." */
837 /* Write out the arguments to the stack. */
838 for (i = 0; i < num_stack_args; i++)
840 struct type *type = value_type (stack_args[i]);
841 const gdb_byte *valbuf = value_contents (stack_args[i]);
842 int len = TYPE_LENGTH (type);
843 CORE_ADDR arg_addr = sp + element * 8;
845 write_memory (arg_addr, valbuf, len);
846 if (arg_addr_regno[i] >= 0)
848 /* We also need to store the address of that argument in
849 the given register. */
851 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
853 store_unsigned_integer (buf, 8, byte_order, arg_addr);
854 regcache_cooked_write (regcache, arg_addr_regno[i], buf);
856 element += ((len + 7) / 8);
859 /* The psABI says that "For calls that may call functions that use
860 varargs or stdargs (prototype-less calls or calls to functions
861 containing ellipsis (...) in the declaration) %al is used as
862 hidden argument to specify the number of SSE registers used. */
863 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
868 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
869 struct regcache *regcache, CORE_ADDR bp_addr,
870 int nargs, struct value **args, CORE_ADDR sp,
871 int struct_return, CORE_ADDR struct_addr)
873 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
874 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
877 /* Pass arguments. */
878 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
880 /* Pass "hidden" argument". */
883 /* The "hidden" argument is passed throught the first argument
885 const int arg_regnum = tdep->call_dummy_integer_regs[0];
887 store_unsigned_integer (buf, 8, byte_order, struct_addr);
888 regcache_cooked_write (regcache, arg_regnum, buf);
891 /* Reserve some memory on the stack for the integer-parameter registers,
892 if required by the ABI. */
893 if (tdep->integer_param_regs_saved_in_caller_frame)
894 sp -= tdep->call_dummy_num_integer_regs * 8;
896 /* Store return address. */
898 store_unsigned_integer (buf, 8, byte_order, bp_addr);
899 write_memory (sp, buf, 8);
901 /* Finally, update the stack pointer... */
902 store_unsigned_integer (buf, 8, byte_order, sp);
903 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
905 /* ...and fake a frame pointer. */
906 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
911 /* Displaced instruction handling. */
913 /* A partially decoded instruction.
914 This contains enough details for displaced stepping purposes. */
918 /* The number of opcode bytes. */
920 /* The offset of the rex prefix or -1 if not present. */
922 /* The offset to the first opcode byte. */
924 /* The offset to the modrm byte or -1 if not present. */
927 /* The raw instruction. */
931 struct displaced_step_closure
933 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
938 /* Details of the instruction. */
939 struct amd64_insn insn_details;
941 /* Amount of space allocated to insn_buf. */
944 /* The possibly modified insn.
945 This is a variable-length field. */
946 gdb_byte insn_buf[1];
949 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
950 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
951 at which point delete these in favor of libopcodes' versions). */
953 static const unsigned char onebyte_has_modrm[256] = {
954 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
955 /* ------------------------------- */
956 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
957 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
958 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
959 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
960 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
961 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
962 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
963 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
964 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
965 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
966 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
967 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
968 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
969 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
970 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
971 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
972 /* ------------------------------- */
973 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
976 static const unsigned char twobyte_has_modrm[256] = {
977 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
978 /* ------------------------------- */
979 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
980 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
981 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
982 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
983 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
984 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
985 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
986 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
987 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
988 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
989 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
990 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
991 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
992 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
993 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
994 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
995 /* ------------------------------- */
996 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
999 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1002 rex_prefix_p (gdb_byte pfx)
1004 return REX_PREFIX_P (pfx);
1007 /* Skip the legacy instruction prefixes in INSN.
1008 We assume INSN is properly sentineled so we don't have to worry
1009 about falling off the end of the buffer. */
1012 amd64_skip_prefixes (gdb_byte *insn)
1018 case DATA_PREFIX_OPCODE:
1019 case ADDR_PREFIX_OPCODE:
1020 case CS_PREFIX_OPCODE:
1021 case DS_PREFIX_OPCODE:
1022 case ES_PREFIX_OPCODE:
1023 case FS_PREFIX_OPCODE:
1024 case GS_PREFIX_OPCODE:
1025 case SS_PREFIX_OPCODE:
1026 case LOCK_PREFIX_OPCODE:
1027 case REPE_PREFIX_OPCODE:
1028 case REPNE_PREFIX_OPCODE:
1040 /* Return an integer register (other than RSP) that is unused as an input
1042 In order to not require adding a rex prefix if the insn doesn't already
1043 have one, the result is restricted to RAX ... RDI, sans RSP.
1044 The register numbering of the result follows architecture ordering,
1048 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1050 /* 1 bit for each reg */
1051 int used_regs_mask = 0;
1053 /* There can be at most 3 int regs used as inputs in an insn, and we have
1054 7 to choose from (RAX ... RDI, sans RSP).
1055 This allows us to take a conservative approach and keep things simple.
1056 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1057 that implicitly specify RAX. */
1060 used_regs_mask |= 1 << EAX_REG_NUM;
1061 /* Similarily avoid RDX, implicit operand in divides. */
1062 used_regs_mask |= 1 << EDX_REG_NUM;
1064 used_regs_mask |= 1 << ESP_REG_NUM;
1066 /* If the opcode is one byte long and there's no ModRM byte,
1067 assume the opcode specifies a register. */
1068 if (details->opcode_len == 1 && details->modrm_offset == -1)
1069 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1071 /* Mark used regs in the modrm/sib bytes. */
1072 if (details->modrm_offset != -1)
1074 int modrm = details->raw_insn[details->modrm_offset];
1075 int mod = MODRM_MOD_FIELD (modrm);
1076 int reg = MODRM_REG_FIELD (modrm);
1077 int rm = MODRM_RM_FIELD (modrm);
1078 int have_sib = mod != 3 && rm == 4;
1080 /* Assume the reg field of the modrm byte specifies a register. */
1081 used_regs_mask |= 1 << reg;
1085 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1086 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1087 used_regs_mask |= 1 << base;
1088 used_regs_mask |= 1 << idx;
1092 used_regs_mask |= 1 << rm;
1096 gdb_assert (used_regs_mask < 256);
1097 gdb_assert (used_regs_mask != 255);
1099 /* Finally, find a free reg. */
1103 for (i = 0; i < 8; ++i)
1105 if (! (used_regs_mask & (1 << i)))
1109 /* We shouldn't get here. */
1110 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1114 /* Extract the details of INSN that we need. */
1117 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1119 gdb_byte *start = insn;
1122 details->raw_insn = insn;
1124 details->opcode_len = -1;
1125 details->rex_offset = -1;
1126 details->opcode_offset = -1;
1127 details->modrm_offset = -1;
1129 /* Skip legacy instruction prefixes. */
1130 insn = amd64_skip_prefixes (insn);
1132 /* Skip REX instruction prefix. */
1133 if (rex_prefix_p (*insn))
1135 details->rex_offset = insn - start;
1139 details->opcode_offset = insn - start;
1141 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1143 /* Two or three-byte opcode. */
1145 need_modrm = twobyte_has_modrm[*insn];
1147 /* Check for three-byte opcode. */
1157 details->opcode_len = 3;
1160 details->opcode_len = 2;
1166 /* One-byte opcode. */
1167 need_modrm = onebyte_has_modrm[*insn];
1168 details->opcode_len = 1;
1174 details->modrm_offset = insn - start;
1178 /* Update %rip-relative addressing in INSN.
1180 %rip-relative addressing only uses a 32-bit displacement.
1181 32 bits is not enough to be guaranteed to cover the distance between where
1182 the real instruction is and where its copy is.
1183 Convert the insn to use base+disp addressing.
1184 We set base = pc + insn_length so we can leave disp unchanged. */
1187 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1188 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1191 const struct amd64_insn *insn_details = &dsc->insn_details;
1192 int modrm_offset = insn_details->modrm_offset;
1193 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1197 int arch_tmp_regno, tmp_regno;
1198 ULONGEST orig_value;
1200 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1203 /* Compute the rip-relative address. */
1204 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1205 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1206 dsc->max_len, from);
1207 rip_base = from + insn_length;
1209 /* We need a register to hold the address.
1210 Pick one not used in the insn.
1211 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1212 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1213 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1215 /* REX.B should be unset as we were using rip-relative addressing,
1216 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1217 if (insn_details->rex_offset != -1)
1218 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1220 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1221 dsc->tmp_regno = tmp_regno;
1222 dsc->tmp_save = orig_value;
1225 /* Convert the ModRM field to be base+disp. */
1226 dsc->insn_buf[modrm_offset] &= ~0xc7;
1227 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1229 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1231 if (debug_displaced)
1232 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1233 "displaced: using temp reg %d, old value %s, new value %s\n",
1234 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1235 paddress (gdbarch, rip_base));
1239 fixup_displaced_copy (struct gdbarch *gdbarch,
1240 struct displaced_step_closure *dsc,
1241 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1243 const struct amd64_insn *details = &dsc->insn_details;
1245 if (details->modrm_offset != -1)
1247 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1249 if ((modrm & 0xc7) == 0x05)
1251 /* The insn uses rip-relative addressing.
1253 fixup_riprel (gdbarch, dsc, from, to, regs);
1258 struct displaced_step_closure *
1259 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1260 CORE_ADDR from, CORE_ADDR to,
1261 struct regcache *regs)
1263 int len = gdbarch_max_insn_length (gdbarch);
1264 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1265 continually watch for running off the end of the buffer. */
1266 int fixup_sentinel_space = len;
1267 struct displaced_step_closure *dsc =
1268 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1269 gdb_byte *buf = &dsc->insn_buf[0];
1270 struct amd64_insn *details = &dsc->insn_details;
1273 dsc->max_len = len + fixup_sentinel_space;
1275 read_memory (from, buf, len);
1277 /* Set up the sentinel space so we don't have to worry about running
1278 off the end of the buffer. An excessive number of leading prefixes
1279 could otherwise cause this. */
1280 memset (buf + len, 0, fixup_sentinel_space);
1282 amd64_get_insn_details (buf, details);
1284 /* GDB may get control back after the insn after the syscall.
1285 Presumably this is a kernel bug.
1286 If this is a syscall, make sure there's a nop afterwards. */
1290 if (amd64_syscall_p (details, &syscall_length))
1291 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1294 /* Modify the insn to cope with the address where it will be executed from.
1295 In particular, handle any rip-relative addressing. */
1296 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1298 write_memory (to, buf, len);
1300 if (debug_displaced)
1302 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1303 paddress (gdbarch, from), paddress (gdbarch, to));
1304 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1311 amd64_absolute_jmp_p (const struct amd64_insn *details)
1313 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1315 if (insn[0] == 0xff)
1317 /* jump near, absolute indirect (/4) */
1318 if ((insn[1] & 0x38) == 0x20)
1321 /* jump far, absolute indirect (/5) */
1322 if ((insn[1] & 0x38) == 0x28)
1330 amd64_absolute_call_p (const struct amd64_insn *details)
1332 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1334 if (insn[0] == 0xff)
1336 /* Call near, absolute indirect (/2) */
1337 if ((insn[1] & 0x38) == 0x10)
1340 /* Call far, absolute indirect (/3) */
1341 if ((insn[1] & 0x38) == 0x18)
1349 amd64_ret_p (const struct amd64_insn *details)
1351 /* NOTE: gcc can emit "repz ; ret". */
1352 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1356 case 0xc2: /* ret near, pop N bytes */
1357 case 0xc3: /* ret near */
1358 case 0xca: /* ret far, pop N bytes */
1359 case 0xcb: /* ret far */
1360 case 0xcf: /* iret */
1369 amd64_call_p (const struct amd64_insn *details)
1371 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1373 if (amd64_absolute_call_p (details))
1376 /* call near, relative */
1377 if (insn[0] == 0xe8)
1383 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1384 length in bytes. Otherwise, return zero. */
1387 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1389 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1391 if (insn[0] == 0x0f && insn[1] == 0x05)
1400 /* Fix up the state of registers and memory after having single-stepped
1401 a displaced instruction. */
1404 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1405 struct displaced_step_closure *dsc,
1406 CORE_ADDR from, CORE_ADDR to,
1407 struct regcache *regs)
1409 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1410 /* The offset we applied to the instruction's address. */
1411 ULONGEST insn_offset = to - from;
1412 gdb_byte *insn = dsc->insn_buf;
1413 const struct amd64_insn *insn_details = &dsc->insn_details;
1415 if (debug_displaced)
1416 fprintf_unfiltered (gdb_stdlog,
1417 "displaced: fixup (%s, %s), "
1418 "insn = 0x%02x 0x%02x ...\n",
1419 paddress (gdbarch, from), paddress (gdbarch, to),
1422 /* If we used a tmp reg, restore it. */
1426 if (debug_displaced)
1427 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1428 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1429 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1432 /* The list of issues to contend with here is taken from
1433 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1434 Yay for Free Software! */
1436 /* Relocate the %rip back to the program's instruction stream,
1439 /* Except in the case of absolute or indirect jump or call
1440 instructions, or a return instruction, the new rip is relative to
1441 the displaced instruction; make it relative to the original insn.
1442 Well, signal handler returns don't need relocation either, but we use the
1443 value of %rip to recognize those; see below. */
1444 if (! amd64_absolute_jmp_p (insn_details)
1445 && ! amd64_absolute_call_p (insn_details)
1446 && ! amd64_ret_p (insn_details))
1451 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1453 /* A signal trampoline system call changes the %rip, resuming
1454 execution of the main program after the signal handler has
1455 returned. That makes them like 'return' instructions; we
1456 shouldn't relocate %rip.
1458 But most system calls don't, and we do need to relocate %rip.
1460 Our heuristic for distinguishing these cases: if stepping
1461 over the system call instruction left control directly after
1462 the instruction, the we relocate --- control almost certainly
1463 doesn't belong in the displaced copy. Otherwise, we assume
1464 the instruction has put control where it belongs, and leave
1465 it unrelocated. Goodness help us if there are PC-relative
1467 if (amd64_syscall_p (insn_details, &insn_len)
1468 && orig_rip != to + insn_len
1469 /* GDB can get control back after the insn after the syscall.
1470 Presumably this is a kernel bug.
1471 Fixup ensures its a nop, we add one to the length for it. */
1472 && orig_rip != to + insn_len + 1)
1474 if (debug_displaced)
1475 fprintf_unfiltered (gdb_stdlog,
1476 "displaced: syscall changed %%rip; "
1477 "not relocating\n");
1481 ULONGEST rip = orig_rip - insn_offset;
1483 /* If we just stepped over a breakpoint insn, we don't backup
1484 the pc on purpose; this is to match behaviour without
1487 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1489 if (debug_displaced)
1490 fprintf_unfiltered (gdb_stdlog,
1492 "relocated %%rip from %s to %s\n",
1493 paddress (gdbarch, orig_rip),
1494 paddress (gdbarch, rip));
1498 /* If the instruction was PUSHFL, then the TF bit will be set in the
1499 pushed value, and should be cleared. We'll leave this for later,
1500 since GDB already messes up the TF flag when stepping over a
1503 /* If the instruction was a call, the return address now atop the
1504 stack is the address following the copied instruction. We need
1505 to make it the address following the original instruction. */
1506 if (amd64_call_p (insn_details))
1510 const ULONGEST retaddr_len = 8;
1512 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1513 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1514 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
1515 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1517 if (debug_displaced)
1518 fprintf_unfiltered (gdb_stdlog,
1519 "displaced: relocated return addr at %s "
1521 paddress (gdbarch, rsp),
1522 paddress (gdbarch, retaddr));
1526 /* If the instruction INSN uses RIP-relative addressing, return the
1527 offset into the raw INSN where the displacement to be adjusted is
1528 found. Returns 0 if the instruction doesn't use RIP-relative
1532 rip_relative_offset (struct amd64_insn *insn)
1534 if (insn->modrm_offset != -1)
1536 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1538 if ((modrm & 0xc7) == 0x05)
1540 /* The displacement is found right after the ModRM byte. */
1541 return insn->modrm_offset + 1;
1549 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1551 target_write_memory (*to, buf, len);
1556 amd64_relocate_instruction (struct gdbarch *gdbarch,
1557 CORE_ADDR *to, CORE_ADDR oldloc)
1559 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1560 int len = gdbarch_max_insn_length (gdbarch);
1561 /* Extra space for sentinels. */
1562 int fixup_sentinel_space = len;
1563 gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1564 struct amd64_insn insn_details;
1566 LONGEST rel32, newrel;
1570 read_memory (oldloc, buf, len);
1572 /* Set up the sentinel space so we don't have to worry about running
1573 off the end of the buffer. An excessive number of leading prefixes
1574 could otherwise cause this. */
1575 memset (buf + len, 0, fixup_sentinel_space);
1578 amd64_get_insn_details (insn, &insn_details);
1580 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1582 /* Skip legacy instruction prefixes. */
1583 insn = amd64_skip_prefixes (insn);
1585 /* Adjust calls with 32-bit relative addresses as push/jump, with
1586 the address pushed being the location where the original call in
1587 the user program would return to. */
1588 if (insn[0] == 0xe8)
1590 gdb_byte push_buf[16];
1591 unsigned int ret_addr;
1593 /* Where "ret" in the original code will return to. */
1594 ret_addr = oldloc + insn_length;
1595 push_buf[0] = 0x68; /* pushq $... */
1596 memcpy (&push_buf[1], &ret_addr, 4);
1597 /* Push the push. */
1598 append_insns (to, 5, push_buf);
1600 /* Convert the relative call to a relative jump. */
1603 /* Adjust the destination offset. */
1604 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1605 newrel = (oldloc - *to) + rel32;
1606 store_signed_integer (insn + 1, 4, byte_order, newrel);
1608 if (debug_displaced)
1609 fprintf_unfiltered (gdb_stdlog,
1610 "Adjusted insn rel32=%s at %s to"
1611 " rel32=%s at %s\n",
1612 hex_string (rel32), paddress (gdbarch, oldloc),
1613 hex_string (newrel), paddress (gdbarch, *to));
1615 /* Write the adjusted jump into its displaced location. */
1616 append_insns (to, 5, insn);
1620 offset = rip_relative_offset (&insn_details);
1623 /* Adjust jumps with 32-bit relative addresses. Calls are
1624 already handled above. */
1625 if (insn[0] == 0xe9)
1627 /* Adjust conditional jumps. */
1628 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1634 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1635 newrel = (oldloc - *to) + rel32;
1636 store_signed_integer (insn + offset, 4, byte_order, newrel);
1637 if (debug_displaced)
1638 fprintf_unfiltered (gdb_stdlog,
1639 "Adjusted insn rel32=%s at %s to"
1640 " rel32=%s at %s\n",
1641 hex_string (rel32), paddress (gdbarch, oldloc),
1642 hex_string (newrel), paddress (gdbarch, *to));
1645 /* Write the adjusted instruction into its displaced location. */
1646 append_insns (to, insn_length, buf);
1650 /* The maximum number of saved registers. This should include %rip. */
1651 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1653 struct amd64_frame_cache
1658 CORE_ADDR sp_offset;
1661 /* Saved registers. */
1662 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1666 /* Do we have a frame? */
1670 /* Initialize a frame cache. */
1673 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1680 cache->sp_offset = -8;
1683 /* Saved registers. We initialize these to -1 since zero is a valid
1684 offset (that's where %rbp is supposed to be stored).
1685 The values start out as being offsets, and are later converted to
1686 addresses (at which point -1 is interpreted as an address, still meaning
1688 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1689 cache->saved_regs[i] = -1;
1690 cache->saved_sp = 0;
1691 cache->saved_sp_reg = -1;
1693 /* Frameless until proven otherwise. */
1694 cache->frameless_p = 1;
1697 /* Allocate and initialize a frame cache. */
1699 static struct amd64_frame_cache *
1700 amd64_alloc_frame_cache (void)
1702 struct amd64_frame_cache *cache;
1704 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1705 amd64_init_frame_cache (cache);
1709 /* GCC 4.4 and later, can put code in the prologue to realign the
1710 stack pointer. Check whether PC points to such code, and update
1711 CACHE accordingly. Return the first instruction after the code
1712 sequence or CURRENT_PC, whichever is smaller. If we don't
1713 recognize the code, return PC. */
1716 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1717 struct amd64_frame_cache *cache)
1719 /* There are 2 code sequences to re-align stack before the frame
1722 1. Use a caller-saved saved register:
1728 2. Use a callee-saved saved register:
1735 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1737 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1738 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1743 int offset, offset_and;
1745 if (target_read_memory (pc, buf, sizeof buf))
1748 /* Check caller-saved saved register. The first instruction has
1749 to be "leaq 8(%rsp), %reg". */
1750 if ((buf[0] & 0xfb) == 0x48
1755 /* MOD must be binary 10 and R/M must be binary 100. */
1756 if ((buf[2] & 0xc7) != 0x44)
1759 /* REG has register number. */
1760 reg = (buf[2] >> 3) & 7;
1762 /* Check the REX.R bit. */
1770 /* Check callee-saved saved register. The first instruction
1771 has to be "pushq %reg". */
1773 if ((buf[0] & 0xf8) == 0x50)
1775 else if ((buf[0] & 0xf6) == 0x40
1776 && (buf[1] & 0xf8) == 0x50)
1778 /* Check the REX.B bit. */
1779 if ((buf[0] & 1) != 0)
1788 reg += buf[offset] & 0x7;
1792 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1793 if ((buf[offset] & 0xfb) != 0x48
1794 || buf[offset + 1] != 0x8d
1795 || buf[offset + 3] != 0x24
1796 || buf[offset + 4] != 0x10)
1799 /* MOD must be binary 10 and R/M must be binary 100. */
1800 if ((buf[offset + 2] & 0xc7) != 0x44)
1803 /* REG has register number. */
1804 r = (buf[offset + 2] >> 3) & 7;
1806 /* Check the REX.R bit. */
1807 if (buf[offset] == 0x4c)
1810 /* Registers in pushq and leaq have to be the same. */
1817 /* Rigister can't be %rsp nor %rbp. */
1818 if (reg == 4 || reg == 5)
1821 /* The next instruction has to be "andq $-XXX, %rsp". */
1822 if (buf[offset] != 0x48
1823 || buf[offset + 2] != 0xe4
1824 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1827 offset_and = offset;
1828 offset += buf[offset + 1] == 0x81 ? 7 : 4;
1830 /* The next instruction has to be "pushq -8(%reg)". */
1832 if (buf[offset] == 0xff)
1834 else if ((buf[offset] & 0xf6) == 0x40
1835 && buf[offset + 1] == 0xff)
1837 /* Check the REX.B bit. */
1838 if ((buf[offset] & 0x1) != 0)
1845 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1847 if (buf[offset + 1] != 0xf8
1848 || (buf[offset] & 0xf8) != 0x70)
1851 /* R/M has register. */
1852 r += buf[offset] & 7;
1854 /* Registers in leaq and pushq have to be the same. */
1858 if (current_pc > pc + offset_and)
1859 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
1861 return min (pc + offset + 2, current_pc);
1864 /* Do a limited analysis of the prologue at PC and update CACHE
1865 accordingly. Bail out early if CURRENT_PC is reached. Return the
1866 address where the analysis stopped.
1868 We will handle only functions beginning with:
1871 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
1873 or (for the X32 ABI):
1876 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
1878 Any function that doesn't start with one of these sequences will be
1879 assumed to have no prologue and thus no valid frame pointer in
1883 amd64_analyze_prologue (struct gdbarch *gdbarch,
1884 CORE_ADDR pc, CORE_ADDR current_pc,
1885 struct amd64_frame_cache *cache)
1887 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1888 /* There are two variations of movq %rsp, %rbp. */
1889 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
1890 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
1891 /* Ditto for movl %esp, %ebp. */
1892 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
1893 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
1898 if (current_pc <= pc)
1901 pc = amd64_analyze_stack_align (pc, current_pc, cache);
1903 op = read_memory_unsigned_integer (pc, 1, byte_order);
1905 if (op == 0x55) /* pushq %rbp */
1907 /* Take into account that we've executed the `pushq %rbp' that
1908 starts this instruction sequence. */
1909 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
1910 cache->sp_offset += 8;
1912 /* If that's all, return now. */
1913 if (current_pc <= pc + 1)
1916 read_memory (pc + 1, buf, 3);
1918 /* Check for `movq %rsp, %rbp'. */
1919 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
1920 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
1922 /* OK, we actually have a frame. */
1923 cache->frameless_p = 0;
1927 /* For X32, also check for `movq %esp, %ebp'. */
1928 if (gdbarch_ptr_bit (gdbarch) == 32)
1930 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
1931 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
1933 /* OK, we actually have a frame. */
1934 cache->frameless_p = 0;
1945 /* Work around false termination of prologue - GCC PR debug/48827.
1947 START_PC is the first instruction of a function, PC is its minimal already
1948 determined advanced address. Function returns PC if it has nothing to do.
1952 <-- here is 0 lines advance - the false prologue end marker.
1953 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
1954 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
1955 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
1956 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
1957 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
1958 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
1959 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
1960 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
1964 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
1966 struct symtab_and_line start_pc_sal, next_sal;
1967 gdb_byte buf[4 + 8 * 7];
1973 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
1974 if (start_pc_sal.symtab == NULL
1975 || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6
1976 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
1979 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
1980 if (next_sal.line != start_pc_sal.line)
1983 /* START_PC can be from overlayed memory, ignored here. */
1984 if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0)
1988 if (buf[0] != 0x84 || buf[1] != 0xc0)
1995 for (xmmreg = 0; xmmreg < 8; xmmreg++)
1997 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
1998 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
1999 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2003 if ((buf[offset + 2] & 0xc0) == 0x40)
2005 /* 8-bit displacement. */
2009 else if ((buf[offset + 2] & 0xc0) == 0x80)
2011 /* 32-bit displacement. */
2019 if (offset - 4 != buf[3])
2022 return next_sal.end;
2025 /* Return PC of first real instruction. */
2028 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2030 struct amd64_frame_cache cache;
2033 amd64_init_frame_cache (&cache);
2034 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2036 if (cache.frameless_p)
2039 return amd64_skip_xmm_prologue (pc, start_pc);
2043 /* Normal frames. */
2046 amd64_frame_cache_1 (struct frame_info *this_frame,
2047 struct amd64_frame_cache *cache)
2049 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2050 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2054 cache->pc = get_frame_func (this_frame);
2056 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2059 if (cache->frameless_p)
2061 /* We didn't find a valid frame. If we're at the start of a
2062 function, or somewhere half-way its prologue, the function's
2063 frame probably hasn't been fully setup yet. Try to
2064 reconstruct the base address for the stack frame by looking
2065 at the stack pointer. For truly "frameless" functions this
2068 if (cache->saved_sp_reg != -1)
2070 /* Stack pointer has been saved. */
2071 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2072 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2074 /* We're halfway aligning the stack. */
2075 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2076 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2078 /* This will be added back below. */
2079 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2083 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2084 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2090 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2091 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2094 /* Now that we have the base address for the stack frame we can
2095 calculate the value of %rsp in the calling frame. */
2096 cache->saved_sp = cache->base + 16;
2098 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2099 frame we find it at the same offset from the reconstructed base
2100 address. If we're halfway aligning the stack, %rip is handled
2101 differently (see above). */
2102 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2103 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2105 /* Adjust all the saved registers such that they contain addresses
2106 instead of offsets. */
2107 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2108 if (cache->saved_regs[i] != -1)
2109 cache->saved_regs[i] += cache->base;
2114 static struct amd64_frame_cache *
2115 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2117 volatile struct gdb_exception ex;
2118 struct amd64_frame_cache *cache;
2123 cache = amd64_alloc_frame_cache ();
2124 *this_cache = cache;
2126 TRY_CATCH (ex, RETURN_MASK_ERROR)
2128 amd64_frame_cache_1 (this_frame, cache);
2130 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2131 throw_exception (ex);
2136 static enum unwind_stop_reason
2137 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2140 struct amd64_frame_cache *cache =
2141 amd64_frame_cache (this_frame, this_cache);
2144 return UNWIND_UNAVAILABLE;
2146 /* This marks the outermost frame. */
2147 if (cache->base == 0)
2148 return UNWIND_OUTERMOST;
2150 return UNWIND_NO_REASON;
2154 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2155 struct frame_id *this_id)
2157 struct amd64_frame_cache *cache =
2158 amd64_frame_cache (this_frame, this_cache);
2163 /* This marks the outermost frame. */
2164 if (cache->base == 0)
2167 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2170 static struct value *
2171 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2174 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2175 struct amd64_frame_cache *cache =
2176 amd64_frame_cache (this_frame, this_cache);
2178 gdb_assert (regnum >= 0);
2180 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2181 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2183 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2184 return frame_unwind_got_memory (this_frame, regnum,
2185 cache->saved_regs[regnum]);
2187 return frame_unwind_got_register (this_frame, regnum, regnum);
2190 static const struct frame_unwind amd64_frame_unwind =
2193 amd64_frame_unwind_stop_reason,
2194 amd64_frame_this_id,
2195 amd64_frame_prev_register,
2197 default_frame_sniffer
2200 /* Generate a bytecode expression to get the value of the saved PC. */
2203 amd64_gen_return_address (struct gdbarch *gdbarch,
2204 struct agent_expr *ax, struct axs_value *value,
2207 /* The following sequence assumes the traditional use of the base
2209 ax_reg (ax, AMD64_RBP_REGNUM);
2211 ax_simple (ax, aop_add);
2212 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2213 value->kind = axs_lvalue_memory;
2217 /* Signal trampolines. */
2219 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2220 64-bit variants. This would require using identical frame caches
2221 on both platforms. */
2223 static struct amd64_frame_cache *
2224 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2226 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2228 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2229 volatile struct gdb_exception ex;
2230 struct amd64_frame_cache *cache;
2238 cache = amd64_alloc_frame_cache ();
2240 TRY_CATCH (ex, RETURN_MASK_ERROR)
2242 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2243 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2245 addr = tdep->sigcontext_addr (this_frame);
2246 gdb_assert (tdep->sc_reg_offset);
2247 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2248 for (i = 0; i < tdep->sc_num_regs; i++)
2249 if (tdep->sc_reg_offset[i] != -1)
2250 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2254 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2255 throw_exception (ex);
2257 *this_cache = cache;
2261 static enum unwind_stop_reason
2262 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2265 struct amd64_frame_cache *cache =
2266 amd64_sigtramp_frame_cache (this_frame, this_cache);
2269 return UNWIND_UNAVAILABLE;
2271 return UNWIND_NO_REASON;
2275 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2276 void **this_cache, struct frame_id *this_id)
2278 struct amd64_frame_cache *cache =
2279 amd64_sigtramp_frame_cache (this_frame, this_cache);
2284 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2287 static struct value *
2288 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2289 void **this_cache, int regnum)
2291 /* Make sure we've initialized the cache. */
2292 amd64_sigtramp_frame_cache (this_frame, this_cache);
2294 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2298 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2299 struct frame_info *this_frame,
2302 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2304 /* We shouldn't even bother if we don't have a sigcontext_addr
2306 if (tdep->sigcontext_addr == NULL)
2309 if (tdep->sigtramp_p != NULL)
2311 if (tdep->sigtramp_p (this_frame))
2315 if (tdep->sigtramp_start != 0)
2317 CORE_ADDR pc = get_frame_pc (this_frame);
2319 gdb_assert (tdep->sigtramp_end != 0);
2320 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2327 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2330 amd64_sigtramp_frame_unwind_stop_reason,
2331 amd64_sigtramp_frame_this_id,
2332 amd64_sigtramp_frame_prev_register,
2334 amd64_sigtramp_frame_sniffer
2339 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2341 struct amd64_frame_cache *cache =
2342 amd64_frame_cache (this_frame, this_cache);
2347 static const struct frame_base amd64_frame_base =
2349 &amd64_frame_unwind,
2350 amd64_frame_base_address,
2351 amd64_frame_base_address,
2352 amd64_frame_base_address
2355 /* Normal frames, but in a function epilogue. */
2357 /* The epilogue is defined here as the 'ret' instruction, which will
2358 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2359 the function's stack frame. */
2362 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2365 struct symtab *symtab;
2367 symtab = find_pc_symtab (pc);
2368 if (symtab && symtab->epilogue_unwind_valid)
2371 if (target_read_memory (pc, &insn, 1))
2372 return 0; /* Can't read memory at pc. */
2374 if (insn != 0xc3) /* 'ret' instruction. */
2381 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2382 struct frame_info *this_frame,
2383 void **this_prologue_cache)
2385 if (frame_relative_level (this_frame) == 0)
2386 return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
2387 get_frame_pc (this_frame));
2392 static struct amd64_frame_cache *
2393 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2395 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2396 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2397 volatile struct gdb_exception ex;
2398 struct amd64_frame_cache *cache;
2404 cache = amd64_alloc_frame_cache ();
2405 *this_cache = cache;
2407 TRY_CATCH (ex, RETURN_MASK_ERROR)
2409 /* Cache base will be %esp plus cache->sp_offset (-8). */
2410 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2411 cache->base = extract_unsigned_integer (buf, 8,
2412 byte_order) + cache->sp_offset;
2414 /* Cache pc will be the frame func. */
2415 cache->pc = get_frame_pc (this_frame);
2417 /* The saved %esp will be at cache->base plus 16. */
2418 cache->saved_sp = cache->base + 16;
2420 /* The saved %eip will be at cache->base plus 8. */
2421 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2425 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2426 throw_exception (ex);
2431 static enum unwind_stop_reason
2432 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2435 struct amd64_frame_cache *cache
2436 = amd64_epilogue_frame_cache (this_frame, this_cache);
2439 return UNWIND_UNAVAILABLE;
2441 return UNWIND_NO_REASON;
2445 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2447 struct frame_id *this_id)
2449 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2455 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2458 static const struct frame_unwind amd64_epilogue_frame_unwind =
2461 amd64_epilogue_frame_unwind_stop_reason,
2462 amd64_epilogue_frame_this_id,
2463 amd64_frame_prev_register,
2465 amd64_epilogue_frame_sniffer
2468 static struct frame_id
2469 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2473 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2475 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2478 /* 16 byte align the SP per frame requirements. */
2481 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2483 return sp & -(CORE_ADDR)16;
2487 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2488 in the floating-point register set REGSET to register cache
2489 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2492 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2493 int regnum, const void *fpregs, size_t len)
2495 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2497 gdb_assert (len == tdep->sizeof_fpregset);
2498 amd64_supply_fxsave (regcache, regnum, fpregs);
2501 /* Collect register REGNUM from the register cache REGCACHE and store
2502 it in the buffer specified by FPREGS and LEN as described by the
2503 floating-point register set REGSET. If REGNUM is -1, do this for
2504 all registers in REGSET. */
2507 amd64_collect_fpregset (const struct regset *regset,
2508 const struct regcache *regcache,
2509 int regnum, void *fpregs, size_t len)
2511 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2513 gdb_assert (len == tdep->sizeof_fpregset);
2514 amd64_collect_fxsave (regcache, regnum, fpregs);
2517 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2520 amd64_supply_xstateregset (const struct regset *regset,
2521 struct regcache *regcache, int regnum,
2522 const void *xstateregs, size_t len)
2524 amd64_supply_xsave (regcache, regnum, xstateregs);
2527 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2530 amd64_collect_xstateregset (const struct regset *regset,
2531 const struct regcache *regcache,
2532 int regnum, void *xstateregs, size_t len)
2534 amd64_collect_xsave (regcache, regnum, xstateregs, 1);
2537 /* Return the appropriate register set for the core section identified
2538 by SECT_NAME and SECT_SIZE. */
2540 static const struct regset *
2541 amd64_regset_from_core_section (struct gdbarch *gdbarch,
2542 const char *sect_name, size_t sect_size)
2544 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2546 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2548 if (tdep->fpregset == NULL)
2549 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
2550 amd64_collect_fpregset);
2552 return tdep->fpregset;
2555 if (strcmp (sect_name, ".reg-xstate") == 0)
2557 if (tdep->xstateregset == NULL)
2558 tdep->xstateregset = regset_alloc (gdbarch,
2559 amd64_supply_xstateregset,
2560 amd64_collect_xstateregset);
2562 return tdep->xstateregset;
2565 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
2569 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2570 %rdi. We expect its value to be a pointer to the jmp_buf structure
2571 from which we extract the address that we will land at. This
2572 address is copied into PC. This routine returns non-zero on
2576 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2580 struct gdbarch *gdbarch = get_frame_arch (frame);
2581 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2582 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2584 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2585 longjmp will land. */
2586 if (jb_pc_offset == -1)
2589 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2590 jb_addr= extract_typed_address
2591 (buf, builtin_type (gdbarch)->builtin_data_ptr);
2592 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2595 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2600 static const int amd64_record_regmap[] =
2602 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2603 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2604 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2605 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2606 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2607 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2611 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2613 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2614 const struct target_desc *tdesc = info.target_desc;
2616 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2617 floating-point registers. */
2618 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2620 if (! tdesc_has_registers (tdesc))
2621 tdesc = tdesc_amd64;
2622 tdep->tdesc = tdesc;
2624 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2625 tdep->register_names = amd64_register_names;
2627 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2629 tdep->ymmh_register_names = amd64_ymmh_names;
2630 tdep->num_ymm_regs = 16;
2631 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
2634 tdep->num_byte_regs = 20;
2635 tdep->num_word_regs = 16;
2636 tdep->num_dword_regs = 16;
2637 /* Avoid wiring in the MMX registers for now. */
2638 tdep->num_mmx_regs = 0;
2640 set_gdbarch_pseudo_register_read_value (gdbarch,
2641 amd64_pseudo_register_read_value);
2642 set_gdbarch_pseudo_register_write (gdbarch,
2643 amd64_pseudo_register_write);
2645 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
2647 /* AMD64 has an FPU and 16 SSE registers. */
2648 tdep->st0_regnum = AMD64_ST0_REGNUM;
2649 tdep->num_xmm_regs = 16;
2651 /* This is what all the fuss is about. */
2652 set_gdbarch_long_bit (gdbarch, 64);
2653 set_gdbarch_long_long_bit (gdbarch, 64);
2654 set_gdbarch_ptr_bit (gdbarch, 64);
2656 /* In contrast to the i386, on AMD64 a `long double' actually takes
2657 up 128 bits, even though it's still based on the i387 extended
2658 floating-point format which has only 80 significant bits. */
2659 set_gdbarch_long_double_bit (gdbarch, 128);
2661 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
2663 /* Register numbers of various important registers. */
2664 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
2665 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
2666 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
2667 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
2669 /* The "default" register numbering scheme for AMD64 is referred to
2670 as the "DWARF Register Number Mapping" in the System V psABI.
2671 The preferred debugging format for all known AMD64 targets is
2672 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2673 DWARF-1), but we provide the same mapping just in case. This
2674 mapping is also used for stabs, which GCC does support. */
2675 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2676 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2678 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2679 be in use on any of the supported AMD64 targets. */
2681 /* Call dummy code. */
2682 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
2683 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
2684 set_gdbarch_frame_red_zone_size (gdbarch, 128);
2685 tdep->call_dummy_num_integer_regs =
2686 ARRAY_SIZE (amd64_dummy_call_integer_regs);
2687 tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs;
2688 tdep->classify = amd64_classify;
2690 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
2691 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
2692 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
2694 set_gdbarch_return_value (gdbarch, amd64_return_value);
2696 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
2698 tdep->record_regmap = amd64_record_regmap;
2700 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
2702 /* Hook the function epilogue frame unwinder. This unwinder is
2703 appended to the list first, so that it supercedes the other
2704 unwinders in function epilogues. */
2705 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
2707 /* Hook the prologue-based frame unwinders. */
2708 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
2709 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
2710 frame_base_set_default (gdbarch, &amd64_frame_base);
2712 /* If we have a register mapping, enable the generic core file support. */
2713 if (tdep->gregset_reg_offset)
2714 set_gdbarch_regset_from_core_section (gdbarch,
2715 amd64_regset_from_core_section);
2717 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
2719 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
2721 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
2723 /* SystemTap variables and functions. */
2724 set_gdbarch_stap_integer_prefix (gdbarch, "$");
2725 set_gdbarch_stap_register_prefix (gdbarch, "%");
2726 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
2727 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
2728 set_gdbarch_stap_is_single_operand (gdbarch,
2729 i386_stap_is_single_operand);
2730 set_gdbarch_stap_parse_special_token (gdbarch,
2731 i386_stap_parse_special_token);
2735 static struct type *
2736 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2738 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2740 switch (regnum - tdep->eax_regnum)
2742 case AMD64_RBP_REGNUM: /* %ebp */
2743 case AMD64_RSP_REGNUM: /* %esp */
2744 return builtin_type (gdbarch)->builtin_data_ptr;
2745 case AMD64_RIP_REGNUM: /* %eip */
2746 return builtin_type (gdbarch)->builtin_func_ptr;
2749 return i386_pseudo_register_type (gdbarch, regnum);
2753 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2755 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2756 const struct target_desc *tdesc = info.target_desc;
2758 amd64_init_abi (info, gdbarch);
2760 if (! tdesc_has_registers (tdesc))
2762 tdep->tdesc = tdesc;
2764 tdep->num_dword_regs = 17;
2765 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
2767 set_gdbarch_long_bit (gdbarch, 32);
2768 set_gdbarch_ptr_bit (gdbarch, 32);
2771 /* Provide a prototype to silence -Wmissing-prototypes. */
2772 void _initialize_amd64_tdep (void);
2775 _initialize_amd64_tdep (void)
2777 initialize_tdesc_amd64 ();
2778 initialize_tdesc_amd64_avx ();
2779 initialize_tdesc_x32 ();
2780 initialize_tdesc_x32_avx ();
2784 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2785 sense that the instruction pointer and data pointer are simply
2786 64-bit offsets into the code segment and the data segment instead
2787 of a selector offset pair. The functions below store the upper 32
2788 bits of these pointers (instead of just the 16-bits of the segment
2791 /* Fill register REGNUM in REGCACHE with the appropriate
2792 floating-point or SSE register value from *FXSAVE. If REGNUM is
2793 -1, do this for all registers. This function masks off any of the
2794 reserved bits in *FXSAVE. */
2797 amd64_supply_fxsave (struct regcache *regcache, int regnum,
2800 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2801 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2803 i387_supply_fxsave (regcache, regnum, fxsave);
2805 if (fxsave && gdbarch_ptr_bit (gdbarch) == 64)
2807 const gdb_byte *regs = fxsave;
2809 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2810 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
2811 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2812 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
2816 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
2819 amd64_supply_xsave (struct regcache *regcache, int regnum,
2822 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2823 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2825 i387_supply_xsave (regcache, regnum, xsave);
2827 if (xsave && gdbarch_ptr_bit (gdbarch) == 64)
2829 const gdb_byte *regs = xsave;
2831 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2832 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
2834 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2835 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
2840 /* Fill register REGNUM (if it is a floating-point or SSE register) in
2841 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
2842 all registers. This function doesn't touch any of the reserved
2846 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
2849 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2850 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2851 gdb_byte *regs = fxsave;
2853 i387_collect_fxsave (regcache, regnum, fxsave);
2855 if (gdbarch_ptr_bit (gdbarch) == 64)
2857 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2858 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
2859 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2860 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
2864 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
2867 amd64_collect_xsave (const struct regcache *regcache, int regnum,
2868 void *xsave, int gcore)
2870 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2871 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2872 gdb_byte *regs = xsave;
2874 i387_collect_xsave (regcache, regnum, xsave, gcore);
2876 if (gdbarch_ptr_bit (gdbarch) == 64)
2878 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2879 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
2881 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2882 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),