1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "opcode/i386.h"
26 #include "arch-utils.h"
28 #include "dummy-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
40 #include "gdb_assert.h"
41 #include "exceptions.h"
42 #include "amd64-tdep.h"
43 #include "i387-tdep.h"
45 #include "features/i386/amd64.c"
46 #include "features/i386/amd64-avx.c"
48 /* Note that the AMD64 architecture was previously known as x86-64.
49 The latter is (forever) engraved into the canonical system name as
50 returned by config.guess, and used as the name for the AMD64 port
51 of GNU/Linux. The BSD's have renamed their ports to amd64; they
52 don't like to shout. For GDB we prefer the amd64_-prefix over the
53 x86_64_-prefix since it's so much easier to type. */
55 /* Register information. */
57 static const char *amd64_register_names[] =
59 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
61 /* %r8 is indeed register number 8. */
62 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
63 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
65 /* %st0 is register number 24. */
66 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
67 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
69 /* %xmm0 is register number 40. */
70 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
71 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
75 static const char *amd64_ymm_names[] =
77 "ymm0", "ymm1", "ymm2", "ymm3",
78 "ymm4", "ymm5", "ymm6", "ymm7",
79 "ymm8", "ymm9", "ymm10", "ymm11",
80 "ymm12", "ymm13", "ymm14", "ymm15"
83 static const char *amd64_ymmh_names[] =
85 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
86 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
87 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
88 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
91 /* The registers used to pass integer arguments during a function call. */
92 static int amd64_dummy_call_integer_regs[] =
94 AMD64_RDI_REGNUM, /* %rdi */
95 AMD64_RSI_REGNUM, /* %rsi */
96 AMD64_RDX_REGNUM, /* %rdx */
97 AMD64_RCX_REGNUM, /* %rcx */
102 /* DWARF Register Number Mapping as defined in the System V psABI,
105 static int amd64_dwarf_regmap[] =
107 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
108 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
109 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
110 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
112 /* Frame Pointer Register RBP. */
115 /* Stack Pointer Register RSP. */
118 /* Extended Integer Registers 8 - 15. */
119 8, 9, 10, 11, 12, 13, 14, 15,
121 /* Return Address RA. Mapped to RIP. */
124 /* SSE Registers 0 - 7. */
125 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
126 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
127 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
128 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
130 /* Extended SSE Registers 8 - 15. */
131 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
132 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
133 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
134 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
136 /* Floating Point Registers 0-7. */
137 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
138 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
139 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
140 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
142 /* Control and Status Flags Register. */
145 /* Selector Registers. */
155 /* Segment Base Address Registers. */
161 /* Special Selector Registers. */
165 /* Floating Point Control Registers. */
171 static const int amd64_dwarf_regmap_len =
172 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
174 /* Convert DWARF register number REG to the appropriate register
175 number used by GDB. */
178 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
181 int ymm0_regnum = tdep->ymm0_regnum;
184 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
185 regnum = amd64_dwarf_regmap[reg];
188 warning (_("Unmapped DWARF Register #%d encountered."), reg);
189 else if (ymm0_regnum >= 0
190 && i386_xmm_regnum_p (gdbarch, regnum))
191 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
196 /* Map architectural register numbers to gdb register numbers. */
198 static const int amd64_arch_regmap[16] =
200 AMD64_RAX_REGNUM, /* %rax */
201 AMD64_RCX_REGNUM, /* %rcx */
202 AMD64_RDX_REGNUM, /* %rdx */
203 AMD64_RBX_REGNUM, /* %rbx */
204 AMD64_RSP_REGNUM, /* %rsp */
205 AMD64_RBP_REGNUM, /* %rbp */
206 AMD64_RSI_REGNUM, /* %rsi */
207 AMD64_RDI_REGNUM, /* %rdi */
208 AMD64_R8_REGNUM, /* %r8 */
209 AMD64_R9_REGNUM, /* %r9 */
210 AMD64_R10_REGNUM, /* %r10 */
211 AMD64_R11_REGNUM, /* %r11 */
212 AMD64_R12_REGNUM, /* %r12 */
213 AMD64_R13_REGNUM, /* %r13 */
214 AMD64_R14_REGNUM, /* %r14 */
215 AMD64_R15_REGNUM /* %r15 */
218 static const int amd64_arch_regmap_len =
219 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
221 /* Convert architectural register number REG to the appropriate register
222 number used by GDB. */
225 amd64_arch_reg_to_regnum (int reg)
227 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
229 return amd64_arch_regmap[reg];
232 /* Register names for byte pseudo-registers. */
234 static const char *amd64_byte_names[] =
236 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
237 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
238 "ah", "bh", "ch", "dh"
241 /* Number of lower byte registers. */
242 #define AMD64_NUM_LOWER_BYTE_REGS 16
244 /* Register names for word pseudo-registers. */
246 static const char *amd64_word_names[] =
248 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
249 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
252 /* Register names for dword pseudo-registers. */
254 static const char *amd64_dword_names[] =
256 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
257 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
260 /* Return the name of register REGNUM. */
263 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
265 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
266 if (i386_byte_regnum_p (gdbarch, regnum))
267 return amd64_byte_names[regnum - tdep->al_regnum];
268 else if (i386_ymm_regnum_p (gdbarch, regnum))
269 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
270 else if (i386_word_regnum_p (gdbarch, regnum))
271 return amd64_word_names[regnum - tdep->ax_regnum];
272 else if (i386_dword_regnum_p (gdbarch, regnum))
273 return amd64_dword_names[regnum - tdep->eax_regnum];
275 return i386_pseudo_register_name (gdbarch, regnum);
278 static struct value *
279 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
280 struct regcache *regcache,
283 gdb_byte raw_buf[MAX_REGISTER_SIZE];
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
285 enum register_status status;
286 struct value *result_value;
289 result_value = allocate_value (register_type (gdbarch, regnum));
290 VALUE_LVAL (result_value) = lval_register;
291 VALUE_REGNUM (result_value) = regnum;
292 buf = value_contents_raw (result_value);
294 if (i386_byte_regnum_p (gdbarch, regnum))
296 int gpnum = regnum - tdep->al_regnum;
298 /* Extract (always little endian). */
299 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
301 /* Special handling for AH, BH, CH, DH. */
302 status = regcache_raw_read (regcache,
303 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
305 if (status == REG_VALID)
306 memcpy (buf, raw_buf + 1, 1);
308 mark_value_bytes_unavailable (result_value, 0,
309 TYPE_LENGTH (value_type (result_value)));
313 status = regcache_raw_read (regcache, gpnum, raw_buf);
314 if (status == REG_VALID)
315 memcpy (buf, raw_buf, 1);
317 mark_value_bytes_unavailable (result_value, 0,
318 TYPE_LENGTH (value_type (result_value)));
321 else if (i386_dword_regnum_p (gdbarch, regnum))
323 int gpnum = regnum - tdep->eax_regnum;
324 /* Extract (always little endian). */
325 status = regcache_raw_read (regcache, gpnum, raw_buf);
326 if (status == REG_VALID)
327 memcpy (buf, raw_buf, 4);
329 mark_value_bytes_unavailable (result_value, 0,
330 TYPE_LENGTH (value_type (result_value)));
333 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
340 amd64_pseudo_register_write (struct gdbarch *gdbarch,
341 struct regcache *regcache,
342 int regnum, const gdb_byte *buf)
344 gdb_byte raw_buf[MAX_REGISTER_SIZE];
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
347 if (i386_byte_regnum_p (gdbarch, regnum))
349 int gpnum = regnum - tdep->al_regnum;
351 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
353 /* Read ... AH, BH, CH, DH. */
354 regcache_raw_read (regcache,
355 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
356 /* ... Modify ... (always little endian). */
357 memcpy (raw_buf + 1, buf, 1);
359 regcache_raw_write (regcache,
360 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
365 regcache_raw_read (regcache, gpnum, raw_buf);
366 /* ... Modify ... (always little endian). */
367 memcpy (raw_buf, buf, 1);
369 regcache_raw_write (regcache, gpnum, raw_buf);
372 else if (i386_dword_regnum_p (gdbarch, regnum))
374 int gpnum = regnum - tdep->eax_regnum;
377 regcache_raw_read (regcache, gpnum, raw_buf);
378 /* ... Modify ... (always little endian). */
379 memcpy (raw_buf, buf, 4);
381 regcache_raw_write (regcache, gpnum, raw_buf);
384 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
389 /* Return the union class of CLASS1 and CLASS2. See the psABI for
392 static enum amd64_reg_class
393 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
395 /* Rule (a): If both classes are equal, this is the resulting class. */
396 if (class1 == class2)
399 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
400 is the other class. */
401 if (class1 == AMD64_NO_CLASS)
403 if (class2 == AMD64_NO_CLASS)
406 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
407 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
410 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
411 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
412 return AMD64_INTEGER;
414 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
415 MEMORY is used as class. */
416 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
417 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
418 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
421 /* Rule (f): Otherwise class SSE is used. */
425 /* Return non-zero if TYPE is a non-POD structure or union type. */
428 amd64_non_pod_p (struct type *type)
430 /* ??? A class with a base class certainly isn't POD, but does this
431 catch all non-POD structure types? */
432 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
438 /* Classify TYPE according to the rules for aggregate (structures and
439 arrays) and union types, and store the result in CLASS. */
442 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
444 int len = TYPE_LENGTH (type);
446 /* 1. If the size of an object is larger than two eightbytes, or in
447 C++, is a non-POD structure or union type, or contains
448 unaligned fields, it has class memory. */
449 if (len > 16 || amd64_non_pod_p (type))
451 class[0] = class[1] = AMD64_MEMORY;
455 /* 2. Both eightbytes get initialized to class NO_CLASS. */
456 class[0] = class[1] = AMD64_NO_CLASS;
458 /* 3. Each field of an object is classified recursively so that
459 always two fields are considered. The resulting class is
460 calculated according to the classes of the fields in the
463 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
465 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
467 /* All fields in an array have the same type. */
468 amd64_classify (subtype, class);
469 if (len > 8 && class[1] == AMD64_NO_CLASS)
476 /* Structure or union. */
477 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
478 || TYPE_CODE (type) == TYPE_CODE_UNION);
480 for (i = 0; i < TYPE_NFIELDS (type); i++)
482 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
483 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
484 enum amd64_reg_class subclass[2];
485 int bitsize = TYPE_FIELD_BITSIZE (type, i);
489 bitsize = TYPE_LENGTH (subtype) * 8;
490 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
492 /* Ignore static fields. */
493 if (field_is_static (&TYPE_FIELD (type, i)))
496 gdb_assert (pos == 0 || pos == 1);
498 amd64_classify (subtype, subclass);
499 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
500 if (bitsize <= 64 && pos == 0 && endpos == 1)
501 /* This is a bit of an odd case: We have a field that would
502 normally fit in one of the two eightbytes, except that
503 it is placed in a way that this field straddles them.
504 This has been seen with a structure containing an array.
506 The ABI is a bit unclear in this case, but we assume that
507 this field's class (stored in subclass[0]) must also be merged
508 into class[1]. In other words, our field has a piece stored
509 in the second eight-byte, and thus its class applies to
510 the second eight-byte as well.
512 In the case where the field length exceeds 8 bytes,
513 it should not be necessary to merge the field class
514 into class[1]. As LEN > 8, subclass[1] is necessarily
515 different from AMD64_NO_CLASS. If subclass[1] is equal
516 to subclass[0], then the normal class[1]/subclass[1]
517 merging will take care of everything. For subclass[1]
518 to be different from subclass[0], I can only see the case
519 where we have a SSE/SSEUP or X87/X87UP pair, which both
520 use up all 16 bytes of the aggregate, and are already
521 handled just fine (because each portion sits on its own
523 class[1] = amd64_merge_classes (class[1], subclass[0]);
525 class[1] = amd64_merge_classes (class[1], subclass[1]);
529 /* 4. Then a post merger cleanup is done: */
531 /* Rule (a): If one of the classes is MEMORY, the whole argument is
533 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
534 class[0] = class[1] = AMD64_MEMORY;
536 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
538 if (class[0] == AMD64_SSEUP)
539 class[0] = AMD64_SSE;
540 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
541 class[1] = AMD64_SSE;
544 /* Classify TYPE, and store the result in CLASS. */
547 amd64_classify (struct type *type, enum amd64_reg_class class[2])
549 enum type_code code = TYPE_CODE (type);
550 int len = TYPE_LENGTH (type);
552 class[0] = class[1] = AMD64_NO_CLASS;
554 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
555 long, long long, and pointers are in the INTEGER class. Similarly,
556 range types, used by languages such as Ada, are also in the INTEGER
558 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
559 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
560 || code == TYPE_CODE_CHAR
561 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
562 && (len == 1 || len == 2 || len == 4 || len == 8))
563 class[0] = AMD64_INTEGER;
565 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
567 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
568 && (len == 4 || len == 8))
570 class[0] = AMD64_SSE;
572 /* Arguments of types __float128, _Decimal128 and __m128 are split into
573 two halves. The least significant ones belong to class SSE, the most
574 significant one to class SSEUP. */
575 else if (code == TYPE_CODE_DECFLOAT && len == 16)
576 /* FIXME: __float128, __m128. */
577 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
579 /* The 64-bit mantissa of arguments of type long double belongs to
580 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
582 else if (code == TYPE_CODE_FLT && len == 16)
583 /* Class X87 and X87UP. */
584 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
587 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
588 || code == TYPE_CODE_UNION)
589 amd64_classify_aggregate (type, class);
592 static enum return_value_convention
593 amd64_return_value (struct gdbarch *gdbarch, struct type *func_type,
594 struct type *type, struct regcache *regcache,
595 gdb_byte *readbuf, const gdb_byte *writebuf)
597 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
598 enum amd64_reg_class class[2];
599 int len = TYPE_LENGTH (type);
600 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
601 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
606 gdb_assert (!(readbuf && writebuf));
607 gdb_assert (tdep->classify);
609 /* 1. Classify the return type with the classification algorithm. */
610 tdep->classify (type, class);
612 /* 2. If the type has class MEMORY, then the caller provides space
613 for the return value and passes the address of this storage in
614 %rdi as if it were the first argument to the function. In effect,
615 this address becomes a hidden first argument.
617 On return %rax will contain the address that has been passed in
618 by the caller in %rdi. */
619 if (class[0] == AMD64_MEMORY)
621 /* As indicated by the comment above, the ABI guarantees that we
622 can always find the return value just after the function has
629 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
630 read_memory (addr, readbuf, TYPE_LENGTH (type));
633 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
636 gdb_assert (class[1] != AMD64_MEMORY);
637 gdb_assert (len <= 16);
639 for (i = 0; len > 0; i++, len -= 8)
647 /* 3. If the class is INTEGER, the next available register
648 of the sequence %rax, %rdx is used. */
649 regnum = integer_regnum[integer_reg++];
653 /* 4. If the class is SSE, the next available SSE register
654 of the sequence %xmm0, %xmm1 is used. */
655 regnum = sse_regnum[sse_reg++];
659 /* 5. If the class is SSEUP, the eightbyte is passed in the
660 upper half of the last used SSE register. */
661 gdb_assert (sse_reg > 0);
662 regnum = sse_regnum[sse_reg - 1];
667 /* 6. If the class is X87, the value is returned on the X87
668 stack in %st0 as 80-bit x87 number. */
669 regnum = AMD64_ST0_REGNUM;
671 i387_return_value (gdbarch, regcache);
675 /* 7. If the class is X87UP, the value is returned together
676 with the previous X87 value in %st0. */
677 gdb_assert (i > 0 && class[0] == AMD64_X87);
678 regnum = AMD64_ST0_REGNUM;
687 gdb_assert (!"Unexpected register class.");
690 gdb_assert (regnum != -1);
693 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
696 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
700 return RETURN_VALUE_REGISTER_CONVENTION;
705 amd64_push_arguments (struct regcache *regcache, int nargs,
706 struct value **args, CORE_ADDR sp, int struct_return)
708 struct gdbarch *gdbarch = get_regcache_arch (regcache);
709 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
710 int *integer_regs = tdep->call_dummy_integer_regs;
711 int num_integer_regs = tdep->call_dummy_num_integer_regs;
713 static int sse_regnum[] =
715 /* %xmm0 ... %xmm7 */
716 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
717 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
718 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
719 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
721 struct value **stack_args = alloca (nargs * sizeof (struct value *));
722 /* An array that mirrors the stack_args array. For all arguments
723 that are passed by MEMORY, if that argument's address also needs
724 to be stored in a register, the ARG_ADDR_REGNO array will contain
725 that register number (or a negative value otherwise). */
726 int *arg_addr_regno = alloca (nargs * sizeof (int));
727 int num_stack_args = 0;
728 int num_elements = 0;
734 gdb_assert (tdep->classify);
736 /* Reserve a register for the "hidden" argument. */
740 for (i = 0; i < nargs; i++)
742 struct type *type = value_type (args[i]);
743 int len = TYPE_LENGTH (type);
744 enum amd64_reg_class class[2];
745 int needed_integer_regs = 0;
746 int needed_sse_regs = 0;
749 /* Classify argument. */
750 tdep->classify (type, class);
752 /* Calculate the number of integer and SSE registers needed for
754 for (j = 0; j < 2; j++)
756 if (class[j] == AMD64_INTEGER)
757 needed_integer_regs++;
758 else if (class[j] == AMD64_SSE)
762 /* Check whether enough registers are available, and if the
763 argument should be passed in registers at all. */
764 if (integer_reg + needed_integer_regs > num_integer_regs
765 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
766 || (needed_integer_regs == 0 && needed_sse_regs == 0))
768 /* The argument will be passed on the stack. */
769 num_elements += ((len + 7) / 8);
770 stack_args[num_stack_args] = args[i];
771 /* If this is an AMD64_MEMORY argument whose address must also
772 be passed in one of the integer registers, reserve that
773 register and associate this value to that register so that
774 we can store the argument address as soon as we know it. */
775 if (class[0] == AMD64_MEMORY
776 && tdep->memory_args_by_pointer
777 && integer_reg < tdep->call_dummy_num_integer_regs)
778 arg_addr_regno[num_stack_args] =
779 tdep->call_dummy_integer_regs[integer_reg++];
781 arg_addr_regno[num_stack_args] = -1;
786 /* The argument will be passed in registers. */
787 const gdb_byte *valbuf = value_contents (args[i]);
790 gdb_assert (len <= 16);
792 for (j = 0; len > 0; j++, len -= 8)
800 regnum = integer_regs[integer_reg++];
804 regnum = sse_regnum[sse_reg++];
808 gdb_assert (sse_reg > 0);
809 regnum = sse_regnum[sse_reg - 1];
814 gdb_assert (!"Unexpected register class.");
817 gdb_assert (regnum != -1);
818 memset (buf, 0, sizeof buf);
819 memcpy (buf, valbuf + j * 8, min (len, 8));
820 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
825 /* Allocate space for the arguments on the stack. */
826 sp -= num_elements * 8;
828 /* The psABI says that "The end of the input argument area shall be
829 aligned on a 16 byte boundary." */
832 /* Write out the arguments to the stack. */
833 for (i = 0; i < num_stack_args; i++)
835 struct type *type = value_type (stack_args[i]);
836 const gdb_byte *valbuf = value_contents (stack_args[i]);
837 int len = TYPE_LENGTH (type);
838 CORE_ADDR arg_addr = sp + element * 8;
840 write_memory (arg_addr, valbuf, len);
841 if (arg_addr_regno[i] >= 0)
843 /* We also need to store the address of that argument in
844 the given register. */
846 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
848 store_unsigned_integer (buf, 8, byte_order, arg_addr);
849 regcache_cooked_write (regcache, arg_addr_regno[i], buf);
851 element += ((len + 7) / 8);
854 /* The psABI says that "For calls that may call functions that use
855 varargs or stdargs (prototype-less calls or calls to functions
856 containing ellipsis (...) in the declaration) %al is used as
857 hidden argument to specify the number of SSE registers used. */
858 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
863 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
864 struct regcache *regcache, CORE_ADDR bp_addr,
865 int nargs, struct value **args, CORE_ADDR sp,
866 int struct_return, CORE_ADDR struct_addr)
868 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
869 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
872 /* Pass arguments. */
873 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
875 /* Pass "hidden" argument". */
878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
879 /* The "hidden" argument is passed throught the first argument
881 const int arg_regnum = tdep->call_dummy_integer_regs[0];
883 store_unsigned_integer (buf, 8, byte_order, struct_addr);
884 regcache_cooked_write (regcache, arg_regnum, buf);
887 /* Reserve some memory on the stack for the integer-parameter registers,
888 if required by the ABI. */
889 if (tdep->integer_param_regs_saved_in_caller_frame)
890 sp -= tdep->call_dummy_num_integer_regs * 8;
892 /* Store return address. */
894 store_unsigned_integer (buf, 8, byte_order, bp_addr);
895 write_memory (sp, buf, 8);
897 /* Finally, update the stack pointer... */
898 store_unsigned_integer (buf, 8, byte_order, sp);
899 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
901 /* ...and fake a frame pointer. */
902 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
907 /* Displaced instruction handling. */
909 /* A partially decoded instruction.
910 This contains enough details for displaced stepping purposes. */
914 /* The number of opcode bytes. */
916 /* The offset of the rex prefix or -1 if not present. */
918 /* The offset to the first opcode byte. */
920 /* The offset to the modrm byte or -1 if not present. */
923 /* The raw instruction. */
927 struct displaced_step_closure
929 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
934 /* Details of the instruction. */
935 struct amd64_insn insn_details;
937 /* Amount of space allocated to insn_buf. */
940 /* The possibly modified insn.
941 This is a variable-length field. */
942 gdb_byte insn_buf[1];
945 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
946 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
947 at which point delete these in favor of libopcodes' versions). */
949 static const unsigned char onebyte_has_modrm[256] = {
950 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
951 /* ------------------------------- */
952 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
953 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
954 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
955 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
956 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
957 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
958 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
959 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
960 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
961 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
962 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
963 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
964 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
965 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
966 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
967 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
968 /* ------------------------------- */
969 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
972 static const unsigned char twobyte_has_modrm[256] = {
973 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
974 /* ------------------------------- */
975 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
976 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
977 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
978 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
979 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
980 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
981 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
982 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
983 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
984 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
985 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
986 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
987 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
988 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
989 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
990 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
991 /* ------------------------------- */
992 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
995 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
998 rex_prefix_p (gdb_byte pfx)
1000 return REX_PREFIX_P (pfx);
1003 /* Skip the legacy instruction prefixes in INSN.
1004 We assume INSN is properly sentineled so we don't have to worry
1005 about falling off the end of the buffer. */
1008 amd64_skip_prefixes (gdb_byte *insn)
1014 case DATA_PREFIX_OPCODE:
1015 case ADDR_PREFIX_OPCODE:
1016 case CS_PREFIX_OPCODE:
1017 case DS_PREFIX_OPCODE:
1018 case ES_PREFIX_OPCODE:
1019 case FS_PREFIX_OPCODE:
1020 case GS_PREFIX_OPCODE:
1021 case SS_PREFIX_OPCODE:
1022 case LOCK_PREFIX_OPCODE:
1023 case REPE_PREFIX_OPCODE:
1024 case REPNE_PREFIX_OPCODE:
1036 /* Return an integer register (other than RSP) that is unused as an input
1038 In order to not require adding a rex prefix if the insn doesn't already
1039 have one, the result is restricted to RAX ... RDI, sans RSP.
1040 The register numbering of the result follows architecture ordering,
1044 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1046 /* 1 bit for each reg */
1047 int used_regs_mask = 0;
1049 /* There can be at most 3 int regs used as inputs in an insn, and we have
1050 7 to choose from (RAX ... RDI, sans RSP).
1051 This allows us to take a conservative approach and keep things simple.
1052 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1053 that implicitly specify RAX. */
1056 used_regs_mask |= 1 << EAX_REG_NUM;
1057 /* Similarily avoid RDX, implicit operand in divides. */
1058 used_regs_mask |= 1 << EDX_REG_NUM;
1060 used_regs_mask |= 1 << ESP_REG_NUM;
1062 /* If the opcode is one byte long and there's no ModRM byte,
1063 assume the opcode specifies a register. */
1064 if (details->opcode_len == 1 && details->modrm_offset == -1)
1065 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1067 /* Mark used regs in the modrm/sib bytes. */
1068 if (details->modrm_offset != -1)
1070 int modrm = details->raw_insn[details->modrm_offset];
1071 int mod = MODRM_MOD_FIELD (modrm);
1072 int reg = MODRM_REG_FIELD (modrm);
1073 int rm = MODRM_RM_FIELD (modrm);
1074 int have_sib = mod != 3 && rm == 4;
1076 /* Assume the reg field of the modrm byte specifies a register. */
1077 used_regs_mask |= 1 << reg;
1081 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1082 int index = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1083 used_regs_mask |= 1 << base;
1084 used_regs_mask |= 1 << index;
1088 used_regs_mask |= 1 << rm;
1092 gdb_assert (used_regs_mask < 256);
1093 gdb_assert (used_regs_mask != 255);
1095 /* Finally, find a free reg. */
1099 for (i = 0; i < 8; ++i)
1101 if (! (used_regs_mask & (1 << i)))
1105 /* We shouldn't get here. */
1106 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1110 /* Extract the details of INSN that we need. */
1113 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1115 gdb_byte *start = insn;
1118 details->raw_insn = insn;
1120 details->opcode_len = -1;
1121 details->rex_offset = -1;
1122 details->opcode_offset = -1;
1123 details->modrm_offset = -1;
1125 /* Skip legacy instruction prefixes. */
1126 insn = amd64_skip_prefixes (insn);
1128 /* Skip REX instruction prefix. */
1129 if (rex_prefix_p (*insn))
1131 details->rex_offset = insn - start;
1135 details->opcode_offset = insn - start;
1137 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1139 /* Two or three-byte opcode. */
1141 need_modrm = twobyte_has_modrm[*insn];
1143 /* Check for three-byte opcode. */
1153 details->opcode_len = 3;
1156 details->opcode_len = 2;
1162 /* One-byte opcode. */
1163 need_modrm = onebyte_has_modrm[*insn];
1164 details->opcode_len = 1;
1170 details->modrm_offset = insn - start;
1174 /* Update %rip-relative addressing in INSN.
1176 %rip-relative addressing only uses a 32-bit displacement.
1177 32 bits is not enough to be guaranteed to cover the distance between where
1178 the real instruction is and where its copy is.
1179 Convert the insn to use base+disp addressing.
1180 We set base = pc + insn_length so we can leave disp unchanged. */
1183 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1184 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1186 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1187 const struct amd64_insn *insn_details = &dsc->insn_details;
1188 int modrm_offset = insn_details->modrm_offset;
1189 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1193 int arch_tmp_regno, tmp_regno;
1194 ULONGEST orig_value;
1196 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1199 /* Compute the rip-relative address. */
1200 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1201 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1202 dsc->max_len, from);
1203 rip_base = from + insn_length;
1205 /* We need a register to hold the address.
1206 Pick one not used in the insn.
1207 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1208 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1209 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1211 /* REX.B should be unset as we were using rip-relative addressing,
1212 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1213 if (insn_details->rex_offset != -1)
1214 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1216 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1217 dsc->tmp_regno = tmp_regno;
1218 dsc->tmp_save = orig_value;
1221 /* Convert the ModRM field to be base+disp. */
1222 dsc->insn_buf[modrm_offset] &= ~0xc7;
1223 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1225 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1227 if (debug_displaced)
1228 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1229 "displaced: using temp reg %d, old value %s, new value %s\n",
1230 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1231 paddress (gdbarch, rip_base));
1235 fixup_displaced_copy (struct gdbarch *gdbarch,
1236 struct displaced_step_closure *dsc,
1237 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1239 const struct amd64_insn *details = &dsc->insn_details;
1241 if (details->modrm_offset != -1)
1243 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1245 if ((modrm & 0xc7) == 0x05)
1247 /* The insn uses rip-relative addressing.
1249 fixup_riprel (gdbarch, dsc, from, to, regs);
1254 struct displaced_step_closure *
1255 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1256 CORE_ADDR from, CORE_ADDR to,
1257 struct regcache *regs)
1259 int len = gdbarch_max_insn_length (gdbarch);
1260 /* Extra space for sentinels so fixup_{riprel,displaced_copy don't have to
1261 continually watch for running off the end of the buffer. */
1262 int fixup_sentinel_space = len;
1263 struct displaced_step_closure *dsc =
1264 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1265 gdb_byte *buf = &dsc->insn_buf[0];
1266 struct amd64_insn *details = &dsc->insn_details;
1269 dsc->max_len = len + fixup_sentinel_space;
1271 read_memory (from, buf, len);
1273 /* Set up the sentinel space so we don't have to worry about running
1274 off the end of the buffer. An excessive number of leading prefixes
1275 could otherwise cause this. */
1276 memset (buf + len, 0, fixup_sentinel_space);
1278 amd64_get_insn_details (buf, details);
1280 /* GDB may get control back after the insn after the syscall.
1281 Presumably this is a kernel bug.
1282 If this is a syscall, make sure there's a nop afterwards. */
1286 if (amd64_syscall_p (details, &syscall_length))
1287 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1290 /* Modify the insn to cope with the address where it will be executed from.
1291 In particular, handle any rip-relative addressing. */
1292 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1294 write_memory (to, buf, len);
1296 if (debug_displaced)
1298 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1299 paddress (gdbarch, from), paddress (gdbarch, to));
1300 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1307 amd64_absolute_jmp_p (const struct amd64_insn *details)
1309 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1311 if (insn[0] == 0xff)
1313 /* jump near, absolute indirect (/4) */
1314 if ((insn[1] & 0x38) == 0x20)
1317 /* jump far, absolute indirect (/5) */
1318 if ((insn[1] & 0x38) == 0x28)
1326 amd64_absolute_call_p (const struct amd64_insn *details)
1328 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1330 if (insn[0] == 0xff)
1332 /* Call near, absolute indirect (/2) */
1333 if ((insn[1] & 0x38) == 0x10)
1336 /* Call far, absolute indirect (/3) */
1337 if ((insn[1] & 0x38) == 0x18)
1345 amd64_ret_p (const struct amd64_insn *details)
1347 /* NOTE: gcc can emit "repz ; ret". */
1348 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1352 case 0xc2: /* ret near, pop N bytes */
1353 case 0xc3: /* ret near */
1354 case 0xca: /* ret far, pop N bytes */
1355 case 0xcb: /* ret far */
1356 case 0xcf: /* iret */
1365 amd64_call_p (const struct amd64_insn *details)
1367 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1369 if (amd64_absolute_call_p (details))
1372 /* call near, relative */
1373 if (insn[0] == 0xe8)
1379 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1380 length in bytes. Otherwise, return zero. */
1383 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1385 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1387 if (insn[0] == 0x0f && insn[1] == 0x05)
1396 /* Fix up the state of registers and memory after having single-stepped
1397 a displaced instruction. */
1400 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1401 struct displaced_step_closure *dsc,
1402 CORE_ADDR from, CORE_ADDR to,
1403 struct regcache *regs)
1405 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1406 /* The offset we applied to the instruction's address. */
1407 ULONGEST insn_offset = to - from;
1408 gdb_byte *insn = dsc->insn_buf;
1409 const struct amd64_insn *insn_details = &dsc->insn_details;
1411 if (debug_displaced)
1412 fprintf_unfiltered (gdb_stdlog,
1413 "displaced: fixup (%s, %s), "
1414 "insn = 0x%02x 0x%02x ...\n",
1415 paddress (gdbarch, from), paddress (gdbarch, to),
1418 /* If we used a tmp reg, restore it. */
1422 if (debug_displaced)
1423 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1424 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1425 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1428 /* The list of issues to contend with here is taken from
1429 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1430 Yay for Free Software! */
1432 /* Relocate the %rip back to the program's instruction stream,
1435 /* Except in the case of absolute or indirect jump or call
1436 instructions, or a return instruction, the new rip is relative to
1437 the displaced instruction; make it relative to the original insn.
1438 Well, signal handler returns don't need relocation either, but we use the
1439 value of %rip to recognize those; see below. */
1440 if (! amd64_absolute_jmp_p (insn_details)
1441 && ! amd64_absolute_call_p (insn_details)
1442 && ! amd64_ret_p (insn_details))
1447 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1449 /* A signal trampoline system call changes the %rip, resuming
1450 execution of the main program after the signal handler has
1451 returned. That makes them like 'return' instructions; we
1452 shouldn't relocate %rip.
1454 But most system calls don't, and we do need to relocate %rip.
1456 Our heuristic for distinguishing these cases: if stepping
1457 over the system call instruction left control directly after
1458 the instruction, the we relocate --- control almost certainly
1459 doesn't belong in the displaced copy. Otherwise, we assume
1460 the instruction has put control where it belongs, and leave
1461 it unrelocated. Goodness help us if there are PC-relative
1463 if (amd64_syscall_p (insn_details, &insn_len)
1464 && orig_rip != to + insn_len
1465 /* GDB can get control back after the insn after the syscall.
1466 Presumably this is a kernel bug.
1467 Fixup ensures its a nop, we add one to the length for it. */
1468 && orig_rip != to + insn_len + 1)
1470 if (debug_displaced)
1471 fprintf_unfiltered (gdb_stdlog,
1472 "displaced: syscall changed %%rip; "
1473 "not relocating\n");
1477 ULONGEST rip = orig_rip - insn_offset;
1479 /* If we just stepped over a breakpoint insn, we don't backup
1480 the pc on purpose; this is to match behaviour without
1483 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1485 if (debug_displaced)
1486 fprintf_unfiltered (gdb_stdlog,
1488 "relocated %%rip from %s to %s\n",
1489 paddress (gdbarch, orig_rip),
1490 paddress (gdbarch, rip));
1494 /* If the instruction was PUSHFL, then the TF bit will be set in the
1495 pushed value, and should be cleared. We'll leave this for later,
1496 since GDB already messes up the TF flag when stepping over a
1499 /* If the instruction was a call, the return address now atop the
1500 stack is the address following the copied instruction. We need
1501 to make it the address following the original instruction. */
1502 if (amd64_call_p (insn_details))
1506 const ULONGEST retaddr_len = 8;
1508 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1509 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1510 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
1511 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1513 if (debug_displaced)
1514 fprintf_unfiltered (gdb_stdlog,
1515 "displaced: relocated return addr at %s "
1517 paddress (gdbarch, rsp),
1518 paddress (gdbarch, retaddr));
1522 /* If the instruction INSN uses RIP-relative addressing, return the
1523 offset into the raw INSN where the displacement to be adjusted is
1524 found. Returns 0 if the instruction doesn't use RIP-relative
1528 rip_relative_offset (struct amd64_insn *insn)
1530 if (insn->modrm_offset != -1)
1532 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1534 if ((modrm & 0xc7) == 0x05)
1536 /* The displacement is found right after the ModRM byte. */
1537 return insn->modrm_offset + 1;
1545 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1547 target_write_memory (*to, buf, len);
1552 amd64_relocate_instruction (struct gdbarch *gdbarch,
1553 CORE_ADDR *to, CORE_ADDR oldloc)
1555 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1556 int len = gdbarch_max_insn_length (gdbarch);
1557 /* Extra space for sentinels. */
1558 int fixup_sentinel_space = len;
1559 gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1560 struct amd64_insn insn_details;
1562 LONGEST rel32, newrel;
1566 read_memory (oldloc, buf, len);
1568 /* Set up the sentinel space so we don't have to worry about running
1569 off the end of the buffer. An excessive number of leading prefixes
1570 could otherwise cause this. */
1571 memset (buf + len, 0, fixup_sentinel_space);
1574 amd64_get_insn_details (insn, &insn_details);
1576 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1578 /* Skip legacy instruction prefixes. */
1579 insn = amd64_skip_prefixes (insn);
1581 /* Adjust calls with 32-bit relative addresses as push/jump, with
1582 the address pushed being the location where the original call in
1583 the user program would return to. */
1584 if (insn[0] == 0xe8)
1586 gdb_byte push_buf[16];
1587 unsigned int ret_addr;
1589 /* Where "ret" in the original code will return to. */
1590 ret_addr = oldloc + insn_length;
1591 push_buf[0] = 0x68; /* pushq $... */
1592 memcpy (&push_buf[1], &ret_addr, 4);
1593 /* Push the push. */
1594 append_insns (to, 5, push_buf);
1596 /* Convert the relative call to a relative jump. */
1599 /* Adjust the destination offset. */
1600 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1601 newrel = (oldloc - *to) + rel32;
1602 store_signed_integer (insn + 1, 4, byte_order, newrel);
1604 if (debug_displaced)
1605 fprintf_unfiltered (gdb_stdlog,
1606 "Adjusted insn rel32=%s at %s to"
1607 " rel32=%s at %s\n",
1608 hex_string (rel32), paddress (gdbarch, oldloc),
1609 hex_string (newrel), paddress (gdbarch, *to));
1611 /* Write the adjusted jump into its displaced location. */
1612 append_insns (to, 5, insn);
1616 offset = rip_relative_offset (&insn_details);
1619 /* Adjust jumps with 32-bit relative addresses. Calls are
1620 already handled above. */
1621 if (insn[0] == 0xe9)
1623 /* Adjust conditional jumps. */
1624 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1630 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1631 newrel = (oldloc - *to) + rel32;
1632 store_signed_integer (insn + offset, 4, byte_order, newrel);
1633 if (debug_displaced)
1634 fprintf_unfiltered (gdb_stdlog,
1635 "Adjusted insn rel32=%s at %s to"
1636 " rel32=%s at %s\n",
1637 hex_string (rel32), paddress (gdbarch, oldloc),
1638 hex_string (newrel), paddress (gdbarch, *to));
1641 /* Write the adjusted instruction into its displaced location. */
1642 append_insns (to, insn_length, buf);
1646 /* The maximum number of saved registers. This should include %rip. */
1647 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1649 struct amd64_frame_cache
1654 CORE_ADDR sp_offset;
1657 /* Saved registers. */
1658 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1662 /* Do we have a frame? */
1666 /* Initialize a frame cache. */
1669 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1676 cache->sp_offset = -8;
1679 /* Saved registers. We initialize these to -1 since zero is a valid
1680 offset (that's where %rbp is supposed to be stored).
1681 The values start out as being offsets, and are later converted to
1682 addresses (at which point -1 is interpreted as an address, still meaning
1684 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1685 cache->saved_regs[i] = -1;
1686 cache->saved_sp = 0;
1687 cache->saved_sp_reg = -1;
1689 /* Frameless until proven otherwise. */
1690 cache->frameless_p = 1;
1693 /* Allocate and initialize a frame cache. */
1695 static struct amd64_frame_cache *
1696 amd64_alloc_frame_cache (void)
1698 struct amd64_frame_cache *cache;
1700 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1701 amd64_init_frame_cache (cache);
1705 /* GCC 4.4 and later, can put code in the prologue to realign the
1706 stack pointer. Check whether PC points to such code, and update
1707 CACHE accordingly. Return the first instruction after the code
1708 sequence or CURRENT_PC, whichever is smaller. If we don't
1709 recognize the code, return PC. */
1712 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1713 struct amd64_frame_cache *cache)
1715 /* There are 2 code sequences to re-align stack before the frame
1718 1. Use a caller-saved saved register:
1724 2. Use a callee-saved saved register:
1731 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1733 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1734 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1739 int offset, offset_and;
1741 if (target_read_memory (pc, buf, sizeof buf))
1744 /* Check caller-saved saved register. The first instruction has
1745 to be "leaq 8(%rsp), %reg". */
1746 if ((buf[0] & 0xfb) == 0x48
1751 /* MOD must be binary 10 and R/M must be binary 100. */
1752 if ((buf[2] & 0xc7) != 0x44)
1755 /* REG has register number. */
1756 reg = (buf[2] >> 3) & 7;
1758 /* Check the REX.R bit. */
1766 /* Check callee-saved saved register. The first instruction
1767 has to be "pushq %reg". */
1769 if ((buf[0] & 0xf8) == 0x50)
1771 else if ((buf[0] & 0xf6) == 0x40
1772 && (buf[1] & 0xf8) == 0x50)
1774 /* Check the REX.B bit. */
1775 if ((buf[0] & 1) != 0)
1784 reg += buf[offset] & 0x7;
1788 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1789 if ((buf[offset] & 0xfb) != 0x48
1790 || buf[offset + 1] != 0x8d
1791 || buf[offset + 3] != 0x24
1792 || buf[offset + 4] != 0x10)
1795 /* MOD must be binary 10 and R/M must be binary 100. */
1796 if ((buf[offset + 2] & 0xc7) != 0x44)
1799 /* REG has register number. */
1800 r = (buf[offset + 2] >> 3) & 7;
1802 /* Check the REX.R bit. */
1803 if (buf[offset] == 0x4c)
1806 /* Registers in pushq and leaq have to be the same. */
1813 /* Rigister can't be %rsp nor %rbp. */
1814 if (reg == 4 || reg == 5)
1817 /* The next instruction has to be "andq $-XXX, %rsp". */
1818 if (buf[offset] != 0x48
1819 || buf[offset + 2] != 0xe4
1820 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1823 offset_and = offset;
1824 offset += buf[offset + 1] == 0x81 ? 7 : 4;
1826 /* The next instruction has to be "pushq -8(%reg)". */
1828 if (buf[offset] == 0xff)
1830 else if ((buf[offset] & 0xf6) == 0x40
1831 && buf[offset + 1] == 0xff)
1833 /* Check the REX.B bit. */
1834 if ((buf[offset] & 0x1) != 0)
1841 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1843 if (buf[offset + 1] != 0xf8
1844 || (buf[offset] & 0xf8) != 0x70)
1847 /* R/M has register. */
1848 r += buf[offset] & 7;
1850 /* Registers in leaq and pushq have to be the same. */
1854 if (current_pc > pc + offset_and)
1855 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
1857 return min (pc + offset + 2, current_pc);
1860 /* Do a limited analysis of the prologue at PC and update CACHE
1861 accordingly. Bail out early if CURRENT_PC is reached. Return the
1862 address where the analysis stopped.
1864 We will handle only functions beginning with:
1867 movq %rsp, %rbp 0x48 0x89 0xe5
1869 Any function that doesn't start with this sequence will be assumed
1870 to have no prologue and thus no valid frame pointer in %rbp. */
1873 amd64_analyze_prologue (struct gdbarch *gdbarch,
1874 CORE_ADDR pc, CORE_ADDR current_pc,
1875 struct amd64_frame_cache *cache)
1877 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1878 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
1882 if (current_pc <= pc)
1885 pc = amd64_analyze_stack_align (pc, current_pc, cache);
1887 op = read_memory_unsigned_integer (pc, 1, byte_order);
1889 if (op == 0x55) /* pushq %rbp */
1891 /* Take into account that we've executed the `pushq %rbp' that
1892 starts this instruction sequence. */
1893 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
1894 cache->sp_offset += 8;
1896 /* If that's all, return now. */
1897 if (current_pc <= pc + 1)
1900 /* Check for `movq %rsp, %rbp'. */
1901 read_memory (pc + 1, buf, 3);
1902 if (memcmp (buf, proto, 3) != 0)
1905 /* OK, we actually have a frame. */
1906 cache->frameless_p = 0;
1913 /* Work around false termination of prologue - GCC PR debug/48827.
1915 START_PC is the first instruction of a function, PC is its minimal already
1916 determined advanced address. Function returns PC if it has nothing to do.
1920 <-- here is 0 lines advance - the false prologue end marker.
1921 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
1922 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
1923 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
1924 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
1925 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
1926 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
1927 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
1928 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
1932 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
1934 struct symtab_and_line start_pc_sal, next_sal;
1935 gdb_byte buf[4 + 8 * 7];
1941 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
1942 if (start_pc_sal.symtab == NULL
1943 || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6
1944 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
1947 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
1948 if (next_sal.line != start_pc_sal.line)
1951 /* START_PC can be from overlayed memory, ignored here. */
1952 if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0)
1956 if (buf[0] != 0x84 || buf[1] != 0xc0)
1963 for (xmmreg = 0; xmmreg < 8; xmmreg++)
1965 /* movaps %xmmreg?,-0x??(%rbp) */
1966 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
1967 || (buf[offset + 2] & 0b00111111) != (xmmreg << 3 | 0b101))
1970 if ((buf[offset + 2] & 0b11000000) == 0b01000000)
1972 /* 8-bit displacement. */
1975 else if ((buf[offset + 2] & 0b11000000) == 0b10000000)
1977 /* 32-bit displacement. */
1985 if (offset - 4 != buf[3])
1988 return next_sal.end;
1991 /* Return PC of first real instruction. */
1994 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1996 struct amd64_frame_cache cache;
1999 amd64_init_frame_cache (&cache);
2000 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2002 if (cache.frameless_p)
2005 return amd64_skip_xmm_prologue (pc, start_pc);
2009 /* Normal frames. */
2012 amd64_frame_cache_1 (struct frame_info *this_frame,
2013 struct amd64_frame_cache *cache)
2015 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2016 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2020 cache->pc = get_frame_func (this_frame);
2022 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2025 if (cache->frameless_p)
2027 /* We didn't find a valid frame. If we're at the start of a
2028 function, or somewhere half-way its prologue, the function's
2029 frame probably hasn't been fully setup yet. Try to
2030 reconstruct the base address for the stack frame by looking
2031 at the stack pointer. For truly "frameless" functions this
2034 if (cache->saved_sp_reg != -1)
2036 /* Stack pointer has been saved. */
2037 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2038 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2040 /* We're halfway aligning the stack. */
2041 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2042 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2044 /* This will be added back below. */
2045 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2049 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2050 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2056 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2057 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2060 /* Now that we have the base address for the stack frame we can
2061 calculate the value of %rsp in the calling frame. */
2062 cache->saved_sp = cache->base + 16;
2064 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2065 frame we find it at the same offset from the reconstructed base
2066 address. If we're halfway aligning the stack, %rip is handled
2067 differently (see above). */
2068 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2069 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2071 /* Adjust all the saved registers such that they contain addresses
2072 instead of offsets. */
2073 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2074 if (cache->saved_regs[i] != -1)
2075 cache->saved_regs[i] += cache->base;
2080 static struct amd64_frame_cache *
2081 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2083 volatile struct gdb_exception ex;
2084 struct amd64_frame_cache *cache;
2089 cache = amd64_alloc_frame_cache ();
2090 *this_cache = cache;
2092 TRY_CATCH (ex, RETURN_MASK_ERROR)
2094 amd64_frame_cache_1 (this_frame, cache);
2096 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2097 throw_exception (ex);
2102 static enum unwind_stop_reason
2103 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2106 struct amd64_frame_cache *cache =
2107 amd64_frame_cache (this_frame, this_cache);
2110 return UNWIND_UNAVAILABLE;
2112 /* This marks the outermost frame. */
2113 if (cache->base == 0)
2114 return UNWIND_OUTERMOST;
2116 return UNWIND_NO_REASON;
2120 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2121 struct frame_id *this_id)
2123 struct amd64_frame_cache *cache =
2124 amd64_frame_cache (this_frame, this_cache);
2129 /* This marks the outermost frame. */
2130 if (cache->base == 0)
2133 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2136 static struct value *
2137 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2140 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2141 struct amd64_frame_cache *cache =
2142 amd64_frame_cache (this_frame, this_cache);
2144 gdb_assert (regnum >= 0);
2146 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2147 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2149 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2150 return frame_unwind_got_memory (this_frame, regnum,
2151 cache->saved_regs[regnum]);
2153 return frame_unwind_got_register (this_frame, regnum, regnum);
2156 static const struct frame_unwind amd64_frame_unwind =
2159 amd64_frame_unwind_stop_reason,
2160 amd64_frame_this_id,
2161 amd64_frame_prev_register,
2163 default_frame_sniffer
2167 /* Signal trampolines. */
2169 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2170 64-bit variants. This would require using identical frame caches
2171 on both platforms. */
2173 static struct amd64_frame_cache *
2174 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2176 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2177 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2178 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2179 volatile struct gdb_exception ex;
2180 struct amd64_frame_cache *cache;
2188 cache = amd64_alloc_frame_cache ();
2190 TRY_CATCH (ex, RETURN_MASK_ERROR)
2192 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2193 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2195 addr = tdep->sigcontext_addr (this_frame);
2196 gdb_assert (tdep->sc_reg_offset);
2197 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2198 for (i = 0; i < tdep->sc_num_regs; i++)
2199 if (tdep->sc_reg_offset[i] != -1)
2200 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2204 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2205 throw_exception (ex);
2207 *this_cache = cache;
2211 static enum unwind_stop_reason
2212 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2215 struct amd64_frame_cache *cache =
2216 amd64_sigtramp_frame_cache (this_frame, this_cache);
2219 return UNWIND_UNAVAILABLE;
2221 return UNWIND_NO_REASON;
2225 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2226 void **this_cache, struct frame_id *this_id)
2228 struct amd64_frame_cache *cache =
2229 amd64_sigtramp_frame_cache (this_frame, this_cache);
2234 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2237 static struct value *
2238 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2239 void **this_cache, int regnum)
2241 /* Make sure we've initialized the cache. */
2242 amd64_sigtramp_frame_cache (this_frame, this_cache);
2244 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2248 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2249 struct frame_info *this_frame,
2252 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2254 /* We shouldn't even bother if we don't have a sigcontext_addr
2256 if (tdep->sigcontext_addr == NULL)
2259 if (tdep->sigtramp_p != NULL)
2261 if (tdep->sigtramp_p (this_frame))
2265 if (tdep->sigtramp_start != 0)
2267 CORE_ADDR pc = get_frame_pc (this_frame);
2269 gdb_assert (tdep->sigtramp_end != 0);
2270 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2277 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2280 amd64_sigtramp_frame_unwind_stop_reason,
2281 amd64_sigtramp_frame_this_id,
2282 amd64_sigtramp_frame_prev_register,
2284 amd64_sigtramp_frame_sniffer
2289 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2291 struct amd64_frame_cache *cache =
2292 amd64_frame_cache (this_frame, this_cache);
2297 static const struct frame_base amd64_frame_base =
2299 &amd64_frame_unwind,
2300 amd64_frame_base_address,
2301 amd64_frame_base_address,
2302 amd64_frame_base_address
2305 /* Normal frames, but in a function epilogue. */
2307 /* The epilogue is defined here as the 'ret' instruction, which will
2308 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2309 the function's stack frame. */
2312 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2315 struct symtab *symtab;
2317 symtab = find_pc_symtab (pc);
2318 if (symtab && symtab->epilogue_unwind_valid)
2321 if (target_read_memory (pc, &insn, 1))
2322 return 0; /* Can't read memory at pc. */
2324 if (insn != 0xc3) /* 'ret' instruction. */
2331 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2332 struct frame_info *this_frame,
2333 void **this_prologue_cache)
2335 if (frame_relative_level (this_frame) == 0)
2336 return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
2337 get_frame_pc (this_frame));
2342 static struct amd64_frame_cache *
2343 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2345 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2346 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2347 volatile struct gdb_exception ex;
2348 struct amd64_frame_cache *cache;
2354 cache = amd64_alloc_frame_cache ();
2355 *this_cache = cache;
2357 TRY_CATCH (ex, RETURN_MASK_ERROR)
2359 /* Cache base will be %esp plus cache->sp_offset (-8). */
2360 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2361 cache->base = extract_unsigned_integer (buf, 8,
2362 byte_order) + cache->sp_offset;
2364 /* Cache pc will be the frame func. */
2365 cache->pc = get_frame_pc (this_frame);
2367 /* The saved %esp will be at cache->base plus 16. */
2368 cache->saved_sp = cache->base + 16;
2370 /* The saved %eip will be at cache->base plus 8. */
2371 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2375 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2376 throw_exception (ex);
2381 static enum unwind_stop_reason
2382 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2385 struct amd64_frame_cache *cache
2386 = amd64_epilogue_frame_cache (this_frame, this_cache);
2389 return UNWIND_UNAVAILABLE;
2391 return UNWIND_NO_REASON;
2395 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2397 struct frame_id *this_id)
2399 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2405 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2408 static const struct frame_unwind amd64_epilogue_frame_unwind =
2411 amd64_epilogue_frame_unwind_stop_reason,
2412 amd64_epilogue_frame_this_id,
2413 amd64_frame_prev_register,
2415 amd64_epilogue_frame_sniffer
2418 static struct frame_id
2419 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2423 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2425 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2428 /* 16 byte align the SP per frame requirements. */
2431 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2433 return sp & -(CORE_ADDR)16;
2437 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2438 in the floating-point register set REGSET to register cache
2439 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2442 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2443 int regnum, const void *fpregs, size_t len)
2445 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2447 gdb_assert (len == tdep->sizeof_fpregset);
2448 amd64_supply_fxsave (regcache, regnum, fpregs);
2451 /* Collect register REGNUM from the register cache REGCACHE and store
2452 it in the buffer specified by FPREGS and LEN as described by the
2453 floating-point register set REGSET. If REGNUM is -1, do this for
2454 all registers in REGSET. */
2457 amd64_collect_fpregset (const struct regset *regset,
2458 const struct regcache *regcache,
2459 int regnum, void *fpregs, size_t len)
2461 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2463 gdb_assert (len == tdep->sizeof_fpregset);
2464 amd64_collect_fxsave (regcache, regnum, fpregs);
2467 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2470 amd64_supply_xstateregset (const struct regset *regset,
2471 struct regcache *regcache, int regnum,
2472 const void *xstateregs, size_t len)
2474 amd64_supply_xsave (regcache, regnum, xstateregs);
2477 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2480 amd64_collect_xstateregset (const struct regset *regset,
2481 const struct regcache *regcache,
2482 int regnum, void *xstateregs, size_t len)
2484 amd64_collect_xsave (regcache, regnum, xstateregs, 1);
2487 /* Return the appropriate register set for the core section identified
2488 by SECT_NAME and SECT_SIZE. */
2490 static const struct regset *
2491 amd64_regset_from_core_section (struct gdbarch *gdbarch,
2492 const char *sect_name, size_t sect_size)
2494 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2496 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2498 if (tdep->fpregset == NULL)
2499 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
2500 amd64_collect_fpregset);
2502 return tdep->fpregset;
2505 if (strcmp (sect_name, ".reg-xstate") == 0)
2507 if (tdep->xstateregset == NULL)
2508 tdep->xstateregset = regset_alloc (gdbarch,
2509 amd64_supply_xstateregset,
2510 amd64_collect_xstateregset);
2512 return tdep->xstateregset;
2515 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
2519 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2520 %rdi. We expect its value to be a pointer to the jmp_buf structure
2521 from which we extract the address that we will land at. This
2522 address is copied into PC. This routine returns non-zero on
2526 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2530 struct gdbarch *gdbarch = get_frame_arch (frame);
2531 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2532 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2534 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2535 longjmp will land. */
2536 if (jb_pc_offset == -1)
2539 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2540 jb_addr= extract_typed_address
2541 (buf, builtin_type (gdbarch)->builtin_data_ptr);
2542 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2545 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2550 static const int amd64_record_regmap[] =
2552 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2553 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2554 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2555 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2556 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2557 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2561 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2563 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2564 const struct target_desc *tdesc = info.target_desc;
2566 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2567 floating-point registers. */
2568 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2570 if (! tdesc_has_registers (tdesc))
2571 tdesc = tdesc_amd64;
2572 tdep->tdesc = tdesc;
2574 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2575 tdep->register_names = amd64_register_names;
2577 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2579 tdep->ymmh_register_names = amd64_ymmh_names;
2580 tdep->num_ymm_regs = 16;
2581 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
2584 tdep->num_byte_regs = 20;
2585 tdep->num_word_regs = 16;
2586 tdep->num_dword_regs = 16;
2587 /* Avoid wiring in the MMX registers for now. */
2588 tdep->num_mmx_regs = 0;
2590 set_gdbarch_pseudo_register_read_value (gdbarch,
2591 amd64_pseudo_register_read_value);
2592 set_gdbarch_pseudo_register_write (gdbarch,
2593 amd64_pseudo_register_write);
2595 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
2597 /* AMD64 has an FPU and 16 SSE registers. */
2598 tdep->st0_regnum = AMD64_ST0_REGNUM;
2599 tdep->num_xmm_regs = 16;
2601 /* This is what all the fuss is about. */
2602 set_gdbarch_long_bit (gdbarch, 64);
2603 set_gdbarch_long_long_bit (gdbarch, 64);
2604 set_gdbarch_ptr_bit (gdbarch, 64);
2606 /* In contrast to the i386, on AMD64 a `long double' actually takes
2607 up 128 bits, even though it's still based on the i387 extended
2608 floating-point format which has only 80 significant bits. */
2609 set_gdbarch_long_double_bit (gdbarch, 128);
2611 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
2613 /* Register numbers of various important registers. */
2614 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
2615 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
2616 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
2617 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
2619 /* The "default" register numbering scheme for AMD64 is referred to
2620 as the "DWARF Register Number Mapping" in the System V psABI.
2621 The preferred debugging format for all known AMD64 targets is
2622 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2623 DWARF-1), but we provide the same mapping just in case. This
2624 mapping is also used for stabs, which GCC does support. */
2625 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2626 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2628 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2629 be in use on any of the supported AMD64 targets. */
2631 /* Call dummy code. */
2632 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
2633 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
2634 set_gdbarch_frame_red_zone_size (gdbarch, 128);
2635 tdep->call_dummy_num_integer_regs =
2636 ARRAY_SIZE (amd64_dummy_call_integer_regs);
2637 tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs;
2638 tdep->classify = amd64_classify;
2640 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
2641 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
2642 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
2644 set_gdbarch_return_value (gdbarch, amd64_return_value);
2646 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
2648 tdep->record_regmap = amd64_record_regmap;
2650 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
2652 /* Hook the function epilogue frame unwinder. This unwinder is
2653 appended to the list first, so that it supercedes the other
2654 unwinders in function epilogues. */
2655 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
2657 /* Hook the prologue-based frame unwinders. */
2658 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
2659 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
2660 frame_base_set_default (gdbarch, &amd64_frame_base);
2662 /* If we have a register mapping, enable the generic core file support. */
2663 if (tdep->gregset_reg_offset)
2664 set_gdbarch_regset_from_core_section (gdbarch,
2665 amd64_regset_from_core_section);
2667 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
2669 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
2672 /* Provide a prototype to silence -Wmissing-prototypes. */
2673 void _initialize_amd64_tdep (void);
2676 _initialize_amd64_tdep (void)
2678 initialize_tdesc_amd64 ();
2679 initialize_tdesc_amd64_avx ();
2683 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2684 sense that the instruction pointer and data pointer are simply
2685 64-bit offsets into the code segment and the data segment instead
2686 of a selector offset pair. The functions below store the upper 32
2687 bits of these pointers (instead of just the 16-bits of the segment
2690 /* Fill register REGNUM in REGCACHE with the appropriate
2691 floating-point or SSE register value from *FXSAVE. If REGNUM is
2692 -1, do this for all registers. This function masks off any of the
2693 reserved bits in *FXSAVE. */
2696 amd64_supply_fxsave (struct regcache *regcache, int regnum,
2699 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2700 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2702 i387_supply_fxsave (regcache, regnum, fxsave);
2704 if (fxsave && gdbarch_ptr_bit (gdbarch) == 64)
2706 const gdb_byte *regs = fxsave;
2708 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2709 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
2710 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2711 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
2715 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
2718 amd64_supply_xsave (struct regcache *regcache, int regnum,
2721 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2722 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2724 i387_supply_xsave (regcache, regnum, xsave);
2726 if (xsave && gdbarch_ptr_bit (gdbarch) == 64)
2728 const gdb_byte *regs = xsave;
2730 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2731 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
2733 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2734 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
2739 /* Fill register REGNUM (if it is a floating-point or SSE register) in
2740 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
2741 all registers. This function doesn't touch any of the reserved
2745 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
2748 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2749 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2750 gdb_byte *regs = fxsave;
2752 i387_collect_fxsave (regcache, regnum, fxsave);
2754 if (gdbarch_ptr_bit (gdbarch) == 64)
2756 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2757 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
2758 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2759 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
2763 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
2766 amd64_collect_xsave (const struct regcache *regcache, int regnum,
2767 void *xsave, int gcore)
2769 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2770 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2771 gdb_byte *regs = xsave;
2773 i387_collect_xsave (regcache, regnum, xsave, gcore);
2775 if (gdbarch_ptr_bit (gdbarch) == 64)
2777 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2778 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
2780 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2781 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),