1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned by config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
50 /* Register information. */
52 static const char *amd64_register_names[] =
54 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
56 /* %r8 is indeed register number 8. */
57 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
58 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
60 /* %st0 is register number 24. */
61 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
62 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
64 /* %xmm0 is register number 40. */
65 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
66 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
70 /* Total number of registers. */
71 #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names)
73 /* Return the name of register REGNUM. */
76 amd64_register_name (struct gdbarch *gdbarch, int regnum)
78 if (regnum >= 0 && regnum < AMD64_NUM_REGS)
79 return amd64_register_names[regnum];
84 /* Return the GDB type object for the "standard" data type of data in
88 amd64_register_type (struct gdbarch *gdbarch, int regnum)
90 if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM)
91 return builtin_type_int64;
92 if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM)
93 return builtin_type_void_data_ptr;
94 if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM)
95 return builtin_type_int64;
96 if (regnum == AMD64_RIP_REGNUM)
97 return builtin_type_void_func_ptr;
98 if (regnum == AMD64_EFLAGS_REGNUM)
99 return i386_eflags_type;
100 if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM)
101 return builtin_type_int32;
102 if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7)
103 return builtin_type_i387_ext;
104 if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7)
105 return builtin_type_int32;
106 if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15)
107 return i386_sse_type (gdbarch);
108 if (regnum == AMD64_MXCSR_REGNUM)
109 return i386_mxcsr_type;
111 internal_error (__FILE__, __LINE__, _("invalid regnum"));
114 /* DWARF Register Number Mapping as defined in the System V psABI,
117 static int amd64_dwarf_regmap[] =
119 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
120 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
121 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
122 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
124 /* Frame Pointer Register RBP. */
127 /* Stack Pointer Register RSP. */
130 /* Extended Integer Registers 8 - 15. */
131 8, 9, 10, 11, 12, 13, 14, 15,
133 /* Return Address RA. Mapped to RIP. */
136 /* SSE Registers 0 - 7. */
137 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
138 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
139 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
140 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
142 /* Extended SSE Registers 8 - 15. */
143 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
144 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
145 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
146 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
148 /* Floating Point Registers 0-7. */
149 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
150 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
151 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
152 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
154 /* Control and Status Flags Register. */
157 /* Selector Registers. */
167 /* Segment Base Address Registers. */
173 /* Special Selector Registers. */
177 /* Floating Point Control Registers. */
183 static const int amd64_dwarf_regmap_len =
184 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
186 /* Convert DWARF register number REG to the appropriate register
187 number used by GDB. */
190 amd64_dwarf_reg_to_regnum (int reg)
194 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
195 regnum = amd64_dwarf_regmap[reg];
198 warning (_("Unmapped DWARF Register #%d encountered."), reg);
205 /* Register classes as defined in the psABI. */
219 /* Return the union class of CLASS1 and CLASS2. See the psABI for
222 static enum amd64_reg_class
223 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
225 /* Rule (a): If both classes are equal, this is the resulting class. */
226 if (class1 == class2)
229 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
230 is the other class. */
231 if (class1 == AMD64_NO_CLASS)
233 if (class2 == AMD64_NO_CLASS)
236 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
237 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
240 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
241 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
242 return AMD64_INTEGER;
244 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
245 MEMORY is used as class. */
246 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
247 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
248 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
251 /* Rule (f): Otherwise class SSE is used. */
255 static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
257 /* Return non-zero if TYPE is a non-POD structure or union type. */
260 amd64_non_pod_p (struct type *type)
262 /* ??? A class with a base class certainly isn't POD, but does this
263 catch all non-POD structure types? */
264 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
270 /* Classify TYPE according to the rules for aggregate (structures and
271 arrays) and union types, and store the result in CLASS. */
274 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
276 int len = TYPE_LENGTH (type);
278 /* 1. If the size of an object is larger than two eightbytes, or in
279 C++, is a non-POD structure or union type, or contains
280 unaligned fields, it has class memory. */
281 if (len > 16 || amd64_non_pod_p (type))
283 class[0] = class[1] = AMD64_MEMORY;
287 /* 2. Both eightbytes get initialized to class NO_CLASS. */
288 class[0] = class[1] = AMD64_NO_CLASS;
290 /* 3. Each field of an object is classified recursively so that
291 always two fields are considered. The resulting class is
292 calculated according to the classes of the fields in the
295 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
297 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
299 /* All fields in an array have the same type. */
300 amd64_classify (subtype, class);
301 if (len > 8 && class[1] == AMD64_NO_CLASS)
308 /* Structure or union. */
309 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
310 || TYPE_CODE (type) == TYPE_CODE_UNION);
312 for (i = 0; i < TYPE_NFIELDS (type); i++)
314 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
315 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
316 enum amd64_reg_class subclass[2];
318 /* Ignore static fields. */
319 if (TYPE_FIELD_STATIC (type, i))
322 gdb_assert (pos == 0 || pos == 1);
324 amd64_classify (subtype, subclass);
325 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
327 class[1] = amd64_merge_classes (class[1], subclass[1]);
331 /* 4. Then a post merger cleanup is done: */
333 /* Rule (a): If one of the classes is MEMORY, the whole argument is
335 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
336 class[0] = class[1] = AMD64_MEMORY;
338 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
340 if (class[0] == AMD64_SSEUP)
341 class[0] = AMD64_SSE;
342 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
343 class[1] = AMD64_SSE;
346 /* Classify TYPE, and store the result in CLASS. */
349 amd64_classify (struct type *type, enum amd64_reg_class class[2])
351 enum type_code code = TYPE_CODE (type);
352 int len = TYPE_LENGTH (type);
354 class[0] = class[1] = AMD64_NO_CLASS;
356 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
357 long, long long, and pointers are in the INTEGER class. Similarly,
358 range types, used by languages such as Ada, are also in the INTEGER
360 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
361 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
362 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
363 && (len == 1 || len == 2 || len == 4 || len == 8))
364 class[0] = AMD64_INTEGER;
366 /* Arguments of types float, double and __m64 are in class SSE. */
367 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
369 class[0] = AMD64_SSE;
371 /* Arguments of types __float128 and __m128 are split into two
372 halves. The least significant ones belong to class SSE, the most
373 significant one to class SSEUP. */
374 /* FIXME: __float128, __m128. */
376 /* The 64-bit mantissa of arguments of type long double belongs to
377 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
379 else if (code == TYPE_CODE_FLT && len == 16)
380 /* Class X87 and X87UP. */
381 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
384 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
385 || code == TYPE_CODE_UNION)
386 amd64_classify_aggregate (type, class);
389 static enum return_value_convention
390 amd64_return_value (struct gdbarch *gdbarch, struct type *type,
391 struct regcache *regcache,
392 gdb_byte *readbuf, const gdb_byte *writebuf)
394 enum amd64_reg_class class[2];
395 int len = TYPE_LENGTH (type);
396 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
397 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
402 gdb_assert (!(readbuf && writebuf));
404 /* 1. Classify the return type with the classification algorithm. */
405 amd64_classify (type, class);
407 /* 2. If the type has class MEMORY, then the caller provides space
408 for the return value and passes the address of this storage in
409 %rdi as if it were the first argument to the function. In effect,
410 this address becomes a hidden first argument.
412 On return %rax will contain the address that has been passed in
413 by the caller in %rdi. */
414 if (class[0] == AMD64_MEMORY)
416 /* As indicated by the comment above, the ABI guarantees that we
417 can always find the return value just after the function has
424 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
425 read_memory (addr, readbuf, TYPE_LENGTH (type));
428 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
431 gdb_assert (class[1] != AMD64_MEMORY);
432 gdb_assert (len <= 16);
434 for (i = 0; len > 0; i++, len -= 8)
442 /* 3. If the class is INTEGER, the next available register
443 of the sequence %rax, %rdx is used. */
444 regnum = integer_regnum[integer_reg++];
448 /* 4. If the class is SSE, the next available SSE register
449 of the sequence %xmm0, %xmm1 is used. */
450 regnum = sse_regnum[sse_reg++];
454 /* 5. If the class is SSEUP, the eightbyte is passed in the
455 upper half of the last used SSE register. */
456 gdb_assert (sse_reg > 0);
457 regnum = sse_regnum[sse_reg - 1];
462 /* 6. If the class is X87, the value is returned on the X87
463 stack in %st0 as 80-bit x87 number. */
464 regnum = AMD64_ST0_REGNUM;
466 i387_return_value (gdbarch, regcache);
470 /* 7. If the class is X87UP, the value is returned together
471 with the previous X87 value in %st0. */
472 gdb_assert (i > 0 && class[0] == AMD64_X87);
473 regnum = AMD64_ST0_REGNUM;
482 gdb_assert (!"Unexpected register class.");
485 gdb_assert (regnum != -1);
488 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
491 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
495 return RETURN_VALUE_REGISTER_CONVENTION;
500 amd64_push_arguments (struct regcache *regcache, int nargs,
501 struct value **args, CORE_ADDR sp, int struct_return)
503 static int integer_regnum[] =
505 AMD64_RDI_REGNUM, /* %rdi */
506 AMD64_RSI_REGNUM, /* %rsi */
507 AMD64_RDX_REGNUM, /* %rdx */
508 AMD64_RCX_REGNUM, /* %rcx */
512 static int sse_regnum[] =
514 /* %xmm0 ... %xmm7 */
515 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
516 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
517 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
518 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
520 struct value **stack_args = alloca (nargs * sizeof (struct value *));
521 int num_stack_args = 0;
522 int num_elements = 0;
528 /* Reserve a register for the "hidden" argument. */
532 for (i = 0; i < nargs; i++)
534 struct type *type = value_type (args[i]);
535 int len = TYPE_LENGTH (type);
536 enum amd64_reg_class class[2];
537 int needed_integer_regs = 0;
538 int needed_sse_regs = 0;
541 /* Classify argument. */
542 amd64_classify (type, class);
544 /* Calculate the number of integer and SSE registers needed for
546 for (j = 0; j < 2; j++)
548 if (class[j] == AMD64_INTEGER)
549 needed_integer_regs++;
550 else if (class[j] == AMD64_SSE)
554 /* Check whether enough registers are available, and if the
555 argument should be passed in registers at all. */
556 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
557 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
558 || (needed_integer_regs == 0 && needed_sse_regs == 0))
560 /* The argument will be passed on the stack. */
561 num_elements += ((len + 7) / 8);
562 stack_args[num_stack_args++] = args[i];
566 /* The argument will be passed in registers. */
567 const gdb_byte *valbuf = value_contents (args[i]);
570 gdb_assert (len <= 16);
572 for (j = 0; len > 0; j++, len -= 8)
580 regnum = integer_regnum[integer_reg++];
584 regnum = sse_regnum[sse_reg++];
588 gdb_assert (sse_reg > 0);
589 regnum = sse_regnum[sse_reg - 1];
594 gdb_assert (!"Unexpected register class.");
597 gdb_assert (regnum != -1);
598 memset (buf, 0, sizeof buf);
599 memcpy (buf, valbuf + j * 8, min (len, 8));
600 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
605 /* Allocate space for the arguments on the stack. */
606 sp -= num_elements * 8;
608 /* The psABI says that "The end of the input argument area shall be
609 aligned on a 16 byte boundary." */
612 /* Write out the arguments to the stack. */
613 for (i = 0; i < num_stack_args; i++)
615 struct type *type = value_type (stack_args[i]);
616 const gdb_byte *valbuf = value_contents (stack_args[i]);
617 int len = TYPE_LENGTH (type);
619 write_memory (sp + element * 8, valbuf, len);
620 element += ((len + 7) / 8);
623 /* The psABI says that "For calls that may call functions that use
624 varargs or stdargs (prototype-less calls or calls to functions
625 containing ellipsis (...) in the declaration) %al is used as
626 hidden argument to specify the number of SSE registers used. */
627 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
632 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
633 struct regcache *regcache, CORE_ADDR bp_addr,
634 int nargs, struct value **args, CORE_ADDR sp,
635 int struct_return, CORE_ADDR struct_addr)
639 /* Pass arguments. */
640 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
642 /* Pass "hidden" argument". */
645 store_unsigned_integer (buf, 8, struct_addr);
646 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
649 /* Store return address. */
651 store_unsigned_integer (buf, 8, bp_addr);
652 write_memory (sp, buf, 8);
654 /* Finally, update the stack pointer... */
655 store_unsigned_integer (buf, 8, sp);
656 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
658 /* ...and fake a frame pointer. */
659 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
665 /* The maximum number of saved registers. This should include %rip. */
666 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
668 struct amd64_frame_cache
675 /* Saved registers. */
676 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
679 /* Do we have a frame? */
683 /* Initialize a frame cache. */
686 amd64_init_frame_cache (struct amd64_frame_cache *cache)
692 cache->sp_offset = -8;
695 /* Saved registers. We initialize these to -1 since zero is a valid
696 offset (that's where %rbp is supposed to be stored). */
697 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
698 cache->saved_regs[i] = -1;
701 /* Frameless until proven otherwise. */
702 cache->frameless_p = 1;
705 /* Allocate and initialize a frame cache. */
707 static struct amd64_frame_cache *
708 amd64_alloc_frame_cache (void)
710 struct amd64_frame_cache *cache;
712 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
713 amd64_init_frame_cache (cache);
717 /* Do a limited analysis of the prologue at PC and update CACHE
718 accordingly. Bail out early if CURRENT_PC is reached. Return the
719 address where the analysis stopped.
721 We will handle only functions beginning with:
724 movq %rsp, %rbp 0x48 0x89 0xe5
726 Any function that doesn't start with this sequence will be assumed
727 to have no prologue and thus no valid frame pointer in %rbp. */
730 amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
731 struct amd64_frame_cache *cache)
733 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
737 if (current_pc <= pc)
740 op = read_memory_unsigned_integer (pc, 1);
742 if (op == 0x55) /* pushq %rbp */
744 /* Take into account that we've executed the `pushq %rbp' that
745 starts this instruction sequence. */
746 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
747 cache->sp_offset += 8;
749 /* If that's all, return now. */
750 if (current_pc <= pc + 1)
753 /* Check for `movq %rsp, %rbp'. */
754 read_memory (pc + 1, buf, 3);
755 if (memcmp (buf, proto, 3) != 0)
758 /* OK, we actually have a frame. */
759 cache->frameless_p = 0;
766 /* Return PC of first real instruction. */
769 amd64_skip_prologue (CORE_ADDR start_pc)
771 struct amd64_frame_cache cache;
774 amd64_init_frame_cache (&cache);
775 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache);
776 if (cache.frameless_p)
785 static struct amd64_frame_cache *
786 amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
788 struct amd64_frame_cache *cache;
795 cache = amd64_alloc_frame_cache ();
798 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
800 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
802 if (cache->frameless_p)
804 /* We didn't find a valid frame. If we're at the start of a
805 function, or somewhere half-way its prologue, the function's
806 frame probably hasn't been fully setup yet. Try to
807 reconstruct the base address for the stack frame by looking
808 at the stack pointer. For truly "frameless" functions this
811 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
812 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
816 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
817 cache->base = extract_unsigned_integer (buf, 8);
820 /* Now that we have the base address for the stack frame we can
821 calculate the value of %rsp in the calling frame. */
822 cache->saved_sp = cache->base + 16;
824 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
825 frame we find it at the same offset from the reconstructed base
827 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
829 /* Adjust all the saved registers such that they contain addresses
830 instead of offsets. */
831 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
832 if (cache->saved_regs[i] != -1)
833 cache->saved_regs[i] += cache->base;
839 amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
840 struct frame_id *this_id)
842 struct amd64_frame_cache *cache =
843 amd64_frame_cache (next_frame, this_cache);
845 /* This marks the outermost frame. */
846 if (cache->base == 0)
849 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
853 amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
854 int regnum, int *optimizedp,
855 enum lval_type *lvalp, CORE_ADDR *addrp,
856 int *realnump, gdb_byte *valuep)
858 struct gdbarch *gdbarch = get_frame_arch (next_frame);
859 struct amd64_frame_cache *cache =
860 amd64_frame_cache (next_frame, this_cache);
862 gdb_assert (regnum >= 0);
864 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
872 /* Store the value. */
873 store_unsigned_integer (valuep, 8, cache->saved_sp);
878 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
881 *lvalp = lval_memory;
882 *addrp = cache->saved_regs[regnum];
886 /* Read the value in from memory. */
887 read_memory (*addrp, valuep,
888 register_size (gdbarch, regnum));
894 *lvalp = lval_register;
898 frame_unwind_register (next_frame, (*realnump), valuep);
901 static const struct frame_unwind amd64_frame_unwind =
905 amd64_frame_prev_register
908 static const struct frame_unwind *
909 amd64_frame_sniffer (struct frame_info *next_frame)
911 return &amd64_frame_unwind;
915 /* Signal trampolines. */
917 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
918 64-bit variants. This would require using identical frame caches
919 on both platforms. */
921 static struct amd64_frame_cache *
922 amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
924 struct amd64_frame_cache *cache;
925 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
933 cache = amd64_alloc_frame_cache ();
935 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
936 cache->base = extract_unsigned_integer (buf, 8) - 8;
938 addr = tdep->sigcontext_addr (next_frame);
939 gdb_assert (tdep->sc_reg_offset);
940 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
941 for (i = 0; i < tdep->sc_num_regs; i++)
942 if (tdep->sc_reg_offset[i] != -1)
943 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
950 amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
951 void **this_cache, struct frame_id *this_id)
953 struct amd64_frame_cache *cache =
954 amd64_sigtramp_frame_cache (next_frame, this_cache);
956 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
960 amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
962 int regnum, int *optimizedp,
963 enum lval_type *lvalp, CORE_ADDR *addrp,
964 int *realnump, gdb_byte *valuep)
966 /* Make sure we've initialized the cache. */
967 amd64_sigtramp_frame_cache (next_frame, this_cache);
969 amd64_frame_prev_register (next_frame, this_cache, regnum,
970 optimizedp, lvalp, addrp, realnump, valuep);
973 static const struct frame_unwind amd64_sigtramp_frame_unwind =
976 amd64_sigtramp_frame_this_id,
977 amd64_sigtramp_frame_prev_register
980 static const struct frame_unwind *
981 amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
983 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
985 /* We shouldn't even bother if we don't have a sigcontext_addr
987 if (tdep->sigcontext_addr == NULL)
990 if (tdep->sigtramp_p != NULL)
992 if (tdep->sigtramp_p (next_frame))
993 return &amd64_sigtramp_frame_unwind;
996 if (tdep->sigtramp_start != 0)
998 CORE_ADDR pc = frame_pc_unwind (next_frame);
1000 gdb_assert (tdep->sigtramp_end != 0);
1001 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1002 return &amd64_sigtramp_frame_unwind;
1010 amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1012 struct amd64_frame_cache *cache =
1013 amd64_frame_cache (next_frame, this_cache);
1018 static const struct frame_base amd64_frame_base =
1020 &amd64_frame_unwind,
1021 amd64_frame_base_address,
1022 amd64_frame_base_address,
1023 amd64_frame_base_address
1026 static struct frame_id
1027 amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1032 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
1033 fp = extract_unsigned_integer (buf, 8);
1035 return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
1038 /* 16 byte align the SP per frame requirements. */
1041 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1043 return sp & -(CORE_ADDR)16;
1047 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
1048 in the floating-point register set REGSET to register cache
1049 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
1052 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
1053 int regnum, const void *fpregs, size_t len)
1055 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1057 gdb_assert (len == tdep->sizeof_fpregset);
1058 amd64_supply_fxsave (regcache, regnum, fpregs);
1061 /* Collect register REGNUM from the register cache REGCACHE and store
1062 it in the buffer specified by FPREGS and LEN as described by the
1063 floating-point register set REGSET. If REGNUM is -1, do this for
1064 all registers in REGSET. */
1067 amd64_collect_fpregset (const struct regset *regset,
1068 const struct regcache *regcache,
1069 int regnum, void *fpregs, size_t len)
1071 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1073 gdb_assert (len == tdep->sizeof_fpregset);
1074 amd64_collect_fxsave (regcache, regnum, fpregs);
1077 /* Return the appropriate register set for the core section identified
1078 by SECT_NAME and SECT_SIZE. */
1080 static const struct regset *
1081 amd64_regset_from_core_section (struct gdbarch *gdbarch,
1082 const char *sect_name, size_t sect_size)
1084 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1086 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
1088 if (tdep->fpregset == NULL)
1089 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
1090 amd64_collect_fpregset);
1092 return tdep->fpregset;
1095 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
1100 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1102 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1104 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1105 floating-point registers. */
1106 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
1108 /* AMD64 has an FPU and 16 SSE registers. */
1109 tdep->st0_regnum = AMD64_ST0_REGNUM;
1110 tdep->num_xmm_regs = 16;
1112 /* This is what all the fuss is about. */
1113 set_gdbarch_long_bit (gdbarch, 64);
1114 set_gdbarch_long_long_bit (gdbarch, 64);
1115 set_gdbarch_ptr_bit (gdbarch, 64);
1117 /* In contrast to the i386, on AMD64 a `long double' actually takes
1118 up 128 bits, even though it's still based on the i387 extended
1119 floating-point format which has only 80 significant bits. */
1120 set_gdbarch_long_double_bit (gdbarch, 128);
1122 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
1123 set_gdbarch_register_name (gdbarch, amd64_register_name);
1124 set_gdbarch_register_type (gdbarch, amd64_register_type);
1126 /* Register numbers of various important registers. */
1127 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
1128 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
1129 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
1130 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
1132 /* The "default" register numbering scheme for AMD64 is referred to
1133 as the "DWARF Register Number Mapping" in the System V psABI.
1134 The preferred debugging format for all known AMD64 targets is
1135 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1136 DWARF-1), but we provide the same mapping just in case. This
1137 mapping is also used for stabs, which GCC does support. */
1138 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1139 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1140 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1142 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1143 be in use on any of the supported AMD64 targets. */
1145 /* Call dummy code. */
1146 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
1147 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
1148 set_gdbarch_frame_red_zone_size (gdbarch, 128);
1150 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
1151 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1152 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1154 set_gdbarch_return_value (gdbarch, amd64_return_value);
1156 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
1158 /* Avoid wiring in the MMX registers for now. */
1159 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1160 tdep->mm0_regnum = -1;
1162 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
1164 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
1165 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
1166 frame_base_set_default (gdbarch, &amd64_frame_base);
1168 /* If we have a register mapping, enable the generic core file support. */
1169 if (tdep->gregset_reg_offset)
1170 set_gdbarch_regset_from_core_section (gdbarch,
1171 amd64_regset_from_core_section);
1175 #define I387_ST0_REGNUM AMD64_ST0_REGNUM
1177 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1178 sense that the instruction pointer and data pointer are simply
1179 64-bit offsets into the code segment and the data segment instead
1180 of a selector offset pair. The functions below store the upper 32
1181 bits of these pointers (instead of just the 16-bits of the segment
1184 /* Fill register REGNUM in REGCACHE with the appropriate
1185 floating-point or SSE register value from *FXSAVE. If REGNUM is
1186 -1, do this for all registers. This function masks off any of the
1187 reserved bits in *FXSAVE. */
1190 amd64_supply_fxsave (struct regcache *regcache, int regnum,
1193 i387_supply_fxsave (regcache, regnum, fxsave);
1195 if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1197 const gdb_byte *regs = fxsave;
1199 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1200 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
1201 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1202 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
1206 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1207 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
1208 all registers. This function doesn't touch any of the reserved
1212 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
1215 gdb_byte *regs = fxsave;
1217 i387_collect_fxsave (regcache, regnum, fxsave);
1219 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1221 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1222 regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12);
1223 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1224 regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20);