1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned by config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
50 /* Register information. */
52 static const char *amd64_register_names[] =
54 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
56 /* %r8 is indeed register number 8. */
57 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
58 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
60 /* %st0 is register number 24. */
61 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
62 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
64 /* %xmm0 is register number 40. */
65 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
66 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
70 /* Total number of registers. */
71 #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names)
73 /* Return the name of register REGNUM. */
76 amd64_register_name (struct gdbarch *gdbarch, int regnum)
78 if (regnum >= 0 && regnum < AMD64_NUM_REGS)
79 return amd64_register_names[regnum];
84 /* Return the GDB type object for the "standard" data type of data in
88 amd64_register_type (struct gdbarch *gdbarch, int regnum)
90 if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM)
91 return builtin_type_int64;
92 if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM)
93 return builtin_type (gdbarch)->builtin_data_ptr;
94 if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM)
95 return builtin_type_int64;
96 if (regnum == AMD64_RIP_REGNUM)
97 return builtin_type (gdbarch)->builtin_func_ptr;
98 if (regnum == AMD64_EFLAGS_REGNUM)
99 return i386_eflags_type;
100 if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM)
101 return builtin_type_int32;
102 if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7)
103 return builtin_type_i387_ext;
104 if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7)
105 return builtin_type_int32;
106 if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15)
107 return i386_sse_type (gdbarch);
108 if (regnum == AMD64_MXCSR_REGNUM)
109 return i386_mxcsr_type;
111 internal_error (__FILE__, __LINE__, _("invalid regnum"));
114 /* DWARF Register Number Mapping as defined in the System V psABI,
117 static int amd64_dwarf_regmap[] =
119 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
120 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
121 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
122 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
124 /* Frame Pointer Register RBP. */
127 /* Stack Pointer Register RSP. */
130 /* Extended Integer Registers 8 - 15. */
131 8, 9, 10, 11, 12, 13, 14, 15,
133 /* Return Address RA. Mapped to RIP. */
136 /* SSE Registers 0 - 7. */
137 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
138 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
139 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
140 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
142 /* Extended SSE Registers 8 - 15. */
143 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
144 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
145 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
146 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
148 /* Floating Point Registers 0-7. */
149 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
150 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
151 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
152 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
154 /* Control and Status Flags Register. */
157 /* Selector Registers. */
167 /* Segment Base Address Registers. */
173 /* Special Selector Registers. */
177 /* Floating Point Control Registers. */
183 static const int amd64_dwarf_regmap_len =
184 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
186 /* Convert DWARF register number REG to the appropriate register
187 number used by GDB. */
190 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
194 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
195 regnum = amd64_dwarf_regmap[reg];
198 warning (_("Unmapped DWARF Register #%d encountered."), reg);
205 /* Register classes as defined in the psABI. */
219 /* Return the union class of CLASS1 and CLASS2. See the psABI for
222 static enum amd64_reg_class
223 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
225 /* Rule (a): If both classes are equal, this is the resulting class. */
226 if (class1 == class2)
229 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
230 is the other class. */
231 if (class1 == AMD64_NO_CLASS)
233 if (class2 == AMD64_NO_CLASS)
236 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
237 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
240 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
241 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
242 return AMD64_INTEGER;
244 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
245 MEMORY is used as class. */
246 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
247 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
248 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
251 /* Rule (f): Otherwise class SSE is used. */
255 static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
257 /* Return non-zero if TYPE is a non-POD structure or union type. */
260 amd64_non_pod_p (struct type *type)
262 /* ??? A class with a base class certainly isn't POD, but does this
263 catch all non-POD structure types? */
264 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
270 /* Classify TYPE according to the rules for aggregate (structures and
271 arrays) and union types, and store the result in CLASS. */
274 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
276 int len = TYPE_LENGTH (type);
278 /* 1. If the size of an object is larger than two eightbytes, or in
279 C++, is a non-POD structure or union type, or contains
280 unaligned fields, it has class memory. */
281 if (len > 16 || amd64_non_pod_p (type))
283 class[0] = class[1] = AMD64_MEMORY;
287 /* 2. Both eightbytes get initialized to class NO_CLASS. */
288 class[0] = class[1] = AMD64_NO_CLASS;
290 /* 3. Each field of an object is classified recursively so that
291 always two fields are considered. The resulting class is
292 calculated according to the classes of the fields in the
295 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
297 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
299 /* All fields in an array have the same type. */
300 amd64_classify (subtype, class);
301 if (len > 8 && class[1] == AMD64_NO_CLASS)
308 /* Structure or union. */
309 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
310 || TYPE_CODE (type) == TYPE_CODE_UNION);
312 for (i = 0; i < TYPE_NFIELDS (type); i++)
314 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
315 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
316 enum amd64_reg_class subclass[2];
318 /* Ignore static fields. */
319 if (field_is_static (&TYPE_FIELD (type, i)))
322 gdb_assert (pos == 0 || pos == 1);
324 amd64_classify (subtype, subclass);
325 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
327 class[1] = amd64_merge_classes (class[1], subclass[1]);
331 /* 4. Then a post merger cleanup is done: */
333 /* Rule (a): If one of the classes is MEMORY, the whole argument is
335 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
336 class[0] = class[1] = AMD64_MEMORY;
338 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
340 if (class[0] == AMD64_SSEUP)
341 class[0] = AMD64_SSE;
342 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
343 class[1] = AMD64_SSE;
346 /* Classify TYPE, and store the result in CLASS. */
349 amd64_classify (struct type *type, enum amd64_reg_class class[2])
351 enum type_code code = TYPE_CODE (type);
352 int len = TYPE_LENGTH (type);
354 class[0] = class[1] = AMD64_NO_CLASS;
356 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
357 long, long long, and pointers are in the INTEGER class. Similarly,
358 range types, used by languages such as Ada, are also in the INTEGER
360 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
361 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
362 || code == TYPE_CODE_CHAR
363 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
364 && (len == 1 || len == 2 || len == 4 || len == 8))
365 class[0] = AMD64_INTEGER;
367 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
369 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
370 && (len == 4 || len == 8))
372 class[0] = AMD64_SSE;
374 /* Arguments of types __float128, _Decimal128 and __m128 are split into
375 two halves. The least significant ones belong to class SSE, the most
376 significant one to class SSEUP. */
377 else if (code == TYPE_CODE_DECFLOAT && len == 16)
378 /* FIXME: __float128, __m128. */
379 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
381 /* The 64-bit mantissa of arguments of type long double belongs to
382 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
384 else if (code == TYPE_CODE_FLT && len == 16)
385 /* Class X87 and X87UP. */
386 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
389 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
390 || code == TYPE_CODE_UNION)
391 amd64_classify_aggregate (type, class);
394 static enum return_value_convention
395 amd64_return_value (struct gdbarch *gdbarch, struct type *func_type,
396 struct type *type, struct regcache *regcache,
397 gdb_byte *readbuf, const gdb_byte *writebuf)
399 enum amd64_reg_class class[2];
400 int len = TYPE_LENGTH (type);
401 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
402 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
407 gdb_assert (!(readbuf && writebuf));
409 /* 1. Classify the return type with the classification algorithm. */
410 amd64_classify (type, class);
412 /* 2. If the type has class MEMORY, then the caller provides space
413 for the return value and passes the address of this storage in
414 %rdi as if it were the first argument to the function. In effect,
415 this address becomes a hidden first argument.
417 On return %rax will contain the address that has been passed in
418 by the caller in %rdi. */
419 if (class[0] == AMD64_MEMORY)
421 /* As indicated by the comment above, the ABI guarantees that we
422 can always find the return value just after the function has
429 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
430 read_memory (addr, readbuf, TYPE_LENGTH (type));
433 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
436 gdb_assert (class[1] != AMD64_MEMORY);
437 gdb_assert (len <= 16);
439 for (i = 0; len > 0; i++, len -= 8)
447 /* 3. If the class is INTEGER, the next available register
448 of the sequence %rax, %rdx is used. */
449 regnum = integer_regnum[integer_reg++];
453 /* 4. If the class is SSE, the next available SSE register
454 of the sequence %xmm0, %xmm1 is used. */
455 regnum = sse_regnum[sse_reg++];
459 /* 5. If the class is SSEUP, the eightbyte is passed in the
460 upper half of the last used SSE register. */
461 gdb_assert (sse_reg > 0);
462 regnum = sse_regnum[sse_reg - 1];
467 /* 6. If the class is X87, the value is returned on the X87
468 stack in %st0 as 80-bit x87 number. */
469 regnum = AMD64_ST0_REGNUM;
471 i387_return_value (gdbarch, regcache);
475 /* 7. If the class is X87UP, the value is returned together
476 with the previous X87 value in %st0. */
477 gdb_assert (i > 0 && class[0] == AMD64_X87);
478 regnum = AMD64_ST0_REGNUM;
487 gdb_assert (!"Unexpected register class.");
490 gdb_assert (regnum != -1);
493 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
496 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
500 return RETURN_VALUE_REGISTER_CONVENTION;
505 amd64_push_arguments (struct regcache *regcache, int nargs,
506 struct value **args, CORE_ADDR sp, int struct_return)
508 static int integer_regnum[] =
510 AMD64_RDI_REGNUM, /* %rdi */
511 AMD64_RSI_REGNUM, /* %rsi */
512 AMD64_RDX_REGNUM, /* %rdx */
513 AMD64_RCX_REGNUM, /* %rcx */
517 static int sse_regnum[] =
519 /* %xmm0 ... %xmm7 */
520 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
521 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
522 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
523 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
525 struct value **stack_args = alloca (nargs * sizeof (struct value *));
526 int num_stack_args = 0;
527 int num_elements = 0;
533 /* Reserve a register for the "hidden" argument. */
537 for (i = 0; i < nargs; i++)
539 struct type *type = value_type (args[i]);
540 int len = TYPE_LENGTH (type);
541 enum amd64_reg_class class[2];
542 int needed_integer_regs = 0;
543 int needed_sse_regs = 0;
546 /* Classify argument. */
547 amd64_classify (type, class);
549 /* Calculate the number of integer and SSE registers needed for
551 for (j = 0; j < 2; j++)
553 if (class[j] == AMD64_INTEGER)
554 needed_integer_regs++;
555 else if (class[j] == AMD64_SSE)
559 /* Check whether enough registers are available, and if the
560 argument should be passed in registers at all. */
561 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
562 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
563 || (needed_integer_regs == 0 && needed_sse_regs == 0))
565 /* The argument will be passed on the stack. */
566 num_elements += ((len + 7) / 8);
567 stack_args[num_stack_args++] = args[i];
571 /* The argument will be passed in registers. */
572 const gdb_byte *valbuf = value_contents (args[i]);
575 gdb_assert (len <= 16);
577 for (j = 0; len > 0; j++, len -= 8)
585 regnum = integer_regnum[integer_reg++];
589 regnum = sse_regnum[sse_reg++];
593 gdb_assert (sse_reg > 0);
594 regnum = sse_regnum[sse_reg - 1];
599 gdb_assert (!"Unexpected register class.");
602 gdb_assert (regnum != -1);
603 memset (buf, 0, sizeof buf);
604 memcpy (buf, valbuf + j * 8, min (len, 8));
605 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
610 /* Allocate space for the arguments on the stack. */
611 sp -= num_elements * 8;
613 /* The psABI says that "The end of the input argument area shall be
614 aligned on a 16 byte boundary." */
617 /* Write out the arguments to the stack. */
618 for (i = 0; i < num_stack_args; i++)
620 struct type *type = value_type (stack_args[i]);
621 const gdb_byte *valbuf = value_contents (stack_args[i]);
622 int len = TYPE_LENGTH (type);
624 write_memory (sp + element * 8, valbuf, len);
625 element += ((len + 7) / 8);
628 /* The psABI says that "For calls that may call functions that use
629 varargs or stdargs (prototype-less calls or calls to functions
630 containing ellipsis (...) in the declaration) %al is used as
631 hidden argument to specify the number of SSE registers used. */
632 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
637 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
638 struct regcache *regcache, CORE_ADDR bp_addr,
639 int nargs, struct value **args, CORE_ADDR sp,
640 int struct_return, CORE_ADDR struct_addr)
644 /* Pass arguments. */
645 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
647 /* Pass "hidden" argument". */
650 store_unsigned_integer (buf, 8, struct_addr);
651 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
654 /* Store return address. */
656 store_unsigned_integer (buf, 8, bp_addr);
657 write_memory (sp, buf, 8);
659 /* Finally, update the stack pointer... */
660 store_unsigned_integer (buf, 8, sp);
661 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
663 /* ...and fake a frame pointer. */
664 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
670 /* The maximum number of saved registers. This should include %rip. */
671 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
673 struct amd64_frame_cache
680 /* Saved registers. */
681 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
685 /* Do we have a frame? */
689 /* Initialize a frame cache. */
692 amd64_init_frame_cache (struct amd64_frame_cache *cache)
698 cache->sp_offset = -8;
701 /* Saved registers. We initialize these to -1 since zero is a valid
702 offset (that's where %rbp is supposed to be stored). */
703 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
704 cache->saved_regs[i] = -1;
706 cache->saved_sp_reg = -1;
708 /* Frameless until proven otherwise. */
709 cache->frameless_p = 1;
712 /* Allocate and initialize a frame cache. */
714 static struct amd64_frame_cache *
715 amd64_alloc_frame_cache (void)
717 struct amd64_frame_cache *cache;
719 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
720 amd64_init_frame_cache (cache);
724 /* GCC 4.4 and later, can put code in the prologue to realign the
725 stack pointer. Check whether PC points to such code, and update
726 CACHE accordingly. Return the first instruction after the code
727 sequence or CURRENT_PC, whichever is smaller. If we don't
728 recognize the code, return PC. */
731 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
732 struct amd64_frame_cache *cache)
734 /* There are 2 code sequences to re-align stack before the frame
737 1. Use a caller-saved saved register:
743 2. Use a callee-saved saved register:
750 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
752 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
753 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
758 int offset, offset_and;
759 static int regnums[16] = {
760 AMD64_RAX_REGNUM, /* %rax */
761 AMD64_RCX_REGNUM, /* %rcx */
762 AMD64_RDX_REGNUM, /* %rdx */
763 AMD64_RBX_REGNUM, /* %rbx */
764 AMD64_RSP_REGNUM, /* %rsp */
765 AMD64_RBP_REGNUM, /* %rbp */
766 AMD64_RSI_REGNUM, /* %rsi */
767 AMD64_RDI_REGNUM, /* %rdi */
768 AMD64_R8_REGNUM, /* %r8 */
769 AMD64_R9_REGNUM, /* %r9 */
770 AMD64_R10_REGNUM, /* %r10 */
771 AMD64_R11_REGNUM, /* %r11 */
772 AMD64_R12_REGNUM, /* %r12 */
773 AMD64_R13_REGNUM, /* %r13 */
774 AMD64_R14_REGNUM, /* %r14 */
775 AMD64_R15_REGNUM, /* %r15 */
778 if (target_read_memory (pc, buf, sizeof buf))
781 /* Check caller-saved saved register. The first instruction has
782 to be "leaq 8(%rsp), %reg". */
783 if ((buf[0] & 0xfb) == 0x48
788 /* MOD must be binary 10 and R/M must be binary 100. */
789 if ((buf[2] & 0xc7) != 0x44)
792 /* REG has register number. */
793 reg = (buf[2] >> 3) & 7;
795 /* Check the REX.R bit. */
803 /* Check callee-saved saved register. The first instruction
804 has to be "pushq %reg". */
806 if ((buf[0] & 0xf8) == 0x50)
808 else if ((buf[0] & 0xf6) == 0x40
809 && (buf[1] & 0xf8) == 0x50)
811 /* Check the REX.B bit. */
812 if ((buf[0] & 1) != 0)
821 reg += buf[offset] & 0x7;
825 /* The next instruction has to be "leaq 16(%rsp), %reg". */
826 if ((buf[offset] & 0xfb) != 0x48
827 || buf[offset + 1] != 0x8d
828 || buf[offset + 3] != 0x24
829 || buf[offset + 4] != 0x10)
832 /* MOD must be binary 10 and R/M must be binary 100. */
833 if ((buf[offset + 2] & 0xc7) != 0x44)
836 /* REG has register number. */
837 r = (buf[offset + 2] >> 3) & 7;
839 /* Check the REX.R bit. */
840 if (buf[offset] == 0x4c)
843 /* Registers in pushq and leaq have to be the same. */
850 /* Rigister can't be %rsp nor %rbp. */
851 if (reg == 4 || reg == 5)
854 /* The next instruction has to be "andq $-XXX, %rsp". */
855 if (buf[offset] != 0x48
856 || buf[offset + 2] != 0xe4
857 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
861 offset += buf[offset + 1] == 0x81 ? 7 : 4;
863 /* The next instruction has to be "pushq -8(%reg)". */
865 if (buf[offset] == 0xff)
867 else if ((buf[offset] & 0xf6) == 0x40
868 && buf[offset + 1] == 0xff)
870 /* Check the REX.B bit. */
871 if ((buf[offset] & 0x1) != 0)
878 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
880 if (buf[offset + 1] != 0xf8
881 || (buf[offset] & 0xf8) != 0x70)
884 /* R/M has register. */
885 r += buf[offset] & 7;
887 /* Registers in leaq and pushq have to be the same. */
891 if (current_pc > pc + offset_and)
892 cache->saved_sp_reg = regnums[reg];
894 return min (pc + offset + 2, current_pc);
897 /* Do a limited analysis of the prologue at PC and update CACHE
898 accordingly. Bail out early if CURRENT_PC is reached. Return the
899 address where the analysis stopped.
901 We will handle only functions beginning with:
904 movq %rsp, %rbp 0x48 0x89 0xe5
906 Any function that doesn't start with this sequence will be assumed
907 to have no prologue and thus no valid frame pointer in %rbp. */
910 amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
911 struct amd64_frame_cache *cache)
913 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
917 if (current_pc <= pc)
920 pc = amd64_analyze_stack_align (pc, current_pc, cache);
922 op = read_memory_unsigned_integer (pc, 1);
924 if (op == 0x55) /* pushq %rbp */
926 /* Take into account that we've executed the `pushq %rbp' that
927 starts this instruction sequence. */
928 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
929 cache->sp_offset += 8;
931 /* If that's all, return now. */
932 if (current_pc <= pc + 1)
935 /* Check for `movq %rsp, %rbp'. */
936 read_memory (pc + 1, buf, 3);
937 if (memcmp (buf, proto, 3) != 0)
940 /* OK, we actually have a frame. */
941 cache->frameless_p = 0;
948 /* Return PC of first real instruction. */
951 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
953 struct amd64_frame_cache cache;
956 amd64_init_frame_cache (&cache);
957 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache);
958 if (cache.frameless_p)
967 static struct amd64_frame_cache *
968 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
970 struct amd64_frame_cache *cache;
977 cache = amd64_alloc_frame_cache ();
980 cache->pc = get_frame_func (this_frame);
982 amd64_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache);
984 if (cache->saved_sp_reg != -1)
986 /* Stack pointer has been saved. */
987 get_frame_register (this_frame, cache->saved_sp_reg, buf);
988 cache->saved_sp = extract_unsigned_integer(buf, 8);
991 if (cache->frameless_p)
993 /* We didn't find a valid frame. If we're at the start of a
994 function, or somewhere half-way its prologue, the function's
995 frame probably hasn't been fully setup yet. Try to
996 reconstruct the base address for the stack frame by looking
997 at the stack pointer. For truly "frameless" functions this
1000 if (cache->saved_sp_reg != -1)
1002 /* We're halfway aligning the stack. */
1003 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
1004 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
1006 /* This will be added back below. */
1007 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
1011 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
1012 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
1017 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
1018 cache->base = extract_unsigned_integer (buf, 8);
1021 /* Now that we have the base address for the stack frame we can
1022 calculate the value of %rsp in the calling frame. */
1023 cache->saved_sp = cache->base + 16;
1025 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
1026 frame we find it at the same offset from the reconstructed base
1027 address. If we're halfway aligning the stack, %rip is handled
1028 differently (see above). */
1029 if (!cache->frameless_p || cache->saved_sp_reg == -1)
1030 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
1032 /* Adjust all the saved registers such that they contain addresses
1033 instead of offsets. */
1034 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1035 if (cache->saved_regs[i] != -1)
1036 cache->saved_regs[i] += cache->base;
1042 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
1043 struct frame_id *this_id)
1045 struct amd64_frame_cache *cache =
1046 amd64_frame_cache (this_frame, this_cache);
1048 /* This marks the outermost frame. */
1049 if (cache->base == 0)
1052 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
1055 static struct value *
1056 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1059 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1060 struct amd64_frame_cache *cache =
1061 amd64_frame_cache (this_frame, this_cache);
1063 gdb_assert (regnum >= 0);
1065 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
1066 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1068 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1069 return frame_unwind_got_memory (this_frame, regnum,
1070 cache->saved_regs[regnum]);
1072 return frame_unwind_got_register (this_frame, regnum, regnum);
1075 static const struct frame_unwind amd64_frame_unwind =
1078 amd64_frame_this_id,
1079 amd64_frame_prev_register,
1081 default_frame_sniffer
1085 /* Signal trampolines. */
1087 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1088 64-bit variants. This would require using identical frame caches
1089 on both platforms. */
1091 static struct amd64_frame_cache *
1092 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1094 struct amd64_frame_cache *cache;
1095 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1103 cache = amd64_alloc_frame_cache ();
1105 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
1106 cache->base = extract_unsigned_integer (buf, 8) - 8;
1108 addr = tdep->sigcontext_addr (this_frame);
1109 gdb_assert (tdep->sc_reg_offset);
1110 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
1111 for (i = 0; i < tdep->sc_num_regs; i++)
1112 if (tdep->sc_reg_offset[i] != -1)
1113 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1115 *this_cache = cache;
1120 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
1121 void **this_cache, struct frame_id *this_id)
1123 struct amd64_frame_cache *cache =
1124 amd64_sigtramp_frame_cache (this_frame, this_cache);
1126 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
1129 static struct value *
1130 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
1131 void **this_cache, int regnum)
1133 /* Make sure we've initialized the cache. */
1134 amd64_sigtramp_frame_cache (this_frame, this_cache);
1136 return amd64_frame_prev_register (this_frame, this_cache, regnum);
1140 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
1141 struct frame_info *this_frame,
1144 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1146 /* We shouldn't even bother if we don't have a sigcontext_addr
1148 if (tdep->sigcontext_addr == NULL)
1151 if (tdep->sigtramp_p != NULL)
1153 if (tdep->sigtramp_p (this_frame))
1157 if (tdep->sigtramp_start != 0)
1159 CORE_ADDR pc = get_frame_pc (this_frame);
1161 gdb_assert (tdep->sigtramp_end != 0);
1162 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1169 static const struct frame_unwind amd64_sigtramp_frame_unwind =
1172 amd64_sigtramp_frame_this_id,
1173 amd64_sigtramp_frame_prev_register,
1175 amd64_sigtramp_frame_sniffer
1180 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
1182 struct amd64_frame_cache *cache =
1183 amd64_frame_cache (this_frame, this_cache);
1188 static const struct frame_base amd64_frame_base =
1190 &amd64_frame_unwind,
1191 amd64_frame_base_address,
1192 amd64_frame_base_address,
1193 amd64_frame_base_address
1196 static struct frame_id
1197 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1201 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
1203 return frame_id_build (fp + 16, get_frame_pc (this_frame));
1206 /* 16 byte align the SP per frame requirements. */
1209 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1211 return sp & -(CORE_ADDR)16;
1215 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
1216 in the floating-point register set REGSET to register cache
1217 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
1220 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
1221 int regnum, const void *fpregs, size_t len)
1223 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1225 gdb_assert (len == tdep->sizeof_fpregset);
1226 amd64_supply_fxsave (regcache, regnum, fpregs);
1229 /* Collect register REGNUM from the register cache REGCACHE and store
1230 it in the buffer specified by FPREGS and LEN as described by the
1231 floating-point register set REGSET. If REGNUM is -1, do this for
1232 all registers in REGSET. */
1235 amd64_collect_fpregset (const struct regset *regset,
1236 const struct regcache *regcache,
1237 int regnum, void *fpregs, size_t len)
1239 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1241 gdb_assert (len == tdep->sizeof_fpregset);
1242 amd64_collect_fxsave (regcache, regnum, fpregs);
1245 /* Return the appropriate register set for the core section identified
1246 by SECT_NAME and SECT_SIZE. */
1248 static const struct regset *
1249 amd64_regset_from_core_section (struct gdbarch *gdbarch,
1250 const char *sect_name, size_t sect_size)
1252 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1254 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
1256 if (tdep->fpregset == NULL)
1257 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
1258 amd64_collect_fpregset);
1260 return tdep->fpregset;
1263 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
1267 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
1268 %rdi. We expect its value to be a pointer to the jmp_buf structure
1269 from which we extract the address that we will land at. This
1270 address is copied into PC. This routine returns non-zero on
1274 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1278 struct gdbarch *gdbarch = get_frame_arch (frame);
1279 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1280 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
1282 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1283 longjmp will land. */
1284 if (jb_pc_offset == -1)
1287 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
1288 jb_addr= extract_typed_address
1289 (buf, builtin_type (gdbarch)->builtin_data_ptr);
1290 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
1293 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1299 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1301 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1303 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1304 floating-point registers. */
1305 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
1307 /* AMD64 has an FPU and 16 SSE registers. */
1308 tdep->st0_regnum = AMD64_ST0_REGNUM;
1309 tdep->num_xmm_regs = 16;
1311 /* This is what all the fuss is about. */
1312 set_gdbarch_long_bit (gdbarch, 64);
1313 set_gdbarch_long_long_bit (gdbarch, 64);
1314 set_gdbarch_ptr_bit (gdbarch, 64);
1316 /* In contrast to the i386, on AMD64 a `long double' actually takes
1317 up 128 bits, even though it's still based on the i387 extended
1318 floating-point format which has only 80 significant bits. */
1319 set_gdbarch_long_double_bit (gdbarch, 128);
1321 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
1322 set_gdbarch_register_name (gdbarch, amd64_register_name);
1323 set_gdbarch_register_type (gdbarch, amd64_register_type);
1325 /* Register numbers of various important registers. */
1326 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
1327 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
1328 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
1329 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
1331 /* The "default" register numbering scheme for AMD64 is referred to
1332 as the "DWARF Register Number Mapping" in the System V psABI.
1333 The preferred debugging format for all known AMD64 targets is
1334 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1335 DWARF-1), but we provide the same mapping just in case. This
1336 mapping is also used for stabs, which GCC does support. */
1337 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1338 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1340 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1341 be in use on any of the supported AMD64 targets. */
1343 /* Call dummy code. */
1344 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
1345 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
1346 set_gdbarch_frame_red_zone_size (gdbarch, 128);
1348 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
1349 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1350 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1352 set_gdbarch_return_value (gdbarch, amd64_return_value);
1354 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
1356 /* Avoid wiring in the MMX registers for now. */
1357 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1358 tdep->mm0_regnum = -1;
1360 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
1362 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
1363 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
1364 frame_base_set_default (gdbarch, &amd64_frame_base);
1366 /* If we have a register mapping, enable the generic core file support. */
1367 if (tdep->gregset_reg_offset)
1368 set_gdbarch_regset_from_core_section (gdbarch,
1369 amd64_regset_from_core_section);
1371 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
1375 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1376 sense that the instruction pointer and data pointer are simply
1377 64-bit offsets into the code segment and the data segment instead
1378 of a selector offset pair. The functions below store the upper 32
1379 bits of these pointers (instead of just the 16-bits of the segment
1382 /* Fill register REGNUM in REGCACHE with the appropriate
1383 floating-point or SSE register value from *FXSAVE. If REGNUM is
1384 -1, do this for all registers. This function masks off any of the
1385 reserved bits in *FXSAVE. */
1388 amd64_supply_fxsave (struct regcache *regcache, int regnum,
1391 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1392 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1394 i387_supply_fxsave (regcache, regnum, fxsave);
1396 if (fxsave && gdbarch_ptr_bit (gdbarch) == 64)
1398 const gdb_byte *regs = fxsave;
1400 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
1401 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
1402 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
1403 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
1407 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1408 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
1409 all registers. This function doesn't touch any of the reserved
1413 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
1416 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1418 gdb_byte *regs = fxsave;
1420 i387_collect_fxsave (regcache, regnum, fxsave);
1422 if (gdbarch_ptr_bit (gdbarch) == 64)
1424 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
1425 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
1426 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
1427 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);