1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
52 /* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
54 returned by config.guess, and used as the name for the AMD64 port
55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
59 /* Register information. */
61 static const char *amd64_register_names[] =
63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
65 /* %r8 is indeed register number 8. */
66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
69 /* %st0 is register number 24. */
70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
73 /* %xmm0 is register number 40. */
74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
79 static const char *amd64_ymm_names[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
87 static const char *amd64_ymmh_names[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
95 /* DWARF Register Number Mapping as defined in the System V psABI,
98 static int amd64_dwarf_regmap[] =
100 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
101 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
102 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
103 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
105 /* Frame Pointer Register RBP. */
108 /* Stack Pointer Register RSP. */
111 /* Extended Integer Registers 8 - 15. */
112 8, 9, 10, 11, 12, 13, 14, 15,
114 /* Return Address RA. Mapped to RIP. */
117 /* SSE Registers 0 - 7. */
118 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
119 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
120 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
121 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
123 /* Extended SSE Registers 8 - 15. */
124 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
125 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
126 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
127 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
129 /* Floating Point Registers 0-7. */
130 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
131 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
132 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
133 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
135 /* Control and Status Flags Register. */
138 /* Selector Registers. */
148 /* Segment Base Address Registers. */
154 /* Special Selector Registers. */
158 /* Floating Point Control Registers. */
164 static const int amd64_dwarf_regmap_len =
165 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
167 /* Convert DWARF register number REG to the appropriate register
168 number used by GDB. */
171 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
173 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
174 int ymm0_regnum = tdep->ymm0_regnum;
177 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
178 regnum = amd64_dwarf_regmap[reg];
181 warning (_("Unmapped DWARF Register #%d encountered."), reg);
182 else if (ymm0_regnum >= 0
183 && i386_xmm_regnum_p (gdbarch, regnum))
184 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
189 /* Map architectural register numbers to gdb register numbers. */
191 static const int amd64_arch_regmap[16] =
193 AMD64_RAX_REGNUM, /* %rax */
194 AMD64_RCX_REGNUM, /* %rcx */
195 AMD64_RDX_REGNUM, /* %rdx */
196 AMD64_RBX_REGNUM, /* %rbx */
197 AMD64_RSP_REGNUM, /* %rsp */
198 AMD64_RBP_REGNUM, /* %rbp */
199 AMD64_RSI_REGNUM, /* %rsi */
200 AMD64_RDI_REGNUM, /* %rdi */
201 AMD64_R8_REGNUM, /* %r8 */
202 AMD64_R9_REGNUM, /* %r9 */
203 AMD64_R10_REGNUM, /* %r10 */
204 AMD64_R11_REGNUM, /* %r11 */
205 AMD64_R12_REGNUM, /* %r12 */
206 AMD64_R13_REGNUM, /* %r13 */
207 AMD64_R14_REGNUM, /* %r14 */
208 AMD64_R15_REGNUM /* %r15 */
211 static const int amd64_arch_regmap_len =
212 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
214 /* Convert architectural register number REG to the appropriate register
215 number used by GDB. */
218 amd64_arch_reg_to_regnum (int reg)
220 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
222 return amd64_arch_regmap[reg];
225 /* Register names for byte pseudo-registers. */
227 static const char *amd64_byte_names[] =
229 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
230 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
231 "ah", "bh", "ch", "dh"
234 /* Number of lower byte registers. */
235 #define AMD64_NUM_LOWER_BYTE_REGS 16
237 /* Register names for word pseudo-registers. */
239 static const char *amd64_word_names[] =
241 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
242 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
245 /* Register names for dword pseudo-registers. */
247 static const char *amd64_dword_names[] =
249 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
250 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
254 /* Return the name of register REGNUM. */
257 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
260 if (i386_byte_regnum_p (gdbarch, regnum))
261 return amd64_byte_names[regnum - tdep->al_regnum];
262 else if (i386_ymm_regnum_p (gdbarch, regnum))
263 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
264 else if (i386_word_regnum_p (gdbarch, regnum))
265 return amd64_word_names[regnum - tdep->ax_regnum];
266 else if (i386_dword_regnum_p (gdbarch, regnum))
267 return amd64_dword_names[regnum - tdep->eax_regnum];
269 return i386_pseudo_register_name (gdbarch, regnum);
272 static struct value *
273 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
274 struct regcache *regcache,
277 gdb_byte raw_buf[MAX_REGISTER_SIZE];
278 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
279 enum register_status status;
280 struct value *result_value;
283 result_value = allocate_value (register_type (gdbarch, regnum));
284 VALUE_LVAL (result_value) = lval_register;
285 VALUE_REGNUM (result_value) = regnum;
286 buf = value_contents_raw (result_value);
288 if (i386_byte_regnum_p (gdbarch, regnum))
290 int gpnum = regnum - tdep->al_regnum;
292 /* Extract (always little endian). */
293 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
295 /* Special handling for AH, BH, CH, DH. */
296 status = regcache_raw_read (regcache,
297 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
299 if (status == REG_VALID)
300 memcpy (buf, raw_buf + 1, 1);
302 mark_value_bytes_unavailable (result_value, 0,
303 TYPE_LENGTH (value_type (result_value)));
307 status = regcache_raw_read (regcache, gpnum, raw_buf);
308 if (status == REG_VALID)
309 memcpy (buf, raw_buf, 1);
311 mark_value_bytes_unavailable (result_value, 0,
312 TYPE_LENGTH (value_type (result_value)));
315 else if (i386_dword_regnum_p (gdbarch, regnum))
317 int gpnum = regnum - tdep->eax_regnum;
318 /* Extract (always little endian). */
319 status = regcache_raw_read (regcache, gpnum, raw_buf);
320 if (status == REG_VALID)
321 memcpy (buf, raw_buf, 4);
323 mark_value_bytes_unavailable (result_value, 0,
324 TYPE_LENGTH (value_type (result_value)));
327 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
334 amd64_pseudo_register_write (struct gdbarch *gdbarch,
335 struct regcache *regcache,
336 int regnum, const gdb_byte *buf)
338 gdb_byte raw_buf[MAX_REGISTER_SIZE];
339 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
341 if (i386_byte_regnum_p (gdbarch, regnum))
343 int gpnum = regnum - tdep->al_regnum;
345 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
347 /* Read ... AH, BH, CH, DH. */
348 regcache_raw_read (regcache,
349 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
350 /* ... Modify ... (always little endian). */
351 memcpy (raw_buf + 1, buf, 1);
353 regcache_raw_write (regcache,
354 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
359 regcache_raw_read (regcache, gpnum, raw_buf);
360 /* ... Modify ... (always little endian). */
361 memcpy (raw_buf, buf, 1);
363 regcache_raw_write (regcache, gpnum, raw_buf);
366 else if (i386_dword_regnum_p (gdbarch, regnum))
368 int gpnum = regnum - tdep->eax_regnum;
371 regcache_raw_read (regcache, gpnum, raw_buf);
372 /* ... Modify ... (always little endian). */
373 memcpy (raw_buf, buf, 4);
375 regcache_raw_write (regcache, gpnum, raw_buf);
378 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
383 /* Register classes as defined in the psABI. */
397 /* Return the union class of CLASS1 and CLASS2. See the psABI for
400 static enum amd64_reg_class
401 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
403 /* Rule (a): If both classes are equal, this is the resulting class. */
404 if (class1 == class2)
407 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
408 is the other class. */
409 if (class1 == AMD64_NO_CLASS)
411 if (class2 == AMD64_NO_CLASS)
414 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
415 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
418 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
419 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
420 return AMD64_INTEGER;
422 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
423 MEMORY is used as class. */
424 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
425 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
426 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
429 /* Rule (f): Otherwise class SSE is used. */
433 static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
435 /* Return non-zero if TYPE is a non-POD structure or union type. */
438 amd64_non_pod_p (struct type *type)
440 /* ??? A class with a base class certainly isn't POD, but does this
441 catch all non-POD structure types? */
442 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
448 /* Classify TYPE according to the rules for aggregate (structures and
449 arrays) and union types, and store the result in CLASS. */
452 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
454 /* 1. If the size of an object is larger than two eightbytes, or in
455 C++, is a non-POD structure or union type, or contains
456 unaligned fields, it has class memory. */
457 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
459 class[0] = class[1] = AMD64_MEMORY;
463 /* 2. Both eightbytes get initialized to class NO_CLASS. */
464 class[0] = class[1] = AMD64_NO_CLASS;
466 /* 3. Each field of an object is classified recursively so that
467 always two fields are considered. The resulting class is
468 calculated according to the classes of the fields in the
471 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
473 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
475 /* All fields in an array have the same type. */
476 amd64_classify (subtype, class);
477 if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS)
484 /* Structure or union. */
485 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
486 || TYPE_CODE (type) == TYPE_CODE_UNION);
488 for (i = 0; i < TYPE_NFIELDS (type); i++)
490 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
491 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
492 enum amd64_reg_class subclass[2];
493 int bitsize = TYPE_FIELD_BITSIZE (type, i);
497 bitsize = TYPE_LENGTH (subtype) * 8;
498 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
500 /* Ignore static fields. */
501 if (field_is_static (&TYPE_FIELD (type, i)))
504 gdb_assert (pos == 0 || pos == 1);
506 amd64_classify (subtype, subclass);
507 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
508 if (bitsize <= 64 && pos == 0 && endpos == 1)
509 /* This is a bit of an odd case: We have a field that would
510 normally fit in one of the two eightbytes, except that
511 it is placed in a way that this field straddles them.
512 This has been seen with a structure containing an array.
514 The ABI is a bit unclear in this case, but we assume that
515 this field's class (stored in subclass[0]) must also be merged
516 into class[1]. In other words, our field has a piece stored
517 in the second eight-byte, and thus its class applies to
518 the second eight-byte as well.
520 In the case where the field length exceeds 8 bytes,
521 it should not be necessary to merge the field class
522 into class[1]. As LEN > 8, subclass[1] is necessarily
523 different from AMD64_NO_CLASS. If subclass[1] is equal
524 to subclass[0], then the normal class[1]/subclass[1]
525 merging will take care of everything. For subclass[1]
526 to be different from subclass[0], I can only see the case
527 where we have a SSE/SSEUP or X87/X87UP pair, which both
528 use up all 16 bytes of the aggregate, and are already
529 handled just fine (because each portion sits on its own
531 class[1] = amd64_merge_classes (class[1], subclass[0]);
533 class[1] = amd64_merge_classes (class[1], subclass[1]);
537 /* 4. Then a post merger cleanup is done: */
539 /* Rule (a): If one of the classes is MEMORY, the whole argument is
541 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
542 class[0] = class[1] = AMD64_MEMORY;
544 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
546 if (class[0] == AMD64_SSEUP)
547 class[0] = AMD64_SSE;
548 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
549 class[1] = AMD64_SSE;
552 /* Classify TYPE, and store the result in CLASS. */
555 amd64_classify (struct type *type, enum amd64_reg_class class[2])
557 enum type_code code = TYPE_CODE (type);
558 int len = TYPE_LENGTH (type);
560 class[0] = class[1] = AMD64_NO_CLASS;
562 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
563 long, long long, and pointers are in the INTEGER class. Similarly,
564 range types, used by languages such as Ada, are also in the INTEGER
566 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
567 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
568 || code == TYPE_CODE_CHAR
569 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
570 && (len == 1 || len == 2 || len == 4 || len == 8))
571 class[0] = AMD64_INTEGER;
573 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
575 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
576 && (len == 4 || len == 8))
578 class[0] = AMD64_SSE;
580 /* Arguments of types __float128, _Decimal128 and __m128 are split into
581 two halves. The least significant ones belong to class SSE, the most
582 significant one to class SSEUP. */
583 else if (code == TYPE_CODE_DECFLOAT && len == 16)
584 /* FIXME: __float128, __m128. */
585 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
587 /* The 64-bit mantissa of arguments of type long double belongs to
588 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
590 else if (code == TYPE_CODE_FLT && len == 16)
591 /* Class X87 and X87UP. */
592 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
594 /* Arguments of complex T where T is one of the types float or
595 double get treated as if they are implemented as:
601 else if (code == TYPE_CODE_COMPLEX && len == 8)
602 class[0] = AMD64_SSE;
603 else if (code == TYPE_CODE_COMPLEX && len == 16)
604 class[0] = class[1] = AMD64_SSE;
606 /* A variable of type complex long double is classified as type
608 else if (code == TYPE_CODE_COMPLEX && len == 32)
609 class[0] = AMD64_COMPLEX_X87;
612 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
613 || code == TYPE_CODE_UNION)
614 amd64_classify_aggregate (type, class);
617 static enum return_value_convention
618 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
619 struct type *type, struct regcache *regcache,
620 gdb_byte *readbuf, const gdb_byte *writebuf)
622 enum amd64_reg_class class[2];
623 int len = TYPE_LENGTH (type);
624 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
625 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
630 gdb_assert (!(readbuf && writebuf));
632 /* 1. Classify the return type with the classification algorithm. */
633 amd64_classify (type, class);
635 /* 2. If the type has class MEMORY, then the caller provides space
636 for the return value and passes the address of this storage in
637 %rdi as if it were the first argument to the function. In effect,
638 this address becomes a hidden first argument.
640 On return %rax will contain the address that has been passed in
641 by the caller in %rdi. */
642 if (class[0] == AMD64_MEMORY)
644 /* As indicated by the comment above, the ABI guarantees that we
645 can always find the return value just after the function has
652 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
653 read_memory (addr, readbuf, TYPE_LENGTH (type));
656 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
659 /* 8. If the class is COMPLEX_X87, the real part of the value is
660 returned in %st0 and the imaginary part in %st1. */
661 if (class[0] == AMD64_COMPLEX_X87)
665 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
666 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
671 i387_return_value (gdbarch, regcache);
672 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
673 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
675 /* Fix up the tag word such that both %st(0) and %st(1) are
677 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
680 return RETURN_VALUE_REGISTER_CONVENTION;
683 gdb_assert (class[1] != AMD64_MEMORY);
684 gdb_assert (len <= 16);
686 for (i = 0; len > 0; i++, len -= 8)
694 /* 3. If the class is INTEGER, the next available register
695 of the sequence %rax, %rdx is used. */
696 regnum = integer_regnum[integer_reg++];
700 /* 4. If the class is SSE, the next available SSE register
701 of the sequence %xmm0, %xmm1 is used. */
702 regnum = sse_regnum[sse_reg++];
706 /* 5. If the class is SSEUP, the eightbyte is passed in the
707 upper half of the last used SSE register. */
708 gdb_assert (sse_reg > 0);
709 regnum = sse_regnum[sse_reg - 1];
714 /* 6. If the class is X87, the value is returned on the X87
715 stack in %st0 as 80-bit x87 number. */
716 regnum = AMD64_ST0_REGNUM;
718 i387_return_value (gdbarch, regcache);
722 /* 7. If the class is X87UP, the value is returned together
723 with the previous X87 value in %st0. */
724 gdb_assert (i > 0 && class[0] == AMD64_X87);
725 regnum = AMD64_ST0_REGNUM;
734 gdb_assert (!"Unexpected register class.");
737 gdb_assert (regnum != -1);
740 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
743 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
747 return RETURN_VALUE_REGISTER_CONVENTION;
752 amd64_push_arguments (struct regcache *regcache, int nargs,
753 struct value **args, CORE_ADDR sp, int struct_return)
755 static int integer_regnum[] =
757 AMD64_RDI_REGNUM, /* %rdi */
758 AMD64_RSI_REGNUM, /* %rsi */
759 AMD64_RDX_REGNUM, /* %rdx */
760 AMD64_RCX_REGNUM, /* %rcx */
764 static int sse_regnum[] =
766 /* %xmm0 ... %xmm7 */
767 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
768 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
769 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
770 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
772 struct value **stack_args = alloca (nargs * sizeof (struct value *));
773 int num_stack_args = 0;
774 int num_elements = 0;
780 /* Reserve a register for the "hidden" argument. */
784 for (i = 0; i < nargs; i++)
786 struct type *type = value_type (args[i]);
787 int len = TYPE_LENGTH (type);
788 enum amd64_reg_class class[2];
789 int needed_integer_regs = 0;
790 int needed_sse_regs = 0;
793 /* Classify argument. */
794 amd64_classify (type, class);
796 /* Calculate the number of integer and SSE registers needed for
798 for (j = 0; j < 2; j++)
800 if (class[j] == AMD64_INTEGER)
801 needed_integer_regs++;
802 else if (class[j] == AMD64_SSE)
806 /* Check whether enough registers are available, and if the
807 argument should be passed in registers at all. */
808 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
809 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
810 || (needed_integer_regs == 0 && needed_sse_regs == 0))
812 /* The argument will be passed on the stack. */
813 num_elements += ((len + 7) / 8);
814 stack_args[num_stack_args++] = args[i];
818 /* The argument will be passed in registers. */
819 const gdb_byte *valbuf = value_contents (args[i]);
822 gdb_assert (len <= 16);
824 for (j = 0; len > 0; j++, len -= 8)
832 regnum = integer_regnum[integer_reg++];
836 regnum = sse_regnum[sse_reg++];
840 gdb_assert (sse_reg > 0);
841 regnum = sse_regnum[sse_reg - 1];
846 gdb_assert (!"Unexpected register class.");
849 gdb_assert (regnum != -1);
850 memset (buf, 0, sizeof buf);
851 memcpy (buf, valbuf + j * 8, min (len, 8));
852 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
857 /* Allocate space for the arguments on the stack. */
858 sp -= num_elements * 8;
860 /* The psABI says that "The end of the input argument area shall be
861 aligned on a 16 byte boundary." */
864 /* Write out the arguments to the stack. */
865 for (i = 0; i < num_stack_args; i++)
867 struct type *type = value_type (stack_args[i]);
868 const gdb_byte *valbuf = value_contents (stack_args[i]);
869 int len = TYPE_LENGTH (type);
871 write_memory (sp + element * 8, valbuf, len);
872 element += ((len + 7) / 8);
875 /* The psABI says that "For calls that may call functions that use
876 varargs or stdargs (prototype-less calls or calls to functions
877 containing ellipsis (...) in the declaration) %al is used as
878 hidden argument to specify the number of SSE registers used. */
879 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
884 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
885 struct regcache *regcache, CORE_ADDR bp_addr,
886 int nargs, struct value **args, CORE_ADDR sp,
887 int struct_return, CORE_ADDR struct_addr)
889 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
892 /* Pass arguments. */
893 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
895 /* Pass "hidden" argument". */
898 store_unsigned_integer (buf, 8, byte_order, struct_addr);
899 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
902 /* Store return address. */
904 store_unsigned_integer (buf, 8, byte_order, bp_addr);
905 write_memory (sp, buf, 8);
907 /* Finally, update the stack pointer... */
908 store_unsigned_integer (buf, 8, byte_order, sp);
909 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
911 /* ...and fake a frame pointer. */
912 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
917 /* Displaced instruction handling. */
919 /* A partially decoded instruction.
920 This contains enough details for displaced stepping purposes. */
924 /* The number of opcode bytes. */
926 /* The offset of the rex prefix or -1 if not present. */
928 /* The offset to the first opcode byte. */
930 /* The offset to the modrm byte or -1 if not present. */
933 /* The raw instruction. */
937 struct displaced_step_closure
939 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
944 /* Details of the instruction. */
945 struct amd64_insn insn_details;
947 /* Amount of space allocated to insn_buf. */
950 /* The possibly modified insn.
951 This is a variable-length field. */
952 gdb_byte insn_buf[1];
955 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
956 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
957 at which point delete these in favor of libopcodes' versions). */
959 static const unsigned char onebyte_has_modrm[256] = {
960 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
961 /* ------------------------------- */
962 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
963 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
964 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
965 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
966 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
967 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
968 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
969 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
970 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
971 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
972 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
973 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
974 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
975 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
976 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
977 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
978 /* ------------------------------- */
979 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
982 static const unsigned char twobyte_has_modrm[256] = {
983 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
984 /* ------------------------------- */
985 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
986 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
987 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
988 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
989 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
990 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
991 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
992 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
993 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
994 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
995 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
996 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
997 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
998 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
999 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1000 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1001 /* ------------------------------- */
1002 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1005 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1008 rex_prefix_p (gdb_byte pfx)
1010 return REX_PREFIX_P (pfx);
1013 /* Skip the legacy instruction prefixes in INSN.
1014 We assume INSN is properly sentineled so we don't have to worry
1015 about falling off the end of the buffer. */
1018 amd64_skip_prefixes (gdb_byte *insn)
1024 case DATA_PREFIX_OPCODE:
1025 case ADDR_PREFIX_OPCODE:
1026 case CS_PREFIX_OPCODE:
1027 case DS_PREFIX_OPCODE:
1028 case ES_PREFIX_OPCODE:
1029 case FS_PREFIX_OPCODE:
1030 case GS_PREFIX_OPCODE:
1031 case SS_PREFIX_OPCODE:
1032 case LOCK_PREFIX_OPCODE:
1033 case REPE_PREFIX_OPCODE:
1034 case REPNE_PREFIX_OPCODE:
1046 /* Return an integer register (other than RSP) that is unused as an input
1048 In order to not require adding a rex prefix if the insn doesn't already
1049 have one, the result is restricted to RAX ... RDI, sans RSP.
1050 The register numbering of the result follows architecture ordering,
1054 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1056 /* 1 bit for each reg */
1057 int used_regs_mask = 0;
1059 /* There can be at most 3 int regs used as inputs in an insn, and we have
1060 7 to choose from (RAX ... RDI, sans RSP).
1061 This allows us to take a conservative approach and keep things simple.
1062 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1063 that implicitly specify RAX. */
1066 used_regs_mask |= 1 << EAX_REG_NUM;
1067 /* Similarily avoid RDX, implicit operand in divides. */
1068 used_regs_mask |= 1 << EDX_REG_NUM;
1070 used_regs_mask |= 1 << ESP_REG_NUM;
1072 /* If the opcode is one byte long and there's no ModRM byte,
1073 assume the opcode specifies a register. */
1074 if (details->opcode_len == 1 && details->modrm_offset == -1)
1075 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1077 /* Mark used regs in the modrm/sib bytes. */
1078 if (details->modrm_offset != -1)
1080 int modrm = details->raw_insn[details->modrm_offset];
1081 int mod = MODRM_MOD_FIELD (modrm);
1082 int reg = MODRM_REG_FIELD (modrm);
1083 int rm = MODRM_RM_FIELD (modrm);
1084 int have_sib = mod != 3 && rm == 4;
1086 /* Assume the reg field of the modrm byte specifies a register. */
1087 used_regs_mask |= 1 << reg;
1091 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1092 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1093 used_regs_mask |= 1 << base;
1094 used_regs_mask |= 1 << idx;
1098 used_regs_mask |= 1 << rm;
1102 gdb_assert (used_regs_mask < 256);
1103 gdb_assert (used_regs_mask != 255);
1105 /* Finally, find a free reg. */
1109 for (i = 0; i < 8; ++i)
1111 if (! (used_regs_mask & (1 << i)))
1115 /* We shouldn't get here. */
1116 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1120 /* Extract the details of INSN that we need. */
1123 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1125 gdb_byte *start = insn;
1128 details->raw_insn = insn;
1130 details->opcode_len = -1;
1131 details->rex_offset = -1;
1132 details->opcode_offset = -1;
1133 details->modrm_offset = -1;
1135 /* Skip legacy instruction prefixes. */
1136 insn = amd64_skip_prefixes (insn);
1138 /* Skip REX instruction prefix. */
1139 if (rex_prefix_p (*insn))
1141 details->rex_offset = insn - start;
1145 details->opcode_offset = insn - start;
1147 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1149 /* Two or three-byte opcode. */
1151 need_modrm = twobyte_has_modrm[*insn];
1153 /* Check for three-byte opcode. */
1163 details->opcode_len = 3;
1166 details->opcode_len = 2;
1172 /* One-byte opcode. */
1173 need_modrm = onebyte_has_modrm[*insn];
1174 details->opcode_len = 1;
1180 details->modrm_offset = insn - start;
1184 /* Update %rip-relative addressing in INSN.
1186 %rip-relative addressing only uses a 32-bit displacement.
1187 32 bits is not enough to be guaranteed to cover the distance between where
1188 the real instruction is and where its copy is.
1189 Convert the insn to use base+disp addressing.
1190 We set base = pc + insn_length so we can leave disp unchanged. */
1193 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1194 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1196 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1197 const struct amd64_insn *insn_details = &dsc->insn_details;
1198 int modrm_offset = insn_details->modrm_offset;
1199 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1203 int arch_tmp_regno, tmp_regno;
1204 ULONGEST orig_value;
1206 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1209 /* Compute the rip-relative address. */
1210 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1211 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1212 dsc->max_len, from);
1213 rip_base = from + insn_length;
1215 /* We need a register to hold the address.
1216 Pick one not used in the insn.
1217 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1218 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1219 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1221 /* REX.B should be unset as we were using rip-relative addressing,
1222 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1223 if (insn_details->rex_offset != -1)
1224 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1226 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1227 dsc->tmp_regno = tmp_regno;
1228 dsc->tmp_save = orig_value;
1231 /* Convert the ModRM field to be base+disp. */
1232 dsc->insn_buf[modrm_offset] &= ~0xc7;
1233 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1235 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1237 if (debug_displaced)
1238 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1239 "displaced: using temp reg %d, old value %s, new value %s\n",
1240 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1241 paddress (gdbarch, rip_base));
1245 fixup_displaced_copy (struct gdbarch *gdbarch,
1246 struct displaced_step_closure *dsc,
1247 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1249 const struct amd64_insn *details = &dsc->insn_details;
1251 if (details->modrm_offset != -1)
1253 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1255 if ((modrm & 0xc7) == 0x05)
1257 /* The insn uses rip-relative addressing.
1259 fixup_riprel (gdbarch, dsc, from, to, regs);
1264 struct displaced_step_closure *
1265 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1266 CORE_ADDR from, CORE_ADDR to,
1267 struct regcache *regs)
1269 int len = gdbarch_max_insn_length (gdbarch);
1270 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1271 continually watch for running off the end of the buffer. */
1272 int fixup_sentinel_space = len;
1273 struct displaced_step_closure *dsc =
1274 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1275 gdb_byte *buf = &dsc->insn_buf[0];
1276 struct amd64_insn *details = &dsc->insn_details;
1279 dsc->max_len = len + fixup_sentinel_space;
1281 read_memory (from, buf, len);
1283 /* Set up the sentinel space so we don't have to worry about running
1284 off the end of the buffer. An excessive number of leading prefixes
1285 could otherwise cause this. */
1286 memset (buf + len, 0, fixup_sentinel_space);
1288 amd64_get_insn_details (buf, details);
1290 /* GDB may get control back after the insn after the syscall.
1291 Presumably this is a kernel bug.
1292 If this is a syscall, make sure there's a nop afterwards. */
1296 if (amd64_syscall_p (details, &syscall_length))
1297 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1300 /* Modify the insn to cope with the address where it will be executed from.
1301 In particular, handle any rip-relative addressing. */
1302 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1304 write_memory (to, buf, len);
1306 if (debug_displaced)
1308 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1309 paddress (gdbarch, from), paddress (gdbarch, to));
1310 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1317 amd64_absolute_jmp_p (const struct amd64_insn *details)
1319 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1321 if (insn[0] == 0xff)
1323 /* jump near, absolute indirect (/4) */
1324 if ((insn[1] & 0x38) == 0x20)
1327 /* jump far, absolute indirect (/5) */
1328 if ((insn[1] & 0x38) == 0x28)
1336 amd64_absolute_call_p (const struct amd64_insn *details)
1338 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1340 if (insn[0] == 0xff)
1342 /* Call near, absolute indirect (/2) */
1343 if ((insn[1] & 0x38) == 0x10)
1346 /* Call far, absolute indirect (/3) */
1347 if ((insn[1] & 0x38) == 0x18)
1355 amd64_ret_p (const struct amd64_insn *details)
1357 /* NOTE: gcc can emit "repz ; ret". */
1358 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1362 case 0xc2: /* ret near, pop N bytes */
1363 case 0xc3: /* ret near */
1364 case 0xca: /* ret far, pop N bytes */
1365 case 0xcb: /* ret far */
1366 case 0xcf: /* iret */
1375 amd64_call_p (const struct amd64_insn *details)
1377 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1379 if (amd64_absolute_call_p (details))
1382 /* call near, relative */
1383 if (insn[0] == 0xe8)
1389 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1390 length in bytes. Otherwise, return zero. */
1393 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1395 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1397 if (insn[0] == 0x0f && insn[1] == 0x05)
1406 /* Fix up the state of registers and memory after having single-stepped
1407 a displaced instruction. */
1410 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1411 struct displaced_step_closure *dsc,
1412 CORE_ADDR from, CORE_ADDR to,
1413 struct regcache *regs)
1415 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1416 /* The offset we applied to the instruction's address. */
1417 ULONGEST insn_offset = to - from;
1418 gdb_byte *insn = dsc->insn_buf;
1419 const struct amd64_insn *insn_details = &dsc->insn_details;
1421 if (debug_displaced)
1422 fprintf_unfiltered (gdb_stdlog,
1423 "displaced: fixup (%s, %s), "
1424 "insn = 0x%02x 0x%02x ...\n",
1425 paddress (gdbarch, from), paddress (gdbarch, to),
1428 /* If we used a tmp reg, restore it. */
1432 if (debug_displaced)
1433 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1434 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1435 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1438 /* The list of issues to contend with here is taken from
1439 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1440 Yay for Free Software! */
1442 /* Relocate the %rip back to the program's instruction stream,
1445 /* Except in the case of absolute or indirect jump or call
1446 instructions, or a return instruction, the new rip is relative to
1447 the displaced instruction; make it relative to the original insn.
1448 Well, signal handler returns don't need relocation either, but we use the
1449 value of %rip to recognize those; see below. */
1450 if (! amd64_absolute_jmp_p (insn_details)
1451 && ! amd64_absolute_call_p (insn_details)
1452 && ! amd64_ret_p (insn_details))
1457 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1459 /* A signal trampoline system call changes the %rip, resuming
1460 execution of the main program after the signal handler has
1461 returned. That makes them like 'return' instructions; we
1462 shouldn't relocate %rip.
1464 But most system calls don't, and we do need to relocate %rip.
1466 Our heuristic for distinguishing these cases: if stepping
1467 over the system call instruction left control directly after
1468 the instruction, the we relocate --- control almost certainly
1469 doesn't belong in the displaced copy. Otherwise, we assume
1470 the instruction has put control where it belongs, and leave
1471 it unrelocated. Goodness help us if there are PC-relative
1473 if (amd64_syscall_p (insn_details, &insn_len)
1474 && orig_rip != to + insn_len
1475 /* GDB can get control back after the insn after the syscall.
1476 Presumably this is a kernel bug.
1477 Fixup ensures its a nop, we add one to the length for it. */
1478 && orig_rip != to + insn_len + 1)
1480 if (debug_displaced)
1481 fprintf_unfiltered (gdb_stdlog,
1482 "displaced: syscall changed %%rip; "
1483 "not relocating\n");
1487 ULONGEST rip = orig_rip - insn_offset;
1489 /* If we just stepped over a breakpoint insn, we don't backup
1490 the pc on purpose; this is to match behaviour without
1493 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1495 if (debug_displaced)
1496 fprintf_unfiltered (gdb_stdlog,
1498 "relocated %%rip from %s to %s\n",
1499 paddress (gdbarch, orig_rip),
1500 paddress (gdbarch, rip));
1504 /* If the instruction was PUSHFL, then the TF bit will be set in the
1505 pushed value, and should be cleared. We'll leave this for later,
1506 since GDB already messes up the TF flag when stepping over a
1509 /* If the instruction was a call, the return address now atop the
1510 stack is the address following the copied instruction. We need
1511 to make it the address following the original instruction. */
1512 if (amd64_call_p (insn_details))
1516 const ULONGEST retaddr_len = 8;
1518 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1519 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1520 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
1521 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1523 if (debug_displaced)
1524 fprintf_unfiltered (gdb_stdlog,
1525 "displaced: relocated return addr at %s "
1527 paddress (gdbarch, rsp),
1528 paddress (gdbarch, retaddr));
1532 /* If the instruction INSN uses RIP-relative addressing, return the
1533 offset into the raw INSN where the displacement to be adjusted is
1534 found. Returns 0 if the instruction doesn't use RIP-relative
1538 rip_relative_offset (struct amd64_insn *insn)
1540 if (insn->modrm_offset != -1)
1542 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1544 if ((modrm & 0xc7) == 0x05)
1546 /* The displacement is found right after the ModRM byte. */
1547 return insn->modrm_offset + 1;
1555 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1557 target_write_memory (*to, buf, len);
1562 amd64_relocate_instruction (struct gdbarch *gdbarch,
1563 CORE_ADDR *to, CORE_ADDR oldloc)
1565 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1566 int len = gdbarch_max_insn_length (gdbarch);
1567 /* Extra space for sentinels. */
1568 int fixup_sentinel_space = len;
1569 gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1570 struct amd64_insn insn_details;
1572 LONGEST rel32, newrel;
1576 read_memory (oldloc, buf, len);
1578 /* Set up the sentinel space so we don't have to worry about running
1579 off the end of the buffer. An excessive number of leading prefixes
1580 could otherwise cause this. */
1581 memset (buf + len, 0, fixup_sentinel_space);
1584 amd64_get_insn_details (insn, &insn_details);
1586 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1588 /* Skip legacy instruction prefixes. */
1589 insn = amd64_skip_prefixes (insn);
1591 /* Adjust calls with 32-bit relative addresses as push/jump, with
1592 the address pushed being the location where the original call in
1593 the user program would return to. */
1594 if (insn[0] == 0xe8)
1596 gdb_byte push_buf[16];
1597 unsigned int ret_addr;
1599 /* Where "ret" in the original code will return to. */
1600 ret_addr = oldloc + insn_length;
1601 push_buf[0] = 0x68; /* pushq $... */
1602 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1603 /* Push the push. */
1604 append_insns (to, 5, push_buf);
1606 /* Convert the relative call to a relative jump. */
1609 /* Adjust the destination offset. */
1610 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1611 newrel = (oldloc - *to) + rel32;
1612 store_signed_integer (insn + 1, 4, byte_order, newrel);
1614 if (debug_displaced)
1615 fprintf_unfiltered (gdb_stdlog,
1616 "Adjusted insn rel32=%s at %s to"
1617 " rel32=%s at %s\n",
1618 hex_string (rel32), paddress (gdbarch, oldloc),
1619 hex_string (newrel), paddress (gdbarch, *to));
1621 /* Write the adjusted jump into its displaced location. */
1622 append_insns (to, 5, insn);
1626 offset = rip_relative_offset (&insn_details);
1629 /* Adjust jumps with 32-bit relative addresses. Calls are
1630 already handled above. */
1631 if (insn[0] == 0xe9)
1633 /* Adjust conditional jumps. */
1634 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1640 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1641 newrel = (oldloc - *to) + rel32;
1642 store_signed_integer (insn + offset, 4, byte_order, newrel);
1643 if (debug_displaced)
1644 fprintf_unfiltered (gdb_stdlog,
1645 "Adjusted insn rel32=%s at %s to"
1646 " rel32=%s at %s\n",
1647 hex_string (rel32), paddress (gdbarch, oldloc),
1648 hex_string (newrel), paddress (gdbarch, *to));
1651 /* Write the adjusted instruction into its displaced location. */
1652 append_insns (to, insn_length, buf);
1656 /* The maximum number of saved registers. This should include %rip. */
1657 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1659 struct amd64_frame_cache
1664 CORE_ADDR sp_offset;
1667 /* Saved registers. */
1668 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1672 /* Do we have a frame? */
1676 /* Initialize a frame cache. */
1679 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1686 cache->sp_offset = -8;
1689 /* Saved registers. We initialize these to -1 since zero is a valid
1690 offset (that's where %rbp is supposed to be stored).
1691 The values start out as being offsets, and are later converted to
1692 addresses (at which point -1 is interpreted as an address, still meaning
1694 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1695 cache->saved_regs[i] = -1;
1696 cache->saved_sp = 0;
1697 cache->saved_sp_reg = -1;
1699 /* Frameless until proven otherwise. */
1700 cache->frameless_p = 1;
1703 /* Allocate and initialize a frame cache. */
1705 static struct amd64_frame_cache *
1706 amd64_alloc_frame_cache (void)
1708 struct amd64_frame_cache *cache;
1710 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1711 amd64_init_frame_cache (cache);
1715 /* GCC 4.4 and later, can put code in the prologue to realign the
1716 stack pointer. Check whether PC points to such code, and update
1717 CACHE accordingly. Return the first instruction after the code
1718 sequence or CURRENT_PC, whichever is smaller. If we don't
1719 recognize the code, return PC. */
1722 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1723 struct amd64_frame_cache *cache)
1725 /* There are 2 code sequences to re-align stack before the frame
1728 1. Use a caller-saved saved register:
1734 2. Use a callee-saved saved register:
1741 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1743 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1744 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1749 int offset, offset_and;
1751 if (target_read_memory (pc, buf, sizeof buf))
1754 /* Check caller-saved saved register. The first instruction has
1755 to be "leaq 8(%rsp), %reg". */
1756 if ((buf[0] & 0xfb) == 0x48
1761 /* MOD must be binary 10 and R/M must be binary 100. */
1762 if ((buf[2] & 0xc7) != 0x44)
1765 /* REG has register number. */
1766 reg = (buf[2] >> 3) & 7;
1768 /* Check the REX.R bit. */
1776 /* Check callee-saved saved register. The first instruction
1777 has to be "pushq %reg". */
1779 if ((buf[0] & 0xf8) == 0x50)
1781 else if ((buf[0] & 0xf6) == 0x40
1782 && (buf[1] & 0xf8) == 0x50)
1784 /* Check the REX.B bit. */
1785 if ((buf[0] & 1) != 0)
1794 reg += buf[offset] & 0x7;
1798 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1799 if ((buf[offset] & 0xfb) != 0x48
1800 || buf[offset + 1] != 0x8d
1801 || buf[offset + 3] != 0x24
1802 || buf[offset + 4] != 0x10)
1805 /* MOD must be binary 10 and R/M must be binary 100. */
1806 if ((buf[offset + 2] & 0xc7) != 0x44)
1809 /* REG has register number. */
1810 r = (buf[offset + 2] >> 3) & 7;
1812 /* Check the REX.R bit. */
1813 if (buf[offset] == 0x4c)
1816 /* Registers in pushq and leaq have to be the same. */
1823 /* Rigister can't be %rsp nor %rbp. */
1824 if (reg == 4 || reg == 5)
1827 /* The next instruction has to be "andq $-XXX, %rsp". */
1828 if (buf[offset] != 0x48
1829 || buf[offset + 2] != 0xe4
1830 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1833 offset_and = offset;
1834 offset += buf[offset + 1] == 0x81 ? 7 : 4;
1836 /* The next instruction has to be "pushq -8(%reg)". */
1838 if (buf[offset] == 0xff)
1840 else if ((buf[offset] & 0xf6) == 0x40
1841 && buf[offset + 1] == 0xff)
1843 /* Check the REX.B bit. */
1844 if ((buf[offset] & 0x1) != 0)
1851 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1853 if (buf[offset + 1] != 0xf8
1854 || (buf[offset] & 0xf8) != 0x70)
1857 /* R/M has register. */
1858 r += buf[offset] & 7;
1860 /* Registers in leaq and pushq have to be the same. */
1864 if (current_pc > pc + offset_and)
1865 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
1867 return min (pc + offset + 2, current_pc);
1870 /* Similar to amd64_analyze_stack_align for x32. */
1873 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1874 struct amd64_frame_cache *cache)
1876 /* There are 2 code sequences to re-align stack before the frame
1879 1. Use a caller-saved saved register:
1887 [addr32] leal 8(%rsp), %reg
1889 [addr32] pushq -8(%reg)
1891 2. Use a callee-saved saved register:
1901 [addr32] leal 16(%rsp), %reg
1903 [addr32] pushq -8(%reg)
1905 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1907 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1908 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1910 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1912 0x83 0xe4 0xf0 andl $-16, %esp
1913 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1918 int offset, offset_and;
1920 if (target_read_memory (pc, buf, sizeof buf))
1923 /* Skip optional addr32 prefix. */
1924 offset = buf[0] == 0x67 ? 1 : 0;
1926 /* Check caller-saved saved register. The first instruction has
1927 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
1928 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
1929 && buf[offset + 1] == 0x8d
1930 && buf[offset + 3] == 0x24
1931 && buf[offset + 4] == 0x8)
1933 /* MOD must be binary 10 and R/M must be binary 100. */
1934 if ((buf[offset + 2] & 0xc7) != 0x44)
1937 /* REG has register number. */
1938 reg = (buf[offset + 2] >> 3) & 7;
1940 /* Check the REX.R bit. */
1941 if ((buf[offset] & 0x4) != 0)
1948 /* Check callee-saved saved register. The first instruction
1949 has to be "pushq %reg". */
1951 if ((buf[offset] & 0xf6) == 0x40
1952 && (buf[offset + 1] & 0xf8) == 0x50)
1954 /* Check the REX.B bit. */
1955 if ((buf[offset] & 1) != 0)
1960 else if ((buf[offset] & 0xf8) != 0x50)
1964 reg += buf[offset] & 0x7;
1968 /* Skip optional addr32 prefix. */
1969 if (buf[offset] == 0x67)
1972 /* The next instruction has to be "leaq 16(%rsp), %reg" or
1973 "leal 16(%rsp), %reg". */
1974 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
1975 || buf[offset + 1] != 0x8d
1976 || buf[offset + 3] != 0x24
1977 || buf[offset + 4] != 0x10)
1980 /* MOD must be binary 10 and R/M must be binary 100. */
1981 if ((buf[offset + 2] & 0xc7) != 0x44)
1984 /* REG has register number. */
1985 r = (buf[offset + 2] >> 3) & 7;
1987 /* Check the REX.R bit. */
1988 if ((buf[offset] & 0x4) != 0)
1991 /* Registers in pushq and leaq have to be the same. */
1998 /* Rigister can't be %rsp nor %rbp. */
1999 if (reg == 4 || reg == 5)
2002 /* The next instruction may be "andq $-XXX, %rsp" or
2003 "andl $-XXX, %esp". */
2004 if (buf[offset] != 0x48)
2007 if (buf[offset + 2] != 0xe4
2008 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2011 offset_and = offset;
2012 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2014 /* Skip optional addr32 prefix. */
2015 if (buf[offset] == 0x67)
2018 /* The next instruction has to be "pushq -8(%reg)". */
2020 if (buf[offset] == 0xff)
2022 else if ((buf[offset] & 0xf6) == 0x40
2023 && buf[offset + 1] == 0xff)
2025 /* Check the REX.B bit. */
2026 if ((buf[offset] & 0x1) != 0)
2033 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2035 if (buf[offset + 1] != 0xf8
2036 || (buf[offset] & 0xf8) != 0x70)
2039 /* R/M has register. */
2040 r += buf[offset] & 7;
2042 /* Registers in leaq and pushq have to be the same. */
2046 if (current_pc > pc + offset_and)
2047 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2049 return min (pc + offset + 2, current_pc);
2052 /* Do a limited analysis of the prologue at PC and update CACHE
2053 accordingly. Bail out early if CURRENT_PC is reached. Return the
2054 address where the analysis stopped.
2056 We will handle only functions beginning with:
2059 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2061 or (for the X32 ABI):
2064 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2066 Any function that doesn't start with one of these sequences will be
2067 assumed to have no prologue and thus no valid frame pointer in
2071 amd64_analyze_prologue (struct gdbarch *gdbarch,
2072 CORE_ADDR pc, CORE_ADDR current_pc,
2073 struct amd64_frame_cache *cache)
2075 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2076 /* There are two variations of movq %rsp, %rbp. */
2077 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2078 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2079 /* Ditto for movl %esp, %ebp. */
2080 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2081 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2086 if (current_pc <= pc)
2089 if (gdbarch_ptr_bit (gdbarch) == 32)
2090 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2092 pc = amd64_analyze_stack_align (pc, current_pc, cache);
2094 op = read_memory_unsigned_integer (pc, 1, byte_order);
2096 if (op == 0x55) /* pushq %rbp */
2098 /* Take into account that we've executed the `pushq %rbp' that
2099 starts this instruction sequence. */
2100 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2101 cache->sp_offset += 8;
2103 /* If that's all, return now. */
2104 if (current_pc <= pc + 1)
2107 read_memory (pc + 1, buf, 3);
2109 /* Check for `movq %rsp, %rbp'. */
2110 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2111 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2113 /* OK, we actually have a frame. */
2114 cache->frameless_p = 0;
2118 /* For X32, also check for `movq %esp, %ebp'. */
2119 if (gdbarch_ptr_bit (gdbarch) == 32)
2121 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2122 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2124 /* OK, we actually have a frame. */
2125 cache->frameless_p = 0;
2136 /* Work around false termination of prologue - GCC PR debug/48827.
2138 START_PC is the first instruction of a function, PC is its minimal already
2139 determined advanced address. Function returns PC if it has nothing to do.
2143 <-- here is 0 lines advance - the false prologue end marker.
2144 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2145 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2146 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2147 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2148 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2149 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2150 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2151 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2155 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2157 struct symtab_and_line start_pc_sal, next_sal;
2158 gdb_byte buf[4 + 8 * 7];
2164 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2165 if (start_pc_sal.symtab == NULL
2166 || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6
2167 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2170 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2171 if (next_sal.line != start_pc_sal.line)
2174 /* START_PC can be from overlayed memory, ignored here. */
2175 if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2179 if (buf[0] != 0x84 || buf[1] != 0xc0)
2186 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2188 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2189 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2190 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2194 if ((buf[offset + 2] & 0xc0) == 0x40)
2196 /* 8-bit displacement. */
2200 else if ((buf[offset + 2] & 0xc0) == 0x80)
2202 /* 32-bit displacement. */
2210 if (offset - 4 != buf[3])
2213 return next_sal.end;
2216 /* Return PC of first real instruction. */
2219 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2221 struct amd64_frame_cache cache;
2223 CORE_ADDR func_addr;
2225 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2227 CORE_ADDR post_prologue_pc
2228 = skip_prologue_using_sal (gdbarch, func_addr);
2229 struct symtab *s = find_pc_symtab (func_addr);
2231 /* Clang always emits a line note before the prologue and another
2232 one after. We trust clang to emit usable line notes. */
2233 if (post_prologue_pc
2235 && s->producer != NULL
2236 && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
2237 return max (start_pc, post_prologue_pc);
2240 amd64_init_frame_cache (&cache);
2241 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2243 if (cache.frameless_p)
2246 return amd64_skip_xmm_prologue (pc, start_pc);
2250 /* Normal frames. */
2253 amd64_frame_cache_1 (struct frame_info *this_frame,
2254 struct amd64_frame_cache *cache)
2256 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2257 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2261 cache->pc = get_frame_func (this_frame);
2263 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2266 if (cache->frameless_p)
2268 /* We didn't find a valid frame. If we're at the start of a
2269 function, or somewhere half-way its prologue, the function's
2270 frame probably hasn't been fully setup yet. Try to
2271 reconstruct the base address for the stack frame by looking
2272 at the stack pointer. For truly "frameless" functions this
2275 if (cache->saved_sp_reg != -1)
2277 /* Stack pointer has been saved. */
2278 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2279 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2281 /* We're halfway aligning the stack. */
2282 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2283 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2285 /* This will be added back below. */
2286 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2290 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2291 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2297 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2298 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2301 /* Now that we have the base address for the stack frame we can
2302 calculate the value of %rsp in the calling frame. */
2303 cache->saved_sp = cache->base + 16;
2305 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2306 frame we find it at the same offset from the reconstructed base
2307 address. If we're halfway aligning the stack, %rip is handled
2308 differently (see above). */
2309 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2310 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2312 /* Adjust all the saved registers such that they contain addresses
2313 instead of offsets. */
2314 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2315 if (cache->saved_regs[i] != -1)
2316 cache->saved_regs[i] += cache->base;
2321 static struct amd64_frame_cache *
2322 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2324 volatile struct gdb_exception ex;
2325 struct amd64_frame_cache *cache;
2330 cache = amd64_alloc_frame_cache ();
2331 *this_cache = cache;
2333 TRY_CATCH (ex, RETURN_MASK_ERROR)
2335 amd64_frame_cache_1 (this_frame, cache);
2337 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2338 throw_exception (ex);
2343 static enum unwind_stop_reason
2344 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2347 struct amd64_frame_cache *cache =
2348 amd64_frame_cache (this_frame, this_cache);
2351 return UNWIND_UNAVAILABLE;
2353 /* This marks the outermost frame. */
2354 if (cache->base == 0)
2355 return UNWIND_OUTERMOST;
2357 return UNWIND_NO_REASON;
2361 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2362 struct frame_id *this_id)
2364 struct amd64_frame_cache *cache =
2365 amd64_frame_cache (this_frame, this_cache);
2370 /* This marks the outermost frame. */
2371 if (cache->base == 0)
2374 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2377 static struct value *
2378 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2381 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2382 struct amd64_frame_cache *cache =
2383 amd64_frame_cache (this_frame, this_cache);
2385 gdb_assert (regnum >= 0);
2387 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2388 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2390 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2391 return frame_unwind_got_memory (this_frame, regnum,
2392 cache->saved_regs[regnum]);
2394 return frame_unwind_got_register (this_frame, regnum, regnum);
2397 static const struct frame_unwind amd64_frame_unwind =
2400 amd64_frame_unwind_stop_reason,
2401 amd64_frame_this_id,
2402 amd64_frame_prev_register,
2404 default_frame_sniffer
2407 /* Generate a bytecode expression to get the value of the saved PC. */
2410 amd64_gen_return_address (struct gdbarch *gdbarch,
2411 struct agent_expr *ax, struct axs_value *value,
2414 /* The following sequence assumes the traditional use of the base
2416 ax_reg (ax, AMD64_RBP_REGNUM);
2418 ax_simple (ax, aop_add);
2419 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2420 value->kind = axs_lvalue_memory;
2424 /* Signal trampolines. */
2426 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2427 64-bit variants. This would require using identical frame caches
2428 on both platforms. */
2430 static struct amd64_frame_cache *
2431 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2433 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2434 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2435 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2436 volatile struct gdb_exception ex;
2437 struct amd64_frame_cache *cache;
2445 cache = amd64_alloc_frame_cache ();
2447 TRY_CATCH (ex, RETURN_MASK_ERROR)
2449 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2450 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2452 addr = tdep->sigcontext_addr (this_frame);
2453 gdb_assert (tdep->sc_reg_offset);
2454 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2455 for (i = 0; i < tdep->sc_num_regs; i++)
2456 if (tdep->sc_reg_offset[i] != -1)
2457 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2461 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2462 throw_exception (ex);
2464 *this_cache = cache;
2468 static enum unwind_stop_reason
2469 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2472 struct amd64_frame_cache *cache =
2473 amd64_sigtramp_frame_cache (this_frame, this_cache);
2476 return UNWIND_UNAVAILABLE;
2478 return UNWIND_NO_REASON;
2482 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2483 void **this_cache, struct frame_id *this_id)
2485 struct amd64_frame_cache *cache =
2486 amd64_sigtramp_frame_cache (this_frame, this_cache);
2491 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2494 static struct value *
2495 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2496 void **this_cache, int regnum)
2498 /* Make sure we've initialized the cache. */
2499 amd64_sigtramp_frame_cache (this_frame, this_cache);
2501 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2505 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2506 struct frame_info *this_frame,
2509 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2511 /* We shouldn't even bother if we don't have a sigcontext_addr
2513 if (tdep->sigcontext_addr == NULL)
2516 if (tdep->sigtramp_p != NULL)
2518 if (tdep->sigtramp_p (this_frame))
2522 if (tdep->sigtramp_start != 0)
2524 CORE_ADDR pc = get_frame_pc (this_frame);
2526 gdb_assert (tdep->sigtramp_end != 0);
2527 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2534 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2537 amd64_sigtramp_frame_unwind_stop_reason,
2538 amd64_sigtramp_frame_this_id,
2539 amd64_sigtramp_frame_prev_register,
2541 amd64_sigtramp_frame_sniffer
2546 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2548 struct amd64_frame_cache *cache =
2549 amd64_frame_cache (this_frame, this_cache);
2554 static const struct frame_base amd64_frame_base =
2556 &amd64_frame_unwind,
2557 amd64_frame_base_address,
2558 amd64_frame_base_address,
2559 amd64_frame_base_address
2562 /* Normal frames, but in a function epilogue. */
2564 /* The epilogue is defined here as the 'ret' instruction, which will
2565 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2566 the function's stack frame. */
2569 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2572 struct symtab *symtab;
2574 symtab = find_pc_symtab (pc);
2575 if (symtab && symtab->epilogue_unwind_valid)
2578 if (target_read_memory (pc, &insn, 1))
2579 return 0; /* Can't read memory at pc. */
2581 if (insn != 0xc3) /* 'ret' instruction. */
2588 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2589 struct frame_info *this_frame,
2590 void **this_prologue_cache)
2592 if (frame_relative_level (this_frame) == 0)
2593 return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
2594 get_frame_pc (this_frame));
2599 static struct amd64_frame_cache *
2600 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2602 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2603 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2604 volatile struct gdb_exception ex;
2605 struct amd64_frame_cache *cache;
2611 cache = amd64_alloc_frame_cache ();
2612 *this_cache = cache;
2614 TRY_CATCH (ex, RETURN_MASK_ERROR)
2616 /* Cache base will be %esp plus cache->sp_offset (-8). */
2617 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2618 cache->base = extract_unsigned_integer (buf, 8,
2619 byte_order) + cache->sp_offset;
2621 /* Cache pc will be the frame func. */
2622 cache->pc = get_frame_pc (this_frame);
2624 /* The saved %esp will be at cache->base plus 16. */
2625 cache->saved_sp = cache->base + 16;
2627 /* The saved %eip will be at cache->base plus 8. */
2628 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2632 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2633 throw_exception (ex);
2638 static enum unwind_stop_reason
2639 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2642 struct amd64_frame_cache *cache
2643 = amd64_epilogue_frame_cache (this_frame, this_cache);
2646 return UNWIND_UNAVAILABLE;
2648 return UNWIND_NO_REASON;
2652 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2654 struct frame_id *this_id)
2656 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2662 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2665 static const struct frame_unwind amd64_epilogue_frame_unwind =
2668 amd64_epilogue_frame_unwind_stop_reason,
2669 amd64_epilogue_frame_this_id,
2670 amd64_frame_prev_register,
2672 amd64_epilogue_frame_sniffer
2675 static struct frame_id
2676 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2680 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2682 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2685 /* 16 byte align the SP per frame requirements. */
2688 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2690 return sp & -(CORE_ADDR)16;
2694 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2695 in the floating-point register set REGSET to register cache
2696 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2699 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2700 int regnum, const void *fpregs, size_t len)
2702 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2704 gdb_assert (len == tdep->sizeof_fpregset);
2705 amd64_supply_fxsave (regcache, regnum, fpregs);
2708 /* Collect register REGNUM from the register cache REGCACHE and store
2709 it in the buffer specified by FPREGS and LEN as described by the
2710 floating-point register set REGSET. If REGNUM is -1, do this for
2711 all registers in REGSET. */
2714 amd64_collect_fpregset (const struct regset *regset,
2715 const struct regcache *regcache,
2716 int regnum, void *fpregs, size_t len)
2718 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2720 gdb_assert (len == tdep->sizeof_fpregset);
2721 amd64_collect_fxsave (regcache, regnum, fpregs);
2724 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2727 amd64_supply_xstateregset (const struct regset *regset,
2728 struct regcache *regcache, int regnum,
2729 const void *xstateregs, size_t len)
2731 amd64_supply_xsave (regcache, regnum, xstateregs);
2734 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2737 amd64_collect_xstateregset (const struct regset *regset,
2738 const struct regcache *regcache,
2739 int regnum, void *xstateregs, size_t len)
2741 amd64_collect_xsave (regcache, regnum, xstateregs, 1);
2744 /* Return the appropriate register set for the core section identified
2745 by SECT_NAME and SECT_SIZE. */
2747 static const struct regset *
2748 amd64_regset_from_core_section (struct gdbarch *gdbarch,
2749 const char *sect_name, size_t sect_size)
2751 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2753 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2755 if (tdep->fpregset == NULL)
2756 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
2757 amd64_collect_fpregset);
2759 return tdep->fpregset;
2762 if (strcmp (sect_name, ".reg-xstate") == 0)
2764 if (tdep->xstateregset == NULL)
2765 tdep->xstateregset = regset_alloc (gdbarch,
2766 amd64_supply_xstateregset,
2767 amd64_collect_xstateregset);
2769 return tdep->xstateregset;
2772 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
2776 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2777 %rdi. We expect its value to be a pointer to the jmp_buf structure
2778 from which we extract the address that we will land at. This
2779 address is copied into PC. This routine returns non-zero on
2783 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2787 struct gdbarch *gdbarch = get_frame_arch (frame);
2788 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2789 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2791 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2792 longjmp will land. */
2793 if (jb_pc_offset == -1)
2796 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2797 jb_addr= extract_typed_address
2798 (buf, builtin_type (gdbarch)->builtin_data_ptr);
2799 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2802 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2807 static const int amd64_record_regmap[] =
2809 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2810 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2811 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2812 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2813 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2814 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2818 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2820 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2821 const struct target_desc *tdesc = info.target_desc;
2823 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2824 floating-point registers. */
2825 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2827 if (! tdesc_has_registers (tdesc))
2828 tdesc = tdesc_amd64;
2829 tdep->tdesc = tdesc;
2831 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2832 tdep->register_names = amd64_register_names;
2834 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2836 tdep->ymmh_register_names = amd64_ymmh_names;
2837 tdep->num_ymm_regs = 16;
2838 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
2841 tdep->num_byte_regs = 20;
2842 tdep->num_word_regs = 16;
2843 tdep->num_dword_regs = 16;
2844 /* Avoid wiring in the MMX registers for now. */
2845 tdep->num_mmx_regs = 0;
2847 set_gdbarch_pseudo_register_read_value (gdbarch,
2848 amd64_pseudo_register_read_value);
2849 set_gdbarch_pseudo_register_write (gdbarch,
2850 amd64_pseudo_register_write);
2852 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
2854 /* AMD64 has an FPU and 16 SSE registers. */
2855 tdep->st0_regnum = AMD64_ST0_REGNUM;
2856 tdep->num_xmm_regs = 16;
2858 /* This is what all the fuss is about. */
2859 set_gdbarch_long_bit (gdbarch, 64);
2860 set_gdbarch_long_long_bit (gdbarch, 64);
2861 set_gdbarch_ptr_bit (gdbarch, 64);
2863 /* In contrast to the i386, on AMD64 a `long double' actually takes
2864 up 128 bits, even though it's still based on the i387 extended
2865 floating-point format which has only 80 significant bits. */
2866 set_gdbarch_long_double_bit (gdbarch, 128);
2868 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
2870 /* Register numbers of various important registers. */
2871 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
2872 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
2873 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
2874 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
2876 /* The "default" register numbering scheme for AMD64 is referred to
2877 as the "DWARF Register Number Mapping" in the System V psABI.
2878 The preferred debugging format for all known AMD64 targets is
2879 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2880 DWARF-1), but we provide the same mapping just in case. This
2881 mapping is also used for stabs, which GCC does support. */
2882 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2883 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2885 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2886 be in use on any of the supported AMD64 targets. */
2888 /* Call dummy code. */
2889 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
2890 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
2891 set_gdbarch_frame_red_zone_size (gdbarch, 128);
2893 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
2894 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
2895 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
2897 set_gdbarch_return_value (gdbarch, amd64_return_value);
2899 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
2901 tdep->record_regmap = amd64_record_regmap;
2903 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
2905 /* Hook the function epilogue frame unwinder. This unwinder is
2906 appended to the list first, so that it supercedes the other
2907 unwinders in function epilogues. */
2908 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
2910 /* Hook the prologue-based frame unwinders. */
2911 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
2912 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
2913 frame_base_set_default (gdbarch, &amd64_frame_base);
2915 /* If we have a register mapping, enable the generic core file support. */
2916 if (tdep->gregset_reg_offset)
2917 set_gdbarch_regset_from_core_section (gdbarch,
2918 amd64_regset_from_core_section);
2920 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
2922 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
2924 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
2926 /* SystemTap variables and functions. */
2927 set_gdbarch_stap_integer_prefix (gdbarch, "$");
2928 set_gdbarch_stap_register_prefix (gdbarch, "%");
2929 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
2930 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
2931 set_gdbarch_stap_is_single_operand (gdbarch,
2932 i386_stap_is_single_operand);
2933 set_gdbarch_stap_parse_special_token (gdbarch,
2934 i386_stap_parse_special_token);
2938 static struct type *
2939 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2941 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2943 switch (regnum - tdep->eax_regnum)
2945 case AMD64_RBP_REGNUM: /* %ebp */
2946 case AMD64_RSP_REGNUM: /* %esp */
2947 return builtin_type (gdbarch)->builtin_data_ptr;
2948 case AMD64_RIP_REGNUM: /* %eip */
2949 return builtin_type (gdbarch)->builtin_func_ptr;
2952 return i386_pseudo_register_type (gdbarch, regnum);
2956 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2958 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2959 const struct target_desc *tdesc = info.target_desc;
2961 amd64_init_abi (info, gdbarch);
2963 if (! tdesc_has_registers (tdesc))
2965 tdep->tdesc = tdesc;
2967 tdep->num_dword_regs = 17;
2968 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
2970 set_gdbarch_long_bit (gdbarch, 32);
2971 set_gdbarch_ptr_bit (gdbarch, 32);
2974 /* Provide a prototype to silence -Wmissing-prototypes. */
2975 void _initialize_amd64_tdep (void);
2978 _initialize_amd64_tdep (void)
2980 initialize_tdesc_amd64 ();
2981 initialize_tdesc_amd64_avx ();
2982 initialize_tdesc_x32 ();
2983 initialize_tdesc_x32_avx ();
2987 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2988 sense that the instruction pointer and data pointer are simply
2989 64-bit offsets into the code segment and the data segment instead
2990 of a selector offset pair. The functions below store the upper 32
2991 bits of these pointers (instead of just the 16-bits of the segment
2994 /* Fill register REGNUM in REGCACHE with the appropriate
2995 floating-point or SSE register value from *FXSAVE. If REGNUM is
2996 -1, do this for all registers. This function masks off any of the
2997 reserved bits in *FXSAVE. */
3000 amd64_supply_fxsave (struct regcache *regcache, int regnum,
3003 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3004 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3006 i387_supply_fxsave (regcache, regnum, fxsave);
3009 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3011 const gdb_byte *regs = fxsave;
3013 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3014 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3015 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3016 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3020 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3023 amd64_supply_xsave (struct regcache *regcache, int regnum,
3026 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3027 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3029 i387_supply_xsave (regcache, regnum, xsave);
3032 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3034 const gdb_byte *regs = xsave;
3036 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3037 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3039 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3040 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3045 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3046 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3047 all registers. This function doesn't touch any of the reserved
3051 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3054 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3055 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3056 gdb_byte *regs = fxsave;
3058 i387_collect_fxsave (regcache, regnum, fxsave);
3060 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3062 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3063 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3064 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3065 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3069 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3072 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3073 void *xsave, int gcore)
3075 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3076 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3077 gdb_byte *regs = xsave;
3079 i387_collect_xsave (regcache, regnum, xsave, gcore);
3081 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3083 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3084 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3086 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3087 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),