1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
26 #include "arch-utils.h"
28 #include "dummy-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
40 #include "gdb_assert.h"
42 #include "amd64-tdep.h"
43 #include "i387-tdep.h"
45 /* Note that the AMD64 architecture was previously known as x86-64.
46 The latter is (forever) engraved into the canonical system name as
47 returned by config.guess, and used as the name for the AMD64 port
48 of GNU/Linux. The BSD's have renamed their ports to amd64; they
49 don't like to shout. For GDB we prefer the amd64_-prefix over the
50 x86_64_-prefix since it's so much easier to type. */
52 /* Register information. */
54 struct amd64_register_info
60 static struct amd64_register_info const amd64_register_info[] =
62 { "rax", &builtin_type_int64 },
63 { "rbx", &builtin_type_int64 },
64 { "rcx", &builtin_type_int64 },
65 { "rdx", &builtin_type_int64 },
66 { "rsi", &builtin_type_int64 },
67 { "rdi", &builtin_type_int64 },
68 { "rbp", &builtin_type_void_data_ptr },
69 { "rsp", &builtin_type_void_data_ptr },
71 /* %r8 is indeed register number 8. */
72 { "r8", &builtin_type_int64 },
73 { "r9", &builtin_type_int64 },
74 { "r10", &builtin_type_int64 },
75 { "r11", &builtin_type_int64 },
76 { "r12", &builtin_type_int64 },
77 { "r13", &builtin_type_int64 },
78 { "r14", &builtin_type_int64 },
79 { "r15", &builtin_type_int64 },
80 { "rip", &builtin_type_void_func_ptr },
81 { "eflags", &i386_eflags_type },
82 { "cs", &builtin_type_int32 },
83 { "ss", &builtin_type_int32 },
84 { "ds", &builtin_type_int32 },
85 { "es", &builtin_type_int32 },
86 { "fs", &builtin_type_int32 },
87 { "gs", &builtin_type_int32 },
89 /* %st0 is register number 24. */
90 { "st0", &builtin_type_i387_ext },
91 { "st1", &builtin_type_i387_ext },
92 { "st2", &builtin_type_i387_ext },
93 { "st3", &builtin_type_i387_ext },
94 { "st4", &builtin_type_i387_ext },
95 { "st5", &builtin_type_i387_ext },
96 { "st6", &builtin_type_i387_ext },
97 { "st7", &builtin_type_i387_ext },
98 { "fctrl", &builtin_type_int32 },
99 { "fstat", &builtin_type_int32 },
100 { "ftag", &builtin_type_int32 },
101 { "fiseg", &builtin_type_int32 },
102 { "fioff", &builtin_type_int32 },
103 { "foseg", &builtin_type_int32 },
104 { "fooff", &builtin_type_int32 },
105 { "fop", &builtin_type_int32 },
107 /* %xmm0 is register number 40. */
108 { "xmm0", &i386_sse_type },
109 { "xmm1", &i386_sse_type },
110 { "xmm2", &i386_sse_type },
111 { "xmm3", &i386_sse_type },
112 { "xmm4", &i386_sse_type },
113 { "xmm5", &i386_sse_type },
114 { "xmm6", &i386_sse_type },
115 { "xmm7", &i386_sse_type },
116 { "xmm8", &i386_sse_type },
117 { "xmm9", &i386_sse_type },
118 { "xmm10", &i386_sse_type },
119 { "xmm11", &i386_sse_type },
120 { "xmm12", &i386_sse_type },
121 { "xmm13", &i386_sse_type },
122 { "xmm14", &i386_sse_type },
123 { "xmm15", &i386_sse_type },
124 { "mxcsr", &builtin_type_int32 }
127 /* Total number of registers. */
128 #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_info)
130 /* Return the name of register REGNUM. */
133 amd64_register_name (int regnum)
135 if (regnum >= 0 && regnum < AMD64_NUM_REGS)
136 return amd64_register_info[regnum].name;
141 /* Return the GDB type object for the "standard" data type of data in
145 amd64_register_type (struct gdbarch *gdbarch, int regnum)
147 gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS);
149 return *amd64_register_info[regnum].type;
152 /* DWARF Register Number Mapping as defined in the System V psABI,
155 static int amd64_dwarf_regmap[] =
157 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
158 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
159 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
160 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
162 /* Frame Pointer Register RBP. */
165 /* Stack Pointer Register RSP. */
168 /* Extended Integer Registers 8 - 15. */
169 8, 9, 10, 11, 12, 13, 14, 15,
171 /* Return Address RA. Mapped to RIP. */
174 /* SSE Registers 0 - 7. */
175 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
176 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
177 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
178 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
180 /* Extended SSE Registers 8 - 15. */
181 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
182 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
183 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
184 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
186 /* Floating Point Registers 0-7. */
187 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
188 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
189 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
190 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
192 /* Control and Status Flags Register. */
195 /* Selector Registers. */
205 /* Segment Base Address Registers. */
211 /* Special Selector Registers. */
215 /* Floating Point Control Registers. */
221 static const int amd64_dwarf_regmap_len =
222 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
224 /* Convert DWARF register number REG to the appropriate register
225 number used by GDB. */
228 amd64_dwarf_reg_to_regnum (int reg)
232 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
233 regnum = amd64_dwarf_regmap[reg];
236 warning (_("Unmapped DWARF Register #%d encountered."), reg);
241 /* Return nonzero if a value of type TYPE stored in register REGNUM
242 needs any special handling. */
245 amd64_convert_register_p (int regnum, struct type *type)
247 return i386_fp_regnum_p (regnum);
251 /* Register classes as defined in the psABI. */
265 /* Return the union class of CLASS1 and CLASS2. See the psABI for
268 static enum amd64_reg_class
269 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
271 /* Rule (a): If both classes are equal, this is the resulting class. */
272 if (class1 == class2)
275 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
276 is the other class. */
277 if (class1 == AMD64_NO_CLASS)
279 if (class2 == AMD64_NO_CLASS)
282 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
283 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
286 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
287 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
288 return AMD64_INTEGER;
290 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
291 MEMORY is used as class. */
292 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
293 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
294 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
297 /* Rule (f): Otherwise class SSE is used. */
301 static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
303 /* Return non-zero if TYPE is a non-POD structure or union type. */
306 amd64_non_pod_p (struct type *type)
308 /* ??? A class with a base class certainly isn't POD, but does this
309 catch all non-POD structure types? */
310 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
316 /* Classify TYPE according to the rules for aggregate (structures and
317 arrays) and union types, and store the result in CLASS. */
320 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
322 int len = TYPE_LENGTH (type);
324 /* 1. If the size of an object is larger than two eightbytes, or in
325 C++, is a non-POD structure or union type, or contains
326 unaligned fields, it has class memory. */
327 if (len > 16 || amd64_non_pod_p (type))
329 class[0] = class[1] = AMD64_MEMORY;
333 /* 2. Both eightbytes get initialized to class NO_CLASS. */
334 class[0] = class[1] = AMD64_NO_CLASS;
336 /* 3. Each field of an object is classified recursively so that
337 always two fields are considered. The resulting class is
338 calculated according to the classes of the fields in the
341 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
343 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
345 /* All fields in an array have the same type. */
346 amd64_classify (subtype, class);
347 if (len > 8 && class[1] == AMD64_NO_CLASS)
354 /* Structure or union. */
355 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
356 || TYPE_CODE (type) == TYPE_CODE_UNION);
358 for (i = 0; i < TYPE_NFIELDS (type); i++)
360 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
361 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
362 enum amd64_reg_class subclass[2];
364 /* Ignore static fields. */
365 if (TYPE_FIELD_STATIC (type, i))
368 gdb_assert (pos == 0 || pos == 1);
370 amd64_classify (subtype, subclass);
371 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
373 class[1] = amd64_merge_classes (class[1], subclass[1]);
377 /* 4. Then a post merger cleanup is done: */
379 /* Rule (a): If one of the classes is MEMORY, the whole argument is
381 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
382 class[0] = class[1] = AMD64_MEMORY;
384 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
386 if (class[0] == AMD64_SSEUP)
387 class[0] = AMD64_SSE;
388 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
389 class[1] = AMD64_SSE;
392 /* Classify TYPE, and store the result in CLASS. */
395 amd64_classify (struct type *type, enum amd64_reg_class class[2])
397 enum type_code code = TYPE_CODE (type);
398 int len = TYPE_LENGTH (type);
400 class[0] = class[1] = AMD64_NO_CLASS;
402 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
403 long, long long, and pointers are in the INTEGER class. Similarly,
404 range types, used by languages such as Ada, are also in the INTEGER
406 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
407 || code == TYPE_CODE_RANGE
408 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
409 && (len == 1 || len == 2 || len == 4 || len == 8))
410 class[0] = AMD64_INTEGER;
412 /* Arguments of types float, double and __m64 are in class SSE. */
413 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
415 class[0] = AMD64_SSE;
417 /* Arguments of types __float128 and __m128 are split into two
418 halves. The least significant ones belong to class SSE, the most
419 significant one to class SSEUP. */
420 /* FIXME: __float128, __m128. */
422 /* The 64-bit mantissa of arguments of type long double belongs to
423 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
425 else if (code == TYPE_CODE_FLT && len == 16)
426 /* Class X87 and X87UP. */
427 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
430 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
431 || code == TYPE_CODE_UNION)
432 amd64_classify_aggregate (type, class);
435 static enum return_value_convention
436 amd64_return_value (struct gdbarch *gdbarch, struct type *type,
437 struct regcache *regcache,
438 gdb_byte *readbuf, const gdb_byte *writebuf)
440 enum amd64_reg_class class[2];
441 int len = TYPE_LENGTH (type);
442 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
443 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
448 gdb_assert (!(readbuf && writebuf));
450 /* 1. Classify the return type with the classification algorithm. */
451 amd64_classify (type, class);
453 /* 2. If the type has class MEMORY, then the caller provides space
454 for the return value and passes the address of this storage in
455 %rdi as if it were the first argument to the function. In effect,
456 this address becomes a hidden first argument.
458 On return %rax will contain the address that has been passed in
459 by the caller in %rdi. */
460 if (class[0] == AMD64_MEMORY)
462 /* As indicated by the comment above, the ABI guarantees that we
463 can always find the return value just after the function has
470 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
471 read_memory (addr, readbuf, TYPE_LENGTH (type));
474 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
477 gdb_assert (class[1] != AMD64_MEMORY);
478 gdb_assert (len <= 16);
480 for (i = 0; len > 0; i++, len -= 8)
488 /* 3. If the class is INTEGER, the next available register
489 of the sequence %rax, %rdx is used. */
490 regnum = integer_regnum[integer_reg++];
494 /* 4. If the class is SSE, the next available SSE register
495 of the sequence %xmm0, %xmm1 is used. */
496 regnum = sse_regnum[sse_reg++];
500 /* 5. If the class is SSEUP, the eightbyte is passed in the
501 upper half of the last used SSE register. */
502 gdb_assert (sse_reg > 0);
503 regnum = sse_regnum[sse_reg - 1];
508 /* 6. If the class is X87, the value is returned on the X87
509 stack in %st0 as 80-bit x87 number. */
510 regnum = AMD64_ST0_REGNUM;
512 i387_return_value (gdbarch, regcache);
516 /* 7. If the class is X87UP, the value is returned together
517 with the previous X87 value in %st0. */
518 gdb_assert (i > 0 && class[0] == AMD64_X87);
519 regnum = AMD64_ST0_REGNUM;
528 gdb_assert (!"Unexpected register class.");
531 gdb_assert (regnum != -1);
534 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
537 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
541 return RETURN_VALUE_REGISTER_CONVENTION;
546 amd64_push_arguments (struct regcache *regcache, int nargs,
547 struct value **args, CORE_ADDR sp, int struct_return)
549 static int integer_regnum[] =
551 AMD64_RDI_REGNUM, /* %rdi */
552 AMD64_RSI_REGNUM, /* %rsi */
553 AMD64_RDX_REGNUM, /* %rdx */
554 AMD64_RCX_REGNUM, /* %rcx */
558 static int sse_regnum[] =
560 /* %xmm0 ... %xmm7 */
561 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
562 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
563 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
564 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
566 struct value **stack_args = alloca (nargs * sizeof (struct value *));
567 int num_stack_args = 0;
568 int num_elements = 0;
574 /* Reserve a register for the "hidden" argument. */
578 for (i = 0; i < nargs; i++)
580 struct type *type = value_type (args[i]);
581 int len = TYPE_LENGTH (type);
582 enum amd64_reg_class class[2];
583 int needed_integer_regs = 0;
584 int needed_sse_regs = 0;
587 /* Classify argument. */
588 amd64_classify (type, class);
590 /* Calculate the number of integer and SSE registers needed for
592 for (j = 0; j < 2; j++)
594 if (class[j] == AMD64_INTEGER)
595 needed_integer_regs++;
596 else if (class[j] == AMD64_SSE)
600 /* Check whether enough registers are available, and if the
601 argument should be passed in registers at all. */
602 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
603 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
604 || (needed_integer_regs == 0 && needed_sse_regs == 0))
606 /* The argument will be passed on the stack. */
607 num_elements += ((len + 7) / 8);
608 stack_args[num_stack_args++] = args[i];
612 /* The argument will be passed in registers. */
613 const gdb_byte *valbuf = value_contents (args[i]);
616 gdb_assert (len <= 16);
618 for (j = 0; len > 0; j++, len -= 8)
626 regnum = integer_regnum[integer_reg++];
630 regnum = sse_regnum[sse_reg++];
634 gdb_assert (sse_reg > 0);
635 regnum = sse_regnum[sse_reg - 1];
640 gdb_assert (!"Unexpected register class.");
643 gdb_assert (regnum != -1);
644 memset (buf, 0, sizeof buf);
645 memcpy (buf, valbuf + j * 8, min (len, 8));
646 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
651 /* Allocate space for the arguments on the stack. */
652 sp -= num_elements * 8;
654 /* The psABI says that "The end of the input argument area shall be
655 aligned on a 16 byte boundary." */
658 /* Write out the arguments to the stack. */
659 for (i = 0; i < num_stack_args; i++)
661 struct type *type = value_type (stack_args[i]);
662 const gdb_byte *valbuf = value_contents (stack_args[i]);
663 int len = TYPE_LENGTH (type);
665 write_memory (sp + element * 8, valbuf, len);
666 element += ((len + 7) / 8);
669 /* The psABI says that "For calls that may call functions that use
670 varargs or stdargs (prototype-less calls or calls to functions
671 containing ellipsis (...) in the declaration) %al is used as
672 hidden argument to specify the number of SSE registers used. */
673 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
678 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
679 struct regcache *regcache, CORE_ADDR bp_addr,
680 int nargs, struct value **args, CORE_ADDR sp,
681 int struct_return, CORE_ADDR struct_addr)
685 /* Pass arguments. */
686 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
688 /* Pass "hidden" argument". */
691 store_unsigned_integer (buf, 8, struct_addr);
692 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
695 /* Store return address. */
697 store_unsigned_integer (buf, 8, bp_addr);
698 write_memory (sp, buf, 8);
700 /* Finally, update the stack pointer... */
701 store_unsigned_integer (buf, 8, sp);
702 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
704 /* ...and fake a frame pointer. */
705 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
711 /* The maximum number of saved registers. This should include %rip. */
712 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
714 struct amd64_frame_cache
721 /* Saved registers. */
722 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
725 /* Do we have a frame? */
729 /* Allocate and initialize a frame cache. */
731 static struct amd64_frame_cache *
732 amd64_alloc_frame_cache (void)
734 struct amd64_frame_cache *cache;
737 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
741 cache->sp_offset = -8;
744 /* Saved registers. We initialize these to -1 since zero is a valid
745 offset (that's where %rbp is supposed to be stored). */
746 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
747 cache->saved_regs[i] = -1;
750 /* Frameless until proven otherwise. */
751 cache->frameless_p = 1;
756 /* Do a limited analysis of the prologue at PC and update CACHE
757 accordingly. Bail out early if CURRENT_PC is reached. Return the
758 address where the analysis stopped.
760 We will handle only functions beginning with:
763 movq %rsp, %rbp 0x48 0x89 0xe5
765 Any function that doesn't start with this sequence will be assumed
766 to have no prologue and thus no valid frame pointer in %rbp. */
769 amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
770 struct amd64_frame_cache *cache)
772 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
776 if (current_pc <= pc)
779 op = read_memory_unsigned_integer (pc, 1);
781 if (op == 0x55) /* pushq %rbp */
783 /* Take into account that we've executed the `pushq %rbp' that
784 starts this instruction sequence. */
785 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
786 cache->sp_offset += 8;
788 /* If that's all, return now. */
789 if (current_pc <= pc + 1)
792 /* Check for `movq %rsp, %rbp'. */
793 read_memory (pc + 1, buf, 3);
794 if (memcmp (buf, proto, 3) != 0)
797 /* OK, we actually have a frame. */
798 cache->frameless_p = 0;
805 /* Return PC of first real instruction. */
808 amd64_skip_prologue (CORE_ADDR start_pc)
810 struct amd64_frame_cache cache;
813 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache);
814 if (cache.frameless_p)
823 static struct amd64_frame_cache *
824 amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
826 struct amd64_frame_cache *cache;
833 cache = amd64_alloc_frame_cache ();
836 cache->pc = frame_func_unwind (next_frame);
838 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
840 if (cache->frameless_p)
842 /* We didn't find a valid frame. If we're at the start of a
843 function, or somewhere half-way its prologue, the function's
844 frame probably hasn't been fully setup yet. Try to
845 reconstruct the base address for the stack frame by looking
846 at the stack pointer. For truly "frameless" functions this
849 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
850 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
854 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
855 cache->base = extract_unsigned_integer (buf, 8);
858 /* Now that we have the base address for the stack frame we can
859 calculate the value of %rsp in the calling frame. */
860 cache->saved_sp = cache->base + 16;
862 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
863 frame we find it at the same offset from the reconstructed base
865 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
867 /* Adjust all the saved registers such that they contain addresses
868 instead of offsets. */
869 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
870 if (cache->saved_regs[i] != -1)
871 cache->saved_regs[i] += cache->base;
877 amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
878 struct frame_id *this_id)
880 struct amd64_frame_cache *cache =
881 amd64_frame_cache (next_frame, this_cache);
883 /* This marks the outermost frame. */
884 if (cache->base == 0)
887 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
891 amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
892 int regnum, int *optimizedp,
893 enum lval_type *lvalp, CORE_ADDR *addrp,
894 int *realnump, gdb_byte *valuep)
896 struct amd64_frame_cache *cache =
897 amd64_frame_cache (next_frame, this_cache);
899 gdb_assert (regnum >= 0);
901 if (regnum == SP_REGNUM && cache->saved_sp)
909 /* Store the value. */
910 store_unsigned_integer (valuep, 8, cache->saved_sp);
915 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
918 *lvalp = lval_memory;
919 *addrp = cache->saved_regs[regnum];
923 /* Read the value in from memory. */
924 read_memory (*addrp, valuep,
925 register_size (current_gdbarch, regnum));
931 *lvalp = lval_register;
935 frame_unwind_register (next_frame, (*realnump), valuep);
938 static const struct frame_unwind amd64_frame_unwind =
942 amd64_frame_prev_register
945 static const struct frame_unwind *
946 amd64_frame_sniffer (struct frame_info *next_frame)
948 return &amd64_frame_unwind;
952 /* Signal trampolines. */
954 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
955 64-bit variants. This would require using identical frame caches
956 on both platforms. */
958 static struct amd64_frame_cache *
959 amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
961 struct amd64_frame_cache *cache;
962 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
970 cache = amd64_alloc_frame_cache ();
972 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
973 cache->base = extract_unsigned_integer (buf, 8) - 8;
975 addr = tdep->sigcontext_addr (next_frame);
976 gdb_assert (tdep->sc_reg_offset);
977 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
978 for (i = 0; i < tdep->sc_num_regs; i++)
979 if (tdep->sc_reg_offset[i] != -1)
980 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
987 amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
988 void **this_cache, struct frame_id *this_id)
990 struct amd64_frame_cache *cache =
991 amd64_sigtramp_frame_cache (next_frame, this_cache);
993 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
997 amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
999 int regnum, int *optimizedp,
1000 enum lval_type *lvalp, CORE_ADDR *addrp,
1001 int *realnump, gdb_byte *valuep)
1003 /* Make sure we've initialized the cache. */
1004 amd64_sigtramp_frame_cache (next_frame, this_cache);
1006 amd64_frame_prev_register (next_frame, this_cache, regnum,
1007 optimizedp, lvalp, addrp, realnump, valuep);
1010 static const struct frame_unwind amd64_sigtramp_frame_unwind =
1013 amd64_sigtramp_frame_this_id,
1014 amd64_sigtramp_frame_prev_register
1017 static const struct frame_unwind *
1018 amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
1020 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
1022 /* We shouldn't even bother if we don't have a sigcontext_addr
1024 if (tdep->sigcontext_addr == NULL)
1027 if (tdep->sigtramp_p != NULL)
1029 if (tdep->sigtramp_p (next_frame))
1030 return &amd64_sigtramp_frame_unwind;
1033 if (tdep->sigtramp_start != 0)
1035 CORE_ADDR pc = frame_pc_unwind (next_frame);
1037 gdb_assert (tdep->sigtramp_end != 0);
1038 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1039 return &amd64_sigtramp_frame_unwind;
1047 amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1049 struct amd64_frame_cache *cache =
1050 amd64_frame_cache (next_frame, this_cache);
1055 static const struct frame_base amd64_frame_base =
1057 &amd64_frame_unwind,
1058 amd64_frame_base_address,
1059 amd64_frame_base_address,
1060 amd64_frame_base_address
1063 static struct frame_id
1064 amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1069 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
1070 fp = extract_unsigned_integer (buf, 8);
1072 return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
1075 /* 16 byte align the SP per frame requirements. */
1078 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1080 return sp & -(CORE_ADDR)16;
1084 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
1085 in the floating-point register set REGSET to register cache
1086 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
1089 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
1090 int regnum, const void *fpregs, size_t len)
1092 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1094 gdb_assert (len == tdep->sizeof_fpregset);
1095 amd64_supply_fxsave (regcache, regnum, fpregs);
1098 /* Collect register REGNUM from the register cache REGCACHE and store
1099 it in the buffer specified by FPREGS and LEN as described by the
1100 floating-point register set REGSET. If REGNUM is -1, do this for
1101 all registers in REGSET. */
1104 amd64_collect_fpregset (const struct regset *regset,
1105 const struct regcache *regcache,
1106 int regnum, void *fpregs, size_t len)
1108 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1110 gdb_assert (len == tdep->sizeof_fpregset);
1111 amd64_collect_fxsave (regcache, regnum, fpregs);
1114 /* Return the appropriate register set for the core section identified
1115 by SECT_NAME and SECT_SIZE. */
1117 static const struct regset *
1118 amd64_regset_from_core_section (struct gdbarch *gdbarch,
1119 const char *sect_name, size_t sect_size)
1121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1123 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
1125 if (tdep->fpregset == NULL)
1126 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
1127 amd64_collect_fpregset);
1129 return tdep->fpregset;
1132 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
1137 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1141 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1142 floating-point registers. */
1143 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
1145 /* AMD64 has an FPU and 16 SSE registers. */
1146 tdep->st0_regnum = AMD64_ST0_REGNUM;
1147 tdep->num_xmm_regs = 16;
1149 /* This is what all the fuss is about. */
1150 set_gdbarch_long_bit (gdbarch, 64);
1151 set_gdbarch_long_long_bit (gdbarch, 64);
1152 set_gdbarch_ptr_bit (gdbarch, 64);
1154 /* In contrast to the i386, on AMD64 a `long double' actually takes
1155 up 128 bits, even though it's still based on the i387 extended
1156 floating-point format which has only 80 significant bits. */
1157 set_gdbarch_long_double_bit (gdbarch, 128);
1159 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
1160 set_gdbarch_register_name (gdbarch, amd64_register_name);
1161 set_gdbarch_register_type (gdbarch, amd64_register_type);
1163 /* Register numbers of various important registers. */
1164 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
1165 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
1166 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
1167 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
1169 /* The "default" register numbering scheme for AMD64 is referred to
1170 as the "DWARF Register Number Mapping" in the System V psABI.
1171 The preferred debugging format for all known AMD64 targets is
1172 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1173 DWARF-1), but we provide the same mapping just in case. This
1174 mapping is also used for stabs, which GCC does support. */
1175 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1176 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1177 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1179 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1180 be in use on any of the supported AMD64 targets. */
1182 /* Call dummy code. */
1183 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
1184 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
1185 set_gdbarch_frame_red_zone_size (gdbarch, 128);
1187 set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
1188 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1189 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1191 set_gdbarch_return_value (gdbarch, amd64_return_value);
1193 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
1195 /* Avoid wiring in the MMX registers for now. */
1196 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1197 tdep->mm0_regnum = -1;
1199 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
1201 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
1202 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
1203 frame_base_set_default (gdbarch, &amd64_frame_base);
1205 /* If we have a register mapping, enable the generic core file support. */
1206 if (tdep->gregset_reg_offset)
1207 set_gdbarch_regset_from_core_section (gdbarch,
1208 amd64_regset_from_core_section);
1212 #define I387_ST0_REGNUM AMD64_ST0_REGNUM
1214 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1215 sense that the instruction pointer and data pointer are simply
1216 64-bit offsets into the code segment and the data segment instead
1217 of a selector offset pair. The functions below store the upper 32
1218 bits of these pointers (instead of just the 16-bits of the segment
1221 /* Fill register REGNUM in REGCACHE with the appropriate
1222 floating-point or SSE register value from *FXSAVE. If REGNUM is
1223 -1, do this for all registers. This function masks off any of the
1224 reserved bits in *FXSAVE. */
1227 amd64_supply_fxsave (struct regcache *regcache, int regnum,
1230 i387_supply_fxsave (regcache, regnum, fxsave);
1232 if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1234 const gdb_byte *regs = fxsave;
1236 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1237 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
1238 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1239 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
1243 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1244 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
1245 all registers. This function doesn't touch any of the reserved
1249 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
1252 gdb_byte *regs = fxsave;
1254 i387_collect_fxsave (regcache, regnum, fxsave);
1256 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1258 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1259 regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12);
1260 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1261 regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20);