1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
52 /* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
54 returned by config.guess, and used as the name for the AMD64 port
55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
59 /* Register information. */
61 static const char *amd64_register_names[] =
63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
65 /* %r8 is indeed register number 8. */
66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
69 /* %st0 is register number 24. */
70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
73 /* %xmm0 is register number 40. */
74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
79 static const char *amd64_ymm_names[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
87 static const char *amd64_ymmh_names[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
95 /* The registers used to pass integer arguments during a function call. */
96 static int amd64_dummy_call_integer_regs[] =
98 AMD64_RDI_REGNUM, /* %rdi */
99 AMD64_RSI_REGNUM, /* %rsi */
100 AMD64_RDX_REGNUM, /* %rdx */
101 AMD64_RCX_REGNUM, /* %rcx */
106 /* DWARF Register Number Mapping as defined in the System V psABI,
109 static int amd64_dwarf_regmap[] =
111 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
112 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
113 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
114 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
116 /* Frame Pointer Register RBP. */
119 /* Stack Pointer Register RSP. */
122 /* Extended Integer Registers 8 - 15. */
123 8, 9, 10, 11, 12, 13, 14, 15,
125 /* Return Address RA. Mapped to RIP. */
128 /* SSE Registers 0 - 7. */
129 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
130 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
131 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
132 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
134 /* Extended SSE Registers 8 - 15. */
135 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
136 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
137 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
138 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
140 /* Floating Point Registers 0-7. */
141 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
142 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
143 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
144 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
146 /* Control and Status Flags Register. */
149 /* Selector Registers. */
159 /* Segment Base Address Registers. */
165 /* Special Selector Registers. */
169 /* Floating Point Control Registers. */
175 static const int amd64_dwarf_regmap_len =
176 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
178 /* Convert DWARF register number REG to the appropriate register
179 number used by GDB. */
182 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
185 int ymm0_regnum = tdep->ymm0_regnum;
188 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
189 regnum = amd64_dwarf_regmap[reg];
192 warning (_("Unmapped DWARF Register #%d encountered."), reg);
193 else if (ymm0_regnum >= 0
194 && i386_xmm_regnum_p (gdbarch, regnum))
195 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
200 /* Map architectural register numbers to gdb register numbers. */
202 static const int amd64_arch_regmap[16] =
204 AMD64_RAX_REGNUM, /* %rax */
205 AMD64_RCX_REGNUM, /* %rcx */
206 AMD64_RDX_REGNUM, /* %rdx */
207 AMD64_RBX_REGNUM, /* %rbx */
208 AMD64_RSP_REGNUM, /* %rsp */
209 AMD64_RBP_REGNUM, /* %rbp */
210 AMD64_RSI_REGNUM, /* %rsi */
211 AMD64_RDI_REGNUM, /* %rdi */
212 AMD64_R8_REGNUM, /* %r8 */
213 AMD64_R9_REGNUM, /* %r9 */
214 AMD64_R10_REGNUM, /* %r10 */
215 AMD64_R11_REGNUM, /* %r11 */
216 AMD64_R12_REGNUM, /* %r12 */
217 AMD64_R13_REGNUM, /* %r13 */
218 AMD64_R14_REGNUM, /* %r14 */
219 AMD64_R15_REGNUM /* %r15 */
222 static const int amd64_arch_regmap_len =
223 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
225 /* Convert architectural register number REG to the appropriate register
226 number used by GDB. */
229 amd64_arch_reg_to_regnum (int reg)
231 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
233 return amd64_arch_regmap[reg];
236 /* Register names for byte pseudo-registers. */
238 static const char *amd64_byte_names[] =
240 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
241 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
242 "ah", "bh", "ch", "dh"
245 /* Number of lower byte registers. */
246 #define AMD64_NUM_LOWER_BYTE_REGS 16
248 /* Register names for word pseudo-registers. */
250 static const char *amd64_word_names[] =
252 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
253 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
256 /* Register names for dword pseudo-registers. */
258 static const char *amd64_dword_names[] =
260 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
261 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
265 /* Return the name of register REGNUM. */
268 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
270 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
271 if (i386_byte_regnum_p (gdbarch, regnum))
272 return amd64_byte_names[regnum - tdep->al_regnum];
273 else if (i386_ymm_regnum_p (gdbarch, regnum))
274 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
275 else if (i386_word_regnum_p (gdbarch, regnum))
276 return amd64_word_names[regnum - tdep->ax_regnum];
277 else if (i386_dword_regnum_p (gdbarch, regnum))
278 return amd64_dword_names[regnum - tdep->eax_regnum];
280 return i386_pseudo_register_name (gdbarch, regnum);
283 static struct value *
284 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
285 struct regcache *regcache,
288 gdb_byte raw_buf[MAX_REGISTER_SIZE];
289 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
290 enum register_status status;
291 struct value *result_value;
294 result_value = allocate_value (register_type (gdbarch, regnum));
295 VALUE_LVAL (result_value) = lval_register;
296 VALUE_REGNUM (result_value) = regnum;
297 buf = value_contents_raw (result_value);
299 if (i386_byte_regnum_p (gdbarch, regnum))
301 int gpnum = regnum - tdep->al_regnum;
303 /* Extract (always little endian). */
304 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
306 /* Special handling for AH, BH, CH, DH. */
307 status = regcache_raw_read (regcache,
308 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
310 if (status == REG_VALID)
311 memcpy (buf, raw_buf + 1, 1);
313 mark_value_bytes_unavailable (result_value, 0,
314 TYPE_LENGTH (value_type (result_value)));
318 status = regcache_raw_read (regcache, gpnum, raw_buf);
319 if (status == REG_VALID)
320 memcpy (buf, raw_buf, 1);
322 mark_value_bytes_unavailable (result_value, 0,
323 TYPE_LENGTH (value_type (result_value)));
326 else if (i386_dword_regnum_p (gdbarch, regnum))
328 int gpnum = regnum - tdep->eax_regnum;
329 /* Extract (always little endian). */
330 status = regcache_raw_read (regcache, gpnum, raw_buf);
331 if (status == REG_VALID)
332 memcpy (buf, raw_buf, 4);
334 mark_value_bytes_unavailable (result_value, 0,
335 TYPE_LENGTH (value_type (result_value)));
338 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
345 amd64_pseudo_register_write (struct gdbarch *gdbarch,
346 struct regcache *regcache,
347 int regnum, const gdb_byte *buf)
349 gdb_byte raw_buf[MAX_REGISTER_SIZE];
350 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
352 if (i386_byte_regnum_p (gdbarch, regnum))
354 int gpnum = regnum - tdep->al_regnum;
356 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
358 /* Read ... AH, BH, CH, DH. */
359 regcache_raw_read (regcache,
360 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
361 /* ... Modify ... (always little endian). */
362 memcpy (raw_buf + 1, buf, 1);
364 regcache_raw_write (regcache,
365 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
370 regcache_raw_read (regcache, gpnum, raw_buf);
371 /* ... Modify ... (always little endian). */
372 memcpy (raw_buf, buf, 1);
374 regcache_raw_write (regcache, gpnum, raw_buf);
377 else if (i386_dword_regnum_p (gdbarch, regnum))
379 int gpnum = regnum - tdep->eax_regnum;
382 regcache_raw_read (regcache, gpnum, raw_buf);
383 /* ... Modify ... (always little endian). */
384 memcpy (raw_buf, buf, 4);
386 regcache_raw_write (regcache, gpnum, raw_buf);
389 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
394 /* Return the union class of CLASS1 and CLASS2. See the psABI for
397 static enum amd64_reg_class
398 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
400 /* Rule (a): If both classes are equal, this is the resulting class. */
401 if (class1 == class2)
404 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
405 is the other class. */
406 if (class1 == AMD64_NO_CLASS)
408 if (class2 == AMD64_NO_CLASS)
411 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
412 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
415 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
416 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
417 return AMD64_INTEGER;
419 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
420 MEMORY is used as class. */
421 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
422 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
423 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
426 /* Rule (f): Otherwise class SSE is used. */
430 /* Return non-zero if TYPE is a non-POD structure or union type. */
433 amd64_non_pod_p (struct type *type)
435 /* ??? A class with a base class certainly isn't POD, but does this
436 catch all non-POD structure types? */
437 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
443 /* Classify TYPE according to the rules for aggregate (structures and
444 arrays) and union types, and store the result in CLASS. */
447 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
449 /* 1. If the size of an object is larger than two eightbytes, or in
450 C++, is a non-POD structure or union type, or contains
451 unaligned fields, it has class memory. */
452 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
454 class[0] = class[1] = AMD64_MEMORY;
458 /* 2. Both eightbytes get initialized to class NO_CLASS. */
459 class[0] = class[1] = AMD64_NO_CLASS;
461 /* 3. Each field of an object is classified recursively so that
462 always two fields are considered. The resulting class is
463 calculated according to the classes of the fields in the
466 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
468 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
470 /* All fields in an array have the same type. */
471 amd64_classify (subtype, class);
472 if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS)
479 /* Structure or union. */
480 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
481 || TYPE_CODE (type) == TYPE_CODE_UNION);
483 for (i = 0; i < TYPE_NFIELDS (type); i++)
485 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
486 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
487 enum amd64_reg_class subclass[2];
488 int bitsize = TYPE_FIELD_BITSIZE (type, i);
492 bitsize = TYPE_LENGTH (subtype) * 8;
493 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
495 /* Ignore static fields. */
496 if (field_is_static (&TYPE_FIELD (type, i)))
499 gdb_assert (pos == 0 || pos == 1);
501 amd64_classify (subtype, subclass);
502 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
503 if (bitsize <= 64 && pos == 0 && endpos == 1)
504 /* This is a bit of an odd case: We have a field that would
505 normally fit in one of the two eightbytes, except that
506 it is placed in a way that this field straddles them.
507 This has been seen with a structure containing an array.
509 The ABI is a bit unclear in this case, but we assume that
510 this field's class (stored in subclass[0]) must also be merged
511 into class[1]. In other words, our field has a piece stored
512 in the second eight-byte, and thus its class applies to
513 the second eight-byte as well.
515 In the case where the field length exceeds 8 bytes,
516 it should not be necessary to merge the field class
517 into class[1]. As LEN > 8, subclass[1] is necessarily
518 different from AMD64_NO_CLASS. If subclass[1] is equal
519 to subclass[0], then the normal class[1]/subclass[1]
520 merging will take care of everything. For subclass[1]
521 to be different from subclass[0], I can only see the case
522 where we have a SSE/SSEUP or X87/X87UP pair, which both
523 use up all 16 bytes of the aggregate, and are already
524 handled just fine (because each portion sits on its own
526 class[1] = amd64_merge_classes (class[1], subclass[0]);
528 class[1] = amd64_merge_classes (class[1], subclass[1]);
532 /* 4. Then a post merger cleanup is done: */
534 /* Rule (a): If one of the classes is MEMORY, the whole argument is
536 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
537 class[0] = class[1] = AMD64_MEMORY;
539 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
541 if (class[0] == AMD64_SSEUP)
542 class[0] = AMD64_SSE;
543 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
544 class[1] = AMD64_SSE;
547 /* Classify TYPE, and store the result in CLASS. */
550 amd64_classify (struct type *type, enum amd64_reg_class class[2])
552 enum type_code code = TYPE_CODE (type);
553 int len = TYPE_LENGTH (type);
555 class[0] = class[1] = AMD64_NO_CLASS;
557 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
558 long, long long, and pointers are in the INTEGER class. Similarly,
559 range types, used by languages such as Ada, are also in the INTEGER
561 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
562 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
563 || code == TYPE_CODE_CHAR
564 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
565 && (len == 1 || len == 2 || len == 4 || len == 8))
566 class[0] = AMD64_INTEGER;
568 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
570 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
571 && (len == 4 || len == 8))
573 class[0] = AMD64_SSE;
575 /* Arguments of types __float128, _Decimal128 and __m128 are split into
576 two halves. The least significant ones belong to class SSE, the most
577 significant one to class SSEUP. */
578 else if (code == TYPE_CODE_DECFLOAT && len == 16)
579 /* FIXME: __float128, __m128. */
580 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
582 /* The 64-bit mantissa of arguments of type long double belongs to
583 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
585 else if (code == TYPE_CODE_FLT && len == 16)
586 /* Class X87 and X87UP. */
587 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
589 /* Arguments of complex T where T is one of the types float or
590 double get treated as if they are implemented as:
596 else if (code == TYPE_CODE_COMPLEX && len == 8)
597 class[0] = AMD64_SSE;
598 else if (code == TYPE_CODE_COMPLEX && len == 16)
599 class[0] = class[1] = AMD64_SSE;
601 /* A variable of type complex long double is classified as type
603 else if (code == TYPE_CODE_COMPLEX && len == 32)
604 class[0] = AMD64_COMPLEX_X87;
607 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
608 || code == TYPE_CODE_UNION)
609 amd64_classify_aggregate (type, class);
612 static enum return_value_convention
613 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
614 struct type *type, struct regcache *regcache,
615 gdb_byte *readbuf, const gdb_byte *writebuf)
617 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
618 enum amd64_reg_class class[2];
619 int len = TYPE_LENGTH (type);
620 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
621 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
626 gdb_assert (!(readbuf && writebuf));
627 gdb_assert (tdep->classify);
629 /* 1. Classify the return type with the classification algorithm. */
630 tdep->classify (type, class);
632 /* 2. If the type has class MEMORY, then the caller provides space
633 for the return value and passes the address of this storage in
634 %rdi as if it were the first argument to the function. In effect,
635 this address becomes a hidden first argument.
637 On return %rax will contain the address that has been passed in
638 by the caller in %rdi. */
639 if (class[0] == AMD64_MEMORY)
641 /* As indicated by the comment above, the ABI guarantees that we
642 can always find the return value just after the function has
649 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
650 read_memory (addr, readbuf, TYPE_LENGTH (type));
653 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
656 /* 8. If the class is COMPLEX_X87, the real part of the value is
657 returned in %st0 and the imaginary part in %st1. */
658 if (class[0] == AMD64_COMPLEX_X87)
662 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
663 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
668 i387_return_value (gdbarch, regcache);
669 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
670 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
672 /* Fix up the tag word such that both %st(0) and %st(1) are
674 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
677 return RETURN_VALUE_REGISTER_CONVENTION;
680 gdb_assert (class[1] != AMD64_MEMORY);
681 gdb_assert (len <= 16);
683 for (i = 0; len > 0; i++, len -= 8)
691 /* 3. If the class is INTEGER, the next available register
692 of the sequence %rax, %rdx is used. */
693 regnum = integer_regnum[integer_reg++];
697 /* 4. If the class is SSE, the next available SSE register
698 of the sequence %xmm0, %xmm1 is used. */
699 regnum = sse_regnum[sse_reg++];
703 /* 5. If the class is SSEUP, the eightbyte is passed in the
704 upper half of the last used SSE register. */
705 gdb_assert (sse_reg > 0);
706 regnum = sse_regnum[sse_reg - 1];
711 /* 6. If the class is X87, the value is returned on the X87
712 stack in %st0 as 80-bit x87 number. */
713 regnum = AMD64_ST0_REGNUM;
715 i387_return_value (gdbarch, regcache);
719 /* 7. If the class is X87UP, the value is returned together
720 with the previous X87 value in %st0. */
721 gdb_assert (i > 0 && class[0] == AMD64_X87);
722 regnum = AMD64_ST0_REGNUM;
731 gdb_assert (!"Unexpected register class.");
734 gdb_assert (regnum != -1);
737 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
740 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
744 return RETURN_VALUE_REGISTER_CONVENTION;
749 amd64_push_arguments (struct regcache *regcache, int nargs,
750 struct value **args, CORE_ADDR sp, int struct_return)
752 struct gdbarch *gdbarch = get_regcache_arch (regcache);
753 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
754 int *integer_regs = tdep->call_dummy_integer_regs;
755 int num_integer_regs = tdep->call_dummy_num_integer_regs;
757 static int sse_regnum[] =
759 /* %xmm0 ... %xmm7 */
760 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
761 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
762 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
763 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
765 struct value **stack_args = alloca (nargs * sizeof (struct value *));
766 /* An array that mirrors the stack_args array. For all arguments
767 that are passed by MEMORY, if that argument's address also needs
768 to be stored in a register, the ARG_ADDR_REGNO array will contain
769 that register number (or a negative value otherwise). */
770 int *arg_addr_regno = alloca (nargs * sizeof (int));
771 int num_stack_args = 0;
772 int num_elements = 0;
778 gdb_assert (tdep->classify);
780 /* Reserve a register for the "hidden" argument. */
784 for (i = 0; i < nargs; i++)
786 struct type *type = value_type (args[i]);
787 int len = TYPE_LENGTH (type);
788 enum amd64_reg_class class[2];
789 int needed_integer_regs = 0;
790 int needed_sse_regs = 0;
793 /* Classify argument. */
794 tdep->classify (type, class);
796 /* Calculate the number of integer and SSE registers needed for
798 for (j = 0; j < 2; j++)
800 if (class[j] == AMD64_INTEGER)
801 needed_integer_regs++;
802 else if (class[j] == AMD64_SSE)
806 /* Check whether enough registers are available, and if the
807 argument should be passed in registers at all. */
808 if (integer_reg + needed_integer_regs > num_integer_regs
809 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
810 || (needed_integer_regs == 0 && needed_sse_regs == 0))
812 /* The argument will be passed on the stack. */
813 num_elements += ((len + 7) / 8);
814 stack_args[num_stack_args] = args[i];
815 /* If this is an AMD64_MEMORY argument whose address must also
816 be passed in one of the integer registers, reserve that
817 register and associate this value to that register so that
818 we can store the argument address as soon as we know it. */
819 if (class[0] == AMD64_MEMORY
820 && tdep->memory_args_by_pointer
821 && integer_reg < tdep->call_dummy_num_integer_regs)
822 arg_addr_regno[num_stack_args] =
823 tdep->call_dummy_integer_regs[integer_reg++];
825 arg_addr_regno[num_stack_args] = -1;
830 /* The argument will be passed in registers. */
831 const gdb_byte *valbuf = value_contents (args[i]);
834 gdb_assert (len <= 16);
836 for (j = 0; len > 0; j++, len -= 8)
844 regnum = integer_regs[integer_reg++];
848 regnum = sse_regnum[sse_reg++];
852 gdb_assert (sse_reg > 0);
853 regnum = sse_regnum[sse_reg - 1];
858 gdb_assert (!"Unexpected register class.");
861 gdb_assert (regnum != -1);
862 memset (buf, 0, sizeof buf);
863 memcpy (buf, valbuf + j * 8, min (len, 8));
864 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
869 /* Allocate space for the arguments on the stack. */
870 sp -= num_elements * 8;
872 /* The psABI says that "The end of the input argument area shall be
873 aligned on a 16 byte boundary." */
876 /* Write out the arguments to the stack. */
877 for (i = 0; i < num_stack_args; i++)
879 struct type *type = value_type (stack_args[i]);
880 const gdb_byte *valbuf = value_contents (stack_args[i]);
881 CORE_ADDR arg_addr = sp + element * 8;
883 write_memory (arg_addr, valbuf, TYPE_LENGTH (type));
884 if (arg_addr_regno[i] >= 0)
886 /* We also need to store the address of that argument in
887 the given register. */
889 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
891 store_unsigned_integer (buf, 8, byte_order, arg_addr);
892 regcache_cooked_write (regcache, arg_addr_regno[i], buf);
894 element += ((TYPE_LENGTH (type) + 7) / 8);
897 /* The psABI says that "For calls that may call functions that use
898 varargs or stdargs (prototype-less calls or calls to functions
899 containing ellipsis (...) in the declaration) %al is used as
900 hidden argument to specify the number of SSE registers used. */
901 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
906 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
907 struct regcache *regcache, CORE_ADDR bp_addr,
908 int nargs, struct value **args, CORE_ADDR sp,
909 int struct_return, CORE_ADDR struct_addr)
911 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
912 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
915 /* Pass arguments. */
916 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
918 /* Pass "hidden" argument". */
921 /* The "hidden" argument is passed throught the first argument
923 const int arg_regnum = tdep->call_dummy_integer_regs[0];
925 store_unsigned_integer (buf, 8, byte_order, struct_addr);
926 regcache_cooked_write (regcache, arg_regnum, buf);
929 /* Store return address. */
931 store_unsigned_integer (buf, 8, byte_order, bp_addr);
932 write_memory (sp, buf, 8);
934 /* Finally, update the stack pointer... */
935 store_unsigned_integer (buf, 8, byte_order, sp);
936 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
938 /* ...and fake a frame pointer. */
939 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
944 /* Displaced instruction handling. */
946 /* A partially decoded instruction.
947 This contains enough details for displaced stepping purposes. */
951 /* The number of opcode bytes. */
953 /* The offset of the rex prefix or -1 if not present. */
955 /* The offset to the first opcode byte. */
957 /* The offset to the modrm byte or -1 if not present. */
960 /* The raw instruction. */
964 struct displaced_step_closure
966 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
971 /* Details of the instruction. */
972 struct amd64_insn insn_details;
974 /* Amount of space allocated to insn_buf. */
977 /* The possibly modified insn.
978 This is a variable-length field. */
979 gdb_byte insn_buf[1];
982 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
983 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
984 at which point delete these in favor of libopcodes' versions). */
986 static const unsigned char onebyte_has_modrm[256] = {
987 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
988 /* ------------------------------- */
989 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
990 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
991 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
992 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
993 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
994 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
995 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
996 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
997 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
998 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
999 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1000 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1001 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1002 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1003 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1004 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1005 /* ------------------------------- */
1006 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1009 static const unsigned char twobyte_has_modrm[256] = {
1010 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1011 /* ------------------------------- */
1012 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1013 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1014 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1015 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1016 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1017 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1018 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1019 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1020 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1021 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1022 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1023 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1024 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1025 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1026 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1027 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1028 /* ------------------------------- */
1029 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1032 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1035 rex_prefix_p (gdb_byte pfx)
1037 return REX_PREFIX_P (pfx);
1040 /* Skip the legacy instruction prefixes in INSN.
1041 We assume INSN is properly sentineled so we don't have to worry
1042 about falling off the end of the buffer. */
1045 amd64_skip_prefixes (gdb_byte *insn)
1051 case DATA_PREFIX_OPCODE:
1052 case ADDR_PREFIX_OPCODE:
1053 case CS_PREFIX_OPCODE:
1054 case DS_PREFIX_OPCODE:
1055 case ES_PREFIX_OPCODE:
1056 case FS_PREFIX_OPCODE:
1057 case GS_PREFIX_OPCODE:
1058 case SS_PREFIX_OPCODE:
1059 case LOCK_PREFIX_OPCODE:
1060 case REPE_PREFIX_OPCODE:
1061 case REPNE_PREFIX_OPCODE:
1073 /* Return an integer register (other than RSP) that is unused as an input
1075 In order to not require adding a rex prefix if the insn doesn't already
1076 have one, the result is restricted to RAX ... RDI, sans RSP.
1077 The register numbering of the result follows architecture ordering,
1081 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1083 /* 1 bit for each reg */
1084 int used_regs_mask = 0;
1086 /* There can be at most 3 int regs used as inputs in an insn, and we have
1087 7 to choose from (RAX ... RDI, sans RSP).
1088 This allows us to take a conservative approach and keep things simple.
1089 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1090 that implicitly specify RAX. */
1093 used_regs_mask |= 1 << EAX_REG_NUM;
1094 /* Similarily avoid RDX, implicit operand in divides. */
1095 used_regs_mask |= 1 << EDX_REG_NUM;
1097 used_regs_mask |= 1 << ESP_REG_NUM;
1099 /* If the opcode is one byte long and there's no ModRM byte,
1100 assume the opcode specifies a register. */
1101 if (details->opcode_len == 1 && details->modrm_offset == -1)
1102 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1104 /* Mark used regs in the modrm/sib bytes. */
1105 if (details->modrm_offset != -1)
1107 int modrm = details->raw_insn[details->modrm_offset];
1108 int mod = MODRM_MOD_FIELD (modrm);
1109 int reg = MODRM_REG_FIELD (modrm);
1110 int rm = MODRM_RM_FIELD (modrm);
1111 int have_sib = mod != 3 && rm == 4;
1113 /* Assume the reg field of the modrm byte specifies a register. */
1114 used_regs_mask |= 1 << reg;
1118 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1119 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1120 used_regs_mask |= 1 << base;
1121 used_regs_mask |= 1 << idx;
1125 used_regs_mask |= 1 << rm;
1129 gdb_assert (used_regs_mask < 256);
1130 gdb_assert (used_regs_mask != 255);
1132 /* Finally, find a free reg. */
1136 for (i = 0; i < 8; ++i)
1138 if (! (used_regs_mask & (1 << i)))
1142 /* We shouldn't get here. */
1143 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1147 /* Extract the details of INSN that we need. */
1150 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1152 gdb_byte *start = insn;
1155 details->raw_insn = insn;
1157 details->opcode_len = -1;
1158 details->rex_offset = -1;
1159 details->opcode_offset = -1;
1160 details->modrm_offset = -1;
1162 /* Skip legacy instruction prefixes. */
1163 insn = amd64_skip_prefixes (insn);
1165 /* Skip REX instruction prefix. */
1166 if (rex_prefix_p (*insn))
1168 details->rex_offset = insn - start;
1172 details->opcode_offset = insn - start;
1174 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1176 /* Two or three-byte opcode. */
1178 need_modrm = twobyte_has_modrm[*insn];
1180 /* Check for three-byte opcode. */
1190 details->opcode_len = 3;
1193 details->opcode_len = 2;
1199 /* One-byte opcode. */
1200 need_modrm = onebyte_has_modrm[*insn];
1201 details->opcode_len = 1;
1207 details->modrm_offset = insn - start;
1211 /* Update %rip-relative addressing in INSN.
1213 %rip-relative addressing only uses a 32-bit displacement.
1214 32 bits is not enough to be guaranteed to cover the distance between where
1215 the real instruction is and where its copy is.
1216 Convert the insn to use base+disp addressing.
1217 We set base = pc + insn_length so we can leave disp unchanged. */
1220 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1221 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1223 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1224 const struct amd64_insn *insn_details = &dsc->insn_details;
1225 int modrm_offset = insn_details->modrm_offset;
1226 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1230 int arch_tmp_regno, tmp_regno;
1231 ULONGEST orig_value;
1233 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1236 /* Compute the rip-relative address. */
1237 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1238 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1239 dsc->max_len, from);
1240 rip_base = from + insn_length;
1242 /* We need a register to hold the address.
1243 Pick one not used in the insn.
1244 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1245 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1246 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1248 /* REX.B should be unset as we were using rip-relative addressing,
1249 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1250 if (insn_details->rex_offset != -1)
1251 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1253 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1254 dsc->tmp_regno = tmp_regno;
1255 dsc->tmp_save = orig_value;
1258 /* Convert the ModRM field to be base+disp. */
1259 dsc->insn_buf[modrm_offset] &= ~0xc7;
1260 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1262 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1264 if (debug_displaced)
1265 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1266 "displaced: using temp reg %d, old value %s, new value %s\n",
1267 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1268 paddress (gdbarch, rip_base));
1272 fixup_displaced_copy (struct gdbarch *gdbarch,
1273 struct displaced_step_closure *dsc,
1274 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1276 const struct amd64_insn *details = &dsc->insn_details;
1278 if (details->modrm_offset != -1)
1280 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1282 if ((modrm & 0xc7) == 0x05)
1284 /* The insn uses rip-relative addressing.
1286 fixup_riprel (gdbarch, dsc, from, to, regs);
1291 struct displaced_step_closure *
1292 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1293 CORE_ADDR from, CORE_ADDR to,
1294 struct regcache *regs)
1296 int len = gdbarch_max_insn_length (gdbarch);
1297 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1298 continually watch for running off the end of the buffer. */
1299 int fixup_sentinel_space = len;
1300 struct displaced_step_closure *dsc =
1301 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1302 gdb_byte *buf = &dsc->insn_buf[0];
1303 struct amd64_insn *details = &dsc->insn_details;
1306 dsc->max_len = len + fixup_sentinel_space;
1308 read_memory (from, buf, len);
1310 /* Set up the sentinel space so we don't have to worry about running
1311 off the end of the buffer. An excessive number of leading prefixes
1312 could otherwise cause this. */
1313 memset (buf + len, 0, fixup_sentinel_space);
1315 amd64_get_insn_details (buf, details);
1317 /* GDB may get control back after the insn after the syscall.
1318 Presumably this is a kernel bug.
1319 If this is a syscall, make sure there's a nop afterwards. */
1323 if (amd64_syscall_p (details, &syscall_length))
1324 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1327 /* Modify the insn to cope with the address where it will be executed from.
1328 In particular, handle any rip-relative addressing. */
1329 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1331 write_memory (to, buf, len);
1333 if (debug_displaced)
1335 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1336 paddress (gdbarch, from), paddress (gdbarch, to));
1337 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1344 amd64_absolute_jmp_p (const struct amd64_insn *details)
1346 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1348 if (insn[0] == 0xff)
1350 /* jump near, absolute indirect (/4) */
1351 if ((insn[1] & 0x38) == 0x20)
1354 /* jump far, absolute indirect (/5) */
1355 if ((insn[1] & 0x38) == 0x28)
1363 amd64_absolute_call_p (const struct amd64_insn *details)
1365 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1367 if (insn[0] == 0xff)
1369 /* Call near, absolute indirect (/2) */
1370 if ((insn[1] & 0x38) == 0x10)
1373 /* Call far, absolute indirect (/3) */
1374 if ((insn[1] & 0x38) == 0x18)
1382 amd64_ret_p (const struct amd64_insn *details)
1384 /* NOTE: gcc can emit "repz ; ret". */
1385 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1389 case 0xc2: /* ret near, pop N bytes */
1390 case 0xc3: /* ret near */
1391 case 0xca: /* ret far, pop N bytes */
1392 case 0xcb: /* ret far */
1393 case 0xcf: /* iret */
1402 amd64_call_p (const struct amd64_insn *details)
1404 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1406 if (amd64_absolute_call_p (details))
1409 /* call near, relative */
1410 if (insn[0] == 0xe8)
1416 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1417 length in bytes. Otherwise, return zero. */
1420 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1422 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1424 if (insn[0] == 0x0f && insn[1] == 0x05)
1433 /* Fix up the state of registers and memory after having single-stepped
1434 a displaced instruction. */
1437 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1438 struct displaced_step_closure *dsc,
1439 CORE_ADDR from, CORE_ADDR to,
1440 struct regcache *regs)
1442 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1443 /* The offset we applied to the instruction's address. */
1444 ULONGEST insn_offset = to - from;
1445 gdb_byte *insn = dsc->insn_buf;
1446 const struct amd64_insn *insn_details = &dsc->insn_details;
1448 if (debug_displaced)
1449 fprintf_unfiltered (gdb_stdlog,
1450 "displaced: fixup (%s, %s), "
1451 "insn = 0x%02x 0x%02x ...\n",
1452 paddress (gdbarch, from), paddress (gdbarch, to),
1455 /* If we used a tmp reg, restore it. */
1459 if (debug_displaced)
1460 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1461 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1462 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1465 /* The list of issues to contend with here is taken from
1466 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1467 Yay for Free Software! */
1469 /* Relocate the %rip back to the program's instruction stream,
1472 /* Except in the case of absolute or indirect jump or call
1473 instructions, or a return instruction, the new rip is relative to
1474 the displaced instruction; make it relative to the original insn.
1475 Well, signal handler returns don't need relocation either, but we use the
1476 value of %rip to recognize those; see below. */
1477 if (! amd64_absolute_jmp_p (insn_details)
1478 && ! amd64_absolute_call_p (insn_details)
1479 && ! amd64_ret_p (insn_details))
1484 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1486 /* A signal trampoline system call changes the %rip, resuming
1487 execution of the main program after the signal handler has
1488 returned. That makes them like 'return' instructions; we
1489 shouldn't relocate %rip.
1491 But most system calls don't, and we do need to relocate %rip.
1493 Our heuristic for distinguishing these cases: if stepping
1494 over the system call instruction left control directly after
1495 the instruction, the we relocate --- control almost certainly
1496 doesn't belong in the displaced copy. Otherwise, we assume
1497 the instruction has put control where it belongs, and leave
1498 it unrelocated. Goodness help us if there are PC-relative
1500 if (amd64_syscall_p (insn_details, &insn_len)
1501 && orig_rip != to + insn_len
1502 /* GDB can get control back after the insn after the syscall.
1503 Presumably this is a kernel bug.
1504 Fixup ensures its a nop, we add one to the length for it. */
1505 && orig_rip != to + insn_len + 1)
1507 if (debug_displaced)
1508 fprintf_unfiltered (gdb_stdlog,
1509 "displaced: syscall changed %%rip; "
1510 "not relocating\n");
1514 ULONGEST rip = orig_rip - insn_offset;
1516 /* If we just stepped over a breakpoint insn, we don't backup
1517 the pc on purpose; this is to match behaviour without
1520 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1522 if (debug_displaced)
1523 fprintf_unfiltered (gdb_stdlog,
1525 "relocated %%rip from %s to %s\n",
1526 paddress (gdbarch, orig_rip),
1527 paddress (gdbarch, rip));
1531 /* If the instruction was PUSHFL, then the TF bit will be set in the
1532 pushed value, and should be cleared. We'll leave this for later,
1533 since GDB already messes up the TF flag when stepping over a
1536 /* If the instruction was a call, the return address now atop the
1537 stack is the address following the copied instruction. We need
1538 to make it the address following the original instruction. */
1539 if (amd64_call_p (insn_details))
1543 const ULONGEST retaddr_len = 8;
1545 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1546 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1547 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
1548 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1550 if (debug_displaced)
1551 fprintf_unfiltered (gdb_stdlog,
1552 "displaced: relocated return addr at %s "
1554 paddress (gdbarch, rsp),
1555 paddress (gdbarch, retaddr));
1559 /* If the instruction INSN uses RIP-relative addressing, return the
1560 offset into the raw INSN where the displacement to be adjusted is
1561 found. Returns 0 if the instruction doesn't use RIP-relative
1565 rip_relative_offset (struct amd64_insn *insn)
1567 if (insn->modrm_offset != -1)
1569 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1571 if ((modrm & 0xc7) == 0x05)
1573 /* The displacement is found right after the ModRM byte. */
1574 return insn->modrm_offset + 1;
1582 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1584 target_write_memory (*to, buf, len);
1589 amd64_relocate_instruction (struct gdbarch *gdbarch,
1590 CORE_ADDR *to, CORE_ADDR oldloc)
1592 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1593 int len = gdbarch_max_insn_length (gdbarch);
1594 /* Extra space for sentinels. */
1595 int fixup_sentinel_space = len;
1596 gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1597 struct amd64_insn insn_details;
1599 LONGEST rel32, newrel;
1603 read_memory (oldloc, buf, len);
1605 /* Set up the sentinel space so we don't have to worry about running
1606 off the end of the buffer. An excessive number of leading prefixes
1607 could otherwise cause this. */
1608 memset (buf + len, 0, fixup_sentinel_space);
1611 amd64_get_insn_details (insn, &insn_details);
1613 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1615 /* Skip legacy instruction prefixes. */
1616 insn = amd64_skip_prefixes (insn);
1618 /* Adjust calls with 32-bit relative addresses as push/jump, with
1619 the address pushed being the location where the original call in
1620 the user program would return to. */
1621 if (insn[0] == 0xe8)
1623 gdb_byte push_buf[16];
1624 unsigned int ret_addr;
1626 /* Where "ret" in the original code will return to. */
1627 ret_addr = oldloc + insn_length;
1628 push_buf[0] = 0x68; /* pushq $... */
1629 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1630 /* Push the push. */
1631 append_insns (to, 5, push_buf);
1633 /* Convert the relative call to a relative jump. */
1636 /* Adjust the destination offset. */
1637 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1638 newrel = (oldloc - *to) + rel32;
1639 store_signed_integer (insn + 1, 4, byte_order, newrel);
1641 if (debug_displaced)
1642 fprintf_unfiltered (gdb_stdlog,
1643 "Adjusted insn rel32=%s at %s to"
1644 " rel32=%s at %s\n",
1645 hex_string (rel32), paddress (gdbarch, oldloc),
1646 hex_string (newrel), paddress (gdbarch, *to));
1648 /* Write the adjusted jump into its displaced location. */
1649 append_insns (to, 5, insn);
1653 offset = rip_relative_offset (&insn_details);
1656 /* Adjust jumps with 32-bit relative addresses. Calls are
1657 already handled above. */
1658 if (insn[0] == 0xe9)
1660 /* Adjust conditional jumps. */
1661 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1667 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1668 newrel = (oldloc - *to) + rel32;
1669 store_signed_integer (insn + offset, 4, byte_order, newrel);
1670 if (debug_displaced)
1671 fprintf_unfiltered (gdb_stdlog,
1672 "Adjusted insn rel32=%s at %s to"
1673 " rel32=%s at %s\n",
1674 hex_string (rel32), paddress (gdbarch, oldloc),
1675 hex_string (newrel), paddress (gdbarch, *to));
1678 /* Write the adjusted instruction into its displaced location. */
1679 append_insns (to, insn_length, buf);
1683 /* The maximum number of saved registers. This should include %rip. */
1684 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1686 struct amd64_frame_cache
1691 CORE_ADDR sp_offset;
1694 /* Saved registers. */
1695 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1699 /* Do we have a frame? */
1703 /* Initialize a frame cache. */
1706 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1713 cache->sp_offset = -8;
1716 /* Saved registers. We initialize these to -1 since zero is a valid
1717 offset (that's where %rbp is supposed to be stored).
1718 The values start out as being offsets, and are later converted to
1719 addresses (at which point -1 is interpreted as an address, still meaning
1721 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1722 cache->saved_regs[i] = -1;
1723 cache->saved_sp = 0;
1724 cache->saved_sp_reg = -1;
1726 /* Frameless until proven otherwise. */
1727 cache->frameless_p = 1;
1730 /* Allocate and initialize a frame cache. */
1732 static struct amd64_frame_cache *
1733 amd64_alloc_frame_cache (void)
1735 struct amd64_frame_cache *cache;
1737 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1738 amd64_init_frame_cache (cache);
1742 /* GCC 4.4 and later, can put code in the prologue to realign the
1743 stack pointer. Check whether PC points to such code, and update
1744 CACHE accordingly. Return the first instruction after the code
1745 sequence or CURRENT_PC, whichever is smaller. If we don't
1746 recognize the code, return PC. */
1749 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1750 struct amd64_frame_cache *cache)
1752 /* There are 2 code sequences to re-align stack before the frame
1755 1. Use a caller-saved saved register:
1761 2. Use a callee-saved saved register:
1768 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1770 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1771 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1776 int offset, offset_and;
1778 if (target_read_memory (pc, buf, sizeof buf))
1781 /* Check caller-saved saved register. The first instruction has
1782 to be "leaq 8(%rsp), %reg". */
1783 if ((buf[0] & 0xfb) == 0x48
1788 /* MOD must be binary 10 and R/M must be binary 100. */
1789 if ((buf[2] & 0xc7) != 0x44)
1792 /* REG has register number. */
1793 reg = (buf[2] >> 3) & 7;
1795 /* Check the REX.R bit. */
1803 /* Check callee-saved saved register. The first instruction
1804 has to be "pushq %reg". */
1806 if ((buf[0] & 0xf8) == 0x50)
1808 else if ((buf[0] & 0xf6) == 0x40
1809 && (buf[1] & 0xf8) == 0x50)
1811 /* Check the REX.B bit. */
1812 if ((buf[0] & 1) != 0)
1821 reg += buf[offset] & 0x7;
1825 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1826 if ((buf[offset] & 0xfb) != 0x48
1827 || buf[offset + 1] != 0x8d
1828 || buf[offset + 3] != 0x24
1829 || buf[offset + 4] != 0x10)
1832 /* MOD must be binary 10 and R/M must be binary 100. */
1833 if ((buf[offset + 2] & 0xc7) != 0x44)
1836 /* REG has register number. */
1837 r = (buf[offset + 2] >> 3) & 7;
1839 /* Check the REX.R bit. */
1840 if (buf[offset] == 0x4c)
1843 /* Registers in pushq and leaq have to be the same. */
1850 /* Rigister can't be %rsp nor %rbp. */
1851 if (reg == 4 || reg == 5)
1854 /* The next instruction has to be "andq $-XXX, %rsp". */
1855 if (buf[offset] != 0x48
1856 || buf[offset + 2] != 0xe4
1857 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1860 offset_and = offset;
1861 offset += buf[offset + 1] == 0x81 ? 7 : 4;
1863 /* The next instruction has to be "pushq -8(%reg)". */
1865 if (buf[offset] == 0xff)
1867 else if ((buf[offset] & 0xf6) == 0x40
1868 && buf[offset + 1] == 0xff)
1870 /* Check the REX.B bit. */
1871 if ((buf[offset] & 0x1) != 0)
1878 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1880 if (buf[offset + 1] != 0xf8
1881 || (buf[offset] & 0xf8) != 0x70)
1884 /* R/M has register. */
1885 r += buf[offset] & 7;
1887 /* Registers in leaq and pushq have to be the same. */
1891 if (current_pc > pc + offset_and)
1892 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
1894 return min (pc + offset + 2, current_pc);
1897 /* Similar to amd64_analyze_stack_align for x32. */
1900 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1901 struct amd64_frame_cache *cache)
1903 /* There are 2 code sequences to re-align stack before the frame
1906 1. Use a caller-saved saved register:
1914 [addr32] leal 8(%rsp), %reg
1916 [addr32] pushq -8(%reg)
1918 2. Use a callee-saved saved register:
1928 [addr32] leal 16(%rsp), %reg
1930 [addr32] pushq -8(%reg)
1932 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1934 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1935 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1937 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1939 0x83 0xe4 0xf0 andl $-16, %esp
1940 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1945 int offset, offset_and;
1947 if (target_read_memory (pc, buf, sizeof buf))
1950 /* Skip optional addr32 prefix. */
1951 offset = buf[0] == 0x67 ? 1 : 0;
1953 /* Check caller-saved saved register. The first instruction has
1954 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
1955 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
1956 && buf[offset + 1] == 0x8d
1957 && buf[offset + 3] == 0x24
1958 && buf[offset + 4] == 0x8)
1960 /* MOD must be binary 10 and R/M must be binary 100. */
1961 if ((buf[offset + 2] & 0xc7) != 0x44)
1964 /* REG has register number. */
1965 reg = (buf[offset + 2] >> 3) & 7;
1967 /* Check the REX.R bit. */
1968 if ((buf[offset] & 0x4) != 0)
1975 /* Check callee-saved saved register. The first instruction
1976 has to be "pushq %reg". */
1978 if ((buf[offset] & 0xf6) == 0x40
1979 && (buf[offset + 1] & 0xf8) == 0x50)
1981 /* Check the REX.B bit. */
1982 if ((buf[offset] & 1) != 0)
1987 else if ((buf[offset] & 0xf8) != 0x50)
1991 reg += buf[offset] & 0x7;
1995 /* Skip optional addr32 prefix. */
1996 if (buf[offset] == 0x67)
1999 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2000 "leal 16(%rsp), %reg". */
2001 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2002 || buf[offset + 1] != 0x8d
2003 || buf[offset + 3] != 0x24
2004 || buf[offset + 4] != 0x10)
2007 /* MOD must be binary 10 and R/M must be binary 100. */
2008 if ((buf[offset + 2] & 0xc7) != 0x44)
2011 /* REG has register number. */
2012 r = (buf[offset + 2] >> 3) & 7;
2014 /* Check the REX.R bit. */
2015 if ((buf[offset] & 0x4) != 0)
2018 /* Registers in pushq and leaq have to be the same. */
2025 /* Rigister can't be %rsp nor %rbp. */
2026 if (reg == 4 || reg == 5)
2029 /* The next instruction may be "andq $-XXX, %rsp" or
2030 "andl $-XXX, %esp". */
2031 if (buf[offset] != 0x48)
2034 if (buf[offset + 2] != 0xe4
2035 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2038 offset_and = offset;
2039 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2041 /* Skip optional addr32 prefix. */
2042 if (buf[offset] == 0x67)
2045 /* The next instruction has to be "pushq -8(%reg)". */
2047 if (buf[offset] == 0xff)
2049 else if ((buf[offset] & 0xf6) == 0x40
2050 && buf[offset + 1] == 0xff)
2052 /* Check the REX.B bit. */
2053 if ((buf[offset] & 0x1) != 0)
2060 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2062 if (buf[offset + 1] != 0xf8
2063 || (buf[offset] & 0xf8) != 0x70)
2066 /* R/M has register. */
2067 r += buf[offset] & 7;
2069 /* Registers in leaq and pushq have to be the same. */
2073 if (current_pc > pc + offset_and)
2074 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2076 return min (pc + offset + 2, current_pc);
2079 /* Do a limited analysis of the prologue at PC and update CACHE
2080 accordingly. Bail out early if CURRENT_PC is reached. Return the
2081 address where the analysis stopped.
2083 We will handle only functions beginning with:
2086 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2088 or (for the X32 ABI):
2091 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2093 Any function that doesn't start with one of these sequences will be
2094 assumed to have no prologue and thus no valid frame pointer in
2098 amd64_analyze_prologue (struct gdbarch *gdbarch,
2099 CORE_ADDR pc, CORE_ADDR current_pc,
2100 struct amd64_frame_cache *cache)
2102 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2103 /* There are two variations of movq %rsp, %rbp. */
2104 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2105 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2106 /* Ditto for movl %esp, %ebp. */
2107 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2108 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2113 if (current_pc <= pc)
2116 if (gdbarch_ptr_bit (gdbarch) == 32)
2117 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2119 pc = amd64_analyze_stack_align (pc, current_pc, cache);
2121 op = read_memory_unsigned_integer (pc, 1, byte_order);
2123 if (op == 0x55) /* pushq %rbp */
2125 /* Take into account that we've executed the `pushq %rbp' that
2126 starts this instruction sequence. */
2127 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2128 cache->sp_offset += 8;
2130 /* If that's all, return now. */
2131 if (current_pc <= pc + 1)
2134 read_memory (pc + 1, buf, 3);
2136 /* Check for `movq %rsp, %rbp'. */
2137 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2138 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2140 /* OK, we actually have a frame. */
2141 cache->frameless_p = 0;
2145 /* For X32, also check for `movq %esp, %ebp'. */
2146 if (gdbarch_ptr_bit (gdbarch) == 32)
2148 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2149 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2151 /* OK, we actually have a frame. */
2152 cache->frameless_p = 0;
2163 /* Work around false termination of prologue - GCC PR debug/48827.
2165 START_PC is the first instruction of a function, PC is its minimal already
2166 determined advanced address. Function returns PC if it has nothing to do.
2170 <-- here is 0 lines advance - the false prologue end marker.
2171 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2172 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2173 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2174 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2175 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2176 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2177 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2178 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2182 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2184 struct symtab_and_line start_pc_sal, next_sal;
2185 gdb_byte buf[4 + 8 * 7];
2191 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2192 if (start_pc_sal.symtab == NULL
2193 || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6
2194 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2197 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2198 if (next_sal.line != start_pc_sal.line)
2201 /* START_PC can be from overlayed memory, ignored here. */
2202 if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2206 if (buf[0] != 0x84 || buf[1] != 0xc0)
2213 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2215 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2216 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2217 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2221 if ((buf[offset + 2] & 0xc0) == 0x40)
2223 /* 8-bit displacement. */
2227 else if ((buf[offset + 2] & 0xc0) == 0x80)
2229 /* 32-bit displacement. */
2237 if (offset - 4 != buf[3])
2240 return next_sal.end;
2243 /* Return PC of first real instruction. */
2246 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2248 struct amd64_frame_cache cache;
2250 CORE_ADDR func_addr;
2252 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2254 CORE_ADDR post_prologue_pc
2255 = skip_prologue_using_sal (gdbarch, func_addr);
2256 struct symtab *s = find_pc_symtab (func_addr);
2258 /* Clang always emits a line note before the prologue and another
2259 one after. We trust clang to emit usable line notes. */
2260 if (post_prologue_pc
2262 && s->producer != NULL
2263 && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
2264 return max (start_pc, post_prologue_pc);
2267 amd64_init_frame_cache (&cache);
2268 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2270 if (cache.frameless_p)
2273 return amd64_skip_xmm_prologue (pc, start_pc);
2277 /* Normal frames. */
2280 amd64_frame_cache_1 (struct frame_info *this_frame,
2281 struct amd64_frame_cache *cache)
2283 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2284 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2288 cache->pc = get_frame_func (this_frame);
2290 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2293 if (cache->frameless_p)
2295 /* We didn't find a valid frame. If we're at the start of a
2296 function, or somewhere half-way its prologue, the function's
2297 frame probably hasn't been fully setup yet. Try to
2298 reconstruct the base address for the stack frame by looking
2299 at the stack pointer. For truly "frameless" functions this
2302 if (cache->saved_sp_reg != -1)
2304 /* Stack pointer has been saved. */
2305 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2306 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2308 /* We're halfway aligning the stack. */
2309 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2310 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2312 /* This will be added back below. */
2313 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2317 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2318 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2324 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2325 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2328 /* Now that we have the base address for the stack frame we can
2329 calculate the value of %rsp in the calling frame. */
2330 cache->saved_sp = cache->base + 16;
2332 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2333 frame we find it at the same offset from the reconstructed base
2334 address. If we're halfway aligning the stack, %rip is handled
2335 differently (see above). */
2336 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2337 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2339 /* Adjust all the saved registers such that they contain addresses
2340 instead of offsets. */
2341 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2342 if (cache->saved_regs[i] != -1)
2343 cache->saved_regs[i] += cache->base;
2348 static struct amd64_frame_cache *
2349 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2351 volatile struct gdb_exception ex;
2352 struct amd64_frame_cache *cache;
2357 cache = amd64_alloc_frame_cache ();
2358 *this_cache = cache;
2360 TRY_CATCH (ex, RETURN_MASK_ERROR)
2362 amd64_frame_cache_1 (this_frame, cache);
2364 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2365 throw_exception (ex);
2370 static enum unwind_stop_reason
2371 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2374 struct amd64_frame_cache *cache =
2375 amd64_frame_cache (this_frame, this_cache);
2378 return UNWIND_UNAVAILABLE;
2380 /* This marks the outermost frame. */
2381 if (cache->base == 0)
2382 return UNWIND_OUTERMOST;
2384 return UNWIND_NO_REASON;
2388 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2389 struct frame_id *this_id)
2391 struct amd64_frame_cache *cache =
2392 amd64_frame_cache (this_frame, this_cache);
2397 /* This marks the outermost frame. */
2398 if (cache->base == 0)
2401 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2404 static struct value *
2405 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2408 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2409 struct amd64_frame_cache *cache =
2410 amd64_frame_cache (this_frame, this_cache);
2412 gdb_assert (regnum >= 0);
2414 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2415 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2417 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2418 return frame_unwind_got_memory (this_frame, regnum,
2419 cache->saved_regs[regnum]);
2421 return frame_unwind_got_register (this_frame, regnum, regnum);
2424 static const struct frame_unwind amd64_frame_unwind =
2427 amd64_frame_unwind_stop_reason,
2428 amd64_frame_this_id,
2429 amd64_frame_prev_register,
2431 default_frame_sniffer
2434 /* Generate a bytecode expression to get the value of the saved PC. */
2437 amd64_gen_return_address (struct gdbarch *gdbarch,
2438 struct agent_expr *ax, struct axs_value *value,
2441 /* The following sequence assumes the traditional use of the base
2443 ax_reg (ax, AMD64_RBP_REGNUM);
2445 ax_simple (ax, aop_add);
2446 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2447 value->kind = axs_lvalue_memory;
2451 /* Signal trampolines. */
2453 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2454 64-bit variants. This would require using identical frame caches
2455 on both platforms. */
2457 static struct amd64_frame_cache *
2458 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2460 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2461 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2462 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2463 volatile struct gdb_exception ex;
2464 struct amd64_frame_cache *cache;
2472 cache = amd64_alloc_frame_cache ();
2474 TRY_CATCH (ex, RETURN_MASK_ERROR)
2476 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2477 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2479 addr = tdep->sigcontext_addr (this_frame);
2480 gdb_assert (tdep->sc_reg_offset);
2481 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2482 for (i = 0; i < tdep->sc_num_regs; i++)
2483 if (tdep->sc_reg_offset[i] != -1)
2484 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2488 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2489 throw_exception (ex);
2491 *this_cache = cache;
2495 static enum unwind_stop_reason
2496 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2499 struct amd64_frame_cache *cache =
2500 amd64_sigtramp_frame_cache (this_frame, this_cache);
2503 return UNWIND_UNAVAILABLE;
2505 return UNWIND_NO_REASON;
2509 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2510 void **this_cache, struct frame_id *this_id)
2512 struct amd64_frame_cache *cache =
2513 amd64_sigtramp_frame_cache (this_frame, this_cache);
2518 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2521 static struct value *
2522 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2523 void **this_cache, int regnum)
2525 /* Make sure we've initialized the cache. */
2526 amd64_sigtramp_frame_cache (this_frame, this_cache);
2528 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2532 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2533 struct frame_info *this_frame,
2536 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2538 /* We shouldn't even bother if we don't have a sigcontext_addr
2540 if (tdep->sigcontext_addr == NULL)
2543 if (tdep->sigtramp_p != NULL)
2545 if (tdep->sigtramp_p (this_frame))
2549 if (tdep->sigtramp_start != 0)
2551 CORE_ADDR pc = get_frame_pc (this_frame);
2553 gdb_assert (tdep->sigtramp_end != 0);
2554 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2561 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2564 amd64_sigtramp_frame_unwind_stop_reason,
2565 amd64_sigtramp_frame_this_id,
2566 amd64_sigtramp_frame_prev_register,
2568 amd64_sigtramp_frame_sniffer
2573 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2575 struct amd64_frame_cache *cache =
2576 amd64_frame_cache (this_frame, this_cache);
2581 static const struct frame_base amd64_frame_base =
2583 &amd64_frame_unwind,
2584 amd64_frame_base_address,
2585 amd64_frame_base_address,
2586 amd64_frame_base_address
2589 /* Normal frames, but in a function epilogue. */
2591 /* The epilogue is defined here as the 'ret' instruction, which will
2592 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2593 the function's stack frame. */
2596 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2599 struct symtab *symtab;
2601 symtab = find_pc_symtab (pc);
2602 if (symtab && symtab->epilogue_unwind_valid)
2605 if (target_read_memory (pc, &insn, 1))
2606 return 0; /* Can't read memory at pc. */
2608 if (insn != 0xc3) /* 'ret' instruction. */
2615 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2616 struct frame_info *this_frame,
2617 void **this_prologue_cache)
2619 if (frame_relative_level (this_frame) == 0)
2620 return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
2621 get_frame_pc (this_frame));
2626 static struct amd64_frame_cache *
2627 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2629 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2630 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2631 volatile struct gdb_exception ex;
2632 struct amd64_frame_cache *cache;
2638 cache = amd64_alloc_frame_cache ();
2639 *this_cache = cache;
2641 TRY_CATCH (ex, RETURN_MASK_ERROR)
2643 /* Cache base will be %esp plus cache->sp_offset (-8). */
2644 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2645 cache->base = extract_unsigned_integer (buf, 8,
2646 byte_order) + cache->sp_offset;
2648 /* Cache pc will be the frame func. */
2649 cache->pc = get_frame_pc (this_frame);
2651 /* The saved %esp will be at cache->base plus 16. */
2652 cache->saved_sp = cache->base + 16;
2654 /* The saved %eip will be at cache->base plus 8. */
2655 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2659 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2660 throw_exception (ex);
2665 static enum unwind_stop_reason
2666 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2669 struct amd64_frame_cache *cache
2670 = amd64_epilogue_frame_cache (this_frame, this_cache);
2673 return UNWIND_UNAVAILABLE;
2675 return UNWIND_NO_REASON;
2679 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2681 struct frame_id *this_id)
2683 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2689 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2692 static const struct frame_unwind amd64_epilogue_frame_unwind =
2695 amd64_epilogue_frame_unwind_stop_reason,
2696 amd64_epilogue_frame_this_id,
2697 amd64_frame_prev_register,
2699 amd64_epilogue_frame_sniffer
2702 static struct frame_id
2703 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2707 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2709 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2712 /* 16 byte align the SP per frame requirements. */
2715 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2717 return sp & -(CORE_ADDR)16;
2721 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2722 in the floating-point register set REGSET to register cache
2723 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2726 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2727 int regnum, const void *fpregs, size_t len)
2729 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2731 gdb_assert (len == tdep->sizeof_fpregset);
2732 amd64_supply_fxsave (regcache, regnum, fpregs);
2735 /* Collect register REGNUM from the register cache REGCACHE and store
2736 it in the buffer specified by FPREGS and LEN as described by the
2737 floating-point register set REGSET. If REGNUM is -1, do this for
2738 all registers in REGSET. */
2741 amd64_collect_fpregset (const struct regset *regset,
2742 const struct regcache *regcache,
2743 int regnum, void *fpregs, size_t len)
2745 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2747 gdb_assert (len == tdep->sizeof_fpregset);
2748 amd64_collect_fxsave (regcache, regnum, fpregs);
2751 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2754 amd64_supply_xstateregset (const struct regset *regset,
2755 struct regcache *regcache, int regnum,
2756 const void *xstateregs, size_t len)
2758 amd64_supply_xsave (regcache, regnum, xstateregs);
2761 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2764 amd64_collect_xstateregset (const struct regset *regset,
2765 const struct regcache *regcache,
2766 int regnum, void *xstateregs, size_t len)
2768 amd64_collect_xsave (regcache, regnum, xstateregs, 1);
2771 /* Return the appropriate register set for the core section identified
2772 by SECT_NAME and SECT_SIZE. */
2774 static const struct regset *
2775 amd64_regset_from_core_section (struct gdbarch *gdbarch,
2776 const char *sect_name, size_t sect_size)
2778 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2780 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2782 if (tdep->fpregset == NULL)
2783 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
2784 amd64_collect_fpregset);
2786 return tdep->fpregset;
2789 if (strcmp (sect_name, ".reg-xstate") == 0)
2791 if (tdep->xstateregset == NULL)
2792 tdep->xstateregset = regset_alloc (gdbarch,
2793 amd64_supply_xstateregset,
2794 amd64_collect_xstateregset);
2796 return tdep->xstateregset;
2799 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
2803 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2804 %rdi. We expect its value to be a pointer to the jmp_buf structure
2805 from which we extract the address that we will land at. This
2806 address is copied into PC. This routine returns non-zero on
2810 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2814 struct gdbarch *gdbarch = get_frame_arch (frame);
2815 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2816 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2818 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2819 longjmp will land. */
2820 if (jb_pc_offset == -1)
2823 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2824 jb_addr= extract_typed_address
2825 (buf, builtin_type (gdbarch)->builtin_data_ptr);
2826 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2829 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2834 static const int amd64_record_regmap[] =
2836 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2837 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2838 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2839 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2840 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2841 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2845 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2847 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2848 const struct target_desc *tdesc = info.target_desc;
2850 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2851 floating-point registers. */
2852 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2854 if (! tdesc_has_registers (tdesc))
2855 tdesc = tdesc_amd64;
2856 tdep->tdesc = tdesc;
2858 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2859 tdep->register_names = amd64_register_names;
2861 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2863 tdep->ymmh_register_names = amd64_ymmh_names;
2864 tdep->num_ymm_regs = 16;
2865 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
2868 tdep->num_byte_regs = 20;
2869 tdep->num_word_regs = 16;
2870 tdep->num_dword_regs = 16;
2871 /* Avoid wiring in the MMX registers for now. */
2872 tdep->num_mmx_regs = 0;
2874 set_gdbarch_pseudo_register_read_value (gdbarch,
2875 amd64_pseudo_register_read_value);
2876 set_gdbarch_pseudo_register_write (gdbarch,
2877 amd64_pseudo_register_write);
2879 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
2881 /* AMD64 has an FPU and 16 SSE registers. */
2882 tdep->st0_regnum = AMD64_ST0_REGNUM;
2883 tdep->num_xmm_regs = 16;
2885 /* This is what all the fuss is about. */
2886 set_gdbarch_long_bit (gdbarch, 64);
2887 set_gdbarch_long_long_bit (gdbarch, 64);
2888 set_gdbarch_ptr_bit (gdbarch, 64);
2890 /* In contrast to the i386, on AMD64 a `long double' actually takes
2891 up 128 bits, even though it's still based on the i387 extended
2892 floating-point format which has only 80 significant bits. */
2893 set_gdbarch_long_double_bit (gdbarch, 128);
2895 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
2897 /* Register numbers of various important registers. */
2898 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
2899 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
2900 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
2901 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
2903 /* The "default" register numbering scheme for AMD64 is referred to
2904 as the "DWARF Register Number Mapping" in the System V psABI.
2905 The preferred debugging format for all known AMD64 targets is
2906 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2907 DWARF-1), but we provide the same mapping just in case. This
2908 mapping is also used for stabs, which GCC does support. */
2909 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2910 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2912 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2913 be in use on any of the supported AMD64 targets. */
2915 /* Call dummy code. */
2916 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
2917 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
2918 set_gdbarch_frame_red_zone_size (gdbarch, 128);
2919 tdep->call_dummy_num_integer_regs =
2920 ARRAY_SIZE (amd64_dummy_call_integer_regs);
2921 tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs;
2922 tdep->classify = amd64_classify;
2924 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
2925 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
2926 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
2928 set_gdbarch_return_value (gdbarch, amd64_return_value);
2930 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
2932 tdep->record_regmap = amd64_record_regmap;
2934 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
2936 /* Hook the function epilogue frame unwinder. This unwinder is
2937 appended to the list first, so that it supercedes the other
2938 unwinders in function epilogues. */
2939 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
2941 /* Hook the prologue-based frame unwinders. */
2942 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
2943 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
2944 frame_base_set_default (gdbarch, &amd64_frame_base);
2946 /* If we have a register mapping, enable the generic core file support. */
2947 if (tdep->gregset_reg_offset)
2948 set_gdbarch_regset_from_core_section (gdbarch,
2949 amd64_regset_from_core_section);
2951 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
2953 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
2955 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
2957 /* SystemTap variables and functions. */
2958 set_gdbarch_stap_integer_prefix (gdbarch, "$");
2959 set_gdbarch_stap_register_prefix (gdbarch, "%");
2960 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
2961 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
2962 set_gdbarch_stap_is_single_operand (gdbarch,
2963 i386_stap_is_single_operand);
2964 set_gdbarch_stap_parse_special_token (gdbarch,
2965 i386_stap_parse_special_token);
2969 static struct type *
2970 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2972 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2974 switch (regnum - tdep->eax_regnum)
2976 case AMD64_RBP_REGNUM: /* %ebp */
2977 case AMD64_RSP_REGNUM: /* %esp */
2978 return builtin_type (gdbarch)->builtin_data_ptr;
2979 case AMD64_RIP_REGNUM: /* %eip */
2980 return builtin_type (gdbarch)->builtin_func_ptr;
2983 return i386_pseudo_register_type (gdbarch, regnum);
2987 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2989 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2990 const struct target_desc *tdesc = info.target_desc;
2992 amd64_init_abi (info, gdbarch);
2994 if (! tdesc_has_registers (tdesc))
2996 tdep->tdesc = tdesc;
2998 tdep->num_dword_regs = 17;
2999 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3001 set_gdbarch_long_bit (gdbarch, 32);
3002 set_gdbarch_ptr_bit (gdbarch, 32);
3005 /* Provide a prototype to silence -Wmissing-prototypes. */
3006 void _initialize_amd64_tdep (void);
3009 _initialize_amd64_tdep (void)
3011 initialize_tdesc_amd64 ();
3012 initialize_tdesc_amd64_avx ();
3013 initialize_tdesc_x32 ();
3014 initialize_tdesc_x32_avx ();
3018 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3019 sense that the instruction pointer and data pointer are simply
3020 64-bit offsets into the code segment and the data segment instead
3021 of a selector offset pair. The functions below store the upper 32
3022 bits of these pointers (instead of just the 16-bits of the segment
3025 /* Fill register REGNUM in REGCACHE with the appropriate
3026 floating-point or SSE register value from *FXSAVE. If REGNUM is
3027 -1, do this for all registers. This function masks off any of the
3028 reserved bits in *FXSAVE. */
3031 amd64_supply_fxsave (struct regcache *regcache, int regnum,
3034 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3037 i387_supply_fxsave (regcache, regnum, fxsave);
3040 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3042 const gdb_byte *regs = fxsave;
3044 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3045 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3046 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3047 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3051 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3054 amd64_supply_xsave (struct regcache *regcache, int regnum,
3057 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3058 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3060 i387_supply_xsave (regcache, regnum, xsave);
3063 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3065 const gdb_byte *regs = xsave;
3067 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3068 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3070 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3071 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3076 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3077 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3078 all registers. This function doesn't touch any of the reserved
3082 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3085 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3086 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3087 gdb_byte *regs = fxsave;
3089 i387_collect_fxsave (regcache, regnum, fxsave);
3091 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3093 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3094 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3095 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3096 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3100 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3103 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3104 void *xsave, int gcore)
3106 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3107 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3108 gdb_byte *regs = xsave;
3110 i387_collect_xsave (regcache, regnum, xsave, gcore);
3112 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3114 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3115 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3117 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3118 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),