1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2019 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "common/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "common/byte-vector.h"
53 /* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
55 returned by config.guess, and used as the name for the AMD64 port
56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
60 /* Register information. */
62 static const char *amd64_register_names[] =
64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
66 /* %r8 is indeed register number 8. */
67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
70 /* %st0 is register number 24. */
71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
74 /* %xmm0 is register number 40. */
75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
80 static const char *amd64_ymm_names[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
88 static const char *amd64_ymm_avx512_names[] =
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
96 static const char *amd64_ymmh_names[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
104 static const char *amd64_ymmh_avx512_names[] =
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
112 static const char *amd64_mpx_names[] =
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
117 static const char *amd64_k_names[] =
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
123 static const char *amd64_zmmh_names[] =
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
135 static const char *amd64_zmm_names[] =
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
147 static const char *amd64_xmm_avx512_names[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
154 static const char *amd64_pkeys_names[] = {
158 /* DWARF Register Number Mapping as defined in the System V psABI,
161 static int amd64_dwarf_regmap[] =
163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
164 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
165 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
166 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
168 /* Frame Pointer Register RBP. */
171 /* Stack Pointer Register RSP. */
174 /* Extended Integer Registers 8 - 15. */
175 AMD64_R8_REGNUM, /* %r8 */
176 AMD64_R9_REGNUM, /* %r9 */
177 AMD64_R10_REGNUM, /* %r10 */
178 AMD64_R11_REGNUM, /* %r11 */
179 AMD64_R12_REGNUM, /* %r12 */
180 AMD64_R13_REGNUM, /* %r13 */
181 AMD64_R14_REGNUM, /* %r14 */
182 AMD64_R15_REGNUM, /* %r15 */
184 /* Return Address RA. Mapped to RIP. */
187 /* SSE Registers 0 - 7. */
188 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
189 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
190 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
191 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
193 /* Extended SSE Registers 8 - 15. */
194 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
195 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
196 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
197 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
199 /* Floating Point Registers 0-7. */
200 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
201 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
202 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
203 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
211 /* Control and Status Flags Register. */
214 /* Selector Registers. */
224 /* Segment Base Address Registers. */
230 /* Special Selector Registers. */
234 /* Floating Point Control Registers. */
240 static const int amd64_dwarf_regmap_len =
241 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
243 /* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
247 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int ymm0_regnum = tdep->ymm0_regnum;
253 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
254 regnum = amd64_dwarf_regmap[reg];
257 && i386_xmm_regnum_p (gdbarch, regnum))
258 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap[16] =
267 AMD64_RAX_REGNUM, /* %rax */
268 AMD64_RCX_REGNUM, /* %rcx */
269 AMD64_RDX_REGNUM, /* %rdx */
270 AMD64_RBX_REGNUM, /* %rbx */
271 AMD64_RSP_REGNUM, /* %rsp */
272 AMD64_RBP_REGNUM, /* %rbp */
273 AMD64_RSI_REGNUM, /* %rsi */
274 AMD64_RDI_REGNUM, /* %rdi */
275 AMD64_R8_REGNUM, /* %r8 */
276 AMD64_R9_REGNUM, /* %r9 */
277 AMD64_R10_REGNUM, /* %r10 */
278 AMD64_R11_REGNUM, /* %r11 */
279 AMD64_R12_REGNUM, /* %r12 */
280 AMD64_R13_REGNUM, /* %r13 */
281 AMD64_R14_REGNUM, /* %r14 */
282 AMD64_R15_REGNUM /* %r15 */
285 static const int amd64_arch_regmap_len =
286 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg)
294 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
296 return amd64_arch_regmap[reg];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 if (i386_byte_regnum_p (gdbarch, regnum))
335 return amd64_byte_names[regnum - tdep->al_regnum];
336 else if (i386_zmm_regnum_p (gdbarch, regnum))
337 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
338 else if (i386_ymm_regnum_p (gdbarch, regnum))
339 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
340 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
341 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
342 else if (i386_word_regnum_p (gdbarch, regnum))
343 return amd64_word_names[regnum - tdep->ax_regnum];
344 else if (i386_dword_regnum_p (gdbarch, regnum))
345 return amd64_dword_names[regnum - tdep->eax_regnum];
347 return i386_pseudo_register_name (gdbarch, regnum);
350 static struct value *
351 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
352 readable_regcache *regcache,
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 value *result_value = allocate_value (register_type (gdbarch, regnum));
358 VALUE_LVAL (result_value) = lval_register;
359 VALUE_REGNUM (result_value) = regnum;
360 gdb_byte *buf = value_contents_raw (result_value);
362 if (i386_byte_regnum_p (gdbarch, regnum))
364 int gpnum = regnum - tdep->al_regnum;
366 /* Extract (always little endian). */
367 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
369 gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
370 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
372 /* Special handling for AH, BH, CH, DH. */
373 register_status status = regcache->raw_read (gpnum, raw_buf);
374 if (status == REG_VALID)
375 memcpy (buf, raw_buf + 1, 1);
377 mark_value_bytes_unavailable (result_value, 0,
378 TYPE_LENGTH (value_type (result_value)));
382 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
383 register_status status = regcache->raw_read (gpnum, raw_buf);
384 if (status == REG_VALID)
385 memcpy (buf, raw_buf, 1);
387 mark_value_bytes_unavailable (result_value, 0,
388 TYPE_LENGTH (value_type (result_value)));
391 else if (i386_dword_regnum_p (gdbarch, regnum))
393 int gpnum = regnum - tdep->eax_regnum;
394 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
395 /* Extract (always little endian). */
396 register_status status = regcache->raw_read (gpnum, raw_buf);
397 if (status == REG_VALID)
398 memcpy (buf, raw_buf, 4);
400 mark_value_bytes_unavailable (result_value, 0,
401 TYPE_LENGTH (value_type (result_value)));
404 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
411 amd64_pseudo_register_write (struct gdbarch *gdbarch,
412 struct regcache *regcache,
413 int regnum, const gdb_byte *buf)
415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
417 if (i386_byte_regnum_p (gdbarch, regnum))
419 int gpnum = regnum - tdep->al_regnum;
421 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
423 gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
424 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
426 /* Read ... AH, BH, CH, DH. */
427 regcache->raw_read (gpnum, raw_buf);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf + 1, buf, 1);
431 regcache->raw_write (gpnum, raw_buf);
435 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
438 regcache->raw_read (gpnum, raw_buf);
439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf, buf, 1);
442 regcache->raw_write (gpnum, raw_buf);
445 else if (i386_dword_regnum_p (gdbarch, regnum))
447 int gpnum = regnum - tdep->eax_regnum;
448 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
451 regcache->raw_read (gpnum, raw_buf);
452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf, buf, 4);
455 regcache->raw_write (gpnum, raw_buf);
458 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
461 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
464 amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
465 struct agent_expr *ax, int regnum)
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
469 if (i386_byte_regnum_p (gdbarch, regnum))
471 int gpnum = regnum - tdep->al_regnum;
473 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
474 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
476 ax_reg_mask (ax, gpnum);
479 else if (i386_dword_regnum_p (gdbarch, regnum))
481 int gpnum = regnum - tdep->eax_regnum;
483 ax_reg_mask (ax, gpnum);
487 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
492 /* Register classes as defined in the psABI. */
506 /* Return the union class of CLASS1 and CLASS2. See the psABI for
509 static enum amd64_reg_class
510 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1 == class2)
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1 == AMD64_NO_CLASS)
520 if (class2 == AMD64_NO_CLASS)
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
529 return AMD64_INTEGER;
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
534 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
535 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
538 /* Rule (f): Otherwise class SSE is used. */
542 static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
544 /* Return true if TYPE is a structure or union with unaligned fields. */
547 amd64_has_unaligned_fields (struct type *type)
549 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
550 || TYPE_CODE (type) == TYPE_CODE_UNION)
552 for (int i = 0; i < TYPE_NFIELDS (type); i++)
554 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
555 int bitpos = TYPE_FIELD_BITPOS (type, i);
556 int align = type_align(subtype);
558 /* Ignore static fields, or empty fields, for example nested
560 if (field_is_static (&TYPE_FIELD (type, i))
561 || (TYPE_FIELD_BITSIZE (type, i) == 0
562 && TYPE_LENGTH (subtype) == 0))
568 int bytepos = bitpos / 8;
569 if (bytepos % align != 0)
572 if (amd64_has_unaligned_fields(subtype))
580 /* Classify TYPE according to the rules for aggregate (structures and
581 arrays) and union types, and store the result in CLASS. */
584 amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
586 /* 1. If the size of an object is larger than two eightbytes, or it has
587 unaligned fields, it has class memory. */
588 if (TYPE_LENGTH (type) > 16 || amd64_has_unaligned_fields (type))
590 theclass[0] = theclass[1] = AMD64_MEMORY;
594 /* 2. Both eightbytes get initialized to class NO_CLASS. */
595 theclass[0] = theclass[1] = AMD64_NO_CLASS;
597 /* 3. Each field of an object is classified recursively so that
598 always two fields are considered. The resulting class is
599 calculated according to the classes of the fields in the
602 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
604 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
606 /* All fields in an array have the same type. */
607 amd64_classify (subtype, theclass);
608 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
609 theclass[1] = theclass[0];
615 /* Structure or union. */
616 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
617 || TYPE_CODE (type) == TYPE_CODE_UNION);
619 for (i = 0; i < TYPE_NFIELDS (type); i++)
621 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
622 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
623 enum amd64_reg_class subclass[2];
624 int bitsize = TYPE_FIELD_BITSIZE (type, i);
628 bitsize = TYPE_LENGTH (subtype) * 8;
629 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
631 /* Ignore static fields, or empty fields, for example nested
633 if (field_is_static (&TYPE_FIELD (type, i)) || bitsize == 0)
636 gdb_assert (pos == 0 || pos == 1);
638 amd64_classify (subtype, subclass);
639 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
640 if (bitsize <= 64 && pos == 0 && endpos == 1)
641 /* This is a bit of an odd case: We have a field that would
642 normally fit in one of the two eightbytes, except that
643 it is placed in a way that this field straddles them.
644 This has been seen with a structure containing an array.
646 The ABI is a bit unclear in this case, but we assume that
647 this field's class (stored in subclass[0]) must also be merged
648 into class[1]. In other words, our field has a piece stored
649 in the second eight-byte, and thus its class applies to
650 the second eight-byte as well.
652 In the case where the field length exceeds 8 bytes,
653 it should not be necessary to merge the field class
654 into class[1]. As LEN > 8, subclass[1] is necessarily
655 different from AMD64_NO_CLASS. If subclass[1] is equal
656 to subclass[0], then the normal class[1]/subclass[1]
657 merging will take care of everything. For subclass[1]
658 to be different from subclass[0], I can only see the case
659 where we have a SSE/SSEUP or X87/X87UP pair, which both
660 use up all 16 bytes of the aggregate, and are already
661 handled just fine (because each portion sits on its own
663 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
665 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
669 /* 4. Then a post merger cleanup is done: */
671 /* Rule (a): If one of the classes is MEMORY, the whole argument is
673 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
674 theclass[0] = theclass[1] = AMD64_MEMORY;
676 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
678 if (theclass[0] == AMD64_SSEUP)
679 theclass[0] = AMD64_SSE;
680 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
681 theclass[1] = AMD64_SSE;
684 /* Classify TYPE, and store the result in CLASS. */
687 amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
689 enum type_code code = TYPE_CODE (type);
690 int len = TYPE_LENGTH (type);
692 theclass[0] = theclass[1] = AMD64_NO_CLASS;
694 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
695 long, long long, and pointers are in the INTEGER class. Similarly,
696 range types, used by languages such as Ada, are also in the INTEGER
698 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
699 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
700 || code == TYPE_CODE_CHAR
701 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
702 && (len == 1 || len == 2 || len == 4 || len == 8))
703 theclass[0] = AMD64_INTEGER;
705 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
707 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
708 && (len == 4 || len == 8))
710 theclass[0] = AMD64_SSE;
712 /* Arguments of types __float128, _Decimal128 and __m128 are split into
713 two halves. The least significant ones belong to class SSE, the most
714 significant one to class SSEUP. */
715 else if (code == TYPE_CODE_DECFLOAT && len == 16)
716 /* FIXME: __float128, __m128. */
717 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
719 /* The 64-bit mantissa of arguments of type long double belongs to
720 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
722 else if (code == TYPE_CODE_FLT && len == 16)
723 /* Class X87 and X87UP. */
724 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
726 /* Arguments of complex T where T is one of the types float or
727 double get treated as if they are implemented as:
735 else if (code == TYPE_CODE_COMPLEX && len == 8)
736 theclass[0] = AMD64_SSE;
737 else if (code == TYPE_CODE_COMPLEX && len == 16)
738 theclass[0] = theclass[1] = AMD64_SSE;
740 /* A variable of type complex long double is classified as type
742 else if (code == TYPE_CODE_COMPLEX && len == 32)
743 theclass[0] = AMD64_COMPLEX_X87;
746 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
747 || code == TYPE_CODE_UNION)
748 amd64_classify_aggregate (type, theclass);
751 static enum return_value_convention
752 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
753 struct type *type, struct regcache *regcache,
754 gdb_byte *readbuf, const gdb_byte *writebuf)
756 enum amd64_reg_class theclass[2];
757 int len = TYPE_LENGTH (type);
758 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
759 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
764 gdb_assert (!(readbuf && writebuf));
766 /* 1. Classify the return type with the classification algorithm. */
767 amd64_classify (type, theclass);
769 /* 2. If the type has class MEMORY, then the caller provides space
770 for the return value and passes the address of this storage in
771 %rdi as if it were the first argument to the function. In effect,
772 this address becomes a hidden first argument.
774 On return %rax will contain the address that has been passed in
775 by the caller in %rdi. */
776 if (theclass[0] == AMD64_MEMORY)
778 /* As indicated by the comment above, the ABI guarantees that we
779 can always find the return value just after the function has
786 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
787 read_memory (addr, readbuf, TYPE_LENGTH (type));
790 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
793 /* 8. If the class is COMPLEX_X87, the real part of the value is
794 returned in %st0 and the imaginary part in %st1. */
795 if (theclass[0] == AMD64_COMPLEX_X87)
799 regcache->raw_read (AMD64_ST0_REGNUM, readbuf);
800 regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16);
805 i387_return_value (gdbarch, regcache);
806 regcache->raw_write (AMD64_ST0_REGNUM, writebuf);
807 regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16);
809 /* Fix up the tag word such that both %st(0) and %st(1) are
811 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
814 return RETURN_VALUE_REGISTER_CONVENTION;
817 gdb_assert (theclass[1] != AMD64_MEMORY);
818 gdb_assert (len <= 16);
820 for (i = 0; len > 0; i++, len -= 8)
828 /* 3. If the class is INTEGER, the next available register
829 of the sequence %rax, %rdx is used. */
830 regnum = integer_regnum[integer_reg++];
834 /* 4. If the class is SSE, the next available SSE register
835 of the sequence %xmm0, %xmm1 is used. */
836 regnum = sse_regnum[sse_reg++];
840 /* 5. If the class is SSEUP, the eightbyte is passed in the
841 upper half of the last used SSE register. */
842 gdb_assert (sse_reg > 0);
843 regnum = sse_regnum[sse_reg - 1];
848 /* 6. If the class is X87, the value is returned on the X87
849 stack in %st0 as 80-bit x87 number. */
850 regnum = AMD64_ST0_REGNUM;
852 i387_return_value (gdbarch, regcache);
856 /* 7. If the class is X87UP, the value is returned together
857 with the previous X87 value in %st0. */
858 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
859 regnum = AMD64_ST0_REGNUM;
868 gdb_assert (!"Unexpected register class.");
871 gdb_assert (regnum != -1);
874 regcache->raw_read_part (regnum, offset, std::min (len, 8),
877 regcache->raw_write_part (regnum, offset, std::min (len, 8),
881 return RETURN_VALUE_REGISTER_CONVENTION;
886 amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args,
887 CORE_ADDR sp, function_call_return_method return_method)
889 static int integer_regnum[] =
891 AMD64_RDI_REGNUM, /* %rdi */
892 AMD64_RSI_REGNUM, /* %rsi */
893 AMD64_RDX_REGNUM, /* %rdx */
894 AMD64_RCX_REGNUM, /* %rcx */
895 AMD64_R8_REGNUM, /* %r8 */
896 AMD64_R9_REGNUM /* %r9 */
898 static int sse_regnum[] =
900 /* %xmm0 ... %xmm7 */
901 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
902 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
903 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
904 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
906 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
907 int num_stack_args = 0;
908 int num_elements = 0;
914 /* Reserve a register for the "hidden" argument. */
915 if (return_method == return_method_struct)
918 for (i = 0; i < nargs; i++)
920 struct type *type = value_type (args[i]);
921 int len = TYPE_LENGTH (type);
922 enum amd64_reg_class theclass[2];
923 int needed_integer_regs = 0;
924 int needed_sse_regs = 0;
927 /* Classify argument. */
928 amd64_classify (type, theclass);
930 /* Calculate the number of integer and SSE registers needed for
932 for (j = 0; j < 2; j++)
934 if (theclass[j] == AMD64_INTEGER)
935 needed_integer_regs++;
936 else if (theclass[j] == AMD64_SSE)
940 /* Check whether enough registers are available, and if the
941 argument should be passed in registers at all. */
942 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
943 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
944 || (needed_integer_regs == 0 && needed_sse_regs == 0))
946 /* The argument will be passed on the stack. */
947 num_elements += ((len + 7) / 8);
948 stack_args[num_stack_args++] = args[i];
952 /* The argument will be passed in registers. */
953 const gdb_byte *valbuf = value_contents (args[i]);
956 gdb_assert (len <= 16);
958 for (j = 0; len > 0; j++, len -= 8)
966 regnum = integer_regnum[integer_reg++];
970 regnum = sse_regnum[sse_reg++];
974 gdb_assert (sse_reg > 0);
975 regnum = sse_regnum[sse_reg - 1];
980 gdb_assert (!"Unexpected register class.");
983 gdb_assert (regnum != -1);
984 memset (buf, 0, sizeof buf);
985 memcpy (buf, valbuf + j * 8, std::min (len, 8));
986 regcache->raw_write_part (regnum, offset, 8, buf);
991 /* Allocate space for the arguments on the stack. */
992 sp -= num_elements * 8;
994 /* The psABI says that "The end of the input argument area shall be
995 aligned on a 16 byte boundary." */
998 /* Write out the arguments to the stack. */
999 for (i = 0; i < num_stack_args; i++)
1001 struct type *type = value_type (stack_args[i]);
1002 const gdb_byte *valbuf = value_contents (stack_args[i]);
1003 int len = TYPE_LENGTH (type);
1005 write_memory (sp + element * 8, valbuf, len);
1006 element += ((len + 7) / 8);
1009 /* The psABI says that "For calls that may call functions that use
1010 varargs or stdargs (prototype-less calls or calls to functions
1011 containing ellipsis (...) in the declaration) %al is used as
1012 hidden argument to specify the number of SSE registers used. */
1013 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
1018 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1019 struct regcache *regcache, CORE_ADDR bp_addr,
1020 int nargs, struct value **args, CORE_ADDR sp,
1021 function_call_return_method return_method,
1022 CORE_ADDR struct_addr)
1024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1027 /* BND registers can be in arbitrary values at the moment of the
1028 inferior call. This can cause boundary violations that are not
1029 due to a real bug or even desired by the user. The best to be done
1030 is set the BND registers to allow access to the whole memory, INIT
1031 state, before pushing the inferior call. */
1032 i387_reset_bnd_regs (gdbarch, regcache);
1034 /* Pass arguments. */
1035 sp = amd64_push_arguments (regcache, nargs, args, sp, return_method);
1037 /* Pass "hidden" argument". */
1038 if (return_method == return_method_struct)
1040 store_unsigned_integer (buf, 8, byte_order, struct_addr);
1041 regcache->cooked_write (AMD64_RDI_REGNUM, buf);
1044 /* Store return address. */
1046 store_unsigned_integer (buf, 8, byte_order, bp_addr);
1047 write_memory (sp, buf, 8);
1049 /* Finally, update the stack pointer... */
1050 store_unsigned_integer (buf, 8, byte_order, sp);
1051 regcache->cooked_write (AMD64_RSP_REGNUM, buf);
1053 /* ...and fake a frame pointer. */
1054 regcache->cooked_write (AMD64_RBP_REGNUM, buf);
1059 /* Displaced instruction handling. */
1061 /* A partially decoded instruction.
1062 This contains enough details for displaced stepping purposes. */
1066 /* The number of opcode bytes. */
1068 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1070 int enc_prefix_offset;
1071 /* The offset to the first opcode byte. */
1073 /* The offset to the modrm byte or -1 if not present. */
1076 /* The raw instruction. */
1080 struct amd64_displaced_step_closure : public displaced_step_closure
1082 amd64_displaced_step_closure (int insn_buf_len)
1083 : insn_buf (insn_buf_len, 0)
1086 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1091 /* Details of the instruction. */
1092 struct amd64_insn insn_details;
1094 /* The possibly modified insn. */
1095 gdb::byte_vector insn_buf;
1098 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1099 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1100 at which point delete these in favor of libopcodes' versions). */
1102 static const unsigned char onebyte_has_modrm[256] = {
1103 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1104 /* ------------------------------- */
1105 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1106 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1107 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1108 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1109 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1110 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1111 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1112 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1113 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1114 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1115 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1116 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1117 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1118 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1119 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1120 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1121 /* ------------------------------- */
1122 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1125 static const unsigned char twobyte_has_modrm[256] = {
1126 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1127 /* ------------------------------- */
1128 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1129 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1130 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1131 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1132 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1133 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1134 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1135 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1136 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1137 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1138 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1139 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1140 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1141 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1142 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1143 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1144 /* ------------------------------- */
1145 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1148 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1151 rex_prefix_p (gdb_byte pfx)
1153 return REX_PREFIX_P (pfx);
1156 /* True if PFX is the start of the 2-byte VEX prefix. */
1159 vex2_prefix_p (gdb_byte pfx)
1164 /* True if PFX is the start of the 3-byte VEX prefix. */
1167 vex3_prefix_p (gdb_byte pfx)
1172 /* Skip the legacy instruction prefixes in INSN.
1173 We assume INSN is properly sentineled so we don't have to worry
1174 about falling off the end of the buffer. */
1177 amd64_skip_prefixes (gdb_byte *insn)
1183 case DATA_PREFIX_OPCODE:
1184 case ADDR_PREFIX_OPCODE:
1185 case CS_PREFIX_OPCODE:
1186 case DS_PREFIX_OPCODE:
1187 case ES_PREFIX_OPCODE:
1188 case FS_PREFIX_OPCODE:
1189 case GS_PREFIX_OPCODE:
1190 case SS_PREFIX_OPCODE:
1191 case LOCK_PREFIX_OPCODE:
1192 case REPE_PREFIX_OPCODE:
1193 case REPNE_PREFIX_OPCODE:
1205 /* Return an integer register (other than RSP) that is unused as an input
1207 In order to not require adding a rex prefix if the insn doesn't already
1208 have one, the result is restricted to RAX ... RDI, sans RSP.
1209 The register numbering of the result follows architecture ordering,
1213 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1215 /* 1 bit for each reg */
1216 int used_regs_mask = 0;
1218 /* There can be at most 3 int regs used as inputs in an insn, and we have
1219 7 to choose from (RAX ... RDI, sans RSP).
1220 This allows us to take a conservative approach and keep things simple.
1221 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1222 that implicitly specify RAX. */
1225 used_regs_mask |= 1 << EAX_REG_NUM;
1226 /* Similarily avoid RDX, implicit operand in divides. */
1227 used_regs_mask |= 1 << EDX_REG_NUM;
1229 used_regs_mask |= 1 << ESP_REG_NUM;
1231 /* If the opcode is one byte long and there's no ModRM byte,
1232 assume the opcode specifies a register. */
1233 if (details->opcode_len == 1 && details->modrm_offset == -1)
1234 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1236 /* Mark used regs in the modrm/sib bytes. */
1237 if (details->modrm_offset != -1)
1239 int modrm = details->raw_insn[details->modrm_offset];
1240 int mod = MODRM_MOD_FIELD (modrm);
1241 int reg = MODRM_REG_FIELD (modrm);
1242 int rm = MODRM_RM_FIELD (modrm);
1243 int have_sib = mod != 3 && rm == 4;
1245 /* Assume the reg field of the modrm byte specifies a register. */
1246 used_regs_mask |= 1 << reg;
1250 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1251 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1252 used_regs_mask |= 1 << base;
1253 used_regs_mask |= 1 << idx;
1257 used_regs_mask |= 1 << rm;
1261 gdb_assert (used_regs_mask < 256);
1262 gdb_assert (used_regs_mask != 255);
1264 /* Finally, find a free reg. */
1268 for (i = 0; i < 8; ++i)
1270 if (! (used_regs_mask & (1 << i)))
1274 /* We shouldn't get here. */
1275 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1279 /* Extract the details of INSN that we need. */
1282 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1284 gdb_byte *start = insn;
1287 details->raw_insn = insn;
1289 details->opcode_len = -1;
1290 details->enc_prefix_offset = -1;
1291 details->opcode_offset = -1;
1292 details->modrm_offset = -1;
1294 /* Skip legacy instruction prefixes. */
1295 insn = amd64_skip_prefixes (insn);
1297 /* Skip REX/VEX instruction encoding prefixes. */
1298 if (rex_prefix_p (*insn))
1300 details->enc_prefix_offset = insn - start;
1303 else if (vex2_prefix_p (*insn))
1305 /* Don't record the offset in this case because this prefix has
1306 no REX.B equivalent. */
1309 else if (vex3_prefix_p (*insn))
1311 details->enc_prefix_offset = insn - start;
1315 details->opcode_offset = insn - start;
1317 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1319 /* Two or three-byte opcode. */
1321 need_modrm = twobyte_has_modrm[*insn];
1323 /* Check for three-byte opcode. */
1333 details->opcode_len = 3;
1336 details->opcode_len = 2;
1342 /* One-byte opcode. */
1343 need_modrm = onebyte_has_modrm[*insn];
1344 details->opcode_len = 1;
1350 details->modrm_offset = insn - start;
1354 /* Update %rip-relative addressing in INSN.
1356 %rip-relative addressing only uses a 32-bit displacement.
1357 32 bits is not enough to be guaranteed to cover the distance between where
1358 the real instruction is and where its copy is.
1359 Convert the insn to use base+disp addressing.
1360 We set base = pc + insn_length so we can leave disp unchanged. */
1363 fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc,
1364 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1366 const struct amd64_insn *insn_details = &dsc->insn_details;
1367 int modrm_offset = insn_details->modrm_offset;
1368 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1371 int arch_tmp_regno, tmp_regno;
1372 ULONGEST orig_value;
1374 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1377 /* Compute the rip-relative address. */
1378 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
1379 dsc->insn_buf.size (), from);
1380 rip_base = from + insn_length;
1382 /* We need a register to hold the address.
1383 Pick one not used in the insn.
1384 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1385 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1386 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1388 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1389 static constexpr gdb_byte VEX3_NOT_B = 0x20;
1391 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1392 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1394 if (insn_details->enc_prefix_offset != -1)
1396 gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
1397 if (rex_prefix_p (pfx[0]))
1399 else if (vex3_prefix_p (pfx[0]))
1400 pfx[1] |= VEX3_NOT_B;
1402 gdb_assert_not_reached ("unhandled prefix");
1405 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1406 dsc->tmp_regno = tmp_regno;
1407 dsc->tmp_save = orig_value;
1410 /* Convert the ModRM field to be base+disp. */
1411 dsc->insn_buf[modrm_offset] &= ~0xc7;
1412 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1414 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1416 if (debug_displaced)
1417 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1418 "displaced: using temp reg %d, old value %s, new value %s\n",
1419 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1420 paddress (gdbarch, rip_base));
1424 fixup_displaced_copy (struct gdbarch *gdbarch,
1425 amd64_displaced_step_closure *dsc,
1426 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1428 const struct amd64_insn *details = &dsc->insn_details;
1430 if (details->modrm_offset != -1)
1432 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1434 if ((modrm & 0xc7) == 0x05)
1436 /* The insn uses rip-relative addressing.
1438 fixup_riprel (gdbarch, dsc, from, to, regs);
1443 struct displaced_step_closure *
1444 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1445 CORE_ADDR from, CORE_ADDR to,
1446 struct regcache *regs)
1448 int len = gdbarch_max_insn_length (gdbarch);
1449 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1450 continually watch for running off the end of the buffer. */
1451 int fixup_sentinel_space = len;
1452 amd64_displaced_step_closure *dsc
1453 = new amd64_displaced_step_closure (len + fixup_sentinel_space);
1454 gdb_byte *buf = &dsc->insn_buf[0];
1455 struct amd64_insn *details = &dsc->insn_details;
1457 read_memory (from, buf, len);
1459 /* Set up the sentinel space so we don't have to worry about running
1460 off the end of the buffer. An excessive number of leading prefixes
1461 could otherwise cause this. */
1462 memset (buf + len, 0, fixup_sentinel_space);
1464 amd64_get_insn_details (buf, details);
1466 /* GDB may get control back after the insn after the syscall.
1467 Presumably this is a kernel bug.
1468 If this is a syscall, make sure there's a nop afterwards. */
1472 if (amd64_syscall_p (details, &syscall_length))
1473 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1476 /* Modify the insn to cope with the address where it will be executed from.
1477 In particular, handle any rip-relative addressing. */
1478 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1480 write_memory (to, buf, len);
1482 if (debug_displaced)
1484 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1485 paddress (gdbarch, from), paddress (gdbarch, to));
1486 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1493 amd64_absolute_jmp_p (const struct amd64_insn *details)
1495 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1497 if (insn[0] == 0xff)
1499 /* jump near, absolute indirect (/4) */
1500 if ((insn[1] & 0x38) == 0x20)
1503 /* jump far, absolute indirect (/5) */
1504 if ((insn[1] & 0x38) == 0x28)
1511 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1514 amd64_jmp_p (const struct amd64_insn *details)
1516 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1518 /* jump short, relative. */
1519 if (insn[0] == 0xeb)
1522 /* jump near, relative. */
1523 if (insn[0] == 0xe9)
1526 return amd64_absolute_jmp_p (details);
1530 amd64_absolute_call_p (const struct amd64_insn *details)
1532 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1534 if (insn[0] == 0xff)
1536 /* Call near, absolute indirect (/2) */
1537 if ((insn[1] & 0x38) == 0x10)
1540 /* Call far, absolute indirect (/3) */
1541 if ((insn[1] & 0x38) == 0x18)
1549 amd64_ret_p (const struct amd64_insn *details)
1551 /* NOTE: gcc can emit "repz ; ret". */
1552 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1556 case 0xc2: /* ret near, pop N bytes */
1557 case 0xc3: /* ret near */
1558 case 0xca: /* ret far, pop N bytes */
1559 case 0xcb: /* ret far */
1560 case 0xcf: /* iret */
1569 amd64_call_p (const struct amd64_insn *details)
1571 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1573 if (amd64_absolute_call_p (details))
1576 /* call near, relative */
1577 if (insn[0] == 0xe8)
1583 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1584 length in bytes. Otherwise, return zero. */
1587 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1589 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1591 if (insn[0] == 0x0f && insn[1] == 0x05)
1600 /* Classify the instruction at ADDR using PRED.
1601 Throw an error if the memory can't be read. */
1604 amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1605 int (*pred) (const struct amd64_insn *))
1607 struct amd64_insn details;
1609 int len, classification;
1611 len = gdbarch_max_insn_length (gdbarch);
1612 buf = (gdb_byte *) alloca (len);
1614 read_code (addr, buf, len);
1615 amd64_get_insn_details (buf, &details);
1617 classification = pred (&details);
1619 return classification;
1622 /* The gdbarch insn_is_call method. */
1625 amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1627 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1630 /* The gdbarch insn_is_ret method. */
1633 amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1635 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1638 /* The gdbarch insn_is_jump method. */
1641 amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1643 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1646 /* Fix up the state of registers and memory after having single-stepped
1647 a displaced instruction. */
1650 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1651 struct displaced_step_closure *dsc_,
1652 CORE_ADDR from, CORE_ADDR to,
1653 struct regcache *regs)
1655 amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_;
1656 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1657 /* The offset we applied to the instruction's address. */
1658 ULONGEST insn_offset = to - from;
1659 gdb_byte *insn = dsc->insn_buf.data ();
1660 const struct amd64_insn *insn_details = &dsc->insn_details;
1662 if (debug_displaced)
1663 fprintf_unfiltered (gdb_stdlog,
1664 "displaced: fixup (%s, %s), "
1665 "insn = 0x%02x 0x%02x ...\n",
1666 paddress (gdbarch, from), paddress (gdbarch, to),
1669 /* If we used a tmp reg, restore it. */
1673 if (debug_displaced)
1674 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1675 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1676 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1679 /* The list of issues to contend with here is taken from
1680 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1681 Yay for Free Software! */
1683 /* Relocate the %rip back to the program's instruction stream,
1686 /* Except in the case of absolute or indirect jump or call
1687 instructions, or a return instruction, the new rip is relative to
1688 the displaced instruction; make it relative to the original insn.
1689 Well, signal handler returns don't need relocation either, but we use the
1690 value of %rip to recognize those; see below. */
1691 if (! amd64_absolute_jmp_p (insn_details)
1692 && ! amd64_absolute_call_p (insn_details)
1693 && ! amd64_ret_p (insn_details))
1698 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1700 /* A signal trampoline system call changes the %rip, resuming
1701 execution of the main program after the signal handler has
1702 returned. That makes them like 'return' instructions; we
1703 shouldn't relocate %rip.
1705 But most system calls don't, and we do need to relocate %rip.
1707 Our heuristic for distinguishing these cases: if stepping
1708 over the system call instruction left control directly after
1709 the instruction, the we relocate --- control almost certainly
1710 doesn't belong in the displaced copy. Otherwise, we assume
1711 the instruction has put control where it belongs, and leave
1712 it unrelocated. Goodness help us if there are PC-relative
1714 if (amd64_syscall_p (insn_details, &insn_len)
1715 && orig_rip != to + insn_len
1716 /* GDB can get control back after the insn after the syscall.
1717 Presumably this is a kernel bug.
1718 Fixup ensures its a nop, we add one to the length for it. */
1719 && orig_rip != to + insn_len + 1)
1721 if (debug_displaced)
1722 fprintf_unfiltered (gdb_stdlog,
1723 "displaced: syscall changed %%rip; "
1724 "not relocating\n");
1728 ULONGEST rip = orig_rip - insn_offset;
1730 /* If we just stepped over a breakpoint insn, we don't backup
1731 the pc on purpose; this is to match behaviour without
1734 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1736 if (debug_displaced)
1737 fprintf_unfiltered (gdb_stdlog,
1739 "relocated %%rip from %s to %s\n",
1740 paddress (gdbarch, orig_rip),
1741 paddress (gdbarch, rip));
1745 /* If the instruction was PUSHFL, then the TF bit will be set in the
1746 pushed value, and should be cleared. We'll leave this for later,
1747 since GDB already messes up the TF flag when stepping over a
1750 /* If the instruction was a call, the return address now atop the
1751 stack is the address following the copied instruction. We need
1752 to make it the address following the original instruction. */
1753 if (amd64_call_p (insn_details))
1757 const ULONGEST retaddr_len = 8;
1759 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1760 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1761 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
1762 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1764 if (debug_displaced)
1765 fprintf_unfiltered (gdb_stdlog,
1766 "displaced: relocated return addr at %s "
1768 paddress (gdbarch, rsp),
1769 paddress (gdbarch, retaddr));
1773 /* If the instruction INSN uses RIP-relative addressing, return the
1774 offset into the raw INSN where the displacement to be adjusted is
1775 found. Returns 0 if the instruction doesn't use RIP-relative
1779 rip_relative_offset (struct amd64_insn *insn)
1781 if (insn->modrm_offset != -1)
1783 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1785 if ((modrm & 0xc7) == 0x05)
1787 /* The displacement is found right after the ModRM byte. */
1788 return insn->modrm_offset + 1;
1796 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1798 target_write_memory (*to, buf, len);
1803 amd64_relocate_instruction (struct gdbarch *gdbarch,
1804 CORE_ADDR *to, CORE_ADDR oldloc)
1806 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1807 int len = gdbarch_max_insn_length (gdbarch);
1808 /* Extra space for sentinels. */
1809 int fixup_sentinel_space = len;
1810 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
1811 struct amd64_insn insn_details;
1813 LONGEST rel32, newrel;
1817 read_memory (oldloc, buf, len);
1819 /* Set up the sentinel space so we don't have to worry about running
1820 off the end of the buffer. An excessive number of leading prefixes
1821 could otherwise cause this. */
1822 memset (buf + len, 0, fixup_sentinel_space);
1825 amd64_get_insn_details (insn, &insn_details);
1827 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1829 /* Skip legacy instruction prefixes. */
1830 insn = amd64_skip_prefixes (insn);
1832 /* Adjust calls with 32-bit relative addresses as push/jump, with
1833 the address pushed being the location where the original call in
1834 the user program would return to. */
1835 if (insn[0] == 0xe8)
1837 gdb_byte push_buf[32];
1841 /* Where "ret" in the original code will return to. */
1842 ret_addr = oldloc + insn_length;
1844 /* If pushing an address higher than or equal to 0x80000000,
1845 avoid 'pushq', as that sign extends its 32-bit operand, which
1846 would be incorrect. */
1847 if (ret_addr <= 0x7fffffff)
1849 push_buf[0] = 0x68; /* pushq $... */
1850 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1855 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1856 push_buf[i++] = 0x83;
1857 push_buf[i++] = 0xec;
1858 push_buf[i++] = 0x08;
1860 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1861 push_buf[i++] = 0x04;
1862 push_buf[i++] = 0x24;
1863 store_unsigned_integer (&push_buf[i], 4, byte_order,
1864 ret_addr & 0xffffffff);
1867 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1868 push_buf[i++] = 0x44;
1869 push_buf[i++] = 0x24;
1870 push_buf[i++] = 0x04;
1871 store_unsigned_integer (&push_buf[i], 4, byte_order,
1875 gdb_assert (i <= sizeof (push_buf));
1876 /* Push the push. */
1877 append_insns (to, i, push_buf);
1879 /* Convert the relative call to a relative jump. */
1882 /* Adjust the destination offset. */
1883 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1884 newrel = (oldloc - *to) + rel32;
1885 store_signed_integer (insn + 1, 4, byte_order, newrel);
1887 if (debug_displaced)
1888 fprintf_unfiltered (gdb_stdlog,
1889 "Adjusted insn rel32=%s at %s to"
1890 " rel32=%s at %s\n",
1891 hex_string (rel32), paddress (gdbarch, oldloc),
1892 hex_string (newrel), paddress (gdbarch, *to));
1894 /* Write the adjusted jump into its displaced location. */
1895 append_insns (to, 5, insn);
1899 offset = rip_relative_offset (&insn_details);
1902 /* Adjust jumps with 32-bit relative addresses. Calls are
1903 already handled above. */
1904 if (insn[0] == 0xe9)
1906 /* Adjust conditional jumps. */
1907 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1913 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1914 newrel = (oldloc - *to) + rel32;
1915 store_signed_integer (insn + offset, 4, byte_order, newrel);
1916 if (debug_displaced)
1917 fprintf_unfiltered (gdb_stdlog,
1918 "Adjusted insn rel32=%s at %s to"
1919 " rel32=%s at %s\n",
1920 hex_string (rel32), paddress (gdbarch, oldloc),
1921 hex_string (newrel), paddress (gdbarch, *to));
1924 /* Write the adjusted instruction into its displaced location. */
1925 append_insns (to, insn_length, buf);
1929 /* The maximum number of saved registers. This should include %rip. */
1930 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1932 struct amd64_frame_cache
1937 CORE_ADDR sp_offset;
1940 /* Saved registers. */
1941 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1945 /* Do we have a frame? */
1949 /* Initialize a frame cache. */
1952 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1959 cache->sp_offset = -8;
1962 /* Saved registers. We initialize these to -1 since zero is a valid
1963 offset (that's where %rbp is supposed to be stored).
1964 The values start out as being offsets, and are later converted to
1965 addresses (at which point -1 is interpreted as an address, still meaning
1967 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1968 cache->saved_regs[i] = -1;
1969 cache->saved_sp = 0;
1970 cache->saved_sp_reg = -1;
1972 /* Frameless until proven otherwise. */
1973 cache->frameless_p = 1;
1976 /* Allocate and initialize a frame cache. */
1978 static struct amd64_frame_cache *
1979 amd64_alloc_frame_cache (void)
1981 struct amd64_frame_cache *cache;
1983 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1984 amd64_init_frame_cache (cache);
1988 /* GCC 4.4 and later, can put code in the prologue to realign the
1989 stack pointer. Check whether PC points to such code, and update
1990 CACHE accordingly. Return the first instruction after the code
1991 sequence or CURRENT_PC, whichever is smaller. If we don't
1992 recognize the code, return PC. */
1995 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1996 struct amd64_frame_cache *cache)
1998 /* There are 2 code sequences to re-align stack before the frame
2001 1. Use a caller-saved saved register:
2007 2. Use a callee-saved saved register:
2014 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2016 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2017 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2022 int offset, offset_and;
2024 if (target_read_code (pc, buf, sizeof buf))
2027 /* Check caller-saved saved register. The first instruction has
2028 to be "leaq 8(%rsp), %reg". */
2029 if ((buf[0] & 0xfb) == 0x48
2034 /* MOD must be binary 10 and R/M must be binary 100. */
2035 if ((buf[2] & 0xc7) != 0x44)
2038 /* REG has register number. */
2039 reg = (buf[2] >> 3) & 7;
2041 /* Check the REX.R bit. */
2049 /* Check callee-saved saved register. The first instruction
2050 has to be "pushq %reg". */
2052 if ((buf[0] & 0xf8) == 0x50)
2054 else if ((buf[0] & 0xf6) == 0x40
2055 && (buf[1] & 0xf8) == 0x50)
2057 /* Check the REX.B bit. */
2058 if ((buf[0] & 1) != 0)
2067 reg += buf[offset] & 0x7;
2071 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2072 if ((buf[offset] & 0xfb) != 0x48
2073 || buf[offset + 1] != 0x8d
2074 || buf[offset + 3] != 0x24
2075 || buf[offset + 4] != 0x10)
2078 /* MOD must be binary 10 and R/M must be binary 100. */
2079 if ((buf[offset + 2] & 0xc7) != 0x44)
2082 /* REG has register number. */
2083 r = (buf[offset + 2] >> 3) & 7;
2085 /* Check the REX.R bit. */
2086 if (buf[offset] == 0x4c)
2089 /* Registers in pushq and leaq have to be the same. */
2096 /* Rigister can't be %rsp nor %rbp. */
2097 if (reg == 4 || reg == 5)
2100 /* The next instruction has to be "andq $-XXX, %rsp". */
2101 if (buf[offset] != 0x48
2102 || buf[offset + 2] != 0xe4
2103 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2106 offset_and = offset;
2107 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2109 /* The next instruction has to be "pushq -8(%reg)". */
2111 if (buf[offset] == 0xff)
2113 else if ((buf[offset] & 0xf6) == 0x40
2114 && buf[offset + 1] == 0xff)
2116 /* Check the REX.B bit. */
2117 if ((buf[offset] & 0x1) != 0)
2124 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2126 if (buf[offset + 1] != 0xf8
2127 || (buf[offset] & 0xf8) != 0x70)
2130 /* R/M has register. */
2131 r += buf[offset] & 7;
2133 /* Registers in leaq and pushq have to be the same. */
2137 if (current_pc > pc + offset_and)
2138 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2140 return std::min (pc + offset + 2, current_pc);
2143 /* Similar to amd64_analyze_stack_align for x32. */
2146 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2147 struct amd64_frame_cache *cache)
2149 /* There are 2 code sequences to re-align stack before the frame
2152 1. Use a caller-saved saved register:
2160 [addr32] leal 8(%rsp), %reg
2162 [addr32] pushq -8(%reg)
2164 2. Use a callee-saved saved register:
2174 [addr32] leal 16(%rsp), %reg
2176 [addr32] pushq -8(%reg)
2178 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2180 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2181 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2183 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2185 0x83 0xe4 0xf0 andl $-16, %esp
2186 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2191 int offset, offset_and;
2193 if (target_read_memory (pc, buf, sizeof buf))
2196 /* Skip optional addr32 prefix. */
2197 offset = buf[0] == 0x67 ? 1 : 0;
2199 /* Check caller-saved saved register. The first instruction has
2200 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2201 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2202 && buf[offset + 1] == 0x8d
2203 && buf[offset + 3] == 0x24
2204 && buf[offset + 4] == 0x8)
2206 /* MOD must be binary 10 and R/M must be binary 100. */
2207 if ((buf[offset + 2] & 0xc7) != 0x44)
2210 /* REG has register number. */
2211 reg = (buf[offset + 2] >> 3) & 7;
2213 /* Check the REX.R bit. */
2214 if ((buf[offset] & 0x4) != 0)
2221 /* Check callee-saved saved register. The first instruction
2222 has to be "pushq %reg". */
2224 if ((buf[offset] & 0xf6) == 0x40
2225 && (buf[offset + 1] & 0xf8) == 0x50)
2227 /* Check the REX.B bit. */
2228 if ((buf[offset] & 1) != 0)
2233 else if ((buf[offset] & 0xf8) != 0x50)
2237 reg += buf[offset] & 0x7;
2241 /* Skip optional addr32 prefix. */
2242 if (buf[offset] == 0x67)
2245 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2246 "leal 16(%rsp), %reg". */
2247 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2248 || buf[offset + 1] != 0x8d
2249 || buf[offset + 3] != 0x24
2250 || buf[offset + 4] != 0x10)
2253 /* MOD must be binary 10 and R/M must be binary 100. */
2254 if ((buf[offset + 2] & 0xc7) != 0x44)
2257 /* REG has register number. */
2258 r = (buf[offset + 2] >> 3) & 7;
2260 /* Check the REX.R bit. */
2261 if ((buf[offset] & 0x4) != 0)
2264 /* Registers in pushq and leaq have to be the same. */
2271 /* Rigister can't be %rsp nor %rbp. */
2272 if (reg == 4 || reg == 5)
2275 /* The next instruction may be "andq $-XXX, %rsp" or
2276 "andl $-XXX, %esp". */
2277 if (buf[offset] != 0x48)
2280 if (buf[offset + 2] != 0xe4
2281 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2284 offset_and = offset;
2285 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2287 /* Skip optional addr32 prefix. */
2288 if (buf[offset] == 0x67)
2291 /* The next instruction has to be "pushq -8(%reg)". */
2293 if (buf[offset] == 0xff)
2295 else if ((buf[offset] & 0xf6) == 0x40
2296 && buf[offset + 1] == 0xff)
2298 /* Check the REX.B bit. */
2299 if ((buf[offset] & 0x1) != 0)
2306 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2308 if (buf[offset + 1] != 0xf8
2309 || (buf[offset] & 0xf8) != 0x70)
2312 /* R/M has register. */
2313 r += buf[offset] & 7;
2315 /* Registers in leaq and pushq have to be the same. */
2319 if (current_pc > pc + offset_and)
2320 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2322 return std::min (pc + offset + 2, current_pc);
2325 /* Do a limited analysis of the prologue at PC and update CACHE
2326 accordingly. Bail out early if CURRENT_PC is reached. Return the
2327 address where the analysis stopped.
2329 We will handle only functions beginning with:
2332 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2334 or (for the X32 ABI):
2337 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2339 Any function that doesn't start with one of these sequences will be
2340 assumed to have no prologue and thus no valid frame pointer in
2344 amd64_analyze_prologue (struct gdbarch *gdbarch,
2345 CORE_ADDR pc, CORE_ADDR current_pc,
2346 struct amd64_frame_cache *cache)
2348 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2349 /* There are two variations of movq %rsp, %rbp. */
2350 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2351 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2352 /* Ditto for movl %esp, %ebp. */
2353 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2354 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2359 if (current_pc <= pc)
2362 if (gdbarch_ptr_bit (gdbarch) == 32)
2363 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2365 pc = amd64_analyze_stack_align (pc, current_pc, cache);
2367 op = read_code_unsigned_integer (pc, 1, byte_order);
2369 if (op == 0x55) /* pushq %rbp */
2371 /* Take into account that we've executed the `pushq %rbp' that
2372 starts this instruction sequence. */
2373 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2374 cache->sp_offset += 8;
2376 /* If that's all, return now. */
2377 if (current_pc <= pc + 1)
2380 read_code (pc + 1, buf, 3);
2382 /* Check for `movq %rsp, %rbp'. */
2383 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2384 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2386 /* OK, we actually have a frame. */
2387 cache->frameless_p = 0;
2391 /* For X32, also check for `movq %esp, %ebp'. */
2392 if (gdbarch_ptr_bit (gdbarch) == 32)
2394 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2395 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2397 /* OK, we actually have a frame. */
2398 cache->frameless_p = 0;
2409 /* Work around false termination of prologue - GCC PR debug/48827.
2411 START_PC is the first instruction of a function, PC is its minimal already
2412 determined advanced address. Function returns PC if it has nothing to do.
2416 <-- here is 0 lines advance - the false prologue end marker.
2417 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2418 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2419 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2420 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2421 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2422 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2423 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2424 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2428 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2430 struct symtab_and_line start_pc_sal, next_sal;
2431 gdb_byte buf[4 + 8 * 7];
2437 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2438 if (start_pc_sal.symtab == NULL
2439 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2440 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
2441 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2444 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2445 if (next_sal.line != start_pc_sal.line)
2448 /* START_PC can be from overlayed memory, ignored here. */
2449 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2453 if (buf[0] != 0x84 || buf[1] != 0xc0)
2460 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2462 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2463 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2464 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2468 if ((buf[offset + 2] & 0xc0) == 0x40)
2470 /* 8-bit displacement. */
2474 else if ((buf[offset + 2] & 0xc0) == 0x80)
2476 /* 32-bit displacement. */
2484 if (offset - 4 != buf[3])
2487 return next_sal.end;
2490 /* Return PC of first real instruction. */
2493 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2495 struct amd64_frame_cache cache;
2497 CORE_ADDR func_addr;
2499 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2501 CORE_ADDR post_prologue_pc
2502 = skip_prologue_using_sal (gdbarch, func_addr);
2503 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
2505 /* Clang always emits a line note before the prologue and another
2506 one after. We trust clang to emit usable line notes. */
2507 if (post_prologue_pc
2509 && COMPUNIT_PRODUCER (cust) != NULL
2510 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
2511 return std::max (start_pc, post_prologue_pc);
2514 amd64_init_frame_cache (&cache);
2515 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2517 if (cache.frameless_p)
2520 return amd64_skip_xmm_prologue (pc, start_pc);
2524 /* Normal frames. */
2527 amd64_frame_cache_1 (struct frame_info *this_frame,
2528 struct amd64_frame_cache *cache)
2530 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2531 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2535 cache->pc = get_frame_func (this_frame);
2537 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2540 if (cache->frameless_p)
2542 /* We didn't find a valid frame. If we're at the start of a
2543 function, or somewhere half-way its prologue, the function's
2544 frame probably hasn't been fully setup yet. Try to
2545 reconstruct the base address for the stack frame by looking
2546 at the stack pointer. For truly "frameless" functions this
2549 if (cache->saved_sp_reg != -1)
2551 /* Stack pointer has been saved. */
2552 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2553 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2555 /* We're halfway aligning the stack. */
2556 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2557 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2559 /* This will be added back below. */
2560 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2564 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2565 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2571 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2572 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2575 /* Now that we have the base address for the stack frame we can
2576 calculate the value of %rsp in the calling frame. */
2577 cache->saved_sp = cache->base + 16;
2579 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2580 frame we find it at the same offset from the reconstructed base
2581 address. If we're halfway aligning the stack, %rip is handled
2582 differently (see above). */
2583 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2584 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2586 /* Adjust all the saved registers such that they contain addresses
2587 instead of offsets. */
2588 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2589 if (cache->saved_regs[i] != -1)
2590 cache->saved_regs[i] += cache->base;
2595 static struct amd64_frame_cache *
2596 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2598 struct amd64_frame_cache *cache;
2601 return (struct amd64_frame_cache *) *this_cache;
2603 cache = amd64_alloc_frame_cache ();
2604 *this_cache = cache;
2608 amd64_frame_cache_1 (this_frame, cache);
2610 catch (const gdb_exception_error &ex)
2612 if (ex.error != NOT_AVAILABLE_ERROR)
2619 static enum unwind_stop_reason
2620 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2623 struct amd64_frame_cache *cache =
2624 amd64_frame_cache (this_frame, this_cache);
2627 return UNWIND_UNAVAILABLE;
2629 /* This marks the outermost frame. */
2630 if (cache->base == 0)
2631 return UNWIND_OUTERMOST;
2633 return UNWIND_NO_REASON;
2637 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2638 struct frame_id *this_id)
2640 struct amd64_frame_cache *cache =
2641 amd64_frame_cache (this_frame, this_cache);
2644 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2645 else if (cache->base == 0)
2647 /* This marks the outermost frame. */
2651 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2654 static struct value *
2655 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2658 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2659 struct amd64_frame_cache *cache =
2660 amd64_frame_cache (this_frame, this_cache);
2662 gdb_assert (regnum >= 0);
2664 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2665 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2667 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2668 return frame_unwind_got_memory (this_frame, regnum,
2669 cache->saved_regs[regnum]);
2671 return frame_unwind_got_register (this_frame, regnum, regnum);
2674 static const struct frame_unwind amd64_frame_unwind =
2677 amd64_frame_unwind_stop_reason,
2678 amd64_frame_this_id,
2679 amd64_frame_prev_register,
2681 default_frame_sniffer
2684 /* Generate a bytecode expression to get the value of the saved PC. */
2687 amd64_gen_return_address (struct gdbarch *gdbarch,
2688 struct agent_expr *ax, struct axs_value *value,
2691 /* The following sequence assumes the traditional use of the base
2693 ax_reg (ax, AMD64_RBP_REGNUM);
2695 ax_simple (ax, aop_add);
2696 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2697 value->kind = axs_lvalue_memory;
2701 /* Signal trampolines. */
2703 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2704 64-bit variants. This would require using identical frame caches
2705 on both platforms. */
2707 static struct amd64_frame_cache *
2708 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2710 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2711 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2712 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2713 struct amd64_frame_cache *cache;
2719 return (struct amd64_frame_cache *) *this_cache;
2721 cache = amd64_alloc_frame_cache ();
2725 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2726 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2728 addr = tdep->sigcontext_addr (this_frame);
2729 gdb_assert (tdep->sc_reg_offset);
2730 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2731 for (i = 0; i < tdep->sc_num_regs; i++)
2732 if (tdep->sc_reg_offset[i] != -1)
2733 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2737 catch (const gdb_exception_error &ex)
2739 if (ex.error != NOT_AVAILABLE_ERROR)
2743 *this_cache = cache;
2747 static enum unwind_stop_reason
2748 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2751 struct amd64_frame_cache *cache =
2752 amd64_sigtramp_frame_cache (this_frame, this_cache);
2755 return UNWIND_UNAVAILABLE;
2757 return UNWIND_NO_REASON;
2761 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2762 void **this_cache, struct frame_id *this_id)
2764 struct amd64_frame_cache *cache =
2765 amd64_sigtramp_frame_cache (this_frame, this_cache);
2768 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2769 else if (cache->base == 0)
2771 /* This marks the outermost frame. */
2775 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2778 static struct value *
2779 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2780 void **this_cache, int regnum)
2782 /* Make sure we've initialized the cache. */
2783 amd64_sigtramp_frame_cache (this_frame, this_cache);
2785 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2789 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2790 struct frame_info *this_frame,
2793 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2795 /* We shouldn't even bother if we don't have a sigcontext_addr
2797 if (tdep->sigcontext_addr == NULL)
2800 if (tdep->sigtramp_p != NULL)
2802 if (tdep->sigtramp_p (this_frame))
2806 if (tdep->sigtramp_start != 0)
2808 CORE_ADDR pc = get_frame_pc (this_frame);
2810 gdb_assert (tdep->sigtramp_end != 0);
2811 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2818 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2821 amd64_sigtramp_frame_unwind_stop_reason,
2822 amd64_sigtramp_frame_this_id,
2823 amd64_sigtramp_frame_prev_register,
2825 amd64_sigtramp_frame_sniffer
2830 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2832 struct amd64_frame_cache *cache =
2833 amd64_frame_cache (this_frame, this_cache);
2838 static const struct frame_base amd64_frame_base =
2840 &amd64_frame_unwind,
2841 amd64_frame_base_address,
2842 amd64_frame_base_address,
2843 amd64_frame_base_address
2846 /* Normal frames, but in a function epilogue. */
2848 /* Implement the stack_frame_destroyed_p gdbarch method.
2850 The epilogue is defined here as the 'ret' instruction, which will
2851 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2852 the function's stack frame. */
2855 amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2858 struct compunit_symtab *cust;
2860 cust = find_pc_compunit_symtab (pc);
2861 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2864 if (target_read_memory (pc, &insn, 1))
2865 return 0; /* Can't read memory at pc. */
2867 if (insn != 0xc3) /* 'ret' instruction. */
2874 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2875 struct frame_info *this_frame,
2876 void **this_prologue_cache)
2878 if (frame_relative_level (this_frame) == 0)
2879 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2880 get_frame_pc (this_frame));
2885 static struct amd64_frame_cache *
2886 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2888 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2889 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2890 struct amd64_frame_cache *cache;
2894 return (struct amd64_frame_cache *) *this_cache;
2896 cache = amd64_alloc_frame_cache ();
2897 *this_cache = cache;
2901 /* Cache base will be %esp plus cache->sp_offset (-8). */
2902 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2903 cache->base = extract_unsigned_integer (buf, 8,
2904 byte_order) + cache->sp_offset;
2906 /* Cache pc will be the frame func. */
2907 cache->pc = get_frame_pc (this_frame);
2909 /* The saved %esp will be at cache->base plus 16. */
2910 cache->saved_sp = cache->base + 16;
2912 /* The saved %eip will be at cache->base plus 8. */
2913 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2917 catch (const gdb_exception_error &ex)
2919 if (ex.error != NOT_AVAILABLE_ERROR)
2926 static enum unwind_stop_reason
2927 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2930 struct amd64_frame_cache *cache
2931 = amd64_epilogue_frame_cache (this_frame, this_cache);
2934 return UNWIND_UNAVAILABLE;
2936 return UNWIND_NO_REASON;
2940 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2942 struct frame_id *this_id)
2944 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2948 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2950 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2953 static const struct frame_unwind amd64_epilogue_frame_unwind =
2956 amd64_epilogue_frame_unwind_stop_reason,
2957 amd64_epilogue_frame_this_id,
2958 amd64_frame_prev_register,
2960 amd64_epilogue_frame_sniffer
2963 static struct frame_id
2964 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2968 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2970 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2973 /* 16 byte align the SP per frame requirements. */
2976 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2978 return sp & -(CORE_ADDR)16;
2982 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2983 in the floating-point register set REGSET to register cache
2984 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2987 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2988 int regnum, const void *fpregs, size_t len)
2990 struct gdbarch *gdbarch = regcache->arch ();
2991 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2993 gdb_assert (len >= tdep->sizeof_fpregset);
2994 amd64_supply_fxsave (regcache, regnum, fpregs);
2997 /* Collect register REGNUM from the register cache REGCACHE and store
2998 it in the buffer specified by FPREGS and LEN as described by the
2999 floating-point register set REGSET. If REGNUM is -1, do this for
3000 all registers in REGSET. */
3003 amd64_collect_fpregset (const struct regset *regset,
3004 const struct regcache *regcache,
3005 int regnum, void *fpregs, size_t len)
3007 struct gdbarch *gdbarch = regcache->arch ();
3008 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3010 gdb_assert (len >= tdep->sizeof_fpregset);
3011 amd64_collect_fxsave (regcache, regnum, fpregs);
3014 const struct regset amd64_fpregset =
3016 NULL, amd64_supply_fpregset, amd64_collect_fpregset
3020 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3021 %rdi. We expect its value to be a pointer to the jmp_buf structure
3022 from which we extract the address that we will land at. This
3023 address is copied into PC. This routine returns non-zero on
3027 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
3031 struct gdbarch *gdbarch = get_frame_arch (frame);
3032 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
3033 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
3035 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3036 longjmp will land. */
3037 if (jb_pc_offset == -1)
3040 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
3041 jb_addr= extract_typed_address
3042 (buf, builtin_type (gdbarch)->builtin_data_ptr);
3043 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
3046 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
3051 static const int amd64_record_regmap[] =
3053 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
3054 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
3055 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
3056 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
3057 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
3058 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
3061 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3064 amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc)
3066 return x86_in_indirect_branch_thunk (pc, amd64_register_names,
3072 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
3073 const target_desc *default_tdesc)
3075 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3076 const struct target_desc *tdesc = info.target_desc;
3077 static const char *const stap_integer_prefixes[] = { "$", NULL };
3078 static const char *const stap_register_prefixes[] = { "%", NULL };
3079 static const char *const stap_register_indirection_prefixes[] = { "(",
3081 static const char *const stap_register_indirection_suffixes[] = { ")",
3084 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3085 floating-point registers. */
3086 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
3087 tdep->fpregset = &amd64_fpregset;
3089 if (! tdesc_has_registers (tdesc))
3090 tdesc = default_tdesc;
3091 tdep->tdesc = tdesc;
3093 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3094 tdep->register_names = amd64_register_names;
3096 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3098 tdep->zmmh_register_names = amd64_zmmh_names;
3099 tdep->k_register_names = amd64_k_names;
3100 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3101 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3103 tdep->num_zmm_regs = 32;
3104 tdep->num_xmm_avx512_regs = 16;
3105 tdep->num_ymm_avx512_regs = 16;
3107 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3108 tdep->k0_regnum = AMD64_K0_REGNUM;
3109 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3110 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3113 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3115 tdep->ymmh_register_names = amd64_ymmh_names;
3116 tdep->num_ymm_regs = 16;
3117 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3120 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3122 tdep->mpx_register_names = amd64_mpx_names;
3123 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3124 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3127 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
3129 tdep->fsbase_regnum = AMD64_FSBASE_REGNUM;
3132 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
3134 tdep->pkeys_register_names = amd64_pkeys_names;
3135 tdep->pkru_regnum = AMD64_PKRU_REGNUM;
3136 tdep->num_pkeys_regs = 1;
3139 tdep->num_byte_regs = 20;
3140 tdep->num_word_regs = 16;
3141 tdep->num_dword_regs = 16;
3142 /* Avoid wiring in the MMX registers for now. */
3143 tdep->num_mmx_regs = 0;
3145 set_gdbarch_pseudo_register_read_value (gdbarch,
3146 amd64_pseudo_register_read_value);
3147 set_gdbarch_pseudo_register_write (gdbarch,
3148 amd64_pseudo_register_write);
3149 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3150 amd64_ax_pseudo_register_collect);
3152 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3154 /* AMD64 has an FPU and 16 SSE registers. */
3155 tdep->st0_regnum = AMD64_ST0_REGNUM;
3156 tdep->num_xmm_regs = 16;
3158 /* This is what all the fuss is about. */
3159 set_gdbarch_long_bit (gdbarch, 64);
3160 set_gdbarch_long_long_bit (gdbarch, 64);
3161 set_gdbarch_ptr_bit (gdbarch, 64);
3163 /* In contrast to the i386, on AMD64 a `long double' actually takes
3164 up 128 bits, even though it's still based on the i387 extended
3165 floating-point format which has only 80 significant bits. */
3166 set_gdbarch_long_double_bit (gdbarch, 128);
3168 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
3170 /* Register numbers of various important registers. */
3171 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3172 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3173 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3174 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
3176 /* The "default" register numbering scheme for AMD64 is referred to
3177 as the "DWARF Register Number Mapping" in the System V psABI.
3178 The preferred debugging format for all known AMD64 targets is
3179 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3180 DWARF-1), but we provide the same mapping just in case. This
3181 mapping is also used for stabs, which GCC does support. */
3182 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
3183 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
3185 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3186 be in use on any of the supported AMD64 targets. */
3188 /* Call dummy code. */
3189 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3190 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
3191 set_gdbarch_frame_red_zone_size (gdbarch, 128);
3193 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
3194 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3195 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3197 set_gdbarch_return_value (gdbarch, amd64_return_value);
3199 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
3201 tdep->record_regmap = amd64_record_regmap;
3203 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
3205 /* Hook the function epilogue frame unwinder. This unwinder is
3206 appended to the list first, so that it supercedes the other
3207 unwinders in function epilogues. */
3208 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3210 /* Hook the prologue-based frame unwinders. */
3211 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3212 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
3213 frame_base_set_default (gdbarch, &amd64_frame_base);
3215 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
3217 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
3219 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
3221 /* SystemTap variables and functions. */
3222 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3223 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3224 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3225 stap_register_indirection_prefixes);
3226 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3227 stap_register_indirection_suffixes);
3228 set_gdbarch_stap_is_single_operand (gdbarch,
3229 i386_stap_is_single_operand);
3230 set_gdbarch_stap_parse_special_token (gdbarch,
3231 i386_stap_parse_special_token);
3232 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3233 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3234 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
3236 set_gdbarch_in_indirect_branch_thunk (gdbarch,
3237 amd64_in_indirect_branch_thunk);
3240 /* Initialize ARCH for x86-64, no osabi. */
3243 amd64_none_init_abi (gdbarch_info info, gdbarch *arch)
3245 amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK,
3249 static struct type *
3250 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3252 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3254 switch (regnum - tdep->eax_regnum)
3256 case AMD64_RBP_REGNUM: /* %ebp */
3257 case AMD64_RSP_REGNUM: /* %esp */
3258 return builtin_type (gdbarch)->builtin_data_ptr;
3259 case AMD64_RIP_REGNUM: /* %eip */
3260 return builtin_type (gdbarch)->builtin_func_ptr;
3263 return i386_pseudo_register_type (gdbarch, regnum);
3267 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
3268 const target_desc *default_tdesc)
3270 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3272 amd64_init_abi (info, gdbarch, default_tdesc);
3274 tdep->num_dword_regs = 17;
3275 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3277 set_gdbarch_long_bit (gdbarch, 32);
3278 set_gdbarch_ptr_bit (gdbarch, 32);
3281 /* Initialize ARCH for x64-32, no osabi. */
3284 amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch)
3286 amd64_x32_init_abi (info, arch,
3287 amd64_target_description (X86_XSTATE_SSE_MASK, true));
3290 /* Return the target description for a specified XSAVE feature mask. */
3292 const struct target_desc *
3293 amd64_target_description (uint64_t xcr0, bool segments)
3295 static target_desc *amd64_tdescs \
3296 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3297 target_desc **tdesc;
3299 tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
3300 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
3301 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
3302 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0]
3306 *tdesc = amd64_create_target_description (xcr0, false, false,
3313 _initialize_amd64_tdep (void)
3315 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE,
3316 amd64_none_init_abi);
3317 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE,
3318 amd64_x32_none_init_abi);
3326 { "i386/amd64.xml", X86_XSTATE_SSE_MASK },
3327 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK },
3328 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK },
3329 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
3330 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
3331 { "i386/amd64-avx-mpx-avx512-pku.xml",
3332 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
3335 for (auto &a : xml_masks)
3337 auto tdesc = amd64_target_description (a.mask, true);
3339 selftests::record_xml_tdesc (a.xml, tdesc);
3341 #endif /* GDB_SELF_TEST */
3345 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3346 sense that the instruction pointer and data pointer are simply
3347 64-bit offsets into the code segment and the data segment instead
3348 of a selector offset pair. The functions below store the upper 32
3349 bits of these pointers (instead of just the 16-bits of the segment
3352 /* Fill register REGNUM in REGCACHE with the appropriate
3353 floating-point or SSE register value from *FXSAVE. If REGNUM is
3354 -1, do this for all registers. This function masks off any of the
3355 reserved bits in *FXSAVE. */
3358 amd64_supply_fxsave (struct regcache *regcache, int regnum,
3361 struct gdbarch *gdbarch = regcache->arch ();
3362 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3364 i387_supply_fxsave (regcache, regnum, fxsave);
3367 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3369 const gdb_byte *regs = (const gdb_byte *) fxsave;
3371 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3372 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
3373 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3374 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
3378 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3381 amd64_supply_xsave (struct regcache *regcache, int regnum,
3384 struct gdbarch *gdbarch = regcache->arch ();
3385 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3387 i387_supply_xsave (regcache, regnum, xsave);
3390 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3392 const gdb_byte *regs = (const gdb_byte *) xsave;
3395 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
3397 /* If the FISEG and FOSEG registers have not been initialised yet
3398 (their CLEAR_BV bit is set) then their default values of zero will
3399 have already been setup by I387_SUPPLY_XSAVE. */
3400 if (!(clear_bv & X86_XSTATE_X87))
3402 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3403 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
3404 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3405 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
3410 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3411 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3412 all registers. This function doesn't touch any of the reserved
3416 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3419 struct gdbarch *gdbarch = regcache->arch ();
3420 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3421 gdb_byte *regs = (gdb_byte *) fxsave;
3423 i387_collect_fxsave (regcache, regnum, fxsave);
3425 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3427 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3428 regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12);
3429 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3430 regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20);
3434 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3437 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3438 void *xsave, int gcore)
3440 struct gdbarch *gdbarch = regcache->arch ();
3441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3442 gdb_byte *regs = (gdb_byte *) xsave;
3444 i387_collect_xsave (regcache, regnum, xsave, gcore);
3446 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3448 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3449 regcache->raw_collect (I387_FISEG_REGNUM (tdep),
3451 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3452 regcache->raw_collect (I387_FOSEG_REGNUM (tdep),