1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/amd64-mpx.c"
47 #include "features/i386/amd64-avx-mpx.c"
48 #include "features/i386/amd64-avx512.c"
50 #include "features/i386/x32.c"
51 #include "features/i386/x32-avx.c"
52 #include "features/i386/x32-avx512.c"
57 /* Note that the AMD64 architecture was previously known as x86-64.
58 The latter is (forever) engraved into the canonical system name as
59 returned by config.guess, and used as the name for the AMD64 port
60 of GNU/Linux. The BSD's have renamed their ports to amd64; they
61 don't like to shout. For GDB we prefer the amd64_-prefix over the
62 x86_64_-prefix since it's so much easier to type. */
64 /* Register information. */
66 static const char *amd64_register_names[] =
68 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
70 /* %r8 is indeed register number 8. */
71 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
72 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
74 /* %st0 is register number 24. */
75 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
76 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
78 /* %xmm0 is register number 40. */
79 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
80 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
84 static const char *amd64_ymm_names[] =
86 "ymm0", "ymm1", "ymm2", "ymm3",
87 "ymm4", "ymm5", "ymm6", "ymm7",
88 "ymm8", "ymm9", "ymm10", "ymm11",
89 "ymm12", "ymm13", "ymm14", "ymm15"
92 static const char *amd64_ymm_avx512_names[] =
94 "ymm16", "ymm17", "ymm18", "ymm19",
95 "ymm20", "ymm21", "ymm22", "ymm23",
96 "ymm24", "ymm25", "ymm26", "ymm27",
97 "ymm28", "ymm29", "ymm30", "ymm31"
100 static const char *amd64_ymmh_names[] =
102 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
103 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
104 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
105 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
108 static const char *amd64_ymmh_avx512_names[] =
110 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
111 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
112 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
113 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
116 static const char *amd64_mpx_names[] =
118 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
121 static const char *amd64_k_names[] =
123 "k0", "k1", "k2", "k3",
124 "k4", "k5", "k6", "k7"
127 static const char *amd64_zmmh_names[] =
129 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
130 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
131 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
132 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
133 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
134 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
135 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
136 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
139 static const char *amd64_zmm_names[] =
141 "zmm0", "zmm1", "zmm2", "zmm3",
142 "zmm4", "zmm5", "zmm6", "zmm7",
143 "zmm8", "zmm9", "zmm10", "zmm11",
144 "zmm12", "zmm13", "zmm14", "zmm15",
145 "zmm16", "zmm17", "zmm18", "zmm19",
146 "zmm20", "zmm21", "zmm22", "zmm23",
147 "zmm24", "zmm25", "zmm26", "zmm27",
148 "zmm28", "zmm29", "zmm30", "zmm31"
151 static const char *amd64_xmm_avx512_names[] = {
152 "xmm16", "xmm17", "xmm18", "xmm19",
153 "xmm20", "xmm21", "xmm22", "xmm23",
154 "xmm24", "xmm25", "xmm26", "xmm27",
155 "xmm28", "xmm29", "xmm30", "xmm31"
158 /* DWARF Register Number Mapping as defined in the System V psABI,
161 static int amd64_dwarf_regmap[] =
163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
164 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
165 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
166 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
168 /* Frame Pointer Register RBP. */
171 /* Stack Pointer Register RSP. */
174 /* Extended Integer Registers 8 - 15. */
175 AMD64_R8_REGNUM, /* %r8 */
176 AMD64_R9_REGNUM, /* %r9 */
177 AMD64_R10_REGNUM, /* %r10 */
178 AMD64_R11_REGNUM, /* %r11 */
179 AMD64_R12_REGNUM, /* %r12 */
180 AMD64_R13_REGNUM, /* %r13 */
181 AMD64_R14_REGNUM, /* %r14 */
182 AMD64_R15_REGNUM, /* %r15 */
184 /* Return Address RA. Mapped to RIP. */
187 /* SSE Registers 0 - 7. */
188 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
189 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
190 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
191 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
193 /* Extended SSE Registers 8 - 15. */
194 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
195 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
196 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
197 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
199 /* Floating Point Registers 0-7. */
200 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
201 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
202 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
203 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
211 /* Control and Status Flags Register. */
214 /* Selector Registers. */
224 /* Segment Base Address Registers. */
230 /* Special Selector Registers. */
234 /* Floating Point Control Registers. */
240 static const int amd64_dwarf_regmap_len =
241 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
243 /* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
247 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int ymm0_regnum = tdep->ymm0_regnum;
253 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
254 regnum = amd64_dwarf_regmap[reg];
257 && i386_xmm_regnum_p (gdbarch, regnum))
258 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap[16] =
267 AMD64_RAX_REGNUM, /* %rax */
268 AMD64_RCX_REGNUM, /* %rcx */
269 AMD64_RDX_REGNUM, /* %rdx */
270 AMD64_RBX_REGNUM, /* %rbx */
271 AMD64_RSP_REGNUM, /* %rsp */
272 AMD64_RBP_REGNUM, /* %rbp */
273 AMD64_RSI_REGNUM, /* %rsi */
274 AMD64_RDI_REGNUM, /* %rdi */
275 AMD64_R8_REGNUM, /* %r8 */
276 AMD64_R9_REGNUM, /* %r9 */
277 AMD64_R10_REGNUM, /* %r10 */
278 AMD64_R11_REGNUM, /* %r11 */
279 AMD64_R12_REGNUM, /* %r12 */
280 AMD64_R13_REGNUM, /* %r13 */
281 AMD64_R14_REGNUM, /* %r14 */
282 AMD64_R15_REGNUM /* %r15 */
285 static const int amd64_arch_regmap_len =
286 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg)
294 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
296 return amd64_arch_regmap[reg];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 if (i386_byte_regnum_p (gdbarch, regnum))
335 return amd64_byte_names[regnum - tdep->al_regnum];
336 else if (i386_zmm_regnum_p (gdbarch, regnum))
337 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
338 else if (i386_ymm_regnum_p (gdbarch, regnum))
339 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
340 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
341 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
342 else if (i386_word_regnum_p (gdbarch, regnum))
343 return amd64_word_names[regnum - tdep->ax_regnum];
344 else if (i386_dword_regnum_p (gdbarch, regnum))
345 return amd64_dword_names[regnum - tdep->eax_regnum];
347 return i386_pseudo_register_name (gdbarch, regnum);
350 static struct value *
351 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
352 struct regcache *regcache,
355 gdb_byte raw_buf[MAX_REGISTER_SIZE];
356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 enum register_status status;
358 struct value *result_value;
361 result_value = allocate_value (register_type (gdbarch, regnum));
362 VALUE_LVAL (result_value) = lval_register;
363 VALUE_REGNUM (result_value) = regnum;
364 buf = value_contents_raw (result_value);
366 if (i386_byte_regnum_p (gdbarch, regnum))
368 int gpnum = regnum - tdep->al_regnum;
370 /* Extract (always little endian). */
371 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
373 /* Special handling for AH, BH, CH, DH. */
374 status = regcache_raw_read (regcache,
375 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
377 if (status == REG_VALID)
378 memcpy (buf, raw_buf + 1, 1);
380 mark_value_bytes_unavailable (result_value, 0,
381 TYPE_LENGTH (value_type (result_value)));
385 status = regcache_raw_read (regcache, gpnum, raw_buf);
386 if (status == REG_VALID)
387 memcpy (buf, raw_buf, 1);
389 mark_value_bytes_unavailable (result_value, 0,
390 TYPE_LENGTH (value_type (result_value)));
393 else if (i386_dword_regnum_p (gdbarch, regnum))
395 int gpnum = regnum - tdep->eax_regnum;
396 /* Extract (always little endian). */
397 status = regcache_raw_read (regcache, gpnum, raw_buf);
398 if (status == REG_VALID)
399 memcpy (buf, raw_buf, 4);
401 mark_value_bytes_unavailable (result_value, 0,
402 TYPE_LENGTH (value_type (result_value)));
405 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
412 amd64_pseudo_register_write (struct gdbarch *gdbarch,
413 struct regcache *regcache,
414 int regnum, const gdb_byte *buf)
416 gdb_byte raw_buf[MAX_REGISTER_SIZE];
417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
419 if (i386_byte_regnum_p (gdbarch, regnum))
421 int gpnum = regnum - tdep->al_regnum;
423 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
425 /* Read ... AH, BH, CH, DH. */
426 regcache_raw_read (regcache,
427 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf + 1, buf, 1);
431 regcache_raw_write (regcache,
432 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
437 regcache_raw_read (regcache, gpnum, raw_buf);
438 /* ... Modify ... (always little endian). */
439 memcpy (raw_buf, buf, 1);
441 regcache_raw_write (regcache, gpnum, raw_buf);
444 else if (i386_dword_regnum_p (gdbarch, regnum))
446 int gpnum = regnum - tdep->eax_regnum;
449 regcache_raw_read (regcache, gpnum, raw_buf);
450 /* ... Modify ... (always little endian). */
451 memcpy (raw_buf, buf, 4);
453 regcache_raw_write (regcache, gpnum, raw_buf);
456 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
459 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
462 amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
463 struct agent_expr *ax, int regnum)
465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
467 if (i386_byte_regnum_p (gdbarch, regnum))
469 int gpnum = regnum - tdep->al_regnum;
471 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
472 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
474 ax_reg_mask (ax, gpnum);
477 else if (i386_dword_regnum_p (gdbarch, regnum))
479 int gpnum = regnum - tdep->eax_regnum;
481 ax_reg_mask (ax, gpnum);
485 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
490 /* Register classes as defined in the psABI. */
504 /* Return the union class of CLASS1 and CLASS2. See the psABI for
507 static enum amd64_reg_class
508 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
510 /* Rule (a): If both classes are equal, this is the resulting class. */
511 if (class1 == class2)
514 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
515 is the other class. */
516 if (class1 == AMD64_NO_CLASS)
518 if (class2 == AMD64_NO_CLASS)
521 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
522 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
525 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
526 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
527 return AMD64_INTEGER;
529 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
530 MEMORY is used as class. */
531 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
532 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
533 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
536 /* Rule (f): Otherwise class SSE is used. */
540 static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
542 /* Return non-zero if TYPE is a non-POD structure or union type. */
545 amd64_non_pod_p (struct type *type)
547 /* ??? A class with a base class certainly isn't POD, but does this
548 catch all non-POD structure types? */
549 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
555 /* Classify TYPE according to the rules for aggregate (structures and
556 arrays) and union types, and store the result in CLASS. */
559 amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
561 /* 1. If the size of an object is larger than two eightbytes, or in
562 C++, is a non-POD structure or union type, or contains
563 unaligned fields, it has class memory. */
564 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
566 theclass[0] = theclass[1] = AMD64_MEMORY;
570 /* 2. Both eightbytes get initialized to class NO_CLASS. */
571 theclass[0] = theclass[1] = AMD64_NO_CLASS;
573 /* 3. Each field of an object is classified recursively so that
574 always two fields are considered. The resulting class is
575 calculated according to the classes of the fields in the
578 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
580 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
582 /* All fields in an array have the same type. */
583 amd64_classify (subtype, theclass);
584 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
585 theclass[1] = theclass[0];
591 /* Structure or union. */
592 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
593 || TYPE_CODE (type) == TYPE_CODE_UNION);
595 for (i = 0; i < TYPE_NFIELDS (type); i++)
597 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
598 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
599 enum amd64_reg_class subclass[2];
600 int bitsize = TYPE_FIELD_BITSIZE (type, i);
604 bitsize = TYPE_LENGTH (subtype) * 8;
605 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
607 /* Ignore static fields. */
608 if (field_is_static (&TYPE_FIELD (type, i)))
611 gdb_assert (pos == 0 || pos == 1);
613 amd64_classify (subtype, subclass);
614 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
615 if (bitsize <= 64 && pos == 0 && endpos == 1)
616 /* This is a bit of an odd case: We have a field that would
617 normally fit in one of the two eightbytes, except that
618 it is placed in a way that this field straddles them.
619 This has been seen with a structure containing an array.
621 The ABI is a bit unclear in this case, but we assume that
622 this field's class (stored in subclass[0]) must also be merged
623 into class[1]. In other words, our field has a piece stored
624 in the second eight-byte, and thus its class applies to
625 the second eight-byte as well.
627 In the case where the field length exceeds 8 bytes,
628 it should not be necessary to merge the field class
629 into class[1]. As LEN > 8, subclass[1] is necessarily
630 different from AMD64_NO_CLASS. If subclass[1] is equal
631 to subclass[0], then the normal class[1]/subclass[1]
632 merging will take care of everything. For subclass[1]
633 to be different from subclass[0], I can only see the case
634 where we have a SSE/SSEUP or X87/X87UP pair, which both
635 use up all 16 bytes of the aggregate, and are already
636 handled just fine (because each portion sits on its own
638 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
640 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
644 /* 4. Then a post merger cleanup is done: */
646 /* Rule (a): If one of the classes is MEMORY, the whole argument is
648 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
649 theclass[0] = theclass[1] = AMD64_MEMORY;
651 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
653 if (theclass[0] == AMD64_SSEUP)
654 theclass[0] = AMD64_SSE;
655 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
656 theclass[1] = AMD64_SSE;
659 /* Classify TYPE, and store the result in CLASS. */
662 amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
664 enum type_code code = TYPE_CODE (type);
665 int len = TYPE_LENGTH (type);
667 theclass[0] = theclass[1] = AMD64_NO_CLASS;
669 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
670 long, long long, and pointers are in the INTEGER class. Similarly,
671 range types, used by languages such as Ada, are also in the INTEGER
673 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
674 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
675 || code == TYPE_CODE_CHAR
676 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
677 && (len == 1 || len == 2 || len == 4 || len == 8))
678 theclass[0] = AMD64_INTEGER;
680 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
682 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
683 && (len == 4 || len == 8))
685 theclass[0] = AMD64_SSE;
687 /* Arguments of types __float128, _Decimal128 and __m128 are split into
688 two halves. The least significant ones belong to class SSE, the most
689 significant one to class SSEUP. */
690 else if (code == TYPE_CODE_DECFLOAT && len == 16)
691 /* FIXME: __float128, __m128. */
692 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
694 /* The 64-bit mantissa of arguments of type long double belongs to
695 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
697 else if (code == TYPE_CODE_FLT && len == 16)
698 /* Class X87 and X87UP. */
699 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
701 /* Arguments of complex T where T is one of the types float or
702 double get treated as if they are implemented as:
710 else if (code == TYPE_CODE_COMPLEX && len == 8)
711 theclass[0] = AMD64_SSE;
712 else if (code == TYPE_CODE_COMPLEX && len == 16)
713 theclass[0] = theclass[1] = AMD64_SSE;
715 /* A variable of type complex long double is classified as type
717 else if (code == TYPE_CODE_COMPLEX && len == 32)
718 theclass[0] = AMD64_COMPLEX_X87;
721 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
722 || code == TYPE_CODE_UNION)
723 amd64_classify_aggregate (type, theclass);
726 static enum return_value_convention
727 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
728 struct type *type, struct regcache *regcache,
729 gdb_byte *readbuf, const gdb_byte *writebuf)
731 enum amd64_reg_class theclass[2];
732 int len = TYPE_LENGTH (type);
733 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
734 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
739 gdb_assert (!(readbuf && writebuf));
741 /* 1. Classify the return type with the classification algorithm. */
742 amd64_classify (type, theclass);
744 /* 2. If the type has class MEMORY, then the caller provides space
745 for the return value and passes the address of this storage in
746 %rdi as if it were the first argument to the function. In effect,
747 this address becomes a hidden first argument.
749 On return %rax will contain the address that has been passed in
750 by the caller in %rdi. */
751 if (theclass[0] == AMD64_MEMORY)
753 /* As indicated by the comment above, the ABI guarantees that we
754 can always find the return value just after the function has
761 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
762 read_memory (addr, readbuf, TYPE_LENGTH (type));
765 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
768 /* 8. If the class is COMPLEX_X87, the real part of the value is
769 returned in %st0 and the imaginary part in %st1. */
770 if (theclass[0] == AMD64_COMPLEX_X87)
774 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
775 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
780 i387_return_value (gdbarch, regcache);
781 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
782 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
784 /* Fix up the tag word such that both %st(0) and %st(1) are
786 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
789 return RETURN_VALUE_REGISTER_CONVENTION;
792 gdb_assert (theclass[1] != AMD64_MEMORY);
793 gdb_assert (len <= 16);
795 for (i = 0; len > 0; i++, len -= 8)
803 /* 3. If the class is INTEGER, the next available register
804 of the sequence %rax, %rdx is used. */
805 regnum = integer_regnum[integer_reg++];
809 /* 4. If the class is SSE, the next available SSE register
810 of the sequence %xmm0, %xmm1 is used. */
811 regnum = sse_regnum[sse_reg++];
815 /* 5. If the class is SSEUP, the eightbyte is passed in the
816 upper half of the last used SSE register. */
817 gdb_assert (sse_reg > 0);
818 regnum = sse_regnum[sse_reg - 1];
823 /* 6. If the class is X87, the value is returned on the X87
824 stack in %st0 as 80-bit x87 number. */
825 regnum = AMD64_ST0_REGNUM;
827 i387_return_value (gdbarch, regcache);
831 /* 7. If the class is X87UP, the value is returned together
832 with the previous X87 value in %st0. */
833 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
834 regnum = AMD64_ST0_REGNUM;
843 gdb_assert (!"Unexpected register class.");
846 gdb_assert (regnum != -1);
849 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
852 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
856 return RETURN_VALUE_REGISTER_CONVENTION;
861 amd64_push_arguments (struct regcache *regcache, int nargs,
862 struct value **args, CORE_ADDR sp, int struct_return)
864 static int integer_regnum[] =
866 AMD64_RDI_REGNUM, /* %rdi */
867 AMD64_RSI_REGNUM, /* %rsi */
868 AMD64_RDX_REGNUM, /* %rdx */
869 AMD64_RCX_REGNUM, /* %rcx */
870 AMD64_R8_REGNUM, /* %r8 */
871 AMD64_R9_REGNUM /* %r9 */
873 static int sse_regnum[] =
875 /* %xmm0 ... %xmm7 */
876 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
877 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
878 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
879 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
881 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
882 int num_stack_args = 0;
883 int num_elements = 0;
889 /* Reserve a register for the "hidden" argument. */
893 for (i = 0; i < nargs; i++)
895 struct type *type = value_type (args[i]);
896 int len = TYPE_LENGTH (type);
897 enum amd64_reg_class theclass[2];
898 int needed_integer_regs = 0;
899 int needed_sse_regs = 0;
902 /* Classify argument. */
903 amd64_classify (type, theclass);
905 /* Calculate the number of integer and SSE registers needed for
907 for (j = 0; j < 2; j++)
909 if (theclass[j] == AMD64_INTEGER)
910 needed_integer_regs++;
911 else if (theclass[j] == AMD64_SSE)
915 /* Check whether enough registers are available, and if the
916 argument should be passed in registers at all. */
917 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
918 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
919 || (needed_integer_regs == 0 && needed_sse_regs == 0))
921 /* The argument will be passed on the stack. */
922 num_elements += ((len + 7) / 8);
923 stack_args[num_stack_args++] = args[i];
927 /* The argument will be passed in registers. */
928 const gdb_byte *valbuf = value_contents (args[i]);
931 gdb_assert (len <= 16);
933 for (j = 0; len > 0; j++, len -= 8)
941 regnum = integer_regnum[integer_reg++];
945 regnum = sse_regnum[sse_reg++];
949 gdb_assert (sse_reg > 0);
950 regnum = sse_regnum[sse_reg - 1];
955 gdb_assert (!"Unexpected register class.");
958 gdb_assert (regnum != -1);
959 memset (buf, 0, sizeof buf);
960 memcpy (buf, valbuf + j * 8, min (len, 8));
961 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
966 /* Allocate space for the arguments on the stack. */
967 sp -= num_elements * 8;
969 /* The psABI says that "The end of the input argument area shall be
970 aligned on a 16 byte boundary." */
973 /* Write out the arguments to the stack. */
974 for (i = 0; i < num_stack_args; i++)
976 struct type *type = value_type (stack_args[i]);
977 const gdb_byte *valbuf = value_contents (stack_args[i]);
978 int len = TYPE_LENGTH (type);
980 write_memory (sp + element * 8, valbuf, len);
981 element += ((len + 7) / 8);
984 /* The psABI says that "For calls that may call functions that use
985 varargs or stdargs (prototype-less calls or calls to functions
986 containing ellipsis (...) in the declaration) %al is used as
987 hidden argument to specify the number of SSE registers used. */
988 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
993 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
994 struct regcache *regcache, CORE_ADDR bp_addr,
995 int nargs, struct value **args, CORE_ADDR sp,
996 int struct_return, CORE_ADDR struct_addr)
998 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1001 /* Pass arguments. */
1002 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
1004 /* Pass "hidden" argument". */
1007 store_unsigned_integer (buf, 8, byte_order, struct_addr);
1008 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
1011 /* Store return address. */
1013 store_unsigned_integer (buf, 8, byte_order, bp_addr);
1014 write_memory (sp, buf, 8);
1016 /* Finally, update the stack pointer... */
1017 store_unsigned_integer (buf, 8, byte_order, sp);
1018 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
1020 /* ...and fake a frame pointer. */
1021 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
1026 /* Displaced instruction handling. */
1028 /* A partially decoded instruction.
1029 This contains enough details for displaced stepping purposes. */
1033 /* The number of opcode bytes. */
1035 /* The offset of the rex prefix or -1 if not present. */
1037 /* The offset to the first opcode byte. */
1039 /* The offset to the modrm byte or -1 if not present. */
1042 /* The raw instruction. */
1046 struct displaced_step_closure
1048 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1053 /* Details of the instruction. */
1054 struct amd64_insn insn_details;
1056 /* Amount of space allocated to insn_buf. */
1059 /* The possibly modified insn.
1060 This is a variable-length field. */
1061 gdb_byte insn_buf[1];
1064 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1065 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1066 at which point delete these in favor of libopcodes' versions). */
1068 static const unsigned char onebyte_has_modrm[256] = {
1069 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1070 /* ------------------------------- */
1071 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1072 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1073 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1074 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1075 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1076 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1077 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1078 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1079 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1080 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1081 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1082 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1083 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1084 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1085 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1086 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1087 /* ------------------------------- */
1088 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1091 static const unsigned char twobyte_has_modrm[256] = {
1092 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1093 /* ------------------------------- */
1094 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1095 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1096 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1097 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1098 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1099 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1100 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1101 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1102 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1103 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1104 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1105 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1106 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1107 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1108 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1109 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1110 /* ------------------------------- */
1111 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1114 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1117 rex_prefix_p (gdb_byte pfx)
1119 return REX_PREFIX_P (pfx);
1122 /* Skip the legacy instruction prefixes in INSN.
1123 We assume INSN is properly sentineled so we don't have to worry
1124 about falling off the end of the buffer. */
1127 amd64_skip_prefixes (gdb_byte *insn)
1133 case DATA_PREFIX_OPCODE:
1134 case ADDR_PREFIX_OPCODE:
1135 case CS_PREFIX_OPCODE:
1136 case DS_PREFIX_OPCODE:
1137 case ES_PREFIX_OPCODE:
1138 case FS_PREFIX_OPCODE:
1139 case GS_PREFIX_OPCODE:
1140 case SS_PREFIX_OPCODE:
1141 case LOCK_PREFIX_OPCODE:
1142 case REPE_PREFIX_OPCODE:
1143 case REPNE_PREFIX_OPCODE:
1155 /* Return an integer register (other than RSP) that is unused as an input
1157 In order to not require adding a rex prefix if the insn doesn't already
1158 have one, the result is restricted to RAX ... RDI, sans RSP.
1159 The register numbering of the result follows architecture ordering,
1163 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1165 /* 1 bit for each reg */
1166 int used_regs_mask = 0;
1168 /* There can be at most 3 int regs used as inputs in an insn, and we have
1169 7 to choose from (RAX ... RDI, sans RSP).
1170 This allows us to take a conservative approach and keep things simple.
1171 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1172 that implicitly specify RAX. */
1175 used_regs_mask |= 1 << EAX_REG_NUM;
1176 /* Similarily avoid RDX, implicit operand in divides. */
1177 used_regs_mask |= 1 << EDX_REG_NUM;
1179 used_regs_mask |= 1 << ESP_REG_NUM;
1181 /* If the opcode is one byte long and there's no ModRM byte,
1182 assume the opcode specifies a register. */
1183 if (details->opcode_len == 1 && details->modrm_offset == -1)
1184 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1186 /* Mark used regs in the modrm/sib bytes. */
1187 if (details->modrm_offset != -1)
1189 int modrm = details->raw_insn[details->modrm_offset];
1190 int mod = MODRM_MOD_FIELD (modrm);
1191 int reg = MODRM_REG_FIELD (modrm);
1192 int rm = MODRM_RM_FIELD (modrm);
1193 int have_sib = mod != 3 && rm == 4;
1195 /* Assume the reg field of the modrm byte specifies a register. */
1196 used_regs_mask |= 1 << reg;
1200 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1201 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1202 used_regs_mask |= 1 << base;
1203 used_regs_mask |= 1 << idx;
1207 used_regs_mask |= 1 << rm;
1211 gdb_assert (used_regs_mask < 256);
1212 gdb_assert (used_regs_mask != 255);
1214 /* Finally, find a free reg. */
1218 for (i = 0; i < 8; ++i)
1220 if (! (used_regs_mask & (1 << i)))
1224 /* We shouldn't get here. */
1225 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1229 /* Extract the details of INSN that we need. */
1232 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1234 gdb_byte *start = insn;
1237 details->raw_insn = insn;
1239 details->opcode_len = -1;
1240 details->rex_offset = -1;
1241 details->opcode_offset = -1;
1242 details->modrm_offset = -1;
1244 /* Skip legacy instruction prefixes. */
1245 insn = amd64_skip_prefixes (insn);
1247 /* Skip REX instruction prefix. */
1248 if (rex_prefix_p (*insn))
1250 details->rex_offset = insn - start;
1254 details->opcode_offset = insn - start;
1256 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1258 /* Two or three-byte opcode. */
1260 need_modrm = twobyte_has_modrm[*insn];
1262 /* Check for three-byte opcode. */
1272 details->opcode_len = 3;
1275 details->opcode_len = 2;
1281 /* One-byte opcode. */
1282 need_modrm = onebyte_has_modrm[*insn];
1283 details->opcode_len = 1;
1289 details->modrm_offset = insn - start;
1293 /* Update %rip-relative addressing in INSN.
1295 %rip-relative addressing only uses a 32-bit displacement.
1296 32 bits is not enough to be guaranteed to cover the distance between where
1297 the real instruction is and where its copy is.
1298 Convert the insn to use base+disp addressing.
1299 We set base = pc + insn_length so we can leave disp unchanged. */
1302 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1303 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1305 const struct amd64_insn *insn_details = &dsc->insn_details;
1306 int modrm_offset = insn_details->modrm_offset;
1307 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1310 int arch_tmp_regno, tmp_regno;
1311 ULONGEST orig_value;
1313 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1316 /* Compute the rip-relative address. */
1317 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1318 dsc->max_len, from);
1319 rip_base = from + insn_length;
1321 /* We need a register to hold the address.
1322 Pick one not used in the insn.
1323 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1324 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1325 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1327 /* REX.B should be unset as we were using rip-relative addressing,
1328 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1329 if (insn_details->rex_offset != -1)
1330 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1332 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1333 dsc->tmp_regno = tmp_regno;
1334 dsc->tmp_save = orig_value;
1337 /* Convert the ModRM field to be base+disp. */
1338 dsc->insn_buf[modrm_offset] &= ~0xc7;
1339 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1341 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1343 if (debug_displaced)
1344 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1345 "displaced: using temp reg %d, old value %s, new value %s\n",
1346 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1347 paddress (gdbarch, rip_base));
1351 fixup_displaced_copy (struct gdbarch *gdbarch,
1352 struct displaced_step_closure *dsc,
1353 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1355 const struct amd64_insn *details = &dsc->insn_details;
1357 if (details->modrm_offset != -1)
1359 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1361 if ((modrm & 0xc7) == 0x05)
1363 /* The insn uses rip-relative addressing.
1365 fixup_riprel (gdbarch, dsc, from, to, regs);
1370 struct displaced_step_closure *
1371 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1372 CORE_ADDR from, CORE_ADDR to,
1373 struct regcache *regs)
1375 int len = gdbarch_max_insn_length (gdbarch);
1376 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1377 continually watch for running off the end of the buffer. */
1378 int fixup_sentinel_space = len;
1379 struct displaced_step_closure *dsc
1380 = ((struct displaced_step_closure *)
1381 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space));
1382 gdb_byte *buf = &dsc->insn_buf[0];
1383 struct amd64_insn *details = &dsc->insn_details;
1386 dsc->max_len = len + fixup_sentinel_space;
1388 read_memory (from, buf, len);
1390 /* Set up the sentinel space so we don't have to worry about running
1391 off the end of the buffer. An excessive number of leading prefixes
1392 could otherwise cause this. */
1393 memset (buf + len, 0, fixup_sentinel_space);
1395 amd64_get_insn_details (buf, details);
1397 /* GDB may get control back after the insn after the syscall.
1398 Presumably this is a kernel bug.
1399 If this is a syscall, make sure there's a nop afterwards. */
1403 if (amd64_syscall_p (details, &syscall_length))
1404 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1407 /* Modify the insn to cope with the address where it will be executed from.
1408 In particular, handle any rip-relative addressing. */
1409 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1411 write_memory (to, buf, len);
1413 if (debug_displaced)
1415 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1416 paddress (gdbarch, from), paddress (gdbarch, to));
1417 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1424 amd64_absolute_jmp_p (const struct amd64_insn *details)
1426 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1428 if (insn[0] == 0xff)
1430 /* jump near, absolute indirect (/4) */
1431 if ((insn[1] & 0x38) == 0x20)
1434 /* jump far, absolute indirect (/5) */
1435 if ((insn[1] & 0x38) == 0x28)
1442 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1445 amd64_jmp_p (const struct amd64_insn *details)
1447 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1449 /* jump short, relative. */
1450 if (insn[0] == 0xeb)
1453 /* jump near, relative. */
1454 if (insn[0] == 0xe9)
1457 return amd64_absolute_jmp_p (details);
1461 amd64_absolute_call_p (const struct amd64_insn *details)
1463 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1465 if (insn[0] == 0xff)
1467 /* Call near, absolute indirect (/2) */
1468 if ((insn[1] & 0x38) == 0x10)
1471 /* Call far, absolute indirect (/3) */
1472 if ((insn[1] & 0x38) == 0x18)
1480 amd64_ret_p (const struct amd64_insn *details)
1482 /* NOTE: gcc can emit "repz ; ret". */
1483 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1487 case 0xc2: /* ret near, pop N bytes */
1488 case 0xc3: /* ret near */
1489 case 0xca: /* ret far, pop N bytes */
1490 case 0xcb: /* ret far */
1491 case 0xcf: /* iret */
1500 amd64_call_p (const struct amd64_insn *details)
1502 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1504 if (amd64_absolute_call_p (details))
1507 /* call near, relative */
1508 if (insn[0] == 0xe8)
1514 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1515 length in bytes. Otherwise, return zero. */
1518 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1520 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1522 if (insn[0] == 0x0f && insn[1] == 0x05)
1531 /* Classify the instruction at ADDR using PRED.
1532 Throw an error if the memory can't be read. */
1535 amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1536 int (*pred) (const struct amd64_insn *))
1538 struct amd64_insn details;
1540 int len, classification;
1542 len = gdbarch_max_insn_length (gdbarch);
1543 buf = (gdb_byte *) alloca (len);
1545 read_code (addr, buf, len);
1546 amd64_get_insn_details (buf, &details);
1548 classification = pred (&details);
1550 return classification;
1553 /* The gdbarch insn_is_call method. */
1556 amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1558 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1561 /* The gdbarch insn_is_ret method. */
1564 amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1566 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1569 /* The gdbarch insn_is_jump method. */
1572 amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1574 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1577 /* Fix up the state of registers and memory after having single-stepped
1578 a displaced instruction. */
1581 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1582 struct displaced_step_closure *dsc,
1583 CORE_ADDR from, CORE_ADDR to,
1584 struct regcache *regs)
1586 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1587 /* The offset we applied to the instruction's address. */
1588 ULONGEST insn_offset = to - from;
1589 gdb_byte *insn = dsc->insn_buf;
1590 const struct amd64_insn *insn_details = &dsc->insn_details;
1592 if (debug_displaced)
1593 fprintf_unfiltered (gdb_stdlog,
1594 "displaced: fixup (%s, %s), "
1595 "insn = 0x%02x 0x%02x ...\n",
1596 paddress (gdbarch, from), paddress (gdbarch, to),
1599 /* If we used a tmp reg, restore it. */
1603 if (debug_displaced)
1604 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1605 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1606 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1609 /* The list of issues to contend with here is taken from
1610 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1611 Yay for Free Software! */
1613 /* Relocate the %rip back to the program's instruction stream,
1616 /* Except in the case of absolute or indirect jump or call
1617 instructions, or a return instruction, the new rip is relative to
1618 the displaced instruction; make it relative to the original insn.
1619 Well, signal handler returns don't need relocation either, but we use the
1620 value of %rip to recognize those; see below. */
1621 if (! amd64_absolute_jmp_p (insn_details)
1622 && ! amd64_absolute_call_p (insn_details)
1623 && ! amd64_ret_p (insn_details))
1628 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1630 /* A signal trampoline system call changes the %rip, resuming
1631 execution of the main program after the signal handler has
1632 returned. That makes them like 'return' instructions; we
1633 shouldn't relocate %rip.
1635 But most system calls don't, and we do need to relocate %rip.
1637 Our heuristic for distinguishing these cases: if stepping
1638 over the system call instruction left control directly after
1639 the instruction, the we relocate --- control almost certainly
1640 doesn't belong in the displaced copy. Otherwise, we assume
1641 the instruction has put control where it belongs, and leave
1642 it unrelocated. Goodness help us if there are PC-relative
1644 if (amd64_syscall_p (insn_details, &insn_len)
1645 && orig_rip != to + insn_len
1646 /* GDB can get control back after the insn after the syscall.
1647 Presumably this is a kernel bug.
1648 Fixup ensures its a nop, we add one to the length for it. */
1649 && orig_rip != to + insn_len + 1)
1651 if (debug_displaced)
1652 fprintf_unfiltered (gdb_stdlog,
1653 "displaced: syscall changed %%rip; "
1654 "not relocating\n");
1658 ULONGEST rip = orig_rip - insn_offset;
1660 /* If we just stepped over a breakpoint insn, we don't backup
1661 the pc on purpose; this is to match behaviour without
1664 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1666 if (debug_displaced)
1667 fprintf_unfiltered (gdb_stdlog,
1669 "relocated %%rip from %s to %s\n",
1670 paddress (gdbarch, orig_rip),
1671 paddress (gdbarch, rip));
1675 /* If the instruction was PUSHFL, then the TF bit will be set in the
1676 pushed value, and should be cleared. We'll leave this for later,
1677 since GDB already messes up the TF flag when stepping over a
1680 /* If the instruction was a call, the return address now atop the
1681 stack is the address following the copied instruction. We need
1682 to make it the address following the original instruction. */
1683 if (amd64_call_p (insn_details))
1687 const ULONGEST retaddr_len = 8;
1689 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1690 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1691 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
1692 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1694 if (debug_displaced)
1695 fprintf_unfiltered (gdb_stdlog,
1696 "displaced: relocated return addr at %s "
1698 paddress (gdbarch, rsp),
1699 paddress (gdbarch, retaddr));
1703 /* If the instruction INSN uses RIP-relative addressing, return the
1704 offset into the raw INSN where the displacement to be adjusted is
1705 found. Returns 0 if the instruction doesn't use RIP-relative
1709 rip_relative_offset (struct amd64_insn *insn)
1711 if (insn->modrm_offset != -1)
1713 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1715 if ((modrm & 0xc7) == 0x05)
1717 /* The displacement is found right after the ModRM byte. */
1718 return insn->modrm_offset + 1;
1726 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1728 target_write_memory (*to, buf, len);
1733 amd64_relocate_instruction (struct gdbarch *gdbarch,
1734 CORE_ADDR *to, CORE_ADDR oldloc)
1736 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1737 int len = gdbarch_max_insn_length (gdbarch);
1738 /* Extra space for sentinels. */
1739 int fixup_sentinel_space = len;
1740 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
1741 struct amd64_insn insn_details;
1743 LONGEST rel32, newrel;
1747 read_memory (oldloc, buf, len);
1749 /* Set up the sentinel space so we don't have to worry about running
1750 off the end of the buffer. An excessive number of leading prefixes
1751 could otherwise cause this. */
1752 memset (buf + len, 0, fixup_sentinel_space);
1755 amd64_get_insn_details (insn, &insn_details);
1757 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1759 /* Skip legacy instruction prefixes. */
1760 insn = amd64_skip_prefixes (insn);
1762 /* Adjust calls with 32-bit relative addresses as push/jump, with
1763 the address pushed being the location where the original call in
1764 the user program would return to. */
1765 if (insn[0] == 0xe8)
1767 gdb_byte push_buf[16];
1768 unsigned int ret_addr;
1770 /* Where "ret" in the original code will return to. */
1771 ret_addr = oldloc + insn_length;
1772 push_buf[0] = 0x68; /* pushq $... */
1773 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1774 /* Push the push. */
1775 append_insns (to, 5, push_buf);
1777 /* Convert the relative call to a relative jump. */
1780 /* Adjust the destination offset. */
1781 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1782 newrel = (oldloc - *to) + rel32;
1783 store_signed_integer (insn + 1, 4, byte_order, newrel);
1785 if (debug_displaced)
1786 fprintf_unfiltered (gdb_stdlog,
1787 "Adjusted insn rel32=%s at %s to"
1788 " rel32=%s at %s\n",
1789 hex_string (rel32), paddress (gdbarch, oldloc),
1790 hex_string (newrel), paddress (gdbarch, *to));
1792 /* Write the adjusted jump into its displaced location. */
1793 append_insns (to, 5, insn);
1797 offset = rip_relative_offset (&insn_details);
1800 /* Adjust jumps with 32-bit relative addresses. Calls are
1801 already handled above. */
1802 if (insn[0] == 0xe9)
1804 /* Adjust conditional jumps. */
1805 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1811 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1812 newrel = (oldloc - *to) + rel32;
1813 store_signed_integer (insn + offset, 4, byte_order, newrel);
1814 if (debug_displaced)
1815 fprintf_unfiltered (gdb_stdlog,
1816 "Adjusted insn rel32=%s at %s to"
1817 " rel32=%s at %s\n",
1818 hex_string (rel32), paddress (gdbarch, oldloc),
1819 hex_string (newrel), paddress (gdbarch, *to));
1822 /* Write the adjusted instruction into its displaced location. */
1823 append_insns (to, insn_length, buf);
1827 /* The maximum number of saved registers. This should include %rip. */
1828 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1830 struct amd64_frame_cache
1835 CORE_ADDR sp_offset;
1838 /* Saved registers. */
1839 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1843 /* Do we have a frame? */
1847 /* Initialize a frame cache. */
1850 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1857 cache->sp_offset = -8;
1860 /* Saved registers. We initialize these to -1 since zero is a valid
1861 offset (that's where %rbp is supposed to be stored).
1862 The values start out as being offsets, and are later converted to
1863 addresses (at which point -1 is interpreted as an address, still meaning
1865 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1866 cache->saved_regs[i] = -1;
1867 cache->saved_sp = 0;
1868 cache->saved_sp_reg = -1;
1870 /* Frameless until proven otherwise. */
1871 cache->frameless_p = 1;
1874 /* Allocate and initialize a frame cache. */
1876 static struct amd64_frame_cache *
1877 amd64_alloc_frame_cache (void)
1879 struct amd64_frame_cache *cache;
1881 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1882 amd64_init_frame_cache (cache);
1886 /* GCC 4.4 and later, can put code in the prologue to realign the
1887 stack pointer. Check whether PC points to such code, and update
1888 CACHE accordingly. Return the first instruction after the code
1889 sequence or CURRENT_PC, whichever is smaller. If we don't
1890 recognize the code, return PC. */
1893 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1894 struct amd64_frame_cache *cache)
1896 /* There are 2 code sequences to re-align stack before the frame
1899 1. Use a caller-saved saved register:
1905 2. Use a callee-saved saved register:
1912 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1914 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1915 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1920 int offset, offset_and;
1922 if (target_read_code (pc, buf, sizeof buf))
1925 /* Check caller-saved saved register. The first instruction has
1926 to be "leaq 8(%rsp), %reg". */
1927 if ((buf[0] & 0xfb) == 0x48
1932 /* MOD must be binary 10 and R/M must be binary 100. */
1933 if ((buf[2] & 0xc7) != 0x44)
1936 /* REG has register number. */
1937 reg = (buf[2] >> 3) & 7;
1939 /* Check the REX.R bit. */
1947 /* Check callee-saved saved register. The first instruction
1948 has to be "pushq %reg". */
1950 if ((buf[0] & 0xf8) == 0x50)
1952 else if ((buf[0] & 0xf6) == 0x40
1953 && (buf[1] & 0xf8) == 0x50)
1955 /* Check the REX.B bit. */
1956 if ((buf[0] & 1) != 0)
1965 reg += buf[offset] & 0x7;
1969 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1970 if ((buf[offset] & 0xfb) != 0x48
1971 || buf[offset + 1] != 0x8d
1972 || buf[offset + 3] != 0x24
1973 || buf[offset + 4] != 0x10)
1976 /* MOD must be binary 10 and R/M must be binary 100. */
1977 if ((buf[offset + 2] & 0xc7) != 0x44)
1980 /* REG has register number. */
1981 r = (buf[offset + 2] >> 3) & 7;
1983 /* Check the REX.R bit. */
1984 if (buf[offset] == 0x4c)
1987 /* Registers in pushq and leaq have to be the same. */
1994 /* Rigister can't be %rsp nor %rbp. */
1995 if (reg == 4 || reg == 5)
1998 /* The next instruction has to be "andq $-XXX, %rsp". */
1999 if (buf[offset] != 0x48
2000 || buf[offset + 2] != 0xe4
2001 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2004 offset_and = offset;
2005 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2007 /* The next instruction has to be "pushq -8(%reg)". */
2009 if (buf[offset] == 0xff)
2011 else if ((buf[offset] & 0xf6) == 0x40
2012 && buf[offset + 1] == 0xff)
2014 /* Check the REX.B bit. */
2015 if ((buf[offset] & 0x1) != 0)
2022 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2024 if (buf[offset + 1] != 0xf8
2025 || (buf[offset] & 0xf8) != 0x70)
2028 /* R/M has register. */
2029 r += buf[offset] & 7;
2031 /* Registers in leaq and pushq have to be the same. */
2035 if (current_pc > pc + offset_and)
2036 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2038 return min (pc + offset + 2, current_pc);
2041 /* Similar to amd64_analyze_stack_align for x32. */
2044 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2045 struct amd64_frame_cache *cache)
2047 /* There are 2 code sequences to re-align stack before the frame
2050 1. Use a caller-saved saved register:
2058 [addr32] leal 8(%rsp), %reg
2060 [addr32] pushq -8(%reg)
2062 2. Use a callee-saved saved register:
2072 [addr32] leal 16(%rsp), %reg
2074 [addr32] pushq -8(%reg)
2076 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2078 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2079 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2081 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2083 0x83 0xe4 0xf0 andl $-16, %esp
2084 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2089 int offset, offset_and;
2091 if (target_read_memory (pc, buf, sizeof buf))
2094 /* Skip optional addr32 prefix. */
2095 offset = buf[0] == 0x67 ? 1 : 0;
2097 /* Check caller-saved saved register. The first instruction has
2098 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2099 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2100 && buf[offset + 1] == 0x8d
2101 && buf[offset + 3] == 0x24
2102 && buf[offset + 4] == 0x8)
2104 /* MOD must be binary 10 and R/M must be binary 100. */
2105 if ((buf[offset + 2] & 0xc7) != 0x44)
2108 /* REG has register number. */
2109 reg = (buf[offset + 2] >> 3) & 7;
2111 /* Check the REX.R bit. */
2112 if ((buf[offset] & 0x4) != 0)
2119 /* Check callee-saved saved register. The first instruction
2120 has to be "pushq %reg". */
2122 if ((buf[offset] & 0xf6) == 0x40
2123 && (buf[offset + 1] & 0xf8) == 0x50)
2125 /* Check the REX.B bit. */
2126 if ((buf[offset] & 1) != 0)
2131 else if ((buf[offset] & 0xf8) != 0x50)
2135 reg += buf[offset] & 0x7;
2139 /* Skip optional addr32 prefix. */
2140 if (buf[offset] == 0x67)
2143 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2144 "leal 16(%rsp), %reg". */
2145 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2146 || buf[offset + 1] != 0x8d
2147 || buf[offset + 3] != 0x24
2148 || buf[offset + 4] != 0x10)
2151 /* MOD must be binary 10 and R/M must be binary 100. */
2152 if ((buf[offset + 2] & 0xc7) != 0x44)
2155 /* REG has register number. */
2156 r = (buf[offset + 2] >> 3) & 7;
2158 /* Check the REX.R bit. */
2159 if ((buf[offset] & 0x4) != 0)
2162 /* Registers in pushq and leaq have to be the same. */
2169 /* Rigister can't be %rsp nor %rbp. */
2170 if (reg == 4 || reg == 5)
2173 /* The next instruction may be "andq $-XXX, %rsp" or
2174 "andl $-XXX, %esp". */
2175 if (buf[offset] != 0x48)
2178 if (buf[offset + 2] != 0xe4
2179 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2182 offset_and = offset;
2183 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2185 /* Skip optional addr32 prefix. */
2186 if (buf[offset] == 0x67)
2189 /* The next instruction has to be "pushq -8(%reg)". */
2191 if (buf[offset] == 0xff)
2193 else if ((buf[offset] & 0xf6) == 0x40
2194 && buf[offset + 1] == 0xff)
2196 /* Check the REX.B bit. */
2197 if ((buf[offset] & 0x1) != 0)
2204 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2206 if (buf[offset + 1] != 0xf8
2207 || (buf[offset] & 0xf8) != 0x70)
2210 /* R/M has register. */
2211 r += buf[offset] & 7;
2213 /* Registers in leaq and pushq have to be the same. */
2217 if (current_pc > pc + offset_and)
2218 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2220 return min (pc + offset + 2, current_pc);
2223 /* Do a limited analysis of the prologue at PC and update CACHE
2224 accordingly. Bail out early if CURRENT_PC is reached. Return the
2225 address where the analysis stopped.
2227 We will handle only functions beginning with:
2230 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2232 or (for the X32 ABI):
2235 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2237 Any function that doesn't start with one of these sequences will be
2238 assumed to have no prologue and thus no valid frame pointer in
2242 amd64_analyze_prologue (struct gdbarch *gdbarch,
2243 CORE_ADDR pc, CORE_ADDR current_pc,
2244 struct amd64_frame_cache *cache)
2246 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2247 /* There are two variations of movq %rsp, %rbp. */
2248 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2249 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2250 /* Ditto for movl %esp, %ebp. */
2251 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2252 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2257 if (current_pc <= pc)
2260 if (gdbarch_ptr_bit (gdbarch) == 32)
2261 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2263 pc = amd64_analyze_stack_align (pc, current_pc, cache);
2265 op = read_code_unsigned_integer (pc, 1, byte_order);
2267 if (op == 0x55) /* pushq %rbp */
2269 /* Take into account that we've executed the `pushq %rbp' that
2270 starts this instruction sequence. */
2271 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2272 cache->sp_offset += 8;
2274 /* If that's all, return now. */
2275 if (current_pc <= pc + 1)
2278 read_code (pc + 1, buf, 3);
2280 /* Check for `movq %rsp, %rbp'. */
2281 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2282 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2284 /* OK, we actually have a frame. */
2285 cache->frameless_p = 0;
2289 /* For X32, also check for `movq %esp, %ebp'. */
2290 if (gdbarch_ptr_bit (gdbarch) == 32)
2292 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2293 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2295 /* OK, we actually have a frame. */
2296 cache->frameless_p = 0;
2307 /* Work around false termination of prologue - GCC PR debug/48827.
2309 START_PC is the first instruction of a function, PC is its minimal already
2310 determined advanced address. Function returns PC if it has nothing to do.
2314 <-- here is 0 lines advance - the false prologue end marker.
2315 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2316 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2317 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2318 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2319 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2320 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2321 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2322 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2326 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2328 struct symtab_and_line start_pc_sal, next_sal;
2329 gdb_byte buf[4 + 8 * 7];
2335 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2336 if (start_pc_sal.symtab == NULL
2337 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2338 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
2339 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2342 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2343 if (next_sal.line != start_pc_sal.line)
2346 /* START_PC can be from overlayed memory, ignored here. */
2347 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2351 if (buf[0] != 0x84 || buf[1] != 0xc0)
2358 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2360 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2361 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2362 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2366 if ((buf[offset + 2] & 0xc0) == 0x40)
2368 /* 8-bit displacement. */
2372 else if ((buf[offset + 2] & 0xc0) == 0x80)
2374 /* 32-bit displacement. */
2382 if (offset - 4 != buf[3])
2385 return next_sal.end;
2388 /* Return PC of first real instruction. */
2391 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2393 struct amd64_frame_cache cache;
2395 CORE_ADDR func_addr;
2397 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2399 CORE_ADDR post_prologue_pc
2400 = skip_prologue_using_sal (gdbarch, func_addr);
2401 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
2403 /* Clang always emits a line note before the prologue and another
2404 one after. We trust clang to emit usable line notes. */
2405 if (post_prologue_pc
2407 && COMPUNIT_PRODUCER (cust) != NULL
2408 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
2409 return max (start_pc, post_prologue_pc);
2412 amd64_init_frame_cache (&cache);
2413 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2415 if (cache.frameless_p)
2418 return amd64_skip_xmm_prologue (pc, start_pc);
2422 /* Normal frames. */
2425 amd64_frame_cache_1 (struct frame_info *this_frame,
2426 struct amd64_frame_cache *cache)
2428 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2429 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2433 cache->pc = get_frame_func (this_frame);
2435 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2438 if (cache->frameless_p)
2440 /* We didn't find a valid frame. If we're at the start of a
2441 function, or somewhere half-way its prologue, the function's
2442 frame probably hasn't been fully setup yet. Try to
2443 reconstruct the base address for the stack frame by looking
2444 at the stack pointer. For truly "frameless" functions this
2447 if (cache->saved_sp_reg != -1)
2449 /* Stack pointer has been saved. */
2450 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2451 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2453 /* We're halfway aligning the stack. */
2454 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2455 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2457 /* This will be added back below. */
2458 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2462 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2463 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2469 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2470 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2473 /* Now that we have the base address for the stack frame we can
2474 calculate the value of %rsp in the calling frame. */
2475 cache->saved_sp = cache->base + 16;
2477 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2478 frame we find it at the same offset from the reconstructed base
2479 address. If we're halfway aligning the stack, %rip is handled
2480 differently (see above). */
2481 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2482 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2484 /* Adjust all the saved registers such that they contain addresses
2485 instead of offsets. */
2486 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2487 if (cache->saved_regs[i] != -1)
2488 cache->saved_regs[i] += cache->base;
2493 static struct amd64_frame_cache *
2494 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2496 struct amd64_frame_cache *cache;
2499 return (struct amd64_frame_cache *) *this_cache;
2501 cache = amd64_alloc_frame_cache ();
2502 *this_cache = cache;
2506 amd64_frame_cache_1 (this_frame, cache);
2508 CATCH (ex, RETURN_MASK_ERROR)
2510 if (ex.error != NOT_AVAILABLE_ERROR)
2511 throw_exception (ex);
2518 static enum unwind_stop_reason
2519 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2522 struct amd64_frame_cache *cache =
2523 amd64_frame_cache (this_frame, this_cache);
2526 return UNWIND_UNAVAILABLE;
2528 /* This marks the outermost frame. */
2529 if (cache->base == 0)
2530 return UNWIND_OUTERMOST;
2532 return UNWIND_NO_REASON;
2536 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2537 struct frame_id *this_id)
2539 struct amd64_frame_cache *cache =
2540 amd64_frame_cache (this_frame, this_cache);
2543 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2544 else if (cache->base == 0)
2546 /* This marks the outermost frame. */
2550 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2553 static struct value *
2554 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2557 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2558 struct amd64_frame_cache *cache =
2559 amd64_frame_cache (this_frame, this_cache);
2561 gdb_assert (regnum >= 0);
2563 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2564 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2566 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2567 return frame_unwind_got_memory (this_frame, regnum,
2568 cache->saved_regs[regnum]);
2570 return frame_unwind_got_register (this_frame, regnum, regnum);
2573 static const struct frame_unwind amd64_frame_unwind =
2576 amd64_frame_unwind_stop_reason,
2577 amd64_frame_this_id,
2578 amd64_frame_prev_register,
2580 default_frame_sniffer
2583 /* Generate a bytecode expression to get the value of the saved PC. */
2586 amd64_gen_return_address (struct gdbarch *gdbarch,
2587 struct agent_expr *ax, struct axs_value *value,
2590 /* The following sequence assumes the traditional use of the base
2592 ax_reg (ax, AMD64_RBP_REGNUM);
2594 ax_simple (ax, aop_add);
2595 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2596 value->kind = axs_lvalue_memory;
2600 /* Signal trampolines. */
2602 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2603 64-bit variants. This would require using identical frame caches
2604 on both platforms. */
2606 static struct amd64_frame_cache *
2607 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2609 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2610 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2611 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2612 struct amd64_frame_cache *cache;
2618 return (struct amd64_frame_cache *) *this_cache;
2620 cache = amd64_alloc_frame_cache ();
2624 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2625 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2627 addr = tdep->sigcontext_addr (this_frame);
2628 gdb_assert (tdep->sc_reg_offset);
2629 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2630 for (i = 0; i < tdep->sc_num_regs; i++)
2631 if (tdep->sc_reg_offset[i] != -1)
2632 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2636 CATCH (ex, RETURN_MASK_ERROR)
2638 if (ex.error != NOT_AVAILABLE_ERROR)
2639 throw_exception (ex);
2643 *this_cache = cache;
2647 static enum unwind_stop_reason
2648 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2651 struct amd64_frame_cache *cache =
2652 amd64_sigtramp_frame_cache (this_frame, this_cache);
2655 return UNWIND_UNAVAILABLE;
2657 return UNWIND_NO_REASON;
2661 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2662 void **this_cache, struct frame_id *this_id)
2664 struct amd64_frame_cache *cache =
2665 amd64_sigtramp_frame_cache (this_frame, this_cache);
2668 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2669 else if (cache->base == 0)
2671 /* This marks the outermost frame. */
2675 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2678 static struct value *
2679 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2680 void **this_cache, int regnum)
2682 /* Make sure we've initialized the cache. */
2683 amd64_sigtramp_frame_cache (this_frame, this_cache);
2685 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2689 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2690 struct frame_info *this_frame,
2693 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2695 /* We shouldn't even bother if we don't have a sigcontext_addr
2697 if (tdep->sigcontext_addr == NULL)
2700 if (tdep->sigtramp_p != NULL)
2702 if (tdep->sigtramp_p (this_frame))
2706 if (tdep->sigtramp_start != 0)
2708 CORE_ADDR pc = get_frame_pc (this_frame);
2710 gdb_assert (tdep->sigtramp_end != 0);
2711 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2718 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2721 amd64_sigtramp_frame_unwind_stop_reason,
2722 amd64_sigtramp_frame_this_id,
2723 amd64_sigtramp_frame_prev_register,
2725 amd64_sigtramp_frame_sniffer
2730 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2732 struct amd64_frame_cache *cache =
2733 amd64_frame_cache (this_frame, this_cache);
2738 static const struct frame_base amd64_frame_base =
2740 &amd64_frame_unwind,
2741 amd64_frame_base_address,
2742 amd64_frame_base_address,
2743 amd64_frame_base_address
2746 /* Normal frames, but in a function epilogue. */
2748 /* Implement the stack_frame_destroyed_p gdbarch method.
2750 The epilogue is defined here as the 'ret' instruction, which will
2751 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2752 the function's stack frame. */
2755 amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2758 struct compunit_symtab *cust;
2760 cust = find_pc_compunit_symtab (pc);
2761 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2764 if (target_read_memory (pc, &insn, 1))
2765 return 0; /* Can't read memory at pc. */
2767 if (insn != 0xc3) /* 'ret' instruction. */
2774 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2775 struct frame_info *this_frame,
2776 void **this_prologue_cache)
2778 if (frame_relative_level (this_frame) == 0)
2779 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2780 get_frame_pc (this_frame));
2785 static struct amd64_frame_cache *
2786 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2788 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2789 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2790 struct amd64_frame_cache *cache;
2794 return (struct amd64_frame_cache *) *this_cache;
2796 cache = amd64_alloc_frame_cache ();
2797 *this_cache = cache;
2801 /* Cache base will be %esp plus cache->sp_offset (-8). */
2802 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2803 cache->base = extract_unsigned_integer (buf, 8,
2804 byte_order) + cache->sp_offset;
2806 /* Cache pc will be the frame func. */
2807 cache->pc = get_frame_pc (this_frame);
2809 /* The saved %esp will be at cache->base plus 16. */
2810 cache->saved_sp = cache->base + 16;
2812 /* The saved %eip will be at cache->base plus 8. */
2813 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2817 CATCH (ex, RETURN_MASK_ERROR)
2819 if (ex.error != NOT_AVAILABLE_ERROR)
2820 throw_exception (ex);
2827 static enum unwind_stop_reason
2828 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2831 struct amd64_frame_cache *cache
2832 = amd64_epilogue_frame_cache (this_frame, this_cache);
2835 return UNWIND_UNAVAILABLE;
2837 return UNWIND_NO_REASON;
2841 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2843 struct frame_id *this_id)
2845 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2849 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2851 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2854 static const struct frame_unwind amd64_epilogue_frame_unwind =
2857 amd64_epilogue_frame_unwind_stop_reason,
2858 amd64_epilogue_frame_this_id,
2859 amd64_frame_prev_register,
2861 amd64_epilogue_frame_sniffer
2864 static struct frame_id
2865 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2869 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2871 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2874 /* 16 byte align the SP per frame requirements. */
2877 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2879 return sp & -(CORE_ADDR)16;
2883 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2884 in the floating-point register set REGSET to register cache
2885 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2888 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2889 int regnum, const void *fpregs, size_t len)
2891 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2892 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2894 gdb_assert (len >= tdep->sizeof_fpregset);
2895 amd64_supply_fxsave (regcache, regnum, fpregs);
2898 /* Collect register REGNUM from the register cache REGCACHE and store
2899 it in the buffer specified by FPREGS and LEN as described by the
2900 floating-point register set REGSET. If REGNUM is -1, do this for
2901 all registers in REGSET. */
2904 amd64_collect_fpregset (const struct regset *regset,
2905 const struct regcache *regcache,
2906 int regnum, void *fpregs, size_t len)
2908 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2909 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2911 gdb_assert (len >= tdep->sizeof_fpregset);
2912 amd64_collect_fxsave (regcache, regnum, fpregs);
2915 const struct regset amd64_fpregset =
2917 NULL, amd64_supply_fpregset, amd64_collect_fpregset
2921 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2922 %rdi. We expect its value to be a pointer to the jmp_buf structure
2923 from which we extract the address that we will land at. This
2924 address is copied into PC. This routine returns non-zero on
2928 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2932 struct gdbarch *gdbarch = get_frame_arch (frame);
2933 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2934 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2936 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2937 longjmp will land. */
2938 if (jb_pc_offset == -1)
2941 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2942 jb_addr= extract_typed_address
2943 (buf, builtin_type (gdbarch)->builtin_data_ptr);
2944 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2947 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2952 static const int amd64_record_regmap[] =
2954 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2955 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2956 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2957 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2958 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2959 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2963 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2965 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2966 const struct target_desc *tdesc = info.target_desc;
2967 static const char *const stap_integer_prefixes[] = { "$", NULL };
2968 static const char *const stap_register_prefixes[] = { "%", NULL };
2969 static const char *const stap_register_indirection_prefixes[] = { "(",
2971 static const char *const stap_register_indirection_suffixes[] = { ")",
2974 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2975 floating-point registers. */
2976 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2977 tdep->fpregset = &amd64_fpregset;
2979 if (! tdesc_has_registers (tdesc))
2980 tdesc = tdesc_amd64;
2981 tdep->tdesc = tdesc;
2983 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2984 tdep->register_names = amd64_register_names;
2986 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
2988 tdep->zmmh_register_names = amd64_zmmh_names;
2989 tdep->k_register_names = amd64_k_names;
2990 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
2991 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
2993 tdep->num_zmm_regs = 32;
2994 tdep->num_xmm_avx512_regs = 16;
2995 tdep->num_ymm_avx512_regs = 16;
2997 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
2998 tdep->k0_regnum = AMD64_K0_REGNUM;
2999 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3000 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3003 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3005 tdep->ymmh_register_names = amd64_ymmh_names;
3006 tdep->num_ymm_regs = 16;
3007 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3010 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3012 tdep->mpx_register_names = amd64_mpx_names;
3013 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3014 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3017 tdep->num_byte_regs = 20;
3018 tdep->num_word_regs = 16;
3019 tdep->num_dword_regs = 16;
3020 /* Avoid wiring in the MMX registers for now. */
3021 tdep->num_mmx_regs = 0;
3023 set_gdbarch_pseudo_register_read_value (gdbarch,
3024 amd64_pseudo_register_read_value);
3025 set_gdbarch_pseudo_register_write (gdbarch,
3026 amd64_pseudo_register_write);
3027 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3028 amd64_ax_pseudo_register_collect);
3030 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3032 /* AMD64 has an FPU and 16 SSE registers. */
3033 tdep->st0_regnum = AMD64_ST0_REGNUM;
3034 tdep->num_xmm_regs = 16;
3036 /* This is what all the fuss is about. */
3037 set_gdbarch_long_bit (gdbarch, 64);
3038 set_gdbarch_long_long_bit (gdbarch, 64);
3039 set_gdbarch_ptr_bit (gdbarch, 64);
3041 /* In contrast to the i386, on AMD64 a `long double' actually takes
3042 up 128 bits, even though it's still based on the i387 extended
3043 floating-point format which has only 80 significant bits. */
3044 set_gdbarch_long_double_bit (gdbarch, 128);
3046 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
3048 /* Register numbers of various important registers. */
3049 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3050 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3051 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3052 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
3054 /* The "default" register numbering scheme for AMD64 is referred to
3055 as the "DWARF Register Number Mapping" in the System V psABI.
3056 The preferred debugging format for all known AMD64 targets is
3057 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3058 DWARF-1), but we provide the same mapping just in case. This
3059 mapping is also used for stabs, which GCC does support. */
3060 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
3061 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
3063 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3064 be in use on any of the supported AMD64 targets. */
3066 /* Call dummy code. */
3067 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3068 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
3069 set_gdbarch_frame_red_zone_size (gdbarch, 128);
3071 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
3072 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3073 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3075 set_gdbarch_return_value (gdbarch, amd64_return_value);
3077 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
3079 tdep->record_regmap = amd64_record_regmap;
3081 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
3083 /* Hook the function epilogue frame unwinder. This unwinder is
3084 appended to the list first, so that it supercedes the other
3085 unwinders in function epilogues. */
3086 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3088 /* Hook the prologue-based frame unwinders. */
3089 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3090 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
3091 frame_base_set_default (gdbarch, &amd64_frame_base);
3093 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
3095 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
3097 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
3099 /* SystemTap variables and functions. */
3100 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3101 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3102 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3103 stap_register_indirection_prefixes);
3104 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3105 stap_register_indirection_suffixes);
3106 set_gdbarch_stap_is_single_operand (gdbarch,
3107 i386_stap_is_single_operand);
3108 set_gdbarch_stap_parse_special_token (gdbarch,
3109 i386_stap_parse_special_token);
3110 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3111 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3112 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
3116 static struct type *
3117 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3119 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3121 switch (regnum - tdep->eax_regnum)
3123 case AMD64_RBP_REGNUM: /* %ebp */
3124 case AMD64_RSP_REGNUM: /* %esp */
3125 return builtin_type (gdbarch)->builtin_data_ptr;
3126 case AMD64_RIP_REGNUM: /* %eip */
3127 return builtin_type (gdbarch)->builtin_func_ptr;
3130 return i386_pseudo_register_type (gdbarch, regnum);
3134 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3137 const struct target_desc *tdesc = info.target_desc;
3139 amd64_init_abi (info, gdbarch);
3141 if (! tdesc_has_registers (tdesc))
3143 tdep->tdesc = tdesc;
3145 tdep->num_dword_regs = 17;
3146 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3148 set_gdbarch_long_bit (gdbarch, 32);
3149 set_gdbarch_ptr_bit (gdbarch, 32);
3152 /* Return the target description for a specified XSAVE feature mask. */
3154 const struct target_desc *
3155 amd64_target_description (uint64_t xcr0)
3157 switch (xcr0 & X86_XSTATE_ALL_MASK)
3159 case X86_XSTATE_MPX_AVX512_MASK:
3160 case X86_XSTATE_AVX512_MASK:
3161 return tdesc_amd64_avx512;
3162 case X86_XSTATE_MPX_MASK:
3163 return tdesc_amd64_mpx;
3164 case X86_XSTATE_AVX_MPX_MASK:
3165 return tdesc_amd64_avx_mpx;
3166 case X86_XSTATE_AVX_MASK:
3167 return tdesc_amd64_avx;
3173 /* Provide a prototype to silence -Wmissing-prototypes. */
3174 void _initialize_amd64_tdep (void);
3177 _initialize_amd64_tdep (void)
3179 initialize_tdesc_amd64 ();
3180 initialize_tdesc_amd64_avx ();
3181 initialize_tdesc_amd64_mpx ();
3182 initialize_tdesc_amd64_avx_mpx ();
3183 initialize_tdesc_amd64_avx512 ();
3185 initialize_tdesc_x32 ();
3186 initialize_tdesc_x32_avx ();
3187 initialize_tdesc_x32_avx512 ();
3191 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3192 sense that the instruction pointer and data pointer are simply
3193 64-bit offsets into the code segment and the data segment instead
3194 of a selector offset pair. The functions below store the upper 32
3195 bits of these pointers (instead of just the 16-bits of the segment
3198 /* Fill register REGNUM in REGCACHE with the appropriate
3199 floating-point or SSE register value from *FXSAVE. If REGNUM is
3200 -1, do this for all registers. This function masks off any of the
3201 reserved bits in *FXSAVE. */
3204 amd64_supply_fxsave (struct regcache *regcache, int regnum,
3207 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3210 i387_supply_fxsave (regcache, regnum, fxsave);
3213 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3215 const gdb_byte *regs = (const gdb_byte *) fxsave;
3217 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3218 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3219 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3220 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3224 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3227 amd64_supply_xsave (struct regcache *regcache, int regnum,
3230 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3233 i387_supply_xsave (regcache, regnum, xsave);
3236 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3238 const gdb_byte *regs = (const gdb_byte *) xsave;
3240 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3241 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3243 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3244 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3249 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3250 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3251 all registers. This function doesn't touch any of the reserved
3255 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3258 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3260 gdb_byte *regs = (gdb_byte *) fxsave;
3262 i387_collect_fxsave (regcache, regnum, fxsave);
3264 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3266 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3267 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3268 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3269 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3273 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3276 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3277 void *xsave, int gcore)
3279 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3280 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3281 gdb_byte *regs = (gdb_byte *) xsave;
3283 i387_collect_xsave (regcache, regnum, xsave, gcore);
3285 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3287 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3288 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3290 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3291 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),