1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2012 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
52 /* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
54 returned by config.guess, and used as the name for the AMD64 port
55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
59 /* Register information. */
61 static const char *amd64_register_names[] =
63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
65 /* %r8 is indeed register number 8. */
66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
69 /* %st0 is register number 24. */
70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
73 /* %xmm0 is register number 40. */
74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
79 static const char *amd64_ymm_names[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
87 static const char *amd64_ymmh_names[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
95 /* The registers used to pass integer arguments during a function call. */
96 static int amd64_dummy_call_integer_regs[] =
98 AMD64_RDI_REGNUM, /* %rdi */
99 AMD64_RSI_REGNUM, /* %rsi */
100 AMD64_RDX_REGNUM, /* %rdx */
101 AMD64_RCX_REGNUM, /* %rcx */
106 /* DWARF Register Number Mapping as defined in the System V psABI,
109 static int amd64_dwarf_regmap[] =
111 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
112 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
113 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
114 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
116 /* Frame Pointer Register RBP. */
119 /* Stack Pointer Register RSP. */
122 /* Extended Integer Registers 8 - 15. */
123 8, 9, 10, 11, 12, 13, 14, 15,
125 /* Return Address RA. Mapped to RIP. */
128 /* SSE Registers 0 - 7. */
129 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
130 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
131 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
132 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
134 /* Extended SSE Registers 8 - 15. */
135 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
136 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
137 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
138 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
140 /* Floating Point Registers 0-7. */
141 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
142 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
143 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
144 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
146 /* Control and Status Flags Register. */
149 /* Selector Registers. */
159 /* Segment Base Address Registers. */
165 /* Special Selector Registers. */
169 /* Floating Point Control Registers. */
175 static const int amd64_dwarf_regmap_len =
176 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
178 /* Convert DWARF register number REG to the appropriate register
179 number used by GDB. */
182 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
185 int ymm0_regnum = tdep->ymm0_regnum;
188 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
189 regnum = amd64_dwarf_regmap[reg];
192 warning (_("Unmapped DWARF Register #%d encountered."), reg);
193 else if (ymm0_regnum >= 0
194 && i386_xmm_regnum_p (gdbarch, regnum))
195 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
200 /* Map architectural register numbers to gdb register numbers. */
202 static const int amd64_arch_regmap[16] =
204 AMD64_RAX_REGNUM, /* %rax */
205 AMD64_RCX_REGNUM, /* %rcx */
206 AMD64_RDX_REGNUM, /* %rdx */
207 AMD64_RBX_REGNUM, /* %rbx */
208 AMD64_RSP_REGNUM, /* %rsp */
209 AMD64_RBP_REGNUM, /* %rbp */
210 AMD64_RSI_REGNUM, /* %rsi */
211 AMD64_RDI_REGNUM, /* %rdi */
212 AMD64_R8_REGNUM, /* %r8 */
213 AMD64_R9_REGNUM, /* %r9 */
214 AMD64_R10_REGNUM, /* %r10 */
215 AMD64_R11_REGNUM, /* %r11 */
216 AMD64_R12_REGNUM, /* %r12 */
217 AMD64_R13_REGNUM, /* %r13 */
218 AMD64_R14_REGNUM, /* %r14 */
219 AMD64_R15_REGNUM /* %r15 */
222 static const int amd64_arch_regmap_len =
223 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
225 /* Convert architectural register number REG to the appropriate register
226 number used by GDB. */
229 amd64_arch_reg_to_regnum (int reg)
231 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
233 return amd64_arch_regmap[reg];
236 /* Register names for byte pseudo-registers. */
238 static const char *amd64_byte_names[] =
240 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
241 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
242 "ah", "bh", "ch", "dh"
245 /* Number of lower byte registers. */
246 #define AMD64_NUM_LOWER_BYTE_REGS 16
248 /* Register names for word pseudo-registers. */
250 static const char *amd64_word_names[] =
252 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
253 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
256 /* Register names for dword pseudo-registers. */
258 static const char *amd64_dword_names[] =
260 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
261 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
265 /* Return the name of register REGNUM. */
268 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
270 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
271 if (i386_byte_regnum_p (gdbarch, regnum))
272 return amd64_byte_names[regnum - tdep->al_regnum];
273 else if (i386_ymm_regnum_p (gdbarch, regnum))
274 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
275 else if (i386_word_regnum_p (gdbarch, regnum))
276 return amd64_word_names[regnum - tdep->ax_regnum];
277 else if (i386_dword_regnum_p (gdbarch, regnum))
278 return amd64_dword_names[regnum - tdep->eax_regnum];
280 return i386_pseudo_register_name (gdbarch, regnum);
283 static struct value *
284 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
285 struct regcache *regcache,
288 gdb_byte raw_buf[MAX_REGISTER_SIZE];
289 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
290 enum register_status status;
291 struct value *result_value;
294 result_value = allocate_value (register_type (gdbarch, regnum));
295 VALUE_LVAL (result_value) = lval_register;
296 VALUE_REGNUM (result_value) = regnum;
297 buf = value_contents_raw (result_value);
299 if (i386_byte_regnum_p (gdbarch, regnum))
301 int gpnum = regnum - tdep->al_regnum;
303 /* Extract (always little endian). */
304 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
306 /* Special handling for AH, BH, CH, DH. */
307 status = regcache_raw_read (regcache,
308 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
310 if (status == REG_VALID)
311 memcpy (buf, raw_buf + 1, 1);
313 mark_value_bytes_unavailable (result_value, 0,
314 TYPE_LENGTH (value_type (result_value)));
318 status = regcache_raw_read (regcache, gpnum, raw_buf);
319 if (status == REG_VALID)
320 memcpy (buf, raw_buf, 1);
322 mark_value_bytes_unavailable (result_value, 0,
323 TYPE_LENGTH (value_type (result_value)));
326 else if (i386_dword_regnum_p (gdbarch, regnum))
328 int gpnum = regnum - tdep->eax_regnum;
329 /* Extract (always little endian). */
330 status = regcache_raw_read (regcache, gpnum, raw_buf);
331 if (status == REG_VALID)
332 memcpy (buf, raw_buf, 4);
334 mark_value_bytes_unavailable (result_value, 0,
335 TYPE_LENGTH (value_type (result_value)));
338 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
345 amd64_pseudo_register_write (struct gdbarch *gdbarch,
346 struct regcache *regcache,
347 int regnum, const gdb_byte *buf)
349 gdb_byte raw_buf[MAX_REGISTER_SIZE];
350 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
352 if (i386_byte_regnum_p (gdbarch, regnum))
354 int gpnum = regnum - tdep->al_regnum;
356 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
358 /* Read ... AH, BH, CH, DH. */
359 regcache_raw_read (regcache,
360 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
361 /* ... Modify ... (always little endian). */
362 memcpy (raw_buf + 1, buf, 1);
364 regcache_raw_write (regcache,
365 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
370 regcache_raw_read (regcache, gpnum, raw_buf);
371 /* ... Modify ... (always little endian). */
372 memcpy (raw_buf, buf, 1);
374 regcache_raw_write (regcache, gpnum, raw_buf);
377 else if (i386_dword_regnum_p (gdbarch, regnum))
379 int gpnum = regnum - tdep->eax_regnum;
382 regcache_raw_read (regcache, gpnum, raw_buf);
383 /* ... Modify ... (always little endian). */
384 memcpy (raw_buf, buf, 4);
386 regcache_raw_write (regcache, gpnum, raw_buf);
389 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
394 /* Return the union class of CLASS1 and CLASS2. See the psABI for
397 static enum amd64_reg_class
398 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
400 /* Rule (a): If both classes are equal, this is the resulting class. */
401 if (class1 == class2)
404 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
405 is the other class. */
406 if (class1 == AMD64_NO_CLASS)
408 if (class2 == AMD64_NO_CLASS)
411 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
412 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
415 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
416 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
417 return AMD64_INTEGER;
419 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
420 MEMORY is used as class. */
421 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
422 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
423 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
426 /* Rule (f): Otherwise class SSE is used. */
430 /* Return non-zero if TYPE is a non-POD structure or union type. */
433 amd64_non_pod_p (struct type *type)
435 /* ??? A class with a base class certainly isn't POD, but does this
436 catch all non-POD structure types? */
437 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
443 /* Classify TYPE according to the rules for aggregate (structures and
444 arrays) and union types, and store the result in CLASS. */
447 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
449 /* 1. If the size of an object is larger than two eightbytes, or in
450 C++, is a non-POD structure or union type, or contains
451 unaligned fields, it has class memory. */
452 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
454 class[0] = class[1] = AMD64_MEMORY;
458 /* 2. Both eightbytes get initialized to class NO_CLASS. */
459 class[0] = class[1] = AMD64_NO_CLASS;
461 /* 3. Each field of an object is classified recursively so that
462 always two fields are considered. The resulting class is
463 calculated according to the classes of the fields in the
466 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
468 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
470 /* All fields in an array have the same type. */
471 amd64_classify (subtype, class);
472 if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS)
479 /* Structure or union. */
480 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
481 || TYPE_CODE (type) == TYPE_CODE_UNION);
483 for (i = 0; i < TYPE_NFIELDS (type); i++)
485 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
486 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
487 enum amd64_reg_class subclass[2];
488 int bitsize = TYPE_FIELD_BITSIZE (type, i);
492 bitsize = TYPE_LENGTH (subtype) * 8;
493 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
495 /* Ignore static fields. */
496 if (field_is_static (&TYPE_FIELD (type, i)))
499 gdb_assert (pos == 0 || pos == 1);
501 amd64_classify (subtype, subclass);
502 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
503 if (bitsize <= 64 && pos == 0 && endpos == 1)
504 /* This is a bit of an odd case: We have a field that would
505 normally fit in one of the two eightbytes, except that
506 it is placed in a way that this field straddles them.
507 This has been seen with a structure containing an array.
509 The ABI is a bit unclear in this case, but we assume that
510 this field's class (stored in subclass[0]) must also be merged
511 into class[1]. In other words, our field has a piece stored
512 in the second eight-byte, and thus its class applies to
513 the second eight-byte as well.
515 In the case where the field length exceeds 8 bytes,
516 it should not be necessary to merge the field class
517 into class[1]. As LEN > 8, subclass[1] is necessarily
518 different from AMD64_NO_CLASS. If subclass[1] is equal
519 to subclass[0], then the normal class[1]/subclass[1]
520 merging will take care of everything. For subclass[1]
521 to be different from subclass[0], I can only see the case
522 where we have a SSE/SSEUP or X87/X87UP pair, which both
523 use up all 16 bytes of the aggregate, and are already
524 handled just fine (because each portion sits on its own
526 class[1] = amd64_merge_classes (class[1], subclass[0]);
528 class[1] = amd64_merge_classes (class[1], subclass[1]);
532 /* 4. Then a post merger cleanup is done: */
534 /* Rule (a): If one of the classes is MEMORY, the whole argument is
536 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
537 class[0] = class[1] = AMD64_MEMORY;
539 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
541 if (class[0] == AMD64_SSEUP)
542 class[0] = AMD64_SSE;
543 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
544 class[1] = AMD64_SSE;
547 /* Classify TYPE, and store the result in CLASS. */
550 amd64_classify (struct type *type, enum amd64_reg_class class[2])
552 enum type_code code = TYPE_CODE (type);
553 int len = TYPE_LENGTH (type);
555 class[0] = class[1] = AMD64_NO_CLASS;
557 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
558 long, long long, and pointers are in the INTEGER class. Similarly,
559 range types, used by languages such as Ada, are also in the INTEGER
561 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
562 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
563 || code == TYPE_CODE_CHAR
564 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
565 && (len == 1 || len == 2 || len == 4 || len == 8))
566 class[0] = AMD64_INTEGER;
568 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
570 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
571 && (len == 4 || len == 8))
573 class[0] = AMD64_SSE;
575 /* Arguments of types __float128, _Decimal128 and __m128 are split into
576 two halves. The least significant ones belong to class SSE, the most
577 significant one to class SSEUP. */
578 else if (code == TYPE_CODE_DECFLOAT && len == 16)
579 /* FIXME: __float128, __m128. */
580 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
582 /* The 64-bit mantissa of arguments of type long double belongs to
583 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
585 else if (code == TYPE_CODE_FLT && len == 16)
586 /* Class X87 and X87UP. */
587 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
590 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
591 || code == TYPE_CODE_UNION)
592 amd64_classify_aggregate (type, class);
595 static enum return_value_convention
596 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
597 struct type *type, struct regcache *regcache,
598 gdb_byte *readbuf, const gdb_byte *writebuf)
600 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
601 enum amd64_reg_class class[2];
602 int len = TYPE_LENGTH (type);
603 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
604 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
609 gdb_assert (!(readbuf && writebuf));
610 gdb_assert (tdep->classify);
612 /* 1. Classify the return type with the classification algorithm. */
613 tdep->classify (type, class);
615 /* 2. If the type has class MEMORY, then the caller provides space
616 for the return value and passes the address of this storage in
617 %rdi as if it were the first argument to the function. In effect,
618 this address becomes a hidden first argument.
620 On return %rax will contain the address that has been passed in
621 by the caller in %rdi. */
622 if (class[0] == AMD64_MEMORY)
624 /* As indicated by the comment above, the ABI guarantees that we
625 can always find the return value just after the function has
632 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
633 read_memory (addr, readbuf, TYPE_LENGTH (type));
636 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
639 gdb_assert (class[1] != AMD64_MEMORY);
640 gdb_assert (TYPE_LENGTH (type) <= 16);
642 for (i = 0; len > 0; i++, len -= 8)
650 /* 3. If the class is INTEGER, the next available register
651 of the sequence %rax, %rdx is used. */
652 regnum = integer_regnum[integer_reg++];
656 /* 4. If the class is SSE, the next available SSE register
657 of the sequence %xmm0, %xmm1 is used. */
658 regnum = sse_regnum[sse_reg++];
662 /* 5. If the class is SSEUP, the eightbyte is passed in the
663 upper half of the last used SSE register. */
664 gdb_assert (sse_reg > 0);
665 regnum = sse_regnum[sse_reg - 1];
670 /* 6. If the class is X87, the value is returned on the X87
671 stack in %st0 as 80-bit x87 number. */
672 regnum = AMD64_ST0_REGNUM;
674 i387_return_value (gdbarch, regcache);
678 /* 7. If the class is X87UP, the value is returned together
679 with the previous X87 value in %st0. */
680 gdb_assert (i > 0 && class[0] == AMD64_X87);
681 regnum = AMD64_ST0_REGNUM;
690 gdb_assert (!"Unexpected register class.");
693 gdb_assert (regnum != -1);
696 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
699 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
703 return RETURN_VALUE_REGISTER_CONVENTION;
708 amd64_push_arguments (struct regcache *regcache, int nargs,
709 struct value **args, CORE_ADDR sp, int struct_return)
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
712 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
713 int *integer_regs = tdep->call_dummy_integer_regs;
714 int num_integer_regs = tdep->call_dummy_num_integer_regs;
716 static int sse_regnum[] =
718 /* %xmm0 ... %xmm7 */
719 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
720 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
721 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
722 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
724 struct value **stack_args = alloca (nargs * sizeof (struct value *));
725 /* An array that mirrors the stack_args array. For all arguments
726 that are passed by MEMORY, if that argument's address also needs
727 to be stored in a register, the ARG_ADDR_REGNO array will contain
728 that register number (or a negative value otherwise). */
729 int *arg_addr_regno = alloca (nargs * sizeof (int));
730 int num_stack_args = 0;
731 int num_elements = 0;
737 gdb_assert (tdep->classify);
739 /* Reserve a register for the "hidden" argument. */
743 for (i = 0; i < nargs; i++)
745 struct type *type = value_type (args[i]);
746 int len = TYPE_LENGTH (type);
747 enum amd64_reg_class class[2];
748 int needed_integer_regs = 0;
749 int needed_sse_regs = 0;
752 /* Classify argument. */
753 tdep->classify (type, class);
755 /* Calculate the number of integer and SSE registers needed for
757 for (j = 0; j < 2; j++)
759 if (class[j] == AMD64_INTEGER)
760 needed_integer_regs++;
761 else if (class[j] == AMD64_SSE)
765 /* Check whether enough registers are available, and if the
766 argument should be passed in registers at all. */
767 if (integer_reg + needed_integer_regs > num_integer_regs
768 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
769 || (needed_integer_regs == 0 && needed_sse_regs == 0))
771 /* The argument will be passed on the stack. */
772 num_elements += ((len + 7) / 8);
773 stack_args[num_stack_args] = args[i];
774 /* If this is an AMD64_MEMORY argument whose address must also
775 be passed in one of the integer registers, reserve that
776 register and associate this value to that register so that
777 we can store the argument address as soon as we know it. */
778 if (class[0] == AMD64_MEMORY
779 && tdep->memory_args_by_pointer
780 && integer_reg < tdep->call_dummy_num_integer_regs)
781 arg_addr_regno[num_stack_args] =
782 tdep->call_dummy_integer_regs[integer_reg++];
784 arg_addr_regno[num_stack_args] = -1;
789 /* The argument will be passed in registers. */
790 const gdb_byte *valbuf = value_contents (args[i]);
793 gdb_assert (len <= 16);
795 for (j = 0; len > 0; j++, len -= 8)
803 regnum = integer_regs[integer_reg++];
807 regnum = sse_regnum[sse_reg++];
811 gdb_assert (sse_reg > 0);
812 regnum = sse_regnum[sse_reg - 1];
817 gdb_assert (!"Unexpected register class.");
820 gdb_assert (regnum != -1);
821 memset (buf, 0, sizeof buf);
822 memcpy (buf, valbuf + j * 8, min (len, 8));
823 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
828 /* Allocate space for the arguments on the stack. */
829 sp -= num_elements * 8;
831 /* The psABI says that "The end of the input argument area shall be
832 aligned on a 16 byte boundary." */
835 /* Write out the arguments to the stack. */
836 for (i = 0; i < num_stack_args; i++)
838 struct type *type = value_type (stack_args[i]);
839 const gdb_byte *valbuf = value_contents (stack_args[i]);
840 CORE_ADDR arg_addr = sp + element * 8;
842 write_memory (arg_addr, valbuf, TYPE_LENGTH (type));
843 if (arg_addr_regno[i] >= 0)
845 /* We also need to store the address of that argument in
846 the given register. */
848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
850 store_unsigned_integer (buf, 8, byte_order, arg_addr);
851 regcache_cooked_write (regcache, arg_addr_regno[i], buf);
853 element += ((TYPE_LENGTH (type) + 7) / 8);
856 /* The psABI says that "For calls that may call functions that use
857 varargs or stdargs (prototype-less calls or calls to functions
858 containing ellipsis (...) in the declaration) %al is used as
859 hidden argument to specify the number of SSE registers used. */
860 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
865 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
866 struct regcache *regcache, CORE_ADDR bp_addr,
867 int nargs, struct value **args, CORE_ADDR sp,
868 int struct_return, CORE_ADDR struct_addr)
870 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
871 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
874 /* Pass arguments. */
875 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
877 /* Pass "hidden" argument". */
880 /* The "hidden" argument is passed throught the first argument
882 const int arg_regnum = tdep->call_dummy_integer_regs[0];
884 store_unsigned_integer (buf, 8, byte_order, struct_addr);
885 regcache_cooked_write (regcache, arg_regnum, buf);
888 /* Reserve some memory on the stack for the integer-parameter registers,
889 if required by the ABI. */
890 if (tdep->integer_param_regs_saved_in_caller_frame)
891 sp -= tdep->call_dummy_num_integer_regs * 8;
893 /* Store return address. */
895 store_unsigned_integer (buf, 8, byte_order, bp_addr);
896 write_memory (sp, buf, 8);
898 /* Finally, update the stack pointer... */
899 store_unsigned_integer (buf, 8, byte_order, sp);
900 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
902 /* ...and fake a frame pointer. */
903 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
908 /* Displaced instruction handling. */
910 /* A partially decoded instruction.
911 This contains enough details for displaced stepping purposes. */
915 /* The number of opcode bytes. */
917 /* The offset of the rex prefix or -1 if not present. */
919 /* The offset to the first opcode byte. */
921 /* The offset to the modrm byte or -1 if not present. */
924 /* The raw instruction. */
928 struct displaced_step_closure
930 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
935 /* Details of the instruction. */
936 struct amd64_insn insn_details;
938 /* Amount of space allocated to insn_buf. */
941 /* The possibly modified insn.
942 This is a variable-length field. */
943 gdb_byte insn_buf[1];
946 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
947 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
948 at which point delete these in favor of libopcodes' versions). */
950 static const unsigned char onebyte_has_modrm[256] = {
951 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
952 /* ------------------------------- */
953 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
954 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
955 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
956 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
957 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
958 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
959 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
960 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
961 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
962 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
963 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
964 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
965 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
966 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
967 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
968 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
969 /* ------------------------------- */
970 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
973 static const unsigned char twobyte_has_modrm[256] = {
974 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
975 /* ------------------------------- */
976 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
977 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
978 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
979 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
980 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
981 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
982 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
983 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
984 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
985 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
986 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
987 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
988 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
989 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
990 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
991 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
992 /* ------------------------------- */
993 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
996 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
999 rex_prefix_p (gdb_byte pfx)
1001 return REX_PREFIX_P (pfx);
1004 /* Skip the legacy instruction prefixes in INSN.
1005 We assume INSN is properly sentineled so we don't have to worry
1006 about falling off the end of the buffer. */
1009 amd64_skip_prefixes (gdb_byte *insn)
1015 case DATA_PREFIX_OPCODE:
1016 case ADDR_PREFIX_OPCODE:
1017 case CS_PREFIX_OPCODE:
1018 case DS_PREFIX_OPCODE:
1019 case ES_PREFIX_OPCODE:
1020 case FS_PREFIX_OPCODE:
1021 case GS_PREFIX_OPCODE:
1022 case SS_PREFIX_OPCODE:
1023 case LOCK_PREFIX_OPCODE:
1024 case REPE_PREFIX_OPCODE:
1025 case REPNE_PREFIX_OPCODE:
1037 /* Return an integer register (other than RSP) that is unused as an input
1039 In order to not require adding a rex prefix if the insn doesn't already
1040 have one, the result is restricted to RAX ... RDI, sans RSP.
1041 The register numbering of the result follows architecture ordering,
1045 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1047 /* 1 bit for each reg */
1048 int used_regs_mask = 0;
1050 /* There can be at most 3 int regs used as inputs in an insn, and we have
1051 7 to choose from (RAX ... RDI, sans RSP).
1052 This allows us to take a conservative approach and keep things simple.
1053 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1054 that implicitly specify RAX. */
1057 used_regs_mask |= 1 << EAX_REG_NUM;
1058 /* Similarily avoid RDX, implicit operand in divides. */
1059 used_regs_mask |= 1 << EDX_REG_NUM;
1061 used_regs_mask |= 1 << ESP_REG_NUM;
1063 /* If the opcode is one byte long and there's no ModRM byte,
1064 assume the opcode specifies a register. */
1065 if (details->opcode_len == 1 && details->modrm_offset == -1)
1066 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1068 /* Mark used regs in the modrm/sib bytes. */
1069 if (details->modrm_offset != -1)
1071 int modrm = details->raw_insn[details->modrm_offset];
1072 int mod = MODRM_MOD_FIELD (modrm);
1073 int reg = MODRM_REG_FIELD (modrm);
1074 int rm = MODRM_RM_FIELD (modrm);
1075 int have_sib = mod != 3 && rm == 4;
1077 /* Assume the reg field of the modrm byte specifies a register. */
1078 used_regs_mask |= 1 << reg;
1082 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1083 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1084 used_regs_mask |= 1 << base;
1085 used_regs_mask |= 1 << idx;
1089 used_regs_mask |= 1 << rm;
1093 gdb_assert (used_regs_mask < 256);
1094 gdb_assert (used_regs_mask != 255);
1096 /* Finally, find a free reg. */
1100 for (i = 0; i < 8; ++i)
1102 if (! (used_regs_mask & (1 << i)))
1106 /* We shouldn't get here. */
1107 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1111 /* Extract the details of INSN that we need. */
1114 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1116 gdb_byte *start = insn;
1119 details->raw_insn = insn;
1121 details->opcode_len = -1;
1122 details->rex_offset = -1;
1123 details->opcode_offset = -1;
1124 details->modrm_offset = -1;
1126 /* Skip legacy instruction prefixes. */
1127 insn = amd64_skip_prefixes (insn);
1129 /* Skip REX instruction prefix. */
1130 if (rex_prefix_p (*insn))
1132 details->rex_offset = insn - start;
1136 details->opcode_offset = insn - start;
1138 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1140 /* Two or three-byte opcode. */
1142 need_modrm = twobyte_has_modrm[*insn];
1144 /* Check for three-byte opcode. */
1154 details->opcode_len = 3;
1157 details->opcode_len = 2;
1163 /* One-byte opcode. */
1164 need_modrm = onebyte_has_modrm[*insn];
1165 details->opcode_len = 1;
1171 details->modrm_offset = insn - start;
1175 /* Update %rip-relative addressing in INSN.
1177 %rip-relative addressing only uses a 32-bit displacement.
1178 32 bits is not enough to be guaranteed to cover the distance between where
1179 the real instruction is and where its copy is.
1180 Convert the insn to use base+disp addressing.
1181 We set base = pc + insn_length so we can leave disp unchanged. */
1184 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1185 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1188 const struct amd64_insn *insn_details = &dsc->insn_details;
1189 int modrm_offset = insn_details->modrm_offset;
1190 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1194 int arch_tmp_regno, tmp_regno;
1195 ULONGEST orig_value;
1197 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1200 /* Compute the rip-relative address. */
1201 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1202 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1203 dsc->max_len, from);
1204 rip_base = from + insn_length;
1206 /* We need a register to hold the address.
1207 Pick one not used in the insn.
1208 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1209 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1210 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1212 /* REX.B should be unset as we were using rip-relative addressing,
1213 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1214 if (insn_details->rex_offset != -1)
1215 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1217 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1218 dsc->tmp_regno = tmp_regno;
1219 dsc->tmp_save = orig_value;
1222 /* Convert the ModRM field to be base+disp. */
1223 dsc->insn_buf[modrm_offset] &= ~0xc7;
1224 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1226 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1228 if (debug_displaced)
1229 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1230 "displaced: using temp reg %d, old value %s, new value %s\n",
1231 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1232 paddress (gdbarch, rip_base));
1236 fixup_displaced_copy (struct gdbarch *gdbarch,
1237 struct displaced_step_closure *dsc,
1238 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1240 const struct amd64_insn *details = &dsc->insn_details;
1242 if (details->modrm_offset != -1)
1244 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1246 if ((modrm & 0xc7) == 0x05)
1248 /* The insn uses rip-relative addressing.
1250 fixup_riprel (gdbarch, dsc, from, to, regs);
1255 struct displaced_step_closure *
1256 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1257 CORE_ADDR from, CORE_ADDR to,
1258 struct regcache *regs)
1260 int len = gdbarch_max_insn_length (gdbarch);
1261 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1262 continually watch for running off the end of the buffer. */
1263 int fixup_sentinel_space = len;
1264 struct displaced_step_closure *dsc =
1265 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1266 gdb_byte *buf = &dsc->insn_buf[0];
1267 struct amd64_insn *details = &dsc->insn_details;
1270 dsc->max_len = len + fixup_sentinel_space;
1272 read_memory (from, buf, len);
1274 /* Set up the sentinel space so we don't have to worry about running
1275 off the end of the buffer. An excessive number of leading prefixes
1276 could otherwise cause this. */
1277 memset (buf + len, 0, fixup_sentinel_space);
1279 amd64_get_insn_details (buf, details);
1281 /* GDB may get control back after the insn after the syscall.
1282 Presumably this is a kernel bug.
1283 If this is a syscall, make sure there's a nop afterwards. */
1287 if (amd64_syscall_p (details, &syscall_length))
1288 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1291 /* Modify the insn to cope with the address where it will be executed from.
1292 In particular, handle any rip-relative addressing. */
1293 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1295 write_memory (to, buf, len);
1297 if (debug_displaced)
1299 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1300 paddress (gdbarch, from), paddress (gdbarch, to));
1301 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1308 amd64_absolute_jmp_p (const struct amd64_insn *details)
1310 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1312 if (insn[0] == 0xff)
1314 /* jump near, absolute indirect (/4) */
1315 if ((insn[1] & 0x38) == 0x20)
1318 /* jump far, absolute indirect (/5) */
1319 if ((insn[1] & 0x38) == 0x28)
1327 amd64_absolute_call_p (const struct amd64_insn *details)
1329 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1331 if (insn[0] == 0xff)
1333 /* Call near, absolute indirect (/2) */
1334 if ((insn[1] & 0x38) == 0x10)
1337 /* Call far, absolute indirect (/3) */
1338 if ((insn[1] & 0x38) == 0x18)
1346 amd64_ret_p (const struct amd64_insn *details)
1348 /* NOTE: gcc can emit "repz ; ret". */
1349 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1353 case 0xc2: /* ret near, pop N bytes */
1354 case 0xc3: /* ret near */
1355 case 0xca: /* ret far, pop N bytes */
1356 case 0xcb: /* ret far */
1357 case 0xcf: /* iret */
1366 amd64_call_p (const struct amd64_insn *details)
1368 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1370 if (amd64_absolute_call_p (details))
1373 /* call near, relative */
1374 if (insn[0] == 0xe8)
1380 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1381 length in bytes. Otherwise, return zero. */
1384 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1386 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1388 if (insn[0] == 0x0f && insn[1] == 0x05)
1397 /* Fix up the state of registers and memory after having single-stepped
1398 a displaced instruction. */
1401 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1402 struct displaced_step_closure *dsc,
1403 CORE_ADDR from, CORE_ADDR to,
1404 struct regcache *regs)
1406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1407 /* The offset we applied to the instruction's address. */
1408 ULONGEST insn_offset = to - from;
1409 gdb_byte *insn = dsc->insn_buf;
1410 const struct amd64_insn *insn_details = &dsc->insn_details;
1412 if (debug_displaced)
1413 fprintf_unfiltered (gdb_stdlog,
1414 "displaced: fixup (%s, %s), "
1415 "insn = 0x%02x 0x%02x ...\n",
1416 paddress (gdbarch, from), paddress (gdbarch, to),
1419 /* If we used a tmp reg, restore it. */
1423 if (debug_displaced)
1424 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1425 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1426 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1429 /* The list of issues to contend with here is taken from
1430 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1431 Yay for Free Software! */
1433 /* Relocate the %rip back to the program's instruction stream,
1436 /* Except in the case of absolute or indirect jump or call
1437 instructions, or a return instruction, the new rip is relative to
1438 the displaced instruction; make it relative to the original insn.
1439 Well, signal handler returns don't need relocation either, but we use the
1440 value of %rip to recognize those; see below. */
1441 if (! amd64_absolute_jmp_p (insn_details)
1442 && ! amd64_absolute_call_p (insn_details)
1443 && ! amd64_ret_p (insn_details))
1448 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1450 /* A signal trampoline system call changes the %rip, resuming
1451 execution of the main program after the signal handler has
1452 returned. That makes them like 'return' instructions; we
1453 shouldn't relocate %rip.
1455 But most system calls don't, and we do need to relocate %rip.
1457 Our heuristic for distinguishing these cases: if stepping
1458 over the system call instruction left control directly after
1459 the instruction, the we relocate --- control almost certainly
1460 doesn't belong in the displaced copy. Otherwise, we assume
1461 the instruction has put control where it belongs, and leave
1462 it unrelocated. Goodness help us if there are PC-relative
1464 if (amd64_syscall_p (insn_details, &insn_len)
1465 && orig_rip != to + insn_len
1466 /* GDB can get control back after the insn after the syscall.
1467 Presumably this is a kernel bug.
1468 Fixup ensures its a nop, we add one to the length for it. */
1469 && orig_rip != to + insn_len + 1)
1471 if (debug_displaced)
1472 fprintf_unfiltered (gdb_stdlog,
1473 "displaced: syscall changed %%rip; "
1474 "not relocating\n");
1478 ULONGEST rip = orig_rip - insn_offset;
1480 /* If we just stepped over a breakpoint insn, we don't backup
1481 the pc on purpose; this is to match behaviour without
1484 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1486 if (debug_displaced)
1487 fprintf_unfiltered (gdb_stdlog,
1489 "relocated %%rip from %s to %s\n",
1490 paddress (gdbarch, orig_rip),
1491 paddress (gdbarch, rip));
1495 /* If the instruction was PUSHFL, then the TF bit will be set in the
1496 pushed value, and should be cleared. We'll leave this for later,
1497 since GDB already messes up the TF flag when stepping over a
1500 /* If the instruction was a call, the return address now atop the
1501 stack is the address following the copied instruction. We need
1502 to make it the address following the original instruction. */
1503 if (amd64_call_p (insn_details))
1507 const ULONGEST retaddr_len = 8;
1509 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1510 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1511 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
1512 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1514 if (debug_displaced)
1515 fprintf_unfiltered (gdb_stdlog,
1516 "displaced: relocated return addr at %s "
1518 paddress (gdbarch, rsp),
1519 paddress (gdbarch, retaddr));
1523 /* If the instruction INSN uses RIP-relative addressing, return the
1524 offset into the raw INSN where the displacement to be adjusted is
1525 found. Returns 0 if the instruction doesn't use RIP-relative
1529 rip_relative_offset (struct amd64_insn *insn)
1531 if (insn->modrm_offset != -1)
1533 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1535 if ((modrm & 0xc7) == 0x05)
1537 /* The displacement is found right after the ModRM byte. */
1538 return insn->modrm_offset + 1;
1546 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1548 target_write_memory (*to, buf, len);
1553 amd64_relocate_instruction (struct gdbarch *gdbarch,
1554 CORE_ADDR *to, CORE_ADDR oldloc)
1556 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1557 int len = gdbarch_max_insn_length (gdbarch);
1558 /* Extra space for sentinels. */
1559 int fixup_sentinel_space = len;
1560 gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1561 struct amd64_insn insn_details;
1563 LONGEST rel32, newrel;
1567 read_memory (oldloc, buf, len);
1569 /* Set up the sentinel space so we don't have to worry about running
1570 off the end of the buffer. An excessive number of leading prefixes
1571 could otherwise cause this. */
1572 memset (buf + len, 0, fixup_sentinel_space);
1575 amd64_get_insn_details (insn, &insn_details);
1577 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1579 /* Skip legacy instruction prefixes. */
1580 insn = amd64_skip_prefixes (insn);
1582 /* Adjust calls with 32-bit relative addresses as push/jump, with
1583 the address pushed being the location where the original call in
1584 the user program would return to. */
1585 if (insn[0] == 0xe8)
1587 gdb_byte push_buf[16];
1588 unsigned int ret_addr;
1590 /* Where "ret" in the original code will return to. */
1591 ret_addr = oldloc + insn_length;
1592 push_buf[0] = 0x68; /* pushq $... */
1593 memcpy (&push_buf[1], &ret_addr, 4);
1594 /* Push the push. */
1595 append_insns (to, 5, push_buf);
1597 /* Convert the relative call to a relative jump. */
1600 /* Adjust the destination offset. */
1601 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1602 newrel = (oldloc - *to) + rel32;
1603 store_signed_integer (insn + 1, 4, byte_order, newrel);
1605 if (debug_displaced)
1606 fprintf_unfiltered (gdb_stdlog,
1607 "Adjusted insn rel32=%s at %s to"
1608 " rel32=%s at %s\n",
1609 hex_string (rel32), paddress (gdbarch, oldloc),
1610 hex_string (newrel), paddress (gdbarch, *to));
1612 /* Write the adjusted jump into its displaced location. */
1613 append_insns (to, 5, insn);
1617 offset = rip_relative_offset (&insn_details);
1620 /* Adjust jumps with 32-bit relative addresses. Calls are
1621 already handled above. */
1622 if (insn[0] == 0xe9)
1624 /* Adjust conditional jumps. */
1625 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1631 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1632 newrel = (oldloc - *to) + rel32;
1633 store_signed_integer (insn + offset, 4, byte_order, newrel);
1634 if (debug_displaced)
1635 fprintf_unfiltered (gdb_stdlog,
1636 "Adjusted insn rel32=%s at %s to"
1637 " rel32=%s at %s\n",
1638 hex_string (rel32), paddress (gdbarch, oldloc),
1639 hex_string (newrel), paddress (gdbarch, *to));
1642 /* Write the adjusted instruction into its displaced location. */
1643 append_insns (to, insn_length, buf);
1647 /* The maximum number of saved registers. This should include %rip. */
1648 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1650 struct amd64_frame_cache
1655 CORE_ADDR sp_offset;
1658 /* Saved registers. */
1659 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1663 /* Do we have a frame? */
1667 /* Initialize a frame cache. */
1670 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1677 cache->sp_offset = -8;
1680 /* Saved registers. We initialize these to -1 since zero is a valid
1681 offset (that's where %rbp is supposed to be stored).
1682 The values start out as being offsets, and are later converted to
1683 addresses (at which point -1 is interpreted as an address, still meaning
1685 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1686 cache->saved_regs[i] = -1;
1687 cache->saved_sp = 0;
1688 cache->saved_sp_reg = -1;
1690 /* Frameless until proven otherwise. */
1691 cache->frameless_p = 1;
1694 /* Allocate and initialize a frame cache. */
1696 static struct amd64_frame_cache *
1697 amd64_alloc_frame_cache (void)
1699 struct amd64_frame_cache *cache;
1701 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1702 amd64_init_frame_cache (cache);
1706 /* GCC 4.4 and later, can put code in the prologue to realign the
1707 stack pointer. Check whether PC points to such code, and update
1708 CACHE accordingly. Return the first instruction after the code
1709 sequence or CURRENT_PC, whichever is smaller. If we don't
1710 recognize the code, return PC. */
1713 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1714 struct amd64_frame_cache *cache)
1716 /* There are 2 code sequences to re-align stack before the frame
1719 1. Use a caller-saved saved register:
1725 2. Use a callee-saved saved register:
1732 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1734 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1735 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1740 int offset, offset_and;
1742 if (target_read_memory (pc, buf, sizeof buf))
1745 /* Check caller-saved saved register. The first instruction has
1746 to be "leaq 8(%rsp), %reg". */
1747 if ((buf[0] & 0xfb) == 0x48
1752 /* MOD must be binary 10 and R/M must be binary 100. */
1753 if ((buf[2] & 0xc7) != 0x44)
1756 /* REG has register number. */
1757 reg = (buf[2] >> 3) & 7;
1759 /* Check the REX.R bit. */
1767 /* Check callee-saved saved register. The first instruction
1768 has to be "pushq %reg". */
1770 if ((buf[0] & 0xf8) == 0x50)
1772 else if ((buf[0] & 0xf6) == 0x40
1773 && (buf[1] & 0xf8) == 0x50)
1775 /* Check the REX.B bit. */
1776 if ((buf[0] & 1) != 0)
1785 reg += buf[offset] & 0x7;
1789 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1790 if ((buf[offset] & 0xfb) != 0x48
1791 || buf[offset + 1] != 0x8d
1792 || buf[offset + 3] != 0x24
1793 || buf[offset + 4] != 0x10)
1796 /* MOD must be binary 10 and R/M must be binary 100. */
1797 if ((buf[offset + 2] & 0xc7) != 0x44)
1800 /* REG has register number. */
1801 r = (buf[offset + 2] >> 3) & 7;
1803 /* Check the REX.R bit. */
1804 if (buf[offset] == 0x4c)
1807 /* Registers in pushq and leaq have to be the same. */
1814 /* Rigister can't be %rsp nor %rbp. */
1815 if (reg == 4 || reg == 5)
1818 /* The next instruction has to be "andq $-XXX, %rsp". */
1819 if (buf[offset] != 0x48
1820 || buf[offset + 2] != 0xe4
1821 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1824 offset_and = offset;
1825 offset += buf[offset + 1] == 0x81 ? 7 : 4;
1827 /* The next instruction has to be "pushq -8(%reg)". */
1829 if (buf[offset] == 0xff)
1831 else if ((buf[offset] & 0xf6) == 0x40
1832 && buf[offset + 1] == 0xff)
1834 /* Check the REX.B bit. */
1835 if ((buf[offset] & 0x1) != 0)
1842 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1844 if (buf[offset + 1] != 0xf8
1845 || (buf[offset] & 0xf8) != 0x70)
1848 /* R/M has register. */
1849 r += buf[offset] & 7;
1851 /* Registers in leaq and pushq have to be the same. */
1855 if (current_pc > pc + offset_and)
1856 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
1858 return min (pc + offset + 2, current_pc);
1861 /* Similar to amd64_analyze_stack_align for x32. */
1864 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1865 struct amd64_frame_cache *cache)
1867 /* There are 2 code sequences to re-align stack before the frame
1870 1. Use a caller-saved saved register:
1878 [addr32] leal 8(%rsp), %reg
1880 [addr32] pushq -8(%reg)
1882 2. Use a callee-saved saved register:
1892 [addr32] leal 16(%rsp), %reg
1894 [addr32] pushq -8(%reg)
1896 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1898 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1899 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1901 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1903 0x83 0xe4 0xf0 andl $-16, %esp
1904 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1909 int offset, offset_and;
1911 if (target_read_memory (pc, buf, sizeof buf))
1914 /* Skip optional addr32 prefix. */
1915 offset = buf[0] == 0x67 ? 1 : 0;
1917 /* Check caller-saved saved register. The first instruction has
1918 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
1919 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
1920 && buf[offset + 1] == 0x8d
1921 && buf[offset + 3] == 0x24
1922 && buf[offset + 4] == 0x8)
1924 /* MOD must be binary 10 and R/M must be binary 100. */
1925 if ((buf[offset + 2] & 0xc7) != 0x44)
1928 /* REG has register number. */
1929 reg = (buf[offset + 2] >> 3) & 7;
1931 /* Check the REX.R bit. */
1932 if ((buf[offset] & 0x4) != 0)
1939 /* Check callee-saved saved register. The first instruction
1940 has to be "pushq %reg". */
1942 if ((buf[offset] & 0xf6) == 0x40
1943 && (buf[offset + 1] & 0xf8) == 0x50)
1945 /* Check the REX.B bit. */
1946 if ((buf[offset] & 1) != 0)
1951 else if ((buf[offset] & 0xf8) != 0x50)
1955 reg += buf[offset] & 0x7;
1959 /* Skip optional addr32 prefix. */
1960 if (buf[offset] == 0x67)
1963 /* The next instruction has to be "leaq 16(%rsp), %reg" or
1964 "leal 16(%rsp), %reg". */
1965 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
1966 || buf[offset + 1] != 0x8d
1967 || buf[offset + 3] != 0x24
1968 || buf[offset + 4] != 0x10)
1971 /* MOD must be binary 10 and R/M must be binary 100. */
1972 if ((buf[offset + 2] & 0xc7) != 0x44)
1975 /* REG has register number. */
1976 r = (buf[offset + 2] >> 3) & 7;
1978 /* Check the REX.R bit. */
1979 if ((buf[offset] & 0x4) != 0)
1982 /* Registers in pushq and leaq have to be the same. */
1989 /* Rigister can't be %rsp nor %rbp. */
1990 if (reg == 4 || reg == 5)
1993 /* The next instruction may be "andq $-XXX, %rsp" or
1994 "andl $-XXX, %esp". */
1995 if (buf[offset] != 0x48)
1998 if (buf[offset + 2] != 0xe4
1999 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2002 offset_and = offset;
2003 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2005 /* Skip optional addr32 prefix. */
2006 if (buf[offset] == 0x67)
2009 /* The next instruction has to be "pushq -8(%reg)". */
2011 if (buf[offset] == 0xff)
2013 else if ((buf[offset] & 0xf6) == 0x40
2014 && buf[offset + 1] == 0xff)
2016 /* Check the REX.B bit. */
2017 if ((buf[offset] & 0x1) != 0)
2024 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2026 if (buf[offset + 1] != 0xf8
2027 || (buf[offset] & 0xf8) != 0x70)
2030 /* R/M has register. */
2031 r += buf[offset] & 7;
2033 /* Registers in leaq and pushq have to be the same. */
2037 if (current_pc > pc + offset_and)
2038 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2040 return min (pc + offset + 2, current_pc);
2043 /* Do a limited analysis of the prologue at PC and update CACHE
2044 accordingly. Bail out early if CURRENT_PC is reached. Return the
2045 address where the analysis stopped.
2047 We will handle only functions beginning with:
2050 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2052 or (for the X32 ABI):
2055 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2057 Any function that doesn't start with one of these sequences will be
2058 assumed to have no prologue and thus no valid frame pointer in
2062 amd64_analyze_prologue (struct gdbarch *gdbarch,
2063 CORE_ADDR pc, CORE_ADDR current_pc,
2064 struct amd64_frame_cache *cache)
2066 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2067 /* There are two variations of movq %rsp, %rbp. */
2068 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2069 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2070 /* Ditto for movl %esp, %ebp. */
2071 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2072 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2077 if (current_pc <= pc)
2080 if (gdbarch_ptr_bit (gdbarch) == 32)
2081 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2083 pc = amd64_analyze_stack_align (pc, current_pc, cache);
2085 op = read_memory_unsigned_integer (pc, 1, byte_order);
2087 if (op == 0x55) /* pushq %rbp */
2089 /* Take into account that we've executed the `pushq %rbp' that
2090 starts this instruction sequence. */
2091 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2092 cache->sp_offset += 8;
2094 /* If that's all, return now. */
2095 if (current_pc <= pc + 1)
2098 read_memory (pc + 1, buf, 3);
2100 /* Check for `movq %rsp, %rbp'. */
2101 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2102 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2104 /* OK, we actually have a frame. */
2105 cache->frameless_p = 0;
2109 /* For X32, also check for `movq %esp, %ebp'. */
2110 if (gdbarch_ptr_bit (gdbarch) == 32)
2112 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2113 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2115 /* OK, we actually have a frame. */
2116 cache->frameless_p = 0;
2127 /* Work around false termination of prologue - GCC PR debug/48827.
2129 START_PC is the first instruction of a function, PC is its minimal already
2130 determined advanced address. Function returns PC if it has nothing to do.
2134 <-- here is 0 lines advance - the false prologue end marker.
2135 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2136 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2137 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2138 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2139 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2140 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2141 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2142 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2146 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2148 struct symtab_and_line start_pc_sal, next_sal;
2149 gdb_byte buf[4 + 8 * 7];
2155 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2156 if (start_pc_sal.symtab == NULL
2157 || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6
2158 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2161 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2162 if (next_sal.line != start_pc_sal.line)
2165 /* START_PC can be from overlayed memory, ignored here. */
2166 if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2170 if (buf[0] != 0x84 || buf[1] != 0xc0)
2177 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2179 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2180 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2181 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2185 if ((buf[offset + 2] & 0xc0) == 0x40)
2187 /* 8-bit displacement. */
2191 else if ((buf[offset + 2] & 0xc0) == 0x80)
2193 /* 32-bit displacement. */
2201 if (offset - 4 != buf[3])
2204 return next_sal.end;
2207 /* Return PC of first real instruction. */
2210 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2212 struct amd64_frame_cache cache;
2215 amd64_init_frame_cache (&cache);
2216 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2218 if (cache.frameless_p)
2221 return amd64_skip_xmm_prologue (pc, start_pc);
2225 /* Normal frames. */
2228 amd64_frame_cache_1 (struct frame_info *this_frame,
2229 struct amd64_frame_cache *cache)
2231 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2232 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2236 cache->pc = get_frame_func (this_frame);
2238 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2241 if (cache->frameless_p)
2243 /* We didn't find a valid frame. If we're at the start of a
2244 function, or somewhere half-way its prologue, the function's
2245 frame probably hasn't been fully setup yet. Try to
2246 reconstruct the base address for the stack frame by looking
2247 at the stack pointer. For truly "frameless" functions this
2250 if (cache->saved_sp_reg != -1)
2252 /* Stack pointer has been saved. */
2253 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2254 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2256 /* We're halfway aligning the stack. */
2257 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2258 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2260 /* This will be added back below. */
2261 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2265 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2266 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2272 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2273 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2276 /* Now that we have the base address for the stack frame we can
2277 calculate the value of %rsp in the calling frame. */
2278 cache->saved_sp = cache->base + 16;
2280 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2281 frame we find it at the same offset from the reconstructed base
2282 address. If we're halfway aligning the stack, %rip is handled
2283 differently (see above). */
2284 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2285 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2287 /* Adjust all the saved registers such that they contain addresses
2288 instead of offsets. */
2289 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2290 if (cache->saved_regs[i] != -1)
2291 cache->saved_regs[i] += cache->base;
2296 static struct amd64_frame_cache *
2297 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2299 volatile struct gdb_exception ex;
2300 struct amd64_frame_cache *cache;
2305 cache = amd64_alloc_frame_cache ();
2306 *this_cache = cache;
2308 TRY_CATCH (ex, RETURN_MASK_ERROR)
2310 amd64_frame_cache_1 (this_frame, cache);
2312 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2313 throw_exception (ex);
2318 static enum unwind_stop_reason
2319 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2322 struct amd64_frame_cache *cache =
2323 amd64_frame_cache (this_frame, this_cache);
2326 return UNWIND_UNAVAILABLE;
2328 /* This marks the outermost frame. */
2329 if (cache->base == 0)
2330 return UNWIND_OUTERMOST;
2332 return UNWIND_NO_REASON;
2336 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2337 struct frame_id *this_id)
2339 struct amd64_frame_cache *cache =
2340 amd64_frame_cache (this_frame, this_cache);
2345 /* This marks the outermost frame. */
2346 if (cache->base == 0)
2349 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2352 static struct value *
2353 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2356 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2357 struct amd64_frame_cache *cache =
2358 amd64_frame_cache (this_frame, this_cache);
2360 gdb_assert (regnum >= 0);
2362 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2363 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2365 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2366 return frame_unwind_got_memory (this_frame, regnum,
2367 cache->saved_regs[regnum]);
2369 return frame_unwind_got_register (this_frame, regnum, regnum);
2372 static const struct frame_unwind amd64_frame_unwind =
2375 amd64_frame_unwind_stop_reason,
2376 amd64_frame_this_id,
2377 amd64_frame_prev_register,
2379 default_frame_sniffer
2382 /* Generate a bytecode expression to get the value of the saved PC. */
2385 amd64_gen_return_address (struct gdbarch *gdbarch,
2386 struct agent_expr *ax, struct axs_value *value,
2389 /* The following sequence assumes the traditional use of the base
2391 ax_reg (ax, AMD64_RBP_REGNUM);
2393 ax_simple (ax, aop_add);
2394 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2395 value->kind = axs_lvalue_memory;
2399 /* Signal trampolines. */
2401 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2402 64-bit variants. This would require using identical frame caches
2403 on both platforms. */
2405 static struct amd64_frame_cache *
2406 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2408 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2409 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2410 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2411 volatile struct gdb_exception ex;
2412 struct amd64_frame_cache *cache;
2420 cache = amd64_alloc_frame_cache ();
2422 TRY_CATCH (ex, RETURN_MASK_ERROR)
2424 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2425 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2427 addr = tdep->sigcontext_addr (this_frame);
2428 gdb_assert (tdep->sc_reg_offset);
2429 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2430 for (i = 0; i < tdep->sc_num_regs; i++)
2431 if (tdep->sc_reg_offset[i] != -1)
2432 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2436 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2437 throw_exception (ex);
2439 *this_cache = cache;
2443 static enum unwind_stop_reason
2444 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2447 struct amd64_frame_cache *cache =
2448 amd64_sigtramp_frame_cache (this_frame, this_cache);
2451 return UNWIND_UNAVAILABLE;
2453 return UNWIND_NO_REASON;
2457 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2458 void **this_cache, struct frame_id *this_id)
2460 struct amd64_frame_cache *cache =
2461 amd64_sigtramp_frame_cache (this_frame, this_cache);
2466 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2469 static struct value *
2470 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2471 void **this_cache, int regnum)
2473 /* Make sure we've initialized the cache. */
2474 amd64_sigtramp_frame_cache (this_frame, this_cache);
2476 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2480 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2481 struct frame_info *this_frame,
2484 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2486 /* We shouldn't even bother if we don't have a sigcontext_addr
2488 if (tdep->sigcontext_addr == NULL)
2491 if (tdep->sigtramp_p != NULL)
2493 if (tdep->sigtramp_p (this_frame))
2497 if (tdep->sigtramp_start != 0)
2499 CORE_ADDR pc = get_frame_pc (this_frame);
2501 gdb_assert (tdep->sigtramp_end != 0);
2502 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2509 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2512 amd64_sigtramp_frame_unwind_stop_reason,
2513 amd64_sigtramp_frame_this_id,
2514 amd64_sigtramp_frame_prev_register,
2516 amd64_sigtramp_frame_sniffer
2521 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2523 struct amd64_frame_cache *cache =
2524 amd64_frame_cache (this_frame, this_cache);
2529 static const struct frame_base amd64_frame_base =
2531 &amd64_frame_unwind,
2532 amd64_frame_base_address,
2533 amd64_frame_base_address,
2534 amd64_frame_base_address
2537 /* Normal frames, but in a function epilogue. */
2539 /* The epilogue is defined here as the 'ret' instruction, which will
2540 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2541 the function's stack frame. */
2544 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2547 struct symtab *symtab;
2549 symtab = find_pc_symtab (pc);
2550 if (symtab && symtab->epilogue_unwind_valid)
2553 if (target_read_memory (pc, &insn, 1))
2554 return 0; /* Can't read memory at pc. */
2556 if (insn != 0xc3) /* 'ret' instruction. */
2563 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2564 struct frame_info *this_frame,
2565 void **this_prologue_cache)
2567 if (frame_relative_level (this_frame) == 0)
2568 return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
2569 get_frame_pc (this_frame));
2574 static struct amd64_frame_cache *
2575 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2577 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2579 volatile struct gdb_exception ex;
2580 struct amd64_frame_cache *cache;
2586 cache = amd64_alloc_frame_cache ();
2587 *this_cache = cache;
2589 TRY_CATCH (ex, RETURN_MASK_ERROR)
2591 /* Cache base will be %esp plus cache->sp_offset (-8). */
2592 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2593 cache->base = extract_unsigned_integer (buf, 8,
2594 byte_order) + cache->sp_offset;
2596 /* Cache pc will be the frame func. */
2597 cache->pc = get_frame_pc (this_frame);
2599 /* The saved %esp will be at cache->base plus 16. */
2600 cache->saved_sp = cache->base + 16;
2602 /* The saved %eip will be at cache->base plus 8. */
2603 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2607 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2608 throw_exception (ex);
2613 static enum unwind_stop_reason
2614 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2617 struct amd64_frame_cache *cache
2618 = amd64_epilogue_frame_cache (this_frame, this_cache);
2621 return UNWIND_UNAVAILABLE;
2623 return UNWIND_NO_REASON;
2627 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2629 struct frame_id *this_id)
2631 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2637 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2640 static const struct frame_unwind amd64_epilogue_frame_unwind =
2643 amd64_epilogue_frame_unwind_stop_reason,
2644 amd64_epilogue_frame_this_id,
2645 amd64_frame_prev_register,
2647 amd64_epilogue_frame_sniffer
2650 static struct frame_id
2651 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2655 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2657 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2660 /* 16 byte align the SP per frame requirements. */
2663 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2665 return sp & -(CORE_ADDR)16;
2669 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2670 in the floating-point register set REGSET to register cache
2671 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2674 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2675 int regnum, const void *fpregs, size_t len)
2677 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2679 gdb_assert (len == tdep->sizeof_fpregset);
2680 amd64_supply_fxsave (regcache, regnum, fpregs);
2683 /* Collect register REGNUM from the register cache REGCACHE and store
2684 it in the buffer specified by FPREGS and LEN as described by the
2685 floating-point register set REGSET. If REGNUM is -1, do this for
2686 all registers in REGSET. */
2689 amd64_collect_fpregset (const struct regset *regset,
2690 const struct regcache *regcache,
2691 int regnum, void *fpregs, size_t len)
2693 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2695 gdb_assert (len == tdep->sizeof_fpregset);
2696 amd64_collect_fxsave (regcache, regnum, fpregs);
2699 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2702 amd64_supply_xstateregset (const struct regset *regset,
2703 struct regcache *regcache, int regnum,
2704 const void *xstateregs, size_t len)
2706 amd64_supply_xsave (regcache, regnum, xstateregs);
2709 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2712 amd64_collect_xstateregset (const struct regset *regset,
2713 const struct regcache *regcache,
2714 int regnum, void *xstateregs, size_t len)
2716 amd64_collect_xsave (regcache, regnum, xstateregs, 1);
2719 /* Return the appropriate register set for the core section identified
2720 by SECT_NAME and SECT_SIZE. */
2722 static const struct regset *
2723 amd64_regset_from_core_section (struct gdbarch *gdbarch,
2724 const char *sect_name, size_t sect_size)
2726 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2728 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2730 if (tdep->fpregset == NULL)
2731 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
2732 amd64_collect_fpregset);
2734 return tdep->fpregset;
2737 if (strcmp (sect_name, ".reg-xstate") == 0)
2739 if (tdep->xstateregset == NULL)
2740 tdep->xstateregset = regset_alloc (gdbarch,
2741 amd64_supply_xstateregset,
2742 amd64_collect_xstateregset);
2744 return tdep->xstateregset;
2747 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
2751 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2752 %rdi. We expect its value to be a pointer to the jmp_buf structure
2753 from which we extract the address that we will land at. This
2754 address is copied into PC. This routine returns non-zero on
2758 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2762 struct gdbarch *gdbarch = get_frame_arch (frame);
2763 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2764 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2766 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2767 longjmp will land. */
2768 if (jb_pc_offset == -1)
2771 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2772 jb_addr= extract_typed_address
2773 (buf, builtin_type (gdbarch)->builtin_data_ptr);
2774 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2777 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2782 static const int amd64_record_regmap[] =
2784 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2785 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2786 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2787 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2788 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2789 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2793 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2795 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2796 const struct target_desc *tdesc = info.target_desc;
2798 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2799 floating-point registers. */
2800 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2802 if (! tdesc_has_registers (tdesc))
2803 tdesc = tdesc_amd64;
2804 tdep->tdesc = tdesc;
2806 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2807 tdep->register_names = amd64_register_names;
2809 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2811 tdep->ymmh_register_names = amd64_ymmh_names;
2812 tdep->num_ymm_regs = 16;
2813 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
2816 tdep->num_byte_regs = 20;
2817 tdep->num_word_regs = 16;
2818 tdep->num_dword_regs = 16;
2819 /* Avoid wiring in the MMX registers for now. */
2820 tdep->num_mmx_regs = 0;
2822 set_gdbarch_pseudo_register_read_value (gdbarch,
2823 amd64_pseudo_register_read_value);
2824 set_gdbarch_pseudo_register_write (gdbarch,
2825 amd64_pseudo_register_write);
2827 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
2829 /* AMD64 has an FPU and 16 SSE registers. */
2830 tdep->st0_regnum = AMD64_ST0_REGNUM;
2831 tdep->num_xmm_regs = 16;
2833 /* This is what all the fuss is about. */
2834 set_gdbarch_long_bit (gdbarch, 64);
2835 set_gdbarch_long_long_bit (gdbarch, 64);
2836 set_gdbarch_ptr_bit (gdbarch, 64);
2838 /* In contrast to the i386, on AMD64 a `long double' actually takes
2839 up 128 bits, even though it's still based on the i387 extended
2840 floating-point format which has only 80 significant bits. */
2841 set_gdbarch_long_double_bit (gdbarch, 128);
2843 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
2845 /* Register numbers of various important registers. */
2846 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
2847 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
2848 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
2849 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
2851 /* The "default" register numbering scheme for AMD64 is referred to
2852 as the "DWARF Register Number Mapping" in the System V psABI.
2853 The preferred debugging format for all known AMD64 targets is
2854 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2855 DWARF-1), but we provide the same mapping just in case. This
2856 mapping is also used for stabs, which GCC does support. */
2857 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2858 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2860 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2861 be in use on any of the supported AMD64 targets. */
2863 /* Call dummy code. */
2864 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
2865 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
2866 set_gdbarch_frame_red_zone_size (gdbarch, 128);
2867 tdep->call_dummy_num_integer_regs =
2868 ARRAY_SIZE (amd64_dummy_call_integer_regs);
2869 tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs;
2870 tdep->classify = amd64_classify;
2872 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
2873 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
2874 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
2876 set_gdbarch_return_value (gdbarch, amd64_return_value);
2878 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
2880 tdep->record_regmap = amd64_record_regmap;
2882 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
2884 /* Hook the function epilogue frame unwinder. This unwinder is
2885 appended to the list first, so that it supercedes the other
2886 unwinders in function epilogues. */
2887 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
2889 /* Hook the prologue-based frame unwinders. */
2890 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
2891 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
2892 frame_base_set_default (gdbarch, &amd64_frame_base);
2894 /* If we have a register mapping, enable the generic core file support. */
2895 if (tdep->gregset_reg_offset)
2896 set_gdbarch_regset_from_core_section (gdbarch,
2897 amd64_regset_from_core_section);
2899 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
2901 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
2903 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
2905 /* SystemTap variables and functions. */
2906 set_gdbarch_stap_integer_prefix (gdbarch, "$");
2907 set_gdbarch_stap_register_prefix (gdbarch, "%");
2908 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
2909 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
2910 set_gdbarch_stap_is_single_operand (gdbarch,
2911 i386_stap_is_single_operand);
2912 set_gdbarch_stap_parse_special_token (gdbarch,
2913 i386_stap_parse_special_token);
2917 static struct type *
2918 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2920 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2922 switch (regnum - tdep->eax_regnum)
2924 case AMD64_RBP_REGNUM: /* %ebp */
2925 case AMD64_RSP_REGNUM: /* %esp */
2926 return builtin_type (gdbarch)->builtin_data_ptr;
2927 case AMD64_RIP_REGNUM: /* %eip */
2928 return builtin_type (gdbarch)->builtin_func_ptr;
2931 return i386_pseudo_register_type (gdbarch, regnum);
2935 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2937 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2938 const struct target_desc *tdesc = info.target_desc;
2940 amd64_init_abi (info, gdbarch);
2942 if (! tdesc_has_registers (tdesc))
2944 tdep->tdesc = tdesc;
2946 tdep->sp_regnum_from_eax = AMD64_RSP_REGNUM;
2947 tdep->pc_regnum_from_eax = AMD64_RIP_REGNUM;
2949 tdep->num_dword_regs = 17;
2950 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
2952 set_gdbarch_long_bit (gdbarch, 32);
2953 set_gdbarch_ptr_bit (gdbarch, 32);
2956 /* Provide a prototype to silence -Wmissing-prototypes. */
2957 void _initialize_amd64_tdep (void);
2960 _initialize_amd64_tdep (void)
2962 initialize_tdesc_amd64 ();
2963 initialize_tdesc_amd64_avx ();
2964 initialize_tdesc_x32 ();
2965 initialize_tdesc_x32_avx ();
2969 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2970 sense that the instruction pointer and data pointer are simply
2971 64-bit offsets into the code segment and the data segment instead
2972 of a selector offset pair. The functions below store the upper 32
2973 bits of these pointers (instead of just the 16-bits of the segment
2976 /* Fill register REGNUM in REGCACHE with the appropriate
2977 floating-point or SSE register value from *FXSAVE. If REGNUM is
2978 -1, do this for all registers. This function masks off any of the
2979 reserved bits in *FXSAVE. */
2982 amd64_supply_fxsave (struct regcache *regcache, int regnum,
2985 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2986 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2988 i387_supply_fxsave (regcache, regnum, fxsave);
2991 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
2993 const gdb_byte *regs = fxsave;
2995 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
2996 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
2997 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
2998 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3002 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3005 amd64_supply_xsave (struct regcache *regcache, int regnum,
3008 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3009 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3011 i387_supply_xsave (regcache, regnum, xsave);
3014 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3016 const gdb_byte *regs = xsave;
3018 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3019 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3021 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3022 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3027 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3028 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3029 all registers. This function doesn't touch any of the reserved
3033 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3036 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3037 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3038 gdb_byte *regs = fxsave;
3040 i387_collect_fxsave (regcache, regnum, fxsave);
3042 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3044 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3045 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3046 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3047 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3051 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3054 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3055 void *xsave, int gcore)
3057 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3058 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3059 gdb_byte *regs = xsave;
3061 i387_collect_xsave (regcache, regnum, xsave, gcore);
3063 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3065 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3066 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3068 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3069 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),