1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1993-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "frame-unwind.h"
23 #include "frame-base.h"
24 #include "dwarf2-frame.h"
35 #include "reggroups.h"
36 #include "arch-utils.h"
40 #include "trad-frame.h"
44 #include "alpha-tdep.h"
47 /* Instruction decoding. The notations for registers, immediates and
48 opcodes are the same as the one used in Compaq's Alpha architecture
51 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
53 /* Memory instruction format */
54 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
55 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
56 #define MEM_DISP(insn) \
57 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
59 static const int lda_opcode = 0x08;
60 static const int stq_opcode = 0x2d;
62 /* Branch instruction format */
63 #define BR_RA(insn) MEM_RA(insn)
65 static const int br_opcode = 0x30;
66 static const int bne_opcode = 0x3d;
68 /* Operate instruction format */
69 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
70 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
71 #define OPR_RA(insn) MEM_RA(insn)
72 #define OPR_RC(insn) ((insn & 0x1f))
73 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
75 static const int subq_opcode = 0x10;
76 static const int subq_function = 0x29;
79 /* Return the name of the REGNO register.
81 An empty name corresponds to a register number that used to
82 be used for a virtual register. That virtual register has
83 been removed, but the index is still reserved to maintain
84 compatibility with existing remote alpha targets. */
87 alpha_register_name (struct gdbarch *gdbarch, int regno)
89 static const char * const register_names[] =
91 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
92 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
93 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
94 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
95 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
96 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
97 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
98 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
104 if (regno >= ARRAY_SIZE(register_names))
106 return register_names[regno];
110 alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
112 return (strlen (alpha_register_name (gdbarch, regno)) == 0);
116 alpha_cannot_store_register (struct gdbarch *gdbarch, int regno)
118 return (regno == ALPHA_ZERO_REGNUM
119 || strlen (alpha_register_name (gdbarch, regno)) == 0);
123 alpha_register_type (struct gdbarch *gdbarch, int regno)
125 if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM)
126 return builtin_type (gdbarch)->builtin_data_ptr;
127 if (regno == ALPHA_PC_REGNUM)
128 return builtin_type (gdbarch)->builtin_func_ptr;
130 /* Don't need to worry about little vs big endian until
131 some jerk tries to port to alpha-unicosmk. */
132 if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31)
133 return builtin_type (gdbarch)->builtin_double;
135 return builtin_type (gdbarch)->builtin_int64;
138 /* Is REGNUM a member of REGGROUP? */
141 alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
142 struct reggroup *group)
144 /* Filter out any registers eliminated, but whose regnum is
145 reserved for backward compatibility, e.g. the vfp. */
146 if (gdbarch_register_name (gdbarch, regnum) == NULL
147 || *gdbarch_register_name (gdbarch, regnum) == '\0')
150 if (group == all_reggroup)
153 /* Zero should not be saved or restored. Technically it is a general
154 register (just as $f31 would be a float if we represented it), but
155 there's no point displaying it during "info regs", so leave it out
156 of all groups except for "all". */
157 if (regnum == ALPHA_ZERO_REGNUM)
160 /* All other registers are saved and restored. */
161 if (group == save_reggroup || group == restore_reggroup)
164 /* All other groups are non-overlapping. */
166 /* Since this is really a PALcode memory slot... */
167 if (regnum == ALPHA_UNIQUE_REGNUM)
168 return group == system_reggroup;
170 /* Force the FPCR to be considered part of the floating point state. */
171 if (regnum == ALPHA_FPCR_REGNUM)
172 return group == float_reggroup;
174 if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31)
175 return group == float_reggroup;
177 return group == general_reggroup;
180 /* The following represents exactly the conversion performed by
181 the LDS instruction. This applies to both single-precision
182 floating point and 32-bit integers. */
185 alpha_lds (struct gdbarch *gdbarch, void *out, const void *in)
187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
189 = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order);
190 ULONGEST frac = (mem >> 0) & 0x7fffff;
191 ULONGEST sign = (mem >> 31) & 1;
192 ULONGEST exp_msb = (mem >> 30) & 1;
193 ULONGEST exp_low = (mem >> 23) & 0x7f;
196 exp = (exp_msb << 10) | exp_low;
208 reg = (sign << 63) | (exp << 52) | (frac << 29);
209 store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg);
212 /* Similarly, this represents exactly the conversion performed by
213 the STS instruction. */
216 alpha_sts (struct gdbarch *gdbarch, void *out, const void *in)
218 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
221 reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order);
222 mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff);
223 store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem);
226 /* The alpha needs a conversion between register and memory format if the
227 register is a floating point register and memory format is float, as the
228 register format must be double or memory format is an integer with 4
229 bytes, as the representation of integers in floating point
230 registers is different. */
233 alpha_convert_register_p (struct gdbarch *gdbarch, int regno,
236 return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31
237 && TYPE_LENGTH (type) == 4);
241 alpha_register_to_value (struct frame_info *frame, int regnum,
242 struct type *valtype, gdb_byte *out,
243 int *optimizedp, int *unavailablep)
245 struct gdbarch *gdbarch = get_frame_arch (frame);
246 struct value *value = get_frame_register_value (frame, regnum);
248 gdb_assert (value != NULL);
249 *optimizedp = value_optimized_out (value);
250 *unavailablep = !value_entirely_available (value);
252 if (*optimizedp || *unavailablep)
254 release_value (value);
259 /* Convert to VALTYPE. */
261 gdb_assert (TYPE_LENGTH (valtype) == 4);
262 alpha_sts (gdbarch, out, value_contents_all (value));
264 release_value (value);
270 alpha_value_to_register (struct frame_info *frame, int regnum,
271 struct type *valtype, const gdb_byte *in)
273 gdb_byte out[ALPHA_REGISTER_SIZE];
275 gdb_assert (TYPE_LENGTH (valtype) == 4);
276 gdb_assert (register_size (get_frame_arch (frame), regnum)
277 <= ALPHA_REGISTER_SIZE);
278 alpha_lds (get_frame_arch (frame), out, in);
280 put_frame_register (frame, regnum, out);
284 /* The alpha passes the first six arguments in the registers, the rest on
285 the stack. The register arguments are stored in ARG_REG_BUFFER, and
286 then moved into the register file; this simplifies the passing of a
287 large struct which extends from the registers to the stack, plus avoids
288 three ptrace invocations per word.
290 We don't bother tracking which register values should go in integer
291 regs or fp regs; we load the same values into both.
293 If the called function is returning a structure, the address of the
294 structure to be returned is passed as a hidden first argument. */
297 alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
298 struct regcache *regcache, CORE_ADDR bp_addr,
299 int nargs, struct value **args, CORE_ADDR sp,
300 int struct_return, CORE_ADDR struct_addr)
302 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
304 int accumulate_size = struct_return ? 8 : 0;
307 const gdb_byte *contents;
311 struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs);
312 struct alpha_arg *m_arg;
313 gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS];
314 int required_arg_regs;
315 CORE_ADDR func_addr = find_function_addr (function, NULL);
317 /* The ABI places the address of the called function in T12. */
318 regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr);
320 /* Set the return address register to point to the entry point
321 of the program, where a breakpoint lies in wait. */
322 regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr);
324 /* Lay out the arguments in memory. */
325 for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++)
327 struct value *arg = args[i];
328 struct type *arg_type = check_typedef (value_type (arg));
330 /* Cast argument to long if necessary as the compiler does it too. */
331 switch (TYPE_CODE (arg_type))
336 case TYPE_CODE_RANGE:
338 if (TYPE_LENGTH (arg_type) == 4)
340 /* 32-bit values must be sign-extended to 64 bits
341 even if the base data type is unsigned. */
342 arg_type = builtin_type (gdbarch)->builtin_int32;
343 arg = value_cast (arg_type, arg);
345 if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE)
347 arg_type = builtin_type (gdbarch)->builtin_int64;
348 arg = value_cast (arg_type, arg);
353 /* "float" arguments loaded in registers must be passed in
354 register format, aka "double". */
355 if (accumulate_size < sizeof (arg_reg_buffer)
356 && TYPE_LENGTH (arg_type) == 4)
358 arg_type = builtin_type (gdbarch)->builtin_double;
359 arg = value_cast (arg_type, arg);
361 /* Tru64 5.1 has a 128-bit long double, and passes this by
362 invisible reference. No one else uses this data type. */
363 else if (TYPE_LENGTH (arg_type) == 16)
365 /* Allocate aligned storage. */
366 sp = (sp & -16) - 16;
368 /* Write the real data into the stack. */
369 write_memory (sp, value_contents (arg), 16);
371 /* Construct the indirection. */
372 arg_type = lookup_pointer_type (arg_type);
373 arg = value_from_pointer (arg_type, sp);
377 case TYPE_CODE_COMPLEX:
378 /* ??? The ABI says that complex values are passed as two
379 separate scalar values. This distinction only matters
380 for complex float. However, GCC does not implement this. */
382 /* Tru64 5.1 has a 128-bit long double, and passes this by
383 invisible reference. */
384 if (TYPE_LENGTH (arg_type) == 32)
386 /* Allocate aligned storage. */
387 sp = (sp & -16) - 16;
389 /* Write the real data into the stack. */
390 write_memory (sp, value_contents (arg), 32);
392 /* Construct the indirection. */
393 arg_type = lookup_pointer_type (arg_type);
394 arg = value_from_pointer (arg_type, sp);
401 m_arg->len = TYPE_LENGTH (arg_type);
402 m_arg->offset = accumulate_size;
403 accumulate_size = (accumulate_size + m_arg->len + 7) & ~7;
404 m_arg->contents = value_contents (arg);
407 /* Determine required argument register loads, loading an argument register
408 is expensive as it uses three ptrace calls. */
409 required_arg_regs = accumulate_size / 8;
410 if (required_arg_regs > ALPHA_NUM_ARG_REGS)
411 required_arg_regs = ALPHA_NUM_ARG_REGS;
413 /* Make room for the arguments on the stack. */
414 if (accumulate_size < sizeof(arg_reg_buffer))
417 accumulate_size -= sizeof(arg_reg_buffer);
418 sp -= accumulate_size;
420 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
423 /* `Push' arguments on the stack. */
424 for (i = nargs; m_arg--, --i >= 0;)
426 const gdb_byte *contents = m_arg->contents;
427 int offset = m_arg->offset;
428 int len = m_arg->len;
430 /* Copy the bytes destined for registers into arg_reg_buffer. */
431 if (offset < sizeof(arg_reg_buffer))
433 if (offset + len <= sizeof(arg_reg_buffer))
435 memcpy (arg_reg_buffer + offset, contents, len);
440 int tlen = sizeof(arg_reg_buffer) - offset;
441 memcpy (arg_reg_buffer + offset, contents, tlen);
448 /* Everything else goes to the stack. */
449 write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len);
452 store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE,
453 byte_order, struct_addr);
455 /* Load the argument registers. */
456 for (i = 0; i < required_arg_regs; i++)
458 regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i,
459 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
460 regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i,
461 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
464 /* Finally, update the stack pointer. */
465 regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp);
470 /* Extract from REGCACHE the value about to be returned from a function
471 and copy it into VALBUF. */
474 alpha_extract_return_value (struct type *valtype, struct regcache *regcache,
477 struct gdbarch *gdbarch = regcache->arch ();
478 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
479 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
482 switch (TYPE_CODE (valtype))
485 switch (TYPE_LENGTH (valtype))
488 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer);
489 alpha_sts (gdbarch, valbuf, raw_buffer);
493 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
497 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
498 read_memory (l, valbuf, 16);
502 internal_error (__FILE__, __LINE__,
503 _("unknown floating point width"));
507 case TYPE_CODE_COMPLEX:
508 switch (TYPE_LENGTH (valtype))
511 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
512 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
516 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
517 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
521 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
522 read_memory (l, valbuf, 32);
526 internal_error (__FILE__, __LINE__,
527 _("unknown floating point width"));
532 /* Assume everything else degenerates to an integer. */
533 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
534 store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l);
539 /* Insert the given value into REGCACHE as if it was being
540 returned by a function. */
543 alpha_store_return_value (struct type *valtype, struct regcache *regcache,
544 const gdb_byte *valbuf)
546 struct gdbarch *gdbarch = regcache->arch ();
547 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
550 switch (TYPE_CODE (valtype))
553 switch (TYPE_LENGTH (valtype))
556 alpha_lds (gdbarch, raw_buffer, valbuf);
557 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer);
561 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
565 /* FIXME: 128-bit long doubles are returned like structures:
566 by writing into indirect storage provided by the caller
567 as the first argument. */
568 error (_("Cannot set a 128-bit long double return value."));
571 internal_error (__FILE__, __LINE__,
572 _("unknown floating point width"));
576 case TYPE_CODE_COMPLEX:
577 switch (TYPE_LENGTH (valtype))
580 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
581 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
585 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
586 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
590 /* FIXME: 128-bit long doubles are returned like structures:
591 by writing into indirect storage provided by the caller
592 as the first argument. */
593 error (_("Cannot set a 128-bit long double return value."));
596 internal_error (__FILE__, __LINE__,
597 _("unknown floating point width"));
602 /* Assume everything else degenerates to an integer. */
603 /* 32-bit values must be sign-extended to 64 bits
604 even if the base data type is unsigned. */
605 if (TYPE_LENGTH (valtype) == 4)
606 valtype = builtin_type (gdbarch)->builtin_int32;
607 l = unpack_long (valtype, valbuf);
608 regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l);
613 static enum return_value_convention
614 alpha_return_value (struct gdbarch *gdbarch, struct value *function,
615 struct type *type, struct regcache *regcache,
616 gdb_byte *readbuf, const gdb_byte *writebuf)
618 enum type_code code = TYPE_CODE (type);
620 if ((code == TYPE_CODE_STRUCT
621 || code == TYPE_CODE_UNION
622 || code == TYPE_CODE_ARRAY)
623 && gdbarch_tdep (gdbarch)->return_in_memory (type))
628 regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr);
629 read_memory (addr, readbuf, TYPE_LENGTH (type));
632 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
636 alpha_extract_return_value (type, regcache, readbuf);
638 alpha_store_return_value (type, regcache, writebuf);
640 return RETURN_VALUE_REGISTER_CONVENTION;
644 alpha_return_in_memory_always (struct type *type)
650 constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
652 typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint;
655 /* This returns the PC of the first insn after the prologue.
656 If we can't find the prologue, then return 0. */
659 alpha_after_prologue (CORE_ADDR pc)
661 struct symtab_and_line sal;
662 CORE_ADDR func_addr, func_end;
664 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
667 sal = find_pc_line (func_addr, 0);
668 if (sal.end < func_end)
671 /* The line after the prologue is after the end of the function. In this
672 case, tell the caller to find the prologue the hard way. */
676 /* Read an instruction from memory at PC, looking through breakpoints. */
679 alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
681 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
682 gdb_byte buf[ALPHA_INSN_SIZE];
685 res = target_read_memory (pc, buf, sizeof (buf));
687 memory_error (TARGET_XFER_E_IO, pc);
688 return extract_unsigned_integer (buf, sizeof (buf), byte_order);
691 /* To skip prologues, I use this predicate. Returns either PC itself
692 if the code at PC does not look like a function prologue; otherwise
693 returns an address that (if we're lucky) follows the prologue. If
694 LENIENT, then we must skip everything which is involved in setting
695 up the frame (it's OK to skip more, just so long as we don't skip
696 anything which might clobber the registers which are being saved. */
699 alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
703 CORE_ADDR post_prologue_pc;
704 gdb_byte buf[ALPHA_INSN_SIZE];
706 /* Silently return the unaltered pc upon memory errors.
707 This could happen on OSF/1 if decode_line_1 tries to skip the
708 prologue for quickstarted shared library functions when the
709 shared library is not yet mapped in.
710 Reading target memory is slow over serial lines, so we perform
711 this check only if the target has shared libraries (which all
712 Alpha targets do). */
713 if (target_read_memory (pc, buf, sizeof (buf)))
716 /* See if we can determine the end of the prologue via the symbol table.
717 If so, then return either PC, or the PC after the prologue, whichever
720 post_prologue_pc = alpha_after_prologue (pc);
721 if (post_prologue_pc != 0)
722 return std::max (pc, post_prologue_pc);
724 /* Can't determine prologue from the symbol table, need to examine
727 /* Skip the typical prologue instructions. These are the stack adjustment
728 instruction and the instructions that save registers on the stack
729 or in the gcc frame. */
730 for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE)
732 inst = alpha_read_insn (gdbarch, pc + offset);
734 if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
736 if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
738 if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
740 if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
743 if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
744 || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
745 && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */
748 if (inst == 0x47de040f) /* bis sp,sp,fp */
750 if (inst == 0x47fe040f) /* bis zero,sp,fp */
759 static const int ldl_l_opcode = 0x2a;
760 static const int ldq_l_opcode = 0x2b;
761 static const int stl_c_opcode = 0x2e;
762 static const int stq_c_opcode = 0x2f;
764 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L
765 instruction and ending with a STL_C/STQ_C instruction. If such a sequence
766 is found, attempt to step through it. A breakpoint is placed at the end of
769 static std::vector<CORE_ADDR>
770 alpha_deal_with_atomic_sequence (struct regcache *regcache)
772 struct gdbarch *gdbarch = regcache->arch ();
773 CORE_ADDR pc = regcache_read_pc (regcache);
774 CORE_ADDR breaks[2] = {-1, -1};
776 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
777 unsigned int insn = alpha_read_insn (gdbarch, loc);
780 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
781 const int atomic_sequence_length = 16; /* Instruction sequence length. */
782 int bc_insn_count = 0; /* Conditional branch instruction count. */
784 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
785 if (INSN_OPCODE (insn) != ldl_l_opcode
786 && INSN_OPCODE (insn) != ldq_l_opcode)
789 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
791 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
793 loc += ALPHA_INSN_SIZE;
794 insn = alpha_read_insn (gdbarch, loc);
796 /* Assume that there is at most one branch in the atomic
797 sequence. If a branch is found, put a breakpoint in
798 its destination address. */
799 if (INSN_OPCODE (insn) >= br_opcode)
801 int immediate = (insn & 0x001fffff) << 2;
803 immediate = (immediate ^ 0x400000) - 0x400000;
805 if (bc_insn_count >= 1)
806 return {}; /* More than one branch found, fallback
807 to the standard single-step code. */
809 breaks[1] = loc + ALPHA_INSN_SIZE + immediate;
815 if (INSN_OPCODE (insn) == stl_c_opcode
816 || INSN_OPCODE (insn) == stq_c_opcode)
820 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
821 if (INSN_OPCODE (insn) != stl_c_opcode
822 && INSN_OPCODE (insn) != stq_c_opcode)
826 loc += ALPHA_INSN_SIZE;
828 /* Insert a breakpoint right after the end of the atomic sequence. */
831 /* Check for duplicated breakpoints. Check also for a breakpoint
832 placed (branch instruction's destination) anywhere in sequence. */
834 && (breaks[1] == breaks[0]
835 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
838 std::vector<CORE_ADDR> next_pcs;
840 for (index = 0; index <= last_breakpoint; index++)
841 next_pcs.push_back (breaks[index]);
847 /* Figure out where the longjmp will land.
848 We expect the first arg to be a pointer to the jmp_buf structure from
849 which we extract the PC (JB_PC) that we will land at. The PC is copied
850 into the "pc". This routine returns true on success. */
853 alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
855 struct gdbarch *gdbarch = get_frame_arch (frame);
856 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
857 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
859 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
861 jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM);
863 if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size),
864 raw_buffer, tdep->jb_elt_size))
867 *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order);
872 /* Frame unwinder for signal trampolines. We use alpha tdep bits that
873 describe the location and shape of the sigcontext structure. After
874 that, all registers are in memory, so it's easy. */
875 /* ??? Shouldn't we be able to do this generically, rather than with
876 OSABI data specific to Alpha? */
878 struct alpha_sigtramp_unwind_cache
880 CORE_ADDR sigcontext_addr;
883 static struct alpha_sigtramp_unwind_cache *
884 alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
885 void **this_prologue_cache)
887 struct alpha_sigtramp_unwind_cache *info;
888 struct gdbarch_tdep *tdep;
890 if (*this_prologue_cache)
891 return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache;
893 info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache);
894 *this_prologue_cache = info;
896 tdep = gdbarch_tdep (get_frame_arch (this_frame));
897 info->sigcontext_addr = tdep->sigcontext_addr (this_frame);
902 /* Return the address of REGNUM in a sigtramp frame. Since this is
903 all arithmetic, it doesn't seem worthwhile to cache it. */
906 alpha_sigtramp_register_address (struct gdbarch *gdbarch,
907 CORE_ADDR sigcontext_addr, int regnum)
909 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
911 if (regnum >= 0 && regnum < 32)
912 return sigcontext_addr + tdep->sc_regs_offset + regnum * 8;
913 else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32)
914 return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8;
915 else if (regnum == ALPHA_PC_REGNUM)
916 return sigcontext_addr + tdep->sc_pc_offset;
921 /* Given a GDB frame, determine the address of the calling function's
922 frame. This will be used to create a new GDB frame struct. */
925 alpha_sigtramp_frame_this_id (struct frame_info *this_frame,
926 void **this_prologue_cache,
927 struct frame_id *this_id)
929 struct gdbarch *gdbarch = get_frame_arch (this_frame);
930 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
931 struct alpha_sigtramp_unwind_cache *info
932 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
933 CORE_ADDR stack_addr, code_addr;
935 /* If the OSABI couldn't locate the sigcontext, give up. */
936 if (info->sigcontext_addr == 0)
939 /* If we have dynamic signal trampolines, find their start.
940 If we do not, then we must assume there is a symbol record
941 that can provide the start address. */
942 if (tdep->dynamic_sigtramp_offset)
945 code_addr = get_frame_pc (this_frame);
946 offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr);
953 code_addr = get_frame_func (this_frame);
955 /* The stack address is trivially read from the sigcontext. */
956 stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr,
958 stack_addr = get_frame_memory_unsigned (this_frame, stack_addr,
959 ALPHA_REGISTER_SIZE);
961 *this_id = frame_id_build (stack_addr, code_addr);
964 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
966 static struct value *
967 alpha_sigtramp_frame_prev_register (struct frame_info *this_frame,
968 void **this_prologue_cache, int regnum)
970 struct alpha_sigtramp_unwind_cache *info
971 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
974 if (info->sigcontext_addr != 0)
976 /* All integer and fp registers are stored in memory. */
977 addr = alpha_sigtramp_register_address (get_frame_arch (this_frame),
978 info->sigcontext_addr, regnum);
980 return frame_unwind_got_memory (this_frame, regnum, addr);
983 /* This extra register may actually be in the sigcontext, but our
984 current description of it in alpha_sigtramp_frame_unwind_cache
985 doesn't include it. Too bad. Fall back on whatever's in the
987 return frame_unwind_got_register (this_frame, regnum, regnum);
991 alpha_sigtramp_frame_sniffer (const struct frame_unwind *self,
992 struct frame_info *this_frame,
993 void **this_prologue_cache)
995 struct gdbarch *gdbarch = get_frame_arch (this_frame);
996 CORE_ADDR pc = get_frame_pc (this_frame);
999 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
1000 look at tramp-frame.h and other simplier per-architecture
1001 sigtramp unwinders. */
1003 /* We shouldn't even bother to try if the OSABI didn't register a
1004 sigcontext_addr handler or pc_in_sigtramp hander. */
1005 if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL)
1007 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL)
1010 /* Otherwise we should be in a signal frame. */
1011 find_pc_partial_function (pc, &name, NULL, NULL);
1012 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name))
1018 static const struct frame_unwind alpha_sigtramp_frame_unwind = {
1020 default_frame_unwind_stop_reason,
1021 alpha_sigtramp_frame_this_id,
1022 alpha_sigtramp_frame_prev_register,
1024 alpha_sigtramp_frame_sniffer
1029 /* Heuristic_proc_start may hunt through the text section for a long
1030 time across a 2400 baud serial line. Allows the user to limit this
1032 static int heuristic_fence_post = 0;
1034 /* Attempt to locate the start of the function containing PC. We assume that
1035 the previous function ends with an about_to_return insn. Not foolproof by
1036 any means, since gcc is happy to put the epilogue in the middle of a
1037 function. But we're guessing anyway... */
1040 alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
1042 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1043 CORE_ADDR last_non_nop = pc;
1044 CORE_ADDR fence = pc - heuristic_fence_post;
1045 CORE_ADDR orig_pc = pc;
1047 struct inferior *inf;
1052 /* First see if we can find the start of the function from minimal
1053 symbol information. This can succeed with a binary that doesn't
1054 have debug info, but hasn't been stripped. */
1055 func = get_pc_function_start (pc);
1059 if (heuristic_fence_post == -1
1060 || fence < tdep->vm_min_address)
1061 fence = tdep->vm_min_address;
1063 /* Search back for previous return; also stop at a 0, which might be
1064 seen for instance before the start of a code section. Don't include
1065 nops, since this usually indicates padding between functions. */
1066 for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE)
1068 unsigned int insn = alpha_read_insn (gdbarch, pc);
1071 case 0: /* invalid insn */
1072 case 0x6bfa8001: /* ret $31,($26),1 */
1073 return last_non_nop;
1075 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
1076 case 0x47ff041f: /* nop: bis $31,$31,$31 */
1085 inf = current_inferior ();
1087 /* It's not clear to me why we reach this point when stopping quietly,
1088 but with this test, at least we don't print out warnings for every
1089 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
1090 if (inf->control.stop_soon == NO_STOP_QUIETLY)
1092 static int blurb_printed = 0;
1094 if (fence == tdep->vm_min_address)
1095 warning (_("Hit beginning of text section without finding \
1096 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1098 warning (_("Hit heuristic-fence-post without finding \
1099 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1103 printf_filtered (_("\
1104 This warning occurs if you are debugging a function without any symbols\n\
1105 (for example, in a stripped executable). In that case, you may wish to\n\
1106 increase the size of the search with the `set heuristic-fence-post' command.\n\
1108 Otherwise, you told GDB there was a function where there isn't one, or\n\
1109 (more likely) you have encountered a bug in GDB.\n"));
1117 /* Fallback alpha frame unwinder. Uses instruction scanning and knows
1118 something about the traditional layout of alpha stack frames. */
1120 struct alpha_heuristic_unwind_cache
1124 struct trad_frame_saved_reg *saved_regs;
1128 /* If a probing loop sequence starts at PC, simulate it and compute
1129 FRAME_SIZE and PC after its execution. Otherwise, return with PC and
1130 FRAME_SIZE unchanged. */
1133 alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc,
1136 CORE_ADDR cur_pc = *pc;
1137 int cur_frame_size = *frame_size;
1138 int nb_of_iterations, reg_index, reg_probe;
1141 /* The following pattern is recognized as a probing loop:
1143 lda REG_INDEX,NB_OF_ITERATIONS
1144 lda REG_PROBE,<immediate>(sp)
1147 stq zero,<immediate>(REG_PROBE)
1148 subq REG_INDEX,0x1,REG_INDEX
1149 lda REG_PROBE,<immediate>(REG_PROBE)
1150 bne REG_INDEX, LOOP_START
1152 lda sp,<immediate>(REG_PROBE)
1154 If anything different is found, the function returns without
1155 changing PC and FRAME_SIZE. Otherwise, PC will point immediately
1156 after this sequence, and FRAME_SIZE will be updated. */
1158 /* lda REG_INDEX,NB_OF_ITERATIONS */
1160 insn = alpha_read_insn (gdbarch, cur_pc);
1161 if (INSN_OPCODE (insn) != lda_opcode)
1163 reg_index = MEM_RA (insn);
1164 nb_of_iterations = MEM_DISP (insn);
1166 /* lda REG_PROBE,<immediate>(sp) */
1168 cur_pc += ALPHA_INSN_SIZE;
1169 insn = alpha_read_insn (gdbarch, cur_pc);
1170 if (INSN_OPCODE (insn) != lda_opcode
1171 || MEM_RB (insn) != ALPHA_SP_REGNUM)
1173 reg_probe = MEM_RA (insn);
1174 cur_frame_size -= MEM_DISP (insn);
1176 /* stq zero,<immediate>(REG_PROBE) */
1178 cur_pc += ALPHA_INSN_SIZE;
1179 insn = alpha_read_insn (gdbarch, cur_pc);
1180 if (INSN_OPCODE (insn) != stq_opcode
1181 || MEM_RA (insn) != 0x1f
1182 || MEM_RB (insn) != reg_probe)
1185 /* subq REG_INDEX,0x1,REG_INDEX */
1187 cur_pc += ALPHA_INSN_SIZE;
1188 insn = alpha_read_insn (gdbarch, cur_pc);
1189 if (INSN_OPCODE (insn) != subq_opcode
1190 || !OPR_HAS_IMMEDIATE (insn)
1191 || OPR_FUNCTION (insn) != subq_function
1192 || OPR_LIT(insn) != 1
1193 || OPR_RA (insn) != reg_index
1194 || OPR_RC (insn) != reg_index)
1197 /* lda REG_PROBE,<immediate>(REG_PROBE) */
1199 cur_pc += ALPHA_INSN_SIZE;
1200 insn = alpha_read_insn (gdbarch, cur_pc);
1201 if (INSN_OPCODE (insn) != lda_opcode
1202 || MEM_RA (insn) != reg_probe
1203 || MEM_RB (insn) != reg_probe)
1205 cur_frame_size -= MEM_DISP (insn) * nb_of_iterations;
1207 /* bne REG_INDEX, LOOP_START */
1209 cur_pc += ALPHA_INSN_SIZE;
1210 insn = alpha_read_insn (gdbarch, cur_pc);
1211 if (INSN_OPCODE (insn) != bne_opcode
1212 || MEM_RA (insn) != reg_index)
1215 /* lda sp,<immediate>(REG_PROBE) */
1217 cur_pc += ALPHA_INSN_SIZE;
1218 insn = alpha_read_insn (gdbarch, cur_pc);
1219 if (INSN_OPCODE (insn) != lda_opcode
1220 || MEM_RA (insn) != ALPHA_SP_REGNUM
1221 || MEM_RB (insn) != reg_probe)
1223 cur_frame_size -= MEM_DISP (insn);
1226 *frame_size = cur_frame_size;
1229 static struct alpha_heuristic_unwind_cache *
1230 alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame,
1231 void **this_prologue_cache,
1234 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1235 struct alpha_heuristic_unwind_cache *info;
1237 CORE_ADDR limit_pc, cur_pc;
1238 int frame_reg, frame_size, return_reg, reg;
1240 if (*this_prologue_cache)
1241 return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache;
1243 info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache);
1244 *this_prologue_cache = info;
1245 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1247 limit_pc = get_frame_pc (this_frame);
1249 start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc);
1250 info->start_pc = start_pc;
1252 frame_reg = ALPHA_SP_REGNUM;
1256 /* If we've identified a likely place to start, do code scanning. */
1259 /* Limit the forward search to 50 instructions. */
1260 if (start_pc + 200 < limit_pc)
1261 limit_pc = start_pc + 200;
1263 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE)
1265 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1267 if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1271 /* Consider only the first stack allocation instruction
1272 to contain the static size of the frame. */
1273 if (frame_size == 0)
1274 frame_size = (-word) & 0xffff;
1278 /* Exit loop if a positive stack adjustment is found, which
1279 usually means that the stack cleanup code in the function
1280 epilogue is reached. */
1284 else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1286 reg = (word & 0x03e00000) >> 21;
1288 /* Ignore this instruction if we have already encountered
1289 an instruction saving the same register earlier in the
1290 function code. The current instruction does not tell
1291 us where the original value upon function entry is saved.
1292 All it says is that the function we are scanning reused
1293 that register for some computation of its own, and is now
1294 saving its result. */
1295 if (trad_frame_addr_p(info->saved_regs, reg))
1301 /* Do not compute the address where the register was saved yet,
1302 because we don't know yet if the offset will need to be
1303 relative to $sp or $fp (we can not compute the address
1304 relative to $sp if $sp is updated during the execution of
1305 the current subroutine, for instance when doing some alloca).
1306 So just store the offset for the moment, and compute the
1307 address later when we know whether this frame has a frame
1309 /* Hack: temporarily add one, so that the offset is non-zero
1310 and we can tell which registers have save offsets below. */
1311 info->saved_regs[reg].addr = (word & 0xffff) + 1;
1313 /* Starting with OSF/1-3.2C, the system libraries are shipped
1314 without local symbols, but they still contain procedure
1315 descriptors without a symbol reference. GDB is currently
1316 unable to find these procedure descriptors and uses
1317 heuristic_proc_desc instead.
1318 As some low level compiler support routines (__div*, __add*)
1319 use a non-standard return address register, we have to
1320 add some heuristics to determine the return address register,
1321 or stepping over these routines will fail.
1322 Usually the return address register is the first register
1323 saved on the stack, but assembler optimization might
1324 rearrange the register saves.
1325 So we recognize only a few registers (t7, t9, ra) within
1326 the procedure prologue as valid return address registers.
1327 If we encounter a return instruction, we extract the
1328 return address register from it.
1330 FIXME: Rewriting GDB to access the procedure descriptors,
1331 e.g. via the minimal symbol table, might obviate this
1333 if (return_reg == -1
1334 && cur_pc < (start_pc + 80)
1335 && (reg == ALPHA_T7_REGNUM
1336 || reg == ALPHA_T9_REGNUM
1337 || reg == ALPHA_RA_REGNUM))
1340 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1341 return_reg = (word >> 16) & 0x1f;
1342 else if (word == 0x47de040f) /* bis sp,sp,fp */
1343 frame_reg = ALPHA_GCC_FP_REGNUM;
1344 else if (word == 0x47fe040f) /* bis zero,sp,fp */
1345 frame_reg = ALPHA_GCC_FP_REGNUM;
1347 alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size);
1350 /* If we haven't found a valid return address register yet, keep
1351 searching in the procedure prologue. */
1352 if (return_reg == -1)
1354 while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80))
1356 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1358 if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1360 reg = (word & 0x03e00000) >> 21;
1361 if (reg == ALPHA_T7_REGNUM
1362 || reg == ALPHA_T9_REGNUM
1363 || reg == ALPHA_RA_REGNUM)
1369 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1371 return_reg = (word >> 16) & 0x1f;
1375 cur_pc += ALPHA_INSN_SIZE;
1380 /* Failing that, do default to the customary RA. */
1381 if (return_reg == -1)
1382 return_reg = ALPHA_RA_REGNUM;
1383 info->return_reg = return_reg;
1385 val = get_frame_register_unsigned (this_frame, frame_reg);
1386 info->vfp = val + frame_size;
1388 /* Convert offsets to absolute addresses. See above about adding
1389 one to the offsets to make all detected offsets non-zero. */
1390 for (reg = 0; reg < ALPHA_NUM_REGS; ++reg)
1391 if (trad_frame_addr_p(info->saved_regs, reg))
1392 info->saved_regs[reg].addr += val - 1;
1394 /* The stack pointer of the previous frame is computed by popping
1395 the current stack frame. */
1396 if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM))
1397 trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp);
1402 /* Given a GDB frame, determine the address of the calling function's
1403 frame. This will be used to create a new GDB frame struct. */
1406 alpha_heuristic_frame_this_id (struct frame_info *this_frame,
1407 void **this_prologue_cache,
1408 struct frame_id *this_id)
1410 struct alpha_heuristic_unwind_cache *info
1411 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1413 *this_id = frame_id_build (info->vfp, info->start_pc);
1416 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
1418 static struct value *
1419 alpha_heuristic_frame_prev_register (struct frame_info *this_frame,
1420 void **this_prologue_cache, int regnum)
1422 struct alpha_heuristic_unwind_cache *info
1423 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1425 /* The PC of the previous frame is stored in the link register of
1426 the current frame. Frob regnum so that we pull the value from
1427 the correct place. */
1428 if (regnum == ALPHA_PC_REGNUM)
1429 regnum = info->return_reg;
1431 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1434 static const struct frame_unwind alpha_heuristic_frame_unwind = {
1436 default_frame_unwind_stop_reason,
1437 alpha_heuristic_frame_this_id,
1438 alpha_heuristic_frame_prev_register,
1440 default_frame_sniffer
1444 alpha_heuristic_frame_base_address (struct frame_info *this_frame,
1445 void **this_prologue_cache)
1447 struct alpha_heuristic_unwind_cache *info
1448 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1453 static const struct frame_base alpha_heuristic_frame_base = {
1454 &alpha_heuristic_frame_unwind,
1455 alpha_heuristic_frame_base_address,
1456 alpha_heuristic_frame_base_address,
1457 alpha_heuristic_frame_base_address
1460 /* Just like reinit_frame_cache, but with the right arguments to be
1461 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
1464 reinit_frame_cache_sfunc (const char *args,
1465 int from_tty, struct cmd_list_element *c)
1467 reinit_frame_cache ();
1471 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1472 dummy frame. The frame ID's base needs to match the TOS value
1473 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1476 static struct frame_id
1477 alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1480 base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM);
1481 return frame_id_build (base, get_frame_pc (this_frame));
1485 alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1488 pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM);
1493 /* Helper routines for alpha*-nat.c files to move register sets to and
1494 from core files. The UNIQUE pointer is allowed to be NULL, as most
1495 targets don't supply this value in their core files. */
1498 alpha_supply_int_regs (struct regcache *regcache, int regno,
1499 const void *r0_r30, const void *pc, const void *unique)
1501 const gdb_byte *regs = (const gdb_byte *) r0_r30;
1504 for (i = 0; i < 31; ++i)
1505 if (regno == i || regno == -1)
1506 regcache_raw_supply (regcache, i, regs + i * 8);
1508 if (regno == ALPHA_ZERO_REGNUM || regno == -1)
1510 const gdb_byte zero[8] = { 0 };
1512 regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero);
1515 if (regno == ALPHA_PC_REGNUM || regno == -1)
1516 regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc);
1518 if (regno == ALPHA_UNIQUE_REGNUM || regno == -1)
1519 regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique);
1523 alpha_fill_int_regs (const struct regcache *regcache,
1524 int regno, void *r0_r30, void *pc, void *unique)
1526 gdb_byte *regs = (gdb_byte *) r0_r30;
1529 for (i = 0; i < 31; ++i)
1530 if (regno == i || regno == -1)
1531 regcache_raw_collect (regcache, i, regs + i * 8);
1533 if (regno == ALPHA_PC_REGNUM || regno == -1)
1534 regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc);
1536 if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1))
1537 regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique);
1541 alpha_supply_fp_regs (struct regcache *regcache, int regno,
1542 const void *f0_f30, const void *fpcr)
1544 const gdb_byte *regs = (const gdb_byte *) f0_f30;
1547 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1548 if (regno == i || regno == -1)
1549 regcache_raw_supply (regcache, i,
1550 regs + (i - ALPHA_FP0_REGNUM) * 8);
1552 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1553 regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr);
1557 alpha_fill_fp_regs (const struct regcache *regcache,
1558 int regno, void *f0_f30, void *fpcr)
1560 gdb_byte *regs = (gdb_byte *) f0_f30;
1563 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1564 if (regno == i || regno == -1)
1565 regcache_raw_collect (regcache, i,
1566 regs + (i - ALPHA_FP0_REGNUM) * 8);
1568 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1569 regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr);
1574 /* Return nonzero if the G_floating register value in REG is equal to
1575 zero for FP control instructions. */
1578 fp_register_zero_p (LONGEST reg)
1580 /* Check that all bits except the sign bit are zero. */
1581 const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1;
1583 return ((reg & zero_mask) == 0);
1586 /* Return the value of the sign bit for the G_floating register
1587 value held in REG. */
1590 fp_register_sign_bit (LONGEST reg)
1592 const LONGEST sign_mask = (LONGEST) 1 << 63;
1594 return ((reg & sign_mask) != 0);
1597 /* alpha_software_single_step() is called just before we want to resume
1598 the inferior, if we want to single-step it but there is no hardware
1599 or kernel single-step support (NetBSD on Alpha, for example). We find
1600 the target of the coming instruction and breakpoint it. */
1603 alpha_next_pc (struct regcache *regcache, CORE_ADDR pc)
1605 struct gdbarch *gdbarch = regcache->arch ();
1612 insn = alpha_read_insn (gdbarch, pc);
1614 /* Opcode is top 6 bits. */
1615 op = (insn >> 26) & 0x3f;
1619 /* Jump format: target PC is:
1621 return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3);
1624 if ((op & 0x30) == 0x30)
1626 /* Branch format: target PC is:
1627 (new PC) + (4 * sext(displacement)) */
1628 if (op == 0x30 /* BR */
1629 || op == 0x34) /* BSR */
1632 offset = (insn & 0x001fffff);
1633 if (offset & 0x00100000)
1634 offset |= 0xffe00000;
1635 offset *= ALPHA_INSN_SIZE;
1636 return (pc + ALPHA_INSN_SIZE + offset);
1639 /* Need to determine if branch is taken; read RA. */
1640 regno = (insn >> 21) & 0x1f;
1643 case 0x31: /* FBEQ */
1644 case 0x36: /* FBGE */
1645 case 0x37: /* FBGT */
1646 case 0x33: /* FBLE */
1647 case 0x32: /* FBLT */
1648 case 0x35: /* FBNE */
1649 regno += gdbarch_fp0_regnum (gdbarch);
1652 rav = regcache_raw_get_signed (regcache, regno);
1656 case 0x38: /* BLBC */
1660 case 0x3c: /* BLBS */
1664 case 0x39: /* BEQ */
1668 case 0x3d: /* BNE */
1672 case 0x3a: /* BLT */
1676 case 0x3b: /* BLE */
1680 case 0x3f: /* BGT */
1684 case 0x3e: /* BGE */
1689 /* Floating point branches. */
1691 case 0x31: /* FBEQ */
1692 if (fp_register_zero_p (rav))
1695 case 0x36: /* FBGE */
1696 if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav))
1699 case 0x37: /* FBGT */
1700 if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav))
1703 case 0x33: /* FBLE */
1704 if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav))
1707 case 0x32: /* FBLT */
1708 if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav))
1711 case 0x35: /* FBNE */
1712 if (! fp_register_zero_p (rav))
1718 /* Not a branch or branch not taken; target PC is:
1720 return (pc + ALPHA_INSN_SIZE);
1723 std::vector<CORE_ADDR>
1724 alpha_software_single_step (struct regcache *regcache)
1726 CORE_ADDR pc = alpha_next_pc (regcache, regcache_read_pc (regcache));
1732 /* Initialize the current architecture based on INFO. If possible, re-use an
1733 architecture from ARCHES, which is a list of architectures already created
1734 during this debugging session.
1736 Called e.g. at program startup, when reading a core file, and when reading
1739 static struct gdbarch *
1740 alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1742 struct gdbarch_tdep *tdep;
1743 struct gdbarch *gdbarch;
1745 /* Find a candidate among extant architectures. */
1746 arches = gdbarch_list_lookup_by_info (arches, &info);
1748 return arches->gdbarch;
1750 tdep = XCNEW (struct gdbarch_tdep);
1751 gdbarch = gdbarch_alloc (&info, tdep);
1753 /* Lowest text address. This is used by heuristic_proc_start()
1754 to decide when to stop looking. */
1755 tdep->vm_min_address = (CORE_ADDR) 0x120000000LL;
1757 tdep->dynamic_sigtramp_offset = NULL;
1758 tdep->sigcontext_addr = NULL;
1759 tdep->sc_pc_offset = 2 * 8;
1760 tdep->sc_regs_offset = 4 * 8;
1761 tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8;
1763 tdep->jb_pc = -1; /* longjmp support not enabled by default. */
1765 tdep->return_in_memory = alpha_return_in_memory_always;
1768 set_gdbarch_short_bit (gdbarch, 16);
1769 set_gdbarch_int_bit (gdbarch, 32);
1770 set_gdbarch_long_bit (gdbarch, 64);
1771 set_gdbarch_long_long_bit (gdbarch, 64);
1772 set_gdbarch_wchar_bit (gdbarch, 64);
1773 set_gdbarch_wchar_signed (gdbarch, 0);
1774 set_gdbarch_float_bit (gdbarch, 32);
1775 set_gdbarch_double_bit (gdbarch, 64);
1776 set_gdbarch_long_double_bit (gdbarch, 64);
1777 set_gdbarch_ptr_bit (gdbarch, 64);
1780 set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS);
1781 set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM);
1782 set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM);
1783 set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM);
1785 set_gdbarch_register_name (gdbarch, alpha_register_name);
1786 set_gdbarch_register_type (gdbarch, alpha_register_type);
1788 set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register);
1789 set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register);
1791 set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p);
1792 set_gdbarch_register_to_value (gdbarch, alpha_register_to_value);
1793 set_gdbarch_value_to_register (gdbarch, alpha_value_to_register);
1795 set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p);
1797 /* Prologue heuristics. */
1798 set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue);
1802 set_gdbarch_return_value (gdbarch, alpha_return_value);
1804 /* Settings for calling functions in the inferior. */
1805 set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call);
1807 /* Methods for saving / extracting a dummy frame's ID. */
1808 set_gdbarch_dummy_id (gdbarch, alpha_dummy_id);
1810 /* Return the unwound PC value. */
1811 set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc);
1813 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1814 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
1816 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1817 alpha_breakpoint::kind_from_pc);
1818 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1819 alpha_breakpoint::bp_from_kind);
1820 set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE);
1821 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1823 /* Handles single stepping of atomic sequences. */
1824 set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence);
1826 /* Hook in ABI-specific overrides, if they have been registered. */
1827 gdbarch_init_osabi (info, gdbarch);
1829 /* Now that we have tuned the configuration, set a few final things
1830 based on what the OS ABI has told us. */
1832 if (tdep->jb_pc >= 0)
1833 set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target);
1835 frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind);
1836 frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind);
1838 frame_base_set_default (gdbarch, &alpha_heuristic_frame_base);
1844 alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1846 dwarf2_append_unwinders (gdbarch);
1847 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
1851 _initialize_alpha_tdep (void)
1854 gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL);
1856 /* Let the user set the fence post for heuristic_proc_start. */
1858 /* We really would like to have both "0" and "unlimited" work, but
1859 command.c doesn't deal with that. So make it a var_zinteger
1860 because the user can always use "999999" or some such for unlimited. */
1861 /* We need to throw away the frame cache when we set this, since it
1862 might change our ability to get backtraces. */
1863 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
1864 &heuristic_fence_post, _("\
1865 Set the distance searched for the start of a function."), _("\
1866 Show the distance searched for the start of a function."), _("\
1867 If you are debugging a stripped executable, GDB needs to search through the\n\
1868 program for the start of a function. This command sets the distance of the\n\
1869 search. The only need to set it is when debugging a stripped executable."),
1870 reinit_frame_cache_sfunc,
1871 NULL, /* FIXME: i18n: The distance searched for
1872 the start of a function is \"%d\". */
1873 &setlist, &showlist);