1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1993-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
25 #include "dwarf2-frame.h"
36 #include "reggroups.h"
37 #include "arch-utils.h"
41 #include "trad-frame.h"
45 #include "alpha-tdep.h"
48 /* Instruction decoding. The notations for registers, immediates and
49 opcodes are the same as the one used in Compaq's Alpha architecture
52 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
54 /* Memory instruction format */
55 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
56 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
57 #define MEM_DISP(insn) \
58 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
60 static const int lda_opcode = 0x08;
61 static const int stq_opcode = 0x2d;
63 /* Branch instruction format */
64 #define BR_RA(insn) MEM_RA(insn)
66 static const int br_opcode = 0x30;
67 static const int bne_opcode = 0x3d;
69 /* Operate instruction format */
70 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
71 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
72 #define OPR_RA(insn) MEM_RA(insn)
73 #define OPR_RC(insn) ((insn & 0x1f))
74 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
76 static const int subq_opcode = 0x10;
77 static const int subq_function = 0x29;
80 /* Return the name of the REGNO register.
82 An empty name corresponds to a register number that used to
83 be used for a virtual register. That virtual register has
84 been removed, but the index is still reserved to maintain
85 compatibility with existing remote alpha targets. */
88 alpha_register_name (struct gdbarch *gdbarch, int regno)
90 static const char * const register_names[] =
92 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
93 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
94 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
95 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
96 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
97 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
98 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
99 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
105 if (regno >= ARRAY_SIZE(register_names))
107 return register_names[regno];
111 alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
113 return (strlen (alpha_register_name (gdbarch, regno)) == 0);
117 alpha_cannot_store_register (struct gdbarch *gdbarch, int regno)
119 return (regno == ALPHA_ZERO_REGNUM
120 || strlen (alpha_register_name (gdbarch, regno)) == 0);
124 alpha_register_type (struct gdbarch *gdbarch, int regno)
126 if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM)
127 return builtin_type (gdbarch)->builtin_data_ptr;
128 if (regno == ALPHA_PC_REGNUM)
129 return builtin_type (gdbarch)->builtin_func_ptr;
131 /* Don't need to worry about little vs big endian until
132 some jerk tries to port to alpha-unicosmk. */
133 if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31)
134 return builtin_type (gdbarch)->builtin_double;
136 return builtin_type (gdbarch)->builtin_int64;
139 /* Is REGNUM a member of REGGROUP? */
142 alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
143 struct reggroup *group)
145 /* Filter out any registers eliminated, but whose regnum is
146 reserved for backward compatibility, e.g. the vfp. */
147 if (gdbarch_register_name (gdbarch, regnum) == NULL
148 || *gdbarch_register_name (gdbarch, regnum) == '\0')
151 if (group == all_reggroup)
154 /* Zero should not be saved or restored. Technically it is a general
155 register (just as $f31 would be a float if we represented it), but
156 there's no point displaying it during "info regs", so leave it out
157 of all groups except for "all". */
158 if (regnum == ALPHA_ZERO_REGNUM)
161 /* All other registers are saved and restored. */
162 if (group == save_reggroup || group == restore_reggroup)
165 /* All other groups are non-overlapping. */
167 /* Since this is really a PALcode memory slot... */
168 if (regnum == ALPHA_UNIQUE_REGNUM)
169 return group == system_reggroup;
171 /* Force the FPCR to be considered part of the floating point state. */
172 if (regnum == ALPHA_FPCR_REGNUM)
173 return group == float_reggroup;
175 if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31)
176 return group == float_reggroup;
178 return group == general_reggroup;
181 /* The following represents exactly the conversion performed by
182 the LDS instruction. This applies to both single-precision
183 floating point and 32-bit integers. */
186 alpha_lds (struct gdbarch *gdbarch, void *out, const void *in)
188 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order);
191 ULONGEST frac = (mem >> 0) & 0x7fffff;
192 ULONGEST sign = (mem >> 31) & 1;
193 ULONGEST exp_msb = (mem >> 30) & 1;
194 ULONGEST exp_low = (mem >> 23) & 0x7f;
197 exp = (exp_msb << 10) | exp_low;
209 reg = (sign << 63) | (exp << 52) | (frac << 29);
210 store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg);
213 /* Similarly, this represents exactly the conversion performed by
214 the STS instruction. */
217 alpha_sts (struct gdbarch *gdbarch, void *out, const void *in)
219 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
222 reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order);
223 mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff);
224 store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem);
227 /* The alpha needs a conversion between register and memory format if the
228 register is a floating point register and memory format is float, as the
229 register format must be double or memory format is an integer with 4
230 bytes, as the representation of integers in floating point
231 registers is different. */
234 alpha_convert_register_p (struct gdbarch *gdbarch, int regno,
237 return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31
238 && TYPE_LENGTH (type) == 4);
242 alpha_register_to_value (struct frame_info *frame, int regnum,
243 struct type *valtype, gdb_byte *out,
244 int *optimizedp, int *unavailablep)
246 struct gdbarch *gdbarch = get_frame_arch (frame);
247 gdb_byte in[MAX_REGISTER_SIZE];
249 /* Convert to TYPE. */
250 if (!get_frame_register_bytes (frame, regnum, 0,
251 register_size (gdbarch, regnum),
252 in, optimizedp, unavailablep))
255 gdb_assert (TYPE_LENGTH (valtype) == 4);
256 alpha_sts (gdbarch, out, in);
257 *optimizedp = *unavailablep = 0;
262 alpha_value_to_register (struct frame_info *frame, int regnum,
263 struct type *valtype, const gdb_byte *in)
265 gdb_byte out[MAX_REGISTER_SIZE];
267 gdb_assert (TYPE_LENGTH (valtype) == 4);
268 alpha_lds (get_frame_arch (frame), out, in);
270 put_frame_register (frame, regnum, out);
274 /* The alpha passes the first six arguments in the registers, the rest on
275 the stack. The register arguments are stored in ARG_REG_BUFFER, and
276 then moved into the register file; this simplifies the passing of a
277 large struct which extends from the registers to the stack, plus avoids
278 three ptrace invocations per word.
280 We don't bother tracking which register values should go in integer
281 regs or fp regs; we load the same values into both.
283 If the called function is returning a structure, the address of the
284 structure to be returned is passed as a hidden first argument. */
287 alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
288 struct regcache *regcache, CORE_ADDR bp_addr,
289 int nargs, struct value **args, CORE_ADDR sp,
290 int struct_return, CORE_ADDR struct_addr)
292 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
294 int accumulate_size = struct_return ? 8 : 0;
297 const gdb_byte *contents;
301 struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs);
302 struct alpha_arg *m_arg;
303 gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS];
304 int required_arg_regs;
305 CORE_ADDR func_addr = find_function_addr (function, NULL);
307 /* The ABI places the address of the called function in T12. */
308 regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr);
310 /* Set the return address register to point to the entry point
311 of the program, where a breakpoint lies in wait. */
312 regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr);
314 /* Lay out the arguments in memory. */
315 for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++)
317 struct value *arg = args[i];
318 struct type *arg_type = check_typedef (value_type (arg));
320 /* Cast argument to long if necessary as the compiler does it too. */
321 switch (TYPE_CODE (arg_type))
326 case TYPE_CODE_RANGE:
328 if (TYPE_LENGTH (arg_type) == 4)
330 /* 32-bit values must be sign-extended to 64 bits
331 even if the base data type is unsigned. */
332 arg_type = builtin_type (gdbarch)->builtin_int32;
333 arg = value_cast (arg_type, arg);
335 if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE)
337 arg_type = builtin_type (gdbarch)->builtin_int64;
338 arg = value_cast (arg_type, arg);
343 /* "float" arguments loaded in registers must be passed in
344 register format, aka "double". */
345 if (accumulate_size < sizeof (arg_reg_buffer)
346 && TYPE_LENGTH (arg_type) == 4)
348 arg_type = builtin_type (gdbarch)->builtin_double;
349 arg = value_cast (arg_type, arg);
351 /* Tru64 5.1 has a 128-bit long double, and passes this by
352 invisible reference. No one else uses this data type. */
353 else if (TYPE_LENGTH (arg_type) == 16)
355 /* Allocate aligned storage. */
356 sp = (sp & -16) - 16;
358 /* Write the real data into the stack. */
359 write_memory (sp, value_contents (arg), 16);
361 /* Construct the indirection. */
362 arg_type = lookup_pointer_type (arg_type);
363 arg = value_from_pointer (arg_type, sp);
367 case TYPE_CODE_COMPLEX:
368 /* ??? The ABI says that complex values are passed as two
369 separate scalar values. This distinction only matters
370 for complex float. However, GCC does not implement this. */
372 /* Tru64 5.1 has a 128-bit long double, and passes this by
373 invisible reference. */
374 if (TYPE_LENGTH (arg_type) == 32)
376 /* Allocate aligned storage. */
377 sp = (sp & -16) - 16;
379 /* Write the real data into the stack. */
380 write_memory (sp, value_contents (arg), 32);
382 /* Construct the indirection. */
383 arg_type = lookup_pointer_type (arg_type);
384 arg = value_from_pointer (arg_type, sp);
391 m_arg->len = TYPE_LENGTH (arg_type);
392 m_arg->offset = accumulate_size;
393 accumulate_size = (accumulate_size + m_arg->len + 7) & ~7;
394 m_arg->contents = value_contents (arg);
397 /* Determine required argument register loads, loading an argument register
398 is expensive as it uses three ptrace calls. */
399 required_arg_regs = accumulate_size / 8;
400 if (required_arg_regs > ALPHA_NUM_ARG_REGS)
401 required_arg_regs = ALPHA_NUM_ARG_REGS;
403 /* Make room for the arguments on the stack. */
404 if (accumulate_size < sizeof(arg_reg_buffer))
407 accumulate_size -= sizeof(arg_reg_buffer);
408 sp -= accumulate_size;
410 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
413 /* `Push' arguments on the stack. */
414 for (i = nargs; m_arg--, --i >= 0;)
416 const gdb_byte *contents = m_arg->contents;
417 int offset = m_arg->offset;
418 int len = m_arg->len;
420 /* Copy the bytes destined for registers into arg_reg_buffer. */
421 if (offset < sizeof(arg_reg_buffer))
423 if (offset + len <= sizeof(arg_reg_buffer))
425 memcpy (arg_reg_buffer + offset, contents, len);
430 int tlen = sizeof(arg_reg_buffer) - offset;
431 memcpy (arg_reg_buffer + offset, contents, tlen);
438 /* Everything else goes to the stack. */
439 write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len);
442 store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE,
443 byte_order, struct_addr);
445 /* Load the argument registers. */
446 for (i = 0; i < required_arg_regs; i++)
448 regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i,
449 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
450 regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i,
451 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
454 /* Finally, update the stack pointer. */
455 regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp);
460 /* Extract from REGCACHE the value about to be returned from a function
461 and copy it into VALBUF. */
464 alpha_extract_return_value (struct type *valtype, struct regcache *regcache,
467 struct gdbarch *gdbarch = get_regcache_arch (regcache);
468 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
469 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
472 switch (TYPE_CODE (valtype))
475 switch (TYPE_LENGTH (valtype))
478 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer);
479 alpha_sts (gdbarch, valbuf, raw_buffer);
483 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
487 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
488 read_memory (l, valbuf, 16);
492 internal_error (__FILE__, __LINE__,
493 _("unknown floating point width"));
497 case TYPE_CODE_COMPLEX:
498 switch (TYPE_LENGTH (valtype))
501 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
502 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
506 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
507 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
511 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
512 read_memory (l, valbuf, 32);
516 internal_error (__FILE__, __LINE__,
517 _("unknown floating point width"));
522 /* Assume everything else degenerates to an integer. */
523 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
524 store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l);
529 /* Insert the given value into REGCACHE as if it was being
530 returned by a function. */
533 alpha_store_return_value (struct type *valtype, struct regcache *regcache,
534 const gdb_byte *valbuf)
536 struct gdbarch *gdbarch = get_regcache_arch (regcache);
537 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
540 switch (TYPE_CODE (valtype))
543 switch (TYPE_LENGTH (valtype))
546 alpha_lds (gdbarch, raw_buffer, valbuf);
547 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer);
551 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
555 /* FIXME: 128-bit long doubles are returned like structures:
556 by writing into indirect storage provided by the caller
557 as the first argument. */
558 error (_("Cannot set a 128-bit long double return value."));
561 internal_error (__FILE__, __LINE__,
562 _("unknown floating point width"));
566 case TYPE_CODE_COMPLEX:
567 switch (TYPE_LENGTH (valtype))
570 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
571 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
575 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
576 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
580 /* FIXME: 128-bit long doubles are returned like structures:
581 by writing into indirect storage provided by the caller
582 as the first argument. */
583 error (_("Cannot set a 128-bit long double return value."));
586 internal_error (__FILE__, __LINE__,
587 _("unknown floating point width"));
592 /* Assume everything else degenerates to an integer. */
593 /* 32-bit values must be sign-extended to 64 bits
594 even if the base data type is unsigned. */
595 if (TYPE_LENGTH (valtype) == 4)
596 valtype = builtin_type (gdbarch)->builtin_int32;
597 l = unpack_long (valtype, valbuf);
598 regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l);
603 static enum return_value_convention
604 alpha_return_value (struct gdbarch *gdbarch, struct value *function,
605 struct type *type, struct regcache *regcache,
606 gdb_byte *readbuf, const gdb_byte *writebuf)
608 enum type_code code = TYPE_CODE (type);
610 if ((code == TYPE_CODE_STRUCT
611 || code == TYPE_CODE_UNION
612 || code == TYPE_CODE_ARRAY)
613 && gdbarch_tdep (gdbarch)->return_in_memory (type))
618 regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr);
619 read_memory (addr, readbuf, TYPE_LENGTH (type));
622 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
626 alpha_extract_return_value (type, regcache, readbuf);
628 alpha_store_return_value (type, regcache, writebuf);
630 return RETURN_VALUE_REGISTER_CONVENTION;
634 alpha_return_in_memory_always (struct type *type)
640 constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
642 typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint;
645 /* This returns the PC of the first insn after the prologue.
646 If we can't find the prologue, then return 0. */
649 alpha_after_prologue (CORE_ADDR pc)
651 struct symtab_and_line sal;
652 CORE_ADDR func_addr, func_end;
654 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
657 sal = find_pc_line (func_addr, 0);
658 if (sal.end < func_end)
661 /* The line after the prologue is after the end of the function. In this
662 case, tell the caller to find the prologue the hard way. */
666 /* Read an instruction from memory at PC, looking through breakpoints. */
669 alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
671 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
672 gdb_byte buf[ALPHA_INSN_SIZE];
675 res = target_read_memory (pc, buf, sizeof (buf));
677 memory_error (TARGET_XFER_E_IO, pc);
678 return extract_unsigned_integer (buf, sizeof (buf), byte_order);
681 /* To skip prologues, I use this predicate. Returns either PC itself
682 if the code at PC does not look like a function prologue; otherwise
683 returns an address that (if we're lucky) follows the prologue. If
684 LENIENT, then we must skip everything which is involved in setting
685 up the frame (it's OK to skip more, just so long as we don't skip
686 anything which might clobber the registers which are being saved. */
689 alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
693 CORE_ADDR post_prologue_pc;
694 gdb_byte buf[ALPHA_INSN_SIZE];
696 /* Silently return the unaltered pc upon memory errors.
697 This could happen on OSF/1 if decode_line_1 tries to skip the
698 prologue for quickstarted shared library functions when the
699 shared library is not yet mapped in.
700 Reading target memory is slow over serial lines, so we perform
701 this check only if the target has shared libraries (which all
702 Alpha targets do). */
703 if (target_read_memory (pc, buf, sizeof (buf)))
706 /* See if we can determine the end of the prologue via the symbol table.
707 If so, then return either PC, or the PC after the prologue, whichever
710 post_prologue_pc = alpha_after_prologue (pc);
711 if (post_prologue_pc != 0)
712 return std::max (pc, post_prologue_pc);
714 /* Can't determine prologue from the symbol table, need to examine
717 /* Skip the typical prologue instructions. These are the stack adjustment
718 instruction and the instructions that save registers on the stack
719 or in the gcc frame. */
720 for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE)
722 inst = alpha_read_insn (gdbarch, pc + offset);
724 if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
726 if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
728 if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
730 if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
733 if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
734 || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
735 && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */
738 if (inst == 0x47de040f) /* bis sp,sp,fp */
740 if (inst == 0x47fe040f) /* bis zero,sp,fp */
749 static const int ldl_l_opcode = 0x2a;
750 static const int ldq_l_opcode = 0x2b;
751 static const int stl_c_opcode = 0x2e;
752 static const int stq_c_opcode = 0x2f;
754 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L
755 instruction and ending with a STL_C/STQ_C instruction. If such a sequence
756 is found, attempt to step through it. A breakpoint is placed at the end of
759 static std::vector<CORE_ADDR>
760 alpha_deal_with_atomic_sequence (struct regcache *regcache)
762 struct gdbarch *gdbarch = get_regcache_arch (regcache);
763 CORE_ADDR pc = regcache_read_pc (regcache);
764 CORE_ADDR breaks[2] = {-1, -1};
766 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
767 unsigned int insn = alpha_read_insn (gdbarch, loc);
770 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
771 const int atomic_sequence_length = 16; /* Instruction sequence length. */
772 int bc_insn_count = 0; /* Conditional branch instruction count. */
774 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
775 if (INSN_OPCODE (insn) != ldl_l_opcode
776 && INSN_OPCODE (insn) != ldq_l_opcode)
779 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
781 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
783 loc += ALPHA_INSN_SIZE;
784 insn = alpha_read_insn (gdbarch, loc);
786 /* Assume that there is at most one branch in the atomic
787 sequence. If a branch is found, put a breakpoint in
788 its destination address. */
789 if (INSN_OPCODE (insn) >= br_opcode)
791 int immediate = (insn & 0x001fffff) << 2;
793 immediate = (immediate ^ 0x400000) - 0x400000;
795 if (bc_insn_count >= 1)
796 return {}; /* More than one branch found, fallback
797 to the standard single-step code. */
799 breaks[1] = loc + ALPHA_INSN_SIZE + immediate;
805 if (INSN_OPCODE (insn) == stl_c_opcode
806 || INSN_OPCODE (insn) == stq_c_opcode)
810 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
811 if (INSN_OPCODE (insn) != stl_c_opcode
812 && INSN_OPCODE (insn) != stq_c_opcode)
816 loc += ALPHA_INSN_SIZE;
818 /* Insert a breakpoint right after the end of the atomic sequence. */
821 /* Check for duplicated breakpoints. Check also for a breakpoint
822 placed (branch instruction's destination) anywhere in sequence. */
824 && (breaks[1] == breaks[0]
825 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
828 std::vector<CORE_ADDR> next_pcs;
830 for (index = 0; index <= last_breakpoint; index++)
831 next_pcs.push_back (breaks[index]);
837 /* Figure out where the longjmp will land.
838 We expect the first arg to be a pointer to the jmp_buf structure from
839 which we extract the PC (JB_PC) that we will land at. The PC is copied
840 into the "pc". This routine returns true on success. */
843 alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
845 struct gdbarch *gdbarch = get_frame_arch (frame);
846 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
847 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
849 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
851 jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM);
853 if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size),
854 raw_buffer, tdep->jb_elt_size))
857 *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order);
862 /* Frame unwinder for signal trampolines. We use alpha tdep bits that
863 describe the location and shape of the sigcontext structure. After
864 that, all registers are in memory, so it's easy. */
865 /* ??? Shouldn't we be able to do this generically, rather than with
866 OSABI data specific to Alpha? */
868 struct alpha_sigtramp_unwind_cache
870 CORE_ADDR sigcontext_addr;
873 static struct alpha_sigtramp_unwind_cache *
874 alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
875 void **this_prologue_cache)
877 struct alpha_sigtramp_unwind_cache *info;
878 struct gdbarch_tdep *tdep;
880 if (*this_prologue_cache)
881 return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache;
883 info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache);
884 *this_prologue_cache = info;
886 tdep = gdbarch_tdep (get_frame_arch (this_frame));
887 info->sigcontext_addr = tdep->sigcontext_addr (this_frame);
892 /* Return the address of REGNUM in a sigtramp frame. Since this is
893 all arithmetic, it doesn't seem worthwhile to cache it. */
896 alpha_sigtramp_register_address (struct gdbarch *gdbarch,
897 CORE_ADDR sigcontext_addr, int regnum)
899 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
901 if (regnum >= 0 && regnum < 32)
902 return sigcontext_addr + tdep->sc_regs_offset + regnum * 8;
903 else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32)
904 return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8;
905 else if (regnum == ALPHA_PC_REGNUM)
906 return sigcontext_addr + tdep->sc_pc_offset;
911 /* Given a GDB frame, determine the address of the calling function's
912 frame. This will be used to create a new GDB frame struct. */
915 alpha_sigtramp_frame_this_id (struct frame_info *this_frame,
916 void **this_prologue_cache,
917 struct frame_id *this_id)
919 struct gdbarch *gdbarch = get_frame_arch (this_frame);
920 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
921 struct alpha_sigtramp_unwind_cache *info
922 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
923 CORE_ADDR stack_addr, code_addr;
925 /* If the OSABI couldn't locate the sigcontext, give up. */
926 if (info->sigcontext_addr == 0)
929 /* If we have dynamic signal trampolines, find their start.
930 If we do not, then we must assume there is a symbol record
931 that can provide the start address. */
932 if (tdep->dynamic_sigtramp_offset)
935 code_addr = get_frame_pc (this_frame);
936 offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr);
943 code_addr = get_frame_func (this_frame);
945 /* The stack address is trivially read from the sigcontext. */
946 stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr,
948 stack_addr = get_frame_memory_unsigned (this_frame, stack_addr,
949 ALPHA_REGISTER_SIZE);
951 *this_id = frame_id_build (stack_addr, code_addr);
954 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
956 static struct value *
957 alpha_sigtramp_frame_prev_register (struct frame_info *this_frame,
958 void **this_prologue_cache, int regnum)
960 struct alpha_sigtramp_unwind_cache *info
961 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
964 if (info->sigcontext_addr != 0)
966 /* All integer and fp registers are stored in memory. */
967 addr = alpha_sigtramp_register_address (get_frame_arch (this_frame),
968 info->sigcontext_addr, regnum);
970 return frame_unwind_got_memory (this_frame, regnum, addr);
973 /* This extra register may actually be in the sigcontext, but our
974 current description of it in alpha_sigtramp_frame_unwind_cache
975 doesn't include it. Too bad. Fall back on whatever's in the
977 return frame_unwind_got_register (this_frame, regnum, regnum);
981 alpha_sigtramp_frame_sniffer (const struct frame_unwind *self,
982 struct frame_info *this_frame,
983 void **this_prologue_cache)
985 struct gdbarch *gdbarch = get_frame_arch (this_frame);
986 CORE_ADDR pc = get_frame_pc (this_frame);
989 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
990 look at tramp-frame.h and other simplier per-architecture
991 sigtramp unwinders. */
993 /* We shouldn't even bother to try if the OSABI didn't register a
994 sigcontext_addr handler or pc_in_sigtramp hander. */
995 if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL)
997 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL)
1000 /* Otherwise we should be in a signal frame. */
1001 find_pc_partial_function (pc, &name, NULL, NULL);
1002 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name))
1008 static const struct frame_unwind alpha_sigtramp_frame_unwind = {
1010 default_frame_unwind_stop_reason,
1011 alpha_sigtramp_frame_this_id,
1012 alpha_sigtramp_frame_prev_register,
1014 alpha_sigtramp_frame_sniffer
1019 /* Heuristic_proc_start may hunt through the text section for a long
1020 time across a 2400 baud serial line. Allows the user to limit this
1022 static int heuristic_fence_post = 0;
1024 /* Attempt to locate the start of the function containing PC. We assume that
1025 the previous function ends with an about_to_return insn. Not foolproof by
1026 any means, since gcc is happy to put the epilogue in the middle of a
1027 function. But we're guessing anyway... */
1030 alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
1032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1033 CORE_ADDR last_non_nop = pc;
1034 CORE_ADDR fence = pc - heuristic_fence_post;
1035 CORE_ADDR orig_pc = pc;
1037 struct inferior *inf;
1042 /* First see if we can find the start of the function from minimal
1043 symbol information. This can succeed with a binary that doesn't
1044 have debug info, but hasn't been stripped. */
1045 func = get_pc_function_start (pc);
1049 if (heuristic_fence_post == -1
1050 || fence < tdep->vm_min_address)
1051 fence = tdep->vm_min_address;
1053 /* Search back for previous return; also stop at a 0, which might be
1054 seen for instance before the start of a code section. Don't include
1055 nops, since this usually indicates padding between functions. */
1056 for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE)
1058 unsigned int insn = alpha_read_insn (gdbarch, pc);
1061 case 0: /* invalid insn */
1062 case 0x6bfa8001: /* ret $31,($26),1 */
1063 return last_non_nop;
1065 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
1066 case 0x47ff041f: /* nop: bis $31,$31,$31 */
1075 inf = current_inferior ();
1077 /* It's not clear to me why we reach this point when stopping quietly,
1078 but with this test, at least we don't print out warnings for every
1079 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
1080 if (inf->control.stop_soon == NO_STOP_QUIETLY)
1082 static int blurb_printed = 0;
1084 if (fence == tdep->vm_min_address)
1085 warning (_("Hit beginning of text section without finding \
1086 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1088 warning (_("Hit heuristic-fence-post without finding \
1089 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1093 printf_filtered (_("\
1094 This warning occurs if you are debugging a function without any symbols\n\
1095 (for example, in a stripped executable). In that case, you may wish to\n\
1096 increase the size of the search with the `set heuristic-fence-post' command.\n\
1098 Otherwise, you told GDB there was a function where there isn't one, or\n\
1099 (more likely) you have encountered a bug in GDB.\n"));
1107 /* Fallback alpha frame unwinder. Uses instruction scanning and knows
1108 something about the traditional layout of alpha stack frames. */
1110 struct alpha_heuristic_unwind_cache
1114 struct trad_frame_saved_reg *saved_regs;
1118 /* If a probing loop sequence starts at PC, simulate it and compute
1119 FRAME_SIZE and PC after its execution. Otherwise, return with PC and
1120 FRAME_SIZE unchanged. */
1123 alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc,
1126 CORE_ADDR cur_pc = *pc;
1127 int cur_frame_size = *frame_size;
1128 int nb_of_iterations, reg_index, reg_probe;
1131 /* The following pattern is recognized as a probing loop:
1133 lda REG_INDEX,NB_OF_ITERATIONS
1134 lda REG_PROBE,<immediate>(sp)
1137 stq zero,<immediate>(REG_PROBE)
1138 subq REG_INDEX,0x1,REG_INDEX
1139 lda REG_PROBE,<immediate>(REG_PROBE)
1140 bne REG_INDEX, LOOP_START
1142 lda sp,<immediate>(REG_PROBE)
1144 If anything different is found, the function returns without
1145 changing PC and FRAME_SIZE. Otherwise, PC will point immediately
1146 after this sequence, and FRAME_SIZE will be updated. */
1148 /* lda REG_INDEX,NB_OF_ITERATIONS */
1150 insn = alpha_read_insn (gdbarch, cur_pc);
1151 if (INSN_OPCODE (insn) != lda_opcode)
1153 reg_index = MEM_RA (insn);
1154 nb_of_iterations = MEM_DISP (insn);
1156 /* lda REG_PROBE,<immediate>(sp) */
1158 cur_pc += ALPHA_INSN_SIZE;
1159 insn = alpha_read_insn (gdbarch, cur_pc);
1160 if (INSN_OPCODE (insn) != lda_opcode
1161 || MEM_RB (insn) != ALPHA_SP_REGNUM)
1163 reg_probe = MEM_RA (insn);
1164 cur_frame_size -= MEM_DISP (insn);
1166 /* stq zero,<immediate>(REG_PROBE) */
1168 cur_pc += ALPHA_INSN_SIZE;
1169 insn = alpha_read_insn (gdbarch, cur_pc);
1170 if (INSN_OPCODE (insn) != stq_opcode
1171 || MEM_RA (insn) != 0x1f
1172 || MEM_RB (insn) != reg_probe)
1175 /* subq REG_INDEX,0x1,REG_INDEX */
1177 cur_pc += ALPHA_INSN_SIZE;
1178 insn = alpha_read_insn (gdbarch, cur_pc);
1179 if (INSN_OPCODE (insn) != subq_opcode
1180 || !OPR_HAS_IMMEDIATE (insn)
1181 || OPR_FUNCTION (insn) != subq_function
1182 || OPR_LIT(insn) != 1
1183 || OPR_RA (insn) != reg_index
1184 || OPR_RC (insn) != reg_index)
1187 /* lda REG_PROBE,<immediate>(REG_PROBE) */
1189 cur_pc += ALPHA_INSN_SIZE;
1190 insn = alpha_read_insn (gdbarch, cur_pc);
1191 if (INSN_OPCODE (insn) != lda_opcode
1192 || MEM_RA (insn) != reg_probe
1193 || MEM_RB (insn) != reg_probe)
1195 cur_frame_size -= MEM_DISP (insn) * nb_of_iterations;
1197 /* bne REG_INDEX, LOOP_START */
1199 cur_pc += ALPHA_INSN_SIZE;
1200 insn = alpha_read_insn (gdbarch, cur_pc);
1201 if (INSN_OPCODE (insn) != bne_opcode
1202 || MEM_RA (insn) != reg_index)
1205 /* lda sp,<immediate>(REG_PROBE) */
1207 cur_pc += ALPHA_INSN_SIZE;
1208 insn = alpha_read_insn (gdbarch, cur_pc);
1209 if (INSN_OPCODE (insn) != lda_opcode
1210 || MEM_RA (insn) != ALPHA_SP_REGNUM
1211 || MEM_RB (insn) != reg_probe)
1213 cur_frame_size -= MEM_DISP (insn);
1216 *frame_size = cur_frame_size;
1219 static struct alpha_heuristic_unwind_cache *
1220 alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame,
1221 void **this_prologue_cache,
1224 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1225 struct alpha_heuristic_unwind_cache *info;
1227 CORE_ADDR limit_pc, cur_pc;
1228 int frame_reg, frame_size, return_reg, reg;
1230 if (*this_prologue_cache)
1231 return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache;
1233 info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache);
1234 *this_prologue_cache = info;
1235 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1237 limit_pc = get_frame_pc (this_frame);
1239 start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc);
1240 info->start_pc = start_pc;
1242 frame_reg = ALPHA_SP_REGNUM;
1246 /* If we've identified a likely place to start, do code scanning. */
1249 /* Limit the forward search to 50 instructions. */
1250 if (start_pc + 200 < limit_pc)
1251 limit_pc = start_pc + 200;
1253 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE)
1255 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1257 if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1261 /* Consider only the first stack allocation instruction
1262 to contain the static size of the frame. */
1263 if (frame_size == 0)
1264 frame_size = (-word) & 0xffff;
1268 /* Exit loop if a positive stack adjustment is found, which
1269 usually means that the stack cleanup code in the function
1270 epilogue is reached. */
1274 else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1276 reg = (word & 0x03e00000) >> 21;
1278 /* Ignore this instruction if we have already encountered
1279 an instruction saving the same register earlier in the
1280 function code. The current instruction does not tell
1281 us where the original value upon function entry is saved.
1282 All it says is that the function we are scanning reused
1283 that register for some computation of its own, and is now
1284 saving its result. */
1285 if (trad_frame_addr_p(info->saved_regs, reg))
1291 /* Do not compute the address where the register was saved yet,
1292 because we don't know yet if the offset will need to be
1293 relative to $sp or $fp (we can not compute the address
1294 relative to $sp if $sp is updated during the execution of
1295 the current subroutine, for instance when doing some alloca).
1296 So just store the offset for the moment, and compute the
1297 address later when we know whether this frame has a frame
1299 /* Hack: temporarily add one, so that the offset is non-zero
1300 and we can tell which registers have save offsets below. */
1301 info->saved_regs[reg].addr = (word & 0xffff) + 1;
1303 /* Starting with OSF/1-3.2C, the system libraries are shipped
1304 without local symbols, but they still contain procedure
1305 descriptors without a symbol reference. GDB is currently
1306 unable to find these procedure descriptors and uses
1307 heuristic_proc_desc instead.
1308 As some low level compiler support routines (__div*, __add*)
1309 use a non-standard return address register, we have to
1310 add some heuristics to determine the return address register,
1311 or stepping over these routines will fail.
1312 Usually the return address register is the first register
1313 saved on the stack, but assembler optimization might
1314 rearrange the register saves.
1315 So we recognize only a few registers (t7, t9, ra) within
1316 the procedure prologue as valid return address registers.
1317 If we encounter a return instruction, we extract the
1318 return address register from it.
1320 FIXME: Rewriting GDB to access the procedure descriptors,
1321 e.g. via the minimal symbol table, might obviate this
1323 if (return_reg == -1
1324 && cur_pc < (start_pc + 80)
1325 && (reg == ALPHA_T7_REGNUM
1326 || reg == ALPHA_T9_REGNUM
1327 || reg == ALPHA_RA_REGNUM))
1330 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1331 return_reg = (word >> 16) & 0x1f;
1332 else if (word == 0x47de040f) /* bis sp,sp,fp */
1333 frame_reg = ALPHA_GCC_FP_REGNUM;
1334 else if (word == 0x47fe040f) /* bis zero,sp,fp */
1335 frame_reg = ALPHA_GCC_FP_REGNUM;
1337 alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size);
1340 /* If we haven't found a valid return address register yet, keep
1341 searching in the procedure prologue. */
1342 if (return_reg == -1)
1344 while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80))
1346 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1348 if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1350 reg = (word & 0x03e00000) >> 21;
1351 if (reg == ALPHA_T7_REGNUM
1352 || reg == ALPHA_T9_REGNUM
1353 || reg == ALPHA_RA_REGNUM)
1359 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1361 return_reg = (word >> 16) & 0x1f;
1365 cur_pc += ALPHA_INSN_SIZE;
1370 /* Failing that, do default to the customary RA. */
1371 if (return_reg == -1)
1372 return_reg = ALPHA_RA_REGNUM;
1373 info->return_reg = return_reg;
1375 val = get_frame_register_unsigned (this_frame, frame_reg);
1376 info->vfp = val + frame_size;
1378 /* Convert offsets to absolute addresses. See above about adding
1379 one to the offsets to make all detected offsets non-zero. */
1380 for (reg = 0; reg < ALPHA_NUM_REGS; ++reg)
1381 if (trad_frame_addr_p(info->saved_regs, reg))
1382 info->saved_regs[reg].addr += val - 1;
1384 /* The stack pointer of the previous frame is computed by popping
1385 the current stack frame. */
1386 if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM))
1387 trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp);
1392 /* Given a GDB frame, determine the address of the calling function's
1393 frame. This will be used to create a new GDB frame struct. */
1396 alpha_heuristic_frame_this_id (struct frame_info *this_frame,
1397 void **this_prologue_cache,
1398 struct frame_id *this_id)
1400 struct alpha_heuristic_unwind_cache *info
1401 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1403 *this_id = frame_id_build (info->vfp, info->start_pc);
1406 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
1408 static struct value *
1409 alpha_heuristic_frame_prev_register (struct frame_info *this_frame,
1410 void **this_prologue_cache, int regnum)
1412 struct alpha_heuristic_unwind_cache *info
1413 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1415 /* The PC of the previous frame is stored in the link register of
1416 the current frame. Frob regnum so that we pull the value from
1417 the correct place. */
1418 if (regnum == ALPHA_PC_REGNUM)
1419 regnum = info->return_reg;
1421 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1424 static const struct frame_unwind alpha_heuristic_frame_unwind = {
1426 default_frame_unwind_stop_reason,
1427 alpha_heuristic_frame_this_id,
1428 alpha_heuristic_frame_prev_register,
1430 default_frame_sniffer
1434 alpha_heuristic_frame_base_address (struct frame_info *this_frame,
1435 void **this_prologue_cache)
1437 struct alpha_heuristic_unwind_cache *info
1438 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1443 static const struct frame_base alpha_heuristic_frame_base = {
1444 &alpha_heuristic_frame_unwind,
1445 alpha_heuristic_frame_base_address,
1446 alpha_heuristic_frame_base_address,
1447 alpha_heuristic_frame_base_address
1450 /* Just like reinit_frame_cache, but with the right arguments to be
1451 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
1454 reinit_frame_cache_sfunc (char *args, int from_tty, struct cmd_list_element *c)
1456 reinit_frame_cache ();
1460 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1461 dummy frame. The frame ID's base needs to match the TOS value
1462 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1465 static struct frame_id
1466 alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1469 base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM);
1470 return frame_id_build (base, get_frame_pc (this_frame));
1474 alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1477 pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM);
1482 /* Helper routines for alpha*-nat.c files to move register sets to and
1483 from core files. The UNIQUE pointer is allowed to be NULL, as most
1484 targets don't supply this value in their core files. */
1487 alpha_supply_int_regs (struct regcache *regcache, int regno,
1488 const void *r0_r30, const void *pc, const void *unique)
1490 const gdb_byte *regs = (const gdb_byte *) r0_r30;
1493 for (i = 0; i < 31; ++i)
1494 if (regno == i || regno == -1)
1495 regcache_raw_supply (regcache, i, regs + i * 8);
1497 if (regno == ALPHA_ZERO_REGNUM || regno == -1)
1499 const gdb_byte zero[8] = { 0 };
1501 regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero);
1504 if (regno == ALPHA_PC_REGNUM || regno == -1)
1505 regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc);
1507 if (regno == ALPHA_UNIQUE_REGNUM || regno == -1)
1508 regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique);
1512 alpha_fill_int_regs (const struct regcache *regcache,
1513 int regno, void *r0_r30, void *pc, void *unique)
1515 gdb_byte *regs = (gdb_byte *) r0_r30;
1518 for (i = 0; i < 31; ++i)
1519 if (regno == i || regno == -1)
1520 regcache_raw_collect (regcache, i, regs + i * 8);
1522 if (regno == ALPHA_PC_REGNUM || regno == -1)
1523 regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc);
1525 if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1))
1526 regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique);
1530 alpha_supply_fp_regs (struct regcache *regcache, int regno,
1531 const void *f0_f30, const void *fpcr)
1533 const gdb_byte *regs = (const gdb_byte *) f0_f30;
1536 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1537 if (regno == i || regno == -1)
1538 regcache_raw_supply (regcache, i,
1539 regs + (i - ALPHA_FP0_REGNUM) * 8);
1541 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1542 regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr);
1546 alpha_fill_fp_regs (const struct regcache *regcache,
1547 int regno, void *f0_f30, void *fpcr)
1549 gdb_byte *regs = (gdb_byte *) f0_f30;
1552 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1553 if (regno == i || regno == -1)
1554 regcache_raw_collect (regcache, i,
1555 regs + (i - ALPHA_FP0_REGNUM) * 8);
1557 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1558 regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr);
1563 /* Return nonzero if the G_floating register value in REG is equal to
1564 zero for FP control instructions. */
1567 fp_register_zero_p (LONGEST reg)
1569 /* Check that all bits except the sign bit are zero. */
1570 const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1;
1572 return ((reg & zero_mask) == 0);
1575 /* Return the value of the sign bit for the G_floating register
1576 value held in REG. */
1579 fp_register_sign_bit (LONGEST reg)
1581 const LONGEST sign_mask = (LONGEST) 1 << 63;
1583 return ((reg & sign_mask) != 0);
1586 /* alpha_software_single_step() is called just before we want to resume
1587 the inferior, if we want to single-step it but there is no hardware
1588 or kernel single-step support (NetBSD on Alpha, for example). We find
1589 the target of the coming instruction and breakpoint it. */
1592 alpha_next_pc (struct regcache *regcache, CORE_ADDR pc)
1594 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1601 insn = alpha_read_insn (gdbarch, pc);
1603 /* Opcode is top 6 bits. */
1604 op = (insn >> 26) & 0x3f;
1608 /* Jump format: target PC is:
1610 return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3);
1613 if ((op & 0x30) == 0x30)
1615 /* Branch format: target PC is:
1616 (new PC) + (4 * sext(displacement)) */
1617 if (op == 0x30 /* BR */
1618 || op == 0x34) /* BSR */
1621 offset = (insn & 0x001fffff);
1622 if (offset & 0x00100000)
1623 offset |= 0xffe00000;
1624 offset *= ALPHA_INSN_SIZE;
1625 return (pc + ALPHA_INSN_SIZE + offset);
1628 /* Need to determine if branch is taken; read RA. */
1629 regno = (insn >> 21) & 0x1f;
1632 case 0x31: /* FBEQ */
1633 case 0x36: /* FBGE */
1634 case 0x37: /* FBGT */
1635 case 0x33: /* FBLE */
1636 case 0x32: /* FBLT */
1637 case 0x35: /* FBNE */
1638 regno += gdbarch_fp0_regnum (gdbarch);
1641 rav = regcache_raw_get_signed (regcache, regno);
1645 case 0x38: /* BLBC */
1649 case 0x3c: /* BLBS */
1653 case 0x39: /* BEQ */
1657 case 0x3d: /* BNE */
1661 case 0x3a: /* BLT */
1665 case 0x3b: /* BLE */
1669 case 0x3f: /* BGT */
1673 case 0x3e: /* BGE */
1678 /* Floating point branches. */
1680 case 0x31: /* FBEQ */
1681 if (fp_register_zero_p (rav))
1684 case 0x36: /* FBGE */
1685 if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav))
1688 case 0x37: /* FBGT */
1689 if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav))
1692 case 0x33: /* FBLE */
1693 if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav))
1696 case 0x32: /* FBLT */
1697 if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav))
1700 case 0x35: /* FBNE */
1701 if (! fp_register_zero_p (rav))
1707 /* Not a branch or branch not taken; target PC is:
1709 return (pc + ALPHA_INSN_SIZE);
1712 std::vector<CORE_ADDR>
1713 alpha_software_single_step (struct regcache *regcache)
1715 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1718 pc = alpha_next_pc (regcache, regcache_read_pc (regcache));
1724 /* Initialize the current architecture based on INFO. If possible, re-use an
1725 architecture from ARCHES, which is a list of architectures already created
1726 during this debugging session.
1728 Called e.g. at program startup, when reading a core file, and when reading
1731 static struct gdbarch *
1732 alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1734 struct gdbarch_tdep *tdep;
1735 struct gdbarch *gdbarch;
1737 /* Find a candidate among extant architectures. */
1738 arches = gdbarch_list_lookup_by_info (arches, &info);
1740 return arches->gdbarch;
1742 tdep = XCNEW (struct gdbarch_tdep);
1743 gdbarch = gdbarch_alloc (&info, tdep);
1745 /* Lowest text address. This is used by heuristic_proc_start()
1746 to decide when to stop looking. */
1747 tdep->vm_min_address = (CORE_ADDR) 0x120000000LL;
1749 tdep->dynamic_sigtramp_offset = NULL;
1750 tdep->sigcontext_addr = NULL;
1751 tdep->sc_pc_offset = 2 * 8;
1752 tdep->sc_regs_offset = 4 * 8;
1753 tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8;
1755 tdep->jb_pc = -1; /* longjmp support not enabled by default. */
1757 tdep->return_in_memory = alpha_return_in_memory_always;
1760 set_gdbarch_short_bit (gdbarch, 16);
1761 set_gdbarch_int_bit (gdbarch, 32);
1762 set_gdbarch_long_bit (gdbarch, 64);
1763 set_gdbarch_long_long_bit (gdbarch, 64);
1764 set_gdbarch_wchar_bit (gdbarch, 64);
1765 set_gdbarch_wchar_signed (gdbarch, 0);
1766 set_gdbarch_float_bit (gdbarch, 32);
1767 set_gdbarch_double_bit (gdbarch, 64);
1768 set_gdbarch_long_double_bit (gdbarch, 64);
1769 set_gdbarch_ptr_bit (gdbarch, 64);
1772 set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS);
1773 set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM);
1774 set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM);
1775 set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM);
1777 set_gdbarch_register_name (gdbarch, alpha_register_name);
1778 set_gdbarch_register_type (gdbarch, alpha_register_type);
1780 set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register);
1781 set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register);
1783 set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p);
1784 set_gdbarch_register_to_value (gdbarch, alpha_register_to_value);
1785 set_gdbarch_value_to_register (gdbarch, alpha_value_to_register);
1787 set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p);
1789 /* Prologue heuristics. */
1790 set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue);
1794 set_gdbarch_return_value (gdbarch, alpha_return_value);
1796 /* Settings for calling functions in the inferior. */
1797 set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call);
1799 /* Methods for saving / extracting a dummy frame's ID. */
1800 set_gdbarch_dummy_id (gdbarch, alpha_dummy_id);
1802 /* Return the unwound PC value. */
1803 set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc);
1805 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1806 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
1808 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1809 alpha_breakpoint::kind_from_pc);
1810 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1811 alpha_breakpoint::bp_from_kind);
1812 set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE);
1813 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1815 /* Handles single stepping of atomic sequences. */
1816 set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence);
1818 /* Hook in ABI-specific overrides, if they have been registered. */
1819 gdbarch_init_osabi (info, gdbarch);
1821 /* Now that we have tuned the configuration, set a few final things
1822 based on what the OS ABI has told us. */
1824 if (tdep->jb_pc >= 0)
1825 set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target);
1827 frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind);
1828 frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind);
1830 frame_base_set_default (gdbarch, &alpha_heuristic_frame_base);
1836 alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1838 dwarf2_append_unwinders (gdbarch);
1839 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
1842 extern initialize_file_ftype _initialize_alpha_tdep; /* -Wmissing-prototypes */
1845 _initialize_alpha_tdep (void)
1848 gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL);
1850 /* Let the user set the fence post for heuristic_proc_start. */
1852 /* We really would like to have both "0" and "unlimited" work, but
1853 command.c doesn't deal with that. So make it a var_zinteger
1854 because the user can always use "999999" or some such for unlimited. */
1855 /* We need to throw away the frame cache when we set this, since it
1856 might change our ability to get backtraces. */
1857 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
1858 &heuristic_fence_post, _("\
1859 Set the distance searched for the start of a function."), _("\
1860 Show the distance searched for the start of a function."), _("\
1861 If you are debugging a stripped executable, GDB needs to search through the\n\
1862 program for the start of a function. This command sets the distance of the\n\
1863 search. The only need to set it is when debugging a stripped executable."),
1864 reinit_frame_cache_sfunc,
1865 NULL, /* FIXME: i18n: The distance searched for
1866 the start of a function is \"%d\". */
1867 &setlist, &showlist);