1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
25 #include "dwarf2-frame.h"
36 #include "reggroups.h"
37 #include "arch-utils.h"
41 #include "trad-frame.h"
45 #include "alpha-tdep.h"
48 /* Instruction decoding. The notations for registers, immediates and
49 opcodes are the same as the one used in Compaq's Alpha architecture
52 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
54 /* Memory instruction format */
55 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
56 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
57 #define MEM_DISP(insn) \
58 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
60 static const int lda_opcode = 0x08;
61 static const int stq_opcode = 0x2d;
63 /* Branch instruction format */
64 #define BR_RA(insn) MEM_RA(insn)
66 static const int br_opcode = 0x30;
67 static const int bne_opcode = 0x3d;
69 /* Operate instruction format */
70 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
71 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
72 #define OPR_RA(insn) MEM_RA(insn)
73 #define OPR_RC(insn) ((insn & 0x1f))
74 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
76 static const int subq_opcode = 0x10;
77 static const int subq_function = 0x29;
80 /* Return the name of the REGNO register.
82 An empty name corresponds to a register number that used to
83 be used for a virtual register. That virtual register has
84 been removed, but the index is still reserved to maintain
85 compatibility with existing remote alpha targets. */
88 alpha_register_name (struct gdbarch *gdbarch, int regno)
90 static const char * const register_names[] =
92 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
93 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
94 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
95 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
96 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
97 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
98 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
99 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
105 if (regno >= ARRAY_SIZE(register_names))
107 return register_names[regno];
111 alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
113 return (strlen (alpha_register_name (gdbarch, regno)) == 0);
117 alpha_cannot_store_register (struct gdbarch *gdbarch, int regno)
119 return (regno == ALPHA_ZERO_REGNUM
120 || strlen (alpha_register_name (gdbarch, regno)) == 0);
124 alpha_register_type (struct gdbarch *gdbarch, int regno)
126 if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM)
127 return builtin_type (gdbarch)->builtin_data_ptr;
128 if (regno == ALPHA_PC_REGNUM)
129 return builtin_type (gdbarch)->builtin_func_ptr;
131 /* Don't need to worry about little vs big endian until
132 some jerk tries to port to alpha-unicosmk. */
133 if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31)
134 return builtin_type (gdbarch)->builtin_double;
136 return builtin_type (gdbarch)->builtin_int64;
139 /* Is REGNUM a member of REGGROUP? */
142 alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
143 struct reggroup *group)
145 /* Filter out any registers eliminated, but whose regnum is
146 reserved for backward compatibility, e.g. the vfp. */
147 if (gdbarch_register_name (gdbarch, regnum) == NULL
148 || *gdbarch_register_name (gdbarch, regnum) == '\0')
151 if (group == all_reggroup)
154 /* Zero should not be saved or restored. Technically it is a general
155 register (just as $f31 would be a float if we represented it), but
156 there's no point displaying it during "info regs", so leave it out
157 of all groups except for "all". */
158 if (regnum == ALPHA_ZERO_REGNUM)
161 /* All other registers are saved and restored. */
162 if (group == save_reggroup || group == restore_reggroup)
165 /* All other groups are non-overlapping. */
167 /* Since this is really a PALcode memory slot... */
168 if (regnum == ALPHA_UNIQUE_REGNUM)
169 return group == system_reggroup;
171 /* Force the FPCR to be considered part of the floating point state. */
172 if (regnum == ALPHA_FPCR_REGNUM)
173 return group == float_reggroup;
175 if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31)
176 return group == float_reggroup;
178 return group == general_reggroup;
181 /* The following represents exactly the conversion performed by
182 the LDS instruction. This applies to both single-precision
183 floating point and 32-bit integers. */
186 alpha_lds (struct gdbarch *gdbarch, void *out, const void *in)
188 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order);
191 ULONGEST frac = (mem >> 0) & 0x7fffff;
192 ULONGEST sign = (mem >> 31) & 1;
193 ULONGEST exp_msb = (mem >> 30) & 1;
194 ULONGEST exp_low = (mem >> 23) & 0x7f;
197 exp = (exp_msb << 10) | exp_low;
209 reg = (sign << 63) | (exp << 52) | (frac << 29);
210 store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg);
213 /* Similarly, this represents exactly the conversion performed by
214 the STS instruction. */
217 alpha_sts (struct gdbarch *gdbarch, void *out, const void *in)
219 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
222 reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order);
223 mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff);
224 store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem);
227 /* The alpha needs a conversion between register and memory format if the
228 register is a floating point register and memory format is float, as the
229 register format must be double or memory format is an integer with 4
230 bytes or less, as the representation of integers in floating point
231 registers is different. */
234 alpha_convert_register_p (struct gdbarch *gdbarch, int regno,
237 return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31
238 && TYPE_LENGTH (type) != 8);
242 alpha_register_to_value (struct frame_info *frame, int regnum,
243 struct type *valtype, gdb_byte *out,
244 int *optimizedp, int *unavailablep)
246 struct gdbarch *gdbarch = get_frame_arch (frame);
247 gdb_byte in[MAX_REGISTER_SIZE];
249 /* Convert to TYPE. */
250 if (!get_frame_register_bytes (frame, regnum, 0,
251 register_size (gdbarch, regnum),
252 in, optimizedp, unavailablep))
255 if (TYPE_LENGTH (valtype) == 4)
257 alpha_sts (gdbarch, out, in);
258 *optimizedp = *unavailablep = 0;
262 error (_("Cannot retrieve value from floating point register"));
266 alpha_value_to_register (struct frame_info *frame, int regnum,
267 struct type *valtype, const gdb_byte *in)
269 gdb_byte out[MAX_REGISTER_SIZE];
271 switch (TYPE_LENGTH (valtype))
274 alpha_lds (get_frame_arch (frame), out, in);
277 error (_("Cannot store value in floating point register"));
279 put_frame_register (frame, regnum, out);
283 /* The alpha passes the first six arguments in the registers, the rest on
284 the stack. The register arguments are stored in ARG_REG_BUFFER, and
285 then moved into the register file; this simplifies the passing of a
286 large struct which extends from the registers to the stack, plus avoids
287 three ptrace invocations per word.
289 We don't bother tracking which register values should go in integer
290 regs or fp regs; we load the same values into both.
292 If the called function is returning a structure, the address of the
293 structure to be returned is passed as a hidden first argument. */
296 alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
297 struct regcache *regcache, CORE_ADDR bp_addr,
298 int nargs, struct value **args, CORE_ADDR sp,
299 int struct_return, CORE_ADDR struct_addr)
301 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
303 int accumulate_size = struct_return ? 8 : 0;
306 const gdb_byte *contents;
310 struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs);
311 struct alpha_arg *m_arg;
312 gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS];
313 int required_arg_regs;
314 CORE_ADDR func_addr = find_function_addr (function, NULL);
316 /* The ABI places the address of the called function in T12. */
317 regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr);
319 /* Set the return address register to point to the entry point
320 of the program, where a breakpoint lies in wait. */
321 regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr);
323 /* Lay out the arguments in memory. */
324 for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++)
326 struct value *arg = args[i];
327 struct type *arg_type = check_typedef (value_type (arg));
329 /* Cast argument to long if necessary as the compiler does it too. */
330 switch (TYPE_CODE (arg_type))
335 case TYPE_CODE_RANGE:
337 if (TYPE_LENGTH (arg_type) == 4)
339 /* 32-bit values must be sign-extended to 64 bits
340 even if the base data type is unsigned. */
341 arg_type = builtin_type (gdbarch)->builtin_int32;
342 arg = value_cast (arg_type, arg);
344 if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE)
346 arg_type = builtin_type (gdbarch)->builtin_int64;
347 arg = value_cast (arg_type, arg);
352 /* "float" arguments loaded in registers must be passed in
353 register format, aka "double". */
354 if (accumulate_size < sizeof (arg_reg_buffer)
355 && TYPE_LENGTH (arg_type) == 4)
357 arg_type = builtin_type (gdbarch)->builtin_double;
358 arg = value_cast (arg_type, arg);
360 /* Tru64 5.1 has a 128-bit long double, and passes this by
361 invisible reference. No one else uses this data type. */
362 else if (TYPE_LENGTH (arg_type) == 16)
364 /* Allocate aligned storage. */
365 sp = (sp & -16) - 16;
367 /* Write the real data into the stack. */
368 write_memory (sp, value_contents (arg), 16);
370 /* Construct the indirection. */
371 arg_type = lookup_pointer_type (arg_type);
372 arg = value_from_pointer (arg_type, sp);
376 case TYPE_CODE_COMPLEX:
377 /* ??? The ABI says that complex values are passed as two
378 separate scalar values. This distinction only matters
379 for complex float. However, GCC does not implement this. */
381 /* Tru64 5.1 has a 128-bit long double, and passes this by
382 invisible reference. */
383 if (TYPE_LENGTH (arg_type) == 32)
385 /* Allocate aligned storage. */
386 sp = (sp & -16) - 16;
388 /* Write the real data into the stack. */
389 write_memory (sp, value_contents (arg), 32);
391 /* Construct the indirection. */
392 arg_type = lookup_pointer_type (arg_type);
393 arg = value_from_pointer (arg_type, sp);
400 m_arg->len = TYPE_LENGTH (arg_type);
401 m_arg->offset = accumulate_size;
402 accumulate_size = (accumulate_size + m_arg->len + 7) & ~7;
403 m_arg->contents = value_contents (arg);
406 /* Determine required argument register loads, loading an argument register
407 is expensive as it uses three ptrace calls. */
408 required_arg_regs = accumulate_size / 8;
409 if (required_arg_regs > ALPHA_NUM_ARG_REGS)
410 required_arg_regs = ALPHA_NUM_ARG_REGS;
412 /* Make room for the arguments on the stack. */
413 if (accumulate_size < sizeof(arg_reg_buffer))
416 accumulate_size -= sizeof(arg_reg_buffer);
417 sp -= accumulate_size;
419 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
422 /* `Push' arguments on the stack. */
423 for (i = nargs; m_arg--, --i >= 0;)
425 const gdb_byte *contents = m_arg->contents;
426 int offset = m_arg->offset;
427 int len = m_arg->len;
429 /* Copy the bytes destined for registers into arg_reg_buffer. */
430 if (offset < sizeof(arg_reg_buffer))
432 if (offset + len <= sizeof(arg_reg_buffer))
434 memcpy (arg_reg_buffer + offset, contents, len);
439 int tlen = sizeof(arg_reg_buffer) - offset;
440 memcpy (arg_reg_buffer + offset, contents, tlen);
447 /* Everything else goes to the stack. */
448 write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len);
451 store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE,
452 byte_order, struct_addr);
454 /* Load the argument registers. */
455 for (i = 0; i < required_arg_regs; i++)
457 regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i,
458 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
459 regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i,
460 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
463 /* Finally, update the stack pointer. */
464 regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp);
469 /* Extract from REGCACHE the value about to be returned from a function
470 and copy it into VALBUF. */
473 alpha_extract_return_value (struct type *valtype, struct regcache *regcache,
476 struct gdbarch *gdbarch = get_regcache_arch (regcache);
477 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
478 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
481 switch (TYPE_CODE (valtype))
484 switch (TYPE_LENGTH (valtype))
487 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer);
488 alpha_sts (gdbarch, valbuf, raw_buffer);
492 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
496 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
497 read_memory (l, valbuf, 16);
501 internal_error (__FILE__, __LINE__,
502 _("unknown floating point width"));
506 case TYPE_CODE_COMPLEX:
507 switch (TYPE_LENGTH (valtype))
510 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
511 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
515 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
516 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
520 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
521 read_memory (l, valbuf, 32);
525 internal_error (__FILE__, __LINE__,
526 _("unknown floating point width"));
531 /* Assume everything else degenerates to an integer. */
532 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
533 store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l);
538 /* Insert the given value into REGCACHE as if it was being
539 returned by a function. */
542 alpha_store_return_value (struct type *valtype, struct regcache *regcache,
543 const gdb_byte *valbuf)
545 struct gdbarch *gdbarch = get_regcache_arch (regcache);
546 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
549 switch (TYPE_CODE (valtype))
552 switch (TYPE_LENGTH (valtype))
555 alpha_lds (gdbarch, raw_buffer, valbuf);
556 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer);
560 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
564 /* FIXME: 128-bit long doubles are returned like structures:
565 by writing into indirect storage provided by the caller
566 as the first argument. */
567 error (_("Cannot set a 128-bit long double return value."));
570 internal_error (__FILE__, __LINE__,
571 _("unknown floating point width"));
575 case TYPE_CODE_COMPLEX:
576 switch (TYPE_LENGTH (valtype))
579 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
580 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
584 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
585 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
589 /* FIXME: 128-bit long doubles are returned like structures:
590 by writing into indirect storage provided by the caller
591 as the first argument. */
592 error (_("Cannot set a 128-bit long double return value."));
595 internal_error (__FILE__, __LINE__,
596 _("unknown floating point width"));
601 /* Assume everything else degenerates to an integer. */
602 /* 32-bit values must be sign-extended to 64 bits
603 even if the base data type is unsigned. */
604 if (TYPE_LENGTH (valtype) == 4)
605 valtype = builtin_type (gdbarch)->builtin_int32;
606 l = unpack_long (valtype, valbuf);
607 regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l);
612 static enum return_value_convention
613 alpha_return_value (struct gdbarch *gdbarch, struct value *function,
614 struct type *type, struct regcache *regcache,
615 gdb_byte *readbuf, const gdb_byte *writebuf)
617 enum type_code code = TYPE_CODE (type);
619 if ((code == TYPE_CODE_STRUCT
620 || code == TYPE_CODE_UNION
621 || code == TYPE_CODE_ARRAY)
622 && gdbarch_tdep (gdbarch)->return_in_memory (type))
627 regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr);
628 read_memory (addr, readbuf, TYPE_LENGTH (type));
631 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
635 alpha_extract_return_value (type, regcache, readbuf);
637 alpha_store_return_value (type, regcache, writebuf);
639 return RETURN_VALUE_REGISTER_CONVENTION;
643 alpha_return_in_memory_always (struct type *type)
649 static const gdb_byte break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
651 GDBARCH_BREAKPOINT_MANIPULATION (alpha, break_insn)
654 /* This returns the PC of the first insn after the prologue.
655 If we can't find the prologue, then return 0. */
658 alpha_after_prologue (CORE_ADDR pc)
660 struct symtab_and_line sal;
661 CORE_ADDR func_addr, func_end;
663 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
666 sal = find_pc_line (func_addr, 0);
667 if (sal.end < func_end)
670 /* The line after the prologue is after the end of the function. In this
671 case, tell the caller to find the prologue the hard way. */
675 /* Read an instruction from memory at PC, looking through breakpoints. */
678 alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
680 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
681 gdb_byte buf[ALPHA_INSN_SIZE];
684 res = target_read_memory (pc, buf, sizeof (buf));
686 memory_error (TARGET_XFER_E_IO, pc);
687 return extract_unsigned_integer (buf, sizeof (buf), byte_order);
690 /* To skip prologues, I use this predicate. Returns either PC itself
691 if the code at PC does not look like a function prologue; otherwise
692 returns an address that (if we're lucky) follows the prologue. If
693 LENIENT, then we must skip everything which is involved in setting
694 up the frame (it's OK to skip more, just so long as we don't skip
695 anything which might clobber the registers which are being saved. */
698 alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
702 CORE_ADDR post_prologue_pc;
703 gdb_byte buf[ALPHA_INSN_SIZE];
705 /* Silently return the unaltered pc upon memory errors.
706 This could happen on OSF/1 if decode_line_1 tries to skip the
707 prologue for quickstarted shared library functions when the
708 shared library is not yet mapped in.
709 Reading target memory is slow over serial lines, so we perform
710 this check only if the target has shared libraries (which all
711 Alpha targets do). */
712 if (target_read_memory (pc, buf, sizeof (buf)))
715 /* See if we can determine the end of the prologue via the symbol table.
716 If so, then return either PC, or the PC after the prologue, whichever
719 post_prologue_pc = alpha_after_prologue (pc);
720 if (post_prologue_pc != 0)
721 return std::max (pc, post_prologue_pc);
723 /* Can't determine prologue from the symbol table, need to examine
726 /* Skip the typical prologue instructions. These are the stack adjustment
727 instruction and the instructions that save registers on the stack
728 or in the gcc frame. */
729 for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE)
731 inst = alpha_read_insn (gdbarch, pc + offset);
733 if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
735 if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
737 if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
739 if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
742 if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
743 || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
744 && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */
747 if (inst == 0x47de040f) /* bis sp,sp,fp */
749 if (inst == 0x47fe040f) /* bis zero,sp,fp */
758 static const int ldl_l_opcode = 0x2a;
759 static const int ldq_l_opcode = 0x2b;
760 static const int stl_c_opcode = 0x2e;
761 static const int stq_c_opcode = 0x2f;
763 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L
764 instruction and ending with a STL_C/STQ_C instruction. If such a sequence
765 is found, attempt to step through it. A breakpoint is placed at the end of
769 alpha_deal_with_atomic_sequence (struct frame_info *frame)
771 struct gdbarch *gdbarch = get_frame_arch (frame);
772 struct address_space *aspace = get_frame_address_space (frame);
773 CORE_ADDR pc = get_frame_pc (frame);
774 CORE_ADDR breaks[2] = {-1, -1};
776 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
777 unsigned int insn = alpha_read_insn (gdbarch, loc);
780 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
781 const int atomic_sequence_length = 16; /* Instruction sequence length. */
782 int bc_insn_count = 0; /* Conditional branch instruction count. */
784 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
785 if (INSN_OPCODE (insn) != ldl_l_opcode
786 && INSN_OPCODE (insn) != ldq_l_opcode)
789 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
791 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
793 loc += ALPHA_INSN_SIZE;
794 insn = alpha_read_insn (gdbarch, loc);
796 /* Assume that there is at most one branch in the atomic
797 sequence. If a branch is found, put a breakpoint in
798 its destination address. */
799 if (INSN_OPCODE (insn) >= br_opcode)
801 int immediate = (insn & 0x001fffff) << 2;
803 immediate = (immediate ^ 0x400000) - 0x400000;
805 if (bc_insn_count >= 1)
806 return 0; /* More than one branch found, fallback
807 to the standard single-step code. */
809 breaks[1] = loc + ALPHA_INSN_SIZE + immediate;
815 if (INSN_OPCODE (insn) == stl_c_opcode
816 || INSN_OPCODE (insn) == stq_c_opcode)
820 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
821 if (INSN_OPCODE (insn) != stl_c_opcode
822 && INSN_OPCODE (insn) != stq_c_opcode)
826 loc += ALPHA_INSN_SIZE;
828 /* Insert a breakpoint right after the end of the atomic sequence. */
831 /* Check for duplicated breakpoints. Check also for a breakpoint
832 placed (branch instruction's destination) anywhere in sequence. */
834 && (breaks[1] == breaks[0]
835 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
838 /* Effectively inserts the breakpoints. */
839 for (index = 0; index <= last_breakpoint; index++)
840 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
846 /* Figure out where the longjmp will land.
847 We expect the first arg to be a pointer to the jmp_buf structure from
848 which we extract the PC (JB_PC) that we will land at. The PC is copied
849 into the "pc". This routine returns true on success. */
852 alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
854 struct gdbarch *gdbarch = get_frame_arch (frame);
855 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
856 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
858 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
860 jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM);
862 if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size),
863 raw_buffer, tdep->jb_elt_size))
866 *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order);
871 /* Frame unwinder for signal trampolines. We use alpha tdep bits that
872 describe the location and shape of the sigcontext structure. After
873 that, all registers are in memory, so it's easy. */
874 /* ??? Shouldn't we be able to do this generically, rather than with
875 OSABI data specific to Alpha? */
877 struct alpha_sigtramp_unwind_cache
879 CORE_ADDR sigcontext_addr;
882 static struct alpha_sigtramp_unwind_cache *
883 alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
884 void **this_prologue_cache)
886 struct alpha_sigtramp_unwind_cache *info;
887 struct gdbarch_tdep *tdep;
889 if (*this_prologue_cache)
890 return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache;
892 info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache);
893 *this_prologue_cache = info;
895 tdep = gdbarch_tdep (get_frame_arch (this_frame));
896 info->sigcontext_addr = tdep->sigcontext_addr (this_frame);
901 /* Return the address of REGNUM in a sigtramp frame. Since this is
902 all arithmetic, it doesn't seem worthwhile to cache it. */
905 alpha_sigtramp_register_address (struct gdbarch *gdbarch,
906 CORE_ADDR sigcontext_addr, int regnum)
908 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
910 if (regnum >= 0 && regnum < 32)
911 return sigcontext_addr + tdep->sc_regs_offset + regnum * 8;
912 else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32)
913 return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8;
914 else if (regnum == ALPHA_PC_REGNUM)
915 return sigcontext_addr + tdep->sc_pc_offset;
920 /* Given a GDB frame, determine the address of the calling function's
921 frame. This will be used to create a new GDB frame struct. */
924 alpha_sigtramp_frame_this_id (struct frame_info *this_frame,
925 void **this_prologue_cache,
926 struct frame_id *this_id)
928 struct gdbarch *gdbarch = get_frame_arch (this_frame);
929 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
930 struct alpha_sigtramp_unwind_cache *info
931 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
932 CORE_ADDR stack_addr, code_addr;
934 /* If the OSABI couldn't locate the sigcontext, give up. */
935 if (info->sigcontext_addr == 0)
938 /* If we have dynamic signal trampolines, find their start.
939 If we do not, then we must assume there is a symbol record
940 that can provide the start address. */
941 if (tdep->dynamic_sigtramp_offset)
944 code_addr = get_frame_pc (this_frame);
945 offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr);
952 code_addr = get_frame_func (this_frame);
954 /* The stack address is trivially read from the sigcontext. */
955 stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr,
957 stack_addr = get_frame_memory_unsigned (this_frame, stack_addr,
958 ALPHA_REGISTER_SIZE);
960 *this_id = frame_id_build (stack_addr, code_addr);
963 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
965 static struct value *
966 alpha_sigtramp_frame_prev_register (struct frame_info *this_frame,
967 void **this_prologue_cache, int regnum)
969 struct alpha_sigtramp_unwind_cache *info
970 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
973 if (info->sigcontext_addr != 0)
975 /* All integer and fp registers are stored in memory. */
976 addr = alpha_sigtramp_register_address (get_frame_arch (this_frame),
977 info->sigcontext_addr, regnum);
979 return frame_unwind_got_memory (this_frame, regnum, addr);
982 /* This extra register may actually be in the sigcontext, but our
983 current description of it in alpha_sigtramp_frame_unwind_cache
984 doesn't include it. Too bad. Fall back on whatever's in the
986 return frame_unwind_got_register (this_frame, regnum, regnum);
990 alpha_sigtramp_frame_sniffer (const struct frame_unwind *self,
991 struct frame_info *this_frame,
992 void **this_prologue_cache)
994 struct gdbarch *gdbarch = get_frame_arch (this_frame);
995 CORE_ADDR pc = get_frame_pc (this_frame);
998 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
999 look at tramp-frame.h and other simplier per-architecture
1000 sigtramp unwinders. */
1002 /* We shouldn't even bother to try if the OSABI didn't register a
1003 sigcontext_addr handler or pc_in_sigtramp hander. */
1004 if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL)
1006 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL)
1009 /* Otherwise we should be in a signal frame. */
1010 find_pc_partial_function (pc, &name, NULL, NULL);
1011 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name))
1017 static const struct frame_unwind alpha_sigtramp_frame_unwind = {
1019 default_frame_unwind_stop_reason,
1020 alpha_sigtramp_frame_this_id,
1021 alpha_sigtramp_frame_prev_register,
1023 alpha_sigtramp_frame_sniffer
1028 /* Heuristic_proc_start may hunt through the text section for a long
1029 time across a 2400 baud serial line. Allows the user to limit this
1031 static int heuristic_fence_post = 0;
1033 /* Attempt to locate the start of the function containing PC. We assume that
1034 the previous function ends with an about_to_return insn. Not foolproof by
1035 any means, since gcc is happy to put the epilogue in the middle of a
1036 function. But we're guessing anyway... */
1039 alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
1041 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1042 CORE_ADDR last_non_nop = pc;
1043 CORE_ADDR fence = pc - heuristic_fence_post;
1044 CORE_ADDR orig_pc = pc;
1046 struct inferior *inf;
1051 /* First see if we can find the start of the function from minimal
1052 symbol information. This can succeed with a binary that doesn't
1053 have debug info, but hasn't been stripped. */
1054 func = get_pc_function_start (pc);
1058 if (heuristic_fence_post == -1
1059 || fence < tdep->vm_min_address)
1060 fence = tdep->vm_min_address;
1062 /* Search back for previous return; also stop at a 0, which might be
1063 seen for instance before the start of a code section. Don't include
1064 nops, since this usually indicates padding between functions. */
1065 for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE)
1067 unsigned int insn = alpha_read_insn (gdbarch, pc);
1070 case 0: /* invalid insn */
1071 case 0x6bfa8001: /* ret $31,($26),1 */
1072 return last_non_nop;
1074 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
1075 case 0x47ff041f: /* nop: bis $31,$31,$31 */
1084 inf = current_inferior ();
1086 /* It's not clear to me why we reach this point when stopping quietly,
1087 but with this test, at least we don't print out warnings for every
1088 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
1089 if (inf->control.stop_soon == NO_STOP_QUIETLY)
1091 static int blurb_printed = 0;
1093 if (fence == tdep->vm_min_address)
1094 warning (_("Hit beginning of text section without finding \
1095 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1097 warning (_("Hit heuristic-fence-post without finding \
1098 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1102 printf_filtered (_("\
1103 This warning occurs if you are debugging a function without any symbols\n\
1104 (for example, in a stripped executable). In that case, you may wish to\n\
1105 increase the size of the search with the `set heuristic-fence-post' command.\n\
1107 Otherwise, you told GDB there was a function where there isn't one, or\n\
1108 (more likely) you have encountered a bug in GDB.\n"));
1116 /* Fallback alpha frame unwinder. Uses instruction scanning and knows
1117 something about the traditional layout of alpha stack frames. */
1119 struct alpha_heuristic_unwind_cache
1123 struct trad_frame_saved_reg *saved_regs;
1127 /* If a probing loop sequence starts at PC, simulate it and compute
1128 FRAME_SIZE and PC after its execution. Otherwise, return with PC and
1129 FRAME_SIZE unchanged. */
1132 alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc,
1135 CORE_ADDR cur_pc = *pc;
1136 int cur_frame_size = *frame_size;
1137 int nb_of_iterations, reg_index, reg_probe;
1140 /* The following pattern is recognized as a probing loop:
1142 lda REG_INDEX,NB_OF_ITERATIONS
1143 lda REG_PROBE,<immediate>(sp)
1146 stq zero,<immediate>(REG_PROBE)
1147 subq REG_INDEX,0x1,REG_INDEX
1148 lda REG_PROBE,<immediate>(REG_PROBE)
1149 bne REG_INDEX, LOOP_START
1151 lda sp,<immediate>(REG_PROBE)
1153 If anything different is found, the function returns without
1154 changing PC and FRAME_SIZE. Otherwise, PC will point immediately
1155 after this sequence, and FRAME_SIZE will be updated. */
1157 /* lda REG_INDEX,NB_OF_ITERATIONS */
1159 insn = alpha_read_insn (gdbarch, cur_pc);
1160 if (INSN_OPCODE (insn) != lda_opcode)
1162 reg_index = MEM_RA (insn);
1163 nb_of_iterations = MEM_DISP (insn);
1165 /* lda REG_PROBE,<immediate>(sp) */
1167 cur_pc += ALPHA_INSN_SIZE;
1168 insn = alpha_read_insn (gdbarch, cur_pc);
1169 if (INSN_OPCODE (insn) != lda_opcode
1170 || MEM_RB (insn) != ALPHA_SP_REGNUM)
1172 reg_probe = MEM_RA (insn);
1173 cur_frame_size -= MEM_DISP (insn);
1175 /* stq zero,<immediate>(REG_PROBE) */
1177 cur_pc += ALPHA_INSN_SIZE;
1178 insn = alpha_read_insn (gdbarch, cur_pc);
1179 if (INSN_OPCODE (insn) != stq_opcode
1180 || MEM_RA (insn) != 0x1f
1181 || MEM_RB (insn) != reg_probe)
1184 /* subq REG_INDEX,0x1,REG_INDEX */
1186 cur_pc += ALPHA_INSN_SIZE;
1187 insn = alpha_read_insn (gdbarch, cur_pc);
1188 if (INSN_OPCODE (insn) != subq_opcode
1189 || !OPR_HAS_IMMEDIATE (insn)
1190 || OPR_FUNCTION (insn) != subq_function
1191 || OPR_LIT(insn) != 1
1192 || OPR_RA (insn) != reg_index
1193 || OPR_RC (insn) != reg_index)
1196 /* lda REG_PROBE,<immediate>(REG_PROBE) */
1198 cur_pc += ALPHA_INSN_SIZE;
1199 insn = alpha_read_insn (gdbarch, cur_pc);
1200 if (INSN_OPCODE (insn) != lda_opcode
1201 || MEM_RA (insn) != reg_probe
1202 || MEM_RB (insn) != reg_probe)
1204 cur_frame_size -= MEM_DISP (insn) * nb_of_iterations;
1206 /* bne REG_INDEX, LOOP_START */
1208 cur_pc += ALPHA_INSN_SIZE;
1209 insn = alpha_read_insn (gdbarch, cur_pc);
1210 if (INSN_OPCODE (insn) != bne_opcode
1211 || MEM_RA (insn) != reg_index)
1214 /* lda sp,<immediate>(REG_PROBE) */
1216 cur_pc += ALPHA_INSN_SIZE;
1217 insn = alpha_read_insn (gdbarch, cur_pc);
1218 if (INSN_OPCODE (insn) != lda_opcode
1219 || MEM_RA (insn) != ALPHA_SP_REGNUM
1220 || MEM_RB (insn) != reg_probe)
1222 cur_frame_size -= MEM_DISP (insn);
1225 *frame_size = cur_frame_size;
1228 static struct alpha_heuristic_unwind_cache *
1229 alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame,
1230 void **this_prologue_cache,
1233 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1234 struct alpha_heuristic_unwind_cache *info;
1236 CORE_ADDR limit_pc, cur_pc;
1237 int frame_reg, frame_size, return_reg, reg;
1239 if (*this_prologue_cache)
1240 return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache;
1242 info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache);
1243 *this_prologue_cache = info;
1244 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1246 limit_pc = get_frame_pc (this_frame);
1248 start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc);
1249 info->start_pc = start_pc;
1251 frame_reg = ALPHA_SP_REGNUM;
1255 /* If we've identified a likely place to start, do code scanning. */
1258 /* Limit the forward search to 50 instructions. */
1259 if (start_pc + 200 < limit_pc)
1260 limit_pc = start_pc + 200;
1262 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE)
1264 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1266 if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1270 /* Consider only the first stack allocation instruction
1271 to contain the static size of the frame. */
1272 if (frame_size == 0)
1273 frame_size = (-word) & 0xffff;
1277 /* Exit loop if a positive stack adjustment is found, which
1278 usually means that the stack cleanup code in the function
1279 epilogue is reached. */
1283 else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1285 reg = (word & 0x03e00000) >> 21;
1287 /* Ignore this instruction if we have already encountered
1288 an instruction saving the same register earlier in the
1289 function code. The current instruction does not tell
1290 us where the original value upon function entry is saved.
1291 All it says is that the function we are scanning reused
1292 that register for some computation of its own, and is now
1293 saving its result. */
1294 if (trad_frame_addr_p(info->saved_regs, reg))
1300 /* Do not compute the address where the register was saved yet,
1301 because we don't know yet if the offset will need to be
1302 relative to $sp or $fp (we can not compute the address
1303 relative to $sp if $sp is updated during the execution of
1304 the current subroutine, for instance when doing some alloca).
1305 So just store the offset for the moment, and compute the
1306 address later when we know whether this frame has a frame
1308 /* Hack: temporarily add one, so that the offset is non-zero
1309 and we can tell which registers have save offsets below. */
1310 info->saved_regs[reg].addr = (word & 0xffff) + 1;
1312 /* Starting with OSF/1-3.2C, the system libraries are shipped
1313 without local symbols, but they still contain procedure
1314 descriptors without a symbol reference. GDB is currently
1315 unable to find these procedure descriptors and uses
1316 heuristic_proc_desc instead.
1317 As some low level compiler support routines (__div*, __add*)
1318 use a non-standard return address register, we have to
1319 add some heuristics to determine the return address register,
1320 or stepping over these routines will fail.
1321 Usually the return address register is the first register
1322 saved on the stack, but assembler optimization might
1323 rearrange the register saves.
1324 So we recognize only a few registers (t7, t9, ra) within
1325 the procedure prologue as valid return address registers.
1326 If we encounter a return instruction, we extract the
1327 return address register from it.
1329 FIXME: Rewriting GDB to access the procedure descriptors,
1330 e.g. via the minimal symbol table, might obviate this
1332 if (return_reg == -1
1333 && cur_pc < (start_pc + 80)
1334 && (reg == ALPHA_T7_REGNUM
1335 || reg == ALPHA_T9_REGNUM
1336 || reg == ALPHA_RA_REGNUM))
1339 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1340 return_reg = (word >> 16) & 0x1f;
1341 else if (word == 0x47de040f) /* bis sp,sp,fp */
1342 frame_reg = ALPHA_GCC_FP_REGNUM;
1343 else if (word == 0x47fe040f) /* bis zero,sp,fp */
1344 frame_reg = ALPHA_GCC_FP_REGNUM;
1346 alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size);
1349 /* If we haven't found a valid return address register yet, keep
1350 searching in the procedure prologue. */
1351 if (return_reg == -1)
1353 while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80))
1355 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1357 if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1359 reg = (word & 0x03e00000) >> 21;
1360 if (reg == ALPHA_T7_REGNUM
1361 || reg == ALPHA_T9_REGNUM
1362 || reg == ALPHA_RA_REGNUM)
1368 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1370 return_reg = (word >> 16) & 0x1f;
1374 cur_pc += ALPHA_INSN_SIZE;
1379 /* Failing that, do default to the customary RA. */
1380 if (return_reg == -1)
1381 return_reg = ALPHA_RA_REGNUM;
1382 info->return_reg = return_reg;
1384 val = get_frame_register_unsigned (this_frame, frame_reg);
1385 info->vfp = val + frame_size;
1387 /* Convert offsets to absolute addresses. See above about adding
1388 one to the offsets to make all detected offsets non-zero. */
1389 for (reg = 0; reg < ALPHA_NUM_REGS; ++reg)
1390 if (trad_frame_addr_p(info->saved_regs, reg))
1391 info->saved_regs[reg].addr += val - 1;
1393 /* The stack pointer of the previous frame is computed by popping
1394 the current stack frame. */
1395 if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM))
1396 trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp);
1401 /* Given a GDB frame, determine the address of the calling function's
1402 frame. This will be used to create a new GDB frame struct. */
1405 alpha_heuristic_frame_this_id (struct frame_info *this_frame,
1406 void **this_prologue_cache,
1407 struct frame_id *this_id)
1409 struct alpha_heuristic_unwind_cache *info
1410 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1412 *this_id = frame_id_build (info->vfp, info->start_pc);
1415 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
1417 static struct value *
1418 alpha_heuristic_frame_prev_register (struct frame_info *this_frame,
1419 void **this_prologue_cache, int regnum)
1421 struct alpha_heuristic_unwind_cache *info
1422 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1424 /* The PC of the previous frame is stored in the link register of
1425 the current frame. Frob regnum so that we pull the value from
1426 the correct place. */
1427 if (regnum == ALPHA_PC_REGNUM)
1428 regnum = info->return_reg;
1430 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1433 static const struct frame_unwind alpha_heuristic_frame_unwind = {
1435 default_frame_unwind_stop_reason,
1436 alpha_heuristic_frame_this_id,
1437 alpha_heuristic_frame_prev_register,
1439 default_frame_sniffer
1443 alpha_heuristic_frame_base_address (struct frame_info *this_frame,
1444 void **this_prologue_cache)
1446 struct alpha_heuristic_unwind_cache *info
1447 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1452 static const struct frame_base alpha_heuristic_frame_base = {
1453 &alpha_heuristic_frame_unwind,
1454 alpha_heuristic_frame_base_address,
1455 alpha_heuristic_frame_base_address,
1456 alpha_heuristic_frame_base_address
1459 /* Just like reinit_frame_cache, but with the right arguments to be
1460 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
1463 reinit_frame_cache_sfunc (char *args, int from_tty, struct cmd_list_element *c)
1465 reinit_frame_cache ();
1469 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1470 dummy frame. The frame ID's base needs to match the TOS value
1471 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1474 static struct frame_id
1475 alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1478 base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM);
1479 return frame_id_build (base, get_frame_pc (this_frame));
1483 alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1486 pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM);
1491 /* Helper routines for alpha*-nat.c files to move register sets to and
1492 from core files. The UNIQUE pointer is allowed to be NULL, as most
1493 targets don't supply this value in their core files. */
1496 alpha_supply_int_regs (struct regcache *regcache, int regno,
1497 const void *r0_r30, const void *pc, const void *unique)
1499 const gdb_byte *regs = (const gdb_byte *) r0_r30;
1502 for (i = 0; i < 31; ++i)
1503 if (regno == i || regno == -1)
1504 regcache_raw_supply (regcache, i, regs + i * 8);
1506 if (regno == ALPHA_ZERO_REGNUM || regno == -1)
1508 const gdb_byte zero[8] = { 0 };
1510 regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero);
1513 if (regno == ALPHA_PC_REGNUM || regno == -1)
1514 regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc);
1516 if (regno == ALPHA_UNIQUE_REGNUM || regno == -1)
1517 regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique);
1521 alpha_fill_int_regs (const struct regcache *regcache,
1522 int regno, void *r0_r30, void *pc, void *unique)
1524 gdb_byte *regs = (gdb_byte *) r0_r30;
1527 for (i = 0; i < 31; ++i)
1528 if (regno == i || regno == -1)
1529 regcache_raw_collect (regcache, i, regs + i * 8);
1531 if (regno == ALPHA_PC_REGNUM || regno == -1)
1532 regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc);
1534 if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1))
1535 regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique);
1539 alpha_supply_fp_regs (struct regcache *regcache, int regno,
1540 const void *f0_f30, const void *fpcr)
1542 const gdb_byte *regs = (const gdb_byte *) f0_f30;
1545 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1546 if (regno == i || regno == -1)
1547 regcache_raw_supply (regcache, i,
1548 regs + (i - ALPHA_FP0_REGNUM) * 8);
1550 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1551 regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr);
1555 alpha_fill_fp_regs (const struct regcache *regcache,
1556 int regno, void *f0_f30, void *fpcr)
1558 gdb_byte *regs = (gdb_byte *) f0_f30;
1561 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1562 if (regno == i || regno == -1)
1563 regcache_raw_collect (regcache, i,
1564 regs + (i - ALPHA_FP0_REGNUM) * 8);
1566 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1567 regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr);
1572 /* Return nonzero if the G_floating register value in REG is equal to
1573 zero for FP control instructions. */
1576 fp_register_zero_p (LONGEST reg)
1578 /* Check that all bits except the sign bit are zero. */
1579 const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1;
1581 return ((reg & zero_mask) == 0);
1584 /* Return the value of the sign bit for the G_floating register
1585 value held in REG. */
1588 fp_register_sign_bit (LONGEST reg)
1590 const LONGEST sign_mask = (LONGEST) 1 << 63;
1592 return ((reg & sign_mask) != 0);
1595 /* alpha_software_single_step() is called just before we want to resume
1596 the inferior, if we want to single-step it but there is no hardware
1597 or kernel single-step support (NetBSD on Alpha, for example). We find
1598 the target of the coming instruction and breakpoint it. */
1601 alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
1603 struct gdbarch *gdbarch = get_frame_arch (frame);
1610 insn = alpha_read_insn (gdbarch, pc);
1612 /* Opcode is top 6 bits. */
1613 op = (insn >> 26) & 0x3f;
1617 /* Jump format: target PC is:
1619 return (get_frame_register_unsigned (frame, (insn >> 16) & 0x1f) & ~3);
1622 if ((op & 0x30) == 0x30)
1624 /* Branch format: target PC is:
1625 (new PC) + (4 * sext(displacement)) */
1626 if (op == 0x30 /* BR */
1627 || op == 0x34) /* BSR */
1630 offset = (insn & 0x001fffff);
1631 if (offset & 0x00100000)
1632 offset |= 0xffe00000;
1633 offset *= ALPHA_INSN_SIZE;
1634 return (pc + ALPHA_INSN_SIZE + offset);
1637 /* Need to determine if branch is taken; read RA. */
1638 regno = (insn >> 21) & 0x1f;
1641 case 0x31: /* FBEQ */
1642 case 0x36: /* FBGE */
1643 case 0x37: /* FBGT */
1644 case 0x33: /* FBLE */
1645 case 0x32: /* FBLT */
1646 case 0x35: /* FBNE */
1647 regno += gdbarch_fp0_regnum (gdbarch);
1650 rav = get_frame_register_signed (frame, regno);
1654 case 0x38: /* BLBC */
1658 case 0x3c: /* BLBS */
1662 case 0x39: /* BEQ */
1666 case 0x3d: /* BNE */
1670 case 0x3a: /* BLT */
1674 case 0x3b: /* BLE */
1678 case 0x3f: /* BGT */
1682 case 0x3e: /* BGE */
1687 /* Floating point branches. */
1689 case 0x31: /* FBEQ */
1690 if (fp_register_zero_p (rav))
1693 case 0x36: /* FBGE */
1694 if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav))
1697 case 0x37: /* FBGT */
1698 if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav))
1701 case 0x33: /* FBLE */
1702 if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav))
1705 case 0x32: /* FBLT */
1706 if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav))
1709 case 0x35: /* FBNE */
1710 if (! fp_register_zero_p (rav))
1716 /* Not a branch or branch not taken; target PC is:
1718 return (pc + ALPHA_INSN_SIZE);
1722 alpha_software_single_step (struct frame_info *frame)
1724 struct gdbarch *gdbarch = get_frame_arch (frame);
1725 struct address_space *aspace = get_frame_address_space (frame);
1726 CORE_ADDR pc, next_pc;
1728 pc = get_frame_pc (frame);
1729 next_pc = alpha_next_pc (frame, pc);
1731 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
1736 /* Initialize the current architecture based on INFO. If possible, re-use an
1737 architecture from ARCHES, which is a list of architectures already created
1738 during this debugging session.
1740 Called e.g. at program startup, when reading a core file, and when reading
1743 static struct gdbarch *
1744 alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1746 struct gdbarch_tdep *tdep;
1747 struct gdbarch *gdbarch;
1749 /* Find a candidate among extant architectures. */
1750 arches = gdbarch_list_lookup_by_info (arches, &info);
1752 return arches->gdbarch;
1754 tdep = XNEW (struct gdbarch_tdep);
1755 gdbarch = gdbarch_alloc (&info, tdep);
1757 /* Lowest text address. This is used by heuristic_proc_start()
1758 to decide when to stop looking. */
1759 tdep->vm_min_address = (CORE_ADDR) 0x120000000LL;
1761 tdep->dynamic_sigtramp_offset = NULL;
1762 tdep->sigcontext_addr = NULL;
1763 tdep->sc_pc_offset = 2 * 8;
1764 tdep->sc_regs_offset = 4 * 8;
1765 tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8;
1767 tdep->jb_pc = -1; /* longjmp support not enabled by default. */
1769 tdep->return_in_memory = alpha_return_in_memory_always;
1772 set_gdbarch_short_bit (gdbarch, 16);
1773 set_gdbarch_int_bit (gdbarch, 32);
1774 set_gdbarch_long_bit (gdbarch, 64);
1775 set_gdbarch_long_long_bit (gdbarch, 64);
1776 set_gdbarch_float_bit (gdbarch, 32);
1777 set_gdbarch_double_bit (gdbarch, 64);
1778 set_gdbarch_long_double_bit (gdbarch, 64);
1779 set_gdbarch_ptr_bit (gdbarch, 64);
1782 set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS);
1783 set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM);
1784 set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM);
1785 set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM);
1787 set_gdbarch_register_name (gdbarch, alpha_register_name);
1788 set_gdbarch_register_type (gdbarch, alpha_register_type);
1790 set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register);
1791 set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register);
1793 set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p);
1794 set_gdbarch_register_to_value (gdbarch, alpha_register_to_value);
1795 set_gdbarch_value_to_register (gdbarch, alpha_value_to_register);
1797 set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p);
1799 /* Prologue heuristics. */
1800 set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue);
1803 set_gdbarch_print_insn (gdbarch, print_insn_alpha);
1807 set_gdbarch_return_value (gdbarch, alpha_return_value);
1809 /* Settings for calling functions in the inferior. */
1810 set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call);
1812 /* Methods for saving / extracting a dummy frame's ID. */
1813 set_gdbarch_dummy_id (gdbarch, alpha_dummy_id);
1815 /* Return the unwound PC value. */
1816 set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc);
1818 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1819 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
1821 SET_GDBARCH_BREAKPOINT_MANIPULATION (alpha);
1822 set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE);
1823 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1825 /* Handles single stepping of atomic sequences. */
1826 set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence);
1828 /* Hook in ABI-specific overrides, if they have been registered. */
1829 gdbarch_init_osabi (info, gdbarch);
1831 /* Now that we have tuned the configuration, set a few final things
1832 based on what the OS ABI has told us. */
1834 if (tdep->jb_pc >= 0)
1835 set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target);
1837 frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind);
1838 frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind);
1840 frame_base_set_default (gdbarch, &alpha_heuristic_frame_base);
1846 alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1848 dwarf2_append_unwinders (gdbarch);
1849 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
1852 extern initialize_file_ftype _initialize_alpha_tdep; /* -Wmissing-prototypes */
1855 _initialize_alpha_tdep (void)
1858 gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL);
1860 /* Let the user set the fence post for heuristic_proc_start. */
1862 /* We really would like to have both "0" and "unlimited" work, but
1863 command.c doesn't deal with that. So make it a var_zinteger
1864 because the user can always use "999999" or some such for unlimited. */
1865 /* We need to throw away the frame cache when we set this, since it
1866 might change our ability to get backtraces. */
1867 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
1868 &heuristic_fence_post, _("\
1869 Set the distance searched for the start of a function."), _("\
1870 Show the distance searched for the start of a function."), _("\
1871 If you are debugging a stripped executable, GDB needs to search through the\n\
1872 program for the start of a function. This command sets the distance of the\n\
1873 search. The only need to set it is when debugging a stripped executable."),
1874 reinit_frame_cache_sfunc,
1875 NULL, /* FIXME: i18n: The distance searched for
1876 the start of a function is \"%d\". */
1877 &setlist, &showlist);