1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1993-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "frame-unwind.h"
23 #include "frame-base.h"
24 #include "dwarf2-frame.h"
35 #include "reggroups.h"
36 #include "arch-utils.h"
40 #include "trad-frame.h"
44 #include "alpha-tdep.h"
47 /* Instruction decoding. The notations for registers, immediates and
48 opcodes are the same as the one used in Compaq's Alpha architecture
51 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
53 /* Memory instruction format */
54 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
55 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
56 #define MEM_DISP(insn) \
57 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
59 static const int lda_opcode = 0x08;
60 static const int stq_opcode = 0x2d;
62 /* Branch instruction format */
63 #define BR_RA(insn) MEM_RA(insn)
65 static const int br_opcode = 0x30;
66 static const int bne_opcode = 0x3d;
68 /* Operate instruction format */
69 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
70 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
71 #define OPR_RA(insn) MEM_RA(insn)
72 #define OPR_RC(insn) ((insn & 0x1f))
73 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
75 static const int subq_opcode = 0x10;
76 static const int subq_function = 0x29;
79 /* Return the name of the REGNO register.
81 An empty name corresponds to a register number that used to
82 be used for a virtual register. That virtual register has
83 been removed, but the index is still reserved to maintain
84 compatibility with existing remote alpha targets. */
87 alpha_register_name (struct gdbarch *gdbarch, int regno)
89 static const char * const register_names[] =
91 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
92 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
93 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
94 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
95 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
96 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
97 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
98 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
104 if (regno >= ARRAY_SIZE(register_names))
106 return register_names[regno];
110 alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
112 return (strlen (alpha_register_name (gdbarch, regno)) == 0);
116 alpha_cannot_store_register (struct gdbarch *gdbarch, int regno)
118 return (regno == ALPHA_ZERO_REGNUM
119 || strlen (alpha_register_name (gdbarch, regno)) == 0);
123 alpha_register_type (struct gdbarch *gdbarch, int regno)
125 if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM)
126 return builtin_type (gdbarch)->builtin_data_ptr;
127 if (regno == ALPHA_PC_REGNUM)
128 return builtin_type (gdbarch)->builtin_func_ptr;
130 /* Don't need to worry about little vs big endian until
131 some jerk tries to port to alpha-unicosmk. */
132 if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31)
133 return builtin_type (gdbarch)->builtin_double;
135 return builtin_type (gdbarch)->builtin_int64;
138 /* Is REGNUM a member of REGGROUP? */
141 alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
142 struct reggroup *group)
144 /* Filter out any registers eliminated, but whose regnum is
145 reserved for backward compatibility, e.g. the vfp. */
146 if (gdbarch_register_name (gdbarch, regnum) == NULL
147 || *gdbarch_register_name (gdbarch, regnum) == '\0')
150 if (group == all_reggroup)
153 /* Zero should not be saved or restored. Technically it is a general
154 register (just as $f31 would be a float if we represented it), but
155 there's no point displaying it during "info regs", so leave it out
156 of all groups except for "all". */
157 if (regnum == ALPHA_ZERO_REGNUM)
160 /* All other registers are saved and restored. */
161 if (group == save_reggroup || group == restore_reggroup)
164 /* All other groups are non-overlapping. */
166 /* Since this is really a PALcode memory slot... */
167 if (regnum == ALPHA_UNIQUE_REGNUM)
168 return group == system_reggroup;
170 /* Force the FPCR to be considered part of the floating point state. */
171 if (regnum == ALPHA_FPCR_REGNUM)
172 return group == float_reggroup;
174 if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31)
175 return group == float_reggroup;
177 return group == general_reggroup;
180 /* The following represents exactly the conversion performed by
181 the LDS instruction. This applies to both single-precision
182 floating point and 32-bit integers. */
185 alpha_lds (struct gdbarch *gdbarch, void *out, const void *in)
187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
189 = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order);
190 ULONGEST frac = (mem >> 0) & 0x7fffff;
191 ULONGEST sign = (mem >> 31) & 1;
192 ULONGEST exp_msb = (mem >> 30) & 1;
193 ULONGEST exp_low = (mem >> 23) & 0x7f;
196 exp = (exp_msb << 10) | exp_low;
208 reg = (sign << 63) | (exp << 52) | (frac << 29);
209 store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg);
212 /* Similarly, this represents exactly the conversion performed by
213 the STS instruction. */
216 alpha_sts (struct gdbarch *gdbarch, void *out, const void *in)
218 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
221 reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order);
222 mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff);
223 store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem);
226 /* The alpha needs a conversion between register and memory format if the
227 register is a floating point register and memory format is float, as the
228 register format must be double or memory format is an integer with 4
229 bytes, as the representation of integers in floating point
230 registers is different. */
233 alpha_convert_register_p (struct gdbarch *gdbarch, int regno,
236 return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31
237 && TYPE_LENGTH (type) == 4);
241 alpha_register_to_value (struct frame_info *frame, int regnum,
242 struct type *valtype, gdb_byte *out,
243 int *optimizedp, int *unavailablep)
245 struct gdbarch *gdbarch = get_frame_arch (frame);
246 struct value *value = get_frame_register_value (frame, regnum);
248 gdb_assert (value != NULL);
249 *optimizedp = value_optimized_out (value);
250 *unavailablep = !value_entirely_available (value);
252 if (*optimizedp || *unavailablep)
254 release_value (value);
258 /* Convert to VALTYPE. */
260 gdb_assert (TYPE_LENGTH (valtype) == 4);
261 alpha_sts (gdbarch, out, value_contents_all (value));
263 release_value (value);
268 alpha_value_to_register (struct frame_info *frame, int regnum,
269 struct type *valtype, const gdb_byte *in)
271 gdb_byte out[ALPHA_REGISTER_SIZE];
273 gdb_assert (TYPE_LENGTH (valtype) == 4);
274 gdb_assert (register_size (get_frame_arch (frame), regnum)
275 <= ALPHA_REGISTER_SIZE);
276 alpha_lds (get_frame_arch (frame), out, in);
278 put_frame_register (frame, regnum, out);
282 /* The alpha passes the first six arguments in the registers, the rest on
283 the stack. The register arguments are stored in ARG_REG_BUFFER, and
284 then moved into the register file; this simplifies the passing of a
285 large struct which extends from the registers to the stack, plus avoids
286 three ptrace invocations per word.
288 We don't bother tracking which register values should go in integer
289 regs or fp regs; we load the same values into both.
291 If the called function is returning a structure, the address of the
292 structure to be returned is passed as a hidden first argument. */
295 alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
296 struct regcache *regcache, CORE_ADDR bp_addr,
297 int nargs, struct value **args, CORE_ADDR sp,
298 int struct_return, CORE_ADDR struct_addr)
300 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
302 int accumulate_size = struct_return ? 8 : 0;
305 const gdb_byte *contents;
309 struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs);
310 struct alpha_arg *m_arg;
311 gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS];
312 int required_arg_regs;
313 CORE_ADDR func_addr = find_function_addr (function, NULL);
315 /* The ABI places the address of the called function in T12. */
316 regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr);
318 /* Set the return address register to point to the entry point
319 of the program, where a breakpoint lies in wait. */
320 regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr);
322 /* Lay out the arguments in memory. */
323 for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++)
325 struct value *arg = args[i];
326 struct type *arg_type = check_typedef (value_type (arg));
328 /* Cast argument to long if necessary as the compiler does it too. */
329 switch (TYPE_CODE (arg_type))
334 case TYPE_CODE_RANGE:
336 if (TYPE_LENGTH (arg_type) == 4)
338 /* 32-bit values must be sign-extended to 64 bits
339 even if the base data type is unsigned. */
340 arg_type = builtin_type (gdbarch)->builtin_int32;
341 arg = value_cast (arg_type, arg);
343 if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE)
345 arg_type = builtin_type (gdbarch)->builtin_int64;
346 arg = value_cast (arg_type, arg);
351 /* "float" arguments loaded in registers must be passed in
352 register format, aka "double". */
353 if (accumulate_size < sizeof (arg_reg_buffer)
354 && TYPE_LENGTH (arg_type) == 4)
356 arg_type = builtin_type (gdbarch)->builtin_double;
357 arg = value_cast (arg_type, arg);
359 /* Tru64 5.1 has a 128-bit long double, and passes this by
360 invisible reference. No one else uses this data type. */
361 else if (TYPE_LENGTH (arg_type) == 16)
363 /* Allocate aligned storage. */
364 sp = (sp & -16) - 16;
366 /* Write the real data into the stack. */
367 write_memory (sp, value_contents (arg), 16);
369 /* Construct the indirection. */
370 arg_type = lookup_pointer_type (arg_type);
371 arg = value_from_pointer (arg_type, sp);
375 case TYPE_CODE_COMPLEX:
376 /* ??? The ABI says that complex values are passed as two
377 separate scalar values. This distinction only matters
378 for complex float. However, GCC does not implement this. */
380 /* Tru64 5.1 has a 128-bit long double, and passes this by
381 invisible reference. */
382 if (TYPE_LENGTH (arg_type) == 32)
384 /* Allocate aligned storage. */
385 sp = (sp & -16) - 16;
387 /* Write the real data into the stack. */
388 write_memory (sp, value_contents (arg), 32);
390 /* Construct the indirection. */
391 arg_type = lookup_pointer_type (arg_type);
392 arg = value_from_pointer (arg_type, sp);
399 m_arg->len = TYPE_LENGTH (arg_type);
400 m_arg->offset = accumulate_size;
401 accumulate_size = (accumulate_size + m_arg->len + 7) & ~7;
402 m_arg->contents = value_contents (arg);
405 /* Determine required argument register loads, loading an argument register
406 is expensive as it uses three ptrace calls. */
407 required_arg_regs = accumulate_size / 8;
408 if (required_arg_regs > ALPHA_NUM_ARG_REGS)
409 required_arg_regs = ALPHA_NUM_ARG_REGS;
411 /* Make room for the arguments on the stack. */
412 if (accumulate_size < sizeof(arg_reg_buffer))
415 accumulate_size -= sizeof(arg_reg_buffer);
416 sp -= accumulate_size;
418 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
421 /* `Push' arguments on the stack. */
422 for (i = nargs; m_arg--, --i >= 0;)
424 const gdb_byte *contents = m_arg->contents;
425 int offset = m_arg->offset;
426 int len = m_arg->len;
428 /* Copy the bytes destined for registers into arg_reg_buffer. */
429 if (offset < sizeof(arg_reg_buffer))
431 if (offset + len <= sizeof(arg_reg_buffer))
433 memcpy (arg_reg_buffer + offset, contents, len);
438 int tlen = sizeof(arg_reg_buffer) - offset;
439 memcpy (arg_reg_buffer + offset, contents, tlen);
446 /* Everything else goes to the stack. */
447 write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len);
450 store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE,
451 byte_order, struct_addr);
453 /* Load the argument registers. */
454 for (i = 0; i < required_arg_regs; i++)
456 regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i,
457 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
458 regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i,
459 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
462 /* Finally, update the stack pointer. */
463 regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp);
468 /* Extract from REGCACHE the value about to be returned from a function
469 and copy it into VALBUF. */
472 alpha_extract_return_value (struct type *valtype, struct regcache *regcache,
475 struct gdbarch *gdbarch = regcache->arch ();
476 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
477 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
480 switch (TYPE_CODE (valtype))
483 switch (TYPE_LENGTH (valtype))
486 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer);
487 alpha_sts (gdbarch, valbuf, raw_buffer);
491 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
495 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
496 read_memory (l, valbuf, 16);
500 internal_error (__FILE__, __LINE__,
501 _("unknown floating point width"));
505 case TYPE_CODE_COMPLEX:
506 switch (TYPE_LENGTH (valtype))
509 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
510 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
514 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
515 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
519 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
520 read_memory (l, valbuf, 32);
524 internal_error (__FILE__, __LINE__,
525 _("unknown floating point width"));
530 /* Assume everything else degenerates to an integer. */
531 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
532 store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l);
537 /* Insert the given value into REGCACHE as if it was being
538 returned by a function. */
541 alpha_store_return_value (struct type *valtype, struct regcache *regcache,
542 const gdb_byte *valbuf)
544 struct gdbarch *gdbarch = regcache->arch ();
545 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
548 switch (TYPE_CODE (valtype))
551 switch (TYPE_LENGTH (valtype))
554 alpha_lds (gdbarch, raw_buffer, valbuf);
555 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer);
559 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
563 /* FIXME: 128-bit long doubles are returned like structures:
564 by writing into indirect storage provided by the caller
565 as the first argument. */
566 error (_("Cannot set a 128-bit long double return value."));
569 internal_error (__FILE__, __LINE__,
570 _("unknown floating point width"));
574 case TYPE_CODE_COMPLEX:
575 switch (TYPE_LENGTH (valtype))
578 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
579 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
583 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
584 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
588 /* FIXME: 128-bit long doubles are returned like structures:
589 by writing into indirect storage provided by the caller
590 as the first argument. */
591 error (_("Cannot set a 128-bit long double return value."));
594 internal_error (__FILE__, __LINE__,
595 _("unknown floating point width"));
600 /* Assume everything else degenerates to an integer. */
601 /* 32-bit values must be sign-extended to 64 bits
602 even if the base data type is unsigned. */
603 if (TYPE_LENGTH (valtype) == 4)
604 valtype = builtin_type (gdbarch)->builtin_int32;
605 l = unpack_long (valtype, valbuf);
606 regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l);
611 static enum return_value_convention
612 alpha_return_value (struct gdbarch *gdbarch, struct value *function,
613 struct type *type, struct regcache *regcache,
614 gdb_byte *readbuf, const gdb_byte *writebuf)
616 enum type_code code = TYPE_CODE (type);
618 if ((code == TYPE_CODE_STRUCT
619 || code == TYPE_CODE_UNION
620 || code == TYPE_CODE_ARRAY)
621 && gdbarch_tdep (gdbarch)->return_in_memory (type))
626 regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr);
627 read_memory (addr, readbuf, TYPE_LENGTH (type));
630 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
634 alpha_extract_return_value (type, regcache, readbuf);
636 alpha_store_return_value (type, regcache, writebuf);
638 return RETURN_VALUE_REGISTER_CONVENTION;
642 alpha_return_in_memory_always (struct type *type)
648 constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
650 typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint;
653 /* This returns the PC of the first insn after the prologue.
654 If we can't find the prologue, then return 0. */
657 alpha_after_prologue (CORE_ADDR pc)
659 struct symtab_and_line sal;
660 CORE_ADDR func_addr, func_end;
662 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
665 sal = find_pc_line (func_addr, 0);
666 if (sal.end < func_end)
669 /* The line after the prologue is after the end of the function. In this
670 case, tell the caller to find the prologue the hard way. */
674 /* Read an instruction from memory at PC, looking through breakpoints. */
677 alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
679 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
680 gdb_byte buf[ALPHA_INSN_SIZE];
683 res = target_read_memory (pc, buf, sizeof (buf));
685 memory_error (TARGET_XFER_E_IO, pc);
686 return extract_unsigned_integer (buf, sizeof (buf), byte_order);
689 /* To skip prologues, I use this predicate. Returns either PC itself
690 if the code at PC does not look like a function prologue; otherwise
691 returns an address that (if we're lucky) follows the prologue. If
692 LENIENT, then we must skip everything which is involved in setting
693 up the frame (it's OK to skip more, just so long as we don't skip
694 anything which might clobber the registers which are being saved. */
697 alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
701 CORE_ADDR post_prologue_pc;
702 gdb_byte buf[ALPHA_INSN_SIZE];
704 /* Silently return the unaltered pc upon memory errors.
705 This could happen on OSF/1 if decode_line_1 tries to skip the
706 prologue for quickstarted shared library functions when the
707 shared library is not yet mapped in.
708 Reading target memory is slow over serial lines, so we perform
709 this check only if the target has shared libraries (which all
710 Alpha targets do). */
711 if (target_read_memory (pc, buf, sizeof (buf)))
714 /* See if we can determine the end of the prologue via the symbol table.
715 If so, then return either PC, or the PC after the prologue, whichever
718 post_prologue_pc = alpha_after_prologue (pc);
719 if (post_prologue_pc != 0)
720 return std::max (pc, post_prologue_pc);
722 /* Can't determine prologue from the symbol table, need to examine
725 /* Skip the typical prologue instructions. These are the stack adjustment
726 instruction and the instructions that save registers on the stack
727 or in the gcc frame. */
728 for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE)
730 inst = alpha_read_insn (gdbarch, pc + offset);
732 if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
734 if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
736 if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
738 if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
741 if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
742 || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
743 && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */
746 if (inst == 0x47de040f) /* bis sp,sp,fp */
748 if (inst == 0x47fe040f) /* bis zero,sp,fp */
757 static const int ldl_l_opcode = 0x2a;
758 static const int ldq_l_opcode = 0x2b;
759 static const int stl_c_opcode = 0x2e;
760 static const int stq_c_opcode = 0x2f;
762 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L
763 instruction and ending with a STL_C/STQ_C instruction. If such a sequence
764 is found, attempt to step through it. A breakpoint is placed at the end of
767 static std::vector<CORE_ADDR>
768 alpha_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
770 CORE_ADDR breaks[2] = {-1, -1};
772 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
773 unsigned int insn = alpha_read_insn (gdbarch, loc);
776 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
777 const int atomic_sequence_length = 16; /* Instruction sequence length. */
778 int bc_insn_count = 0; /* Conditional branch instruction count. */
780 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
781 if (INSN_OPCODE (insn) != ldl_l_opcode
782 && INSN_OPCODE (insn) != ldq_l_opcode)
785 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
787 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
789 loc += ALPHA_INSN_SIZE;
790 insn = alpha_read_insn (gdbarch, loc);
792 /* Assume that there is at most one branch in the atomic
793 sequence. If a branch is found, put a breakpoint in
794 its destination address. */
795 if (INSN_OPCODE (insn) >= br_opcode)
797 int immediate = (insn & 0x001fffff) << 2;
799 immediate = (immediate ^ 0x400000) - 0x400000;
801 if (bc_insn_count >= 1)
802 return {}; /* More than one branch found, fallback
803 to the standard single-step code. */
805 breaks[1] = loc + ALPHA_INSN_SIZE + immediate;
811 if (INSN_OPCODE (insn) == stl_c_opcode
812 || INSN_OPCODE (insn) == stq_c_opcode)
816 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
817 if (INSN_OPCODE (insn) != stl_c_opcode
818 && INSN_OPCODE (insn) != stq_c_opcode)
822 loc += ALPHA_INSN_SIZE;
824 /* Insert a breakpoint right after the end of the atomic sequence. */
827 /* Check for duplicated breakpoints. Check also for a breakpoint
828 placed (branch instruction's destination) anywhere in sequence. */
830 && (breaks[1] == breaks[0]
831 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
834 std::vector<CORE_ADDR> next_pcs;
836 for (index = 0; index <= last_breakpoint; index++)
837 next_pcs.push_back (breaks[index]);
843 /* Figure out where the longjmp will land.
844 We expect the first arg to be a pointer to the jmp_buf structure from
845 which we extract the PC (JB_PC) that we will land at. The PC is copied
846 into the "pc". This routine returns true on success. */
849 alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
851 struct gdbarch *gdbarch = get_frame_arch (frame);
852 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
853 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
855 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
857 jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM);
859 if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size),
860 raw_buffer, tdep->jb_elt_size))
863 *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order);
868 /* Frame unwinder for signal trampolines. We use alpha tdep bits that
869 describe the location and shape of the sigcontext structure. After
870 that, all registers are in memory, so it's easy. */
871 /* ??? Shouldn't we be able to do this generically, rather than with
872 OSABI data specific to Alpha? */
874 struct alpha_sigtramp_unwind_cache
876 CORE_ADDR sigcontext_addr;
879 static struct alpha_sigtramp_unwind_cache *
880 alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
881 void **this_prologue_cache)
883 struct alpha_sigtramp_unwind_cache *info;
884 struct gdbarch_tdep *tdep;
886 if (*this_prologue_cache)
887 return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache;
889 info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache);
890 *this_prologue_cache = info;
892 tdep = gdbarch_tdep (get_frame_arch (this_frame));
893 info->sigcontext_addr = tdep->sigcontext_addr (this_frame);
898 /* Return the address of REGNUM in a sigtramp frame. Since this is
899 all arithmetic, it doesn't seem worthwhile to cache it. */
902 alpha_sigtramp_register_address (struct gdbarch *gdbarch,
903 CORE_ADDR sigcontext_addr, int regnum)
905 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
907 if (regnum >= 0 && regnum < 32)
908 return sigcontext_addr + tdep->sc_regs_offset + regnum * 8;
909 else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32)
910 return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8;
911 else if (regnum == ALPHA_PC_REGNUM)
912 return sigcontext_addr + tdep->sc_pc_offset;
917 /* Given a GDB frame, determine the address of the calling function's
918 frame. This will be used to create a new GDB frame struct. */
921 alpha_sigtramp_frame_this_id (struct frame_info *this_frame,
922 void **this_prologue_cache,
923 struct frame_id *this_id)
925 struct gdbarch *gdbarch = get_frame_arch (this_frame);
926 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
927 struct alpha_sigtramp_unwind_cache *info
928 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
929 CORE_ADDR stack_addr, code_addr;
931 /* If the OSABI couldn't locate the sigcontext, give up. */
932 if (info->sigcontext_addr == 0)
935 /* If we have dynamic signal trampolines, find their start.
936 If we do not, then we must assume there is a symbol record
937 that can provide the start address. */
938 if (tdep->dynamic_sigtramp_offset)
941 code_addr = get_frame_pc (this_frame);
942 offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr);
949 code_addr = get_frame_func (this_frame);
951 /* The stack address is trivially read from the sigcontext. */
952 stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr,
954 stack_addr = get_frame_memory_unsigned (this_frame, stack_addr,
955 ALPHA_REGISTER_SIZE);
957 *this_id = frame_id_build (stack_addr, code_addr);
960 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
962 static struct value *
963 alpha_sigtramp_frame_prev_register (struct frame_info *this_frame,
964 void **this_prologue_cache, int regnum)
966 struct alpha_sigtramp_unwind_cache *info
967 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
970 if (info->sigcontext_addr != 0)
972 /* All integer and fp registers are stored in memory. */
973 addr = alpha_sigtramp_register_address (get_frame_arch (this_frame),
974 info->sigcontext_addr, regnum);
976 return frame_unwind_got_memory (this_frame, regnum, addr);
979 /* This extra register may actually be in the sigcontext, but our
980 current description of it in alpha_sigtramp_frame_unwind_cache
981 doesn't include it. Too bad. Fall back on whatever's in the
983 return frame_unwind_got_register (this_frame, regnum, regnum);
987 alpha_sigtramp_frame_sniffer (const struct frame_unwind *self,
988 struct frame_info *this_frame,
989 void **this_prologue_cache)
991 struct gdbarch *gdbarch = get_frame_arch (this_frame);
992 CORE_ADDR pc = get_frame_pc (this_frame);
995 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
996 look at tramp-frame.h and other simplier per-architecture
997 sigtramp unwinders. */
999 /* We shouldn't even bother to try if the OSABI didn't register a
1000 sigcontext_addr handler or pc_in_sigtramp hander. */
1001 if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL)
1003 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL)
1006 /* Otherwise we should be in a signal frame. */
1007 find_pc_partial_function (pc, &name, NULL, NULL);
1008 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name))
1014 static const struct frame_unwind alpha_sigtramp_frame_unwind = {
1016 default_frame_unwind_stop_reason,
1017 alpha_sigtramp_frame_this_id,
1018 alpha_sigtramp_frame_prev_register,
1020 alpha_sigtramp_frame_sniffer
1025 /* Heuristic_proc_start may hunt through the text section for a long
1026 time across a 2400 baud serial line. Allows the user to limit this
1028 static int heuristic_fence_post = 0;
1030 /* Attempt to locate the start of the function containing PC. We assume that
1031 the previous function ends with an about_to_return insn. Not foolproof by
1032 any means, since gcc is happy to put the epilogue in the middle of a
1033 function. But we're guessing anyway... */
1036 alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
1038 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1039 CORE_ADDR last_non_nop = pc;
1040 CORE_ADDR fence = pc - heuristic_fence_post;
1041 CORE_ADDR orig_pc = pc;
1043 struct inferior *inf;
1048 /* First see if we can find the start of the function from minimal
1049 symbol information. This can succeed with a binary that doesn't
1050 have debug info, but hasn't been stripped. */
1051 func = get_pc_function_start (pc);
1055 if (heuristic_fence_post == -1
1056 || fence < tdep->vm_min_address)
1057 fence = tdep->vm_min_address;
1059 /* Search back for previous return; also stop at a 0, which might be
1060 seen for instance before the start of a code section. Don't include
1061 nops, since this usually indicates padding between functions. */
1062 for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE)
1064 unsigned int insn = alpha_read_insn (gdbarch, pc);
1067 case 0: /* invalid insn */
1068 case 0x6bfa8001: /* ret $31,($26),1 */
1069 return last_non_nop;
1071 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
1072 case 0x47ff041f: /* nop: bis $31,$31,$31 */
1081 inf = current_inferior ();
1083 /* It's not clear to me why we reach this point when stopping quietly,
1084 but with this test, at least we don't print out warnings for every
1085 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
1086 if (inf->control.stop_soon == NO_STOP_QUIETLY)
1088 static int blurb_printed = 0;
1090 if (fence == tdep->vm_min_address)
1091 warning (_("Hit beginning of text section without finding \
1092 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1094 warning (_("Hit heuristic-fence-post without finding \
1095 enclosing function for address %s"), paddress (gdbarch, orig_pc));
1099 printf_filtered (_("\
1100 This warning occurs if you are debugging a function without any symbols\n\
1101 (for example, in a stripped executable). In that case, you may wish to\n\
1102 increase the size of the search with the `set heuristic-fence-post' command.\n\
1104 Otherwise, you told GDB there was a function where there isn't one, or\n\
1105 (more likely) you have encountered a bug in GDB.\n"));
1113 /* Fallback alpha frame unwinder. Uses instruction scanning and knows
1114 something about the traditional layout of alpha stack frames. */
1116 struct alpha_heuristic_unwind_cache
1120 struct trad_frame_saved_reg *saved_regs;
1124 /* If a probing loop sequence starts at PC, simulate it and compute
1125 FRAME_SIZE and PC after its execution. Otherwise, return with PC and
1126 FRAME_SIZE unchanged. */
1129 alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc,
1132 CORE_ADDR cur_pc = *pc;
1133 int cur_frame_size = *frame_size;
1134 int nb_of_iterations, reg_index, reg_probe;
1137 /* The following pattern is recognized as a probing loop:
1139 lda REG_INDEX,NB_OF_ITERATIONS
1140 lda REG_PROBE,<immediate>(sp)
1143 stq zero,<immediate>(REG_PROBE)
1144 subq REG_INDEX,0x1,REG_INDEX
1145 lda REG_PROBE,<immediate>(REG_PROBE)
1146 bne REG_INDEX, LOOP_START
1148 lda sp,<immediate>(REG_PROBE)
1150 If anything different is found, the function returns without
1151 changing PC and FRAME_SIZE. Otherwise, PC will point immediately
1152 after this sequence, and FRAME_SIZE will be updated. */
1154 /* lda REG_INDEX,NB_OF_ITERATIONS */
1156 insn = alpha_read_insn (gdbarch, cur_pc);
1157 if (INSN_OPCODE (insn) != lda_opcode)
1159 reg_index = MEM_RA (insn);
1160 nb_of_iterations = MEM_DISP (insn);
1162 /* lda REG_PROBE,<immediate>(sp) */
1164 cur_pc += ALPHA_INSN_SIZE;
1165 insn = alpha_read_insn (gdbarch, cur_pc);
1166 if (INSN_OPCODE (insn) != lda_opcode
1167 || MEM_RB (insn) != ALPHA_SP_REGNUM)
1169 reg_probe = MEM_RA (insn);
1170 cur_frame_size -= MEM_DISP (insn);
1172 /* stq zero,<immediate>(REG_PROBE) */
1174 cur_pc += ALPHA_INSN_SIZE;
1175 insn = alpha_read_insn (gdbarch, cur_pc);
1176 if (INSN_OPCODE (insn) != stq_opcode
1177 || MEM_RA (insn) != 0x1f
1178 || MEM_RB (insn) != reg_probe)
1181 /* subq REG_INDEX,0x1,REG_INDEX */
1183 cur_pc += ALPHA_INSN_SIZE;
1184 insn = alpha_read_insn (gdbarch, cur_pc);
1185 if (INSN_OPCODE (insn) != subq_opcode
1186 || !OPR_HAS_IMMEDIATE (insn)
1187 || OPR_FUNCTION (insn) != subq_function
1188 || OPR_LIT(insn) != 1
1189 || OPR_RA (insn) != reg_index
1190 || OPR_RC (insn) != reg_index)
1193 /* lda REG_PROBE,<immediate>(REG_PROBE) */
1195 cur_pc += ALPHA_INSN_SIZE;
1196 insn = alpha_read_insn (gdbarch, cur_pc);
1197 if (INSN_OPCODE (insn) != lda_opcode
1198 || MEM_RA (insn) != reg_probe
1199 || MEM_RB (insn) != reg_probe)
1201 cur_frame_size -= MEM_DISP (insn) * nb_of_iterations;
1203 /* bne REG_INDEX, LOOP_START */
1205 cur_pc += ALPHA_INSN_SIZE;
1206 insn = alpha_read_insn (gdbarch, cur_pc);
1207 if (INSN_OPCODE (insn) != bne_opcode
1208 || MEM_RA (insn) != reg_index)
1211 /* lda sp,<immediate>(REG_PROBE) */
1213 cur_pc += ALPHA_INSN_SIZE;
1214 insn = alpha_read_insn (gdbarch, cur_pc);
1215 if (INSN_OPCODE (insn) != lda_opcode
1216 || MEM_RA (insn) != ALPHA_SP_REGNUM
1217 || MEM_RB (insn) != reg_probe)
1219 cur_frame_size -= MEM_DISP (insn);
1222 *frame_size = cur_frame_size;
1225 static struct alpha_heuristic_unwind_cache *
1226 alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame,
1227 void **this_prologue_cache,
1230 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1231 struct alpha_heuristic_unwind_cache *info;
1233 CORE_ADDR limit_pc, cur_pc;
1234 int frame_reg, frame_size, return_reg, reg;
1236 if (*this_prologue_cache)
1237 return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache;
1239 info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache);
1240 *this_prologue_cache = info;
1241 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1243 limit_pc = get_frame_pc (this_frame);
1245 start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc);
1246 info->start_pc = start_pc;
1248 frame_reg = ALPHA_SP_REGNUM;
1252 /* If we've identified a likely place to start, do code scanning. */
1255 /* Limit the forward search to 50 instructions. */
1256 if (start_pc + 200 < limit_pc)
1257 limit_pc = start_pc + 200;
1259 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE)
1261 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1263 if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1267 /* Consider only the first stack allocation instruction
1268 to contain the static size of the frame. */
1269 if (frame_size == 0)
1270 frame_size = (-word) & 0xffff;
1274 /* Exit loop if a positive stack adjustment is found, which
1275 usually means that the stack cleanup code in the function
1276 epilogue is reached. */
1280 else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1282 reg = (word & 0x03e00000) >> 21;
1284 /* Ignore this instruction if we have already encountered
1285 an instruction saving the same register earlier in the
1286 function code. The current instruction does not tell
1287 us where the original value upon function entry is saved.
1288 All it says is that the function we are scanning reused
1289 that register for some computation of its own, and is now
1290 saving its result. */
1291 if (trad_frame_addr_p(info->saved_regs, reg))
1297 /* Do not compute the address where the register was saved yet,
1298 because we don't know yet if the offset will need to be
1299 relative to $sp or $fp (we can not compute the address
1300 relative to $sp if $sp is updated during the execution of
1301 the current subroutine, for instance when doing some alloca).
1302 So just store the offset for the moment, and compute the
1303 address later when we know whether this frame has a frame
1305 /* Hack: temporarily add one, so that the offset is non-zero
1306 and we can tell which registers have save offsets below. */
1307 info->saved_regs[reg].addr = (word & 0xffff) + 1;
1309 /* Starting with OSF/1-3.2C, the system libraries are shipped
1310 without local symbols, but they still contain procedure
1311 descriptors without a symbol reference. GDB is currently
1312 unable to find these procedure descriptors and uses
1313 heuristic_proc_desc instead.
1314 As some low level compiler support routines (__div*, __add*)
1315 use a non-standard return address register, we have to
1316 add some heuristics to determine the return address register,
1317 or stepping over these routines will fail.
1318 Usually the return address register is the first register
1319 saved on the stack, but assembler optimization might
1320 rearrange the register saves.
1321 So we recognize only a few registers (t7, t9, ra) within
1322 the procedure prologue as valid return address registers.
1323 If we encounter a return instruction, we extract the
1324 return address register from it.
1326 FIXME: Rewriting GDB to access the procedure descriptors,
1327 e.g. via the minimal symbol table, might obviate this
1329 if (return_reg == -1
1330 && cur_pc < (start_pc + 80)
1331 && (reg == ALPHA_T7_REGNUM
1332 || reg == ALPHA_T9_REGNUM
1333 || reg == ALPHA_RA_REGNUM))
1336 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1337 return_reg = (word >> 16) & 0x1f;
1338 else if (word == 0x47de040f) /* bis sp,sp,fp */
1339 frame_reg = ALPHA_GCC_FP_REGNUM;
1340 else if (word == 0x47fe040f) /* bis zero,sp,fp */
1341 frame_reg = ALPHA_GCC_FP_REGNUM;
1343 alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size);
1346 /* If we haven't found a valid return address register yet, keep
1347 searching in the procedure prologue. */
1348 if (return_reg == -1)
1350 while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80))
1352 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
1354 if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1356 reg = (word & 0x03e00000) >> 21;
1357 if (reg == ALPHA_T7_REGNUM
1358 || reg == ALPHA_T9_REGNUM
1359 || reg == ALPHA_RA_REGNUM)
1365 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1367 return_reg = (word >> 16) & 0x1f;
1371 cur_pc += ALPHA_INSN_SIZE;
1376 /* Failing that, do default to the customary RA. */
1377 if (return_reg == -1)
1378 return_reg = ALPHA_RA_REGNUM;
1379 info->return_reg = return_reg;
1381 val = get_frame_register_unsigned (this_frame, frame_reg);
1382 info->vfp = val + frame_size;
1384 /* Convert offsets to absolute addresses. See above about adding
1385 one to the offsets to make all detected offsets non-zero. */
1386 for (reg = 0; reg < ALPHA_NUM_REGS; ++reg)
1387 if (trad_frame_addr_p(info->saved_regs, reg))
1388 info->saved_regs[reg].addr += val - 1;
1390 /* The stack pointer of the previous frame is computed by popping
1391 the current stack frame. */
1392 if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM))
1393 trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp);
1398 /* Given a GDB frame, determine the address of the calling function's
1399 frame. This will be used to create a new GDB frame struct. */
1402 alpha_heuristic_frame_this_id (struct frame_info *this_frame,
1403 void **this_prologue_cache,
1404 struct frame_id *this_id)
1406 struct alpha_heuristic_unwind_cache *info
1407 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1409 *this_id = frame_id_build (info->vfp, info->start_pc);
1412 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
1414 static struct value *
1415 alpha_heuristic_frame_prev_register (struct frame_info *this_frame,
1416 void **this_prologue_cache, int regnum)
1418 struct alpha_heuristic_unwind_cache *info
1419 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1421 /* The PC of the previous frame is stored in the link register of
1422 the current frame. Frob regnum so that we pull the value from
1423 the correct place. */
1424 if (regnum == ALPHA_PC_REGNUM)
1425 regnum = info->return_reg;
1427 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1430 static const struct frame_unwind alpha_heuristic_frame_unwind = {
1432 default_frame_unwind_stop_reason,
1433 alpha_heuristic_frame_this_id,
1434 alpha_heuristic_frame_prev_register,
1436 default_frame_sniffer
1440 alpha_heuristic_frame_base_address (struct frame_info *this_frame,
1441 void **this_prologue_cache)
1443 struct alpha_heuristic_unwind_cache *info
1444 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
1449 static const struct frame_base alpha_heuristic_frame_base = {
1450 &alpha_heuristic_frame_unwind,
1451 alpha_heuristic_frame_base_address,
1452 alpha_heuristic_frame_base_address,
1453 alpha_heuristic_frame_base_address
1456 /* Just like reinit_frame_cache, but with the right arguments to be
1457 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
1460 reinit_frame_cache_sfunc (const char *args,
1461 int from_tty, struct cmd_list_element *c)
1463 reinit_frame_cache ();
1467 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1468 dummy frame. The frame ID's base needs to match the TOS value
1469 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1472 static struct frame_id
1473 alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1476 base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM);
1477 return frame_id_build (base, get_frame_pc (this_frame));
1481 alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1484 pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM);
1489 /* Helper routines for alpha*-nat.c files to move register sets to and
1490 from core files. The UNIQUE pointer is allowed to be NULL, as most
1491 targets don't supply this value in their core files. */
1494 alpha_supply_int_regs (struct regcache *regcache, int regno,
1495 const void *r0_r30, const void *pc, const void *unique)
1497 const gdb_byte *regs = (const gdb_byte *) r0_r30;
1500 for (i = 0; i < 31; ++i)
1501 if (regno == i || regno == -1)
1502 regcache_raw_supply (regcache, i, regs + i * 8);
1504 if (regno == ALPHA_ZERO_REGNUM || regno == -1)
1506 const gdb_byte zero[8] = { 0 };
1508 regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero);
1511 if (regno == ALPHA_PC_REGNUM || regno == -1)
1512 regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc);
1514 if (regno == ALPHA_UNIQUE_REGNUM || regno == -1)
1515 regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique);
1519 alpha_fill_int_regs (const struct regcache *regcache,
1520 int regno, void *r0_r30, void *pc, void *unique)
1522 gdb_byte *regs = (gdb_byte *) r0_r30;
1525 for (i = 0; i < 31; ++i)
1526 if (regno == i || regno == -1)
1527 regcache_raw_collect (regcache, i, regs + i * 8);
1529 if (regno == ALPHA_PC_REGNUM || regno == -1)
1530 regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc);
1532 if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1))
1533 regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique);
1537 alpha_supply_fp_regs (struct regcache *regcache, int regno,
1538 const void *f0_f30, const void *fpcr)
1540 const gdb_byte *regs = (const gdb_byte *) f0_f30;
1543 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1544 if (regno == i || regno == -1)
1545 regcache_raw_supply (regcache, i,
1546 regs + (i - ALPHA_FP0_REGNUM) * 8);
1548 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1549 regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr);
1553 alpha_fill_fp_regs (const struct regcache *regcache,
1554 int regno, void *f0_f30, void *fpcr)
1556 gdb_byte *regs = (gdb_byte *) f0_f30;
1559 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1560 if (regno == i || regno == -1)
1561 regcache_raw_collect (regcache, i,
1562 regs + (i - ALPHA_FP0_REGNUM) * 8);
1564 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
1565 regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr);
1570 /* Return nonzero if the G_floating register value in REG is equal to
1571 zero for FP control instructions. */
1574 fp_register_zero_p (LONGEST reg)
1576 /* Check that all bits except the sign bit are zero. */
1577 const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1;
1579 return ((reg & zero_mask) == 0);
1582 /* Return the value of the sign bit for the G_floating register
1583 value held in REG. */
1586 fp_register_sign_bit (LONGEST reg)
1588 const LONGEST sign_mask = (LONGEST) 1 << 63;
1590 return ((reg & sign_mask) != 0);
1593 /* alpha_software_single_step() is called just before we want to resume
1594 the inferior, if we want to single-step it but there is no hardware
1595 or kernel single-step support (NetBSD on Alpha, for example). We find
1596 the target of the coming instruction and breakpoint it. */
1599 alpha_next_pc (struct regcache *regcache, CORE_ADDR pc)
1601 struct gdbarch *gdbarch = regcache->arch ();
1608 insn = alpha_read_insn (gdbarch, pc);
1610 /* Opcode is top 6 bits. */
1611 op = (insn >> 26) & 0x3f;
1615 /* Jump format: target PC is:
1617 return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3);
1620 if ((op & 0x30) == 0x30)
1622 /* Branch format: target PC is:
1623 (new PC) + (4 * sext(displacement)) */
1624 if (op == 0x30 /* BR */
1625 || op == 0x34) /* BSR */
1628 offset = (insn & 0x001fffff);
1629 if (offset & 0x00100000)
1630 offset |= 0xffe00000;
1631 offset *= ALPHA_INSN_SIZE;
1632 return (pc + ALPHA_INSN_SIZE + offset);
1635 /* Need to determine if branch is taken; read RA. */
1636 regno = (insn >> 21) & 0x1f;
1639 case 0x31: /* FBEQ */
1640 case 0x36: /* FBGE */
1641 case 0x37: /* FBGT */
1642 case 0x33: /* FBLE */
1643 case 0x32: /* FBLT */
1644 case 0x35: /* FBNE */
1645 regno += gdbarch_fp0_regnum (gdbarch);
1648 rav = regcache_raw_get_signed (regcache, regno);
1652 case 0x38: /* BLBC */
1656 case 0x3c: /* BLBS */
1660 case 0x39: /* BEQ */
1664 case 0x3d: /* BNE */
1668 case 0x3a: /* BLT */
1672 case 0x3b: /* BLE */
1676 case 0x3f: /* BGT */
1680 case 0x3e: /* BGE */
1685 /* Floating point branches. */
1687 case 0x31: /* FBEQ */
1688 if (fp_register_zero_p (rav))
1691 case 0x36: /* FBGE */
1692 if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav))
1695 case 0x37: /* FBGT */
1696 if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav))
1699 case 0x33: /* FBLE */
1700 if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav))
1703 case 0x32: /* FBLT */
1704 if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav))
1707 case 0x35: /* FBNE */
1708 if (! fp_register_zero_p (rav))
1714 /* Not a branch or branch not taken; target PC is:
1716 return (pc + ALPHA_INSN_SIZE);
1719 std::vector<CORE_ADDR>
1720 alpha_software_single_step (struct regcache *regcache)
1722 struct gdbarch *gdbarch = regcache->arch ();
1724 CORE_ADDR pc = regcache_read_pc (regcache);
1726 std::vector<CORE_ADDR> next_pcs
1727 = alpha_deal_with_atomic_sequence (gdbarch, pc);
1728 if (!next_pcs.empty ())
1731 CORE_ADDR next_pc = alpha_next_pc (regcache, pc);
1736 /* Initialize the current architecture based on INFO. If possible, re-use an
1737 architecture from ARCHES, which is a list of architectures already created
1738 during this debugging session.
1740 Called e.g. at program startup, when reading a core file, and when reading
1743 static struct gdbarch *
1744 alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1746 struct gdbarch_tdep *tdep;
1747 struct gdbarch *gdbarch;
1749 /* Find a candidate among extant architectures. */
1750 arches = gdbarch_list_lookup_by_info (arches, &info);
1752 return arches->gdbarch;
1754 tdep = XCNEW (struct gdbarch_tdep);
1755 gdbarch = gdbarch_alloc (&info, tdep);
1757 /* Lowest text address. This is used by heuristic_proc_start()
1758 to decide when to stop looking. */
1759 tdep->vm_min_address = (CORE_ADDR) 0x120000000LL;
1761 tdep->dynamic_sigtramp_offset = NULL;
1762 tdep->sigcontext_addr = NULL;
1763 tdep->sc_pc_offset = 2 * 8;
1764 tdep->sc_regs_offset = 4 * 8;
1765 tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8;
1767 tdep->jb_pc = -1; /* longjmp support not enabled by default. */
1769 tdep->return_in_memory = alpha_return_in_memory_always;
1772 set_gdbarch_short_bit (gdbarch, 16);
1773 set_gdbarch_int_bit (gdbarch, 32);
1774 set_gdbarch_long_bit (gdbarch, 64);
1775 set_gdbarch_long_long_bit (gdbarch, 64);
1776 set_gdbarch_wchar_bit (gdbarch, 64);
1777 set_gdbarch_wchar_signed (gdbarch, 0);
1778 set_gdbarch_float_bit (gdbarch, 32);
1779 set_gdbarch_double_bit (gdbarch, 64);
1780 set_gdbarch_long_double_bit (gdbarch, 64);
1781 set_gdbarch_ptr_bit (gdbarch, 64);
1784 set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS);
1785 set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM);
1786 set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM);
1787 set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM);
1789 set_gdbarch_register_name (gdbarch, alpha_register_name);
1790 set_gdbarch_register_type (gdbarch, alpha_register_type);
1792 set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register);
1793 set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register);
1795 set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p);
1796 set_gdbarch_register_to_value (gdbarch, alpha_register_to_value);
1797 set_gdbarch_value_to_register (gdbarch, alpha_value_to_register);
1799 set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p);
1801 /* Prologue heuristics. */
1802 set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue);
1806 set_gdbarch_return_value (gdbarch, alpha_return_value);
1808 /* Settings for calling functions in the inferior. */
1809 set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call);
1811 /* Methods for saving / extracting a dummy frame's ID. */
1812 set_gdbarch_dummy_id (gdbarch, alpha_dummy_id);
1814 /* Return the unwound PC value. */
1815 set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc);
1817 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1818 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
1820 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1821 alpha_breakpoint::kind_from_pc);
1822 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1823 alpha_breakpoint::bp_from_kind);
1824 set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE);
1825 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1827 /* Handles single stepping of atomic sequences. */
1828 set_gdbarch_software_single_step (gdbarch, alpha_software_single_step);
1830 /* Hook in ABI-specific overrides, if they have been registered. */
1831 gdbarch_init_osabi (info, gdbarch);
1833 /* Now that we have tuned the configuration, set a few final things
1834 based on what the OS ABI has told us. */
1836 if (tdep->jb_pc >= 0)
1837 set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target);
1839 frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind);
1840 frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind);
1842 frame_base_set_default (gdbarch, &alpha_heuristic_frame_base);
1848 alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1850 dwarf2_append_unwinders (gdbarch);
1851 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
1855 _initialize_alpha_tdep (void)
1858 gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL);
1860 /* Let the user set the fence post for heuristic_proc_start. */
1862 /* We really would like to have both "0" and "unlimited" work, but
1863 command.c doesn't deal with that. So make it a var_zinteger
1864 because the user can always use "999999" or some such for unlimited. */
1865 /* We need to throw away the frame cache when we set this, since it
1866 might change our ability to get backtraces. */
1867 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
1868 &heuristic_fence_post, _("\
1869 Set the distance searched for the start of a function."), _("\
1870 Show the distance searched for the start of a function."), _("\
1871 If you are debugging a stripped executable, GDB needs to search through the\n\
1872 program for the start of a function. This command sets the distance of the\n\
1873 search. The only need to set it is when debugging a stripped executable."),
1874 reinit_frame_cache_sfunc,
1875 NULL, /* FIXME: i18n: The distance searched for
1876 the start of a function is \"%d\". */
1877 &setlist, &showlist);