1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
32 #include "arch-utils.h"
34 #include "frame-unwind.h"
35 #include "frame-base.h"
36 #include "trad-frame.h"
38 #include "dwarf2-frame.h"
40 #include "prologue-value.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
58 #include "features/aarch64.c"
60 #include "arch/aarch64-insn.h"
62 #include "opcode/aarch64.h"
64 #define submask(x) ((1L << ((x) + 1)) - 1)
65 #define bit(obj,st) (((obj) >> (st)) & 1)
66 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
68 /* Pseudo register base numbers. */
69 #define AARCH64_Q0_REGNUM 0
70 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
71 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
72 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
73 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
75 /* The standard register names, and all the valid aliases for them. */
78 const char *const name;
80 } aarch64_register_aliases[] =
82 /* 64-bit register names. */
83 {"fp", AARCH64_FP_REGNUM},
84 {"lr", AARCH64_LR_REGNUM},
85 {"sp", AARCH64_SP_REGNUM},
87 /* 32-bit register names. */
88 {"w0", AARCH64_X0_REGNUM + 0},
89 {"w1", AARCH64_X0_REGNUM + 1},
90 {"w2", AARCH64_X0_REGNUM + 2},
91 {"w3", AARCH64_X0_REGNUM + 3},
92 {"w4", AARCH64_X0_REGNUM + 4},
93 {"w5", AARCH64_X0_REGNUM + 5},
94 {"w6", AARCH64_X0_REGNUM + 6},
95 {"w7", AARCH64_X0_REGNUM + 7},
96 {"w8", AARCH64_X0_REGNUM + 8},
97 {"w9", AARCH64_X0_REGNUM + 9},
98 {"w10", AARCH64_X0_REGNUM + 10},
99 {"w11", AARCH64_X0_REGNUM + 11},
100 {"w12", AARCH64_X0_REGNUM + 12},
101 {"w13", AARCH64_X0_REGNUM + 13},
102 {"w14", AARCH64_X0_REGNUM + 14},
103 {"w15", AARCH64_X0_REGNUM + 15},
104 {"w16", AARCH64_X0_REGNUM + 16},
105 {"w17", AARCH64_X0_REGNUM + 17},
106 {"w18", AARCH64_X0_REGNUM + 18},
107 {"w19", AARCH64_X0_REGNUM + 19},
108 {"w20", AARCH64_X0_REGNUM + 20},
109 {"w21", AARCH64_X0_REGNUM + 21},
110 {"w22", AARCH64_X0_REGNUM + 22},
111 {"w23", AARCH64_X0_REGNUM + 23},
112 {"w24", AARCH64_X0_REGNUM + 24},
113 {"w25", AARCH64_X0_REGNUM + 25},
114 {"w26", AARCH64_X0_REGNUM + 26},
115 {"w27", AARCH64_X0_REGNUM + 27},
116 {"w28", AARCH64_X0_REGNUM + 28},
117 {"w29", AARCH64_X0_REGNUM + 29},
118 {"w30", AARCH64_X0_REGNUM + 30},
121 {"ip0", AARCH64_X0_REGNUM + 16},
122 {"ip1", AARCH64_X0_REGNUM + 17}
125 /* The required core 'R' registers. */
126 static const char *const aarch64_r_register_names[] =
128 /* These registers must appear in consecutive RAW register number
129 order and they must begin with AARCH64_X0_REGNUM! */
130 "x0", "x1", "x2", "x3",
131 "x4", "x5", "x6", "x7",
132 "x8", "x9", "x10", "x11",
133 "x12", "x13", "x14", "x15",
134 "x16", "x17", "x18", "x19",
135 "x20", "x21", "x22", "x23",
136 "x24", "x25", "x26", "x27",
137 "x28", "x29", "x30", "sp",
141 /* The FP/SIMD 'V' registers. */
142 static const char *const aarch64_v_register_names[] =
144 /* These registers must appear in consecutive RAW register number
145 order and they must begin with AARCH64_V0_REGNUM! */
146 "v0", "v1", "v2", "v3",
147 "v4", "v5", "v6", "v7",
148 "v8", "v9", "v10", "v11",
149 "v12", "v13", "v14", "v15",
150 "v16", "v17", "v18", "v19",
151 "v20", "v21", "v22", "v23",
152 "v24", "v25", "v26", "v27",
153 "v28", "v29", "v30", "v31",
158 /* AArch64 prologue cache structure. */
159 struct aarch64_prologue_cache
161 /* The program counter at the start of the function. It is used to
162 identify this frame as a prologue frame. */
165 /* The program counter at the time this frame was created; i.e. where
166 this function was called from. It is used to identify this frame as a
170 /* The stack pointer at the time this frame was created; i.e. the
171 caller's stack pointer when this function was called. It is used
172 to identify this frame. */
175 /* Is the target available to read from? */
178 /* The frame base for this frame is just prev_sp - frame size.
179 FRAMESIZE is the distance from the frame pointer to the
180 initial stack pointer. */
183 /* The register used to hold the frame pointer for this frame. */
186 /* Saved register offsets. */
187 struct trad_frame_saved_reg *saved_regs;
191 show_aarch64_debug (struct ui_file *file, int from_tty,
192 struct cmd_list_element *c, const char *value)
194 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
197 /* Analyze a prologue, looking for a recognizable stack frame
198 and frame pointer. Scan until we encounter a store that could
199 clobber the stack frame unexpectedly, or an unknown instruction. */
202 aarch64_analyze_prologue (struct gdbarch *gdbarch,
203 CORE_ADDR start, CORE_ADDR limit,
204 struct aarch64_prologue_cache *cache)
206 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
208 pv_t regs[AARCH64_X_REGISTER_COUNT];
209 struct pv_area *stack;
210 struct cleanup *back_to;
212 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
213 regs[i] = pv_register (i, 0);
214 stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
215 back_to = make_cleanup_free_pv_area (stack);
217 for (; start < limit; start += 4)
222 insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
224 if (aarch64_decode_insn (insn, &inst, 1) != 0)
227 if (inst.opcode->iclass == addsub_imm
228 && (inst.opcode->op == OP_ADD
229 || strcmp ("sub", inst.opcode->name) == 0))
231 unsigned rd = inst.operands[0].reg.regno;
232 unsigned rn = inst.operands[1].reg.regno;
234 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
235 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
236 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
237 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
239 if (inst.opcode->op == OP_ADD)
241 regs[rd] = pv_add_constant (regs[rn],
242 inst.operands[2].imm.value);
246 regs[rd] = pv_add_constant (regs[rn],
247 -inst.operands[2].imm.value);
250 else if (inst.opcode->iclass == pcreladdr
251 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
253 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
254 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
256 regs[inst.operands[0].reg.regno] = pv_unknown ();
258 else if (inst.opcode->iclass == branch_imm)
260 /* Stop analysis on branch. */
263 else if (inst.opcode->iclass == condbranch)
265 /* Stop analysis on branch. */
268 else if (inst.opcode->iclass == branch_reg)
270 /* Stop analysis on branch. */
273 else if (inst.opcode->iclass == compbranch)
275 /* Stop analysis on branch. */
278 else if (inst.opcode->op == OP_MOVZ)
280 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
281 regs[inst.operands[0].reg.regno] = pv_unknown ();
283 else if (inst.opcode->iclass == log_shift
284 && strcmp (inst.opcode->name, "orr") == 0)
286 unsigned rd = inst.operands[0].reg.regno;
287 unsigned rn = inst.operands[1].reg.regno;
288 unsigned rm = inst.operands[2].reg.regno;
290 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
291 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
292 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
294 if (inst.operands[2].shifter.amount == 0
295 && rn == AARCH64_SP_REGNUM)
301 debug_printf ("aarch64: prologue analysis gave up "
302 "addr=0x%s opcode=0x%x (orr x register)\n",
303 core_addr_to_string_nz (start), insn);
308 else if (inst.opcode->op == OP_STUR)
310 unsigned rt = inst.operands[0].reg.regno;
311 unsigned rn = inst.operands[1].addr.base_regno;
313 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
315 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
316 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
317 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
318 gdb_assert (!inst.operands[1].addr.offset.is_reg);
320 pv_area_store (stack, pv_add_constant (regs[rn],
321 inst.operands[1].addr.offset.imm),
322 is64 ? 8 : 4, regs[rt]);
324 else if ((inst.opcode->iclass == ldstpair_off
325 || inst.opcode->iclass == ldstpair_indexed)
326 && inst.operands[2].addr.preind
327 && strcmp ("stp", inst.opcode->name) == 0)
329 unsigned rt1 = inst.operands[0].reg.regno;
330 unsigned rt2 = inst.operands[1].reg.regno;
331 unsigned rn = inst.operands[2].addr.base_regno;
332 int32_t imm = inst.operands[2].addr.offset.imm;
334 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
335 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2);
336 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
337 gdb_assert (!inst.operands[2].addr.offset.is_reg);
339 /* If recording this store would invalidate the store area
340 (perhaps because rn is not known) then we should abandon
341 further prologue analysis. */
342 if (pv_area_store_would_trash (stack,
343 pv_add_constant (regs[rn], imm)))
346 if (pv_area_store_would_trash (stack,
347 pv_add_constant (regs[rn], imm + 8)))
350 pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
352 pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
355 if (inst.operands[2].addr.writeback)
356 regs[rn] = pv_add_constant (regs[rn], imm);
359 else if (inst.opcode->iclass == testbranch)
361 /* Stop analysis on branch. */
368 debug_printf ("aarch64: prologue analysis gave up addr=0x%s"
370 core_addr_to_string_nz (start), insn);
378 do_cleanups (back_to);
382 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
384 /* Frame pointer is fp. Frame size is constant. */
385 cache->framereg = AARCH64_FP_REGNUM;
386 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
388 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
390 /* Try the stack pointer. */
391 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
392 cache->framereg = AARCH64_SP_REGNUM;
396 /* We're just out of luck. We don't know where the frame is. */
397 cache->framereg = -1;
398 cache->framesize = 0;
401 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
405 if (pv_area_find_reg (stack, gdbarch, i, &offset))
406 cache->saved_regs[i].addr = offset;
409 do_cleanups (back_to);
413 /* Implement the "skip_prologue" gdbarch method. */
416 aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
420 CORE_ADDR func_addr, limit_pc;
421 struct symtab_and_line sal;
423 /* See if we can determine the end of the prologue via the symbol
424 table. If so, then return either PC, or the PC after the
425 prologue, whichever is greater. */
426 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
428 CORE_ADDR post_prologue_pc
429 = skip_prologue_using_sal (gdbarch, func_addr);
431 if (post_prologue_pc != 0)
432 return max (pc, post_prologue_pc);
435 /* Can't determine prologue from the symbol table, need to examine
438 /* Find an upper limit on the function prologue using the debug
439 information. If the debug information could not be used to
440 provide that bound, then use an arbitrary large number as the
442 limit_pc = skip_prologue_using_sal (gdbarch, pc);
444 limit_pc = pc + 128; /* Magic. */
446 /* Try disassembling prologue. */
447 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
450 /* Scan the function prologue for THIS_FRAME and populate the prologue
454 aarch64_scan_prologue (struct frame_info *this_frame,
455 struct aarch64_prologue_cache *cache)
457 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
458 CORE_ADDR prologue_start;
459 CORE_ADDR prologue_end;
460 CORE_ADDR prev_pc = get_frame_pc (this_frame);
461 struct gdbarch *gdbarch = get_frame_arch (this_frame);
463 cache->prev_pc = prev_pc;
465 /* Assume we do not find a frame. */
466 cache->framereg = -1;
467 cache->framesize = 0;
469 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
472 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
476 /* No line info so use the current PC. */
477 prologue_end = prev_pc;
479 else if (sal.end < prologue_end)
481 /* The next line begins after the function end. */
482 prologue_end = sal.end;
485 prologue_end = min (prologue_end, prev_pc);
486 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
493 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
495 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
499 cache->framereg = AARCH64_FP_REGNUM;
500 cache->framesize = 16;
501 cache->saved_regs[29].addr = 0;
502 cache->saved_regs[30].addr = 8;
506 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
507 function may throw an exception if the inferior's registers or memory is
511 aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
512 struct aarch64_prologue_cache *cache)
514 CORE_ADDR unwound_fp;
517 aarch64_scan_prologue (this_frame, cache);
519 if (cache->framereg == -1)
522 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
526 cache->prev_sp = unwound_fp + cache->framesize;
528 /* Calculate actual addresses of saved registers using offsets
529 determined by aarch64_analyze_prologue. */
530 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
531 if (trad_frame_addr_p (cache->saved_regs, reg))
532 cache->saved_regs[reg].addr += cache->prev_sp;
534 cache->func = get_frame_func (this_frame);
536 cache->available_p = 1;
539 /* Allocate and fill in *THIS_CACHE with information about the prologue of
540 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
541 Return a pointer to the current aarch64_prologue_cache in
544 static struct aarch64_prologue_cache *
545 aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
547 struct aarch64_prologue_cache *cache;
549 if (*this_cache != NULL)
550 return (struct aarch64_prologue_cache *) *this_cache;
552 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
553 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
558 aarch64_make_prologue_cache_1 (this_frame, cache);
560 CATCH (ex, RETURN_MASK_ERROR)
562 if (ex.error != NOT_AVAILABLE_ERROR)
563 throw_exception (ex);
570 /* Implement the "stop_reason" frame_unwind method. */
572 static enum unwind_stop_reason
573 aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
576 struct aarch64_prologue_cache *cache
577 = aarch64_make_prologue_cache (this_frame, this_cache);
579 if (!cache->available_p)
580 return UNWIND_UNAVAILABLE;
582 /* Halt the backtrace at "_start". */
583 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
584 return UNWIND_OUTERMOST;
586 /* We've hit a wall, stop. */
587 if (cache->prev_sp == 0)
588 return UNWIND_OUTERMOST;
590 return UNWIND_NO_REASON;
593 /* Our frame ID for a normal frame is the current function's starting
594 PC and the caller's SP when we were called. */
597 aarch64_prologue_this_id (struct frame_info *this_frame,
598 void **this_cache, struct frame_id *this_id)
600 struct aarch64_prologue_cache *cache
601 = aarch64_make_prologue_cache (this_frame, this_cache);
603 if (!cache->available_p)
604 *this_id = frame_id_build_unavailable_stack (cache->func);
606 *this_id = frame_id_build (cache->prev_sp, cache->func);
609 /* Implement the "prev_register" frame_unwind method. */
611 static struct value *
612 aarch64_prologue_prev_register (struct frame_info *this_frame,
613 void **this_cache, int prev_regnum)
615 struct gdbarch *gdbarch = get_frame_arch (this_frame);
616 struct aarch64_prologue_cache *cache
617 = aarch64_make_prologue_cache (this_frame, this_cache);
619 /* If we are asked to unwind the PC, then we need to return the LR
620 instead. The prologue may save PC, but it will point into this
621 frame's prologue, not the next frame's resume location. */
622 if (prev_regnum == AARCH64_PC_REGNUM)
626 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
627 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
630 /* SP is generally not saved to the stack, but this frame is
631 identified by the next frame's stack pointer at the time of the
632 call. The value was already reconstructed into PREV_SP. */
645 if (prev_regnum == AARCH64_SP_REGNUM)
646 return frame_unwind_got_constant (this_frame, prev_regnum,
649 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
653 /* AArch64 prologue unwinder. */
654 struct frame_unwind aarch64_prologue_unwind =
657 aarch64_prologue_frame_unwind_stop_reason,
658 aarch64_prologue_this_id,
659 aarch64_prologue_prev_register,
661 default_frame_sniffer
664 /* Allocate and fill in *THIS_CACHE with information about the prologue of
665 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
666 Return a pointer to the current aarch64_prologue_cache in
669 static struct aarch64_prologue_cache *
670 aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
672 struct aarch64_prologue_cache *cache;
674 if (*this_cache != NULL)
675 return (struct aarch64_prologue_cache *) *this_cache;
677 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
678 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
683 cache->prev_sp = get_frame_register_unsigned (this_frame,
685 cache->prev_pc = get_frame_pc (this_frame);
686 cache->available_p = 1;
688 CATCH (ex, RETURN_MASK_ERROR)
690 if (ex.error != NOT_AVAILABLE_ERROR)
691 throw_exception (ex);
698 /* Implement the "stop_reason" frame_unwind method. */
700 static enum unwind_stop_reason
701 aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
704 struct aarch64_prologue_cache *cache
705 = aarch64_make_stub_cache (this_frame, this_cache);
707 if (!cache->available_p)
708 return UNWIND_UNAVAILABLE;
710 return UNWIND_NO_REASON;
713 /* Our frame ID for a stub frame is the current SP and LR. */
716 aarch64_stub_this_id (struct frame_info *this_frame,
717 void **this_cache, struct frame_id *this_id)
719 struct aarch64_prologue_cache *cache
720 = aarch64_make_stub_cache (this_frame, this_cache);
722 if (cache->available_p)
723 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
725 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
728 /* Implement the "sniffer" frame_unwind method. */
731 aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
732 struct frame_info *this_frame,
733 void **this_prologue_cache)
735 CORE_ADDR addr_in_block;
738 addr_in_block = get_frame_address_in_block (this_frame);
739 if (in_plt_section (addr_in_block)
740 /* We also use the stub winder if the target memory is unreadable
741 to avoid having the prologue unwinder trying to read it. */
742 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
748 /* AArch64 stub unwinder. */
749 struct frame_unwind aarch64_stub_unwind =
752 aarch64_stub_frame_unwind_stop_reason,
753 aarch64_stub_this_id,
754 aarch64_prologue_prev_register,
756 aarch64_stub_unwind_sniffer
759 /* Return the frame base address of *THIS_FRAME. */
762 aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
764 struct aarch64_prologue_cache *cache
765 = aarch64_make_prologue_cache (this_frame, this_cache);
767 return cache->prev_sp - cache->framesize;
770 /* AArch64 default frame base information. */
771 struct frame_base aarch64_normal_base =
773 &aarch64_prologue_unwind,
774 aarch64_normal_frame_base,
775 aarch64_normal_frame_base,
776 aarch64_normal_frame_base
779 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
780 dummy frame. The frame ID's base needs to match the TOS value
781 saved by save_dummy_frame_tos () and returned from
782 aarch64_push_dummy_call, and the PC needs to match the dummy
783 frame's breakpoint. */
785 static struct frame_id
786 aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
788 return frame_id_build (get_frame_register_unsigned (this_frame,
790 get_frame_pc (this_frame));
793 /* Implement the "unwind_pc" gdbarch method. */
796 aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
799 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
804 /* Implement the "unwind_sp" gdbarch method. */
807 aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
809 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
812 /* Return the value of the REGNUM register in the previous frame of
815 static struct value *
816 aarch64_dwarf2_prev_register (struct frame_info *this_frame,
817 void **this_cache, int regnum)
819 struct gdbarch *gdbarch = get_frame_arch (this_frame);
824 case AARCH64_PC_REGNUM:
825 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
826 return frame_unwind_got_constant (this_frame, regnum, lr);
829 internal_error (__FILE__, __LINE__,
830 _("Unexpected register %d"), regnum);
834 /* Implement the "init_reg" dwarf2_frame_ops method. */
837 aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
838 struct dwarf2_frame_state_reg *reg,
839 struct frame_info *this_frame)
843 case AARCH64_PC_REGNUM:
844 reg->how = DWARF2_FRAME_REG_FN;
845 reg->loc.fn = aarch64_dwarf2_prev_register;
847 case AARCH64_SP_REGNUM:
848 reg->how = DWARF2_FRAME_REG_CFA;
853 /* When arguments must be pushed onto the stack, they go on in reverse
854 order. The code below implements a FILO (stack) to do this. */
858 /* Value to pass on stack. */
859 const gdb_byte *data;
861 /* Size in bytes of value to pass on stack. */
865 DEF_VEC_O (stack_item_t);
867 /* Return the alignment (in bytes) of the given type. */
870 aarch64_type_align (struct type *t)
876 t = check_typedef (t);
877 switch (TYPE_CODE (t))
880 /* Should never happen. */
881 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
889 case TYPE_CODE_RANGE:
890 case TYPE_CODE_BITSTRING:
894 return TYPE_LENGTH (t);
896 case TYPE_CODE_ARRAY:
897 case TYPE_CODE_COMPLEX:
898 return aarch64_type_align (TYPE_TARGET_TYPE (t));
900 case TYPE_CODE_STRUCT:
901 case TYPE_CODE_UNION:
903 for (n = 0; n < TYPE_NFIELDS (t); n++)
905 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
913 /* Return 1 if *TY is a homogeneous floating-point aggregate as
914 defined in the AAPCS64 ABI document; otherwise return 0. */
917 is_hfa (struct type *ty)
919 switch (TYPE_CODE (ty))
921 case TYPE_CODE_ARRAY:
923 struct type *target_ty = TYPE_TARGET_TYPE (ty);
924 if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4)
929 case TYPE_CODE_UNION:
930 case TYPE_CODE_STRUCT:
932 if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
934 struct type *member0_type;
936 member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
937 if (TYPE_CODE (member0_type) == TYPE_CODE_FLT)
941 for (i = 0; i < TYPE_NFIELDS (ty); i++)
943 struct type *member1_type;
945 member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i));
946 if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type)
947 || (TYPE_LENGTH (member0_type)
948 != TYPE_LENGTH (member1_type)))
964 /* AArch64 function call information structure. */
965 struct aarch64_call_info
967 /* the current argument number. */
970 /* The next general purpose register number, equivalent to NGRN as
971 described in the AArch64 Procedure Call Standard. */
974 /* The next SIMD and floating point register number, equivalent to
975 NSRN as described in the AArch64 Procedure Call Standard. */
978 /* The next stacked argument address, equivalent to NSAA as
979 described in the AArch64 Procedure Call Standard. */
982 /* Stack item vector. */
983 VEC(stack_item_t) *si;
986 /* Pass a value in a sequence of consecutive X registers. The caller
987 is responsbile for ensuring sufficient registers are available. */
990 pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
991 struct aarch64_call_info *info, struct type *type,
994 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
995 int len = TYPE_LENGTH (type);
996 enum type_code typecode = TYPE_CODE (type);
997 int regnum = AARCH64_X0_REGNUM + info->ngrn;
1003 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1004 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1008 /* Adjust sub-word struct/union args when big-endian. */
1009 if (byte_order == BFD_ENDIAN_BIG
1010 && partial_len < X_REGISTER_SIZE
1011 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1012 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1016 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1017 gdbarch_register_name (gdbarch, regnum),
1018 phex (regval, X_REGISTER_SIZE));
1020 regcache_cooked_write_unsigned (regcache, regnum, regval);
1027 /* Attempt to marshall a value in a V register. Return 1 if
1028 successful, or 0 if insufficient registers are available. This
1029 function, unlike the equivalent pass_in_x() function does not
1030 handle arguments spread across multiple registers. */
1033 pass_in_v (struct gdbarch *gdbarch,
1034 struct regcache *regcache,
1035 struct aarch64_call_info *info,
1036 const bfd_byte *buf)
1040 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1041 int regnum = AARCH64_V0_REGNUM + info->nsrn;
1046 regcache_cooked_write (regcache, regnum, buf);
1049 debug_printf ("arg %d in %s\n", info->argnum,
1050 gdbarch_register_name (gdbarch, regnum));
1058 /* Marshall an argument onto the stack. */
1061 pass_on_stack (struct aarch64_call_info *info, struct type *type,
1062 const bfd_byte *buf)
1064 int len = TYPE_LENGTH (type);
1070 align = aarch64_type_align (type);
1072 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1073 Natural alignment of the argument's type. */
1074 align = align_up (align, 8);
1076 /* The AArch64 PCS requires at most doubleword alignment. */
1082 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1088 VEC_safe_push (stack_item_t, info->si, &item);
1091 if (info->nsaa & (align - 1))
1093 /* Push stack alignment padding. */
1094 int pad = align - (info->nsaa & (align - 1));
1099 VEC_safe_push (stack_item_t, info->si, &item);
1104 /* Marshall an argument into a sequence of one or more consecutive X
1105 registers or, if insufficient X registers are available then onto
1109 pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1110 struct aarch64_call_info *info, struct type *type,
1111 const bfd_byte *buf)
1113 int len = TYPE_LENGTH (type);
1114 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1116 /* PCS C.13 - Pass in registers if we have enough spare */
1117 if (info->ngrn + nregs <= 8)
1119 pass_in_x (gdbarch, regcache, info, type, buf);
1120 info->ngrn += nregs;
1125 pass_on_stack (info, type, buf);
1129 /* Pass a value in a V register, or on the stack if insufficient are
1133 pass_in_v_or_stack (struct gdbarch *gdbarch,
1134 struct regcache *regcache,
1135 struct aarch64_call_info *info,
1137 const bfd_byte *buf)
1139 if (!pass_in_v (gdbarch, regcache, info, buf))
1140 pass_on_stack (info, type, buf);
1143 /* Implement the "push_dummy_call" gdbarch method. */
1146 aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1147 struct regcache *regcache, CORE_ADDR bp_addr,
1149 struct value **args, CORE_ADDR sp, int struct_return,
1150 CORE_ADDR struct_addr)
1156 struct aarch64_call_info info;
1157 struct type *func_type;
1158 struct type *return_type;
1159 int lang_struct_return;
1161 memset (&info, 0, sizeof (info));
1163 /* We need to know what the type of the called function is in order
1164 to determine the number of named/anonymous arguments for the
1165 actual argument placement, and the return type in order to handle
1166 return value correctly.
1168 The generic code above us views the decision of return in memory
1169 or return in registers as a two stage processes. The language
1170 handler is consulted first and may decide to return in memory (eg
1171 class with copy constructor returned by value), this will cause
1172 the generic code to allocate space AND insert an initial leading
1175 If the language code does not decide to pass in memory then the
1176 target code is consulted.
1178 If the language code decides to pass in memory we want to move
1179 the pointer inserted as the initial argument from the argument
1180 list and into X8, the conventional AArch64 struct return pointer
1183 This is slightly awkward, ideally the flag "lang_struct_return"
1184 would be passed to the targets implementation of push_dummy_call.
1185 Rather that change the target interface we call the language code
1186 directly ourselves. */
1188 func_type = check_typedef (value_type (function));
1190 /* Dereference function pointer types. */
1191 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1192 func_type = TYPE_TARGET_TYPE (func_type);
1194 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1195 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1197 /* If language_pass_by_reference () returned true we will have been
1198 given an additional initial argument, a hidden pointer to the
1199 return slot in memory. */
1200 return_type = TYPE_TARGET_TYPE (func_type);
1201 lang_struct_return = language_pass_by_reference (return_type);
1203 /* Set the return address. For the AArch64, the return breakpoint
1204 is always at BP_ADDR. */
1205 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1207 /* If we were given an initial argument for the return slot because
1208 lang_struct_return was true, lose it. */
1209 if (lang_struct_return)
1215 /* The struct_return pointer occupies X8. */
1216 if (struct_return || lang_struct_return)
1220 debug_printf ("struct return in %s = 0x%s\n",
1221 gdbarch_register_name (gdbarch,
1222 AARCH64_STRUCT_RETURN_REGNUM),
1223 paddress (gdbarch, struct_addr));
1225 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1229 for (argnum = 0; argnum < nargs; argnum++)
1231 struct value *arg = args[argnum];
1232 struct type *arg_type;
1235 arg_type = check_typedef (value_type (arg));
1236 len = TYPE_LENGTH (arg_type);
1238 switch (TYPE_CODE (arg_type))
1241 case TYPE_CODE_BOOL:
1242 case TYPE_CODE_CHAR:
1243 case TYPE_CODE_RANGE:
1244 case TYPE_CODE_ENUM:
1247 /* Promote to 32 bit integer. */
1248 if (TYPE_UNSIGNED (arg_type))
1249 arg_type = builtin_type (gdbarch)->builtin_uint32;
1251 arg_type = builtin_type (gdbarch)->builtin_int32;
1252 arg = value_cast (arg_type, arg);
1254 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type,
1255 value_contents (arg));
1258 case TYPE_CODE_COMPLEX:
1261 const bfd_byte *buf = value_contents (arg);
1262 struct type *target_type =
1263 check_typedef (TYPE_TARGET_TYPE (arg_type));
1265 pass_in_v (gdbarch, regcache, &info, buf);
1266 pass_in_v (gdbarch, regcache, &info,
1267 buf + TYPE_LENGTH (target_type));
1272 pass_on_stack (&info, arg_type, value_contents (arg));
1276 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type,
1277 value_contents (arg));
1280 case TYPE_CODE_STRUCT:
1281 case TYPE_CODE_ARRAY:
1282 case TYPE_CODE_UNION:
1283 if (is_hfa (arg_type))
1285 int elements = TYPE_NFIELDS (arg_type);
1287 /* Homogeneous Aggregates */
1288 if (info.nsrn + elements < 8)
1292 for (i = 0; i < elements; i++)
1294 /* We know that we have sufficient registers
1295 available therefore this will never fallback
1297 struct value *field =
1298 value_primitive_field (arg, 0, i, arg_type);
1299 struct type *field_type =
1300 check_typedef (value_type (field));
1302 pass_in_v_or_stack (gdbarch, regcache, &info, field_type,
1303 value_contents_writeable (field));
1309 pass_on_stack (&info, arg_type, value_contents (arg));
1314 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1315 invisible reference. */
1317 /* Allocate aligned storage. */
1318 sp = align_down (sp - len, 16);
1320 /* Write the real data into the stack. */
1321 write_memory (sp, value_contents (arg), len);
1323 /* Construct the indirection. */
1324 arg_type = lookup_pointer_type (arg_type);
1325 arg = value_from_pointer (arg_type, sp);
1326 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type,
1327 value_contents (arg));
1330 /* PCS C.15 / C.18 multiple values pass. */
1331 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type,
1332 value_contents (arg));
1336 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type,
1337 value_contents (arg));
1342 /* Make sure stack retains 16 byte alignment. */
1344 sp -= 16 - (info.nsaa & 15);
1346 while (!VEC_empty (stack_item_t, info.si))
1348 stack_item_t *si = VEC_last (stack_item_t, info.si);
1351 write_memory (sp, si->data, si->len);
1352 VEC_pop (stack_item_t, info.si);
1355 VEC_free (stack_item_t, info.si);
1357 /* Finally, update the SP register. */
1358 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1363 /* Implement the "frame_align" gdbarch method. */
1366 aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1368 /* Align the stack to sixteen bytes. */
1369 return sp & ~(CORE_ADDR) 15;
1372 /* Return the type for an AdvSISD Q register. */
1374 static struct type *
1375 aarch64_vnq_type (struct gdbarch *gdbarch)
1377 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1379 if (tdep->vnq_type == NULL)
1384 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1387 elem = builtin_type (gdbarch)->builtin_uint128;
1388 append_composite_type_field (t, "u", elem);
1390 elem = builtin_type (gdbarch)->builtin_int128;
1391 append_composite_type_field (t, "s", elem);
1396 return tdep->vnq_type;
1399 /* Return the type for an AdvSISD D register. */
1401 static struct type *
1402 aarch64_vnd_type (struct gdbarch *gdbarch)
1404 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1406 if (tdep->vnd_type == NULL)
1411 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1414 elem = builtin_type (gdbarch)->builtin_double;
1415 append_composite_type_field (t, "f", elem);
1417 elem = builtin_type (gdbarch)->builtin_uint64;
1418 append_composite_type_field (t, "u", elem);
1420 elem = builtin_type (gdbarch)->builtin_int64;
1421 append_composite_type_field (t, "s", elem);
1426 return tdep->vnd_type;
1429 /* Return the type for an AdvSISD S register. */
1431 static struct type *
1432 aarch64_vns_type (struct gdbarch *gdbarch)
1434 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1436 if (tdep->vns_type == NULL)
1441 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1444 elem = builtin_type (gdbarch)->builtin_float;
1445 append_composite_type_field (t, "f", elem);
1447 elem = builtin_type (gdbarch)->builtin_uint32;
1448 append_composite_type_field (t, "u", elem);
1450 elem = builtin_type (gdbarch)->builtin_int32;
1451 append_composite_type_field (t, "s", elem);
1456 return tdep->vns_type;
1459 /* Return the type for an AdvSISD H register. */
1461 static struct type *
1462 aarch64_vnh_type (struct gdbarch *gdbarch)
1464 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1466 if (tdep->vnh_type == NULL)
1471 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1474 elem = builtin_type (gdbarch)->builtin_uint16;
1475 append_composite_type_field (t, "u", elem);
1477 elem = builtin_type (gdbarch)->builtin_int16;
1478 append_composite_type_field (t, "s", elem);
1483 return tdep->vnh_type;
1486 /* Return the type for an AdvSISD B register. */
1488 static struct type *
1489 aarch64_vnb_type (struct gdbarch *gdbarch)
1491 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1493 if (tdep->vnb_type == NULL)
1498 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1501 elem = builtin_type (gdbarch)->builtin_uint8;
1502 append_composite_type_field (t, "u", elem);
1504 elem = builtin_type (gdbarch)->builtin_int8;
1505 append_composite_type_field (t, "s", elem);
1510 return tdep->vnb_type;
1513 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1516 aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1518 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1519 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1521 if (reg == AARCH64_DWARF_SP)
1522 return AARCH64_SP_REGNUM;
1524 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1525 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1531 /* Implement the "print_insn" gdbarch method. */
1534 aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1536 info->symbols = NULL;
1537 return print_insn_aarch64 (memaddr, info);
1540 /* AArch64 BRK software debug mode instruction.
1541 Note that AArch64 code is always little-endian.
1542 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1543 static const gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
1545 /* Implement the "breakpoint_from_pc" gdbarch method. */
1547 static const gdb_byte *
1548 aarch64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1551 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1553 *lenptr = sizeof (aarch64_default_breakpoint);
1554 return aarch64_default_breakpoint;
1557 /* Extract from an array REGS containing the (raw) register state a
1558 function return value of type TYPE, and copy that, in virtual
1559 format, into VALBUF. */
1562 aarch64_extract_return_value (struct type *type, struct regcache *regs,
1565 struct gdbarch *gdbarch = get_regcache_arch (regs);
1566 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1568 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1570 bfd_byte buf[V_REGISTER_SIZE];
1571 int len = TYPE_LENGTH (type);
1573 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1574 memcpy (valbuf, buf, len);
1576 else if (TYPE_CODE (type) == TYPE_CODE_INT
1577 || TYPE_CODE (type) == TYPE_CODE_CHAR
1578 || TYPE_CODE (type) == TYPE_CODE_BOOL
1579 || TYPE_CODE (type) == TYPE_CODE_PTR
1580 || TYPE_CODE (type) == TYPE_CODE_REF
1581 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1583 /* If the the type is a plain integer, then the access is
1584 straight-forward. Otherwise we have to play around a bit
1586 int len = TYPE_LENGTH (type);
1587 int regno = AARCH64_X0_REGNUM;
1592 /* By using store_unsigned_integer we avoid having to do
1593 anything special for small big-endian values. */
1594 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1595 store_unsigned_integer (valbuf,
1596 (len > X_REGISTER_SIZE
1597 ? X_REGISTER_SIZE : len), byte_order, tmp);
1598 len -= X_REGISTER_SIZE;
1599 valbuf += X_REGISTER_SIZE;
1602 else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX)
1604 int regno = AARCH64_V0_REGNUM;
1605 bfd_byte buf[V_REGISTER_SIZE];
1606 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1607 int len = TYPE_LENGTH (target_type);
1609 regcache_cooked_read (regs, regno, buf);
1610 memcpy (valbuf, buf, len);
1612 regcache_cooked_read (regs, regno + 1, buf);
1613 memcpy (valbuf, buf, len);
1616 else if (is_hfa (type))
1618 int elements = TYPE_NFIELDS (type);
1619 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1620 int len = TYPE_LENGTH (member_type);
1623 for (i = 0; i < elements; i++)
1625 int regno = AARCH64_V0_REGNUM + i;
1626 bfd_byte buf[X_REGISTER_SIZE];
1630 debug_printf ("read HFA return value element %d from %s\n",
1632 gdbarch_register_name (gdbarch, regno));
1634 regcache_cooked_read (regs, regno, buf);
1636 memcpy (valbuf, buf, len);
1642 /* For a structure or union the behaviour is as if the value had
1643 been stored to word-aligned memory and then loaded into
1644 registers with 64-bit load instruction(s). */
1645 int len = TYPE_LENGTH (type);
1646 int regno = AARCH64_X0_REGNUM;
1647 bfd_byte buf[X_REGISTER_SIZE];
1651 regcache_cooked_read (regs, regno++, buf);
1652 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1653 len -= X_REGISTER_SIZE;
1654 valbuf += X_REGISTER_SIZE;
1660 /* Will a function return an aggregate type in memory or in a
1661 register? Return 0 if an aggregate type can be returned in a
1662 register, 1 if it must be returned in memory. */
1665 aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1668 enum type_code code;
1670 type = check_typedef (type);
1672 /* In the AArch64 ABI, "integer" like aggregate types are returned
1673 in registers. For an aggregate type to be integer like, its size
1674 must be less than or equal to 4 * X_REGISTER_SIZE. */
1678 /* PCS B.5 If the argument is a Named HFA, then the argument is
1683 if (TYPE_LENGTH (type) > 16)
1685 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1686 invisible reference. */
1694 /* Write into appropriate registers a function return value of type
1695 TYPE, given in virtual format. */
1698 aarch64_store_return_value (struct type *type, struct regcache *regs,
1699 const gdb_byte *valbuf)
1701 struct gdbarch *gdbarch = get_regcache_arch (regs);
1702 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1704 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1706 bfd_byte buf[V_REGISTER_SIZE];
1707 int len = TYPE_LENGTH (type);
1709 memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
1710 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
1712 else if (TYPE_CODE (type) == TYPE_CODE_INT
1713 || TYPE_CODE (type) == TYPE_CODE_CHAR
1714 || TYPE_CODE (type) == TYPE_CODE_BOOL
1715 || TYPE_CODE (type) == TYPE_CODE_PTR
1716 || TYPE_CODE (type) == TYPE_CODE_REF
1717 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1719 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
1721 /* Values of one word or less are zero/sign-extended and
1723 bfd_byte tmpbuf[X_REGISTER_SIZE];
1724 LONGEST val = unpack_long (type, valbuf);
1726 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
1727 regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf);
1731 /* Integral values greater than one word are stored in
1732 consecutive registers starting with r0. This will always
1733 be a multiple of the regiser size. */
1734 int len = TYPE_LENGTH (type);
1735 int regno = AARCH64_X0_REGNUM;
1739 regcache_cooked_write (regs, regno++, valbuf);
1740 len -= X_REGISTER_SIZE;
1741 valbuf += X_REGISTER_SIZE;
1745 else if (is_hfa (type))
1747 int elements = TYPE_NFIELDS (type);
1748 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1749 int len = TYPE_LENGTH (member_type);
1752 for (i = 0; i < elements; i++)
1754 int regno = AARCH64_V0_REGNUM + i;
1755 bfd_byte tmpbuf[MAX_REGISTER_SIZE];
1759 debug_printf ("write HFA return value element %d to %s\n",
1761 gdbarch_register_name (gdbarch, regno));
1764 memcpy (tmpbuf, valbuf, len);
1765 regcache_cooked_write (regs, regno, tmpbuf);
1771 /* For a structure or union the behaviour is as if the value had
1772 been stored to word-aligned memory and then loaded into
1773 registers with 64-bit load instruction(s). */
1774 int len = TYPE_LENGTH (type);
1775 int regno = AARCH64_X0_REGNUM;
1776 bfd_byte tmpbuf[X_REGISTER_SIZE];
1780 memcpy (tmpbuf, valbuf,
1781 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1782 regcache_cooked_write (regs, regno++, tmpbuf);
1783 len -= X_REGISTER_SIZE;
1784 valbuf += X_REGISTER_SIZE;
1789 /* Implement the "return_value" gdbarch method. */
1791 static enum return_value_convention
1792 aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
1793 struct type *valtype, struct regcache *regcache,
1794 gdb_byte *readbuf, const gdb_byte *writebuf)
1796 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1798 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1799 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1800 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1802 if (aarch64_return_in_memory (gdbarch, valtype))
1805 debug_printf ("return value in memory\n");
1806 return RETURN_VALUE_STRUCT_CONVENTION;
1811 aarch64_store_return_value (valtype, regcache, writebuf);
1814 aarch64_extract_return_value (valtype, regcache, readbuf);
1817 debug_printf ("return value in registers\n");
1819 return RETURN_VALUE_REGISTER_CONVENTION;
1822 /* Implement the "get_longjmp_target" gdbarch method. */
1825 aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1828 gdb_byte buf[X_REGISTER_SIZE];
1829 struct gdbarch *gdbarch = get_frame_arch (frame);
1830 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1831 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1833 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
1835 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
1839 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
1843 /* Implement the "gen_return_address" gdbarch method. */
1846 aarch64_gen_return_address (struct gdbarch *gdbarch,
1847 struct agent_expr *ax, struct axs_value *value,
1850 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
1851 value->kind = axs_lvalue_register;
1852 value->u.reg = AARCH64_LR_REGNUM;
1856 /* Return the pseudo register name corresponding to register regnum. */
1859 aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
1861 static const char *const q_name[] =
1863 "q0", "q1", "q2", "q3",
1864 "q4", "q5", "q6", "q7",
1865 "q8", "q9", "q10", "q11",
1866 "q12", "q13", "q14", "q15",
1867 "q16", "q17", "q18", "q19",
1868 "q20", "q21", "q22", "q23",
1869 "q24", "q25", "q26", "q27",
1870 "q28", "q29", "q30", "q31",
1873 static const char *const d_name[] =
1875 "d0", "d1", "d2", "d3",
1876 "d4", "d5", "d6", "d7",
1877 "d8", "d9", "d10", "d11",
1878 "d12", "d13", "d14", "d15",
1879 "d16", "d17", "d18", "d19",
1880 "d20", "d21", "d22", "d23",
1881 "d24", "d25", "d26", "d27",
1882 "d28", "d29", "d30", "d31",
1885 static const char *const s_name[] =
1887 "s0", "s1", "s2", "s3",
1888 "s4", "s5", "s6", "s7",
1889 "s8", "s9", "s10", "s11",
1890 "s12", "s13", "s14", "s15",
1891 "s16", "s17", "s18", "s19",
1892 "s20", "s21", "s22", "s23",
1893 "s24", "s25", "s26", "s27",
1894 "s28", "s29", "s30", "s31",
1897 static const char *const h_name[] =
1899 "h0", "h1", "h2", "h3",
1900 "h4", "h5", "h6", "h7",
1901 "h8", "h9", "h10", "h11",
1902 "h12", "h13", "h14", "h15",
1903 "h16", "h17", "h18", "h19",
1904 "h20", "h21", "h22", "h23",
1905 "h24", "h25", "h26", "h27",
1906 "h28", "h29", "h30", "h31",
1909 static const char *const b_name[] =
1911 "b0", "b1", "b2", "b3",
1912 "b4", "b5", "b6", "b7",
1913 "b8", "b9", "b10", "b11",
1914 "b12", "b13", "b14", "b15",
1915 "b16", "b17", "b18", "b19",
1916 "b20", "b21", "b22", "b23",
1917 "b24", "b25", "b26", "b27",
1918 "b28", "b29", "b30", "b31",
1921 regnum -= gdbarch_num_regs (gdbarch);
1923 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
1924 return q_name[regnum - AARCH64_Q0_REGNUM];
1926 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
1927 return d_name[regnum - AARCH64_D0_REGNUM];
1929 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
1930 return s_name[regnum - AARCH64_S0_REGNUM];
1932 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
1933 return h_name[regnum - AARCH64_H0_REGNUM];
1935 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
1936 return b_name[regnum - AARCH64_B0_REGNUM];
1938 internal_error (__FILE__, __LINE__,
1939 _("aarch64_pseudo_register_name: bad register number %d"),
1943 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
1945 static struct type *
1946 aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1948 regnum -= gdbarch_num_regs (gdbarch);
1950 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
1951 return aarch64_vnq_type (gdbarch);
1953 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
1954 return aarch64_vnd_type (gdbarch);
1956 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
1957 return aarch64_vns_type (gdbarch);
1959 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
1960 return aarch64_vnh_type (gdbarch);
1962 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
1963 return aarch64_vnb_type (gdbarch);
1965 internal_error (__FILE__, __LINE__,
1966 _("aarch64_pseudo_register_type: bad register number %d"),
1970 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
1973 aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1974 struct reggroup *group)
1976 regnum -= gdbarch_num_regs (gdbarch);
1978 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
1979 return group == all_reggroup || group == vector_reggroup;
1980 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
1981 return (group == all_reggroup || group == vector_reggroup
1982 || group == float_reggroup);
1983 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
1984 return (group == all_reggroup || group == vector_reggroup
1985 || group == float_reggroup);
1986 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
1987 return group == all_reggroup || group == vector_reggroup;
1988 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
1989 return group == all_reggroup || group == vector_reggroup;
1991 return group == all_reggroup;
1994 /* Implement the "pseudo_register_read_value" gdbarch method. */
1996 static struct value *
1997 aarch64_pseudo_read_value (struct gdbarch *gdbarch,
1998 struct regcache *regcache,
2001 gdb_byte reg_buf[MAX_REGISTER_SIZE];
2002 struct value *result_value;
2005 result_value = allocate_value (register_type (gdbarch, regnum));
2006 VALUE_LVAL (result_value) = lval_register;
2007 VALUE_REGNUM (result_value) = regnum;
2008 buf = value_contents_raw (result_value);
2010 regnum -= gdbarch_num_regs (gdbarch);
2012 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2014 enum register_status status;
2017 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2018 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2019 if (status != REG_VALID)
2020 mark_value_bytes_unavailable (result_value, 0,
2021 TYPE_LENGTH (value_type (result_value)));
2023 memcpy (buf, reg_buf, Q_REGISTER_SIZE);
2024 return result_value;
2027 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2029 enum register_status status;
2032 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2033 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2034 if (status != REG_VALID)
2035 mark_value_bytes_unavailable (result_value, 0,
2036 TYPE_LENGTH (value_type (result_value)));
2038 memcpy (buf, reg_buf, D_REGISTER_SIZE);
2039 return result_value;
2042 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2044 enum register_status status;
2047 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2048 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2049 if (status != REG_VALID)
2050 mark_value_bytes_unavailable (result_value, 0,
2051 TYPE_LENGTH (value_type (result_value)));
2053 memcpy (buf, reg_buf, S_REGISTER_SIZE);
2054 return result_value;
2057 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2059 enum register_status status;
2062 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2063 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2064 if (status != REG_VALID)
2065 mark_value_bytes_unavailable (result_value, 0,
2066 TYPE_LENGTH (value_type (result_value)));
2068 memcpy (buf, reg_buf, H_REGISTER_SIZE);
2069 return result_value;
2072 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2074 enum register_status status;
2077 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2078 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2079 if (status != REG_VALID)
2080 mark_value_bytes_unavailable (result_value, 0,
2081 TYPE_LENGTH (value_type (result_value)));
2083 memcpy (buf, reg_buf, B_REGISTER_SIZE);
2084 return result_value;
2087 gdb_assert_not_reached ("regnum out of bound");
2090 /* Implement the "pseudo_register_write" gdbarch method. */
2093 aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2094 int regnum, const gdb_byte *buf)
2096 gdb_byte reg_buf[MAX_REGISTER_SIZE];
2098 /* Ensure the register buffer is zero, we want gdb writes of the
2099 various 'scalar' pseudo registers to behavior like architectural
2100 writes, register width bytes are written the remainder are set to
2102 memset (reg_buf, 0, sizeof (reg_buf));
2104 regnum -= gdbarch_num_regs (gdbarch);
2106 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2108 /* pseudo Q registers */
2111 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2112 memcpy (reg_buf, buf, Q_REGISTER_SIZE);
2113 regcache_raw_write (regcache, v_regnum, reg_buf);
2117 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2119 /* pseudo D registers */
2122 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2123 memcpy (reg_buf, buf, D_REGISTER_SIZE);
2124 regcache_raw_write (regcache, v_regnum, reg_buf);
2128 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2132 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2133 memcpy (reg_buf, buf, S_REGISTER_SIZE);
2134 regcache_raw_write (regcache, v_regnum, reg_buf);
2138 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2140 /* pseudo H registers */
2143 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2144 memcpy (reg_buf, buf, H_REGISTER_SIZE);
2145 regcache_raw_write (regcache, v_regnum, reg_buf);
2149 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2151 /* pseudo B registers */
2154 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2155 memcpy (reg_buf, buf, B_REGISTER_SIZE);
2156 regcache_raw_write (regcache, v_regnum, reg_buf);
2160 gdb_assert_not_reached ("regnum out of bound");
2163 /* Callback function for user_reg_add. */
2165 static struct value *
2166 value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2168 const int *reg_p = (const int *) baton;
2170 return value_of_register (*reg_p, frame);
2174 /* Implement the "software_single_step" gdbarch method, needed to
2175 single step through atomic sequences on AArch64. */
2178 aarch64_software_single_step (struct frame_info *frame)
2180 struct gdbarch *gdbarch = get_frame_arch (frame);
2181 struct address_space *aspace = get_frame_address_space (frame);
2182 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2183 const int insn_size = 4;
2184 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2185 CORE_ADDR pc = get_frame_pc (frame);
2186 CORE_ADDR breaks[2] = { -1, -1 };
2188 CORE_ADDR closing_insn = 0;
2189 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2190 byte_order_for_code);
2193 int bc_insn_count = 0; /* Conditional branch instruction count. */
2194 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2197 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2200 /* Look for a Load Exclusive instruction which begins the sequence. */
2201 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
2204 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2207 insn = read_memory_unsigned_integer (loc, insn_size,
2208 byte_order_for_code);
2210 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2212 /* Check if the instruction is a conditional branch. */
2213 if (inst.opcode->iclass == condbranch)
2215 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2217 if (bc_insn_count >= 1)
2220 /* It is, so we'll try to set a breakpoint at the destination. */
2221 breaks[1] = loc + inst.operands[0].imm.value;
2227 /* Look for the Store Exclusive which closes the atomic sequence. */
2228 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
2235 /* We didn't find a closing Store Exclusive instruction, fall back. */
2239 /* Insert breakpoint after the end of the atomic sequence. */
2240 breaks[0] = loc + insn_size;
2242 /* Check for duplicated breakpoints, and also check that the second
2243 breakpoint is not within the atomic sequence. */
2245 && (breaks[1] == breaks[0]
2246 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2247 last_breakpoint = 0;
2249 /* Insert the breakpoint at the end of the sequence, and one at the
2250 destination of the conditional branch, if it exists. */
2251 for (index = 0; index <= last_breakpoint; index++)
2252 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
2257 struct displaced_step_closure
2259 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2260 is being displaced stepping. */
2263 /* PC adjustment offset after displaced stepping. */
2267 /* Data when visiting instructions for displaced stepping. */
2269 struct aarch64_displaced_step_data
2271 struct aarch64_insn_data base;
2273 /* The address where the instruction will be executed at. */
2275 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2276 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2277 /* Number of instructions in INSN_BUF. */
2278 unsigned insn_count;
2279 /* Registers when doing displaced stepping. */
2280 struct regcache *regs;
2282 struct displaced_step_closure *dsc;
2285 /* Implementation of aarch64_insn_visitor method "b". */
2288 aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2289 struct aarch64_insn_data *data)
2291 struct aarch64_displaced_step_data *dsd
2292 = (struct aarch64_displaced_step_data *) data;
2293 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2295 if (can_encode_int32 (new_offset, 28))
2297 /* Emit B rather than BL, because executing BL on a new address
2298 will get the wrong address into LR. In order to avoid this,
2299 we emit B, and update LR if the instruction is BL. */
2300 emit_b (dsd->insn_buf, 0, new_offset);
2306 emit_nop (dsd->insn_buf);
2308 dsd->dsc->pc_adjust = offset;
2314 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2315 data->insn_addr + 4);
2319 /* Implementation of aarch64_insn_visitor method "b_cond". */
2322 aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2323 struct aarch64_insn_data *data)
2325 struct aarch64_displaced_step_data *dsd
2326 = (struct aarch64_displaced_step_data *) data;
2327 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2329 /* GDB has to fix up PC after displaced step this instruction
2330 differently according to the condition is true or false. Instead
2331 of checking COND against conditional flags, we can use
2332 the following instructions, and GDB can tell how to fix up PC
2333 according to the PC value.
2335 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2341 emit_bcond (dsd->insn_buf, cond, 8);
2343 dsd->dsc->pc_adjust = offset;
2344 dsd->insn_count = 1;
2347 /* Dynamically allocate a new register. If we know the register
2348 statically, we should make it a global as above instead of using this
2351 static struct aarch64_register
2352 aarch64_register (unsigned num, int is64)
2354 return (struct aarch64_register) { num, is64 };
2357 /* Implementation of aarch64_insn_visitor method "cb". */
2360 aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2361 const unsigned rn, int is64,
2362 struct aarch64_insn_data *data)
2364 struct aarch64_displaced_step_data *dsd
2365 = (struct aarch64_displaced_step_data *) data;
2366 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2368 /* The offset is out of range for a compare and branch
2369 instruction. We can use the following instructions instead:
2371 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2376 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2377 dsd->insn_count = 1;
2379 dsd->dsc->pc_adjust = offset;
2382 /* Implementation of aarch64_insn_visitor method "tb". */
2385 aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2386 const unsigned rt, unsigned bit,
2387 struct aarch64_insn_data *data)
2389 struct aarch64_displaced_step_data *dsd
2390 = (struct aarch64_displaced_step_data *) data;
2391 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2393 /* The offset is out of range for a test bit and branch
2394 instruction We can use the following instructions instead:
2396 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2402 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2403 dsd->insn_count = 1;
2405 dsd->dsc->pc_adjust = offset;
2408 /* Implementation of aarch64_insn_visitor method "adr". */
2411 aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2412 const int is_adrp, struct aarch64_insn_data *data)
2414 struct aarch64_displaced_step_data *dsd
2415 = (struct aarch64_displaced_step_data *) data;
2416 /* We know exactly the address the ADR{P,} instruction will compute.
2417 We can just write it to the destination register. */
2418 CORE_ADDR address = data->insn_addr + offset;
2422 /* Clear the lower 12 bits of the offset to get the 4K page. */
2423 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2427 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2430 dsd->dsc->pc_adjust = 4;
2431 emit_nop (dsd->insn_buf);
2432 dsd->insn_count = 1;
2435 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2438 aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2439 const unsigned rt, const int is64,
2440 struct aarch64_insn_data *data)
2442 struct aarch64_displaced_step_data *dsd
2443 = (struct aarch64_displaced_step_data *) data;
2444 CORE_ADDR address = data->insn_addr + offset;
2445 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2447 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2451 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2452 aarch64_register (rt, 1), zero);
2454 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2455 aarch64_register (rt, 1), zero);
2457 dsd->dsc->pc_adjust = 4;
2460 /* Implementation of aarch64_insn_visitor method "others". */
2463 aarch64_displaced_step_others (const uint32_t insn,
2464 struct aarch64_insn_data *data)
2466 struct aarch64_displaced_step_data *dsd
2467 = (struct aarch64_displaced_step_data *) data;
2469 aarch64_emit_insn (dsd->insn_buf, insn);
2470 dsd->insn_count = 1;
2472 if ((insn & 0xfffffc1f) == 0xd65f0000)
2475 dsd->dsc->pc_adjust = 0;
2478 dsd->dsc->pc_adjust = 4;
2481 static const struct aarch64_insn_visitor visitor =
2483 aarch64_displaced_step_b,
2484 aarch64_displaced_step_b_cond,
2485 aarch64_displaced_step_cb,
2486 aarch64_displaced_step_tb,
2487 aarch64_displaced_step_adr,
2488 aarch64_displaced_step_ldr_literal,
2489 aarch64_displaced_step_others,
2492 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2494 struct displaced_step_closure *
2495 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2496 CORE_ADDR from, CORE_ADDR to,
2497 struct regcache *regs)
2499 struct displaced_step_closure *dsc = NULL;
2500 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2501 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2502 struct aarch64_displaced_step_data dsd;
2504 /* Look for a Load Exclusive instruction which begins the sequence. */
2505 if (decode_masked_match (insn, 0x3fc00000, 0x08400000))
2507 /* We can't displaced step atomic sequences. */
2511 dsc = XCNEW (struct displaced_step_closure);
2512 dsd.base.insn_addr = from;
2517 aarch64_relocate_instruction (insn, &visitor,
2518 (struct aarch64_insn_data *) &dsd);
2519 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2521 if (dsd.insn_count != 0)
2525 /* Instruction can be relocated to scratch pad. Copy
2526 relocated instruction(s) there. */
2527 for (i = 0; i < dsd.insn_count; i++)
2529 if (debug_displaced)
2531 debug_printf ("displaced: writing insn ");
2532 debug_printf ("%.8x", dsd.insn_buf[i]);
2533 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2535 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2536 (ULONGEST) dsd.insn_buf[i]);
2548 /* Implement the "displaced_step_fixup" gdbarch method. */
2551 aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
2552 struct displaced_step_closure *dsc,
2553 CORE_ADDR from, CORE_ADDR to,
2554 struct regcache *regs)
2560 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2563 /* Condition is true. */
2565 else if (pc - to == 4)
2567 /* Condition is false. */
2571 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2574 if (dsc->pc_adjust != 0)
2576 if (debug_displaced)
2578 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2579 paddress (gdbarch, from), dsc->pc_adjust);
2581 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2582 from + dsc->pc_adjust);
2586 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2589 aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2590 struct displaced_step_closure *closure)
2595 /* Initialize the current architecture based on INFO. If possible,
2596 re-use an architecture from ARCHES, which is a list of
2597 architectures already created during this debugging session.
2599 Called e.g. at program startup, when reading a core file, and when
2600 reading a binary file. */
2602 static struct gdbarch *
2603 aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2605 struct gdbarch_tdep *tdep;
2606 struct gdbarch *gdbarch;
2607 struct gdbarch_list *best_arch;
2608 struct tdesc_arch_data *tdesc_data = NULL;
2609 const struct target_desc *tdesc = info.target_desc;
2611 int have_fpa_registers = 1;
2613 const struct tdesc_feature *feature;
2615 int num_pseudo_regs = 0;
2617 /* Ensure we always have a target descriptor. */
2618 if (!tdesc_has_registers (tdesc))
2619 tdesc = tdesc_aarch64;
2623 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2625 if (feature == NULL)
2628 tdesc_data = tdesc_data_alloc ();
2630 /* Validate the descriptor provides the mandatory core R registers
2631 and allocate their numbers. */
2632 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
2634 tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i,
2635 aarch64_r_register_names[i]);
2637 num_regs = AARCH64_X0_REGNUM + i;
2639 /* Look for the V registers. */
2640 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2643 /* Validate the descriptor provides the mandatory V registers
2644 and allocate their numbers. */
2645 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
2647 tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i,
2648 aarch64_v_register_names[i]);
2650 num_regs = AARCH64_V0_REGNUM + i;
2652 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
2653 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
2654 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
2655 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
2656 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
2661 tdesc_data_cleanup (tdesc_data);
2665 /* AArch64 code is always little-endian. */
2666 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
2668 /* If there is already a candidate, use it. */
2669 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2671 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2673 /* Found a match. */
2677 if (best_arch != NULL)
2679 if (tdesc_data != NULL)
2680 tdesc_data_cleanup (tdesc_data);
2681 return best_arch->gdbarch;
2684 tdep = XCNEW (struct gdbarch_tdep);
2685 gdbarch = gdbarch_alloc (&info, tdep);
2687 /* This should be low enough for everything. */
2688 tdep->lowest_pc = 0x20;
2689 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2690 tdep->jb_elt_size = 8;
2692 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
2693 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
2695 /* Frame handling. */
2696 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
2697 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
2698 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
2700 /* Advance PC across function entry code. */
2701 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
2703 /* The stack grows downward. */
2704 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2706 /* Breakpoint manipulation. */
2707 set_gdbarch_breakpoint_from_pc (gdbarch, aarch64_breakpoint_from_pc);
2708 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2709 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
2711 /* Information about registers, etc. */
2712 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
2713 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
2714 set_gdbarch_num_regs (gdbarch, num_regs);
2716 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
2717 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
2718 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
2719 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
2720 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
2721 set_tdesc_pseudo_register_reggroup_p (gdbarch,
2722 aarch64_pseudo_register_reggroup_p);
2725 set_gdbarch_short_bit (gdbarch, 16);
2726 set_gdbarch_int_bit (gdbarch, 32);
2727 set_gdbarch_float_bit (gdbarch, 32);
2728 set_gdbarch_double_bit (gdbarch, 64);
2729 set_gdbarch_long_double_bit (gdbarch, 128);
2730 set_gdbarch_long_bit (gdbarch, 64);
2731 set_gdbarch_long_long_bit (gdbarch, 64);
2732 set_gdbarch_ptr_bit (gdbarch, 64);
2733 set_gdbarch_char_signed (gdbarch, 0);
2734 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2735 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2736 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2738 /* Internal <-> external register number maps. */
2739 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
2741 /* Returning results. */
2742 set_gdbarch_return_value (gdbarch, aarch64_return_value);
2745 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
2747 /* Virtual tables. */
2748 set_gdbarch_vbit_in_delta (gdbarch, 1);
2750 /* Hook in the ABI-specific overrides, if they have been registered. */
2751 info.target_desc = tdesc;
2752 info.tdep_info = (void *) tdesc_data;
2753 gdbarch_init_osabi (info, gdbarch);
2755 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
2757 /* Add some default predicates. */
2758 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
2759 dwarf2_append_unwinders (gdbarch);
2760 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
2762 frame_base_set_default (gdbarch, &aarch64_normal_base);
2764 /* Now we have tuned the configuration, set a few final things,
2765 based on what the OS ABI has told us. */
2767 if (tdep->jb_pc >= 0)
2768 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
2770 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
2772 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2774 /* Add standard register aliases. */
2775 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
2776 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
2777 value_of_aarch64_user_reg,
2778 &aarch64_register_aliases[i].regnum);
2784 aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2786 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2791 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
2792 paddress (gdbarch, tdep->lowest_pc));
2795 /* Suppress warning from -Wmissing-prototypes. */
2796 extern initialize_file_ftype _initialize_aarch64_tdep;
2799 _initialize_aarch64_tdep (void)
2801 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
2804 initialize_tdesc_aarch64 ();
2806 /* Debug this file's internals. */
2807 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
2808 Set AArch64 debugging."), _("\
2809 Show AArch64 debugging."), _("\
2810 When on, AArch64 specific debugging is enabled."),
2813 &setdebuglist, &showdebuglist);
2816 /* AArch64 process record-replay related structures, defines etc. */
2818 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
2821 unsigned int reg_len = LENGTH; \
2824 REGS = XNEWVEC (uint32_t, reg_len); \
2825 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
2830 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
2833 unsigned int mem_len = LENGTH; \
2836 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
2837 memcpy(&MEMS->len, &RECORD_BUF[0], \
2838 sizeof(struct aarch64_mem_r) * LENGTH); \
2843 /* AArch64 record/replay structures and enumerations. */
2845 struct aarch64_mem_r
2847 uint64_t len; /* Record length. */
2848 uint64_t addr; /* Memory address. */
2851 enum aarch64_record_result
2853 AARCH64_RECORD_SUCCESS,
2854 AARCH64_RECORD_FAILURE,
2855 AARCH64_RECORD_UNSUPPORTED,
2856 AARCH64_RECORD_UNKNOWN
2859 typedef struct insn_decode_record_t
2861 struct gdbarch *gdbarch;
2862 struct regcache *regcache;
2863 CORE_ADDR this_addr; /* Address of insn to be recorded. */
2864 uint32_t aarch64_insn; /* Insn to be recorded. */
2865 uint32_t mem_rec_count; /* Count of memory records. */
2866 uint32_t reg_rec_count; /* Count of register records. */
2867 uint32_t *aarch64_regs; /* Registers to be recorded. */
2868 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
2869 } insn_decode_record;
2871 /* Record handler for data processing - register instructions. */
2874 aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
2876 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
2877 uint32_t record_buf[4];
2879 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
2880 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
2881 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
2883 if (!bit (aarch64_insn_r->aarch64_insn, 28))
2887 /* Logical (shifted register). */
2888 if (insn_bits24_27 == 0x0a)
2889 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
2891 else if (insn_bits24_27 == 0x0b)
2892 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
2894 return AARCH64_RECORD_UNKNOWN;
2896 record_buf[0] = reg_rd;
2897 aarch64_insn_r->reg_rec_count = 1;
2899 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
2903 if (insn_bits24_27 == 0x0b)
2905 /* Data-processing (3 source). */
2906 record_buf[0] = reg_rd;
2907 aarch64_insn_r->reg_rec_count = 1;
2909 else if (insn_bits24_27 == 0x0a)
2911 if (insn_bits21_23 == 0x00)
2913 /* Add/subtract (with carry). */
2914 record_buf[0] = reg_rd;
2915 aarch64_insn_r->reg_rec_count = 1;
2916 if (bit (aarch64_insn_r->aarch64_insn, 29))
2918 record_buf[1] = AARCH64_CPSR_REGNUM;
2919 aarch64_insn_r->reg_rec_count = 2;
2922 else if (insn_bits21_23 == 0x02)
2924 /* Conditional compare (register) and conditional compare
2925 (immediate) instructions. */
2926 record_buf[0] = AARCH64_CPSR_REGNUM;
2927 aarch64_insn_r->reg_rec_count = 1;
2929 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
2931 /* CConditional select. */
2932 /* Data-processing (2 source). */
2933 /* Data-processing (1 source). */
2934 record_buf[0] = reg_rd;
2935 aarch64_insn_r->reg_rec_count = 1;
2938 return AARCH64_RECORD_UNKNOWN;
2942 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
2944 return AARCH64_RECORD_SUCCESS;
2947 /* Record handler for data processing - immediate instructions. */
2950 aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
2952 uint8_t reg_rd, insn_bit28, insn_bit23, insn_bits24_27, setflags;
2953 uint32_t record_buf[4];
2955 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
2956 insn_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
2957 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
2958 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
2960 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
2961 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
2962 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
2964 record_buf[0] = reg_rd;
2965 aarch64_insn_r->reg_rec_count = 1;
2967 else if (insn_bits24_27 == 0x01)
2969 /* Add/Subtract (immediate). */
2970 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
2971 record_buf[0] = reg_rd;
2972 aarch64_insn_r->reg_rec_count = 1;
2974 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
2976 else if (insn_bits24_27 == 0x02 && !insn_bit23)
2978 /* Logical (immediate). */
2979 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
2980 record_buf[0] = reg_rd;
2981 aarch64_insn_r->reg_rec_count = 1;
2983 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
2986 return AARCH64_RECORD_UNKNOWN;
2988 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
2990 return AARCH64_RECORD_SUCCESS;
2993 /* Record handler for branch, exception generation and system instructions. */
2996 aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
2998 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
2999 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3000 uint32_t record_buf[4];
3002 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3003 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3004 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3006 if (insn_bits28_31 == 0x0d)
3008 /* Exception generation instructions. */
3009 if (insn_bits24_27 == 0x04)
3011 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3012 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3013 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
3015 ULONGEST svc_number;
3017 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3019 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3023 return AARCH64_RECORD_UNSUPPORTED;
3025 /* System instructions. */
3026 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3028 uint32_t reg_rt, reg_crn;
3030 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3031 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3033 /* Record rt in case of sysl and mrs instructions. */
3034 if (bit (aarch64_insn_r->aarch64_insn, 21))
3036 record_buf[0] = reg_rt;
3037 aarch64_insn_r->reg_rec_count = 1;
3039 /* Record cpsr for hint and msr(immediate) instructions. */
3040 else if (reg_crn == 0x02 || reg_crn == 0x04)
3042 record_buf[0] = AARCH64_CPSR_REGNUM;
3043 aarch64_insn_r->reg_rec_count = 1;
3046 /* Unconditional branch (register). */
3047 else if((insn_bits24_27 & 0x0e) == 0x06)
3049 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3050 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3051 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3054 return AARCH64_RECORD_UNKNOWN;
3056 /* Unconditional branch (immediate). */
3057 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3059 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3060 if (bit (aarch64_insn_r->aarch64_insn, 31))
3061 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3064 /* Compare & branch (immediate), Test & branch (immediate) and
3065 Conditional branch (immediate). */
3066 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3068 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3070 return AARCH64_RECORD_SUCCESS;
3073 /* Record handler for advanced SIMD load and store instructions. */
3076 aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3079 uint64_t addr_offset = 0;
3080 uint32_t record_buf[24];
3081 uint64_t record_buf_mem[24];
3082 uint32_t reg_rn, reg_rt;
3083 uint32_t reg_index = 0, mem_index = 0;
3084 uint8_t opcode_bits, size_bits;
3086 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3087 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3088 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3089 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3090 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3093 debug_printf ("Process record: Advanced SIMD load/store\n");
3095 /* Load/store single structure. */
3096 if (bit (aarch64_insn_r->aarch64_insn, 24))
3098 uint8_t sindex, scale, selem, esize, replicate = 0;
3099 scale = opcode_bits >> 2;
3100 selem = ((opcode_bits & 0x02) |
3101 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3105 if (size_bits & 0x01)
3106 return AARCH64_RECORD_UNKNOWN;
3109 if ((size_bits >> 1) & 0x01)
3110 return AARCH64_RECORD_UNKNOWN;
3111 if (size_bits & 0x01)
3113 if (!((opcode_bits >> 1) & 0x01))
3116 return AARCH64_RECORD_UNKNOWN;
3120 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3127 return AARCH64_RECORD_UNKNOWN;
3133 for (sindex = 0; sindex < selem; sindex++)
3135 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3136 reg_rt = (reg_rt + 1) % 32;
3140 for (sindex = 0; sindex < selem; sindex++)
3141 if (bit (aarch64_insn_r->aarch64_insn, 22))
3142 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3145 record_buf_mem[mem_index++] = esize / 8;
3146 record_buf_mem[mem_index++] = address + addr_offset;
3148 addr_offset = addr_offset + (esize / 8);
3149 reg_rt = (reg_rt + 1) % 32;
3152 /* Load/store multiple structure. */
3155 uint8_t selem, esize, rpt, elements;
3156 uint8_t eindex, rindex;
3158 esize = 8 << size_bits;
3159 if (bit (aarch64_insn_r->aarch64_insn, 30))
3160 elements = 128 / esize;
3162 elements = 64 / esize;
3164 switch (opcode_bits)
3166 /*LD/ST4 (4 Registers). */
3171 /*LD/ST1 (4 Registers). */
3176 /*LD/ST3 (3 Registers). */
3181 /*LD/ST1 (3 Registers). */
3186 /*LD/ST1 (1 Register). */
3191 /*LD/ST2 (2 Registers). */
3196 /*LD/ST1 (2 Registers). */
3202 return AARCH64_RECORD_UNSUPPORTED;
3205 for (rindex = 0; rindex < rpt; rindex++)
3206 for (eindex = 0; eindex < elements; eindex++)
3208 uint8_t reg_tt, sindex;
3209 reg_tt = (reg_rt + rindex) % 32;
3210 for (sindex = 0; sindex < selem; sindex++)
3212 if (bit (aarch64_insn_r->aarch64_insn, 22))
3213 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3216 record_buf_mem[mem_index++] = esize / 8;
3217 record_buf_mem[mem_index++] = address + addr_offset;
3219 addr_offset = addr_offset + (esize / 8);
3220 reg_tt = (reg_tt + 1) % 32;
3225 if (bit (aarch64_insn_r->aarch64_insn, 23))
3226 record_buf[reg_index++] = reg_rn;
3228 aarch64_insn_r->reg_rec_count = reg_index;
3229 aarch64_insn_r->mem_rec_count = mem_index / 2;
3230 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3232 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3234 return AARCH64_RECORD_SUCCESS;
3237 /* Record handler for load and store instructions. */
3240 aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3242 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3243 uint8_t insn_bit23, insn_bit21;
3244 uint8_t opc, size_bits, ld_flag, vector_flag;
3245 uint32_t reg_rn, reg_rt, reg_rt2;
3246 uint64_t datasize, offset;
3247 uint32_t record_buf[8];
3248 uint64_t record_buf_mem[8];
3251 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3252 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3253 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3254 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3255 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3256 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3257 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3258 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3259 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3260 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3261 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3263 /* Load/store exclusive. */
3264 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3267 debug_printf ("Process record: load/store exclusive\n");
3271 record_buf[0] = reg_rt;
3272 aarch64_insn_r->reg_rec_count = 1;
3275 record_buf[1] = reg_rt2;
3276 aarch64_insn_r->reg_rec_count = 2;
3282 datasize = (8 << size_bits) * 2;
3284 datasize = (8 << size_bits);
3285 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3287 record_buf_mem[0] = datasize / 8;
3288 record_buf_mem[1] = address;
3289 aarch64_insn_r->mem_rec_count = 1;
3292 /* Save register rs. */
3293 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3294 aarch64_insn_r->reg_rec_count = 1;
3298 /* Load register (literal) instructions decoding. */
3299 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3302 debug_printf ("Process record: load register (literal)\n");
3304 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3306 record_buf[0] = reg_rt;
3307 aarch64_insn_r->reg_rec_count = 1;
3309 /* All types of load/store pair instructions decoding. */
3310 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3313 debug_printf ("Process record: load/store pair\n");
3319 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3320 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3324 record_buf[0] = reg_rt;
3325 record_buf[1] = reg_rt2;
3327 aarch64_insn_r->reg_rec_count = 2;
3332 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3334 size_bits = size_bits >> 1;
3335 datasize = 8 << (2 + size_bits);
3336 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3337 offset = offset << (2 + size_bits);
3338 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3340 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3342 if (imm7_off & 0x40)
3343 address = address - offset;
3345 address = address + offset;
3348 record_buf_mem[0] = datasize / 8;
3349 record_buf_mem[1] = address;
3350 record_buf_mem[2] = datasize / 8;
3351 record_buf_mem[3] = address + (datasize / 8);
3352 aarch64_insn_r->mem_rec_count = 2;
3354 if (bit (aarch64_insn_r->aarch64_insn, 23))
3355 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3357 /* Load/store register (unsigned immediate) instructions. */
3358 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3360 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3367 if (size_bits != 0x03)
3370 return AARCH64_RECORD_UNKNOWN;
3374 debug_printf ("Process record: load/store (unsigned immediate):"
3375 " size %x V %d opc %x\n", size_bits, vector_flag,
3381 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3382 datasize = 8 << size_bits;
3383 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3385 offset = offset << size_bits;
3386 address = address + offset;
3388 record_buf_mem[0] = datasize >> 3;
3389 record_buf_mem[1] = address;
3390 aarch64_insn_r->mem_rec_count = 1;
3395 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3397 record_buf[0] = reg_rt;
3398 aarch64_insn_r->reg_rec_count = 1;
3401 /* Load/store register (register offset) instructions. */
3402 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3403 && insn_bits10_11 == 0x02 && insn_bit21)
3406 debug_printf ("Process record: load/store (register offset)\n");
3407 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3414 if (size_bits != 0x03)
3417 return AARCH64_RECORD_UNKNOWN;
3421 uint64_t reg_rm_val;
3422 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3423 bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
3424 if (bit (aarch64_insn_r->aarch64_insn, 12))
3425 offset = reg_rm_val << size_bits;
3427 offset = reg_rm_val;
3428 datasize = 8 << size_bits;
3429 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3431 address = address + offset;
3432 record_buf_mem[0] = datasize >> 3;
3433 record_buf_mem[1] = address;
3434 aarch64_insn_r->mem_rec_count = 1;
3439 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3441 record_buf[0] = reg_rt;
3442 aarch64_insn_r->reg_rec_count = 1;
3445 /* Load/store register (immediate and unprivileged) instructions. */
3446 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3451 debug_printf ("Process record: load/store "
3452 "(immediate and unprivileged)\n");
3454 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3461 if (size_bits != 0x03)
3464 return AARCH64_RECORD_UNKNOWN;
3469 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3470 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3471 datasize = 8 << size_bits;
3472 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3474 if (insn_bits10_11 != 0x01)
3476 if (imm9_off & 0x0100)
3477 address = address - offset;
3479 address = address + offset;
3481 record_buf_mem[0] = datasize >> 3;
3482 record_buf_mem[1] = address;
3483 aarch64_insn_r->mem_rec_count = 1;
3488 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3490 record_buf[0] = reg_rt;
3491 aarch64_insn_r->reg_rec_count = 1;
3493 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3494 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3496 /* Advanced SIMD load/store instructions. */
3498 return aarch64_record_asimd_load_store (aarch64_insn_r);
3500 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3502 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3504 return AARCH64_RECORD_SUCCESS;
3507 /* Record handler for data processing SIMD and floating point instructions. */
3510 aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3512 uint8_t insn_bit21, opcode, rmode, reg_rd;
3513 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3514 uint8_t insn_bits11_14;
3515 uint32_t record_buf[2];
3517 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3518 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3519 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3520 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3521 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3522 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3523 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3524 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3525 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3528 debug_printf ("Process record: data processing SIMD/FP: ");
3530 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3532 /* Floating point - fixed point conversion instructions. */
3536 debug_printf ("FP - fixed point conversion");
3538 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3539 record_buf[0] = reg_rd;
3541 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3543 /* Floating point - conditional compare instructions. */
3544 else if (insn_bits10_11 == 0x01)
3547 debug_printf ("FP - conditional compare");
3549 record_buf[0] = AARCH64_CPSR_REGNUM;
3551 /* Floating point - data processing (2-source) and
3552 conditional select instructions. */
3553 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3556 debug_printf ("FP - DP (2-source)");
3558 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3560 else if (insn_bits10_11 == 0x00)
3562 /* Floating point - immediate instructions. */
3563 if ((insn_bits12_15 & 0x01) == 0x01
3564 || (insn_bits12_15 & 0x07) == 0x04)
3567 debug_printf ("FP - immediate");
3568 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3570 /* Floating point - compare instructions. */
3571 else if ((insn_bits12_15 & 0x03) == 0x02)
3574 debug_printf ("FP - immediate");
3575 record_buf[0] = AARCH64_CPSR_REGNUM;
3577 /* Floating point - integer conversions instructions. */
3578 else if (insn_bits12_15 == 0x00)
3580 /* Convert float to integer instruction. */
3581 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3584 debug_printf ("float to int conversion");
3586 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3588 /* Convert integer to float instruction. */
3589 else if ((opcode >> 1) == 0x01 && !rmode)
3592 debug_printf ("int to float conversion");
3594 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3596 /* Move float to integer instruction. */
3597 else if ((opcode >> 1) == 0x03)
3600 debug_printf ("move float to int");
3602 if (!(opcode & 0x01))
3603 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3605 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3608 return AARCH64_RECORD_UNKNOWN;
3611 return AARCH64_RECORD_UNKNOWN;
3614 return AARCH64_RECORD_UNKNOWN;
3616 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
3619 debug_printf ("SIMD copy");
3621 /* Advanced SIMD copy instructions. */
3622 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
3623 && !bit (aarch64_insn_r->aarch64_insn, 15)
3624 && bit (aarch64_insn_r->aarch64_insn, 10))
3626 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
3627 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3629 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3632 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3634 /* All remaining floating point or advanced SIMD instructions. */
3638 debug_printf ("all remain");
3640 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3644 debug_printf ("\n");
3646 aarch64_insn_r->reg_rec_count++;
3647 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
3648 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3650 return AARCH64_RECORD_SUCCESS;
3653 /* Decodes insns type and invokes its record handler. */
3656 aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
3658 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
3660 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
3661 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
3662 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
3663 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3665 /* Data processing - immediate instructions. */
3666 if (!ins_bit26 && !ins_bit27 && ins_bit28)
3667 return aarch64_record_data_proc_imm (aarch64_insn_r);
3669 /* Branch, exception generation and system instructions. */
3670 if (ins_bit26 && !ins_bit27 && ins_bit28)
3671 return aarch64_record_branch_except_sys (aarch64_insn_r);
3673 /* Load and store instructions. */
3674 if (!ins_bit25 && ins_bit27)
3675 return aarch64_record_load_store (aarch64_insn_r);
3677 /* Data processing - register instructions. */
3678 if (ins_bit25 && !ins_bit26 && ins_bit27)
3679 return aarch64_record_data_proc_reg (aarch64_insn_r);
3681 /* Data processing - SIMD and floating point instructions. */
3682 if (ins_bit25 && ins_bit26 && ins_bit27)
3683 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
3685 return AARCH64_RECORD_UNSUPPORTED;
3688 /* Cleans up local record registers and memory allocations. */
3691 deallocate_reg_mem (insn_decode_record *record)
3693 xfree (record->aarch64_regs);
3694 xfree (record->aarch64_mems);
3697 /* Parse the current instruction and record the values of the registers and
3698 memory that will be changed in current instruction to record_arch_list
3699 return -1 if something is wrong. */
3702 aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3703 CORE_ADDR insn_addr)
3705 uint32_t rec_no = 0;
3706 uint8_t insn_size = 4;
3708 ULONGEST t_bit = 0, insn_id = 0;
3709 gdb_byte buf[insn_size];
3710 insn_decode_record aarch64_record;
3712 memset (&buf[0], 0, insn_size);
3713 memset (&aarch64_record, 0, sizeof (insn_decode_record));
3714 target_read_memory (insn_addr, &buf[0], insn_size);
3715 aarch64_record.aarch64_insn
3716 = (uint32_t) extract_unsigned_integer (&buf[0],
3718 gdbarch_byte_order (gdbarch));
3719 aarch64_record.regcache = regcache;
3720 aarch64_record.this_addr = insn_addr;
3721 aarch64_record.gdbarch = gdbarch;
3723 ret = aarch64_record_decode_insn_handler (&aarch64_record);
3724 if (ret == AARCH64_RECORD_UNSUPPORTED)
3726 printf_unfiltered (_("Process record does not support instruction "
3727 "0x%0x at address %s.\n"),
3728 aarch64_record.aarch64_insn,
3729 paddress (gdbarch, insn_addr));
3735 /* Record registers. */
3736 record_full_arch_list_add_reg (aarch64_record.regcache,
3738 /* Always record register CPSR. */
3739 record_full_arch_list_add_reg (aarch64_record.regcache,
3740 AARCH64_CPSR_REGNUM);
3741 if (aarch64_record.aarch64_regs)
3742 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
3743 if (record_full_arch_list_add_reg (aarch64_record.regcache,
3744 aarch64_record.aarch64_regs[rec_no]))
3747 /* Record memories. */
3748 if (aarch64_record.aarch64_mems)
3749 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
3750 if (record_full_arch_list_add_mem
3751 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
3752 aarch64_record.aarch64_mems[rec_no].len))
3755 if (record_full_arch_list_add_end ())
3759 deallocate_reg_mem (&aarch64_record);