1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
57 #include "arch/aarch64-insn.h"
59 #include "opcode/aarch64.h"
62 #define submask(x) ((1L << ((x) + 1)) - 1)
63 #define bit(obj,st) (((obj) >> (st)) & 1)
64 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
66 /* Pseudo register base numbers. */
67 #define AARCH64_Q0_REGNUM 0
68 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
69 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
70 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
71 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
73 /* The standard register names, and all the valid aliases for them. */
76 const char *const name;
78 } aarch64_register_aliases[] =
80 /* 64-bit register names. */
81 {"fp", AARCH64_FP_REGNUM},
82 {"lr", AARCH64_LR_REGNUM},
83 {"sp", AARCH64_SP_REGNUM},
85 /* 32-bit register names. */
86 {"w0", AARCH64_X0_REGNUM + 0},
87 {"w1", AARCH64_X0_REGNUM + 1},
88 {"w2", AARCH64_X0_REGNUM + 2},
89 {"w3", AARCH64_X0_REGNUM + 3},
90 {"w4", AARCH64_X0_REGNUM + 4},
91 {"w5", AARCH64_X0_REGNUM + 5},
92 {"w6", AARCH64_X0_REGNUM + 6},
93 {"w7", AARCH64_X0_REGNUM + 7},
94 {"w8", AARCH64_X0_REGNUM + 8},
95 {"w9", AARCH64_X0_REGNUM + 9},
96 {"w10", AARCH64_X0_REGNUM + 10},
97 {"w11", AARCH64_X0_REGNUM + 11},
98 {"w12", AARCH64_X0_REGNUM + 12},
99 {"w13", AARCH64_X0_REGNUM + 13},
100 {"w14", AARCH64_X0_REGNUM + 14},
101 {"w15", AARCH64_X0_REGNUM + 15},
102 {"w16", AARCH64_X0_REGNUM + 16},
103 {"w17", AARCH64_X0_REGNUM + 17},
104 {"w18", AARCH64_X0_REGNUM + 18},
105 {"w19", AARCH64_X0_REGNUM + 19},
106 {"w20", AARCH64_X0_REGNUM + 20},
107 {"w21", AARCH64_X0_REGNUM + 21},
108 {"w22", AARCH64_X0_REGNUM + 22},
109 {"w23", AARCH64_X0_REGNUM + 23},
110 {"w24", AARCH64_X0_REGNUM + 24},
111 {"w25", AARCH64_X0_REGNUM + 25},
112 {"w26", AARCH64_X0_REGNUM + 26},
113 {"w27", AARCH64_X0_REGNUM + 27},
114 {"w28", AARCH64_X0_REGNUM + 28},
115 {"w29", AARCH64_X0_REGNUM + 29},
116 {"w30", AARCH64_X0_REGNUM + 30},
119 {"ip0", AARCH64_X0_REGNUM + 16},
120 {"ip1", AARCH64_X0_REGNUM + 17}
123 /* The required core 'R' registers. */
124 static const char *const aarch64_r_register_names[] =
126 /* These registers must appear in consecutive RAW register number
127 order and they must begin with AARCH64_X0_REGNUM! */
128 "x0", "x1", "x2", "x3",
129 "x4", "x5", "x6", "x7",
130 "x8", "x9", "x10", "x11",
131 "x12", "x13", "x14", "x15",
132 "x16", "x17", "x18", "x19",
133 "x20", "x21", "x22", "x23",
134 "x24", "x25", "x26", "x27",
135 "x28", "x29", "x30", "sp",
139 /* The FP/SIMD 'V' registers. */
140 static const char *const aarch64_v_register_names[] =
142 /* These registers must appear in consecutive RAW register number
143 order and they must begin with AARCH64_V0_REGNUM! */
144 "v0", "v1", "v2", "v3",
145 "v4", "v5", "v6", "v7",
146 "v8", "v9", "v10", "v11",
147 "v12", "v13", "v14", "v15",
148 "v16", "v17", "v18", "v19",
149 "v20", "v21", "v22", "v23",
150 "v24", "v25", "v26", "v27",
151 "v28", "v29", "v30", "v31",
156 /* AArch64 prologue cache structure. */
157 struct aarch64_prologue_cache
159 /* The program counter at the start of the function. It is used to
160 identify this frame as a prologue frame. */
163 /* The program counter at the time this frame was created; i.e. where
164 this function was called from. It is used to identify this frame as a
168 /* The stack pointer at the time this frame was created; i.e. the
169 caller's stack pointer when this function was called. It is used
170 to identify this frame. */
173 /* Is the target available to read from? */
176 /* The frame base for this frame is just prev_sp - frame size.
177 FRAMESIZE is the distance from the frame pointer to the
178 initial stack pointer. */
181 /* The register used to hold the frame pointer for this frame. */
184 /* Saved register offsets. */
185 struct trad_frame_saved_reg *saved_regs;
189 show_aarch64_debug (struct ui_file *file, int from_tty,
190 struct cmd_list_element *c, const char *value)
192 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
197 /* Abstract instruction reader. */
199 class abstract_instruction_reader
202 /* Read in one instruction. */
203 virtual ULONGEST read (CORE_ADDR memaddr, int len,
204 enum bfd_endian byte_order) = 0;
207 /* Instruction reader from real target. */
209 class instruction_reader : public abstract_instruction_reader
212 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
215 return read_code_unsigned_integer (memaddr, len, byte_order);
221 /* Analyze a prologue, looking for a recognizable stack frame
222 and frame pointer. Scan until we encounter a store that could
223 clobber the stack frame unexpectedly, or an unknown instruction. */
226 aarch64_analyze_prologue (struct gdbarch *gdbarch,
227 CORE_ADDR start, CORE_ADDR limit,
228 struct aarch64_prologue_cache *cache,
229 abstract_instruction_reader& reader)
231 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
233 /* Track X registers and D registers in prologue. */
234 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
236 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
237 regs[i] = pv_register (i, 0);
238 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
240 for (; start < limit; start += 4)
245 insn = reader.read (start, 4, byte_order_for_code);
247 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
250 if (inst.opcode->iclass == addsub_imm
251 && (inst.opcode->op == OP_ADD
252 || strcmp ("sub", inst.opcode->name) == 0))
254 unsigned rd = inst.operands[0].reg.regno;
255 unsigned rn = inst.operands[1].reg.regno;
257 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
258 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
259 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
260 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
262 if (inst.opcode->op == OP_ADD)
264 regs[rd] = pv_add_constant (regs[rn],
265 inst.operands[2].imm.value);
269 regs[rd] = pv_add_constant (regs[rn],
270 -inst.operands[2].imm.value);
273 else if (inst.opcode->iclass == pcreladdr
274 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
276 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
277 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
279 regs[inst.operands[0].reg.regno] = pv_unknown ();
281 else if (inst.opcode->iclass == branch_imm)
283 /* Stop analysis on branch. */
286 else if (inst.opcode->iclass == condbranch)
288 /* Stop analysis on branch. */
291 else if (inst.opcode->iclass == branch_reg)
293 /* Stop analysis on branch. */
296 else if (inst.opcode->iclass == compbranch)
298 /* Stop analysis on branch. */
301 else if (inst.opcode->op == OP_MOVZ)
303 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
304 regs[inst.operands[0].reg.regno] = pv_unknown ();
306 else if (inst.opcode->iclass == log_shift
307 && strcmp (inst.opcode->name, "orr") == 0)
309 unsigned rd = inst.operands[0].reg.regno;
310 unsigned rn = inst.operands[1].reg.regno;
311 unsigned rm = inst.operands[2].reg.regno;
313 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
314 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
315 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
317 if (inst.operands[2].shifter.amount == 0
318 && rn == AARCH64_SP_REGNUM)
324 debug_printf ("aarch64: prologue analysis gave up "
325 "addr=%s opcode=0x%x (orr x register)\n",
326 core_addr_to_string_nz (start), insn);
331 else if (inst.opcode->op == OP_STUR)
333 unsigned rt = inst.operands[0].reg.regno;
334 unsigned rn = inst.operands[1].addr.base_regno;
336 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
338 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
339 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
340 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
341 gdb_assert (!inst.operands[1].addr.offset.is_reg);
343 stack.store (pv_add_constant (regs[rn],
344 inst.operands[1].addr.offset.imm),
345 is64 ? 8 : 4, regs[rt]);
347 else if ((inst.opcode->iclass == ldstpair_off
348 || (inst.opcode->iclass == ldstpair_indexed
349 && inst.operands[2].addr.preind))
350 && strcmp ("stp", inst.opcode->name) == 0)
352 /* STP with addressing mode Pre-indexed and Base register. */
355 unsigned rn = inst.operands[2].addr.base_regno;
356 int32_t imm = inst.operands[2].addr.offset.imm;
358 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
359 || inst.operands[0].type == AARCH64_OPND_Ft);
360 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
361 || inst.operands[1].type == AARCH64_OPND_Ft2);
362 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
363 gdb_assert (!inst.operands[2].addr.offset.is_reg);
365 /* If recording this store would invalidate the store area
366 (perhaps because rn is not known) then we should abandon
367 further prologue analysis. */
368 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
371 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
374 rt1 = inst.operands[0].reg.regno;
375 rt2 = inst.operands[1].reg.regno;
376 if (inst.operands[0].type == AARCH64_OPND_Ft)
378 /* Only bottom 64-bit of each V register (D register) need
380 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
381 rt1 += AARCH64_X_REGISTER_COUNT;
382 rt2 += AARCH64_X_REGISTER_COUNT;
385 stack.store (pv_add_constant (regs[rn], imm), 8,
387 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
390 if (inst.operands[2].addr.writeback)
391 regs[rn] = pv_add_constant (regs[rn], imm);
394 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
395 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
396 && (inst.opcode->op == OP_STR_POS
397 || inst.opcode->op == OP_STRF_POS)))
398 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
399 && strcmp ("str", inst.opcode->name) == 0)
401 /* STR (immediate) */
402 unsigned int rt = inst.operands[0].reg.regno;
403 int32_t imm = inst.operands[1].addr.offset.imm;
404 unsigned int rn = inst.operands[1].addr.base_regno;
406 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
407 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
408 || inst.operands[0].type == AARCH64_OPND_Ft);
410 if (inst.operands[0].type == AARCH64_OPND_Ft)
412 /* Only bottom 64-bit of each V register (D register) need
414 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
415 rt += AARCH64_X_REGISTER_COUNT;
418 stack.store (pv_add_constant (regs[rn], imm),
419 is64 ? 8 : 4, regs[rt]);
420 if (inst.operands[1].addr.writeback)
421 regs[rn] = pv_add_constant (regs[rn], imm);
423 else if (inst.opcode->iclass == testbranch)
425 /* Stop analysis on branch. */
432 debug_printf ("aarch64: prologue analysis gave up addr=%s"
434 core_addr_to_string_nz (start), insn);
443 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
445 /* Frame pointer is fp. Frame size is constant. */
446 cache->framereg = AARCH64_FP_REGNUM;
447 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
449 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
451 /* Try the stack pointer. */
452 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
453 cache->framereg = AARCH64_SP_REGNUM;
457 /* We're just out of luck. We don't know where the frame is. */
458 cache->framereg = -1;
459 cache->framesize = 0;
462 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
466 if (stack.find_reg (gdbarch, i, &offset))
467 cache->saved_regs[i].addr = offset;
470 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
472 int regnum = gdbarch_num_regs (gdbarch);
475 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
477 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
484 aarch64_analyze_prologue (struct gdbarch *gdbarch,
485 CORE_ADDR start, CORE_ADDR limit,
486 struct aarch64_prologue_cache *cache)
488 instruction_reader reader;
490 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
496 namespace selftests {
498 /* Instruction reader from manually cooked instruction sequences. */
500 class instruction_reader_test : public abstract_instruction_reader
503 template<size_t SIZE>
504 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
505 : m_insns (insns), m_insns_size (SIZE)
508 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
511 SELF_CHECK (len == 4);
512 SELF_CHECK (memaddr % 4 == 0);
513 SELF_CHECK (memaddr / 4 < m_insns_size);
515 return m_insns[memaddr / 4];
519 const uint32_t *m_insns;
524 aarch64_analyze_prologue_test (void)
526 struct gdbarch_info info;
528 gdbarch_info_init (&info);
529 info.bfd_arch_info = bfd_scan_arch ("aarch64");
531 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
532 SELF_CHECK (gdbarch != NULL);
534 /* Test the simple prologue in which frame pointer is used. */
536 struct aarch64_prologue_cache cache;
537 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
539 static const uint32_t insns[] = {
540 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
541 0x910003fd, /* mov x29, sp */
542 0x97ffffe6, /* bl 0x400580 */
544 instruction_reader_test reader (insns);
546 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
547 SELF_CHECK (end == 4 * 2);
549 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
550 SELF_CHECK (cache.framesize == 272);
552 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
554 if (i == AARCH64_FP_REGNUM)
555 SELF_CHECK (cache.saved_regs[i].addr == -272);
556 else if (i == AARCH64_LR_REGNUM)
557 SELF_CHECK (cache.saved_regs[i].addr == -264);
559 SELF_CHECK (cache.saved_regs[i].addr == -1);
562 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
564 int regnum = gdbarch_num_regs (gdbarch);
566 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
571 /* Test a prologue in which STR is used and frame pointer is not
574 struct aarch64_prologue_cache cache;
575 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
577 static const uint32_t insns[] = {
578 0xf81d0ff3, /* str x19, [sp, #-48]! */
579 0xb9002fe0, /* str w0, [sp, #44] */
580 0xf90013e1, /* str x1, [sp, #32]*/
581 0xfd000fe0, /* str d0, [sp, #24] */
582 0xaa0203f3, /* mov x19, x2 */
583 0xf94013e0, /* ldr x0, [sp, #32] */
585 instruction_reader_test reader (insns);
587 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
589 SELF_CHECK (end == 4 * 5);
591 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
592 SELF_CHECK (cache.framesize == 48);
594 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
597 SELF_CHECK (cache.saved_regs[i].addr == -16);
599 SELF_CHECK (cache.saved_regs[i].addr == -48);
601 SELF_CHECK (cache.saved_regs[i].addr == -1);
604 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
606 int regnum = gdbarch_num_regs (gdbarch);
609 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
612 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
617 } // namespace selftests
618 #endif /* GDB_SELF_TEST */
620 /* Implement the "skip_prologue" gdbarch method. */
623 aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
625 CORE_ADDR func_addr, limit_pc;
627 /* See if we can determine the end of the prologue via the symbol
628 table. If so, then return either PC, or the PC after the
629 prologue, whichever is greater. */
630 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
632 CORE_ADDR post_prologue_pc
633 = skip_prologue_using_sal (gdbarch, func_addr);
635 if (post_prologue_pc != 0)
636 return std::max (pc, post_prologue_pc);
639 /* Can't determine prologue from the symbol table, need to examine
642 /* Find an upper limit on the function prologue using the debug
643 information. If the debug information could not be used to
644 provide that bound, then use an arbitrary large number as the
646 limit_pc = skip_prologue_using_sal (gdbarch, pc);
648 limit_pc = pc + 128; /* Magic. */
650 /* Try disassembling prologue. */
651 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
654 /* Scan the function prologue for THIS_FRAME and populate the prologue
658 aarch64_scan_prologue (struct frame_info *this_frame,
659 struct aarch64_prologue_cache *cache)
661 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
662 CORE_ADDR prologue_start;
663 CORE_ADDR prologue_end;
664 CORE_ADDR prev_pc = get_frame_pc (this_frame);
665 struct gdbarch *gdbarch = get_frame_arch (this_frame);
667 cache->prev_pc = prev_pc;
669 /* Assume we do not find a frame. */
670 cache->framereg = -1;
671 cache->framesize = 0;
673 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
676 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
680 /* No line info so use the current PC. */
681 prologue_end = prev_pc;
683 else if (sal.end < prologue_end)
685 /* The next line begins after the function end. */
686 prologue_end = sal.end;
689 prologue_end = std::min (prologue_end, prev_pc);
690 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
696 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
700 cache->framereg = AARCH64_FP_REGNUM;
701 cache->framesize = 16;
702 cache->saved_regs[29].addr = 0;
703 cache->saved_regs[30].addr = 8;
707 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
708 function may throw an exception if the inferior's registers or memory is
712 aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
713 struct aarch64_prologue_cache *cache)
715 CORE_ADDR unwound_fp;
718 aarch64_scan_prologue (this_frame, cache);
720 if (cache->framereg == -1)
723 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
727 cache->prev_sp = unwound_fp + cache->framesize;
729 /* Calculate actual addresses of saved registers using offsets
730 determined by aarch64_analyze_prologue. */
731 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
732 if (trad_frame_addr_p (cache->saved_regs, reg))
733 cache->saved_regs[reg].addr += cache->prev_sp;
735 cache->func = get_frame_func (this_frame);
737 cache->available_p = 1;
740 /* Allocate and fill in *THIS_CACHE with information about the prologue of
741 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
742 Return a pointer to the current aarch64_prologue_cache in
745 static struct aarch64_prologue_cache *
746 aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
748 struct aarch64_prologue_cache *cache;
750 if (*this_cache != NULL)
751 return (struct aarch64_prologue_cache *) *this_cache;
753 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
754 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
759 aarch64_make_prologue_cache_1 (this_frame, cache);
761 CATCH (ex, RETURN_MASK_ERROR)
763 if (ex.error != NOT_AVAILABLE_ERROR)
764 throw_exception (ex);
771 /* Implement the "stop_reason" frame_unwind method. */
773 static enum unwind_stop_reason
774 aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
777 struct aarch64_prologue_cache *cache
778 = aarch64_make_prologue_cache (this_frame, this_cache);
780 if (!cache->available_p)
781 return UNWIND_UNAVAILABLE;
783 /* Halt the backtrace at "_start". */
784 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
785 return UNWIND_OUTERMOST;
787 /* We've hit a wall, stop. */
788 if (cache->prev_sp == 0)
789 return UNWIND_OUTERMOST;
791 return UNWIND_NO_REASON;
794 /* Our frame ID for a normal frame is the current function's starting
795 PC and the caller's SP when we were called. */
798 aarch64_prologue_this_id (struct frame_info *this_frame,
799 void **this_cache, struct frame_id *this_id)
801 struct aarch64_prologue_cache *cache
802 = aarch64_make_prologue_cache (this_frame, this_cache);
804 if (!cache->available_p)
805 *this_id = frame_id_build_unavailable_stack (cache->func);
807 *this_id = frame_id_build (cache->prev_sp, cache->func);
810 /* Implement the "prev_register" frame_unwind method. */
812 static struct value *
813 aarch64_prologue_prev_register (struct frame_info *this_frame,
814 void **this_cache, int prev_regnum)
816 struct aarch64_prologue_cache *cache
817 = aarch64_make_prologue_cache (this_frame, this_cache);
819 /* If we are asked to unwind the PC, then we need to return the LR
820 instead. The prologue may save PC, but it will point into this
821 frame's prologue, not the next frame's resume location. */
822 if (prev_regnum == AARCH64_PC_REGNUM)
826 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
827 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
830 /* SP is generally not saved to the stack, but this frame is
831 identified by the next frame's stack pointer at the time of the
832 call. The value was already reconstructed into PREV_SP. */
845 if (prev_regnum == AARCH64_SP_REGNUM)
846 return frame_unwind_got_constant (this_frame, prev_regnum,
849 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
853 /* AArch64 prologue unwinder. */
854 struct frame_unwind aarch64_prologue_unwind =
857 aarch64_prologue_frame_unwind_stop_reason,
858 aarch64_prologue_this_id,
859 aarch64_prologue_prev_register,
861 default_frame_sniffer
864 /* Allocate and fill in *THIS_CACHE with information about the prologue of
865 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
866 Return a pointer to the current aarch64_prologue_cache in
869 static struct aarch64_prologue_cache *
870 aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
872 struct aarch64_prologue_cache *cache;
874 if (*this_cache != NULL)
875 return (struct aarch64_prologue_cache *) *this_cache;
877 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
878 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
883 cache->prev_sp = get_frame_register_unsigned (this_frame,
885 cache->prev_pc = get_frame_pc (this_frame);
886 cache->available_p = 1;
888 CATCH (ex, RETURN_MASK_ERROR)
890 if (ex.error != NOT_AVAILABLE_ERROR)
891 throw_exception (ex);
898 /* Implement the "stop_reason" frame_unwind method. */
900 static enum unwind_stop_reason
901 aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
904 struct aarch64_prologue_cache *cache
905 = aarch64_make_stub_cache (this_frame, this_cache);
907 if (!cache->available_p)
908 return UNWIND_UNAVAILABLE;
910 return UNWIND_NO_REASON;
913 /* Our frame ID for a stub frame is the current SP and LR. */
916 aarch64_stub_this_id (struct frame_info *this_frame,
917 void **this_cache, struct frame_id *this_id)
919 struct aarch64_prologue_cache *cache
920 = aarch64_make_stub_cache (this_frame, this_cache);
922 if (cache->available_p)
923 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
925 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
928 /* Implement the "sniffer" frame_unwind method. */
931 aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
932 struct frame_info *this_frame,
933 void **this_prologue_cache)
935 CORE_ADDR addr_in_block;
938 addr_in_block = get_frame_address_in_block (this_frame);
939 if (in_plt_section (addr_in_block)
940 /* We also use the stub winder if the target memory is unreadable
941 to avoid having the prologue unwinder trying to read it. */
942 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
948 /* AArch64 stub unwinder. */
949 struct frame_unwind aarch64_stub_unwind =
952 aarch64_stub_frame_unwind_stop_reason,
953 aarch64_stub_this_id,
954 aarch64_prologue_prev_register,
956 aarch64_stub_unwind_sniffer
959 /* Return the frame base address of *THIS_FRAME. */
962 aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
964 struct aarch64_prologue_cache *cache
965 = aarch64_make_prologue_cache (this_frame, this_cache);
967 return cache->prev_sp - cache->framesize;
970 /* AArch64 default frame base information. */
971 struct frame_base aarch64_normal_base =
973 &aarch64_prologue_unwind,
974 aarch64_normal_frame_base,
975 aarch64_normal_frame_base,
976 aarch64_normal_frame_base
979 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
980 dummy frame. The frame ID's base needs to match the TOS value
981 saved by save_dummy_frame_tos () and returned from
982 aarch64_push_dummy_call, and the PC needs to match the dummy
983 frame's breakpoint. */
985 static struct frame_id
986 aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
988 return frame_id_build (get_frame_register_unsigned (this_frame,
990 get_frame_pc (this_frame));
993 /* Implement the "unwind_pc" gdbarch method. */
996 aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
999 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
1004 /* Implement the "unwind_sp" gdbarch method. */
1007 aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1009 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
1012 /* Return the value of the REGNUM register in the previous frame of
1015 static struct value *
1016 aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1017 void **this_cache, int regnum)
1023 case AARCH64_PC_REGNUM:
1024 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1025 return frame_unwind_got_constant (this_frame, regnum, lr);
1028 internal_error (__FILE__, __LINE__,
1029 _("Unexpected register %d"), regnum);
1033 /* Implement the "init_reg" dwarf2_frame_ops method. */
1036 aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1037 struct dwarf2_frame_state_reg *reg,
1038 struct frame_info *this_frame)
1042 case AARCH64_PC_REGNUM:
1043 reg->how = DWARF2_FRAME_REG_FN;
1044 reg->loc.fn = aarch64_dwarf2_prev_register;
1046 case AARCH64_SP_REGNUM:
1047 reg->how = DWARF2_FRAME_REG_CFA;
1052 /* When arguments must be pushed onto the stack, they go on in reverse
1053 order. The code below implements a FILO (stack) to do this. */
1057 /* Value to pass on stack. It can be NULL if this item is for stack
1059 const gdb_byte *data;
1061 /* Size in bytes of value to pass on stack. */
1065 DEF_VEC_O (stack_item_t);
1067 /* Return the alignment (in bytes) of the given type. */
1070 aarch64_type_align (struct type *t)
1076 t = check_typedef (t);
1077 switch (TYPE_CODE (t))
1080 /* Should never happen. */
1081 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1085 case TYPE_CODE_ENUM:
1089 case TYPE_CODE_RANGE:
1090 case TYPE_CODE_BITSTRING:
1092 case TYPE_CODE_RVALUE_REF:
1093 case TYPE_CODE_CHAR:
1094 case TYPE_CODE_BOOL:
1095 return TYPE_LENGTH (t);
1097 case TYPE_CODE_ARRAY:
1098 if (TYPE_VECTOR (t))
1100 /* Use the natural alignment for vector types (the same for
1101 scalar type), but the maximum alignment is 128-bit. */
1102 if (TYPE_LENGTH (t) > 16)
1105 return TYPE_LENGTH (t);
1108 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1109 case TYPE_CODE_COMPLEX:
1110 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1112 case TYPE_CODE_STRUCT:
1113 case TYPE_CODE_UNION:
1115 for (n = 0; n < TYPE_NFIELDS (t); n++)
1117 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
1125 /* Return 1 if *TY is a homogeneous floating-point aggregate or
1126 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
1127 document; otherwise return 0. */
1130 is_hfa_or_hva (struct type *ty)
1132 switch (TYPE_CODE (ty))
1134 case TYPE_CODE_ARRAY:
1136 struct type *target_ty = TYPE_TARGET_TYPE (ty);
1138 if (TYPE_VECTOR (ty))
1141 if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */
1142 && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */
1143 || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */
1144 && TYPE_VECTOR (target_ty))))
1149 case TYPE_CODE_UNION:
1150 case TYPE_CODE_STRUCT:
1152 /* HFA or HVA has at most four members. */
1153 if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
1155 struct type *member0_type;
1157 member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
1158 if (TYPE_CODE (member0_type) == TYPE_CODE_FLT
1159 || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY
1160 && TYPE_VECTOR (member0_type)))
1164 for (i = 0; i < TYPE_NFIELDS (ty); i++)
1166 struct type *member1_type;
1168 member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i));
1169 if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type)
1170 || (TYPE_LENGTH (member0_type)
1171 != TYPE_LENGTH (member1_type)))
1187 /* AArch64 function call information structure. */
1188 struct aarch64_call_info
1190 /* the current argument number. */
1193 /* The next general purpose register number, equivalent to NGRN as
1194 described in the AArch64 Procedure Call Standard. */
1197 /* The next SIMD and floating point register number, equivalent to
1198 NSRN as described in the AArch64 Procedure Call Standard. */
1201 /* The next stacked argument address, equivalent to NSAA as
1202 described in the AArch64 Procedure Call Standard. */
1205 /* Stack item vector. */
1206 VEC(stack_item_t) *si;
1209 /* Pass a value in a sequence of consecutive X registers. The caller
1210 is responsbile for ensuring sufficient registers are available. */
1213 pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1214 struct aarch64_call_info *info, struct type *type,
1217 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1218 int len = TYPE_LENGTH (type);
1219 enum type_code typecode = TYPE_CODE (type);
1220 int regnum = AARCH64_X0_REGNUM + info->ngrn;
1221 const bfd_byte *buf = value_contents (arg);
1227 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1228 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1232 /* Adjust sub-word struct/union args when big-endian. */
1233 if (byte_order == BFD_ENDIAN_BIG
1234 && partial_len < X_REGISTER_SIZE
1235 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1236 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1240 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1241 gdbarch_register_name (gdbarch, regnum),
1242 phex (regval, X_REGISTER_SIZE));
1244 regcache_cooked_write_unsigned (regcache, regnum, regval);
1251 /* Attempt to marshall a value in a V register. Return 1 if
1252 successful, or 0 if insufficient registers are available. This
1253 function, unlike the equivalent pass_in_x() function does not
1254 handle arguments spread across multiple registers. */
1257 pass_in_v (struct gdbarch *gdbarch,
1258 struct regcache *regcache,
1259 struct aarch64_call_info *info,
1260 int len, const bfd_byte *buf)
1264 int regnum = AARCH64_V0_REGNUM + info->nsrn;
1265 gdb_byte reg[V_REGISTER_SIZE];
1270 memset (reg, 0, sizeof (reg));
1271 /* PCS C.1, the argument is allocated to the least significant
1272 bits of V register. */
1273 memcpy (reg, buf, len);
1274 regcache->cooked_write (regnum, reg);
1278 debug_printf ("arg %d in %s\n", info->argnum,
1279 gdbarch_register_name (gdbarch, regnum));
1287 /* Marshall an argument onto the stack. */
1290 pass_on_stack (struct aarch64_call_info *info, struct type *type,
1293 const bfd_byte *buf = value_contents (arg);
1294 int len = TYPE_LENGTH (type);
1300 align = aarch64_type_align (type);
1302 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1303 Natural alignment of the argument's type. */
1304 align = align_up (align, 8);
1306 /* The AArch64 PCS requires at most doubleword alignment. */
1312 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1318 VEC_safe_push (stack_item_t, info->si, &item);
1321 if (info->nsaa & (align - 1))
1323 /* Push stack alignment padding. */
1324 int pad = align - (info->nsaa & (align - 1));
1329 VEC_safe_push (stack_item_t, info->si, &item);
1334 /* Marshall an argument into a sequence of one or more consecutive X
1335 registers or, if insufficient X registers are available then onto
1339 pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1340 struct aarch64_call_info *info, struct type *type,
1343 int len = TYPE_LENGTH (type);
1344 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1346 /* PCS C.13 - Pass in registers if we have enough spare */
1347 if (info->ngrn + nregs <= 8)
1349 pass_in_x (gdbarch, regcache, info, type, arg);
1350 info->ngrn += nregs;
1355 pass_on_stack (info, type, arg);
1359 /* Pass a value in a V register, or on the stack if insufficient are
1363 pass_in_v_or_stack (struct gdbarch *gdbarch,
1364 struct regcache *regcache,
1365 struct aarch64_call_info *info,
1369 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type),
1370 value_contents (arg)))
1371 pass_on_stack (info, type, arg);
1374 /* Implement the "push_dummy_call" gdbarch method. */
1377 aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1378 struct regcache *regcache, CORE_ADDR bp_addr,
1380 struct value **args, CORE_ADDR sp, int struct_return,
1381 CORE_ADDR struct_addr)
1384 struct aarch64_call_info info;
1385 struct type *func_type;
1386 struct type *return_type;
1387 int lang_struct_return;
1389 memset (&info, 0, sizeof (info));
1391 /* We need to know what the type of the called function is in order
1392 to determine the number of named/anonymous arguments for the
1393 actual argument placement, and the return type in order to handle
1394 return value correctly.
1396 The generic code above us views the decision of return in memory
1397 or return in registers as a two stage processes. The language
1398 handler is consulted first and may decide to return in memory (eg
1399 class with copy constructor returned by value), this will cause
1400 the generic code to allocate space AND insert an initial leading
1403 If the language code does not decide to pass in memory then the
1404 target code is consulted.
1406 If the language code decides to pass in memory we want to move
1407 the pointer inserted as the initial argument from the argument
1408 list and into X8, the conventional AArch64 struct return pointer
1411 This is slightly awkward, ideally the flag "lang_struct_return"
1412 would be passed to the targets implementation of push_dummy_call.
1413 Rather that change the target interface we call the language code
1414 directly ourselves. */
1416 func_type = check_typedef (value_type (function));
1418 /* Dereference function pointer types. */
1419 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1420 func_type = TYPE_TARGET_TYPE (func_type);
1422 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1423 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1425 /* If language_pass_by_reference () returned true we will have been
1426 given an additional initial argument, a hidden pointer to the
1427 return slot in memory. */
1428 return_type = TYPE_TARGET_TYPE (func_type);
1429 lang_struct_return = language_pass_by_reference (return_type);
1431 /* Set the return address. For the AArch64, the return breakpoint
1432 is always at BP_ADDR. */
1433 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1435 /* If we were given an initial argument for the return slot because
1436 lang_struct_return was true, lose it. */
1437 if (lang_struct_return)
1443 /* The struct_return pointer occupies X8. */
1444 if (struct_return || lang_struct_return)
1448 debug_printf ("struct return in %s = 0x%s\n",
1449 gdbarch_register_name (gdbarch,
1450 AARCH64_STRUCT_RETURN_REGNUM),
1451 paddress (gdbarch, struct_addr));
1453 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1457 for (argnum = 0; argnum < nargs; argnum++)
1459 struct value *arg = args[argnum];
1460 struct type *arg_type;
1463 arg_type = check_typedef (value_type (arg));
1464 len = TYPE_LENGTH (arg_type);
1466 switch (TYPE_CODE (arg_type))
1469 case TYPE_CODE_BOOL:
1470 case TYPE_CODE_CHAR:
1471 case TYPE_CODE_RANGE:
1472 case TYPE_CODE_ENUM:
1475 /* Promote to 32 bit integer. */
1476 if (TYPE_UNSIGNED (arg_type))
1477 arg_type = builtin_type (gdbarch)->builtin_uint32;
1479 arg_type = builtin_type (gdbarch)->builtin_int32;
1480 arg = value_cast (arg_type, arg);
1482 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1485 case TYPE_CODE_COMPLEX:
1488 const bfd_byte *buf = value_contents (arg);
1489 struct type *target_type =
1490 check_typedef (TYPE_TARGET_TYPE (arg_type));
1492 pass_in_v (gdbarch, regcache, &info,
1493 TYPE_LENGTH (target_type), buf);
1494 pass_in_v (gdbarch, regcache, &info,
1495 TYPE_LENGTH (target_type),
1496 buf + TYPE_LENGTH (target_type));
1501 pass_on_stack (&info, arg_type, arg);
1505 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1508 case TYPE_CODE_STRUCT:
1509 case TYPE_CODE_ARRAY:
1510 case TYPE_CODE_UNION:
1511 if (is_hfa_or_hva (arg_type))
1513 int elements = TYPE_NFIELDS (arg_type);
1515 /* Homogeneous Aggregates */
1516 if (info.nsrn + elements < 8)
1520 for (i = 0; i < elements; i++)
1522 /* We know that we have sufficient registers
1523 available therefore this will never fallback
1525 struct value *field =
1526 value_primitive_field (arg, 0, i, arg_type);
1527 struct type *field_type =
1528 check_typedef (value_type (field));
1530 pass_in_v_or_stack (gdbarch, regcache, &info,
1537 pass_on_stack (&info, arg_type, arg);
1540 else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
1541 && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
1543 /* Short vector types are passed in V registers. */
1544 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1548 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1549 invisible reference. */
1551 /* Allocate aligned storage. */
1552 sp = align_down (sp - len, 16);
1554 /* Write the real data into the stack. */
1555 write_memory (sp, value_contents (arg), len);
1557 /* Construct the indirection. */
1558 arg_type = lookup_pointer_type (arg_type);
1559 arg = value_from_pointer (arg_type, sp);
1560 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1563 /* PCS C.15 / C.18 multiple values pass. */
1564 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1568 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1573 /* Make sure stack retains 16 byte alignment. */
1575 sp -= 16 - (info.nsaa & 15);
1577 while (!VEC_empty (stack_item_t, info.si))
1579 stack_item_t *si = VEC_last (stack_item_t, info.si);
1582 if (si->data != NULL)
1583 write_memory (sp, si->data, si->len);
1584 VEC_pop (stack_item_t, info.si);
1587 VEC_free (stack_item_t, info.si);
1589 /* Finally, update the SP register. */
1590 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1595 /* Implement the "frame_align" gdbarch method. */
1598 aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1600 /* Align the stack to sixteen bytes. */
1601 return sp & ~(CORE_ADDR) 15;
1604 /* Return the type for an AdvSISD Q register. */
1606 static struct type *
1607 aarch64_vnq_type (struct gdbarch *gdbarch)
1609 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1611 if (tdep->vnq_type == NULL)
1616 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1619 elem = builtin_type (gdbarch)->builtin_uint128;
1620 append_composite_type_field (t, "u", elem);
1622 elem = builtin_type (gdbarch)->builtin_int128;
1623 append_composite_type_field (t, "s", elem);
1628 return tdep->vnq_type;
1631 /* Return the type for an AdvSISD D register. */
1633 static struct type *
1634 aarch64_vnd_type (struct gdbarch *gdbarch)
1636 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1638 if (tdep->vnd_type == NULL)
1643 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1646 elem = builtin_type (gdbarch)->builtin_double;
1647 append_composite_type_field (t, "f", elem);
1649 elem = builtin_type (gdbarch)->builtin_uint64;
1650 append_composite_type_field (t, "u", elem);
1652 elem = builtin_type (gdbarch)->builtin_int64;
1653 append_composite_type_field (t, "s", elem);
1658 return tdep->vnd_type;
1661 /* Return the type for an AdvSISD S register. */
1663 static struct type *
1664 aarch64_vns_type (struct gdbarch *gdbarch)
1666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1668 if (tdep->vns_type == NULL)
1673 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1676 elem = builtin_type (gdbarch)->builtin_float;
1677 append_composite_type_field (t, "f", elem);
1679 elem = builtin_type (gdbarch)->builtin_uint32;
1680 append_composite_type_field (t, "u", elem);
1682 elem = builtin_type (gdbarch)->builtin_int32;
1683 append_composite_type_field (t, "s", elem);
1688 return tdep->vns_type;
1691 /* Return the type for an AdvSISD H register. */
1693 static struct type *
1694 aarch64_vnh_type (struct gdbarch *gdbarch)
1696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1698 if (tdep->vnh_type == NULL)
1703 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1706 elem = builtin_type (gdbarch)->builtin_uint16;
1707 append_composite_type_field (t, "u", elem);
1709 elem = builtin_type (gdbarch)->builtin_int16;
1710 append_composite_type_field (t, "s", elem);
1715 return tdep->vnh_type;
1718 /* Return the type for an AdvSISD B register. */
1720 static struct type *
1721 aarch64_vnb_type (struct gdbarch *gdbarch)
1723 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1725 if (tdep->vnb_type == NULL)
1730 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1733 elem = builtin_type (gdbarch)->builtin_uint8;
1734 append_composite_type_field (t, "u", elem);
1736 elem = builtin_type (gdbarch)->builtin_int8;
1737 append_composite_type_field (t, "s", elem);
1742 return tdep->vnb_type;
1745 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1748 aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1750 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1751 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1753 if (reg == AARCH64_DWARF_SP)
1754 return AARCH64_SP_REGNUM;
1756 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1757 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1763 /* Implement the "print_insn" gdbarch method. */
1766 aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1768 info->symbols = NULL;
1769 return default_print_insn (memaddr, info);
1772 /* AArch64 BRK software debug mode instruction.
1773 Note that AArch64 code is always little-endian.
1774 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1775 constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
1777 typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
1779 /* Extract from an array REGS containing the (raw) register state a
1780 function return value of type TYPE, and copy that, in virtual
1781 format, into VALBUF. */
1784 aarch64_extract_return_value (struct type *type, struct regcache *regs,
1787 struct gdbarch *gdbarch = regs->arch ();
1788 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1790 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1792 bfd_byte buf[V_REGISTER_SIZE];
1793 int len = TYPE_LENGTH (type);
1795 regs->cooked_read (AARCH64_V0_REGNUM, buf);
1796 memcpy (valbuf, buf, len);
1798 else if (TYPE_CODE (type) == TYPE_CODE_INT
1799 || TYPE_CODE (type) == TYPE_CODE_CHAR
1800 || TYPE_CODE (type) == TYPE_CODE_BOOL
1801 || TYPE_CODE (type) == TYPE_CODE_PTR
1802 || TYPE_IS_REFERENCE (type)
1803 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1805 /* If the the type is a plain integer, then the access is
1806 straight-forward. Otherwise we have to play around a bit
1808 int len = TYPE_LENGTH (type);
1809 int regno = AARCH64_X0_REGNUM;
1814 /* By using store_unsigned_integer we avoid having to do
1815 anything special for small big-endian values. */
1816 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1817 store_unsigned_integer (valbuf,
1818 (len > X_REGISTER_SIZE
1819 ? X_REGISTER_SIZE : len), byte_order, tmp);
1820 len -= X_REGISTER_SIZE;
1821 valbuf += X_REGISTER_SIZE;
1824 else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX)
1826 int regno = AARCH64_V0_REGNUM;
1827 bfd_byte buf[V_REGISTER_SIZE];
1828 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1829 int len = TYPE_LENGTH (target_type);
1831 regs->cooked_read (regno, buf);
1832 memcpy (valbuf, buf, len);
1834 regs->cooked_read (regno + 1, buf);
1835 memcpy (valbuf, buf, len);
1838 else if (is_hfa_or_hva (type))
1840 int elements = TYPE_NFIELDS (type);
1841 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1842 int len = TYPE_LENGTH (member_type);
1845 for (i = 0; i < elements; i++)
1847 int regno = AARCH64_V0_REGNUM + i;
1848 bfd_byte buf[V_REGISTER_SIZE];
1852 debug_printf ("read HFA or HVA return value element %d from %s\n",
1854 gdbarch_register_name (gdbarch, regno));
1856 regs->cooked_read (regno, buf);
1858 memcpy (valbuf, buf, len);
1862 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1863 && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
1865 /* Short vector is returned in V register. */
1866 gdb_byte buf[V_REGISTER_SIZE];
1868 regs->cooked_read (AARCH64_V0_REGNUM, buf);
1869 memcpy (valbuf, buf, TYPE_LENGTH (type));
1873 /* For a structure or union the behaviour is as if the value had
1874 been stored to word-aligned memory and then loaded into
1875 registers with 64-bit load instruction(s). */
1876 int len = TYPE_LENGTH (type);
1877 int regno = AARCH64_X0_REGNUM;
1878 bfd_byte buf[X_REGISTER_SIZE];
1882 regs->cooked_read (regno++, buf);
1883 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1884 len -= X_REGISTER_SIZE;
1885 valbuf += X_REGISTER_SIZE;
1891 /* Will a function return an aggregate type in memory or in a
1892 register? Return 0 if an aggregate type can be returned in a
1893 register, 1 if it must be returned in memory. */
1896 aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1898 type = check_typedef (type);
1900 if (is_hfa_or_hva (type))
1902 /* v0-v7 are used to return values and one register is allocated
1903 for one member. However, HFA or HVA has at most four members. */
1907 if (TYPE_LENGTH (type) > 16)
1909 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1910 invisible reference. */
1918 /* Write into appropriate registers a function return value of type
1919 TYPE, given in virtual format. */
1922 aarch64_store_return_value (struct type *type, struct regcache *regs,
1923 const gdb_byte *valbuf)
1925 struct gdbarch *gdbarch = regs->arch ();
1926 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1928 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1930 bfd_byte buf[V_REGISTER_SIZE];
1931 int len = TYPE_LENGTH (type);
1933 memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
1934 regs->cooked_write (AARCH64_V0_REGNUM, buf);
1936 else if (TYPE_CODE (type) == TYPE_CODE_INT
1937 || TYPE_CODE (type) == TYPE_CODE_CHAR
1938 || TYPE_CODE (type) == TYPE_CODE_BOOL
1939 || TYPE_CODE (type) == TYPE_CODE_PTR
1940 || TYPE_IS_REFERENCE (type)
1941 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1943 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
1945 /* Values of one word or less are zero/sign-extended and
1947 bfd_byte tmpbuf[X_REGISTER_SIZE];
1948 LONGEST val = unpack_long (type, valbuf);
1950 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
1951 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
1955 /* Integral values greater than one word are stored in
1956 consecutive registers starting with r0. This will always
1957 be a multiple of the regiser size. */
1958 int len = TYPE_LENGTH (type);
1959 int regno = AARCH64_X0_REGNUM;
1963 regs->cooked_write (regno++, valbuf);
1964 len -= X_REGISTER_SIZE;
1965 valbuf += X_REGISTER_SIZE;
1969 else if (is_hfa_or_hva (type))
1971 int elements = TYPE_NFIELDS (type);
1972 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1973 int len = TYPE_LENGTH (member_type);
1976 for (i = 0; i < elements; i++)
1978 int regno = AARCH64_V0_REGNUM + i;
1979 bfd_byte tmpbuf[V_REGISTER_SIZE];
1983 debug_printf ("write HFA or HVA return value element %d to %s\n",
1985 gdbarch_register_name (gdbarch, regno));
1988 memcpy (tmpbuf, valbuf, len);
1989 regs->cooked_write (regno, tmpbuf);
1993 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1994 && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
1997 gdb_byte buf[V_REGISTER_SIZE];
1999 memcpy (buf, valbuf, TYPE_LENGTH (type));
2000 regs->cooked_write (AARCH64_V0_REGNUM, buf);
2004 /* For a structure or union the behaviour is as if the value had
2005 been stored to word-aligned memory and then loaded into
2006 registers with 64-bit load instruction(s). */
2007 int len = TYPE_LENGTH (type);
2008 int regno = AARCH64_X0_REGNUM;
2009 bfd_byte tmpbuf[X_REGISTER_SIZE];
2013 memcpy (tmpbuf, valbuf,
2014 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2015 regs->cooked_write (regno++, tmpbuf);
2016 len -= X_REGISTER_SIZE;
2017 valbuf += X_REGISTER_SIZE;
2022 /* Implement the "return_value" gdbarch method. */
2024 static enum return_value_convention
2025 aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2026 struct type *valtype, struct regcache *regcache,
2027 gdb_byte *readbuf, const gdb_byte *writebuf)
2030 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2031 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2032 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2034 if (aarch64_return_in_memory (gdbarch, valtype))
2037 debug_printf ("return value in memory\n");
2038 return RETURN_VALUE_STRUCT_CONVENTION;
2043 aarch64_store_return_value (valtype, regcache, writebuf);
2046 aarch64_extract_return_value (valtype, regcache, readbuf);
2049 debug_printf ("return value in registers\n");
2051 return RETURN_VALUE_REGISTER_CONVENTION;
2054 /* Implement the "get_longjmp_target" gdbarch method. */
2057 aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2060 gdb_byte buf[X_REGISTER_SIZE];
2061 struct gdbarch *gdbarch = get_frame_arch (frame);
2062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2063 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2065 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2067 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2071 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2075 /* Implement the "gen_return_address" gdbarch method. */
2078 aarch64_gen_return_address (struct gdbarch *gdbarch,
2079 struct agent_expr *ax, struct axs_value *value,
2082 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2083 value->kind = axs_lvalue_register;
2084 value->u.reg = AARCH64_LR_REGNUM;
2088 /* Return the pseudo register name corresponding to register regnum. */
2091 aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2093 static const char *const q_name[] =
2095 "q0", "q1", "q2", "q3",
2096 "q4", "q5", "q6", "q7",
2097 "q8", "q9", "q10", "q11",
2098 "q12", "q13", "q14", "q15",
2099 "q16", "q17", "q18", "q19",
2100 "q20", "q21", "q22", "q23",
2101 "q24", "q25", "q26", "q27",
2102 "q28", "q29", "q30", "q31",
2105 static const char *const d_name[] =
2107 "d0", "d1", "d2", "d3",
2108 "d4", "d5", "d6", "d7",
2109 "d8", "d9", "d10", "d11",
2110 "d12", "d13", "d14", "d15",
2111 "d16", "d17", "d18", "d19",
2112 "d20", "d21", "d22", "d23",
2113 "d24", "d25", "d26", "d27",
2114 "d28", "d29", "d30", "d31",
2117 static const char *const s_name[] =
2119 "s0", "s1", "s2", "s3",
2120 "s4", "s5", "s6", "s7",
2121 "s8", "s9", "s10", "s11",
2122 "s12", "s13", "s14", "s15",
2123 "s16", "s17", "s18", "s19",
2124 "s20", "s21", "s22", "s23",
2125 "s24", "s25", "s26", "s27",
2126 "s28", "s29", "s30", "s31",
2129 static const char *const h_name[] =
2131 "h0", "h1", "h2", "h3",
2132 "h4", "h5", "h6", "h7",
2133 "h8", "h9", "h10", "h11",
2134 "h12", "h13", "h14", "h15",
2135 "h16", "h17", "h18", "h19",
2136 "h20", "h21", "h22", "h23",
2137 "h24", "h25", "h26", "h27",
2138 "h28", "h29", "h30", "h31",
2141 static const char *const b_name[] =
2143 "b0", "b1", "b2", "b3",
2144 "b4", "b5", "b6", "b7",
2145 "b8", "b9", "b10", "b11",
2146 "b12", "b13", "b14", "b15",
2147 "b16", "b17", "b18", "b19",
2148 "b20", "b21", "b22", "b23",
2149 "b24", "b25", "b26", "b27",
2150 "b28", "b29", "b30", "b31",
2153 regnum -= gdbarch_num_regs (gdbarch);
2155 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2156 return q_name[regnum - AARCH64_Q0_REGNUM];
2158 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2159 return d_name[regnum - AARCH64_D0_REGNUM];
2161 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2162 return s_name[regnum - AARCH64_S0_REGNUM];
2164 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2165 return h_name[regnum - AARCH64_H0_REGNUM];
2167 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2168 return b_name[regnum - AARCH64_B0_REGNUM];
2170 internal_error (__FILE__, __LINE__,
2171 _("aarch64_pseudo_register_name: bad register number %d"),
2175 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2177 static struct type *
2178 aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2180 regnum -= gdbarch_num_regs (gdbarch);
2182 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2183 return aarch64_vnq_type (gdbarch);
2185 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2186 return aarch64_vnd_type (gdbarch);
2188 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2189 return aarch64_vns_type (gdbarch);
2191 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2192 return aarch64_vnh_type (gdbarch);
2194 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2195 return aarch64_vnb_type (gdbarch);
2197 internal_error (__FILE__, __LINE__,
2198 _("aarch64_pseudo_register_type: bad register number %d"),
2202 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2205 aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2206 struct reggroup *group)
2208 regnum -= gdbarch_num_regs (gdbarch);
2210 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2211 return group == all_reggroup || group == vector_reggroup;
2212 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2213 return (group == all_reggroup || group == vector_reggroup
2214 || group == float_reggroup);
2215 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2216 return (group == all_reggroup || group == vector_reggroup
2217 || group == float_reggroup);
2218 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2219 return group == all_reggroup || group == vector_reggroup;
2220 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2221 return group == all_reggroup || group == vector_reggroup;
2223 return group == all_reggroup;
2226 /* Implement the "pseudo_register_read_value" gdbarch method. */
2228 static struct value *
2229 aarch64_pseudo_read_value (struct gdbarch *gdbarch,
2230 readable_regcache *regcache,
2233 gdb_byte reg_buf[V_REGISTER_SIZE];
2234 struct value *result_value;
2237 result_value = allocate_value (register_type (gdbarch, regnum));
2238 VALUE_LVAL (result_value) = lval_register;
2239 VALUE_REGNUM (result_value) = regnum;
2240 buf = value_contents_raw (result_value);
2242 regnum -= gdbarch_num_regs (gdbarch);
2244 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2246 enum register_status status;
2249 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2250 status = regcache->raw_read (v_regnum, reg_buf);
2251 if (status != REG_VALID)
2252 mark_value_bytes_unavailable (result_value, 0,
2253 TYPE_LENGTH (value_type (result_value)));
2255 memcpy (buf, reg_buf, Q_REGISTER_SIZE);
2256 return result_value;
2259 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2261 enum register_status status;
2264 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2265 status = regcache->raw_read (v_regnum, reg_buf);
2266 if (status != REG_VALID)
2267 mark_value_bytes_unavailable (result_value, 0,
2268 TYPE_LENGTH (value_type (result_value)));
2270 memcpy (buf, reg_buf, D_REGISTER_SIZE);
2271 return result_value;
2274 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2276 enum register_status status;
2279 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2280 status = regcache->raw_read (v_regnum, reg_buf);
2281 if (status != REG_VALID)
2282 mark_value_bytes_unavailable (result_value, 0,
2283 TYPE_LENGTH (value_type (result_value)));
2285 memcpy (buf, reg_buf, S_REGISTER_SIZE);
2286 return result_value;
2289 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2291 enum register_status status;
2294 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2295 status = regcache->raw_read (v_regnum, reg_buf);
2296 if (status != REG_VALID)
2297 mark_value_bytes_unavailable (result_value, 0,
2298 TYPE_LENGTH (value_type (result_value)));
2300 memcpy (buf, reg_buf, H_REGISTER_SIZE);
2301 return result_value;
2304 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2306 enum register_status status;
2309 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2310 status = regcache->raw_read (v_regnum, reg_buf);
2311 if (status != REG_VALID)
2312 mark_value_bytes_unavailable (result_value, 0,
2313 TYPE_LENGTH (value_type (result_value)));
2315 memcpy (buf, reg_buf, B_REGISTER_SIZE);
2316 return result_value;
2319 gdb_assert_not_reached ("regnum out of bound");
2322 /* Implement the "pseudo_register_write" gdbarch method. */
2325 aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2326 int regnum, const gdb_byte *buf)
2328 gdb_byte reg_buf[V_REGISTER_SIZE];
2330 /* Ensure the register buffer is zero, we want gdb writes of the
2331 various 'scalar' pseudo registers to behavior like architectural
2332 writes, register width bytes are written the remainder are set to
2334 memset (reg_buf, 0, sizeof (reg_buf));
2336 regnum -= gdbarch_num_regs (gdbarch);
2338 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2340 /* pseudo Q registers */
2343 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2344 memcpy (reg_buf, buf, Q_REGISTER_SIZE);
2345 regcache->raw_write (v_regnum, reg_buf);
2349 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2351 /* pseudo D registers */
2354 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2355 memcpy (reg_buf, buf, D_REGISTER_SIZE);
2356 regcache->raw_write (v_regnum, reg_buf);
2360 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2364 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2365 memcpy (reg_buf, buf, S_REGISTER_SIZE);
2366 regcache->raw_write (v_regnum, reg_buf);
2370 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2372 /* pseudo H registers */
2375 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2376 memcpy (reg_buf, buf, H_REGISTER_SIZE);
2377 regcache->raw_write (v_regnum, reg_buf);
2381 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2383 /* pseudo B registers */
2386 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2387 memcpy (reg_buf, buf, B_REGISTER_SIZE);
2388 regcache->raw_write (v_regnum, reg_buf);
2392 gdb_assert_not_reached ("regnum out of bound");
2395 /* Callback function for user_reg_add. */
2397 static struct value *
2398 value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2400 const int *reg_p = (const int *) baton;
2402 return value_of_register (*reg_p, frame);
2406 /* Implement the "software_single_step" gdbarch method, needed to
2407 single step through atomic sequences on AArch64. */
2409 static std::vector<CORE_ADDR>
2410 aarch64_software_single_step (struct regcache *regcache)
2412 struct gdbarch *gdbarch = regcache->arch ();
2413 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2414 const int insn_size = 4;
2415 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2416 CORE_ADDR pc = regcache_read_pc (regcache);
2417 CORE_ADDR breaks[2] = { -1, -1 };
2419 CORE_ADDR closing_insn = 0;
2420 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2421 byte_order_for_code);
2424 int bc_insn_count = 0; /* Conditional branch instruction count. */
2425 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2428 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2431 /* Look for a Load Exclusive instruction which begins the sequence. */
2432 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
2435 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2438 insn = read_memory_unsigned_integer (loc, insn_size,
2439 byte_order_for_code);
2441 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2443 /* Check if the instruction is a conditional branch. */
2444 if (inst.opcode->iclass == condbranch)
2446 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2448 if (bc_insn_count >= 1)
2451 /* It is, so we'll try to set a breakpoint at the destination. */
2452 breaks[1] = loc + inst.operands[0].imm.value;
2458 /* Look for the Store Exclusive which closes the atomic sequence. */
2459 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
2466 /* We didn't find a closing Store Exclusive instruction, fall back. */
2470 /* Insert breakpoint after the end of the atomic sequence. */
2471 breaks[0] = loc + insn_size;
2473 /* Check for duplicated breakpoints, and also check that the second
2474 breakpoint is not within the atomic sequence. */
2476 && (breaks[1] == breaks[0]
2477 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2478 last_breakpoint = 0;
2480 std::vector<CORE_ADDR> next_pcs;
2482 /* Insert the breakpoint at the end of the sequence, and one at the
2483 destination of the conditional branch, if it exists. */
2484 for (index = 0; index <= last_breakpoint; index++)
2485 next_pcs.push_back (breaks[index]);
2490 struct aarch64_displaced_step_closure : public displaced_step_closure
2492 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2493 is being displaced stepping. */
2496 /* PC adjustment offset after displaced stepping. */
2497 int32_t pc_adjust = 0;
2500 /* Data when visiting instructions for displaced stepping. */
2502 struct aarch64_displaced_step_data
2504 struct aarch64_insn_data base;
2506 /* The address where the instruction will be executed at. */
2508 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2509 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2510 /* Number of instructions in INSN_BUF. */
2511 unsigned insn_count;
2512 /* Registers when doing displaced stepping. */
2513 struct regcache *regs;
2515 aarch64_displaced_step_closure *dsc;
2518 /* Implementation of aarch64_insn_visitor method "b". */
2521 aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2522 struct aarch64_insn_data *data)
2524 struct aarch64_displaced_step_data *dsd
2525 = (struct aarch64_displaced_step_data *) data;
2526 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
2528 if (can_encode_int32 (new_offset, 28))
2530 /* Emit B rather than BL, because executing BL on a new address
2531 will get the wrong address into LR. In order to avoid this,
2532 we emit B, and update LR if the instruction is BL. */
2533 emit_b (dsd->insn_buf, 0, new_offset);
2539 emit_nop (dsd->insn_buf);
2541 dsd->dsc->pc_adjust = offset;
2547 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2548 data->insn_addr + 4);
2552 /* Implementation of aarch64_insn_visitor method "b_cond". */
2555 aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2556 struct aarch64_insn_data *data)
2558 struct aarch64_displaced_step_data *dsd
2559 = (struct aarch64_displaced_step_data *) data;
2561 /* GDB has to fix up PC after displaced step this instruction
2562 differently according to the condition is true or false. Instead
2563 of checking COND against conditional flags, we can use
2564 the following instructions, and GDB can tell how to fix up PC
2565 according to the PC value.
2567 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2573 emit_bcond (dsd->insn_buf, cond, 8);
2575 dsd->dsc->pc_adjust = offset;
2576 dsd->insn_count = 1;
2579 /* Dynamically allocate a new register. If we know the register
2580 statically, we should make it a global as above instead of using this
2583 static struct aarch64_register
2584 aarch64_register (unsigned num, int is64)
2586 return (struct aarch64_register) { num, is64 };
2589 /* Implementation of aarch64_insn_visitor method "cb". */
2592 aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2593 const unsigned rn, int is64,
2594 struct aarch64_insn_data *data)
2596 struct aarch64_displaced_step_data *dsd
2597 = (struct aarch64_displaced_step_data *) data;
2599 /* The offset is out of range for a compare and branch
2600 instruction. We can use the following instructions instead:
2602 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2607 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2608 dsd->insn_count = 1;
2610 dsd->dsc->pc_adjust = offset;
2613 /* Implementation of aarch64_insn_visitor method "tb". */
2616 aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2617 const unsigned rt, unsigned bit,
2618 struct aarch64_insn_data *data)
2620 struct aarch64_displaced_step_data *dsd
2621 = (struct aarch64_displaced_step_data *) data;
2623 /* The offset is out of range for a test bit and branch
2624 instruction We can use the following instructions instead:
2626 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2632 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2633 dsd->insn_count = 1;
2635 dsd->dsc->pc_adjust = offset;
2638 /* Implementation of aarch64_insn_visitor method "adr". */
2641 aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2642 const int is_adrp, struct aarch64_insn_data *data)
2644 struct aarch64_displaced_step_data *dsd
2645 = (struct aarch64_displaced_step_data *) data;
2646 /* We know exactly the address the ADR{P,} instruction will compute.
2647 We can just write it to the destination register. */
2648 CORE_ADDR address = data->insn_addr + offset;
2652 /* Clear the lower 12 bits of the offset to get the 4K page. */
2653 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2657 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2660 dsd->dsc->pc_adjust = 4;
2661 emit_nop (dsd->insn_buf);
2662 dsd->insn_count = 1;
2665 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2668 aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2669 const unsigned rt, const int is64,
2670 struct aarch64_insn_data *data)
2672 struct aarch64_displaced_step_data *dsd
2673 = (struct aarch64_displaced_step_data *) data;
2674 CORE_ADDR address = data->insn_addr + offset;
2675 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2677 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2681 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2682 aarch64_register (rt, 1), zero);
2684 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2685 aarch64_register (rt, 1), zero);
2687 dsd->dsc->pc_adjust = 4;
2690 /* Implementation of aarch64_insn_visitor method "others". */
2693 aarch64_displaced_step_others (const uint32_t insn,
2694 struct aarch64_insn_data *data)
2696 struct aarch64_displaced_step_data *dsd
2697 = (struct aarch64_displaced_step_data *) data;
2699 aarch64_emit_insn (dsd->insn_buf, insn);
2700 dsd->insn_count = 1;
2702 if ((insn & 0xfffffc1f) == 0xd65f0000)
2705 dsd->dsc->pc_adjust = 0;
2708 dsd->dsc->pc_adjust = 4;
2711 static const struct aarch64_insn_visitor visitor =
2713 aarch64_displaced_step_b,
2714 aarch64_displaced_step_b_cond,
2715 aarch64_displaced_step_cb,
2716 aarch64_displaced_step_tb,
2717 aarch64_displaced_step_adr,
2718 aarch64_displaced_step_ldr_literal,
2719 aarch64_displaced_step_others,
2722 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2724 struct displaced_step_closure *
2725 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2726 CORE_ADDR from, CORE_ADDR to,
2727 struct regcache *regs)
2729 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2730 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2731 struct aarch64_displaced_step_data dsd;
2734 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2737 /* Look for a Load Exclusive instruction which begins the sequence. */
2738 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
2740 /* We can't displaced step atomic sequences. */
2744 std::unique_ptr<aarch64_displaced_step_closure> dsc
2745 (new aarch64_displaced_step_closure);
2746 dsd.base.insn_addr = from;
2749 dsd.dsc = dsc.get ();
2751 aarch64_relocate_instruction (insn, &visitor,
2752 (struct aarch64_insn_data *) &dsd);
2753 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2755 if (dsd.insn_count != 0)
2759 /* Instruction can be relocated to scratch pad. Copy
2760 relocated instruction(s) there. */
2761 for (i = 0; i < dsd.insn_count; i++)
2763 if (debug_displaced)
2765 debug_printf ("displaced: writing insn ");
2766 debug_printf ("%.8x", dsd.insn_buf[i]);
2767 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2769 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2770 (ULONGEST) dsd.insn_buf[i]);
2778 return dsc.release ();
2781 /* Implement the "displaced_step_fixup" gdbarch method. */
2784 aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
2785 struct displaced_step_closure *dsc_,
2786 CORE_ADDR from, CORE_ADDR to,
2787 struct regcache *regs)
2789 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
2795 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2798 /* Condition is true. */
2800 else if (pc - to == 4)
2802 /* Condition is false. */
2806 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2809 if (dsc->pc_adjust != 0)
2811 if (debug_displaced)
2813 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2814 paddress (gdbarch, from), dsc->pc_adjust);
2816 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2817 from + dsc->pc_adjust);
2821 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2824 aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2825 struct displaced_step_closure *closure)
2830 /* Get the correct target description. */
2833 aarch64_read_description ()
2835 static target_desc *aarch64_tdesc = NULL;
2836 target_desc **tdesc = &aarch64_tdesc;
2839 *tdesc = aarch64_create_target_description ();
2844 /* Initialize the current architecture based on INFO. If possible,
2845 re-use an architecture from ARCHES, which is a list of
2846 architectures already created during this debugging session.
2848 Called e.g. at program startup, when reading a core file, and when
2849 reading a binary file. */
2851 static struct gdbarch *
2852 aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2854 struct gdbarch_tdep *tdep;
2855 struct gdbarch *gdbarch;
2856 struct gdbarch_list *best_arch;
2857 struct tdesc_arch_data *tdesc_data = NULL;
2858 const struct target_desc *tdesc = info.target_desc;
2861 const struct tdesc_feature *feature;
2863 int num_pseudo_regs = 0;
2865 /* Ensure we always have a target descriptor. */
2866 if (!tdesc_has_registers (tdesc))
2867 tdesc = aarch64_read_description ();
2871 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2873 if (feature == NULL)
2876 tdesc_data = tdesc_data_alloc ();
2878 /* Validate the descriptor provides the mandatory core R registers
2879 and allocate their numbers. */
2880 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
2882 tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i,
2883 aarch64_r_register_names[i]);
2885 num_regs = AARCH64_X0_REGNUM + i;
2887 /* Look for the V registers. */
2888 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2891 /* Validate the descriptor provides the mandatory V registers
2892 and allocate their numbers. */
2893 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
2895 tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i,
2896 aarch64_v_register_names[i]);
2898 num_regs = AARCH64_V0_REGNUM + i;
2900 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
2901 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
2902 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
2903 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
2904 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
2909 tdesc_data_cleanup (tdesc_data);
2913 /* AArch64 code is always little-endian. */
2914 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
2916 /* If there is already a candidate, use it. */
2917 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2919 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2921 /* Found a match. */
2925 if (best_arch != NULL)
2927 if (tdesc_data != NULL)
2928 tdesc_data_cleanup (tdesc_data);
2929 return best_arch->gdbarch;
2932 tdep = XCNEW (struct gdbarch_tdep);
2933 gdbarch = gdbarch_alloc (&info, tdep);
2935 /* This should be low enough for everything. */
2936 tdep->lowest_pc = 0x20;
2937 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2938 tdep->jb_elt_size = 8;
2940 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
2941 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
2943 /* Frame handling. */
2944 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
2945 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
2946 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
2948 /* Advance PC across function entry code. */
2949 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
2951 /* The stack grows downward. */
2952 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2954 /* Breakpoint manipulation. */
2955 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2956 aarch64_breakpoint::kind_from_pc);
2957 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2958 aarch64_breakpoint::bp_from_kind);
2959 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2960 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
2962 /* Information about registers, etc. */
2963 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
2964 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
2965 set_gdbarch_num_regs (gdbarch, num_regs);
2967 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
2968 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
2969 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
2970 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
2971 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
2972 set_tdesc_pseudo_register_reggroup_p (gdbarch,
2973 aarch64_pseudo_register_reggroup_p);
2976 set_gdbarch_short_bit (gdbarch, 16);
2977 set_gdbarch_int_bit (gdbarch, 32);
2978 set_gdbarch_float_bit (gdbarch, 32);
2979 set_gdbarch_double_bit (gdbarch, 64);
2980 set_gdbarch_long_double_bit (gdbarch, 128);
2981 set_gdbarch_long_bit (gdbarch, 64);
2982 set_gdbarch_long_long_bit (gdbarch, 64);
2983 set_gdbarch_ptr_bit (gdbarch, 64);
2984 set_gdbarch_char_signed (gdbarch, 0);
2985 set_gdbarch_wchar_signed (gdbarch, 0);
2986 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2987 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2988 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2990 /* Internal <-> external register number maps. */
2991 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
2993 /* Returning results. */
2994 set_gdbarch_return_value (gdbarch, aarch64_return_value);
2997 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
2999 /* Virtual tables. */
3000 set_gdbarch_vbit_in_delta (gdbarch, 1);
3002 /* Hook in the ABI-specific overrides, if they have been registered. */
3003 info.target_desc = tdesc;
3004 info.tdesc_data = tdesc_data;
3005 gdbarch_init_osabi (info, gdbarch);
3007 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3009 /* Add some default predicates. */
3010 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3011 dwarf2_append_unwinders (gdbarch);
3012 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3014 frame_base_set_default (gdbarch, &aarch64_normal_base);
3016 /* Now we have tuned the configuration, set a few final things,
3017 based on what the OS ABI has told us. */
3019 if (tdep->jb_pc >= 0)
3020 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3022 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3024 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3026 /* Add standard register aliases. */
3027 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3028 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3029 value_of_aarch64_user_reg,
3030 &aarch64_register_aliases[i].regnum);
3036 aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3038 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3043 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3044 paddress (gdbarch, tdep->lowest_pc));
3050 static void aarch64_process_record_test (void);
3055 _initialize_aarch64_tdep (void)
3057 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3060 /* Debug this file's internals. */
3061 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3062 Set AArch64 debugging."), _("\
3063 Show AArch64 debugging."), _("\
3064 When on, AArch64 specific debugging is enabled."),
3067 &setdebuglist, &showdebuglist);
3070 selftests::register_test ("aarch64-analyze-prologue",
3071 selftests::aarch64_analyze_prologue_test);
3072 selftests::register_test ("aarch64-process-record",
3073 selftests::aarch64_process_record_test);
3074 selftests::record_xml_tdesc ("aarch64.xml",
3075 aarch64_create_target_description ());
3079 /* AArch64 process record-replay related structures, defines etc. */
3081 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3084 unsigned int reg_len = LENGTH; \
3087 REGS = XNEWVEC (uint32_t, reg_len); \
3088 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3093 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3096 unsigned int mem_len = LENGTH; \
3099 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3100 memcpy(&MEMS->len, &RECORD_BUF[0], \
3101 sizeof(struct aarch64_mem_r) * LENGTH); \
3106 /* AArch64 record/replay structures and enumerations. */
3108 struct aarch64_mem_r
3110 uint64_t len; /* Record length. */
3111 uint64_t addr; /* Memory address. */
3114 enum aarch64_record_result
3116 AARCH64_RECORD_SUCCESS,
3117 AARCH64_RECORD_UNSUPPORTED,
3118 AARCH64_RECORD_UNKNOWN
3121 typedef struct insn_decode_record_t
3123 struct gdbarch *gdbarch;
3124 struct regcache *regcache;
3125 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3126 uint32_t aarch64_insn; /* Insn to be recorded. */
3127 uint32_t mem_rec_count; /* Count of memory records. */
3128 uint32_t reg_rec_count; /* Count of register records. */
3129 uint32_t *aarch64_regs; /* Registers to be recorded. */
3130 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3131 } insn_decode_record;
3133 /* Record handler for data processing - register instructions. */
3136 aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3138 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3139 uint32_t record_buf[4];
3141 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3142 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3143 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3145 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3149 /* Logical (shifted register). */
3150 if (insn_bits24_27 == 0x0a)
3151 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3153 else if (insn_bits24_27 == 0x0b)
3154 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3156 return AARCH64_RECORD_UNKNOWN;
3158 record_buf[0] = reg_rd;
3159 aarch64_insn_r->reg_rec_count = 1;
3161 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3165 if (insn_bits24_27 == 0x0b)
3167 /* Data-processing (3 source). */
3168 record_buf[0] = reg_rd;
3169 aarch64_insn_r->reg_rec_count = 1;
3171 else if (insn_bits24_27 == 0x0a)
3173 if (insn_bits21_23 == 0x00)
3175 /* Add/subtract (with carry). */
3176 record_buf[0] = reg_rd;
3177 aarch64_insn_r->reg_rec_count = 1;
3178 if (bit (aarch64_insn_r->aarch64_insn, 29))
3180 record_buf[1] = AARCH64_CPSR_REGNUM;
3181 aarch64_insn_r->reg_rec_count = 2;
3184 else if (insn_bits21_23 == 0x02)
3186 /* Conditional compare (register) and conditional compare
3187 (immediate) instructions. */
3188 record_buf[0] = AARCH64_CPSR_REGNUM;
3189 aarch64_insn_r->reg_rec_count = 1;
3191 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3193 /* CConditional select. */
3194 /* Data-processing (2 source). */
3195 /* Data-processing (1 source). */
3196 record_buf[0] = reg_rd;
3197 aarch64_insn_r->reg_rec_count = 1;
3200 return AARCH64_RECORD_UNKNOWN;
3204 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3206 return AARCH64_RECORD_SUCCESS;
3209 /* Record handler for data processing - immediate instructions. */
3212 aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3214 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
3215 uint32_t record_buf[4];
3217 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3218 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3219 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3221 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3222 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3223 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3225 record_buf[0] = reg_rd;
3226 aarch64_insn_r->reg_rec_count = 1;
3228 else if (insn_bits24_27 == 0x01)
3230 /* Add/Subtract (immediate). */
3231 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3232 record_buf[0] = reg_rd;
3233 aarch64_insn_r->reg_rec_count = 1;
3235 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3237 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3239 /* Logical (immediate). */
3240 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3241 record_buf[0] = reg_rd;
3242 aarch64_insn_r->reg_rec_count = 1;
3244 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3247 return AARCH64_RECORD_UNKNOWN;
3249 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3251 return AARCH64_RECORD_SUCCESS;
3254 /* Record handler for branch, exception generation and system instructions. */
3257 aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3259 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3260 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3261 uint32_t record_buf[4];
3263 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3264 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3265 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3267 if (insn_bits28_31 == 0x0d)
3269 /* Exception generation instructions. */
3270 if (insn_bits24_27 == 0x04)
3272 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3273 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3274 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
3276 ULONGEST svc_number;
3278 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3280 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3284 return AARCH64_RECORD_UNSUPPORTED;
3286 /* System instructions. */
3287 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3289 uint32_t reg_rt, reg_crn;
3291 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3292 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3294 /* Record rt in case of sysl and mrs instructions. */
3295 if (bit (aarch64_insn_r->aarch64_insn, 21))
3297 record_buf[0] = reg_rt;
3298 aarch64_insn_r->reg_rec_count = 1;
3300 /* Record cpsr for hint and msr(immediate) instructions. */
3301 else if (reg_crn == 0x02 || reg_crn == 0x04)
3303 record_buf[0] = AARCH64_CPSR_REGNUM;
3304 aarch64_insn_r->reg_rec_count = 1;
3307 /* Unconditional branch (register). */
3308 else if((insn_bits24_27 & 0x0e) == 0x06)
3310 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3311 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3312 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3315 return AARCH64_RECORD_UNKNOWN;
3317 /* Unconditional branch (immediate). */
3318 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3320 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3321 if (bit (aarch64_insn_r->aarch64_insn, 31))
3322 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3325 /* Compare & branch (immediate), Test & branch (immediate) and
3326 Conditional branch (immediate). */
3327 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3329 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3331 return AARCH64_RECORD_SUCCESS;
3334 /* Record handler for advanced SIMD load and store instructions. */
3337 aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3340 uint64_t addr_offset = 0;
3341 uint32_t record_buf[24];
3342 uint64_t record_buf_mem[24];
3343 uint32_t reg_rn, reg_rt;
3344 uint32_t reg_index = 0, mem_index = 0;
3345 uint8_t opcode_bits, size_bits;
3347 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3348 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3349 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3350 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3351 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3354 debug_printf ("Process record: Advanced SIMD load/store\n");
3356 /* Load/store single structure. */
3357 if (bit (aarch64_insn_r->aarch64_insn, 24))
3359 uint8_t sindex, scale, selem, esize, replicate = 0;
3360 scale = opcode_bits >> 2;
3361 selem = ((opcode_bits & 0x02) |
3362 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3366 if (size_bits & 0x01)
3367 return AARCH64_RECORD_UNKNOWN;
3370 if ((size_bits >> 1) & 0x01)
3371 return AARCH64_RECORD_UNKNOWN;
3372 if (size_bits & 0x01)
3374 if (!((opcode_bits >> 1) & 0x01))
3377 return AARCH64_RECORD_UNKNOWN;
3381 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3388 return AARCH64_RECORD_UNKNOWN;
3394 for (sindex = 0; sindex < selem; sindex++)
3396 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3397 reg_rt = (reg_rt + 1) % 32;
3401 for (sindex = 0; sindex < selem; sindex++)
3403 if (bit (aarch64_insn_r->aarch64_insn, 22))
3404 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3407 record_buf_mem[mem_index++] = esize / 8;
3408 record_buf_mem[mem_index++] = address + addr_offset;
3410 addr_offset = addr_offset + (esize / 8);
3411 reg_rt = (reg_rt + 1) % 32;
3415 /* Load/store multiple structure. */
3418 uint8_t selem, esize, rpt, elements;
3419 uint8_t eindex, rindex;
3421 esize = 8 << size_bits;
3422 if (bit (aarch64_insn_r->aarch64_insn, 30))
3423 elements = 128 / esize;
3425 elements = 64 / esize;
3427 switch (opcode_bits)
3429 /*LD/ST4 (4 Registers). */
3434 /*LD/ST1 (4 Registers). */
3439 /*LD/ST3 (3 Registers). */
3444 /*LD/ST1 (3 Registers). */
3449 /*LD/ST1 (1 Register). */
3454 /*LD/ST2 (2 Registers). */
3459 /*LD/ST1 (2 Registers). */
3465 return AARCH64_RECORD_UNSUPPORTED;
3468 for (rindex = 0; rindex < rpt; rindex++)
3469 for (eindex = 0; eindex < elements; eindex++)
3471 uint8_t reg_tt, sindex;
3472 reg_tt = (reg_rt + rindex) % 32;
3473 for (sindex = 0; sindex < selem; sindex++)
3475 if (bit (aarch64_insn_r->aarch64_insn, 22))
3476 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3479 record_buf_mem[mem_index++] = esize / 8;
3480 record_buf_mem[mem_index++] = address + addr_offset;
3482 addr_offset = addr_offset + (esize / 8);
3483 reg_tt = (reg_tt + 1) % 32;
3488 if (bit (aarch64_insn_r->aarch64_insn, 23))
3489 record_buf[reg_index++] = reg_rn;
3491 aarch64_insn_r->reg_rec_count = reg_index;
3492 aarch64_insn_r->mem_rec_count = mem_index / 2;
3493 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3495 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3497 return AARCH64_RECORD_SUCCESS;
3500 /* Record handler for load and store instructions. */
3503 aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3505 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3506 uint8_t insn_bit23, insn_bit21;
3507 uint8_t opc, size_bits, ld_flag, vector_flag;
3508 uint32_t reg_rn, reg_rt, reg_rt2;
3509 uint64_t datasize, offset;
3510 uint32_t record_buf[8];
3511 uint64_t record_buf_mem[8];
3514 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3515 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3516 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3517 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3518 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3519 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3520 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3521 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3522 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3523 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3524 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3526 /* Load/store exclusive. */
3527 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3530 debug_printf ("Process record: load/store exclusive\n");
3534 record_buf[0] = reg_rt;
3535 aarch64_insn_r->reg_rec_count = 1;
3538 record_buf[1] = reg_rt2;
3539 aarch64_insn_r->reg_rec_count = 2;
3545 datasize = (8 << size_bits) * 2;
3547 datasize = (8 << size_bits);
3548 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3550 record_buf_mem[0] = datasize / 8;
3551 record_buf_mem[1] = address;
3552 aarch64_insn_r->mem_rec_count = 1;
3555 /* Save register rs. */
3556 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3557 aarch64_insn_r->reg_rec_count = 1;
3561 /* Load register (literal) instructions decoding. */
3562 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3565 debug_printf ("Process record: load register (literal)\n");
3567 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3569 record_buf[0] = reg_rt;
3570 aarch64_insn_r->reg_rec_count = 1;
3572 /* All types of load/store pair instructions decoding. */
3573 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3576 debug_printf ("Process record: load/store pair\n");
3582 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3583 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3587 record_buf[0] = reg_rt;
3588 record_buf[1] = reg_rt2;
3590 aarch64_insn_r->reg_rec_count = 2;
3595 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3597 size_bits = size_bits >> 1;
3598 datasize = 8 << (2 + size_bits);
3599 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3600 offset = offset << (2 + size_bits);
3601 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3603 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3605 if (imm7_off & 0x40)
3606 address = address - offset;
3608 address = address + offset;
3611 record_buf_mem[0] = datasize / 8;
3612 record_buf_mem[1] = address;
3613 record_buf_mem[2] = datasize / 8;
3614 record_buf_mem[3] = address + (datasize / 8);
3615 aarch64_insn_r->mem_rec_count = 2;
3617 if (bit (aarch64_insn_r->aarch64_insn, 23))
3618 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3620 /* Load/store register (unsigned immediate) instructions. */
3621 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3623 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3633 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3635 /* PRFM (immediate) */
3636 return AARCH64_RECORD_SUCCESS;
3638 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3640 /* LDRSW (immediate) */
3654 debug_printf ("Process record: load/store (unsigned immediate):"
3655 " size %x V %d opc %x\n", size_bits, vector_flag,
3661 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3662 datasize = 8 << size_bits;
3663 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3665 offset = offset << size_bits;
3666 address = address + offset;
3668 record_buf_mem[0] = datasize >> 3;
3669 record_buf_mem[1] = address;
3670 aarch64_insn_r->mem_rec_count = 1;
3675 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3677 record_buf[0] = reg_rt;
3678 aarch64_insn_r->reg_rec_count = 1;
3681 /* Load/store register (register offset) instructions. */
3682 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3683 && insn_bits10_11 == 0x02 && insn_bit21)
3686 debug_printf ("Process record: load/store (register offset)\n");
3687 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3694 if (size_bits != 0x03)
3697 return AARCH64_RECORD_UNKNOWN;
3701 ULONGEST reg_rm_val;
3703 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3704 bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
3705 if (bit (aarch64_insn_r->aarch64_insn, 12))
3706 offset = reg_rm_val << size_bits;
3708 offset = reg_rm_val;
3709 datasize = 8 << size_bits;
3710 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3712 address = address + offset;
3713 record_buf_mem[0] = datasize >> 3;
3714 record_buf_mem[1] = address;
3715 aarch64_insn_r->mem_rec_count = 1;
3720 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3722 record_buf[0] = reg_rt;
3723 aarch64_insn_r->reg_rec_count = 1;
3726 /* Load/store register (immediate and unprivileged) instructions. */
3727 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3732 debug_printf ("Process record: load/store "
3733 "(immediate and unprivileged)\n");
3735 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3742 if (size_bits != 0x03)
3745 return AARCH64_RECORD_UNKNOWN;
3750 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3751 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3752 datasize = 8 << size_bits;
3753 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3755 if (insn_bits10_11 != 0x01)
3757 if (imm9_off & 0x0100)
3758 address = address - offset;
3760 address = address + offset;
3762 record_buf_mem[0] = datasize >> 3;
3763 record_buf_mem[1] = address;
3764 aarch64_insn_r->mem_rec_count = 1;
3769 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3771 record_buf[0] = reg_rt;
3772 aarch64_insn_r->reg_rec_count = 1;
3774 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3775 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3777 /* Advanced SIMD load/store instructions. */
3779 return aarch64_record_asimd_load_store (aarch64_insn_r);
3781 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3783 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3785 return AARCH64_RECORD_SUCCESS;
3788 /* Record handler for data processing SIMD and floating point instructions. */
3791 aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3793 uint8_t insn_bit21, opcode, rmode, reg_rd;
3794 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3795 uint8_t insn_bits11_14;
3796 uint32_t record_buf[2];
3798 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3799 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3800 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3801 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3802 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3803 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3804 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3805 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3806 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3809 debug_printf ("Process record: data processing SIMD/FP: ");
3811 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3813 /* Floating point - fixed point conversion instructions. */
3817 debug_printf ("FP - fixed point conversion");
3819 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3820 record_buf[0] = reg_rd;
3822 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3824 /* Floating point - conditional compare instructions. */
3825 else if (insn_bits10_11 == 0x01)
3828 debug_printf ("FP - conditional compare");
3830 record_buf[0] = AARCH64_CPSR_REGNUM;
3832 /* Floating point - data processing (2-source) and
3833 conditional select instructions. */
3834 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3837 debug_printf ("FP - DP (2-source)");
3839 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3841 else if (insn_bits10_11 == 0x00)
3843 /* Floating point - immediate instructions. */
3844 if ((insn_bits12_15 & 0x01) == 0x01
3845 || (insn_bits12_15 & 0x07) == 0x04)
3848 debug_printf ("FP - immediate");
3849 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3851 /* Floating point - compare instructions. */
3852 else if ((insn_bits12_15 & 0x03) == 0x02)
3855 debug_printf ("FP - immediate");
3856 record_buf[0] = AARCH64_CPSR_REGNUM;
3858 /* Floating point - integer conversions instructions. */
3859 else if (insn_bits12_15 == 0x00)
3861 /* Convert float to integer instruction. */
3862 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3865 debug_printf ("float to int conversion");
3867 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3869 /* Convert integer to float instruction. */
3870 else if ((opcode >> 1) == 0x01 && !rmode)
3873 debug_printf ("int to float conversion");
3875 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3877 /* Move float to integer instruction. */
3878 else if ((opcode >> 1) == 0x03)
3881 debug_printf ("move float to int");
3883 if (!(opcode & 0x01))
3884 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3886 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3889 return AARCH64_RECORD_UNKNOWN;
3892 return AARCH64_RECORD_UNKNOWN;
3895 return AARCH64_RECORD_UNKNOWN;
3897 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
3900 debug_printf ("SIMD copy");
3902 /* Advanced SIMD copy instructions. */
3903 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
3904 && !bit (aarch64_insn_r->aarch64_insn, 15)
3905 && bit (aarch64_insn_r->aarch64_insn, 10))
3907 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
3908 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3910 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3913 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3915 /* All remaining floating point or advanced SIMD instructions. */
3919 debug_printf ("all remain");
3921 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3925 debug_printf ("\n");
3927 aarch64_insn_r->reg_rec_count++;
3928 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
3929 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3931 return AARCH64_RECORD_SUCCESS;
3934 /* Decodes insns type and invokes its record handler. */
3937 aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
3939 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
3941 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
3942 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
3943 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
3944 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3946 /* Data processing - immediate instructions. */
3947 if (!ins_bit26 && !ins_bit27 && ins_bit28)
3948 return aarch64_record_data_proc_imm (aarch64_insn_r);
3950 /* Branch, exception generation and system instructions. */
3951 if (ins_bit26 && !ins_bit27 && ins_bit28)
3952 return aarch64_record_branch_except_sys (aarch64_insn_r);
3954 /* Load and store instructions. */
3955 if (!ins_bit25 && ins_bit27)
3956 return aarch64_record_load_store (aarch64_insn_r);
3958 /* Data processing - register instructions. */
3959 if (ins_bit25 && !ins_bit26 && ins_bit27)
3960 return aarch64_record_data_proc_reg (aarch64_insn_r);
3962 /* Data processing - SIMD and floating point instructions. */
3963 if (ins_bit25 && ins_bit26 && ins_bit27)
3964 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
3966 return AARCH64_RECORD_UNSUPPORTED;
3969 /* Cleans up local record registers and memory allocations. */
3972 deallocate_reg_mem (insn_decode_record *record)
3974 xfree (record->aarch64_regs);
3975 xfree (record->aarch64_mems);
3979 namespace selftests {
3982 aarch64_process_record_test (void)
3984 struct gdbarch_info info;
3987 gdbarch_info_init (&info);
3988 info.bfd_arch_info = bfd_scan_arch ("aarch64");
3990 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
3991 SELF_CHECK (gdbarch != NULL);
3993 insn_decode_record aarch64_record;
3995 memset (&aarch64_record, 0, sizeof (insn_decode_record));
3996 aarch64_record.regcache = NULL;
3997 aarch64_record.this_addr = 0;
3998 aarch64_record.gdbarch = gdbarch;
4000 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4001 aarch64_record.aarch64_insn = 0xf9800020;
4002 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4003 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4004 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4005 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4007 deallocate_reg_mem (&aarch64_record);
4010 } // namespace selftests
4011 #endif /* GDB_SELF_TEST */
4013 /* Parse the current instruction and record the values of the registers and
4014 memory that will be changed in current instruction to record_arch_list
4015 return -1 if something is wrong. */
4018 aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4019 CORE_ADDR insn_addr)
4021 uint32_t rec_no = 0;
4022 uint8_t insn_size = 4;
4024 gdb_byte buf[insn_size];
4025 insn_decode_record aarch64_record;
4027 memset (&buf[0], 0, insn_size);
4028 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4029 target_read_memory (insn_addr, &buf[0], insn_size);
4030 aarch64_record.aarch64_insn
4031 = (uint32_t) extract_unsigned_integer (&buf[0],
4033 gdbarch_byte_order (gdbarch));
4034 aarch64_record.regcache = regcache;
4035 aarch64_record.this_addr = insn_addr;
4036 aarch64_record.gdbarch = gdbarch;
4038 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4039 if (ret == AARCH64_RECORD_UNSUPPORTED)
4041 printf_unfiltered (_("Process record does not support instruction "
4042 "0x%0x at address %s.\n"),
4043 aarch64_record.aarch64_insn,
4044 paddress (gdbarch, insn_addr));
4050 /* Record registers. */
4051 record_full_arch_list_add_reg (aarch64_record.regcache,
4053 /* Always record register CPSR. */
4054 record_full_arch_list_add_reg (aarch64_record.regcache,
4055 AARCH64_CPSR_REGNUM);
4056 if (aarch64_record.aarch64_regs)
4057 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4058 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4059 aarch64_record.aarch64_regs[rec_no]))
4062 /* Record memories. */
4063 if (aarch64_record.aarch64_mems)
4064 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4065 if (record_full_arch_list_add_mem
4066 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4067 aarch64_record.aarch64_mems[rec_no].len))
4070 if (record_full_arch_list_add_end ())
4074 deallocate_reg_mem (&aarch64_record);