1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
32 #include "arch-utils.h"
34 #include "frame-unwind.h"
35 #include "frame-base.h"
36 #include "trad-frame.h"
38 #include "dwarf2-frame.h"
40 #include "prologue-value.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
58 #include "features/aarch64.c"
60 #include "arch/aarch64-insn.h"
62 #include "opcode/aarch64.h"
64 #define submask(x) ((1L << ((x) + 1)) - 1)
65 #define bit(obj,st) (((obj) >> (st)) & 1)
66 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
68 /* Pseudo register base numbers. */
69 #define AARCH64_Q0_REGNUM 0
70 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
71 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
72 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
73 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
75 /* The standard register names, and all the valid aliases for them. */
78 const char *const name;
80 } aarch64_register_aliases[] =
82 /* 64-bit register names. */
83 {"fp", AARCH64_FP_REGNUM},
84 {"lr", AARCH64_LR_REGNUM},
85 {"sp", AARCH64_SP_REGNUM},
87 /* 32-bit register names. */
88 {"w0", AARCH64_X0_REGNUM + 0},
89 {"w1", AARCH64_X0_REGNUM + 1},
90 {"w2", AARCH64_X0_REGNUM + 2},
91 {"w3", AARCH64_X0_REGNUM + 3},
92 {"w4", AARCH64_X0_REGNUM + 4},
93 {"w5", AARCH64_X0_REGNUM + 5},
94 {"w6", AARCH64_X0_REGNUM + 6},
95 {"w7", AARCH64_X0_REGNUM + 7},
96 {"w8", AARCH64_X0_REGNUM + 8},
97 {"w9", AARCH64_X0_REGNUM + 9},
98 {"w10", AARCH64_X0_REGNUM + 10},
99 {"w11", AARCH64_X0_REGNUM + 11},
100 {"w12", AARCH64_X0_REGNUM + 12},
101 {"w13", AARCH64_X0_REGNUM + 13},
102 {"w14", AARCH64_X0_REGNUM + 14},
103 {"w15", AARCH64_X0_REGNUM + 15},
104 {"w16", AARCH64_X0_REGNUM + 16},
105 {"w17", AARCH64_X0_REGNUM + 17},
106 {"w18", AARCH64_X0_REGNUM + 18},
107 {"w19", AARCH64_X0_REGNUM + 19},
108 {"w20", AARCH64_X0_REGNUM + 20},
109 {"w21", AARCH64_X0_REGNUM + 21},
110 {"w22", AARCH64_X0_REGNUM + 22},
111 {"w23", AARCH64_X0_REGNUM + 23},
112 {"w24", AARCH64_X0_REGNUM + 24},
113 {"w25", AARCH64_X0_REGNUM + 25},
114 {"w26", AARCH64_X0_REGNUM + 26},
115 {"w27", AARCH64_X0_REGNUM + 27},
116 {"w28", AARCH64_X0_REGNUM + 28},
117 {"w29", AARCH64_X0_REGNUM + 29},
118 {"w30", AARCH64_X0_REGNUM + 30},
121 {"ip0", AARCH64_X0_REGNUM + 16},
122 {"ip1", AARCH64_X0_REGNUM + 17}
125 /* The required core 'R' registers. */
126 static const char *const aarch64_r_register_names[] =
128 /* These registers must appear in consecutive RAW register number
129 order and they must begin with AARCH64_X0_REGNUM! */
130 "x0", "x1", "x2", "x3",
131 "x4", "x5", "x6", "x7",
132 "x8", "x9", "x10", "x11",
133 "x12", "x13", "x14", "x15",
134 "x16", "x17", "x18", "x19",
135 "x20", "x21", "x22", "x23",
136 "x24", "x25", "x26", "x27",
137 "x28", "x29", "x30", "sp",
141 /* The FP/SIMD 'V' registers. */
142 static const char *const aarch64_v_register_names[] =
144 /* These registers must appear in consecutive RAW register number
145 order and they must begin with AARCH64_V0_REGNUM! */
146 "v0", "v1", "v2", "v3",
147 "v4", "v5", "v6", "v7",
148 "v8", "v9", "v10", "v11",
149 "v12", "v13", "v14", "v15",
150 "v16", "v17", "v18", "v19",
151 "v20", "v21", "v22", "v23",
152 "v24", "v25", "v26", "v27",
153 "v28", "v29", "v30", "v31",
158 /* AArch64 prologue cache structure. */
159 struct aarch64_prologue_cache
161 /* The program counter at the start of the function. It is used to
162 identify this frame as a prologue frame. */
165 /* The program counter at the time this frame was created; i.e. where
166 this function was called from. It is used to identify this frame as a
170 /* The stack pointer at the time this frame was created; i.e. the
171 caller's stack pointer when this function was called. It is used
172 to identify this frame. */
175 /* Is the target available to read from? */
178 /* The frame base for this frame is just prev_sp - frame size.
179 FRAMESIZE is the distance from the frame pointer to the
180 initial stack pointer. */
183 /* The register used to hold the frame pointer for this frame. */
186 /* Saved register offsets. */
187 struct trad_frame_saved_reg *saved_regs;
191 show_aarch64_debug (struct ui_file *file, int from_tty,
192 struct cmd_list_element *c, const char *value)
194 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
197 /* Analyze a prologue, looking for a recognizable stack frame
198 and frame pointer. Scan until we encounter a store that could
199 clobber the stack frame unexpectedly, or an unknown instruction. */
202 aarch64_analyze_prologue (struct gdbarch *gdbarch,
203 CORE_ADDR start, CORE_ADDR limit,
204 struct aarch64_prologue_cache *cache)
206 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
208 pv_t regs[AARCH64_X_REGISTER_COUNT];
209 struct pv_area *stack;
210 struct cleanup *back_to;
212 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
213 regs[i] = pv_register (i, 0);
214 stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
215 back_to = make_cleanup_free_pv_area (stack);
217 for (; start < limit; start += 4)
222 insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
224 if (aarch64_decode_insn (insn, &inst, 1) != 0)
227 if (inst.opcode->iclass == addsub_imm
228 && (inst.opcode->op == OP_ADD
229 || strcmp ("sub", inst.opcode->name) == 0))
231 unsigned rd = inst.operands[0].reg.regno;
232 unsigned rn = inst.operands[1].reg.regno;
234 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
235 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
236 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
237 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
239 if (inst.opcode->op == OP_ADD)
241 regs[rd] = pv_add_constant (regs[rn],
242 inst.operands[2].imm.value);
246 regs[rd] = pv_add_constant (regs[rn],
247 -inst.operands[2].imm.value);
250 else if (inst.opcode->iclass == pcreladdr
251 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
253 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
254 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
256 regs[inst.operands[0].reg.regno] = pv_unknown ();
258 else if (inst.opcode->iclass == branch_imm)
260 /* Stop analysis on branch. */
263 else if (inst.opcode->iclass == condbranch)
265 /* Stop analysis on branch. */
268 else if (inst.opcode->iclass == branch_reg)
270 /* Stop analysis on branch. */
273 else if (inst.opcode->iclass == compbranch)
275 /* Stop analysis on branch. */
278 else if (inst.opcode->op == OP_MOVZ)
280 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
281 regs[inst.operands[0].reg.regno] = pv_unknown ();
283 else if (inst.opcode->iclass == log_shift
284 && strcmp (inst.opcode->name, "orr") == 0)
286 unsigned rd = inst.operands[0].reg.regno;
287 unsigned rn = inst.operands[1].reg.regno;
288 unsigned rm = inst.operands[2].reg.regno;
290 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
291 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
292 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
294 if (inst.operands[2].shifter.amount == 0
295 && rn == AARCH64_SP_REGNUM)
301 debug_printf ("aarch64: prologue analysis gave up "
302 "addr=0x%s opcode=0x%x (orr x register)\n",
303 core_addr_to_string_nz (start), insn);
308 else if (inst.opcode->op == OP_STUR)
310 unsigned rt = inst.operands[0].reg.regno;
311 unsigned rn = inst.operands[1].addr.base_regno;
313 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
315 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
316 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
317 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
318 gdb_assert (!inst.operands[1].addr.offset.is_reg);
320 pv_area_store (stack, pv_add_constant (regs[rn],
321 inst.operands[1].addr.offset.imm),
322 is64 ? 8 : 4, regs[rt]);
324 else if ((inst.opcode->iclass == ldstpair_off
325 || inst.opcode->iclass == ldstpair_indexed)
326 && inst.operands[2].addr.preind
327 && strcmp ("stp", inst.opcode->name) == 0)
329 unsigned rt1 = inst.operands[0].reg.regno;
330 unsigned rt2 = inst.operands[1].reg.regno;
331 unsigned rn = inst.operands[2].addr.base_regno;
332 int32_t imm = inst.operands[2].addr.offset.imm;
334 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
335 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2);
336 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
337 gdb_assert (!inst.operands[2].addr.offset.is_reg);
339 /* If recording this store would invalidate the store area
340 (perhaps because rn is not known) then we should abandon
341 further prologue analysis. */
342 if (pv_area_store_would_trash (stack,
343 pv_add_constant (regs[rn], imm)))
346 if (pv_area_store_would_trash (stack,
347 pv_add_constant (regs[rn], imm + 8)))
350 pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
352 pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
355 if (inst.operands[2].addr.writeback)
356 regs[rn] = pv_add_constant (regs[rn], imm);
359 else if (inst.opcode->iclass == testbranch)
361 /* Stop analysis on branch. */
368 debug_printf ("aarch64: prologue analysis gave up addr=0x%s"
370 core_addr_to_string_nz (start), insn);
378 do_cleanups (back_to);
382 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
384 /* Frame pointer is fp. Frame size is constant. */
385 cache->framereg = AARCH64_FP_REGNUM;
386 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
388 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
390 /* Try the stack pointer. */
391 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
392 cache->framereg = AARCH64_SP_REGNUM;
396 /* We're just out of luck. We don't know where the frame is. */
397 cache->framereg = -1;
398 cache->framesize = 0;
401 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
405 if (pv_area_find_reg (stack, gdbarch, i, &offset))
406 cache->saved_regs[i].addr = offset;
409 do_cleanups (back_to);
413 /* Implement the "skip_prologue" gdbarch method. */
416 aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
420 CORE_ADDR func_addr, limit_pc;
421 struct symtab_and_line sal;
423 /* See if we can determine the end of the prologue via the symbol
424 table. If so, then return either PC, or the PC after the
425 prologue, whichever is greater. */
426 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
428 CORE_ADDR post_prologue_pc
429 = skip_prologue_using_sal (gdbarch, func_addr);
431 if (post_prologue_pc != 0)
432 return max (pc, post_prologue_pc);
435 /* Can't determine prologue from the symbol table, need to examine
438 /* Find an upper limit on the function prologue using the debug
439 information. If the debug information could not be used to
440 provide that bound, then use an arbitrary large number as the
442 limit_pc = skip_prologue_using_sal (gdbarch, pc);
444 limit_pc = pc + 128; /* Magic. */
446 /* Try disassembling prologue. */
447 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
450 /* Scan the function prologue for THIS_FRAME and populate the prologue
454 aarch64_scan_prologue (struct frame_info *this_frame,
455 struct aarch64_prologue_cache *cache)
457 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
458 CORE_ADDR prologue_start;
459 CORE_ADDR prologue_end;
460 CORE_ADDR prev_pc = get_frame_pc (this_frame);
461 struct gdbarch *gdbarch = get_frame_arch (this_frame);
463 cache->prev_pc = prev_pc;
465 /* Assume we do not find a frame. */
466 cache->framereg = -1;
467 cache->framesize = 0;
469 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
472 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
476 /* No line info so use the current PC. */
477 prologue_end = prev_pc;
479 else if (sal.end < prologue_end)
481 /* The next line begins after the function end. */
482 prologue_end = sal.end;
485 prologue_end = min (prologue_end, prev_pc);
486 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
493 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
495 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
499 cache->framereg = AARCH64_FP_REGNUM;
500 cache->framesize = 16;
501 cache->saved_regs[29].addr = 0;
502 cache->saved_regs[30].addr = 8;
506 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
507 function may throw an exception if the inferior's registers or memory is
511 aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
512 struct aarch64_prologue_cache *cache)
514 CORE_ADDR unwound_fp;
517 aarch64_scan_prologue (this_frame, cache);
519 if (cache->framereg == -1)
522 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
526 cache->prev_sp = unwound_fp + cache->framesize;
528 /* Calculate actual addresses of saved registers using offsets
529 determined by aarch64_analyze_prologue. */
530 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
531 if (trad_frame_addr_p (cache->saved_regs, reg))
532 cache->saved_regs[reg].addr += cache->prev_sp;
534 cache->func = get_frame_func (this_frame);
536 cache->available_p = 1;
539 /* Allocate and fill in *THIS_CACHE with information about the prologue of
540 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
541 Return a pointer to the current aarch64_prologue_cache in
544 static struct aarch64_prologue_cache *
545 aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
547 struct aarch64_prologue_cache *cache;
549 if (*this_cache != NULL)
550 return (struct aarch64_prologue_cache *) *this_cache;
552 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
553 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
558 aarch64_make_prologue_cache_1 (this_frame, cache);
560 CATCH (ex, RETURN_MASK_ERROR)
562 if (ex.error != NOT_AVAILABLE_ERROR)
563 throw_exception (ex);
570 /* Implement the "stop_reason" frame_unwind method. */
572 static enum unwind_stop_reason
573 aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
576 struct aarch64_prologue_cache *cache
577 = aarch64_make_prologue_cache (this_frame, this_cache);
579 if (!cache->available_p)
580 return UNWIND_UNAVAILABLE;
582 /* Halt the backtrace at "_start". */
583 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
584 return UNWIND_OUTERMOST;
586 /* We've hit a wall, stop. */
587 if (cache->prev_sp == 0)
588 return UNWIND_OUTERMOST;
590 return UNWIND_NO_REASON;
593 /* Our frame ID for a normal frame is the current function's starting
594 PC and the caller's SP when we were called. */
597 aarch64_prologue_this_id (struct frame_info *this_frame,
598 void **this_cache, struct frame_id *this_id)
600 struct aarch64_prologue_cache *cache
601 = aarch64_make_prologue_cache (this_frame, this_cache);
603 if (!cache->available_p)
604 *this_id = frame_id_build_unavailable_stack (cache->func);
606 *this_id = frame_id_build (cache->prev_sp, cache->func);
609 /* Implement the "prev_register" frame_unwind method. */
611 static struct value *
612 aarch64_prologue_prev_register (struct frame_info *this_frame,
613 void **this_cache, int prev_regnum)
615 struct gdbarch *gdbarch = get_frame_arch (this_frame);
616 struct aarch64_prologue_cache *cache
617 = aarch64_make_prologue_cache (this_frame, this_cache);
619 /* If we are asked to unwind the PC, then we need to return the LR
620 instead. The prologue may save PC, but it will point into this
621 frame's prologue, not the next frame's resume location. */
622 if (prev_regnum == AARCH64_PC_REGNUM)
626 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
627 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
630 /* SP is generally not saved to the stack, but this frame is
631 identified by the next frame's stack pointer at the time of the
632 call. The value was already reconstructed into PREV_SP. */
645 if (prev_regnum == AARCH64_SP_REGNUM)
646 return frame_unwind_got_constant (this_frame, prev_regnum,
649 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
653 /* AArch64 prologue unwinder. */
654 struct frame_unwind aarch64_prologue_unwind =
657 aarch64_prologue_frame_unwind_stop_reason,
658 aarch64_prologue_this_id,
659 aarch64_prologue_prev_register,
661 default_frame_sniffer
664 /* Allocate and fill in *THIS_CACHE with information about the prologue of
665 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
666 Return a pointer to the current aarch64_prologue_cache in
669 static struct aarch64_prologue_cache *
670 aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
672 struct aarch64_prologue_cache *cache;
674 if (*this_cache != NULL)
675 return (struct aarch64_prologue_cache *) *this_cache;
677 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
678 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
683 cache->prev_sp = get_frame_register_unsigned (this_frame,
685 cache->prev_pc = get_frame_pc (this_frame);
686 cache->available_p = 1;
688 CATCH (ex, RETURN_MASK_ERROR)
690 if (ex.error != NOT_AVAILABLE_ERROR)
691 throw_exception (ex);
698 /* Implement the "stop_reason" frame_unwind method. */
700 static enum unwind_stop_reason
701 aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
704 struct aarch64_prologue_cache *cache
705 = aarch64_make_stub_cache (this_frame, this_cache);
707 if (!cache->available_p)
708 return UNWIND_UNAVAILABLE;
710 return UNWIND_NO_REASON;
713 /* Our frame ID for a stub frame is the current SP and LR. */
716 aarch64_stub_this_id (struct frame_info *this_frame,
717 void **this_cache, struct frame_id *this_id)
719 struct aarch64_prologue_cache *cache
720 = aarch64_make_stub_cache (this_frame, this_cache);
722 if (cache->available_p)
723 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
725 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
728 /* Implement the "sniffer" frame_unwind method. */
731 aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
732 struct frame_info *this_frame,
733 void **this_prologue_cache)
735 CORE_ADDR addr_in_block;
738 addr_in_block = get_frame_address_in_block (this_frame);
739 if (in_plt_section (addr_in_block)
740 /* We also use the stub winder if the target memory is unreadable
741 to avoid having the prologue unwinder trying to read it. */
742 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
748 /* AArch64 stub unwinder. */
749 struct frame_unwind aarch64_stub_unwind =
752 aarch64_stub_frame_unwind_stop_reason,
753 aarch64_stub_this_id,
754 aarch64_prologue_prev_register,
756 aarch64_stub_unwind_sniffer
759 /* Return the frame base address of *THIS_FRAME. */
762 aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
764 struct aarch64_prologue_cache *cache
765 = aarch64_make_prologue_cache (this_frame, this_cache);
767 return cache->prev_sp - cache->framesize;
770 /* AArch64 default frame base information. */
771 struct frame_base aarch64_normal_base =
773 &aarch64_prologue_unwind,
774 aarch64_normal_frame_base,
775 aarch64_normal_frame_base,
776 aarch64_normal_frame_base
779 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
780 dummy frame. The frame ID's base needs to match the TOS value
781 saved by save_dummy_frame_tos () and returned from
782 aarch64_push_dummy_call, and the PC needs to match the dummy
783 frame's breakpoint. */
785 static struct frame_id
786 aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
788 return frame_id_build (get_frame_register_unsigned (this_frame,
790 get_frame_pc (this_frame));
793 /* Implement the "unwind_pc" gdbarch method. */
796 aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
799 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
804 /* Implement the "unwind_sp" gdbarch method. */
807 aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
809 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
812 /* Return the value of the REGNUM register in the previous frame of
815 static struct value *
816 aarch64_dwarf2_prev_register (struct frame_info *this_frame,
817 void **this_cache, int regnum)
819 struct gdbarch *gdbarch = get_frame_arch (this_frame);
824 case AARCH64_PC_REGNUM:
825 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
826 return frame_unwind_got_constant (this_frame, regnum, lr);
829 internal_error (__FILE__, __LINE__,
830 _("Unexpected register %d"), regnum);
834 /* Implement the "init_reg" dwarf2_frame_ops method. */
837 aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
838 struct dwarf2_frame_state_reg *reg,
839 struct frame_info *this_frame)
843 case AARCH64_PC_REGNUM:
844 reg->how = DWARF2_FRAME_REG_FN;
845 reg->loc.fn = aarch64_dwarf2_prev_register;
847 case AARCH64_SP_REGNUM:
848 reg->how = DWARF2_FRAME_REG_CFA;
853 /* When arguments must be pushed onto the stack, they go on in reverse
854 order. The code below implements a FILO (stack) to do this. */
858 /* Value to pass on stack. */
859 const gdb_byte *data;
861 /* Size in bytes of value to pass on stack. */
865 DEF_VEC_O (stack_item_t);
867 /* Return the alignment (in bytes) of the given type. */
870 aarch64_type_align (struct type *t)
876 t = check_typedef (t);
877 switch (TYPE_CODE (t))
880 /* Should never happen. */
881 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
889 case TYPE_CODE_RANGE:
890 case TYPE_CODE_BITSTRING:
894 return TYPE_LENGTH (t);
896 case TYPE_CODE_ARRAY:
899 /* Use the natural alignment for vector types (the same for
900 scalar type), but the maximum alignment is 128-bit. */
901 if (TYPE_LENGTH (t) > 16)
904 return TYPE_LENGTH (t);
907 return aarch64_type_align (TYPE_TARGET_TYPE (t));
908 case TYPE_CODE_COMPLEX:
909 return aarch64_type_align (TYPE_TARGET_TYPE (t));
911 case TYPE_CODE_STRUCT:
912 case TYPE_CODE_UNION:
914 for (n = 0; n < TYPE_NFIELDS (t); n++)
916 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
924 /* Return 1 if *TY is a homogeneous floating-point aggregate as
925 defined in the AAPCS64 ABI document; otherwise return 0. */
928 is_hfa (struct type *ty)
930 switch (TYPE_CODE (ty))
932 case TYPE_CODE_ARRAY:
934 struct type *target_ty = TYPE_TARGET_TYPE (ty);
936 if (TYPE_VECTOR (ty))
939 if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4)
944 case TYPE_CODE_UNION:
945 case TYPE_CODE_STRUCT:
947 if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
949 struct type *member0_type;
951 member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
952 if (TYPE_CODE (member0_type) == TYPE_CODE_FLT)
956 for (i = 0; i < TYPE_NFIELDS (ty); i++)
958 struct type *member1_type;
960 member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i));
961 if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type)
962 || (TYPE_LENGTH (member0_type)
963 != TYPE_LENGTH (member1_type)))
979 /* AArch64 function call information structure. */
980 struct aarch64_call_info
982 /* the current argument number. */
985 /* The next general purpose register number, equivalent to NGRN as
986 described in the AArch64 Procedure Call Standard. */
989 /* The next SIMD and floating point register number, equivalent to
990 NSRN as described in the AArch64 Procedure Call Standard. */
993 /* The next stacked argument address, equivalent to NSAA as
994 described in the AArch64 Procedure Call Standard. */
997 /* Stack item vector. */
998 VEC(stack_item_t) *si;
1001 /* Pass a value in a sequence of consecutive X registers. The caller
1002 is responsbile for ensuring sufficient registers are available. */
1005 pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1006 struct aarch64_call_info *info, struct type *type,
1009 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1010 int len = TYPE_LENGTH (type);
1011 enum type_code typecode = TYPE_CODE (type);
1012 int regnum = AARCH64_X0_REGNUM + info->ngrn;
1013 const bfd_byte *buf = value_contents (arg);
1019 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1020 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1024 /* Adjust sub-word struct/union args when big-endian. */
1025 if (byte_order == BFD_ENDIAN_BIG
1026 && partial_len < X_REGISTER_SIZE
1027 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1028 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1032 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1033 gdbarch_register_name (gdbarch, regnum),
1034 phex (regval, X_REGISTER_SIZE));
1036 regcache_cooked_write_unsigned (regcache, regnum, regval);
1043 /* Attempt to marshall a value in a V register. Return 1 if
1044 successful, or 0 if insufficient registers are available. This
1045 function, unlike the equivalent pass_in_x() function does not
1046 handle arguments spread across multiple registers. */
1049 pass_in_v (struct gdbarch *gdbarch,
1050 struct regcache *regcache,
1051 struct aarch64_call_info *info,
1052 int len, const bfd_byte *buf)
1056 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1057 int regnum = AARCH64_V0_REGNUM + info->nsrn;
1058 gdb_byte reg[V_REGISTER_SIZE];
1063 memset (reg, 0, sizeof (reg));
1064 /* PCS C.1, the argument is allocated to the least significant
1065 bits of V register. */
1066 memcpy (reg, buf, len);
1067 regcache_cooked_write (regcache, regnum, reg);
1071 debug_printf ("arg %d in %s\n", info->argnum,
1072 gdbarch_register_name (gdbarch, regnum));
1080 /* Marshall an argument onto the stack. */
1083 pass_on_stack (struct aarch64_call_info *info, struct type *type,
1086 const bfd_byte *buf = value_contents (arg);
1087 int len = TYPE_LENGTH (type);
1093 align = aarch64_type_align (type);
1095 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1096 Natural alignment of the argument's type. */
1097 align = align_up (align, 8);
1099 /* The AArch64 PCS requires at most doubleword alignment. */
1105 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1111 VEC_safe_push (stack_item_t, info->si, &item);
1114 if (info->nsaa & (align - 1))
1116 /* Push stack alignment padding. */
1117 int pad = align - (info->nsaa & (align - 1));
1122 VEC_safe_push (stack_item_t, info->si, &item);
1127 /* Marshall an argument into a sequence of one or more consecutive X
1128 registers or, if insufficient X registers are available then onto
1132 pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1133 struct aarch64_call_info *info, struct type *type,
1136 int len = TYPE_LENGTH (type);
1137 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1139 /* PCS C.13 - Pass in registers if we have enough spare */
1140 if (info->ngrn + nregs <= 8)
1142 pass_in_x (gdbarch, regcache, info, type, arg);
1143 info->ngrn += nregs;
1148 pass_on_stack (info, type, arg);
1152 /* Pass a value in a V register, or on the stack if insufficient are
1156 pass_in_v_or_stack (struct gdbarch *gdbarch,
1157 struct regcache *regcache,
1158 struct aarch64_call_info *info,
1162 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type),
1163 value_contents (arg)))
1164 pass_on_stack (info, type, arg);
1167 /* Implement the "push_dummy_call" gdbarch method. */
1170 aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1171 struct regcache *regcache, CORE_ADDR bp_addr,
1173 struct value **args, CORE_ADDR sp, int struct_return,
1174 CORE_ADDR struct_addr)
1180 struct aarch64_call_info info;
1181 struct type *func_type;
1182 struct type *return_type;
1183 int lang_struct_return;
1185 memset (&info, 0, sizeof (info));
1187 /* We need to know what the type of the called function is in order
1188 to determine the number of named/anonymous arguments for the
1189 actual argument placement, and the return type in order to handle
1190 return value correctly.
1192 The generic code above us views the decision of return in memory
1193 or return in registers as a two stage processes. The language
1194 handler is consulted first and may decide to return in memory (eg
1195 class with copy constructor returned by value), this will cause
1196 the generic code to allocate space AND insert an initial leading
1199 If the language code does not decide to pass in memory then the
1200 target code is consulted.
1202 If the language code decides to pass in memory we want to move
1203 the pointer inserted as the initial argument from the argument
1204 list and into X8, the conventional AArch64 struct return pointer
1207 This is slightly awkward, ideally the flag "lang_struct_return"
1208 would be passed to the targets implementation of push_dummy_call.
1209 Rather that change the target interface we call the language code
1210 directly ourselves. */
1212 func_type = check_typedef (value_type (function));
1214 /* Dereference function pointer types. */
1215 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1216 func_type = TYPE_TARGET_TYPE (func_type);
1218 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1219 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1221 /* If language_pass_by_reference () returned true we will have been
1222 given an additional initial argument, a hidden pointer to the
1223 return slot in memory. */
1224 return_type = TYPE_TARGET_TYPE (func_type);
1225 lang_struct_return = language_pass_by_reference (return_type);
1227 /* Set the return address. For the AArch64, the return breakpoint
1228 is always at BP_ADDR. */
1229 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1231 /* If we were given an initial argument for the return slot because
1232 lang_struct_return was true, lose it. */
1233 if (lang_struct_return)
1239 /* The struct_return pointer occupies X8. */
1240 if (struct_return || lang_struct_return)
1244 debug_printf ("struct return in %s = 0x%s\n",
1245 gdbarch_register_name (gdbarch,
1246 AARCH64_STRUCT_RETURN_REGNUM),
1247 paddress (gdbarch, struct_addr));
1249 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1253 for (argnum = 0; argnum < nargs; argnum++)
1255 struct value *arg = args[argnum];
1256 struct type *arg_type;
1259 arg_type = check_typedef (value_type (arg));
1260 len = TYPE_LENGTH (arg_type);
1262 switch (TYPE_CODE (arg_type))
1265 case TYPE_CODE_BOOL:
1266 case TYPE_CODE_CHAR:
1267 case TYPE_CODE_RANGE:
1268 case TYPE_CODE_ENUM:
1271 /* Promote to 32 bit integer. */
1272 if (TYPE_UNSIGNED (arg_type))
1273 arg_type = builtin_type (gdbarch)->builtin_uint32;
1275 arg_type = builtin_type (gdbarch)->builtin_int32;
1276 arg = value_cast (arg_type, arg);
1278 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1281 case TYPE_CODE_COMPLEX:
1284 const bfd_byte *buf = value_contents (arg);
1285 struct type *target_type =
1286 check_typedef (TYPE_TARGET_TYPE (arg_type));
1288 pass_in_v (gdbarch, regcache, &info,
1289 TYPE_LENGTH (target_type), buf);
1290 pass_in_v (gdbarch, regcache, &info,
1291 TYPE_LENGTH (target_type),
1292 buf + TYPE_LENGTH (target_type));
1297 pass_on_stack (&info, arg_type, arg);
1301 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1304 case TYPE_CODE_STRUCT:
1305 case TYPE_CODE_ARRAY:
1306 case TYPE_CODE_UNION:
1307 if (is_hfa (arg_type))
1309 int elements = TYPE_NFIELDS (arg_type);
1311 /* Homogeneous Aggregates */
1312 if (info.nsrn + elements < 8)
1316 for (i = 0; i < elements; i++)
1318 /* We know that we have sufficient registers
1319 available therefore this will never fallback
1321 struct value *field =
1322 value_primitive_field (arg, 0, i, arg_type);
1323 struct type *field_type =
1324 check_typedef (value_type (field));
1326 pass_in_v_or_stack (gdbarch, regcache, &info,
1333 pass_on_stack (&info, arg_type, arg);
1336 else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
1337 && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
1339 /* Short vector types are passed in V registers. */
1340 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1344 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1345 invisible reference. */
1347 /* Allocate aligned storage. */
1348 sp = align_down (sp - len, 16);
1350 /* Write the real data into the stack. */
1351 write_memory (sp, value_contents (arg), len);
1353 /* Construct the indirection. */
1354 arg_type = lookup_pointer_type (arg_type);
1355 arg = value_from_pointer (arg_type, sp);
1356 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1359 /* PCS C.15 / C.18 multiple values pass. */
1360 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1364 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1369 /* Make sure stack retains 16 byte alignment. */
1371 sp -= 16 - (info.nsaa & 15);
1373 while (!VEC_empty (stack_item_t, info.si))
1375 stack_item_t *si = VEC_last (stack_item_t, info.si);
1378 write_memory (sp, si->data, si->len);
1379 VEC_pop (stack_item_t, info.si);
1382 VEC_free (stack_item_t, info.si);
1384 /* Finally, update the SP register. */
1385 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1390 /* Implement the "frame_align" gdbarch method. */
1393 aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1395 /* Align the stack to sixteen bytes. */
1396 return sp & ~(CORE_ADDR) 15;
1399 /* Return the type for an AdvSISD Q register. */
1401 static struct type *
1402 aarch64_vnq_type (struct gdbarch *gdbarch)
1404 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1406 if (tdep->vnq_type == NULL)
1411 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1414 elem = builtin_type (gdbarch)->builtin_uint128;
1415 append_composite_type_field (t, "u", elem);
1417 elem = builtin_type (gdbarch)->builtin_int128;
1418 append_composite_type_field (t, "s", elem);
1423 return tdep->vnq_type;
1426 /* Return the type for an AdvSISD D register. */
1428 static struct type *
1429 aarch64_vnd_type (struct gdbarch *gdbarch)
1431 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1433 if (tdep->vnd_type == NULL)
1438 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1441 elem = builtin_type (gdbarch)->builtin_double;
1442 append_composite_type_field (t, "f", elem);
1444 elem = builtin_type (gdbarch)->builtin_uint64;
1445 append_composite_type_field (t, "u", elem);
1447 elem = builtin_type (gdbarch)->builtin_int64;
1448 append_composite_type_field (t, "s", elem);
1453 return tdep->vnd_type;
1456 /* Return the type for an AdvSISD S register. */
1458 static struct type *
1459 aarch64_vns_type (struct gdbarch *gdbarch)
1461 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1463 if (tdep->vns_type == NULL)
1468 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1471 elem = builtin_type (gdbarch)->builtin_float;
1472 append_composite_type_field (t, "f", elem);
1474 elem = builtin_type (gdbarch)->builtin_uint32;
1475 append_composite_type_field (t, "u", elem);
1477 elem = builtin_type (gdbarch)->builtin_int32;
1478 append_composite_type_field (t, "s", elem);
1483 return tdep->vns_type;
1486 /* Return the type for an AdvSISD H register. */
1488 static struct type *
1489 aarch64_vnh_type (struct gdbarch *gdbarch)
1491 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1493 if (tdep->vnh_type == NULL)
1498 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1501 elem = builtin_type (gdbarch)->builtin_uint16;
1502 append_composite_type_field (t, "u", elem);
1504 elem = builtin_type (gdbarch)->builtin_int16;
1505 append_composite_type_field (t, "s", elem);
1510 return tdep->vnh_type;
1513 /* Return the type for an AdvSISD B register. */
1515 static struct type *
1516 aarch64_vnb_type (struct gdbarch *gdbarch)
1518 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1520 if (tdep->vnb_type == NULL)
1525 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1528 elem = builtin_type (gdbarch)->builtin_uint8;
1529 append_composite_type_field (t, "u", elem);
1531 elem = builtin_type (gdbarch)->builtin_int8;
1532 append_composite_type_field (t, "s", elem);
1537 return tdep->vnb_type;
1540 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1543 aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1545 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1546 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1548 if (reg == AARCH64_DWARF_SP)
1549 return AARCH64_SP_REGNUM;
1551 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1552 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1558 /* Implement the "print_insn" gdbarch method. */
1561 aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1563 info->symbols = NULL;
1564 return print_insn_aarch64 (memaddr, info);
1567 /* AArch64 BRK software debug mode instruction.
1568 Note that AArch64 code is always little-endian.
1569 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1570 static const gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
1572 /* Implement the "breakpoint_from_pc" gdbarch method. */
1574 static const gdb_byte *
1575 aarch64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1578 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1580 *lenptr = sizeof (aarch64_default_breakpoint);
1581 return aarch64_default_breakpoint;
1584 /* Extract from an array REGS containing the (raw) register state a
1585 function return value of type TYPE, and copy that, in virtual
1586 format, into VALBUF. */
1589 aarch64_extract_return_value (struct type *type, struct regcache *regs,
1592 struct gdbarch *gdbarch = get_regcache_arch (regs);
1593 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1595 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1597 bfd_byte buf[V_REGISTER_SIZE];
1598 int len = TYPE_LENGTH (type);
1600 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1601 memcpy (valbuf, buf, len);
1603 else if (TYPE_CODE (type) == TYPE_CODE_INT
1604 || TYPE_CODE (type) == TYPE_CODE_CHAR
1605 || TYPE_CODE (type) == TYPE_CODE_BOOL
1606 || TYPE_CODE (type) == TYPE_CODE_PTR
1607 || TYPE_CODE (type) == TYPE_CODE_REF
1608 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1610 /* If the the type is a plain integer, then the access is
1611 straight-forward. Otherwise we have to play around a bit
1613 int len = TYPE_LENGTH (type);
1614 int regno = AARCH64_X0_REGNUM;
1619 /* By using store_unsigned_integer we avoid having to do
1620 anything special for small big-endian values. */
1621 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1622 store_unsigned_integer (valbuf,
1623 (len > X_REGISTER_SIZE
1624 ? X_REGISTER_SIZE : len), byte_order, tmp);
1625 len -= X_REGISTER_SIZE;
1626 valbuf += X_REGISTER_SIZE;
1629 else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX)
1631 int regno = AARCH64_V0_REGNUM;
1632 bfd_byte buf[V_REGISTER_SIZE];
1633 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1634 int len = TYPE_LENGTH (target_type);
1636 regcache_cooked_read (regs, regno, buf);
1637 memcpy (valbuf, buf, len);
1639 regcache_cooked_read (regs, regno + 1, buf);
1640 memcpy (valbuf, buf, len);
1643 else if (is_hfa (type))
1645 int elements = TYPE_NFIELDS (type);
1646 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1647 int len = TYPE_LENGTH (member_type);
1650 for (i = 0; i < elements; i++)
1652 int regno = AARCH64_V0_REGNUM + i;
1653 bfd_byte buf[V_REGISTER_SIZE];
1657 debug_printf ("read HFA return value element %d from %s\n",
1659 gdbarch_register_name (gdbarch, regno));
1661 regcache_cooked_read (regs, regno, buf);
1663 memcpy (valbuf, buf, len);
1667 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1668 && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
1670 /* Short vector is returned in V register. */
1671 gdb_byte buf[V_REGISTER_SIZE];
1673 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1674 memcpy (valbuf, buf, TYPE_LENGTH (type));
1678 /* For a structure or union the behaviour is as if the value had
1679 been stored to word-aligned memory and then loaded into
1680 registers with 64-bit load instruction(s). */
1681 int len = TYPE_LENGTH (type);
1682 int regno = AARCH64_X0_REGNUM;
1683 bfd_byte buf[X_REGISTER_SIZE];
1687 regcache_cooked_read (regs, regno++, buf);
1688 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1689 len -= X_REGISTER_SIZE;
1690 valbuf += X_REGISTER_SIZE;
1696 /* Will a function return an aggregate type in memory or in a
1697 register? Return 0 if an aggregate type can be returned in a
1698 register, 1 if it must be returned in memory. */
1701 aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1704 enum type_code code;
1706 type = check_typedef (type);
1708 /* In the AArch64 ABI, "integer" like aggregate types are returned
1709 in registers. For an aggregate type to be integer like, its size
1710 must be less than or equal to 4 * X_REGISTER_SIZE. */
1714 /* PCS B.5 If the argument is a Named HFA, then the argument is
1719 if (TYPE_LENGTH (type) > 16)
1721 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1722 invisible reference. */
1730 /* Write into appropriate registers a function return value of type
1731 TYPE, given in virtual format. */
1734 aarch64_store_return_value (struct type *type, struct regcache *regs,
1735 const gdb_byte *valbuf)
1737 struct gdbarch *gdbarch = get_regcache_arch (regs);
1738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1740 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1742 bfd_byte buf[V_REGISTER_SIZE];
1743 int len = TYPE_LENGTH (type);
1745 memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
1746 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
1748 else if (TYPE_CODE (type) == TYPE_CODE_INT
1749 || TYPE_CODE (type) == TYPE_CODE_CHAR
1750 || TYPE_CODE (type) == TYPE_CODE_BOOL
1751 || TYPE_CODE (type) == TYPE_CODE_PTR
1752 || TYPE_CODE (type) == TYPE_CODE_REF
1753 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1755 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
1757 /* Values of one word or less are zero/sign-extended and
1759 bfd_byte tmpbuf[X_REGISTER_SIZE];
1760 LONGEST val = unpack_long (type, valbuf);
1762 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
1763 regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf);
1767 /* Integral values greater than one word are stored in
1768 consecutive registers starting with r0. This will always
1769 be a multiple of the regiser size. */
1770 int len = TYPE_LENGTH (type);
1771 int regno = AARCH64_X0_REGNUM;
1775 regcache_cooked_write (regs, regno++, valbuf);
1776 len -= X_REGISTER_SIZE;
1777 valbuf += X_REGISTER_SIZE;
1781 else if (is_hfa (type))
1783 int elements = TYPE_NFIELDS (type);
1784 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1785 int len = TYPE_LENGTH (member_type);
1788 for (i = 0; i < elements; i++)
1790 int regno = AARCH64_V0_REGNUM + i;
1791 bfd_byte tmpbuf[MAX_REGISTER_SIZE];
1795 debug_printf ("write HFA return value element %d to %s\n",
1797 gdbarch_register_name (gdbarch, regno));
1800 memcpy (tmpbuf, valbuf, len);
1801 regcache_cooked_write (regs, regno, tmpbuf);
1805 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1806 && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
1809 gdb_byte buf[V_REGISTER_SIZE];
1811 memcpy (buf, valbuf, TYPE_LENGTH (type));
1812 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
1816 /* For a structure or union the behaviour is as if the value had
1817 been stored to word-aligned memory and then loaded into
1818 registers with 64-bit load instruction(s). */
1819 int len = TYPE_LENGTH (type);
1820 int regno = AARCH64_X0_REGNUM;
1821 bfd_byte tmpbuf[X_REGISTER_SIZE];
1825 memcpy (tmpbuf, valbuf,
1826 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1827 regcache_cooked_write (regs, regno++, tmpbuf);
1828 len -= X_REGISTER_SIZE;
1829 valbuf += X_REGISTER_SIZE;
1834 /* Implement the "return_value" gdbarch method. */
1836 static enum return_value_convention
1837 aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
1838 struct type *valtype, struct regcache *regcache,
1839 gdb_byte *readbuf, const gdb_byte *writebuf)
1841 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1843 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1844 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1845 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1847 if (aarch64_return_in_memory (gdbarch, valtype))
1850 debug_printf ("return value in memory\n");
1851 return RETURN_VALUE_STRUCT_CONVENTION;
1856 aarch64_store_return_value (valtype, regcache, writebuf);
1859 aarch64_extract_return_value (valtype, regcache, readbuf);
1862 debug_printf ("return value in registers\n");
1864 return RETURN_VALUE_REGISTER_CONVENTION;
1867 /* Implement the "get_longjmp_target" gdbarch method. */
1870 aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1873 gdb_byte buf[X_REGISTER_SIZE];
1874 struct gdbarch *gdbarch = get_frame_arch (frame);
1875 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1876 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1878 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
1880 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
1884 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
1888 /* Implement the "gen_return_address" gdbarch method. */
1891 aarch64_gen_return_address (struct gdbarch *gdbarch,
1892 struct agent_expr *ax, struct axs_value *value,
1895 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
1896 value->kind = axs_lvalue_register;
1897 value->u.reg = AARCH64_LR_REGNUM;
1901 /* Return the pseudo register name corresponding to register regnum. */
1904 aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
1906 static const char *const q_name[] =
1908 "q0", "q1", "q2", "q3",
1909 "q4", "q5", "q6", "q7",
1910 "q8", "q9", "q10", "q11",
1911 "q12", "q13", "q14", "q15",
1912 "q16", "q17", "q18", "q19",
1913 "q20", "q21", "q22", "q23",
1914 "q24", "q25", "q26", "q27",
1915 "q28", "q29", "q30", "q31",
1918 static const char *const d_name[] =
1920 "d0", "d1", "d2", "d3",
1921 "d4", "d5", "d6", "d7",
1922 "d8", "d9", "d10", "d11",
1923 "d12", "d13", "d14", "d15",
1924 "d16", "d17", "d18", "d19",
1925 "d20", "d21", "d22", "d23",
1926 "d24", "d25", "d26", "d27",
1927 "d28", "d29", "d30", "d31",
1930 static const char *const s_name[] =
1932 "s0", "s1", "s2", "s3",
1933 "s4", "s5", "s6", "s7",
1934 "s8", "s9", "s10", "s11",
1935 "s12", "s13", "s14", "s15",
1936 "s16", "s17", "s18", "s19",
1937 "s20", "s21", "s22", "s23",
1938 "s24", "s25", "s26", "s27",
1939 "s28", "s29", "s30", "s31",
1942 static const char *const h_name[] =
1944 "h0", "h1", "h2", "h3",
1945 "h4", "h5", "h6", "h7",
1946 "h8", "h9", "h10", "h11",
1947 "h12", "h13", "h14", "h15",
1948 "h16", "h17", "h18", "h19",
1949 "h20", "h21", "h22", "h23",
1950 "h24", "h25", "h26", "h27",
1951 "h28", "h29", "h30", "h31",
1954 static const char *const b_name[] =
1956 "b0", "b1", "b2", "b3",
1957 "b4", "b5", "b6", "b7",
1958 "b8", "b9", "b10", "b11",
1959 "b12", "b13", "b14", "b15",
1960 "b16", "b17", "b18", "b19",
1961 "b20", "b21", "b22", "b23",
1962 "b24", "b25", "b26", "b27",
1963 "b28", "b29", "b30", "b31",
1966 regnum -= gdbarch_num_regs (gdbarch);
1968 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
1969 return q_name[regnum - AARCH64_Q0_REGNUM];
1971 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
1972 return d_name[regnum - AARCH64_D0_REGNUM];
1974 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
1975 return s_name[regnum - AARCH64_S0_REGNUM];
1977 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
1978 return h_name[regnum - AARCH64_H0_REGNUM];
1980 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
1981 return b_name[regnum - AARCH64_B0_REGNUM];
1983 internal_error (__FILE__, __LINE__,
1984 _("aarch64_pseudo_register_name: bad register number %d"),
1988 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
1990 static struct type *
1991 aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1993 regnum -= gdbarch_num_regs (gdbarch);
1995 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
1996 return aarch64_vnq_type (gdbarch);
1998 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
1999 return aarch64_vnd_type (gdbarch);
2001 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2002 return aarch64_vns_type (gdbarch);
2004 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2005 return aarch64_vnh_type (gdbarch);
2007 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2008 return aarch64_vnb_type (gdbarch);
2010 internal_error (__FILE__, __LINE__,
2011 _("aarch64_pseudo_register_type: bad register number %d"),
2015 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2018 aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2019 struct reggroup *group)
2021 regnum -= gdbarch_num_regs (gdbarch);
2023 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2024 return group == all_reggroup || group == vector_reggroup;
2025 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2026 return (group == all_reggroup || group == vector_reggroup
2027 || group == float_reggroup);
2028 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2029 return (group == all_reggroup || group == vector_reggroup
2030 || group == float_reggroup);
2031 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2032 return group == all_reggroup || group == vector_reggroup;
2033 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2034 return group == all_reggroup || group == vector_reggroup;
2036 return group == all_reggroup;
2039 /* Implement the "pseudo_register_read_value" gdbarch method. */
2041 static struct value *
2042 aarch64_pseudo_read_value (struct gdbarch *gdbarch,
2043 struct regcache *regcache,
2046 gdb_byte reg_buf[MAX_REGISTER_SIZE];
2047 struct value *result_value;
2050 result_value = allocate_value (register_type (gdbarch, regnum));
2051 VALUE_LVAL (result_value) = lval_register;
2052 VALUE_REGNUM (result_value) = regnum;
2053 buf = value_contents_raw (result_value);
2055 regnum -= gdbarch_num_regs (gdbarch);
2057 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2059 enum register_status status;
2062 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2063 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2064 if (status != REG_VALID)
2065 mark_value_bytes_unavailable (result_value, 0,
2066 TYPE_LENGTH (value_type (result_value)));
2068 memcpy (buf, reg_buf, Q_REGISTER_SIZE);
2069 return result_value;
2072 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2074 enum register_status status;
2077 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2078 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2079 if (status != REG_VALID)
2080 mark_value_bytes_unavailable (result_value, 0,
2081 TYPE_LENGTH (value_type (result_value)));
2083 memcpy (buf, reg_buf, D_REGISTER_SIZE);
2084 return result_value;
2087 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2089 enum register_status status;
2092 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2093 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2094 if (status != REG_VALID)
2095 mark_value_bytes_unavailable (result_value, 0,
2096 TYPE_LENGTH (value_type (result_value)));
2098 memcpy (buf, reg_buf, S_REGISTER_SIZE);
2099 return result_value;
2102 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2104 enum register_status status;
2107 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2108 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2109 if (status != REG_VALID)
2110 mark_value_bytes_unavailable (result_value, 0,
2111 TYPE_LENGTH (value_type (result_value)));
2113 memcpy (buf, reg_buf, H_REGISTER_SIZE);
2114 return result_value;
2117 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2119 enum register_status status;
2122 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2123 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2124 if (status != REG_VALID)
2125 mark_value_bytes_unavailable (result_value, 0,
2126 TYPE_LENGTH (value_type (result_value)));
2128 memcpy (buf, reg_buf, B_REGISTER_SIZE);
2129 return result_value;
2132 gdb_assert_not_reached ("regnum out of bound");
2135 /* Implement the "pseudo_register_write" gdbarch method. */
2138 aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2139 int regnum, const gdb_byte *buf)
2141 gdb_byte reg_buf[MAX_REGISTER_SIZE];
2143 /* Ensure the register buffer is zero, we want gdb writes of the
2144 various 'scalar' pseudo registers to behavior like architectural
2145 writes, register width bytes are written the remainder are set to
2147 memset (reg_buf, 0, sizeof (reg_buf));
2149 regnum -= gdbarch_num_regs (gdbarch);
2151 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2153 /* pseudo Q registers */
2156 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2157 memcpy (reg_buf, buf, Q_REGISTER_SIZE);
2158 regcache_raw_write (regcache, v_regnum, reg_buf);
2162 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2164 /* pseudo D registers */
2167 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2168 memcpy (reg_buf, buf, D_REGISTER_SIZE);
2169 regcache_raw_write (regcache, v_regnum, reg_buf);
2173 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2177 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2178 memcpy (reg_buf, buf, S_REGISTER_SIZE);
2179 regcache_raw_write (regcache, v_regnum, reg_buf);
2183 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2185 /* pseudo H registers */
2188 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2189 memcpy (reg_buf, buf, H_REGISTER_SIZE);
2190 regcache_raw_write (regcache, v_regnum, reg_buf);
2194 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2196 /* pseudo B registers */
2199 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2200 memcpy (reg_buf, buf, B_REGISTER_SIZE);
2201 regcache_raw_write (regcache, v_regnum, reg_buf);
2205 gdb_assert_not_reached ("regnum out of bound");
2208 /* Callback function for user_reg_add. */
2210 static struct value *
2211 value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2213 const int *reg_p = (const int *) baton;
2215 return value_of_register (*reg_p, frame);
2219 /* Implement the "software_single_step" gdbarch method, needed to
2220 single step through atomic sequences on AArch64. */
2223 aarch64_software_single_step (struct frame_info *frame)
2225 struct gdbarch *gdbarch = get_frame_arch (frame);
2226 struct address_space *aspace = get_frame_address_space (frame);
2227 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2228 const int insn_size = 4;
2229 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2230 CORE_ADDR pc = get_frame_pc (frame);
2231 CORE_ADDR breaks[2] = { -1, -1 };
2233 CORE_ADDR closing_insn = 0;
2234 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2235 byte_order_for_code);
2238 int bc_insn_count = 0; /* Conditional branch instruction count. */
2239 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2242 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2245 /* Look for a Load Exclusive instruction which begins the sequence. */
2246 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
2249 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2252 insn = read_memory_unsigned_integer (loc, insn_size,
2253 byte_order_for_code);
2255 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2257 /* Check if the instruction is a conditional branch. */
2258 if (inst.opcode->iclass == condbranch)
2260 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2262 if (bc_insn_count >= 1)
2265 /* It is, so we'll try to set a breakpoint at the destination. */
2266 breaks[1] = loc + inst.operands[0].imm.value;
2272 /* Look for the Store Exclusive which closes the atomic sequence. */
2273 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
2280 /* We didn't find a closing Store Exclusive instruction, fall back. */
2284 /* Insert breakpoint after the end of the atomic sequence. */
2285 breaks[0] = loc + insn_size;
2287 /* Check for duplicated breakpoints, and also check that the second
2288 breakpoint is not within the atomic sequence. */
2290 && (breaks[1] == breaks[0]
2291 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2292 last_breakpoint = 0;
2294 /* Insert the breakpoint at the end of the sequence, and one at the
2295 destination of the conditional branch, if it exists. */
2296 for (index = 0; index <= last_breakpoint; index++)
2297 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
2302 struct displaced_step_closure
2304 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2305 is being displaced stepping. */
2308 /* PC adjustment offset after displaced stepping. */
2312 /* Data when visiting instructions for displaced stepping. */
2314 struct aarch64_displaced_step_data
2316 struct aarch64_insn_data base;
2318 /* The address where the instruction will be executed at. */
2320 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2321 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2322 /* Number of instructions in INSN_BUF. */
2323 unsigned insn_count;
2324 /* Registers when doing displaced stepping. */
2325 struct regcache *regs;
2327 struct displaced_step_closure *dsc;
2330 /* Implementation of aarch64_insn_visitor method "b". */
2333 aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2334 struct aarch64_insn_data *data)
2336 struct aarch64_displaced_step_data *dsd
2337 = (struct aarch64_displaced_step_data *) data;
2338 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2340 if (can_encode_int32 (new_offset, 28))
2342 /* Emit B rather than BL, because executing BL on a new address
2343 will get the wrong address into LR. In order to avoid this,
2344 we emit B, and update LR if the instruction is BL. */
2345 emit_b (dsd->insn_buf, 0, new_offset);
2351 emit_nop (dsd->insn_buf);
2353 dsd->dsc->pc_adjust = offset;
2359 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2360 data->insn_addr + 4);
2364 /* Implementation of aarch64_insn_visitor method "b_cond". */
2367 aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2368 struct aarch64_insn_data *data)
2370 struct aarch64_displaced_step_data *dsd
2371 = (struct aarch64_displaced_step_data *) data;
2372 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2374 /* GDB has to fix up PC after displaced step this instruction
2375 differently according to the condition is true or false. Instead
2376 of checking COND against conditional flags, we can use
2377 the following instructions, and GDB can tell how to fix up PC
2378 according to the PC value.
2380 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2386 emit_bcond (dsd->insn_buf, cond, 8);
2388 dsd->dsc->pc_adjust = offset;
2389 dsd->insn_count = 1;
2392 /* Dynamically allocate a new register. If we know the register
2393 statically, we should make it a global as above instead of using this
2396 static struct aarch64_register
2397 aarch64_register (unsigned num, int is64)
2399 return (struct aarch64_register) { num, is64 };
2402 /* Implementation of aarch64_insn_visitor method "cb". */
2405 aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2406 const unsigned rn, int is64,
2407 struct aarch64_insn_data *data)
2409 struct aarch64_displaced_step_data *dsd
2410 = (struct aarch64_displaced_step_data *) data;
2411 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2413 /* The offset is out of range for a compare and branch
2414 instruction. We can use the following instructions instead:
2416 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2421 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2422 dsd->insn_count = 1;
2424 dsd->dsc->pc_adjust = offset;
2427 /* Implementation of aarch64_insn_visitor method "tb". */
2430 aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2431 const unsigned rt, unsigned bit,
2432 struct aarch64_insn_data *data)
2434 struct aarch64_displaced_step_data *dsd
2435 = (struct aarch64_displaced_step_data *) data;
2436 int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
2438 /* The offset is out of range for a test bit and branch
2439 instruction We can use the following instructions instead:
2441 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2447 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2448 dsd->insn_count = 1;
2450 dsd->dsc->pc_adjust = offset;
2453 /* Implementation of aarch64_insn_visitor method "adr". */
2456 aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2457 const int is_adrp, struct aarch64_insn_data *data)
2459 struct aarch64_displaced_step_data *dsd
2460 = (struct aarch64_displaced_step_data *) data;
2461 /* We know exactly the address the ADR{P,} instruction will compute.
2462 We can just write it to the destination register. */
2463 CORE_ADDR address = data->insn_addr + offset;
2467 /* Clear the lower 12 bits of the offset to get the 4K page. */
2468 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2472 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2475 dsd->dsc->pc_adjust = 4;
2476 emit_nop (dsd->insn_buf);
2477 dsd->insn_count = 1;
2480 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2483 aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2484 const unsigned rt, const int is64,
2485 struct aarch64_insn_data *data)
2487 struct aarch64_displaced_step_data *dsd
2488 = (struct aarch64_displaced_step_data *) data;
2489 CORE_ADDR address = data->insn_addr + offset;
2490 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2492 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2496 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2497 aarch64_register (rt, 1), zero);
2499 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2500 aarch64_register (rt, 1), zero);
2502 dsd->dsc->pc_adjust = 4;
2505 /* Implementation of aarch64_insn_visitor method "others". */
2508 aarch64_displaced_step_others (const uint32_t insn,
2509 struct aarch64_insn_data *data)
2511 struct aarch64_displaced_step_data *dsd
2512 = (struct aarch64_displaced_step_data *) data;
2514 aarch64_emit_insn (dsd->insn_buf, insn);
2515 dsd->insn_count = 1;
2517 if ((insn & 0xfffffc1f) == 0xd65f0000)
2520 dsd->dsc->pc_adjust = 0;
2523 dsd->dsc->pc_adjust = 4;
2526 static const struct aarch64_insn_visitor visitor =
2528 aarch64_displaced_step_b,
2529 aarch64_displaced_step_b_cond,
2530 aarch64_displaced_step_cb,
2531 aarch64_displaced_step_tb,
2532 aarch64_displaced_step_adr,
2533 aarch64_displaced_step_ldr_literal,
2534 aarch64_displaced_step_others,
2537 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2539 struct displaced_step_closure *
2540 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2541 CORE_ADDR from, CORE_ADDR to,
2542 struct regcache *regs)
2544 struct displaced_step_closure *dsc = NULL;
2545 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2546 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2547 struct aarch64_displaced_step_data dsd;
2550 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2553 /* Look for a Load Exclusive instruction which begins the sequence. */
2554 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
2556 /* We can't displaced step atomic sequences. */
2560 dsc = XCNEW (struct displaced_step_closure);
2561 dsd.base.insn_addr = from;
2566 aarch64_relocate_instruction (insn, &visitor,
2567 (struct aarch64_insn_data *) &dsd);
2568 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2570 if (dsd.insn_count != 0)
2574 /* Instruction can be relocated to scratch pad. Copy
2575 relocated instruction(s) there. */
2576 for (i = 0; i < dsd.insn_count; i++)
2578 if (debug_displaced)
2580 debug_printf ("displaced: writing insn ");
2581 debug_printf ("%.8x", dsd.insn_buf[i]);
2582 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2584 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2585 (ULONGEST) dsd.insn_buf[i]);
2597 /* Implement the "displaced_step_fixup" gdbarch method. */
2600 aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
2601 struct displaced_step_closure *dsc,
2602 CORE_ADDR from, CORE_ADDR to,
2603 struct regcache *regs)
2609 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2612 /* Condition is true. */
2614 else if (pc - to == 4)
2616 /* Condition is false. */
2620 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2623 if (dsc->pc_adjust != 0)
2625 if (debug_displaced)
2627 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2628 paddress (gdbarch, from), dsc->pc_adjust);
2630 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2631 from + dsc->pc_adjust);
2635 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2638 aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2639 struct displaced_step_closure *closure)
2644 /* Initialize the current architecture based on INFO. If possible,
2645 re-use an architecture from ARCHES, which is a list of
2646 architectures already created during this debugging session.
2648 Called e.g. at program startup, when reading a core file, and when
2649 reading a binary file. */
2651 static struct gdbarch *
2652 aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2654 struct gdbarch_tdep *tdep;
2655 struct gdbarch *gdbarch;
2656 struct gdbarch_list *best_arch;
2657 struct tdesc_arch_data *tdesc_data = NULL;
2658 const struct target_desc *tdesc = info.target_desc;
2660 int have_fpa_registers = 1;
2662 const struct tdesc_feature *feature;
2664 int num_pseudo_regs = 0;
2666 /* Ensure we always have a target descriptor. */
2667 if (!tdesc_has_registers (tdesc))
2668 tdesc = tdesc_aarch64;
2672 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2674 if (feature == NULL)
2677 tdesc_data = tdesc_data_alloc ();
2679 /* Validate the descriptor provides the mandatory core R registers
2680 and allocate their numbers. */
2681 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
2683 tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i,
2684 aarch64_r_register_names[i]);
2686 num_regs = AARCH64_X0_REGNUM + i;
2688 /* Look for the V registers. */
2689 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2692 /* Validate the descriptor provides the mandatory V registers
2693 and allocate their numbers. */
2694 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
2696 tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i,
2697 aarch64_v_register_names[i]);
2699 num_regs = AARCH64_V0_REGNUM + i;
2701 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
2702 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
2703 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
2704 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
2705 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
2710 tdesc_data_cleanup (tdesc_data);
2714 /* AArch64 code is always little-endian. */
2715 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
2717 /* If there is already a candidate, use it. */
2718 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2720 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2722 /* Found a match. */
2726 if (best_arch != NULL)
2728 if (tdesc_data != NULL)
2729 tdesc_data_cleanup (tdesc_data);
2730 return best_arch->gdbarch;
2733 tdep = XCNEW (struct gdbarch_tdep);
2734 gdbarch = gdbarch_alloc (&info, tdep);
2736 /* This should be low enough for everything. */
2737 tdep->lowest_pc = 0x20;
2738 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2739 tdep->jb_elt_size = 8;
2741 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
2742 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
2744 /* Frame handling. */
2745 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
2746 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
2747 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
2749 /* Advance PC across function entry code. */
2750 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
2752 /* The stack grows downward. */
2753 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2755 /* Breakpoint manipulation. */
2756 set_gdbarch_breakpoint_from_pc (gdbarch, aarch64_breakpoint_from_pc);
2757 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2758 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
2760 /* Information about registers, etc. */
2761 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
2762 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
2763 set_gdbarch_num_regs (gdbarch, num_regs);
2765 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
2766 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
2767 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
2768 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
2769 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
2770 set_tdesc_pseudo_register_reggroup_p (gdbarch,
2771 aarch64_pseudo_register_reggroup_p);
2774 set_gdbarch_short_bit (gdbarch, 16);
2775 set_gdbarch_int_bit (gdbarch, 32);
2776 set_gdbarch_float_bit (gdbarch, 32);
2777 set_gdbarch_double_bit (gdbarch, 64);
2778 set_gdbarch_long_double_bit (gdbarch, 128);
2779 set_gdbarch_long_bit (gdbarch, 64);
2780 set_gdbarch_long_long_bit (gdbarch, 64);
2781 set_gdbarch_ptr_bit (gdbarch, 64);
2782 set_gdbarch_char_signed (gdbarch, 0);
2783 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2784 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2785 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2787 /* Internal <-> external register number maps. */
2788 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
2790 /* Returning results. */
2791 set_gdbarch_return_value (gdbarch, aarch64_return_value);
2794 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
2796 /* Virtual tables. */
2797 set_gdbarch_vbit_in_delta (gdbarch, 1);
2799 /* Hook in the ABI-specific overrides, if they have been registered. */
2800 info.target_desc = tdesc;
2801 info.tdep_info = (void *) tdesc_data;
2802 gdbarch_init_osabi (info, gdbarch);
2804 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
2806 /* Add some default predicates. */
2807 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
2808 dwarf2_append_unwinders (gdbarch);
2809 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
2811 frame_base_set_default (gdbarch, &aarch64_normal_base);
2813 /* Now we have tuned the configuration, set a few final things,
2814 based on what the OS ABI has told us. */
2816 if (tdep->jb_pc >= 0)
2817 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
2819 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
2821 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2823 /* Add standard register aliases. */
2824 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
2825 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
2826 value_of_aarch64_user_reg,
2827 &aarch64_register_aliases[i].regnum);
2833 aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2835 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2840 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
2841 paddress (gdbarch, tdep->lowest_pc));
2844 /* Suppress warning from -Wmissing-prototypes. */
2845 extern initialize_file_ftype _initialize_aarch64_tdep;
2848 _initialize_aarch64_tdep (void)
2850 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
2853 initialize_tdesc_aarch64 ();
2855 /* Debug this file's internals. */
2856 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
2857 Set AArch64 debugging."), _("\
2858 Show AArch64 debugging."), _("\
2859 When on, AArch64 specific debugging is enabled."),
2862 &setdebuglist, &showdebuglist);
2865 /* AArch64 process record-replay related structures, defines etc. */
2867 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
2870 unsigned int reg_len = LENGTH; \
2873 REGS = XNEWVEC (uint32_t, reg_len); \
2874 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
2879 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
2882 unsigned int mem_len = LENGTH; \
2885 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
2886 memcpy(&MEMS->len, &RECORD_BUF[0], \
2887 sizeof(struct aarch64_mem_r) * LENGTH); \
2892 /* AArch64 record/replay structures and enumerations. */
2894 struct aarch64_mem_r
2896 uint64_t len; /* Record length. */
2897 uint64_t addr; /* Memory address. */
2900 enum aarch64_record_result
2902 AARCH64_RECORD_SUCCESS,
2903 AARCH64_RECORD_FAILURE,
2904 AARCH64_RECORD_UNSUPPORTED,
2905 AARCH64_RECORD_UNKNOWN
2908 typedef struct insn_decode_record_t
2910 struct gdbarch *gdbarch;
2911 struct regcache *regcache;
2912 CORE_ADDR this_addr; /* Address of insn to be recorded. */
2913 uint32_t aarch64_insn; /* Insn to be recorded. */
2914 uint32_t mem_rec_count; /* Count of memory records. */
2915 uint32_t reg_rec_count; /* Count of register records. */
2916 uint32_t *aarch64_regs; /* Registers to be recorded. */
2917 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
2918 } insn_decode_record;
2920 /* Record handler for data processing - register instructions. */
2923 aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
2925 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
2926 uint32_t record_buf[4];
2928 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
2929 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
2930 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
2932 if (!bit (aarch64_insn_r->aarch64_insn, 28))
2936 /* Logical (shifted register). */
2937 if (insn_bits24_27 == 0x0a)
2938 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
2940 else if (insn_bits24_27 == 0x0b)
2941 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
2943 return AARCH64_RECORD_UNKNOWN;
2945 record_buf[0] = reg_rd;
2946 aarch64_insn_r->reg_rec_count = 1;
2948 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
2952 if (insn_bits24_27 == 0x0b)
2954 /* Data-processing (3 source). */
2955 record_buf[0] = reg_rd;
2956 aarch64_insn_r->reg_rec_count = 1;
2958 else if (insn_bits24_27 == 0x0a)
2960 if (insn_bits21_23 == 0x00)
2962 /* Add/subtract (with carry). */
2963 record_buf[0] = reg_rd;
2964 aarch64_insn_r->reg_rec_count = 1;
2965 if (bit (aarch64_insn_r->aarch64_insn, 29))
2967 record_buf[1] = AARCH64_CPSR_REGNUM;
2968 aarch64_insn_r->reg_rec_count = 2;
2971 else if (insn_bits21_23 == 0x02)
2973 /* Conditional compare (register) and conditional compare
2974 (immediate) instructions. */
2975 record_buf[0] = AARCH64_CPSR_REGNUM;
2976 aarch64_insn_r->reg_rec_count = 1;
2978 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
2980 /* CConditional select. */
2981 /* Data-processing (2 source). */
2982 /* Data-processing (1 source). */
2983 record_buf[0] = reg_rd;
2984 aarch64_insn_r->reg_rec_count = 1;
2987 return AARCH64_RECORD_UNKNOWN;
2991 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
2993 return AARCH64_RECORD_SUCCESS;
2996 /* Record handler for data processing - immediate instructions. */
2999 aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3001 uint8_t reg_rd, insn_bit28, insn_bit23, insn_bits24_27, setflags;
3002 uint32_t record_buf[4];
3004 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3005 insn_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3006 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3007 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3009 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3010 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3011 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3013 record_buf[0] = reg_rd;
3014 aarch64_insn_r->reg_rec_count = 1;
3016 else if (insn_bits24_27 == 0x01)
3018 /* Add/Subtract (immediate). */
3019 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3020 record_buf[0] = reg_rd;
3021 aarch64_insn_r->reg_rec_count = 1;
3023 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3025 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3027 /* Logical (immediate). */
3028 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3029 record_buf[0] = reg_rd;
3030 aarch64_insn_r->reg_rec_count = 1;
3032 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3035 return AARCH64_RECORD_UNKNOWN;
3037 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3039 return AARCH64_RECORD_SUCCESS;
3042 /* Record handler for branch, exception generation and system instructions. */
3045 aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3047 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3048 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3049 uint32_t record_buf[4];
3051 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3052 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3053 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3055 if (insn_bits28_31 == 0x0d)
3057 /* Exception generation instructions. */
3058 if (insn_bits24_27 == 0x04)
3060 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3061 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3062 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
3064 ULONGEST svc_number;
3066 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3068 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3072 return AARCH64_RECORD_UNSUPPORTED;
3074 /* System instructions. */
3075 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3077 uint32_t reg_rt, reg_crn;
3079 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3080 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3082 /* Record rt in case of sysl and mrs instructions. */
3083 if (bit (aarch64_insn_r->aarch64_insn, 21))
3085 record_buf[0] = reg_rt;
3086 aarch64_insn_r->reg_rec_count = 1;
3088 /* Record cpsr for hint and msr(immediate) instructions. */
3089 else if (reg_crn == 0x02 || reg_crn == 0x04)
3091 record_buf[0] = AARCH64_CPSR_REGNUM;
3092 aarch64_insn_r->reg_rec_count = 1;
3095 /* Unconditional branch (register). */
3096 else if((insn_bits24_27 & 0x0e) == 0x06)
3098 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3099 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3100 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3103 return AARCH64_RECORD_UNKNOWN;
3105 /* Unconditional branch (immediate). */
3106 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3108 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3109 if (bit (aarch64_insn_r->aarch64_insn, 31))
3110 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3113 /* Compare & branch (immediate), Test & branch (immediate) and
3114 Conditional branch (immediate). */
3115 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3117 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3119 return AARCH64_RECORD_SUCCESS;
3122 /* Record handler for advanced SIMD load and store instructions. */
3125 aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3128 uint64_t addr_offset = 0;
3129 uint32_t record_buf[24];
3130 uint64_t record_buf_mem[24];
3131 uint32_t reg_rn, reg_rt;
3132 uint32_t reg_index = 0, mem_index = 0;
3133 uint8_t opcode_bits, size_bits;
3135 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3136 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3137 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3138 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3139 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3142 debug_printf ("Process record: Advanced SIMD load/store\n");
3144 /* Load/store single structure. */
3145 if (bit (aarch64_insn_r->aarch64_insn, 24))
3147 uint8_t sindex, scale, selem, esize, replicate = 0;
3148 scale = opcode_bits >> 2;
3149 selem = ((opcode_bits & 0x02) |
3150 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3154 if (size_bits & 0x01)
3155 return AARCH64_RECORD_UNKNOWN;
3158 if ((size_bits >> 1) & 0x01)
3159 return AARCH64_RECORD_UNKNOWN;
3160 if (size_bits & 0x01)
3162 if (!((opcode_bits >> 1) & 0x01))
3165 return AARCH64_RECORD_UNKNOWN;
3169 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3176 return AARCH64_RECORD_UNKNOWN;
3182 for (sindex = 0; sindex < selem; sindex++)
3184 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3185 reg_rt = (reg_rt + 1) % 32;
3189 for (sindex = 0; sindex < selem; sindex++)
3190 if (bit (aarch64_insn_r->aarch64_insn, 22))
3191 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3194 record_buf_mem[mem_index++] = esize / 8;
3195 record_buf_mem[mem_index++] = address + addr_offset;
3197 addr_offset = addr_offset + (esize / 8);
3198 reg_rt = (reg_rt + 1) % 32;
3201 /* Load/store multiple structure. */
3204 uint8_t selem, esize, rpt, elements;
3205 uint8_t eindex, rindex;
3207 esize = 8 << size_bits;
3208 if (bit (aarch64_insn_r->aarch64_insn, 30))
3209 elements = 128 / esize;
3211 elements = 64 / esize;
3213 switch (opcode_bits)
3215 /*LD/ST4 (4 Registers). */
3220 /*LD/ST1 (4 Registers). */
3225 /*LD/ST3 (3 Registers). */
3230 /*LD/ST1 (3 Registers). */
3235 /*LD/ST1 (1 Register). */
3240 /*LD/ST2 (2 Registers). */
3245 /*LD/ST1 (2 Registers). */
3251 return AARCH64_RECORD_UNSUPPORTED;
3254 for (rindex = 0; rindex < rpt; rindex++)
3255 for (eindex = 0; eindex < elements; eindex++)
3257 uint8_t reg_tt, sindex;
3258 reg_tt = (reg_rt + rindex) % 32;
3259 for (sindex = 0; sindex < selem; sindex++)
3261 if (bit (aarch64_insn_r->aarch64_insn, 22))
3262 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3265 record_buf_mem[mem_index++] = esize / 8;
3266 record_buf_mem[mem_index++] = address + addr_offset;
3268 addr_offset = addr_offset + (esize / 8);
3269 reg_tt = (reg_tt + 1) % 32;
3274 if (bit (aarch64_insn_r->aarch64_insn, 23))
3275 record_buf[reg_index++] = reg_rn;
3277 aarch64_insn_r->reg_rec_count = reg_index;
3278 aarch64_insn_r->mem_rec_count = mem_index / 2;
3279 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3281 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3283 return AARCH64_RECORD_SUCCESS;
3286 /* Record handler for load and store instructions. */
3289 aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3291 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3292 uint8_t insn_bit23, insn_bit21;
3293 uint8_t opc, size_bits, ld_flag, vector_flag;
3294 uint32_t reg_rn, reg_rt, reg_rt2;
3295 uint64_t datasize, offset;
3296 uint32_t record_buf[8];
3297 uint64_t record_buf_mem[8];
3300 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3301 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3302 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3303 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3304 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3305 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3306 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3307 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3308 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3309 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3310 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3312 /* Load/store exclusive. */
3313 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3316 debug_printf ("Process record: load/store exclusive\n");
3320 record_buf[0] = reg_rt;
3321 aarch64_insn_r->reg_rec_count = 1;
3324 record_buf[1] = reg_rt2;
3325 aarch64_insn_r->reg_rec_count = 2;
3331 datasize = (8 << size_bits) * 2;
3333 datasize = (8 << size_bits);
3334 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3336 record_buf_mem[0] = datasize / 8;
3337 record_buf_mem[1] = address;
3338 aarch64_insn_r->mem_rec_count = 1;
3341 /* Save register rs. */
3342 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3343 aarch64_insn_r->reg_rec_count = 1;
3347 /* Load register (literal) instructions decoding. */
3348 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3351 debug_printf ("Process record: load register (literal)\n");
3353 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3355 record_buf[0] = reg_rt;
3356 aarch64_insn_r->reg_rec_count = 1;
3358 /* All types of load/store pair instructions decoding. */
3359 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3362 debug_printf ("Process record: load/store pair\n");
3368 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3369 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3373 record_buf[0] = reg_rt;
3374 record_buf[1] = reg_rt2;
3376 aarch64_insn_r->reg_rec_count = 2;
3381 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3383 size_bits = size_bits >> 1;
3384 datasize = 8 << (2 + size_bits);
3385 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3386 offset = offset << (2 + size_bits);
3387 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3389 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3391 if (imm7_off & 0x40)
3392 address = address - offset;
3394 address = address + offset;
3397 record_buf_mem[0] = datasize / 8;
3398 record_buf_mem[1] = address;
3399 record_buf_mem[2] = datasize / 8;
3400 record_buf_mem[3] = address + (datasize / 8);
3401 aarch64_insn_r->mem_rec_count = 2;
3403 if (bit (aarch64_insn_r->aarch64_insn, 23))
3404 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3406 /* Load/store register (unsigned immediate) instructions. */
3407 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3409 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3416 if (size_bits != 0x03)
3419 return AARCH64_RECORD_UNKNOWN;
3423 debug_printf ("Process record: load/store (unsigned immediate):"
3424 " size %x V %d opc %x\n", size_bits, vector_flag,
3430 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3431 datasize = 8 << size_bits;
3432 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3434 offset = offset << size_bits;
3435 address = address + offset;
3437 record_buf_mem[0] = datasize >> 3;
3438 record_buf_mem[1] = address;
3439 aarch64_insn_r->mem_rec_count = 1;
3444 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3446 record_buf[0] = reg_rt;
3447 aarch64_insn_r->reg_rec_count = 1;
3450 /* Load/store register (register offset) instructions. */
3451 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3452 && insn_bits10_11 == 0x02 && insn_bit21)
3455 debug_printf ("Process record: load/store (register offset)\n");
3456 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3463 if (size_bits != 0x03)
3466 return AARCH64_RECORD_UNKNOWN;
3470 uint64_t reg_rm_val;
3471 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3472 bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
3473 if (bit (aarch64_insn_r->aarch64_insn, 12))
3474 offset = reg_rm_val << size_bits;
3476 offset = reg_rm_val;
3477 datasize = 8 << size_bits;
3478 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3480 address = address + offset;
3481 record_buf_mem[0] = datasize >> 3;
3482 record_buf_mem[1] = address;
3483 aarch64_insn_r->mem_rec_count = 1;
3488 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3490 record_buf[0] = reg_rt;
3491 aarch64_insn_r->reg_rec_count = 1;
3494 /* Load/store register (immediate and unprivileged) instructions. */
3495 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3500 debug_printf ("Process record: load/store "
3501 "(immediate and unprivileged)\n");
3503 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3510 if (size_bits != 0x03)
3513 return AARCH64_RECORD_UNKNOWN;
3518 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3519 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3520 datasize = 8 << size_bits;
3521 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3523 if (insn_bits10_11 != 0x01)
3525 if (imm9_off & 0x0100)
3526 address = address - offset;
3528 address = address + offset;
3530 record_buf_mem[0] = datasize >> 3;
3531 record_buf_mem[1] = address;
3532 aarch64_insn_r->mem_rec_count = 1;
3537 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3539 record_buf[0] = reg_rt;
3540 aarch64_insn_r->reg_rec_count = 1;
3542 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3543 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3545 /* Advanced SIMD load/store instructions. */
3547 return aarch64_record_asimd_load_store (aarch64_insn_r);
3549 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3551 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3553 return AARCH64_RECORD_SUCCESS;
3556 /* Record handler for data processing SIMD and floating point instructions. */
3559 aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3561 uint8_t insn_bit21, opcode, rmode, reg_rd;
3562 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3563 uint8_t insn_bits11_14;
3564 uint32_t record_buf[2];
3566 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3567 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3568 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3569 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3570 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3571 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3572 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3573 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3574 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3577 debug_printf ("Process record: data processing SIMD/FP: ");
3579 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3581 /* Floating point - fixed point conversion instructions. */
3585 debug_printf ("FP - fixed point conversion");
3587 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3588 record_buf[0] = reg_rd;
3590 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3592 /* Floating point - conditional compare instructions. */
3593 else if (insn_bits10_11 == 0x01)
3596 debug_printf ("FP - conditional compare");
3598 record_buf[0] = AARCH64_CPSR_REGNUM;
3600 /* Floating point - data processing (2-source) and
3601 conditional select instructions. */
3602 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3605 debug_printf ("FP - DP (2-source)");
3607 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3609 else if (insn_bits10_11 == 0x00)
3611 /* Floating point - immediate instructions. */
3612 if ((insn_bits12_15 & 0x01) == 0x01
3613 || (insn_bits12_15 & 0x07) == 0x04)
3616 debug_printf ("FP - immediate");
3617 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3619 /* Floating point - compare instructions. */
3620 else if ((insn_bits12_15 & 0x03) == 0x02)
3623 debug_printf ("FP - immediate");
3624 record_buf[0] = AARCH64_CPSR_REGNUM;
3626 /* Floating point - integer conversions instructions. */
3627 else if (insn_bits12_15 == 0x00)
3629 /* Convert float to integer instruction. */
3630 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3633 debug_printf ("float to int conversion");
3635 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3637 /* Convert integer to float instruction. */
3638 else if ((opcode >> 1) == 0x01 && !rmode)
3641 debug_printf ("int to float conversion");
3643 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3645 /* Move float to integer instruction. */
3646 else if ((opcode >> 1) == 0x03)
3649 debug_printf ("move float to int");
3651 if (!(opcode & 0x01))
3652 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3654 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3657 return AARCH64_RECORD_UNKNOWN;
3660 return AARCH64_RECORD_UNKNOWN;
3663 return AARCH64_RECORD_UNKNOWN;
3665 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
3668 debug_printf ("SIMD copy");
3670 /* Advanced SIMD copy instructions. */
3671 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
3672 && !bit (aarch64_insn_r->aarch64_insn, 15)
3673 && bit (aarch64_insn_r->aarch64_insn, 10))
3675 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
3676 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3678 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3681 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3683 /* All remaining floating point or advanced SIMD instructions. */
3687 debug_printf ("all remain");
3689 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3693 debug_printf ("\n");
3695 aarch64_insn_r->reg_rec_count++;
3696 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
3697 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3699 return AARCH64_RECORD_SUCCESS;
3702 /* Decodes insns type and invokes its record handler. */
3705 aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
3707 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
3709 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
3710 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
3711 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
3712 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3714 /* Data processing - immediate instructions. */
3715 if (!ins_bit26 && !ins_bit27 && ins_bit28)
3716 return aarch64_record_data_proc_imm (aarch64_insn_r);
3718 /* Branch, exception generation and system instructions. */
3719 if (ins_bit26 && !ins_bit27 && ins_bit28)
3720 return aarch64_record_branch_except_sys (aarch64_insn_r);
3722 /* Load and store instructions. */
3723 if (!ins_bit25 && ins_bit27)
3724 return aarch64_record_load_store (aarch64_insn_r);
3726 /* Data processing - register instructions. */
3727 if (ins_bit25 && !ins_bit26 && ins_bit27)
3728 return aarch64_record_data_proc_reg (aarch64_insn_r);
3730 /* Data processing - SIMD and floating point instructions. */
3731 if (ins_bit25 && ins_bit26 && ins_bit27)
3732 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
3734 return AARCH64_RECORD_UNSUPPORTED;
3737 /* Cleans up local record registers and memory allocations. */
3740 deallocate_reg_mem (insn_decode_record *record)
3742 xfree (record->aarch64_regs);
3743 xfree (record->aarch64_mems);
3746 /* Parse the current instruction and record the values of the registers and
3747 memory that will be changed in current instruction to record_arch_list
3748 return -1 if something is wrong. */
3751 aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3752 CORE_ADDR insn_addr)
3754 uint32_t rec_no = 0;
3755 uint8_t insn_size = 4;
3757 ULONGEST t_bit = 0, insn_id = 0;
3758 gdb_byte buf[insn_size];
3759 insn_decode_record aarch64_record;
3761 memset (&buf[0], 0, insn_size);
3762 memset (&aarch64_record, 0, sizeof (insn_decode_record));
3763 target_read_memory (insn_addr, &buf[0], insn_size);
3764 aarch64_record.aarch64_insn
3765 = (uint32_t) extract_unsigned_integer (&buf[0],
3767 gdbarch_byte_order (gdbarch));
3768 aarch64_record.regcache = regcache;
3769 aarch64_record.this_addr = insn_addr;
3770 aarch64_record.gdbarch = gdbarch;
3772 ret = aarch64_record_decode_insn_handler (&aarch64_record);
3773 if (ret == AARCH64_RECORD_UNSUPPORTED)
3775 printf_unfiltered (_("Process record does not support instruction "
3776 "0x%0x at address %s.\n"),
3777 aarch64_record.aarch64_insn,
3778 paddress (gdbarch, insn_addr));
3784 /* Record registers. */
3785 record_full_arch_list_add_reg (aarch64_record.regcache,
3787 /* Always record register CPSR. */
3788 record_full_arch_list_add_reg (aarch64_record.regcache,
3789 AARCH64_CPSR_REGNUM);
3790 if (aarch64_record.aarch64_regs)
3791 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
3792 if (record_full_arch_list_add_reg (aarch64_record.regcache,
3793 aarch64_record.aarch64_regs[rec_no]))
3796 /* Record memories. */
3797 if (aarch64_record.aarch64_mems)
3798 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
3799 if (record_full_arch_list_add_mem
3800 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
3801 aarch64_record.aarch64_mems[rec_no].len))
3804 if (record_full_arch_list_add_end ())
3808 deallocate_reg_mem (&aarch64_record);