1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
32 #include "arch-utils.h"
34 #include "frame-unwind.h"
35 #include "frame-base.h"
36 #include "trad-frame.h"
38 #include "dwarf2-frame.h"
40 #include "prologue-value.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
58 #include "features/aarch64.c"
60 #include "arch/aarch64-insn.h"
62 #include "opcode/aarch64.h"
65 #define submask(x) ((1L << ((x) + 1)) - 1)
66 #define bit(obj,st) (((obj) >> (st)) & 1)
67 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
69 /* Pseudo register base numbers. */
70 #define AARCH64_Q0_REGNUM 0
71 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
72 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
73 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
74 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
76 /* The standard register names, and all the valid aliases for them. */
79 const char *const name;
81 } aarch64_register_aliases[] =
83 /* 64-bit register names. */
84 {"fp", AARCH64_FP_REGNUM},
85 {"lr", AARCH64_LR_REGNUM},
86 {"sp", AARCH64_SP_REGNUM},
88 /* 32-bit register names. */
89 {"w0", AARCH64_X0_REGNUM + 0},
90 {"w1", AARCH64_X0_REGNUM + 1},
91 {"w2", AARCH64_X0_REGNUM + 2},
92 {"w3", AARCH64_X0_REGNUM + 3},
93 {"w4", AARCH64_X0_REGNUM + 4},
94 {"w5", AARCH64_X0_REGNUM + 5},
95 {"w6", AARCH64_X0_REGNUM + 6},
96 {"w7", AARCH64_X0_REGNUM + 7},
97 {"w8", AARCH64_X0_REGNUM + 8},
98 {"w9", AARCH64_X0_REGNUM + 9},
99 {"w10", AARCH64_X0_REGNUM + 10},
100 {"w11", AARCH64_X0_REGNUM + 11},
101 {"w12", AARCH64_X0_REGNUM + 12},
102 {"w13", AARCH64_X0_REGNUM + 13},
103 {"w14", AARCH64_X0_REGNUM + 14},
104 {"w15", AARCH64_X0_REGNUM + 15},
105 {"w16", AARCH64_X0_REGNUM + 16},
106 {"w17", AARCH64_X0_REGNUM + 17},
107 {"w18", AARCH64_X0_REGNUM + 18},
108 {"w19", AARCH64_X0_REGNUM + 19},
109 {"w20", AARCH64_X0_REGNUM + 20},
110 {"w21", AARCH64_X0_REGNUM + 21},
111 {"w22", AARCH64_X0_REGNUM + 22},
112 {"w23", AARCH64_X0_REGNUM + 23},
113 {"w24", AARCH64_X0_REGNUM + 24},
114 {"w25", AARCH64_X0_REGNUM + 25},
115 {"w26", AARCH64_X0_REGNUM + 26},
116 {"w27", AARCH64_X0_REGNUM + 27},
117 {"w28", AARCH64_X0_REGNUM + 28},
118 {"w29", AARCH64_X0_REGNUM + 29},
119 {"w30", AARCH64_X0_REGNUM + 30},
122 {"ip0", AARCH64_X0_REGNUM + 16},
123 {"ip1", AARCH64_X0_REGNUM + 17}
126 /* The required core 'R' registers. */
127 static const char *const aarch64_r_register_names[] =
129 /* These registers must appear in consecutive RAW register number
130 order and they must begin with AARCH64_X0_REGNUM! */
131 "x0", "x1", "x2", "x3",
132 "x4", "x5", "x6", "x7",
133 "x8", "x9", "x10", "x11",
134 "x12", "x13", "x14", "x15",
135 "x16", "x17", "x18", "x19",
136 "x20", "x21", "x22", "x23",
137 "x24", "x25", "x26", "x27",
138 "x28", "x29", "x30", "sp",
142 /* The FP/SIMD 'V' registers. */
143 static const char *const aarch64_v_register_names[] =
145 /* These registers must appear in consecutive RAW register number
146 order and they must begin with AARCH64_V0_REGNUM! */
147 "v0", "v1", "v2", "v3",
148 "v4", "v5", "v6", "v7",
149 "v8", "v9", "v10", "v11",
150 "v12", "v13", "v14", "v15",
151 "v16", "v17", "v18", "v19",
152 "v20", "v21", "v22", "v23",
153 "v24", "v25", "v26", "v27",
154 "v28", "v29", "v30", "v31",
159 /* AArch64 prologue cache structure. */
160 struct aarch64_prologue_cache
162 /* The program counter at the start of the function. It is used to
163 identify this frame as a prologue frame. */
166 /* The program counter at the time this frame was created; i.e. where
167 this function was called from. It is used to identify this frame as a
171 /* The stack pointer at the time this frame was created; i.e. the
172 caller's stack pointer when this function was called. It is used
173 to identify this frame. */
176 /* Is the target available to read from? */
179 /* The frame base for this frame is just prev_sp - frame size.
180 FRAMESIZE is the distance from the frame pointer to the
181 initial stack pointer. */
184 /* The register used to hold the frame pointer for this frame. */
187 /* Saved register offsets. */
188 struct trad_frame_saved_reg *saved_regs;
192 show_aarch64_debug (struct ui_file *file, int from_tty,
193 struct cmd_list_element *c, const char *value)
195 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
198 /* Analyze a prologue, looking for a recognizable stack frame
199 and frame pointer. Scan until we encounter a store that could
200 clobber the stack frame unexpectedly, or an unknown instruction. */
203 aarch64_analyze_prologue (struct gdbarch *gdbarch,
204 CORE_ADDR start, CORE_ADDR limit,
205 struct aarch64_prologue_cache *cache)
207 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
209 /* Track X registers and D registers in prologue. */
210 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
211 struct pv_area *stack;
212 struct cleanup *back_to;
214 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
215 regs[i] = pv_register (i, 0);
216 stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
217 back_to = make_cleanup_free_pv_area (stack);
219 for (; start < limit; start += 4)
224 insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
226 if (aarch64_decode_insn (insn, &inst, 1) != 0)
229 if (inst.opcode->iclass == addsub_imm
230 && (inst.opcode->op == OP_ADD
231 || strcmp ("sub", inst.opcode->name) == 0))
233 unsigned rd = inst.operands[0].reg.regno;
234 unsigned rn = inst.operands[1].reg.regno;
236 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
237 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
238 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
239 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
241 if (inst.opcode->op == OP_ADD)
243 regs[rd] = pv_add_constant (regs[rn],
244 inst.operands[2].imm.value);
248 regs[rd] = pv_add_constant (regs[rn],
249 -inst.operands[2].imm.value);
252 else if (inst.opcode->iclass == pcreladdr
253 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
255 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
256 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
258 regs[inst.operands[0].reg.regno] = pv_unknown ();
260 else if (inst.opcode->iclass == branch_imm)
262 /* Stop analysis on branch. */
265 else if (inst.opcode->iclass == condbranch)
267 /* Stop analysis on branch. */
270 else if (inst.opcode->iclass == branch_reg)
272 /* Stop analysis on branch. */
275 else if (inst.opcode->iclass == compbranch)
277 /* Stop analysis on branch. */
280 else if (inst.opcode->op == OP_MOVZ)
282 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
283 regs[inst.operands[0].reg.regno] = pv_unknown ();
285 else if (inst.opcode->iclass == log_shift
286 && strcmp (inst.opcode->name, "orr") == 0)
288 unsigned rd = inst.operands[0].reg.regno;
289 unsigned rn = inst.operands[1].reg.regno;
290 unsigned rm = inst.operands[2].reg.regno;
292 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
293 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
294 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
296 if (inst.operands[2].shifter.amount == 0
297 && rn == AARCH64_SP_REGNUM)
303 debug_printf ("aarch64: prologue analysis gave up "
304 "addr=%s opcode=0x%x (orr x register)\n",
305 core_addr_to_string_nz (start), insn);
310 else if (inst.opcode->op == OP_STUR)
312 unsigned rt = inst.operands[0].reg.regno;
313 unsigned rn = inst.operands[1].addr.base_regno;
315 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
317 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
318 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
319 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
320 gdb_assert (!inst.operands[1].addr.offset.is_reg);
322 pv_area_store (stack, pv_add_constant (regs[rn],
323 inst.operands[1].addr.offset.imm),
324 is64 ? 8 : 4, regs[rt]);
326 else if ((inst.opcode->iclass == ldstpair_off
327 || (inst.opcode->iclass == ldstpair_indexed
328 && inst.operands[2].addr.preind))
329 && strcmp ("stp", inst.opcode->name) == 0)
331 /* STP with addressing mode Pre-indexed and Base register. */
334 unsigned rn = inst.operands[2].addr.base_regno;
335 int32_t imm = inst.operands[2].addr.offset.imm;
337 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
338 || inst.operands[0].type == AARCH64_OPND_Ft);
339 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
340 || inst.operands[1].type == AARCH64_OPND_Ft2);
341 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
342 gdb_assert (!inst.operands[2].addr.offset.is_reg);
344 /* If recording this store would invalidate the store area
345 (perhaps because rn is not known) then we should abandon
346 further prologue analysis. */
347 if (pv_area_store_would_trash (stack,
348 pv_add_constant (regs[rn], imm)))
351 if (pv_area_store_would_trash (stack,
352 pv_add_constant (regs[rn], imm + 8)))
355 rt1 = inst.operands[0].reg.regno;
356 rt2 = inst.operands[1].reg.regno;
357 if (inst.operands[0].type == AARCH64_OPND_Ft)
359 /* Only bottom 64-bit of each V register (D register) need
361 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
362 rt1 += AARCH64_X_REGISTER_COUNT;
363 rt2 += AARCH64_X_REGISTER_COUNT;
366 pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
368 pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
371 if (inst.operands[2].addr.writeback)
372 regs[rn] = pv_add_constant (regs[rn], imm);
375 else if (inst.opcode->iclass == testbranch)
377 /* Stop analysis on branch. */
384 debug_printf ("aarch64: prologue analysis gave up addr=%s"
386 core_addr_to_string_nz (start), insn);
394 do_cleanups (back_to);
398 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
400 /* Frame pointer is fp. Frame size is constant. */
401 cache->framereg = AARCH64_FP_REGNUM;
402 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
404 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
406 /* Try the stack pointer. */
407 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
408 cache->framereg = AARCH64_SP_REGNUM;
412 /* We're just out of luck. We don't know where the frame is. */
413 cache->framereg = -1;
414 cache->framesize = 0;
417 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
421 if (pv_area_find_reg (stack, gdbarch, i, &offset))
422 cache->saved_regs[i].addr = offset;
425 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
427 int regnum = gdbarch_num_regs (gdbarch);
430 if (pv_area_find_reg (stack, gdbarch, i + AARCH64_X_REGISTER_COUNT,
432 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
435 do_cleanups (back_to);
439 /* Implement the "skip_prologue" gdbarch method. */
442 aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
444 CORE_ADDR func_addr, limit_pc;
446 /* See if we can determine the end of the prologue via the symbol
447 table. If so, then return either PC, or the PC after the
448 prologue, whichever is greater. */
449 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
451 CORE_ADDR post_prologue_pc
452 = skip_prologue_using_sal (gdbarch, func_addr);
454 if (post_prologue_pc != 0)
455 return std::max (pc, post_prologue_pc);
458 /* Can't determine prologue from the symbol table, need to examine
461 /* Find an upper limit on the function prologue using the debug
462 information. If the debug information could not be used to
463 provide that bound, then use an arbitrary large number as the
465 limit_pc = skip_prologue_using_sal (gdbarch, pc);
467 limit_pc = pc + 128; /* Magic. */
469 /* Try disassembling prologue. */
470 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
473 /* Scan the function prologue for THIS_FRAME and populate the prologue
477 aarch64_scan_prologue (struct frame_info *this_frame,
478 struct aarch64_prologue_cache *cache)
480 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
481 CORE_ADDR prologue_start;
482 CORE_ADDR prologue_end;
483 CORE_ADDR prev_pc = get_frame_pc (this_frame);
484 struct gdbarch *gdbarch = get_frame_arch (this_frame);
486 cache->prev_pc = prev_pc;
488 /* Assume we do not find a frame. */
489 cache->framereg = -1;
490 cache->framesize = 0;
492 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
495 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
499 /* No line info so use the current PC. */
500 prologue_end = prev_pc;
502 else if (sal.end < prologue_end)
504 /* The next line begins after the function end. */
505 prologue_end = sal.end;
508 prologue_end = std::min (prologue_end, prev_pc);
509 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
515 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
519 cache->framereg = AARCH64_FP_REGNUM;
520 cache->framesize = 16;
521 cache->saved_regs[29].addr = 0;
522 cache->saved_regs[30].addr = 8;
526 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
527 function may throw an exception if the inferior's registers or memory is
531 aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
532 struct aarch64_prologue_cache *cache)
534 CORE_ADDR unwound_fp;
537 aarch64_scan_prologue (this_frame, cache);
539 if (cache->framereg == -1)
542 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
546 cache->prev_sp = unwound_fp + cache->framesize;
548 /* Calculate actual addresses of saved registers using offsets
549 determined by aarch64_analyze_prologue. */
550 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
551 if (trad_frame_addr_p (cache->saved_regs, reg))
552 cache->saved_regs[reg].addr += cache->prev_sp;
554 cache->func = get_frame_func (this_frame);
556 cache->available_p = 1;
559 /* Allocate and fill in *THIS_CACHE with information about the prologue of
560 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
561 Return a pointer to the current aarch64_prologue_cache in
564 static struct aarch64_prologue_cache *
565 aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
567 struct aarch64_prologue_cache *cache;
569 if (*this_cache != NULL)
570 return (struct aarch64_prologue_cache *) *this_cache;
572 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
573 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
578 aarch64_make_prologue_cache_1 (this_frame, cache);
580 CATCH (ex, RETURN_MASK_ERROR)
582 if (ex.error != NOT_AVAILABLE_ERROR)
583 throw_exception (ex);
590 /* Implement the "stop_reason" frame_unwind method. */
592 static enum unwind_stop_reason
593 aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
596 struct aarch64_prologue_cache *cache
597 = aarch64_make_prologue_cache (this_frame, this_cache);
599 if (!cache->available_p)
600 return UNWIND_UNAVAILABLE;
602 /* Halt the backtrace at "_start". */
603 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
604 return UNWIND_OUTERMOST;
606 /* We've hit a wall, stop. */
607 if (cache->prev_sp == 0)
608 return UNWIND_OUTERMOST;
610 return UNWIND_NO_REASON;
613 /* Our frame ID for a normal frame is the current function's starting
614 PC and the caller's SP when we were called. */
617 aarch64_prologue_this_id (struct frame_info *this_frame,
618 void **this_cache, struct frame_id *this_id)
620 struct aarch64_prologue_cache *cache
621 = aarch64_make_prologue_cache (this_frame, this_cache);
623 if (!cache->available_p)
624 *this_id = frame_id_build_unavailable_stack (cache->func);
626 *this_id = frame_id_build (cache->prev_sp, cache->func);
629 /* Implement the "prev_register" frame_unwind method. */
631 static struct value *
632 aarch64_prologue_prev_register (struct frame_info *this_frame,
633 void **this_cache, int prev_regnum)
635 struct aarch64_prologue_cache *cache
636 = aarch64_make_prologue_cache (this_frame, this_cache);
638 /* If we are asked to unwind the PC, then we need to return the LR
639 instead. The prologue may save PC, but it will point into this
640 frame's prologue, not the next frame's resume location. */
641 if (prev_regnum == AARCH64_PC_REGNUM)
645 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
646 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
649 /* SP is generally not saved to the stack, but this frame is
650 identified by the next frame's stack pointer at the time of the
651 call. The value was already reconstructed into PREV_SP. */
664 if (prev_regnum == AARCH64_SP_REGNUM)
665 return frame_unwind_got_constant (this_frame, prev_regnum,
668 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
672 /* AArch64 prologue unwinder. */
673 struct frame_unwind aarch64_prologue_unwind =
676 aarch64_prologue_frame_unwind_stop_reason,
677 aarch64_prologue_this_id,
678 aarch64_prologue_prev_register,
680 default_frame_sniffer
683 /* Allocate and fill in *THIS_CACHE with information about the prologue of
684 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
685 Return a pointer to the current aarch64_prologue_cache in
688 static struct aarch64_prologue_cache *
689 aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
691 struct aarch64_prologue_cache *cache;
693 if (*this_cache != NULL)
694 return (struct aarch64_prologue_cache *) *this_cache;
696 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
697 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
702 cache->prev_sp = get_frame_register_unsigned (this_frame,
704 cache->prev_pc = get_frame_pc (this_frame);
705 cache->available_p = 1;
707 CATCH (ex, RETURN_MASK_ERROR)
709 if (ex.error != NOT_AVAILABLE_ERROR)
710 throw_exception (ex);
717 /* Implement the "stop_reason" frame_unwind method. */
719 static enum unwind_stop_reason
720 aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
723 struct aarch64_prologue_cache *cache
724 = aarch64_make_stub_cache (this_frame, this_cache);
726 if (!cache->available_p)
727 return UNWIND_UNAVAILABLE;
729 return UNWIND_NO_REASON;
732 /* Our frame ID for a stub frame is the current SP and LR. */
735 aarch64_stub_this_id (struct frame_info *this_frame,
736 void **this_cache, struct frame_id *this_id)
738 struct aarch64_prologue_cache *cache
739 = aarch64_make_stub_cache (this_frame, this_cache);
741 if (cache->available_p)
742 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
744 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
747 /* Implement the "sniffer" frame_unwind method. */
750 aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
751 struct frame_info *this_frame,
752 void **this_prologue_cache)
754 CORE_ADDR addr_in_block;
757 addr_in_block = get_frame_address_in_block (this_frame);
758 if (in_plt_section (addr_in_block)
759 /* We also use the stub winder if the target memory is unreadable
760 to avoid having the prologue unwinder trying to read it. */
761 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
767 /* AArch64 stub unwinder. */
768 struct frame_unwind aarch64_stub_unwind =
771 aarch64_stub_frame_unwind_stop_reason,
772 aarch64_stub_this_id,
773 aarch64_prologue_prev_register,
775 aarch64_stub_unwind_sniffer
778 /* Return the frame base address of *THIS_FRAME. */
781 aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
783 struct aarch64_prologue_cache *cache
784 = aarch64_make_prologue_cache (this_frame, this_cache);
786 return cache->prev_sp - cache->framesize;
789 /* AArch64 default frame base information. */
790 struct frame_base aarch64_normal_base =
792 &aarch64_prologue_unwind,
793 aarch64_normal_frame_base,
794 aarch64_normal_frame_base,
795 aarch64_normal_frame_base
798 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
799 dummy frame. The frame ID's base needs to match the TOS value
800 saved by save_dummy_frame_tos () and returned from
801 aarch64_push_dummy_call, and the PC needs to match the dummy
802 frame's breakpoint. */
804 static struct frame_id
805 aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
807 return frame_id_build (get_frame_register_unsigned (this_frame,
809 get_frame_pc (this_frame));
812 /* Implement the "unwind_pc" gdbarch method. */
815 aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
818 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
823 /* Implement the "unwind_sp" gdbarch method. */
826 aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
828 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
831 /* Return the value of the REGNUM register in the previous frame of
834 static struct value *
835 aarch64_dwarf2_prev_register (struct frame_info *this_frame,
836 void **this_cache, int regnum)
842 case AARCH64_PC_REGNUM:
843 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
844 return frame_unwind_got_constant (this_frame, regnum, lr);
847 internal_error (__FILE__, __LINE__,
848 _("Unexpected register %d"), regnum);
852 /* Implement the "init_reg" dwarf2_frame_ops method. */
855 aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
856 struct dwarf2_frame_state_reg *reg,
857 struct frame_info *this_frame)
861 case AARCH64_PC_REGNUM:
862 reg->how = DWARF2_FRAME_REG_FN;
863 reg->loc.fn = aarch64_dwarf2_prev_register;
865 case AARCH64_SP_REGNUM:
866 reg->how = DWARF2_FRAME_REG_CFA;
871 /* When arguments must be pushed onto the stack, they go on in reverse
872 order. The code below implements a FILO (stack) to do this. */
876 /* Value to pass on stack. It can be NULL if this item is for stack
878 const gdb_byte *data;
880 /* Size in bytes of value to pass on stack. */
884 DEF_VEC_O (stack_item_t);
886 /* Return the alignment (in bytes) of the given type. */
889 aarch64_type_align (struct type *t)
895 t = check_typedef (t);
896 switch (TYPE_CODE (t))
899 /* Should never happen. */
900 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
908 case TYPE_CODE_RANGE:
909 case TYPE_CODE_BITSTRING:
913 return TYPE_LENGTH (t);
915 case TYPE_CODE_ARRAY:
918 /* Use the natural alignment for vector types (the same for
919 scalar type), but the maximum alignment is 128-bit. */
920 if (TYPE_LENGTH (t) > 16)
923 return TYPE_LENGTH (t);
926 return aarch64_type_align (TYPE_TARGET_TYPE (t));
927 case TYPE_CODE_COMPLEX:
928 return aarch64_type_align (TYPE_TARGET_TYPE (t));
930 case TYPE_CODE_STRUCT:
931 case TYPE_CODE_UNION:
933 for (n = 0; n < TYPE_NFIELDS (t); n++)
935 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
943 /* Return 1 if *TY is a homogeneous floating-point aggregate or
944 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
945 document; otherwise return 0. */
948 is_hfa_or_hva (struct type *ty)
950 switch (TYPE_CODE (ty))
952 case TYPE_CODE_ARRAY:
954 struct type *target_ty = TYPE_TARGET_TYPE (ty);
956 if (TYPE_VECTOR (ty))
959 if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */
960 && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */
961 || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */
962 && TYPE_VECTOR (target_ty))))
967 case TYPE_CODE_UNION:
968 case TYPE_CODE_STRUCT:
970 /* HFA or HVA has at most four members. */
971 if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
973 struct type *member0_type;
975 member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
976 if (TYPE_CODE (member0_type) == TYPE_CODE_FLT
977 || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY
978 && TYPE_VECTOR (member0_type)))
982 for (i = 0; i < TYPE_NFIELDS (ty); i++)
984 struct type *member1_type;
986 member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i));
987 if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type)
988 || (TYPE_LENGTH (member0_type)
989 != TYPE_LENGTH (member1_type)))
1005 /* AArch64 function call information structure. */
1006 struct aarch64_call_info
1008 /* the current argument number. */
1011 /* The next general purpose register number, equivalent to NGRN as
1012 described in the AArch64 Procedure Call Standard. */
1015 /* The next SIMD and floating point register number, equivalent to
1016 NSRN as described in the AArch64 Procedure Call Standard. */
1019 /* The next stacked argument address, equivalent to NSAA as
1020 described in the AArch64 Procedure Call Standard. */
1023 /* Stack item vector. */
1024 VEC(stack_item_t) *si;
1027 /* Pass a value in a sequence of consecutive X registers. The caller
1028 is responsbile for ensuring sufficient registers are available. */
1031 pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1032 struct aarch64_call_info *info, struct type *type,
1035 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1036 int len = TYPE_LENGTH (type);
1037 enum type_code typecode = TYPE_CODE (type);
1038 int regnum = AARCH64_X0_REGNUM + info->ngrn;
1039 const bfd_byte *buf = value_contents (arg);
1045 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1046 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1050 /* Adjust sub-word struct/union args when big-endian. */
1051 if (byte_order == BFD_ENDIAN_BIG
1052 && partial_len < X_REGISTER_SIZE
1053 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1054 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1058 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1059 gdbarch_register_name (gdbarch, regnum),
1060 phex (regval, X_REGISTER_SIZE));
1062 regcache_cooked_write_unsigned (regcache, regnum, regval);
1069 /* Attempt to marshall a value in a V register. Return 1 if
1070 successful, or 0 if insufficient registers are available. This
1071 function, unlike the equivalent pass_in_x() function does not
1072 handle arguments spread across multiple registers. */
1075 pass_in_v (struct gdbarch *gdbarch,
1076 struct regcache *regcache,
1077 struct aarch64_call_info *info,
1078 int len, const bfd_byte *buf)
1082 int regnum = AARCH64_V0_REGNUM + info->nsrn;
1083 gdb_byte reg[V_REGISTER_SIZE];
1088 memset (reg, 0, sizeof (reg));
1089 /* PCS C.1, the argument is allocated to the least significant
1090 bits of V register. */
1091 memcpy (reg, buf, len);
1092 regcache_cooked_write (regcache, regnum, reg);
1096 debug_printf ("arg %d in %s\n", info->argnum,
1097 gdbarch_register_name (gdbarch, regnum));
1105 /* Marshall an argument onto the stack. */
1108 pass_on_stack (struct aarch64_call_info *info, struct type *type,
1111 const bfd_byte *buf = value_contents (arg);
1112 int len = TYPE_LENGTH (type);
1118 align = aarch64_type_align (type);
1120 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1121 Natural alignment of the argument's type. */
1122 align = align_up (align, 8);
1124 /* The AArch64 PCS requires at most doubleword alignment. */
1130 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1136 VEC_safe_push (stack_item_t, info->si, &item);
1139 if (info->nsaa & (align - 1))
1141 /* Push stack alignment padding. */
1142 int pad = align - (info->nsaa & (align - 1));
1147 VEC_safe_push (stack_item_t, info->si, &item);
1152 /* Marshall an argument into a sequence of one or more consecutive X
1153 registers or, if insufficient X registers are available then onto
1157 pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1158 struct aarch64_call_info *info, struct type *type,
1161 int len = TYPE_LENGTH (type);
1162 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1164 /* PCS C.13 - Pass in registers if we have enough spare */
1165 if (info->ngrn + nregs <= 8)
1167 pass_in_x (gdbarch, regcache, info, type, arg);
1168 info->ngrn += nregs;
1173 pass_on_stack (info, type, arg);
1177 /* Pass a value in a V register, or on the stack if insufficient are
1181 pass_in_v_or_stack (struct gdbarch *gdbarch,
1182 struct regcache *regcache,
1183 struct aarch64_call_info *info,
1187 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type),
1188 value_contents (arg)))
1189 pass_on_stack (info, type, arg);
1192 /* Implement the "push_dummy_call" gdbarch method. */
1195 aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1196 struct regcache *regcache, CORE_ADDR bp_addr,
1198 struct value **args, CORE_ADDR sp, int struct_return,
1199 CORE_ADDR struct_addr)
1202 struct aarch64_call_info info;
1203 struct type *func_type;
1204 struct type *return_type;
1205 int lang_struct_return;
1207 memset (&info, 0, sizeof (info));
1209 /* We need to know what the type of the called function is in order
1210 to determine the number of named/anonymous arguments for the
1211 actual argument placement, and the return type in order to handle
1212 return value correctly.
1214 The generic code above us views the decision of return in memory
1215 or return in registers as a two stage processes. The language
1216 handler is consulted first and may decide to return in memory (eg
1217 class with copy constructor returned by value), this will cause
1218 the generic code to allocate space AND insert an initial leading
1221 If the language code does not decide to pass in memory then the
1222 target code is consulted.
1224 If the language code decides to pass in memory we want to move
1225 the pointer inserted as the initial argument from the argument
1226 list and into X8, the conventional AArch64 struct return pointer
1229 This is slightly awkward, ideally the flag "lang_struct_return"
1230 would be passed to the targets implementation of push_dummy_call.
1231 Rather that change the target interface we call the language code
1232 directly ourselves. */
1234 func_type = check_typedef (value_type (function));
1236 /* Dereference function pointer types. */
1237 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1238 func_type = TYPE_TARGET_TYPE (func_type);
1240 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1241 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1243 /* If language_pass_by_reference () returned true we will have been
1244 given an additional initial argument, a hidden pointer to the
1245 return slot in memory. */
1246 return_type = TYPE_TARGET_TYPE (func_type);
1247 lang_struct_return = language_pass_by_reference (return_type);
1249 /* Set the return address. For the AArch64, the return breakpoint
1250 is always at BP_ADDR. */
1251 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1253 /* If we were given an initial argument for the return slot because
1254 lang_struct_return was true, lose it. */
1255 if (lang_struct_return)
1261 /* The struct_return pointer occupies X8. */
1262 if (struct_return || lang_struct_return)
1266 debug_printf ("struct return in %s = 0x%s\n",
1267 gdbarch_register_name (gdbarch,
1268 AARCH64_STRUCT_RETURN_REGNUM),
1269 paddress (gdbarch, struct_addr));
1271 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1275 for (argnum = 0; argnum < nargs; argnum++)
1277 struct value *arg = args[argnum];
1278 struct type *arg_type;
1281 arg_type = check_typedef (value_type (arg));
1282 len = TYPE_LENGTH (arg_type);
1284 switch (TYPE_CODE (arg_type))
1287 case TYPE_CODE_BOOL:
1288 case TYPE_CODE_CHAR:
1289 case TYPE_CODE_RANGE:
1290 case TYPE_CODE_ENUM:
1293 /* Promote to 32 bit integer. */
1294 if (TYPE_UNSIGNED (arg_type))
1295 arg_type = builtin_type (gdbarch)->builtin_uint32;
1297 arg_type = builtin_type (gdbarch)->builtin_int32;
1298 arg = value_cast (arg_type, arg);
1300 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1303 case TYPE_CODE_COMPLEX:
1306 const bfd_byte *buf = value_contents (arg);
1307 struct type *target_type =
1308 check_typedef (TYPE_TARGET_TYPE (arg_type));
1310 pass_in_v (gdbarch, regcache, &info,
1311 TYPE_LENGTH (target_type), buf);
1312 pass_in_v (gdbarch, regcache, &info,
1313 TYPE_LENGTH (target_type),
1314 buf + TYPE_LENGTH (target_type));
1319 pass_on_stack (&info, arg_type, arg);
1323 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1326 case TYPE_CODE_STRUCT:
1327 case TYPE_CODE_ARRAY:
1328 case TYPE_CODE_UNION:
1329 if (is_hfa_or_hva (arg_type))
1331 int elements = TYPE_NFIELDS (arg_type);
1333 /* Homogeneous Aggregates */
1334 if (info.nsrn + elements < 8)
1338 for (i = 0; i < elements; i++)
1340 /* We know that we have sufficient registers
1341 available therefore this will never fallback
1343 struct value *field =
1344 value_primitive_field (arg, 0, i, arg_type);
1345 struct type *field_type =
1346 check_typedef (value_type (field));
1348 pass_in_v_or_stack (gdbarch, regcache, &info,
1355 pass_on_stack (&info, arg_type, arg);
1358 else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
1359 && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
1361 /* Short vector types are passed in V registers. */
1362 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1366 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1367 invisible reference. */
1369 /* Allocate aligned storage. */
1370 sp = align_down (sp - len, 16);
1372 /* Write the real data into the stack. */
1373 write_memory (sp, value_contents (arg), len);
1375 /* Construct the indirection. */
1376 arg_type = lookup_pointer_type (arg_type);
1377 arg = value_from_pointer (arg_type, sp);
1378 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1381 /* PCS C.15 / C.18 multiple values pass. */
1382 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1386 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1391 /* Make sure stack retains 16 byte alignment. */
1393 sp -= 16 - (info.nsaa & 15);
1395 while (!VEC_empty (stack_item_t, info.si))
1397 stack_item_t *si = VEC_last (stack_item_t, info.si);
1400 if (si->data != NULL)
1401 write_memory (sp, si->data, si->len);
1402 VEC_pop (stack_item_t, info.si);
1405 VEC_free (stack_item_t, info.si);
1407 /* Finally, update the SP register. */
1408 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1413 /* Implement the "frame_align" gdbarch method. */
1416 aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1418 /* Align the stack to sixteen bytes. */
1419 return sp & ~(CORE_ADDR) 15;
1422 /* Return the type for an AdvSISD Q register. */
1424 static struct type *
1425 aarch64_vnq_type (struct gdbarch *gdbarch)
1427 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1429 if (tdep->vnq_type == NULL)
1434 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1437 elem = builtin_type (gdbarch)->builtin_uint128;
1438 append_composite_type_field (t, "u", elem);
1440 elem = builtin_type (gdbarch)->builtin_int128;
1441 append_composite_type_field (t, "s", elem);
1446 return tdep->vnq_type;
1449 /* Return the type for an AdvSISD D register. */
1451 static struct type *
1452 aarch64_vnd_type (struct gdbarch *gdbarch)
1454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1456 if (tdep->vnd_type == NULL)
1461 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1464 elem = builtin_type (gdbarch)->builtin_double;
1465 append_composite_type_field (t, "f", elem);
1467 elem = builtin_type (gdbarch)->builtin_uint64;
1468 append_composite_type_field (t, "u", elem);
1470 elem = builtin_type (gdbarch)->builtin_int64;
1471 append_composite_type_field (t, "s", elem);
1476 return tdep->vnd_type;
1479 /* Return the type for an AdvSISD S register. */
1481 static struct type *
1482 aarch64_vns_type (struct gdbarch *gdbarch)
1484 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1486 if (tdep->vns_type == NULL)
1491 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1494 elem = builtin_type (gdbarch)->builtin_float;
1495 append_composite_type_field (t, "f", elem);
1497 elem = builtin_type (gdbarch)->builtin_uint32;
1498 append_composite_type_field (t, "u", elem);
1500 elem = builtin_type (gdbarch)->builtin_int32;
1501 append_composite_type_field (t, "s", elem);
1506 return tdep->vns_type;
1509 /* Return the type for an AdvSISD H register. */
1511 static struct type *
1512 aarch64_vnh_type (struct gdbarch *gdbarch)
1514 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1516 if (tdep->vnh_type == NULL)
1521 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1524 elem = builtin_type (gdbarch)->builtin_uint16;
1525 append_composite_type_field (t, "u", elem);
1527 elem = builtin_type (gdbarch)->builtin_int16;
1528 append_composite_type_field (t, "s", elem);
1533 return tdep->vnh_type;
1536 /* Return the type for an AdvSISD B register. */
1538 static struct type *
1539 aarch64_vnb_type (struct gdbarch *gdbarch)
1541 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1543 if (tdep->vnb_type == NULL)
1548 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1551 elem = builtin_type (gdbarch)->builtin_uint8;
1552 append_composite_type_field (t, "u", elem);
1554 elem = builtin_type (gdbarch)->builtin_int8;
1555 append_composite_type_field (t, "s", elem);
1560 return tdep->vnb_type;
1563 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1566 aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1568 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1569 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1571 if (reg == AARCH64_DWARF_SP)
1572 return AARCH64_SP_REGNUM;
1574 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1575 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1581 /* Implement the "print_insn" gdbarch method. */
1584 aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1586 info->symbols = NULL;
1587 return print_insn_aarch64 (memaddr, info);
1590 /* AArch64 BRK software debug mode instruction.
1591 Note that AArch64 code is always little-endian.
1592 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1593 constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
1595 typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
1597 /* Extract from an array REGS containing the (raw) register state a
1598 function return value of type TYPE, and copy that, in virtual
1599 format, into VALBUF. */
1602 aarch64_extract_return_value (struct type *type, struct regcache *regs,
1605 struct gdbarch *gdbarch = get_regcache_arch (regs);
1606 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1608 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1610 bfd_byte buf[V_REGISTER_SIZE];
1611 int len = TYPE_LENGTH (type);
1613 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1614 memcpy (valbuf, buf, len);
1616 else if (TYPE_CODE (type) == TYPE_CODE_INT
1617 || TYPE_CODE (type) == TYPE_CODE_CHAR
1618 || TYPE_CODE (type) == TYPE_CODE_BOOL
1619 || TYPE_CODE (type) == TYPE_CODE_PTR
1620 || TYPE_CODE (type) == TYPE_CODE_REF
1621 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1623 /* If the the type is a plain integer, then the access is
1624 straight-forward. Otherwise we have to play around a bit
1626 int len = TYPE_LENGTH (type);
1627 int regno = AARCH64_X0_REGNUM;
1632 /* By using store_unsigned_integer we avoid having to do
1633 anything special for small big-endian values. */
1634 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1635 store_unsigned_integer (valbuf,
1636 (len > X_REGISTER_SIZE
1637 ? X_REGISTER_SIZE : len), byte_order, tmp);
1638 len -= X_REGISTER_SIZE;
1639 valbuf += X_REGISTER_SIZE;
1642 else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX)
1644 int regno = AARCH64_V0_REGNUM;
1645 bfd_byte buf[V_REGISTER_SIZE];
1646 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1647 int len = TYPE_LENGTH (target_type);
1649 regcache_cooked_read (regs, regno, buf);
1650 memcpy (valbuf, buf, len);
1652 regcache_cooked_read (regs, regno + 1, buf);
1653 memcpy (valbuf, buf, len);
1656 else if (is_hfa_or_hva (type))
1658 int elements = TYPE_NFIELDS (type);
1659 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1660 int len = TYPE_LENGTH (member_type);
1663 for (i = 0; i < elements; i++)
1665 int regno = AARCH64_V0_REGNUM + i;
1666 bfd_byte buf[V_REGISTER_SIZE];
1670 debug_printf ("read HFA or HVA return value element %d from %s\n",
1672 gdbarch_register_name (gdbarch, regno));
1674 regcache_cooked_read (regs, regno, buf);
1676 memcpy (valbuf, buf, len);
1680 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1681 && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
1683 /* Short vector is returned in V register. */
1684 gdb_byte buf[V_REGISTER_SIZE];
1686 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1687 memcpy (valbuf, buf, TYPE_LENGTH (type));
1691 /* For a structure or union the behaviour is as if the value had
1692 been stored to word-aligned memory and then loaded into
1693 registers with 64-bit load instruction(s). */
1694 int len = TYPE_LENGTH (type);
1695 int regno = AARCH64_X0_REGNUM;
1696 bfd_byte buf[X_REGISTER_SIZE];
1700 regcache_cooked_read (regs, regno++, buf);
1701 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1702 len -= X_REGISTER_SIZE;
1703 valbuf += X_REGISTER_SIZE;
1709 /* Will a function return an aggregate type in memory or in a
1710 register? Return 0 if an aggregate type can be returned in a
1711 register, 1 if it must be returned in memory. */
1714 aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1716 type = check_typedef (type);
1718 if (is_hfa_or_hva (type))
1720 /* v0-v7 are used to return values and one register is allocated
1721 for one member. However, HFA or HVA has at most four members. */
1725 if (TYPE_LENGTH (type) > 16)
1727 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1728 invisible reference. */
1736 /* Write into appropriate registers a function return value of type
1737 TYPE, given in virtual format. */
1740 aarch64_store_return_value (struct type *type, struct regcache *regs,
1741 const gdb_byte *valbuf)
1743 struct gdbarch *gdbarch = get_regcache_arch (regs);
1744 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1746 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1748 bfd_byte buf[V_REGISTER_SIZE];
1749 int len = TYPE_LENGTH (type);
1751 memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
1752 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
1754 else if (TYPE_CODE (type) == TYPE_CODE_INT
1755 || TYPE_CODE (type) == TYPE_CODE_CHAR
1756 || TYPE_CODE (type) == TYPE_CODE_BOOL
1757 || TYPE_CODE (type) == TYPE_CODE_PTR
1758 || TYPE_CODE (type) == TYPE_CODE_REF
1759 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1761 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
1763 /* Values of one word or less are zero/sign-extended and
1765 bfd_byte tmpbuf[X_REGISTER_SIZE];
1766 LONGEST val = unpack_long (type, valbuf);
1768 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
1769 regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf);
1773 /* Integral values greater than one word are stored in
1774 consecutive registers starting with r0. This will always
1775 be a multiple of the regiser size. */
1776 int len = TYPE_LENGTH (type);
1777 int regno = AARCH64_X0_REGNUM;
1781 regcache_cooked_write (regs, regno++, valbuf);
1782 len -= X_REGISTER_SIZE;
1783 valbuf += X_REGISTER_SIZE;
1787 else if (is_hfa_or_hva (type))
1789 int elements = TYPE_NFIELDS (type);
1790 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1791 int len = TYPE_LENGTH (member_type);
1794 for (i = 0; i < elements; i++)
1796 int regno = AARCH64_V0_REGNUM + i;
1797 bfd_byte tmpbuf[MAX_REGISTER_SIZE];
1801 debug_printf ("write HFA or HVA return value element %d to %s\n",
1803 gdbarch_register_name (gdbarch, regno));
1806 memcpy (tmpbuf, valbuf, len);
1807 regcache_cooked_write (regs, regno, tmpbuf);
1811 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1812 && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
1815 gdb_byte buf[V_REGISTER_SIZE];
1817 memcpy (buf, valbuf, TYPE_LENGTH (type));
1818 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
1822 /* For a structure or union the behaviour is as if the value had
1823 been stored to word-aligned memory and then loaded into
1824 registers with 64-bit load instruction(s). */
1825 int len = TYPE_LENGTH (type);
1826 int regno = AARCH64_X0_REGNUM;
1827 bfd_byte tmpbuf[X_REGISTER_SIZE];
1831 memcpy (tmpbuf, valbuf,
1832 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1833 regcache_cooked_write (regs, regno++, tmpbuf);
1834 len -= X_REGISTER_SIZE;
1835 valbuf += X_REGISTER_SIZE;
1840 /* Implement the "return_value" gdbarch method. */
1842 static enum return_value_convention
1843 aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
1844 struct type *valtype, struct regcache *regcache,
1845 gdb_byte *readbuf, const gdb_byte *writebuf)
1848 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1849 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1850 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1852 if (aarch64_return_in_memory (gdbarch, valtype))
1855 debug_printf ("return value in memory\n");
1856 return RETURN_VALUE_STRUCT_CONVENTION;
1861 aarch64_store_return_value (valtype, regcache, writebuf);
1864 aarch64_extract_return_value (valtype, regcache, readbuf);
1867 debug_printf ("return value in registers\n");
1869 return RETURN_VALUE_REGISTER_CONVENTION;
1872 /* Implement the "get_longjmp_target" gdbarch method. */
1875 aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1878 gdb_byte buf[X_REGISTER_SIZE];
1879 struct gdbarch *gdbarch = get_frame_arch (frame);
1880 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1881 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1883 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
1885 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
1889 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
1893 /* Implement the "gen_return_address" gdbarch method. */
1896 aarch64_gen_return_address (struct gdbarch *gdbarch,
1897 struct agent_expr *ax, struct axs_value *value,
1900 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
1901 value->kind = axs_lvalue_register;
1902 value->u.reg = AARCH64_LR_REGNUM;
1906 /* Return the pseudo register name corresponding to register regnum. */
1909 aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
1911 static const char *const q_name[] =
1913 "q0", "q1", "q2", "q3",
1914 "q4", "q5", "q6", "q7",
1915 "q8", "q9", "q10", "q11",
1916 "q12", "q13", "q14", "q15",
1917 "q16", "q17", "q18", "q19",
1918 "q20", "q21", "q22", "q23",
1919 "q24", "q25", "q26", "q27",
1920 "q28", "q29", "q30", "q31",
1923 static const char *const d_name[] =
1925 "d0", "d1", "d2", "d3",
1926 "d4", "d5", "d6", "d7",
1927 "d8", "d9", "d10", "d11",
1928 "d12", "d13", "d14", "d15",
1929 "d16", "d17", "d18", "d19",
1930 "d20", "d21", "d22", "d23",
1931 "d24", "d25", "d26", "d27",
1932 "d28", "d29", "d30", "d31",
1935 static const char *const s_name[] =
1937 "s0", "s1", "s2", "s3",
1938 "s4", "s5", "s6", "s7",
1939 "s8", "s9", "s10", "s11",
1940 "s12", "s13", "s14", "s15",
1941 "s16", "s17", "s18", "s19",
1942 "s20", "s21", "s22", "s23",
1943 "s24", "s25", "s26", "s27",
1944 "s28", "s29", "s30", "s31",
1947 static const char *const h_name[] =
1949 "h0", "h1", "h2", "h3",
1950 "h4", "h5", "h6", "h7",
1951 "h8", "h9", "h10", "h11",
1952 "h12", "h13", "h14", "h15",
1953 "h16", "h17", "h18", "h19",
1954 "h20", "h21", "h22", "h23",
1955 "h24", "h25", "h26", "h27",
1956 "h28", "h29", "h30", "h31",
1959 static const char *const b_name[] =
1961 "b0", "b1", "b2", "b3",
1962 "b4", "b5", "b6", "b7",
1963 "b8", "b9", "b10", "b11",
1964 "b12", "b13", "b14", "b15",
1965 "b16", "b17", "b18", "b19",
1966 "b20", "b21", "b22", "b23",
1967 "b24", "b25", "b26", "b27",
1968 "b28", "b29", "b30", "b31",
1971 regnum -= gdbarch_num_regs (gdbarch);
1973 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
1974 return q_name[regnum - AARCH64_Q0_REGNUM];
1976 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
1977 return d_name[regnum - AARCH64_D0_REGNUM];
1979 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
1980 return s_name[regnum - AARCH64_S0_REGNUM];
1982 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
1983 return h_name[regnum - AARCH64_H0_REGNUM];
1985 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
1986 return b_name[regnum - AARCH64_B0_REGNUM];
1988 internal_error (__FILE__, __LINE__,
1989 _("aarch64_pseudo_register_name: bad register number %d"),
1993 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
1995 static struct type *
1996 aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1998 regnum -= gdbarch_num_regs (gdbarch);
2000 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2001 return aarch64_vnq_type (gdbarch);
2003 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2004 return aarch64_vnd_type (gdbarch);
2006 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2007 return aarch64_vns_type (gdbarch);
2009 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2010 return aarch64_vnh_type (gdbarch);
2012 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2013 return aarch64_vnb_type (gdbarch);
2015 internal_error (__FILE__, __LINE__,
2016 _("aarch64_pseudo_register_type: bad register number %d"),
2020 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2023 aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2024 struct reggroup *group)
2026 regnum -= gdbarch_num_regs (gdbarch);
2028 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2029 return group == all_reggroup || group == vector_reggroup;
2030 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2031 return (group == all_reggroup || group == vector_reggroup
2032 || group == float_reggroup);
2033 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2034 return (group == all_reggroup || group == vector_reggroup
2035 || group == float_reggroup);
2036 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2037 return group == all_reggroup || group == vector_reggroup;
2038 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2039 return group == all_reggroup || group == vector_reggroup;
2041 return group == all_reggroup;
2044 /* Implement the "pseudo_register_read_value" gdbarch method. */
2046 static struct value *
2047 aarch64_pseudo_read_value (struct gdbarch *gdbarch,
2048 struct regcache *regcache,
2051 gdb_byte reg_buf[MAX_REGISTER_SIZE];
2052 struct value *result_value;
2055 result_value = allocate_value (register_type (gdbarch, regnum));
2056 VALUE_LVAL (result_value) = lval_register;
2057 VALUE_REGNUM (result_value) = regnum;
2058 buf = value_contents_raw (result_value);
2060 regnum -= gdbarch_num_regs (gdbarch);
2062 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2064 enum register_status status;
2067 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2068 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2069 if (status != REG_VALID)
2070 mark_value_bytes_unavailable (result_value, 0,
2071 TYPE_LENGTH (value_type (result_value)));
2073 memcpy (buf, reg_buf, Q_REGISTER_SIZE);
2074 return result_value;
2077 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2079 enum register_status status;
2082 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2083 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2084 if (status != REG_VALID)
2085 mark_value_bytes_unavailable (result_value, 0,
2086 TYPE_LENGTH (value_type (result_value)));
2088 memcpy (buf, reg_buf, D_REGISTER_SIZE);
2089 return result_value;
2092 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2094 enum register_status status;
2097 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2098 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2099 if (status != REG_VALID)
2100 mark_value_bytes_unavailable (result_value, 0,
2101 TYPE_LENGTH (value_type (result_value)));
2103 memcpy (buf, reg_buf, S_REGISTER_SIZE);
2104 return result_value;
2107 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2109 enum register_status status;
2112 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2113 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2114 if (status != REG_VALID)
2115 mark_value_bytes_unavailable (result_value, 0,
2116 TYPE_LENGTH (value_type (result_value)));
2118 memcpy (buf, reg_buf, H_REGISTER_SIZE);
2119 return result_value;
2122 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2124 enum register_status status;
2127 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2128 status = regcache_raw_read (regcache, v_regnum, reg_buf);
2129 if (status != REG_VALID)
2130 mark_value_bytes_unavailable (result_value, 0,
2131 TYPE_LENGTH (value_type (result_value)));
2133 memcpy (buf, reg_buf, B_REGISTER_SIZE);
2134 return result_value;
2137 gdb_assert_not_reached ("regnum out of bound");
2140 /* Implement the "pseudo_register_write" gdbarch method. */
2143 aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2144 int regnum, const gdb_byte *buf)
2146 gdb_byte reg_buf[MAX_REGISTER_SIZE];
2148 /* Ensure the register buffer is zero, we want gdb writes of the
2149 various 'scalar' pseudo registers to behavior like architectural
2150 writes, register width bytes are written the remainder are set to
2152 memset (reg_buf, 0, sizeof (reg_buf));
2154 regnum -= gdbarch_num_regs (gdbarch);
2156 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2158 /* pseudo Q registers */
2161 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2162 memcpy (reg_buf, buf, Q_REGISTER_SIZE);
2163 regcache_raw_write (regcache, v_regnum, reg_buf);
2167 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2169 /* pseudo D registers */
2172 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2173 memcpy (reg_buf, buf, D_REGISTER_SIZE);
2174 regcache_raw_write (regcache, v_regnum, reg_buf);
2178 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2182 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2183 memcpy (reg_buf, buf, S_REGISTER_SIZE);
2184 regcache_raw_write (regcache, v_regnum, reg_buf);
2188 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2190 /* pseudo H registers */
2193 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2194 memcpy (reg_buf, buf, H_REGISTER_SIZE);
2195 regcache_raw_write (regcache, v_regnum, reg_buf);
2199 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2201 /* pseudo B registers */
2204 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2205 memcpy (reg_buf, buf, B_REGISTER_SIZE);
2206 regcache_raw_write (regcache, v_regnum, reg_buf);
2210 gdb_assert_not_reached ("regnum out of bound");
2213 /* Callback function for user_reg_add. */
2215 static struct value *
2216 value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2218 const int *reg_p = (const int *) baton;
2220 return value_of_register (*reg_p, frame);
2224 /* Implement the "software_single_step" gdbarch method, needed to
2225 single step through atomic sequences on AArch64. */
2227 static VEC (CORE_ADDR) *
2228 aarch64_software_single_step (struct frame_info *frame)
2230 struct regcache *regcache = get_current_regcache ();
2231 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2232 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2233 const int insn_size = 4;
2234 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2235 CORE_ADDR pc = regcache_read_pc (regcache);
2236 CORE_ADDR breaks[2] = { -1, -1 };
2238 CORE_ADDR closing_insn = 0;
2239 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2240 byte_order_for_code);
2243 int bc_insn_count = 0; /* Conditional branch instruction count. */
2244 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2246 VEC (CORE_ADDR) *next_pcs = NULL;
2248 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2251 /* Look for a Load Exclusive instruction which begins the sequence. */
2252 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
2255 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2258 insn = read_memory_unsigned_integer (loc, insn_size,
2259 byte_order_for_code);
2261 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2263 /* Check if the instruction is a conditional branch. */
2264 if (inst.opcode->iclass == condbranch)
2266 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2268 if (bc_insn_count >= 1)
2271 /* It is, so we'll try to set a breakpoint at the destination. */
2272 breaks[1] = loc + inst.operands[0].imm.value;
2278 /* Look for the Store Exclusive which closes the atomic sequence. */
2279 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
2286 /* We didn't find a closing Store Exclusive instruction, fall back. */
2290 /* Insert breakpoint after the end of the atomic sequence. */
2291 breaks[0] = loc + insn_size;
2293 /* Check for duplicated breakpoints, and also check that the second
2294 breakpoint is not within the atomic sequence. */
2296 && (breaks[1] == breaks[0]
2297 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2298 last_breakpoint = 0;
2300 /* Insert the breakpoint at the end of the sequence, and one at the
2301 destination of the conditional branch, if it exists. */
2302 for (index = 0; index <= last_breakpoint; index++)
2303 VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
2308 struct displaced_step_closure
2310 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2311 is being displaced stepping. */
2314 /* PC adjustment offset after displaced stepping. */
2318 /* Data when visiting instructions for displaced stepping. */
2320 struct aarch64_displaced_step_data
2322 struct aarch64_insn_data base;
2324 /* The address where the instruction will be executed at. */
2326 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2327 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2328 /* Number of instructions in INSN_BUF. */
2329 unsigned insn_count;
2330 /* Registers when doing displaced stepping. */
2331 struct regcache *regs;
2333 struct displaced_step_closure *dsc;
2336 /* Implementation of aarch64_insn_visitor method "b". */
2339 aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2340 struct aarch64_insn_data *data)
2342 struct aarch64_displaced_step_data *dsd
2343 = (struct aarch64_displaced_step_data *) data;
2344 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
2346 if (can_encode_int32 (new_offset, 28))
2348 /* Emit B rather than BL, because executing BL on a new address
2349 will get the wrong address into LR. In order to avoid this,
2350 we emit B, and update LR if the instruction is BL. */
2351 emit_b (dsd->insn_buf, 0, new_offset);
2357 emit_nop (dsd->insn_buf);
2359 dsd->dsc->pc_adjust = offset;
2365 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2366 data->insn_addr + 4);
2370 /* Implementation of aarch64_insn_visitor method "b_cond". */
2373 aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2374 struct aarch64_insn_data *data)
2376 struct aarch64_displaced_step_data *dsd
2377 = (struct aarch64_displaced_step_data *) data;
2379 /* GDB has to fix up PC after displaced step this instruction
2380 differently according to the condition is true or false. Instead
2381 of checking COND against conditional flags, we can use
2382 the following instructions, and GDB can tell how to fix up PC
2383 according to the PC value.
2385 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2391 emit_bcond (dsd->insn_buf, cond, 8);
2393 dsd->dsc->pc_adjust = offset;
2394 dsd->insn_count = 1;
2397 /* Dynamically allocate a new register. If we know the register
2398 statically, we should make it a global as above instead of using this
2401 static struct aarch64_register
2402 aarch64_register (unsigned num, int is64)
2404 return (struct aarch64_register) { num, is64 };
2407 /* Implementation of aarch64_insn_visitor method "cb". */
2410 aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2411 const unsigned rn, int is64,
2412 struct aarch64_insn_data *data)
2414 struct aarch64_displaced_step_data *dsd
2415 = (struct aarch64_displaced_step_data *) data;
2417 /* The offset is out of range for a compare and branch
2418 instruction. We can use the following instructions instead:
2420 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2425 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2426 dsd->insn_count = 1;
2428 dsd->dsc->pc_adjust = offset;
2431 /* Implementation of aarch64_insn_visitor method "tb". */
2434 aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2435 const unsigned rt, unsigned bit,
2436 struct aarch64_insn_data *data)
2438 struct aarch64_displaced_step_data *dsd
2439 = (struct aarch64_displaced_step_data *) data;
2441 /* The offset is out of range for a test bit and branch
2442 instruction We can use the following instructions instead:
2444 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2450 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2451 dsd->insn_count = 1;
2453 dsd->dsc->pc_adjust = offset;
2456 /* Implementation of aarch64_insn_visitor method "adr". */
2459 aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2460 const int is_adrp, struct aarch64_insn_data *data)
2462 struct aarch64_displaced_step_data *dsd
2463 = (struct aarch64_displaced_step_data *) data;
2464 /* We know exactly the address the ADR{P,} instruction will compute.
2465 We can just write it to the destination register. */
2466 CORE_ADDR address = data->insn_addr + offset;
2470 /* Clear the lower 12 bits of the offset to get the 4K page. */
2471 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2475 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2478 dsd->dsc->pc_adjust = 4;
2479 emit_nop (dsd->insn_buf);
2480 dsd->insn_count = 1;
2483 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2486 aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2487 const unsigned rt, const int is64,
2488 struct aarch64_insn_data *data)
2490 struct aarch64_displaced_step_data *dsd
2491 = (struct aarch64_displaced_step_data *) data;
2492 CORE_ADDR address = data->insn_addr + offset;
2493 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2495 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2499 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2500 aarch64_register (rt, 1), zero);
2502 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2503 aarch64_register (rt, 1), zero);
2505 dsd->dsc->pc_adjust = 4;
2508 /* Implementation of aarch64_insn_visitor method "others". */
2511 aarch64_displaced_step_others (const uint32_t insn,
2512 struct aarch64_insn_data *data)
2514 struct aarch64_displaced_step_data *dsd
2515 = (struct aarch64_displaced_step_data *) data;
2517 aarch64_emit_insn (dsd->insn_buf, insn);
2518 dsd->insn_count = 1;
2520 if ((insn & 0xfffffc1f) == 0xd65f0000)
2523 dsd->dsc->pc_adjust = 0;
2526 dsd->dsc->pc_adjust = 4;
2529 static const struct aarch64_insn_visitor visitor =
2531 aarch64_displaced_step_b,
2532 aarch64_displaced_step_b_cond,
2533 aarch64_displaced_step_cb,
2534 aarch64_displaced_step_tb,
2535 aarch64_displaced_step_adr,
2536 aarch64_displaced_step_ldr_literal,
2537 aarch64_displaced_step_others,
2540 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2542 struct displaced_step_closure *
2543 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2544 CORE_ADDR from, CORE_ADDR to,
2545 struct regcache *regs)
2547 struct displaced_step_closure *dsc = NULL;
2548 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2549 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2550 struct aarch64_displaced_step_data dsd;
2553 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2556 /* Look for a Load Exclusive instruction which begins the sequence. */
2557 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
2559 /* We can't displaced step atomic sequences. */
2563 dsc = XCNEW (struct displaced_step_closure);
2564 dsd.base.insn_addr = from;
2569 aarch64_relocate_instruction (insn, &visitor,
2570 (struct aarch64_insn_data *) &dsd);
2571 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2573 if (dsd.insn_count != 0)
2577 /* Instruction can be relocated to scratch pad. Copy
2578 relocated instruction(s) there. */
2579 for (i = 0; i < dsd.insn_count; i++)
2581 if (debug_displaced)
2583 debug_printf ("displaced: writing insn ");
2584 debug_printf ("%.8x", dsd.insn_buf[i]);
2585 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2587 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2588 (ULONGEST) dsd.insn_buf[i]);
2600 /* Implement the "displaced_step_fixup" gdbarch method. */
2603 aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
2604 struct displaced_step_closure *dsc,
2605 CORE_ADDR from, CORE_ADDR to,
2606 struct regcache *regs)
2612 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2615 /* Condition is true. */
2617 else if (pc - to == 4)
2619 /* Condition is false. */
2623 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2626 if (dsc->pc_adjust != 0)
2628 if (debug_displaced)
2630 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2631 paddress (gdbarch, from), dsc->pc_adjust);
2633 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2634 from + dsc->pc_adjust);
2638 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2641 aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2642 struct displaced_step_closure *closure)
2647 /* Initialize the current architecture based on INFO. If possible,
2648 re-use an architecture from ARCHES, which is a list of
2649 architectures already created during this debugging session.
2651 Called e.g. at program startup, when reading a core file, and when
2652 reading a binary file. */
2654 static struct gdbarch *
2655 aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2657 struct gdbarch_tdep *tdep;
2658 struct gdbarch *gdbarch;
2659 struct gdbarch_list *best_arch;
2660 struct tdesc_arch_data *tdesc_data = NULL;
2661 const struct target_desc *tdesc = info.target_desc;
2664 const struct tdesc_feature *feature;
2666 int num_pseudo_regs = 0;
2668 /* Ensure we always have a target descriptor. */
2669 if (!tdesc_has_registers (tdesc))
2670 tdesc = tdesc_aarch64;
2674 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2676 if (feature == NULL)
2679 tdesc_data = tdesc_data_alloc ();
2681 /* Validate the descriptor provides the mandatory core R registers
2682 and allocate their numbers. */
2683 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
2685 tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i,
2686 aarch64_r_register_names[i]);
2688 num_regs = AARCH64_X0_REGNUM + i;
2690 /* Look for the V registers. */
2691 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2694 /* Validate the descriptor provides the mandatory V registers
2695 and allocate their numbers. */
2696 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
2698 tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i,
2699 aarch64_v_register_names[i]);
2701 num_regs = AARCH64_V0_REGNUM + i;
2703 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
2704 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
2705 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
2706 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
2707 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
2712 tdesc_data_cleanup (tdesc_data);
2716 /* AArch64 code is always little-endian. */
2717 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
2719 /* If there is already a candidate, use it. */
2720 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2722 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2724 /* Found a match. */
2728 if (best_arch != NULL)
2730 if (tdesc_data != NULL)
2731 tdesc_data_cleanup (tdesc_data);
2732 return best_arch->gdbarch;
2735 tdep = XCNEW (struct gdbarch_tdep);
2736 gdbarch = gdbarch_alloc (&info, tdep);
2738 /* This should be low enough for everything. */
2739 tdep->lowest_pc = 0x20;
2740 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2741 tdep->jb_elt_size = 8;
2743 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
2744 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
2746 /* Frame handling. */
2747 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
2748 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
2749 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
2751 /* Advance PC across function entry code. */
2752 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
2754 /* The stack grows downward. */
2755 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2757 /* Breakpoint manipulation. */
2758 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2759 aarch64_breakpoint::kind_from_pc);
2760 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2761 aarch64_breakpoint::bp_from_kind);
2762 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2763 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
2765 /* Information about registers, etc. */
2766 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
2767 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
2768 set_gdbarch_num_regs (gdbarch, num_regs);
2770 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
2771 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
2772 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
2773 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
2774 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
2775 set_tdesc_pseudo_register_reggroup_p (gdbarch,
2776 aarch64_pseudo_register_reggroup_p);
2779 set_gdbarch_short_bit (gdbarch, 16);
2780 set_gdbarch_int_bit (gdbarch, 32);
2781 set_gdbarch_float_bit (gdbarch, 32);
2782 set_gdbarch_double_bit (gdbarch, 64);
2783 set_gdbarch_long_double_bit (gdbarch, 128);
2784 set_gdbarch_long_bit (gdbarch, 64);
2785 set_gdbarch_long_long_bit (gdbarch, 64);
2786 set_gdbarch_ptr_bit (gdbarch, 64);
2787 set_gdbarch_char_signed (gdbarch, 0);
2788 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2789 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2790 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2792 /* Internal <-> external register number maps. */
2793 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
2795 /* Returning results. */
2796 set_gdbarch_return_value (gdbarch, aarch64_return_value);
2799 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
2801 /* Virtual tables. */
2802 set_gdbarch_vbit_in_delta (gdbarch, 1);
2804 /* Hook in the ABI-specific overrides, if they have been registered. */
2805 info.target_desc = tdesc;
2806 info.tdep_info = (void *) tdesc_data;
2807 gdbarch_init_osabi (info, gdbarch);
2809 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
2811 /* Add some default predicates. */
2812 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
2813 dwarf2_append_unwinders (gdbarch);
2814 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
2816 frame_base_set_default (gdbarch, &aarch64_normal_base);
2818 /* Now we have tuned the configuration, set a few final things,
2819 based on what the OS ABI has told us. */
2821 if (tdep->jb_pc >= 0)
2822 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
2824 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
2826 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2828 /* Add standard register aliases. */
2829 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
2830 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
2831 value_of_aarch64_user_reg,
2832 &aarch64_register_aliases[i].regnum);
2838 aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2840 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2845 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
2846 paddress (gdbarch, tdep->lowest_pc));
2849 /* Suppress warning from -Wmissing-prototypes. */
2850 extern initialize_file_ftype _initialize_aarch64_tdep;
2853 _initialize_aarch64_tdep (void)
2855 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
2858 initialize_tdesc_aarch64 ();
2860 /* Debug this file's internals. */
2861 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
2862 Set AArch64 debugging."), _("\
2863 Show AArch64 debugging."), _("\
2864 When on, AArch64 specific debugging is enabled."),
2867 &setdebuglist, &showdebuglist);
2870 /* AArch64 process record-replay related structures, defines etc. */
2872 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
2875 unsigned int reg_len = LENGTH; \
2878 REGS = XNEWVEC (uint32_t, reg_len); \
2879 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
2884 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
2887 unsigned int mem_len = LENGTH; \
2890 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
2891 memcpy(&MEMS->len, &RECORD_BUF[0], \
2892 sizeof(struct aarch64_mem_r) * LENGTH); \
2897 /* AArch64 record/replay structures and enumerations. */
2899 struct aarch64_mem_r
2901 uint64_t len; /* Record length. */
2902 uint64_t addr; /* Memory address. */
2905 enum aarch64_record_result
2907 AARCH64_RECORD_SUCCESS,
2908 AARCH64_RECORD_FAILURE,
2909 AARCH64_RECORD_UNSUPPORTED,
2910 AARCH64_RECORD_UNKNOWN
2913 typedef struct insn_decode_record_t
2915 struct gdbarch *gdbarch;
2916 struct regcache *regcache;
2917 CORE_ADDR this_addr; /* Address of insn to be recorded. */
2918 uint32_t aarch64_insn; /* Insn to be recorded. */
2919 uint32_t mem_rec_count; /* Count of memory records. */
2920 uint32_t reg_rec_count; /* Count of register records. */
2921 uint32_t *aarch64_regs; /* Registers to be recorded. */
2922 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
2923 } insn_decode_record;
2925 /* Record handler for data processing - register instructions. */
2928 aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
2930 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
2931 uint32_t record_buf[4];
2933 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
2934 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
2935 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
2937 if (!bit (aarch64_insn_r->aarch64_insn, 28))
2941 /* Logical (shifted register). */
2942 if (insn_bits24_27 == 0x0a)
2943 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
2945 else if (insn_bits24_27 == 0x0b)
2946 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
2948 return AARCH64_RECORD_UNKNOWN;
2950 record_buf[0] = reg_rd;
2951 aarch64_insn_r->reg_rec_count = 1;
2953 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
2957 if (insn_bits24_27 == 0x0b)
2959 /* Data-processing (3 source). */
2960 record_buf[0] = reg_rd;
2961 aarch64_insn_r->reg_rec_count = 1;
2963 else if (insn_bits24_27 == 0x0a)
2965 if (insn_bits21_23 == 0x00)
2967 /* Add/subtract (with carry). */
2968 record_buf[0] = reg_rd;
2969 aarch64_insn_r->reg_rec_count = 1;
2970 if (bit (aarch64_insn_r->aarch64_insn, 29))
2972 record_buf[1] = AARCH64_CPSR_REGNUM;
2973 aarch64_insn_r->reg_rec_count = 2;
2976 else if (insn_bits21_23 == 0x02)
2978 /* Conditional compare (register) and conditional compare
2979 (immediate) instructions. */
2980 record_buf[0] = AARCH64_CPSR_REGNUM;
2981 aarch64_insn_r->reg_rec_count = 1;
2983 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
2985 /* CConditional select. */
2986 /* Data-processing (2 source). */
2987 /* Data-processing (1 source). */
2988 record_buf[0] = reg_rd;
2989 aarch64_insn_r->reg_rec_count = 1;
2992 return AARCH64_RECORD_UNKNOWN;
2996 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
2998 return AARCH64_RECORD_SUCCESS;
3001 /* Record handler for data processing - immediate instructions. */
3004 aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3006 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
3007 uint32_t record_buf[4];
3009 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3010 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3011 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3013 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3014 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3015 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3017 record_buf[0] = reg_rd;
3018 aarch64_insn_r->reg_rec_count = 1;
3020 else if (insn_bits24_27 == 0x01)
3022 /* Add/Subtract (immediate). */
3023 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3024 record_buf[0] = reg_rd;
3025 aarch64_insn_r->reg_rec_count = 1;
3027 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3029 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3031 /* Logical (immediate). */
3032 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3033 record_buf[0] = reg_rd;
3034 aarch64_insn_r->reg_rec_count = 1;
3036 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3039 return AARCH64_RECORD_UNKNOWN;
3041 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3043 return AARCH64_RECORD_SUCCESS;
3046 /* Record handler for branch, exception generation and system instructions. */
3049 aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3051 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3052 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3053 uint32_t record_buf[4];
3055 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3056 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3057 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3059 if (insn_bits28_31 == 0x0d)
3061 /* Exception generation instructions. */
3062 if (insn_bits24_27 == 0x04)
3064 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3065 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3066 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
3068 ULONGEST svc_number;
3070 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3072 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3076 return AARCH64_RECORD_UNSUPPORTED;
3078 /* System instructions. */
3079 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3081 uint32_t reg_rt, reg_crn;
3083 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3084 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3086 /* Record rt in case of sysl and mrs instructions. */
3087 if (bit (aarch64_insn_r->aarch64_insn, 21))
3089 record_buf[0] = reg_rt;
3090 aarch64_insn_r->reg_rec_count = 1;
3092 /* Record cpsr for hint and msr(immediate) instructions. */
3093 else if (reg_crn == 0x02 || reg_crn == 0x04)
3095 record_buf[0] = AARCH64_CPSR_REGNUM;
3096 aarch64_insn_r->reg_rec_count = 1;
3099 /* Unconditional branch (register). */
3100 else if((insn_bits24_27 & 0x0e) == 0x06)
3102 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3103 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3104 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3107 return AARCH64_RECORD_UNKNOWN;
3109 /* Unconditional branch (immediate). */
3110 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3112 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3113 if (bit (aarch64_insn_r->aarch64_insn, 31))
3114 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3117 /* Compare & branch (immediate), Test & branch (immediate) and
3118 Conditional branch (immediate). */
3119 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3121 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3123 return AARCH64_RECORD_SUCCESS;
3126 /* Record handler for advanced SIMD load and store instructions. */
3129 aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3132 uint64_t addr_offset = 0;
3133 uint32_t record_buf[24];
3134 uint64_t record_buf_mem[24];
3135 uint32_t reg_rn, reg_rt;
3136 uint32_t reg_index = 0, mem_index = 0;
3137 uint8_t opcode_bits, size_bits;
3139 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3140 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3141 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3142 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3143 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3146 debug_printf ("Process record: Advanced SIMD load/store\n");
3148 /* Load/store single structure. */
3149 if (bit (aarch64_insn_r->aarch64_insn, 24))
3151 uint8_t sindex, scale, selem, esize, replicate = 0;
3152 scale = opcode_bits >> 2;
3153 selem = ((opcode_bits & 0x02) |
3154 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3158 if (size_bits & 0x01)
3159 return AARCH64_RECORD_UNKNOWN;
3162 if ((size_bits >> 1) & 0x01)
3163 return AARCH64_RECORD_UNKNOWN;
3164 if (size_bits & 0x01)
3166 if (!((opcode_bits >> 1) & 0x01))
3169 return AARCH64_RECORD_UNKNOWN;
3173 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3180 return AARCH64_RECORD_UNKNOWN;
3186 for (sindex = 0; sindex < selem; sindex++)
3188 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3189 reg_rt = (reg_rt + 1) % 32;
3193 for (sindex = 0; sindex < selem; sindex++)
3195 if (bit (aarch64_insn_r->aarch64_insn, 22))
3196 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3199 record_buf_mem[mem_index++] = esize / 8;
3200 record_buf_mem[mem_index++] = address + addr_offset;
3202 addr_offset = addr_offset + (esize / 8);
3203 reg_rt = (reg_rt + 1) % 32;
3207 /* Load/store multiple structure. */
3210 uint8_t selem, esize, rpt, elements;
3211 uint8_t eindex, rindex;
3213 esize = 8 << size_bits;
3214 if (bit (aarch64_insn_r->aarch64_insn, 30))
3215 elements = 128 / esize;
3217 elements = 64 / esize;
3219 switch (opcode_bits)
3221 /*LD/ST4 (4 Registers). */
3226 /*LD/ST1 (4 Registers). */
3231 /*LD/ST3 (3 Registers). */
3236 /*LD/ST1 (3 Registers). */
3241 /*LD/ST1 (1 Register). */
3246 /*LD/ST2 (2 Registers). */
3251 /*LD/ST1 (2 Registers). */
3257 return AARCH64_RECORD_UNSUPPORTED;
3260 for (rindex = 0; rindex < rpt; rindex++)
3261 for (eindex = 0; eindex < elements; eindex++)
3263 uint8_t reg_tt, sindex;
3264 reg_tt = (reg_rt + rindex) % 32;
3265 for (sindex = 0; sindex < selem; sindex++)
3267 if (bit (aarch64_insn_r->aarch64_insn, 22))
3268 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3271 record_buf_mem[mem_index++] = esize / 8;
3272 record_buf_mem[mem_index++] = address + addr_offset;
3274 addr_offset = addr_offset + (esize / 8);
3275 reg_tt = (reg_tt + 1) % 32;
3280 if (bit (aarch64_insn_r->aarch64_insn, 23))
3281 record_buf[reg_index++] = reg_rn;
3283 aarch64_insn_r->reg_rec_count = reg_index;
3284 aarch64_insn_r->mem_rec_count = mem_index / 2;
3285 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3287 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3289 return AARCH64_RECORD_SUCCESS;
3292 /* Record handler for load and store instructions. */
3295 aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3297 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3298 uint8_t insn_bit23, insn_bit21;
3299 uint8_t opc, size_bits, ld_flag, vector_flag;
3300 uint32_t reg_rn, reg_rt, reg_rt2;
3301 uint64_t datasize, offset;
3302 uint32_t record_buf[8];
3303 uint64_t record_buf_mem[8];
3306 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3307 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3308 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3309 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3310 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3311 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3312 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3313 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3314 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3315 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3316 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3318 /* Load/store exclusive. */
3319 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3322 debug_printf ("Process record: load/store exclusive\n");
3326 record_buf[0] = reg_rt;
3327 aarch64_insn_r->reg_rec_count = 1;
3330 record_buf[1] = reg_rt2;
3331 aarch64_insn_r->reg_rec_count = 2;
3337 datasize = (8 << size_bits) * 2;
3339 datasize = (8 << size_bits);
3340 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3342 record_buf_mem[0] = datasize / 8;
3343 record_buf_mem[1] = address;
3344 aarch64_insn_r->mem_rec_count = 1;
3347 /* Save register rs. */
3348 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3349 aarch64_insn_r->reg_rec_count = 1;
3353 /* Load register (literal) instructions decoding. */
3354 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3357 debug_printf ("Process record: load register (literal)\n");
3359 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3361 record_buf[0] = reg_rt;
3362 aarch64_insn_r->reg_rec_count = 1;
3364 /* All types of load/store pair instructions decoding. */
3365 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3368 debug_printf ("Process record: load/store pair\n");
3374 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3375 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3379 record_buf[0] = reg_rt;
3380 record_buf[1] = reg_rt2;
3382 aarch64_insn_r->reg_rec_count = 2;
3387 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3389 size_bits = size_bits >> 1;
3390 datasize = 8 << (2 + size_bits);
3391 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3392 offset = offset << (2 + size_bits);
3393 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3395 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3397 if (imm7_off & 0x40)
3398 address = address - offset;
3400 address = address + offset;
3403 record_buf_mem[0] = datasize / 8;
3404 record_buf_mem[1] = address;
3405 record_buf_mem[2] = datasize / 8;
3406 record_buf_mem[3] = address + (datasize / 8);
3407 aarch64_insn_r->mem_rec_count = 2;
3409 if (bit (aarch64_insn_r->aarch64_insn, 23))
3410 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3412 /* Load/store register (unsigned immediate) instructions. */
3413 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3415 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3422 if (size_bits != 0x03)
3425 return AARCH64_RECORD_UNKNOWN;
3429 debug_printf ("Process record: load/store (unsigned immediate):"
3430 " size %x V %d opc %x\n", size_bits, vector_flag,
3436 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3437 datasize = 8 << size_bits;
3438 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3440 offset = offset << size_bits;
3441 address = address + offset;
3443 record_buf_mem[0] = datasize >> 3;
3444 record_buf_mem[1] = address;
3445 aarch64_insn_r->mem_rec_count = 1;
3450 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3452 record_buf[0] = reg_rt;
3453 aarch64_insn_r->reg_rec_count = 1;
3456 /* Load/store register (register offset) instructions. */
3457 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3458 && insn_bits10_11 == 0x02 && insn_bit21)
3461 debug_printf ("Process record: load/store (register offset)\n");
3462 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3469 if (size_bits != 0x03)
3472 return AARCH64_RECORD_UNKNOWN;
3476 ULONGEST reg_rm_val;
3478 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3479 bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
3480 if (bit (aarch64_insn_r->aarch64_insn, 12))
3481 offset = reg_rm_val << size_bits;
3483 offset = reg_rm_val;
3484 datasize = 8 << size_bits;
3485 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3487 address = address + offset;
3488 record_buf_mem[0] = datasize >> 3;
3489 record_buf_mem[1] = address;
3490 aarch64_insn_r->mem_rec_count = 1;
3495 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3497 record_buf[0] = reg_rt;
3498 aarch64_insn_r->reg_rec_count = 1;
3501 /* Load/store register (immediate and unprivileged) instructions. */
3502 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3507 debug_printf ("Process record: load/store "
3508 "(immediate and unprivileged)\n");
3510 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3517 if (size_bits != 0x03)
3520 return AARCH64_RECORD_UNKNOWN;
3525 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3526 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3527 datasize = 8 << size_bits;
3528 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3530 if (insn_bits10_11 != 0x01)
3532 if (imm9_off & 0x0100)
3533 address = address - offset;
3535 address = address + offset;
3537 record_buf_mem[0] = datasize >> 3;
3538 record_buf_mem[1] = address;
3539 aarch64_insn_r->mem_rec_count = 1;
3544 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3546 record_buf[0] = reg_rt;
3547 aarch64_insn_r->reg_rec_count = 1;
3549 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3550 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3552 /* Advanced SIMD load/store instructions. */
3554 return aarch64_record_asimd_load_store (aarch64_insn_r);
3556 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3558 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3560 return AARCH64_RECORD_SUCCESS;
3563 /* Record handler for data processing SIMD and floating point instructions. */
3566 aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3568 uint8_t insn_bit21, opcode, rmode, reg_rd;
3569 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3570 uint8_t insn_bits11_14;
3571 uint32_t record_buf[2];
3573 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3574 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3575 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3576 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3577 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3578 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3579 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3580 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3581 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3584 debug_printf ("Process record: data processing SIMD/FP: ");
3586 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3588 /* Floating point - fixed point conversion instructions. */
3592 debug_printf ("FP - fixed point conversion");
3594 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3595 record_buf[0] = reg_rd;
3597 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3599 /* Floating point - conditional compare instructions. */
3600 else if (insn_bits10_11 == 0x01)
3603 debug_printf ("FP - conditional compare");
3605 record_buf[0] = AARCH64_CPSR_REGNUM;
3607 /* Floating point - data processing (2-source) and
3608 conditional select instructions. */
3609 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3612 debug_printf ("FP - DP (2-source)");
3614 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3616 else if (insn_bits10_11 == 0x00)
3618 /* Floating point - immediate instructions. */
3619 if ((insn_bits12_15 & 0x01) == 0x01
3620 || (insn_bits12_15 & 0x07) == 0x04)
3623 debug_printf ("FP - immediate");
3624 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3626 /* Floating point - compare instructions. */
3627 else if ((insn_bits12_15 & 0x03) == 0x02)
3630 debug_printf ("FP - immediate");
3631 record_buf[0] = AARCH64_CPSR_REGNUM;
3633 /* Floating point - integer conversions instructions. */
3634 else if (insn_bits12_15 == 0x00)
3636 /* Convert float to integer instruction. */
3637 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3640 debug_printf ("float to int conversion");
3642 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3644 /* Convert integer to float instruction. */
3645 else if ((opcode >> 1) == 0x01 && !rmode)
3648 debug_printf ("int to float conversion");
3650 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3652 /* Move float to integer instruction. */
3653 else if ((opcode >> 1) == 0x03)
3656 debug_printf ("move float to int");
3658 if (!(opcode & 0x01))
3659 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3661 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3664 return AARCH64_RECORD_UNKNOWN;
3667 return AARCH64_RECORD_UNKNOWN;
3670 return AARCH64_RECORD_UNKNOWN;
3672 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
3675 debug_printf ("SIMD copy");
3677 /* Advanced SIMD copy instructions. */
3678 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
3679 && !bit (aarch64_insn_r->aarch64_insn, 15)
3680 && bit (aarch64_insn_r->aarch64_insn, 10))
3682 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
3683 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3685 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3688 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3690 /* All remaining floating point or advanced SIMD instructions. */
3694 debug_printf ("all remain");
3696 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3700 debug_printf ("\n");
3702 aarch64_insn_r->reg_rec_count++;
3703 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
3704 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3706 return AARCH64_RECORD_SUCCESS;
3709 /* Decodes insns type and invokes its record handler. */
3712 aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
3714 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
3716 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
3717 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
3718 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
3719 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3721 /* Data processing - immediate instructions. */
3722 if (!ins_bit26 && !ins_bit27 && ins_bit28)
3723 return aarch64_record_data_proc_imm (aarch64_insn_r);
3725 /* Branch, exception generation and system instructions. */
3726 if (ins_bit26 && !ins_bit27 && ins_bit28)
3727 return aarch64_record_branch_except_sys (aarch64_insn_r);
3729 /* Load and store instructions. */
3730 if (!ins_bit25 && ins_bit27)
3731 return aarch64_record_load_store (aarch64_insn_r);
3733 /* Data processing - register instructions. */
3734 if (ins_bit25 && !ins_bit26 && ins_bit27)
3735 return aarch64_record_data_proc_reg (aarch64_insn_r);
3737 /* Data processing - SIMD and floating point instructions. */
3738 if (ins_bit25 && ins_bit26 && ins_bit27)
3739 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
3741 return AARCH64_RECORD_UNSUPPORTED;
3744 /* Cleans up local record registers and memory allocations. */
3747 deallocate_reg_mem (insn_decode_record *record)
3749 xfree (record->aarch64_regs);
3750 xfree (record->aarch64_mems);
3753 /* Parse the current instruction and record the values of the registers and
3754 memory that will be changed in current instruction to record_arch_list
3755 return -1 if something is wrong. */
3758 aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3759 CORE_ADDR insn_addr)
3761 uint32_t rec_no = 0;
3762 uint8_t insn_size = 4;
3764 gdb_byte buf[insn_size];
3765 insn_decode_record aarch64_record;
3767 memset (&buf[0], 0, insn_size);
3768 memset (&aarch64_record, 0, sizeof (insn_decode_record));
3769 target_read_memory (insn_addr, &buf[0], insn_size);
3770 aarch64_record.aarch64_insn
3771 = (uint32_t) extract_unsigned_integer (&buf[0],
3773 gdbarch_byte_order (gdbarch));
3774 aarch64_record.regcache = regcache;
3775 aarch64_record.this_addr = insn_addr;
3776 aarch64_record.gdbarch = gdbarch;
3778 ret = aarch64_record_decode_insn_handler (&aarch64_record);
3779 if (ret == AARCH64_RECORD_UNSUPPORTED)
3781 printf_unfiltered (_("Process record does not support instruction "
3782 "0x%0x at address %s.\n"),
3783 aarch64_record.aarch64_insn,
3784 paddress (gdbarch, insn_addr));
3790 /* Record registers. */
3791 record_full_arch_list_add_reg (aarch64_record.regcache,
3793 /* Always record register CPSR. */
3794 record_full_arch_list_add_reg (aarch64_record.regcache,
3795 AARCH64_CPSR_REGNUM);
3796 if (aarch64_record.aarch64_regs)
3797 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
3798 if (record_full_arch_list_add_reg (aarch64_record.regcache,
3799 aarch64_record.aarch64_regs[rec_no]))
3802 /* Record memories. */
3803 if (aarch64_record.aarch64_mems)
3804 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
3805 if (record_full_arch_list_add_mem
3806 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
3807 aarch64_record.aarch64_mems[rec_no].len))
3810 if (record_full_arch_list_add_end ())
3814 deallocate_reg_mem (&aarch64_record);