1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
48 #include "aarch64-tdep.h"
49 #include "aarch64-ravenscar-thread.h"
52 #include "elf/aarch64.h"
57 #include "record-full.h"
58 #include "arch/aarch64-insn.h"
60 #include "opcode/aarch64.h"
63 #define submask(x) ((1L << ((x) + 1)) - 1)
64 #define bit(obj,st) (((obj) >> (st)) & 1)
65 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
67 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
69 #define HA_MAX_NUM_FLDS 4
71 /* All possible aarch64 target descriptors. */
72 struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1];
74 /* The standard register names, and all the valid aliases for them. */
77 const char *const name;
79 } aarch64_register_aliases[] =
81 /* 64-bit register names. */
82 {"fp", AARCH64_FP_REGNUM},
83 {"lr", AARCH64_LR_REGNUM},
84 {"sp", AARCH64_SP_REGNUM},
86 /* 32-bit register names. */
87 {"w0", AARCH64_X0_REGNUM + 0},
88 {"w1", AARCH64_X0_REGNUM + 1},
89 {"w2", AARCH64_X0_REGNUM + 2},
90 {"w3", AARCH64_X0_REGNUM + 3},
91 {"w4", AARCH64_X0_REGNUM + 4},
92 {"w5", AARCH64_X0_REGNUM + 5},
93 {"w6", AARCH64_X0_REGNUM + 6},
94 {"w7", AARCH64_X0_REGNUM + 7},
95 {"w8", AARCH64_X0_REGNUM + 8},
96 {"w9", AARCH64_X0_REGNUM + 9},
97 {"w10", AARCH64_X0_REGNUM + 10},
98 {"w11", AARCH64_X0_REGNUM + 11},
99 {"w12", AARCH64_X0_REGNUM + 12},
100 {"w13", AARCH64_X0_REGNUM + 13},
101 {"w14", AARCH64_X0_REGNUM + 14},
102 {"w15", AARCH64_X0_REGNUM + 15},
103 {"w16", AARCH64_X0_REGNUM + 16},
104 {"w17", AARCH64_X0_REGNUM + 17},
105 {"w18", AARCH64_X0_REGNUM + 18},
106 {"w19", AARCH64_X0_REGNUM + 19},
107 {"w20", AARCH64_X0_REGNUM + 20},
108 {"w21", AARCH64_X0_REGNUM + 21},
109 {"w22", AARCH64_X0_REGNUM + 22},
110 {"w23", AARCH64_X0_REGNUM + 23},
111 {"w24", AARCH64_X0_REGNUM + 24},
112 {"w25", AARCH64_X0_REGNUM + 25},
113 {"w26", AARCH64_X0_REGNUM + 26},
114 {"w27", AARCH64_X0_REGNUM + 27},
115 {"w28", AARCH64_X0_REGNUM + 28},
116 {"w29", AARCH64_X0_REGNUM + 29},
117 {"w30", AARCH64_X0_REGNUM + 30},
120 {"ip0", AARCH64_X0_REGNUM + 16},
121 {"ip1", AARCH64_X0_REGNUM + 17}
124 /* The required core 'R' registers. */
125 static const char *const aarch64_r_register_names[] =
127 /* These registers must appear in consecutive RAW register number
128 order and they must begin with AARCH64_X0_REGNUM! */
129 "x0", "x1", "x2", "x3",
130 "x4", "x5", "x6", "x7",
131 "x8", "x9", "x10", "x11",
132 "x12", "x13", "x14", "x15",
133 "x16", "x17", "x18", "x19",
134 "x20", "x21", "x22", "x23",
135 "x24", "x25", "x26", "x27",
136 "x28", "x29", "x30", "sp",
140 /* The FP/SIMD 'V' registers. */
141 static const char *const aarch64_v_register_names[] =
143 /* These registers must appear in consecutive RAW register number
144 order and they must begin with AARCH64_V0_REGNUM! */
145 "v0", "v1", "v2", "v3",
146 "v4", "v5", "v6", "v7",
147 "v8", "v9", "v10", "v11",
148 "v12", "v13", "v14", "v15",
149 "v16", "v17", "v18", "v19",
150 "v20", "v21", "v22", "v23",
151 "v24", "v25", "v26", "v27",
152 "v28", "v29", "v30", "v31",
157 /* The SVE 'Z' and 'P' registers. */
158 static const char *const aarch64_sve_register_names[] =
160 /* These registers must appear in consecutive RAW register number
161 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
162 "z0", "z1", "z2", "z3",
163 "z4", "z5", "z6", "z7",
164 "z8", "z9", "z10", "z11",
165 "z12", "z13", "z14", "z15",
166 "z16", "z17", "z18", "z19",
167 "z20", "z21", "z22", "z23",
168 "z24", "z25", "z26", "z27",
169 "z28", "z29", "z30", "z31",
171 "p0", "p1", "p2", "p3",
172 "p4", "p5", "p6", "p7",
173 "p8", "p9", "p10", "p11",
174 "p12", "p13", "p14", "p15",
178 /* AArch64 prologue cache structure. */
179 struct aarch64_prologue_cache
181 /* The program counter at the start of the function. It is used to
182 identify this frame as a prologue frame. */
185 /* The program counter at the time this frame was created; i.e. where
186 this function was called from. It is used to identify this frame as a
190 /* The stack pointer at the time this frame was created; i.e. the
191 caller's stack pointer when this function was called. It is used
192 to identify this frame. */
195 /* Is the target available to read from? */
198 /* The frame base for this frame is just prev_sp - frame size.
199 FRAMESIZE is the distance from the frame pointer to the
200 initial stack pointer. */
203 /* The register used to hold the frame pointer for this frame. */
206 /* Saved register offsets. */
207 struct trad_frame_saved_reg *saved_regs;
211 show_aarch64_debug (struct ui_file *file, int from_tty,
212 struct cmd_list_element *c, const char *value)
214 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
219 /* Abstract instruction reader. */
221 class abstract_instruction_reader
224 /* Read in one instruction. */
225 virtual ULONGEST read (CORE_ADDR memaddr, int len,
226 enum bfd_endian byte_order) = 0;
229 /* Instruction reader from real target. */
231 class instruction_reader : public abstract_instruction_reader
234 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
237 return read_code_unsigned_integer (memaddr, len, byte_order);
243 /* Analyze a prologue, looking for a recognizable stack frame
244 and frame pointer. Scan until we encounter a store that could
245 clobber the stack frame unexpectedly, or an unknown instruction. */
248 aarch64_analyze_prologue (struct gdbarch *gdbarch,
249 CORE_ADDR start, CORE_ADDR limit,
250 struct aarch64_prologue_cache *cache,
251 abstract_instruction_reader& reader)
253 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
255 /* Track X registers and D registers in prologue. */
256 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
258 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
259 regs[i] = pv_register (i, 0);
260 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
262 for (; start < limit; start += 4)
267 insn = reader.read (start, 4, byte_order_for_code);
269 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
272 if (inst.opcode->iclass == addsub_imm
273 && (inst.opcode->op == OP_ADD
274 || strcmp ("sub", inst.opcode->name) == 0))
276 unsigned rd = inst.operands[0].reg.regno;
277 unsigned rn = inst.operands[1].reg.regno;
279 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
280 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
281 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
282 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
284 if (inst.opcode->op == OP_ADD)
286 regs[rd] = pv_add_constant (regs[rn],
287 inst.operands[2].imm.value);
291 regs[rd] = pv_add_constant (regs[rn],
292 -inst.operands[2].imm.value);
295 else if (inst.opcode->iclass == pcreladdr
296 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
298 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
299 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
301 regs[inst.operands[0].reg.regno] = pv_unknown ();
303 else if (inst.opcode->iclass == branch_imm)
305 /* Stop analysis on branch. */
308 else if (inst.opcode->iclass == condbranch)
310 /* Stop analysis on branch. */
313 else if (inst.opcode->iclass == branch_reg)
315 /* Stop analysis on branch. */
318 else if (inst.opcode->iclass == compbranch)
320 /* Stop analysis on branch. */
323 else if (inst.opcode->op == OP_MOVZ)
325 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
326 regs[inst.operands[0].reg.regno] = pv_unknown ();
328 else if (inst.opcode->iclass == log_shift
329 && strcmp (inst.opcode->name, "orr") == 0)
331 unsigned rd = inst.operands[0].reg.regno;
332 unsigned rn = inst.operands[1].reg.regno;
333 unsigned rm = inst.operands[2].reg.regno;
335 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
336 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
337 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
339 if (inst.operands[2].shifter.amount == 0
340 && rn == AARCH64_SP_REGNUM)
346 debug_printf ("aarch64: prologue analysis gave up "
347 "addr=%s opcode=0x%x (orr x register)\n",
348 core_addr_to_string_nz (start), insn);
353 else if (inst.opcode->op == OP_STUR)
355 unsigned rt = inst.operands[0].reg.regno;
356 unsigned rn = inst.operands[1].addr.base_regno;
358 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
360 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
361 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
362 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
363 gdb_assert (!inst.operands[1].addr.offset.is_reg);
365 stack.store (pv_add_constant (regs[rn],
366 inst.operands[1].addr.offset.imm),
367 is64 ? 8 : 4, regs[rt]);
369 else if ((inst.opcode->iclass == ldstpair_off
370 || (inst.opcode->iclass == ldstpair_indexed
371 && inst.operands[2].addr.preind))
372 && strcmp ("stp", inst.opcode->name) == 0)
374 /* STP with addressing mode Pre-indexed and Base register. */
377 unsigned rn = inst.operands[2].addr.base_regno;
378 int32_t imm = inst.operands[2].addr.offset.imm;
380 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
381 || inst.operands[0].type == AARCH64_OPND_Ft);
382 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
383 || inst.operands[1].type == AARCH64_OPND_Ft2);
384 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
385 gdb_assert (!inst.operands[2].addr.offset.is_reg);
387 /* If recording this store would invalidate the store area
388 (perhaps because rn is not known) then we should abandon
389 further prologue analysis. */
390 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
393 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
396 rt1 = inst.operands[0].reg.regno;
397 rt2 = inst.operands[1].reg.regno;
398 if (inst.operands[0].type == AARCH64_OPND_Ft)
400 /* Only bottom 64-bit of each V register (D register) need
402 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
403 rt1 += AARCH64_X_REGISTER_COUNT;
404 rt2 += AARCH64_X_REGISTER_COUNT;
407 stack.store (pv_add_constant (regs[rn], imm), 8,
409 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
412 if (inst.operands[2].addr.writeback)
413 regs[rn] = pv_add_constant (regs[rn], imm);
416 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
417 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
418 && (inst.opcode->op == OP_STR_POS
419 || inst.opcode->op == OP_STRF_POS)))
420 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
421 && strcmp ("str", inst.opcode->name) == 0)
423 /* STR (immediate) */
424 unsigned int rt = inst.operands[0].reg.regno;
425 int32_t imm = inst.operands[1].addr.offset.imm;
426 unsigned int rn = inst.operands[1].addr.base_regno;
428 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
429 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
430 || inst.operands[0].type == AARCH64_OPND_Ft);
432 if (inst.operands[0].type == AARCH64_OPND_Ft)
434 /* Only bottom 64-bit of each V register (D register) need
436 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
437 rt += AARCH64_X_REGISTER_COUNT;
440 stack.store (pv_add_constant (regs[rn], imm),
441 is64 ? 8 : 4, regs[rt]);
442 if (inst.operands[1].addr.writeback)
443 regs[rn] = pv_add_constant (regs[rn], imm);
445 else if (inst.opcode->iclass == testbranch)
447 /* Stop analysis on branch. */
454 debug_printf ("aarch64: prologue analysis gave up addr=%s"
456 core_addr_to_string_nz (start), insn);
465 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
467 /* Frame pointer is fp. Frame size is constant. */
468 cache->framereg = AARCH64_FP_REGNUM;
469 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
471 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
473 /* Try the stack pointer. */
474 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
475 cache->framereg = AARCH64_SP_REGNUM;
479 /* We're just out of luck. We don't know where the frame is. */
480 cache->framereg = -1;
481 cache->framesize = 0;
484 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
488 if (stack.find_reg (gdbarch, i, &offset))
489 cache->saved_regs[i].addr = offset;
492 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
494 int regnum = gdbarch_num_regs (gdbarch);
497 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
499 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
506 aarch64_analyze_prologue (struct gdbarch *gdbarch,
507 CORE_ADDR start, CORE_ADDR limit,
508 struct aarch64_prologue_cache *cache)
510 instruction_reader reader;
512 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
518 namespace selftests {
520 /* Instruction reader from manually cooked instruction sequences. */
522 class instruction_reader_test : public abstract_instruction_reader
525 template<size_t SIZE>
526 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
527 : m_insns (insns), m_insns_size (SIZE)
530 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
533 SELF_CHECK (len == 4);
534 SELF_CHECK (memaddr % 4 == 0);
535 SELF_CHECK (memaddr / 4 < m_insns_size);
537 return m_insns[memaddr / 4];
541 const uint32_t *m_insns;
546 aarch64_analyze_prologue_test (void)
548 struct gdbarch_info info;
550 gdbarch_info_init (&info);
551 info.bfd_arch_info = bfd_scan_arch ("aarch64");
553 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
554 SELF_CHECK (gdbarch != NULL);
556 /* Test the simple prologue in which frame pointer is used. */
558 struct aarch64_prologue_cache cache;
559 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
561 static const uint32_t insns[] = {
562 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
563 0x910003fd, /* mov x29, sp */
564 0x97ffffe6, /* bl 0x400580 */
566 instruction_reader_test reader (insns);
568 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
569 SELF_CHECK (end == 4 * 2);
571 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
572 SELF_CHECK (cache.framesize == 272);
574 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
576 if (i == AARCH64_FP_REGNUM)
577 SELF_CHECK (cache.saved_regs[i].addr == -272);
578 else if (i == AARCH64_LR_REGNUM)
579 SELF_CHECK (cache.saved_regs[i].addr == -264);
581 SELF_CHECK (cache.saved_regs[i].addr == -1);
584 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
586 int regnum = gdbarch_num_regs (gdbarch);
588 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
593 /* Test a prologue in which STR is used and frame pointer is not
596 struct aarch64_prologue_cache cache;
597 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
599 static const uint32_t insns[] = {
600 0xf81d0ff3, /* str x19, [sp, #-48]! */
601 0xb9002fe0, /* str w0, [sp, #44] */
602 0xf90013e1, /* str x1, [sp, #32]*/
603 0xfd000fe0, /* str d0, [sp, #24] */
604 0xaa0203f3, /* mov x19, x2 */
605 0xf94013e0, /* ldr x0, [sp, #32] */
607 instruction_reader_test reader (insns);
609 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
611 SELF_CHECK (end == 4 * 5);
613 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
614 SELF_CHECK (cache.framesize == 48);
616 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
619 SELF_CHECK (cache.saved_regs[i].addr == -16);
621 SELF_CHECK (cache.saved_regs[i].addr == -48);
623 SELF_CHECK (cache.saved_regs[i].addr == -1);
626 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
628 int regnum = gdbarch_num_regs (gdbarch);
631 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
634 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
639 } // namespace selftests
640 #endif /* GDB_SELF_TEST */
642 /* Implement the "skip_prologue" gdbarch method. */
645 aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
647 CORE_ADDR func_addr, limit_pc;
649 /* See if we can determine the end of the prologue via the symbol
650 table. If so, then return either PC, or the PC after the
651 prologue, whichever is greater. */
652 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
654 CORE_ADDR post_prologue_pc
655 = skip_prologue_using_sal (gdbarch, func_addr);
657 if (post_prologue_pc != 0)
658 return std::max (pc, post_prologue_pc);
661 /* Can't determine prologue from the symbol table, need to examine
664 /* Find an upper limit on the function prologue using the debug
665 information. If the debug information could not be used to
666 provide that bound, then use an arbitrary large number as the
668 limit_pc = skip_prologue_using_sal (gdbarch, pc);
670 limit_pc = pc + 128; /* Magic. */
672 /* Try disassembling prologue. */
673 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
676 /* Scan the function prologue for THIS_FRAME and populate the prologue
680 aarch64_scan_prologue (struct frame_info *this_frame,
681 struct aarch64_prologue_cache *cache)
683 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
684 CORE_ADDR prologue_start;
685 CORE_ADDR prologue_end;
686 CORE_ADDR prev_pc = get_frame_pc (this_frame);
687 struct gdbarch *gdbarch = get_frame_arch (this_frame);
689 cache->prev_pc = prev_pc;
691 /* Assume we do not find a frame. */
692 cache->framereg = -1;
693 cache->framesize = 0;
695 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
698 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
702 /* No line info so use the current PC. */
703 prologue_end = prev_pc;
705 else if (sal.end < prologue_end)
707 /* The next line begins after the function end. */
708 prologue_end = sal.end;
711 prologue_end = std::min (prologue_end, prev_pc);
712 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
718 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
722 cache->framereg = AARCH64_FP_REGNUM;
723 cache->framesize = 16;
724 cache->saved_regs[29].addr = 0;
725 cache->saved_regs[30].addr = 8;
729 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
730 function may throw an exception if the inferior's registers or memory is
734 aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
735 struct aarch64_prologue_cache *cache)
737 CORE_ADDR unwound_fp;
740 aarch64_scan_prologue (this_frame, cache);
742 if (cache->framereg == -1)
745 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
749 cache->prev_sp = unwound_fp + cache->framesize;
751 /* Calculate actual addresses of saved registers using offsets
752 determined by aarch64_analyze_prologue. */
753 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
754 if (trad_frame_addr_p (cache->saved_regs, reg))
755 cache->saved_regs[reg].addr += cache->prev_sp;
757 cache->func = get_frame_func (this_frame);
759 cache->available_p = 1;
762 /* Allocate and fill in *THIS_CACHE with information about the prologue of
763 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
764 Return a pointer to the current aarch64_prologue_cache in
767 static struct aarch64_prologue_cache *
768 aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
770 struct aarch64_prologue_cache *cache;
772 if (*this_cache != NULL)
773 return (struct aarch64_prologue_cache *) *this_cache;
775 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
776 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
781 aarch64_make_prologue_cache_1 (this_frame, cache);
783 CATCH (ex, RETURN_MASK_ERROR)
785 if (ex.error != NOT_AVAILABLE_ERROR)
786 throw_exception (ex);
793 /* Implement the "stop_reason" frame_unwind method. */
795 static enum unwind_stop_reason
796 aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
799 struct aarch64_prologue_cache *cache
800 = aarch64_make_prologue_cache (this_frame, this_cache);
802 if (!cache->available_p)
803 return UNWIND_UNAVAILABLE;
805 /* Halt the backtrace at "_start". */
806 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
807 return UNWIND_OUTERMOST;
809 /* We've hit a wall, stop. */
810 if (cache->prev_sp == 0)
811 return UNWIND_OUTERMOST;
813 return UNWIND_NO_REASON;
816 /* Our frame ID for a normal frame is the current function's starting
817 PC and the caller's SP when we were called. */
820 aarch64_prologue_this_id (struct frame_info *this_frame,
821 void **this_cache, struct frame_id *this_id)
823 struct aarch64_prologue_cache *cache
824 = aarch64_make_prologue_cache (this_frame, this_cache);
826 if (!cache->available_p)
827 *this_id = frame_id_build_unavailable_stack (cache->func);
829 *this_id = frame_id_build (cache->prev_sp, cache->func);
832 /* Implement the "prev_register" frame_unwind method. */
834 static struct value *
835 aarch64_prologue_prev_register (struct frame_info *this_frame,
836 void **this_cache, int prev_regnum)
838 struct aarch64_prologue_cache *cache
839 = aarch64_make_prologue_cache (this_frame, this_cache);
841 /* If we are asked to unwind the PC, then we need to return the LR
842 instead. The prologue may save PC, but it will point into this
843 frame's prologue, not the next frame's resume location. */
844 if (prev_regnum == AARCH64_PC_REGNUM)
848 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
849 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
852 /* SP is generally not saved to the stack, but this frame is
853 identified by the next frame's stack pointer at the time of the
854 call. The value was already reconstructed into PREV_SP. */
867 if (prev_regnum == AARCH64_SP_REGNUM)
868 return frame_unwind_got_constant (this_frame, prev_regnum,
871 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
875 /* AArch64 prologue unwinder. */
876 struct frame_unwind aarch64_prologue_unwind =
879 aarch64_prologue_frame_unwind_stop_reason,
880 aarch64_prologue_this_id,
881 aarch64_prologue_prev_register,
883 default_frame_sniffer
886 /* Allocate and fill in *THIS_CACHE with information about the prologue of
887 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
888 Return a pointer to the current aarch64_prologue_cache in
891 static struct aarch64_prologue_cache *
892 aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
894 struct aarch64_prologue_cache *cache;
896 if (*this_cache != NULL)
897 return (struct aarch64_prologue_cache *) *this_cache;
899 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
900 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
905 cache->prev_sp = get_frame_register_unsigned (this_frame,
907 cache->prev_pc = get_frame_pc (this_frame);
908 cache->available_p = 1;
910 CATCH (ex, RETURN_MASK_ERROR)
912 if (ex.error != NOT_AVAILABLE_ERROR)
913 throw_exception (ex);
920 /* Implement the "stop_reason" frame_unwind method. */
922 static enum unwind_stop_reason
923 aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
926 struct aarch64_prologue_cache *cache
927 = aarch64_make_stub_cache (this_frame, this_cache);
929 if (!cache->available_p)
930 return UNWIND_UNAVAILABLE;
932 return UNWIND_NO_REASON;
935 /* Our frame ID for a stub frame is the current SP and LR. */
938 aarch64_stub_this_id (struct frame_info *this_frame,
939 void **this_cache, struct frame_id *this_id)
941 struct aarch64_prologue_cache *cache
942 = aarch64_make_stub_cache (this_frame, this_cache);
944 if (cache->available_p)
945 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
947 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
950 /* Implement the "sniffer" frame_unwind method. */
953 aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
954 struct frame_info *this_frame,
955 void **this_prologue_cache)
957 CORE_ADDR addr_in_block;
960 addr_in_block = get_frame_address_in_block (this_frame);
961 if (in_plt_section (addr_in_block)
962 /* We also use the stub winder if the target memory is unreadable
963 to avoid having the prologue unwinder trying to read it. */
964 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
970 /* AArch64 stub unwinder. */
971 struct frame_unwind aarch64_stub_unwind =
974 aarch64_stub_frame_unwind_stop_reason,
975 aarch64_stub_this_id,
976 aarch64_prologue_prev_register,
978 aarch64_stub_unwind_sniffer
981 /* Return the frame base address of *THIS_FRAME. */
984 aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
986 struct aarch64_prologue_cache *cache
987 = aarch64_make_prologue_cache (this_frame, this_cache);
989 return cache->prev_sp - cache->framesize;
992 /* AArch64 default frame base information. */
993 struct frame_base aarch64_normal_base =
995 &aarch64_prologue_unwind,
996 aarch64_normal_frame_base,
997 aarch64_normal_frame_base,
998 aarch64_normal_frame_base
1001 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1002 dummy frame. The frame ID's base needs to match the TOS value
1003 saved by save_dummy_frame_tos () and returned from
1004 aarch64_push_dummy_call, and the PC needs to match the dummy
1005 frame's breakpoint. */
1007 static struct frame_id
1008 aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1010 return frame_id_build (get_frame_register_unsigned (this_frame,
1012 get_frame_pc (this_frame));
1015 /* Implement the "unwind_pc" gdbarch method. */
1018 aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1021 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
1026 /* Implement the "unwind_sp" gdbarch method. */
1029 aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1031 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
1034 /* Return the value of the REGNUM register in the previous frame of
1037 static struct value *
1038 aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1039 void **this_cache, int regnum)
1045 case AARCH64_PC_REGNUM:
1046 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1047 return frame_unwind_got_constant (this_frame, regnum, lr);
1050 internal_error (__FILE__, __LINE__,
1051 _("Unexpected register %d"), regnum);
1055 /* Implement the "init_reg" dwarf2_frame_ops method. */
1058 aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1059 struct dwarf2_frame_state_reg *reg,
1060 struct frame_info *this_frame)
1064 case AARCH64_PC_REGNUM:
1065 reg->how = DWARF2_FRAME_REG_FN;
1066 reg->loc.fn = aarch64_dwarf2_prev_register;
1068 case AARCH64_SP_REGNUM:
1069 reg->how = DWARF2_FRAME_REG_CFA;
1074 /* When arguments must be pushed onto the stack, they go on in reverse
1075 order. The code below implements a FILO (stack) to do this. */
1079 /* Value to pass on stack. It can be NULL if this item is for stack
1081 const gdb_byte *data;
1083 /* Size in bytes of value to pass on stack. */
1087 DEF_VEC_O (stack_item_t);
1089 /* Return the alignment (in bytes) of the given type. */
1092 aarch64_type_align (struct type *t)
1098 t = check_typedef (t);
1099 switch (TYPE_CODE (t))
1102 /* Should never happen. */
1103 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1107 case TYPE_CODE_ENUM:
1111 case TYPE_CODE_RANGE:
1112 case TYPE_CODE_BITSTRING:
1114 case TYPE_CODE_RVALUE_REF:
1115 case TYPE_CODE_CHAR:
1116 case TYPE_CODE_BOOL:
1117 return TYPE_LENGTH (t);
1119 case TYPE_CODE_ARRAY:
1120 if (TYPE_VECTOR (t))
1122 /* Use the natural alignment for vector types (the same for
1123 scalar type), but the maximum alignment is 128-bit. */
1124 if (TYPE_LENGTH (t) > 16)
1127 return TYPE_LENGTH (t);
1130 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1131 case TYPE_CODE_COMPLEX:
1132 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1134 case TYPE_CODE_STRUCT:
1135 case TYPE_CODE_UNION:
1137 for (n = 0; n < TYPE_NFIELDS (t); n++)
1139 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
1147 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1149 Return the number of register required, or -1 on failure.
1151 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1152 to the element, else fail if the type of this element does not match the
1156 aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1157 struct type **fundamental_type)
1159 if (type == nullptr)
1162 switch (TYPE_CODE (type))
1165 if (TYPE_LENGTH (type) > 16)
1168 if (*fundamental_type == nullptr)
1169 *fundamental_type = type;
1170 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1171 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1176 case TYPE_CODE_COMPLEX:
1178 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1179 if (TYPE_LENGTH (target_type) > 16)
1182 if (*fundamental_type == nullptr)
1183 *fundamental_type = target_type;
1184 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1185 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1191 case TYPE_CODE_ARRAY:
1193 if (TYPE_VECTOR (type))
1195 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1198 if (*fundamental_type == nullptr)
1199 *fundamental_type = type;
1200 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1201 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1208 struct type *target_type = TYPE_TARGET_TYPE (type);
1209 int count = aapcs_is_vfp_call_or_return_candidate_1
1210 (target_type, fundamental_type);
1215 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
1220 case TYPE_CODE_STRUCT:
1221 case TYPE_CODE_UNION:
1225 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1227 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1229 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1230 (member, fundamental_type);
1231 if (sub_count == -1)
1245 /* Return true if an argument, whose type is described by TYPE, can be passed or
1246 returned in simd/fp registers, providing enough parameter passing registers
1247 are available. This is as described in the AAPCS64.
1249 Upon successful return, *COUNT returns the number of needed registers,
1250 *FUNDAMENTAL_TYPE contains the type of those registers.
1252 Candidate as per the AAPCS64 5.4.2.C is either a:
1255 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1256 all the members are floats and has at most 4 members.
1257 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1258 all the members are short vectors and has at most 4 members.
1261 Note that HFAs and HVAs can include nested structures and arrays. */
1264 aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1265 struct type **fundamental_type)
1267 if (type == nullptr)
1270 *fundamental_type = nullptr;
1272 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1275 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1284 /* AArch64 function call information structure. */
1285 struct aarch64_call_info
1287 /* the current argument number. */
1290 /* The next general purpose register number, equivalent to NGRN as
1291 described in the AArch64 Procedure Call Standard. */
1294 /* The next SIMD and floating point register number, equivalent to
1295 NSRN as described in the AArch64 Procedure Call Standard. */
1298 /* The next stacked argument address, equivalent to NSAA as
1299 described in the AArch64 Procedure Call Standard. */
1302 /* Stack item vector. */
1303 VEC(stack_item_t) *si;
1306 /* Pass a value in a sequence of consecutive X registers. The caller
1307 is responsbile for ensuring sufficient registers are available. */
1310 pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1311 struct aarch64_call_info *info, struct type *type,
1314 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1315 int len = TYPE_LENGTH (type);
1316 enum type_code typecode = TYPE_CODE (type);
1317 int regnum = AARCH64_X0_REGNUM + info->ngrn;
1318 const bfd_byte *buf = value_contents (arg);
1324 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1325 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1329 /* Adjust sub-word struct/union args when big-endian. */
1330 if (byte_order == BFD_ENDIAN_BIG
1331 && partial_len < X_REGISTER_SIZE
1332 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1333 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1337 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1338 gdbarch_register_name (gdbarch, regnum),
1339 phex (regval, X_REGISTER_SIZE));
1341 regcache_cooked_write_unsigned (regcache, regnum, regval);
1348 /* Attempt to marshall a value in a V register. Return 1 if
1349 successful, or 0 if insufficient registers are available. This
1350 function, unlike the equivalent pass_in_x() function does not
1351 handle arguments spread across multiple registers. */
1354 pass_in_v (struct gdbarch *gdbarch,
1355 struct regcache *regcache,
1356 struct aarch64_call_info *info,
1357 int len, const bfd_byte *buf)
1361 int regnum = AARCH64_V0_REGNUM + info->nsrn;
1362 /* Enough space for a full vector register. */
1363 gdb_byte reg[register_size (gdbarch, regnum)];
1364 gdb_assert (len <= sizeof (reg));
1369 memset (reg, 0, sizeof (reg));
1370 /* PCS C.1, the argument is allocated to the least significant
1371 bits of V register. */
1372 memcpy (reg, buf, len);
1373 regcache->cooked_write (regnum, reg);
1377 debug_printf ("arg %d in %s\n", info->argnum,
1378 gdbarch_register_name (gdbarch, regnum));
1386 /* Marshall an argument onto the stack. */
1389 pass_on_stack (struct aarch64_call_info *info, struct type *type,
1392 const bfd_byte *buf = value_contents (arg);
1393 int len = TYPE_LENGTH (type);
1399 align = aarch64_type_align (type);
1401 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1402 Natural alignment of the argument's type. */
1403 align = align_up (align, 8);
1405 /* The AArch64 PCS requires at most doubleword alignment. */
1411 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1417 VEC_safe_push (stack_item_t, info->si, &item);
1420 if (info->nsaa & (align - 1))
1422 /* Push stack alignment padding. */
1423 int pad = align - (info->nsaa & (align - 1));
1428 VEC_safe_push (stack_item_t, info->si, &item);
1433 /* Marshall an argument into a sequence of one or more consecutive X
1434 registers or, if insufficient X registers are available then onto
1438 pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1439 struct aarch64_call_info *info, struct type *type,
1442 int len = TYPE_LENGTH (type);
1443 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1445 /* PCS C.13 - Pass in registers if we have enough spare */
1446 if (info->ngrn + nregs <= 8)
1448 pass_in_x (gdbarch, regcache, info, type, arg);
1449 info->ngrn += nregs;
1454 pass_on_stack (info, type, arg);
1458 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1459 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1460 registers. A return value of false is an error state as the value will have
1461 been partially passed to the stack. */
1463 pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1464 struct aarch64_call_info *info, struct type *arg_type,
1467 switch (TYPE_CODE (arg_type))
1470 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1471 value_contents (arg));
1474 case TYPE_CODE_COMPLEX:
1476 const bfd_byte *buf = value_contents (arg);
1477 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1479 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1483 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1484 buf + TYPE_LENGTH (target_type));
1487 case TYPE_CODE_ARRAY:
1488 if (TYPE_VECTOR (arg_type))
1489 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1490 value_contents (arg));
1493 case TYPE_CODE_STRUCT:
1494 case TYPE_CODE_UNION:
1495 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1497 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1498 struct type *field_type = check_typedef (value_type (field));
1500 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1511 /* Implement the "push_dummy_call" gdbarch method. */
1514 aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1515 struct regcache *regcache, CORE_ADDR bp_addr,
1517 struct value **args, CORE_ADDR sp, int struct_return,
1518 CORE_ADDR struct_addr)
1521 struct aarch64_call_info info;
1522 struct type *func_type;
1523 struct type *return_type;
1524 int lang_struct_return;
1526 memset (&info, 0, sizeof (info));
1528 /* We need to know what the type of the called function is in order
1529 to determine the number of named/anonymous arguments for the
1530 actual argument placement, and the return type in order to handle
1531 return value correctly.
1533 The generic code above us views the decision of return in memory
1534 or return in registers as a two stage processes. The language
1535 handler is consulted first and may decide to return in memory (eg
1536 class with copy constructor returned by value), this will cause
1537 the generic code to allocate space AND insert an initial leading
1540 If the language code does not decide to pass in memory then the
1541 target code is consulted.
1543 If the language code decides to pass in memory we want to move
1544 the pointer inserted as the initial argument from the argument
1545 list and into X8, the conventional AArch64 struct return pointer
1548 This is slightly awkward, ideally the flag "lang_struct_return"
1549 would be passed to the targets implementation of push_dummy_call.
1550 Rather that change the target interface we call the language code
1551 directly ourselves. */
1553 func_type = check_typedef (value_type (function));
1555 /* Dereference function pointer types. */
1556 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1557 func_type = TYPE_TARGET_TYPE (func_type);
1559 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1560 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1562 /* If language_pass_by_reference () returned true we will have been
1563 given an additional initial argument, a hidden pointer to the
1564 return slot in memory. */
1565 return_type = TYPE_TARGET_TYPE (func_type);
1566 lang_struct_return = language_pass_by_reference (return_type);
1568 /* Set the return address. For the AArch64, the return breakpoint
1569 is always at BP_ADDR. */
1570 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1572 /* If we were given an initial argument for the return slot because
1573 lang_struct_return was true, lose it. */
1574 if (lang_struct_return)
1580 /* The struct_return pointer occupies X8. */
1581 if (struct_return || lang_struct_return)
1585 debug_printf ("struct return in %s = 0x%s\n",
1586 gdbarch_register_name (gdbarch,
1587 AARCH64_STRUCT_RETURN_REGNUM),
1588 paddress (gdbarch, struct_addr));
1590 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1594 for (argnum = 0; argnum < nargs; argnum++)
1596 struct value *arg = args[argnum];
1597 struct type *arg_type, *fundamental_type;
1600 arg_type = check_typedef (value_type (arg));
1601 len = TYPE_LENGTH (arg_type);
1603 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1604 if there are enough spare registers. */
1605 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1608 if (info.nsrn + elements <= 8)
1610 /* We know that we have sufficient registers available therefore
1611 this will never need to fallback to the stack. */
1612 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1614 gdb_assert_not_reached ("Failed to push args");
1619 pass_on_stack (&info, arg_type, arg);
1624 switch (TYPE_CODE (arg_type))
1627 case TYPE_CODE_BOOL:
1628 case TYPE_CODE_CHAR:
1629 case TYPE_CODE_RANGE:
1630 case TYPE_CODE_ENUM:
1633 /* Promote to 32 bit integer. */
1634 if (TYPE_UNSIGNED (arg_type))
1635 arg_type = builtin_type (gdbarch)->builtin_uint32;
1637 arg_type = builtin_type (gdbarch)->builtin_int32;
1638 arg = value_cast (arg_type, arg);
1640 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1643 case TYPE_CODE_STRUCT:
1644 case TYPE_CODE_ARRAY:
1645 case TYPE_CODE_UNION:
1648 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1649 invisible reference. */
1651 /* Allocate aligned storage. */
1652 sp = align_down (sp - len, 16);
1654 /* Write the real data into the stack. */
1655 write_memory (sp, value_contents (arg), len);
1657 /* Construct the indirection. */
1658 arg_type = lookup_pointer_type (arg_type);
1659 arg = value_from_pointer (arg_type, sp);
1660 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1663 /* PCS C.15 / C.18 multiple values pass. */
1664 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1668 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1673 /* Make sure stack retains 16 byte alignment. */
1675 sp -= 16 - (info.nsaa & 15);
1677 while (!VEC_empty (stack_item_t, info.si))
1679 stack_item_t *si = VEC_last (stack_item_t, info.si);
1682 if (si->data != NULL)
1683 write_memory (sp, si->data, si->len);
1684 VEC_pop (stack_item_t, info.si);
1687 VEC_free (stack_item_t, info.si);
1689 /* Finally, update the SP register. */
1690 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1695 /* Implement the "frame_align" gdbarch method. */
1698 aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1700 /* Align the stack to sixteen bytes. */
1701 return sp & ~(CORE_ADDR) 15;
1704 /* Return the type for an AdvSISD Q register. */
1706 static struct type *
1707 aarch64_vnq_type (struct gdbarch *gdbarch)
1709 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1711 if (tdep->vnq_type == NULL)
1716 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1719 elem = builtin_type (gdbarch)->builtin_uint128;
1720 append_composite_type_field (t, "u", elem);
1722 elem = builtin_type (gdbarch)->builtin_int128;
1723 append_composite_type_field (t, "s", elem);
1728 return tdep->vnq_type;
1731 /* Return the type for an AdvSISD D register. */
1733 static struct type *
1734 aarch64_vnd_type (struct gdbarch *gdbarch)
1736 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1738 if (tdep->vnd_type == NULL)
1743 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1746 elem = builtin_type (gdbarch)->builtin_double;
1747 append_composite_type_field (t, "f", elem);
1749 elem = builtin_type (gdbarch)->builtin_uint64;
1750 append_composite_type_field (t, "u", elem);
1752 elem = builtin_type (gdbarch)->builtin_int64;
1753 append_composite_type_field (t, "s", elem);
1758 return tdep->vnd_type;
1761 /* Return the type for an AdvSISD S register. */
1763 static struct type *
1764 aarch64_vns_type (struct gdbarch *gdbarch)
1766 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1768 if (tdep->vns_type == NULL)
1773 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1776 elem = builtin_type (gdbarch)->builtin_float;
1777 append_composite_type_field (t, "f", elem);
1779 elem = builtin_type (gdbarch)->builtin_uint32;
1780 append_composite_type_field (t, "u", elem);
1782 elem = builtin_type (gdbarch)->builtin_int32;
1783 append_composite_type_field (t, "s", elem);
1788 return tdep->vns_type;
1791 /* Return the type for an AdvSISD H register. */
1793 static struct type *
1794 aarch64_vnh_type (struct gdbarch *gdbarch)
1796 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1798 if (tdep->vnh_type == NULL)
1803 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1806 elem = builtin_type (gdbarch)->builtin_uint16;
1807 append_composite_type_field (t, "u", elem);
1809 elem = builtin_type (gdbarch)->builtin_int16;
1810 append_composite_type_field (t, "s", elem);
1815 return tdep->vnh_type;
1818 /* Return the type for an AdvSISD B register. */
1820 static struct type *
1821 aarch64_vnb_type (struct gdbarch *gdbarch)
1823 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1825 if (tdep->vnb_type == NULL)
1830 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1833 elem = builtin_type (gdbarch)->builtin_uint8;
1834 append_composite_type_field (t, "u", elem);
1836 elem = builtin_type (gdbarch)->builtin_int8;
1837 append_composite_type_field (t, "s", elem);
1842 return tdep->vnb_type;
1845 /* Return the type for an AdvSISD V register. */
1847 static struct type *
1848 aarch64_vnv_type (struct gdbarch *gdbarch)
1850 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1852 if (tdep->vnv_type == NULL)
1854 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1857 append_composite_type_field (t, "d", aarch64_vnd_type (gdbarch));
1858 append_composite_type_field (t, "s", aarch64_vns_type (gdbarch));
1859 append_composite_type_field (t, "h", aarch64_vnh_type (gdbarch));
1860 append_composite_type_field (t, "b", aarch64_vnb_type (gdbarch));
1861 append_composite_type_field (t, "q", aarch64_vnq_type (gdbarch));
1866 return tdep->vnv_type;
1869 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1872 aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1874 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1875 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1877 if (reg == AARCH64_DWARF_SP)
1878 return AARCH64_SP_REGNUM;
1880 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1881 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1883 if (reg == AARCH64_DWARF_SVE_VG)
1884 return AARCH64_SVE_VG_REGNUM;
1886 if (reg == AARCH64_DWARF_SVE_FFR)
1887 return AARCH64_SVE_FFR_REGNUM;
1889 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
1890 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
1892 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
1893 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
1898 /* Implement the "print_insn" gdbarch method. */
1901 aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1903 info->symbols = NULL;
1904 return default_print_insn (memaddr, info);
1907 /* AArch64 BRK software debug mode instruction.
1908 Note that AArch64 code is always little-endian.
1909 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1910 constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
1912 typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
1914 /* Extract from an array REGS containing the (raw) register state a
1915 function return value of type TYPE, and copy that, in virtual
1916 format, into VALBUF. */
1919 aarch64_extract_return_value (struct type *type, struct regcache *regs,
1922 struct gdbarch *gdbarch = regs->arch ();
1923 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1925 struct type *fundamental_type;
1927 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
1930 int len = TYPE_LENGTH (fundamental_type);
1932 for (int i = 0; i < elements; i++)
1934 int regno = AARCH64_V0_REGNUM + i;
1935 /* Enough space for a full vector register. */
1936 gdb_byte buf[register_size (gdbarch, regno)];
1937 gdb_assert (len <= sizeof (buf));
1941 debug_printf ("read HFA or HVA return value element %d from %s\n",
1943 gdbarch_register_name (gdbarch, regno));
1945 regs->cooked_read (regno, buf);
1947 memcpy (valbuf, buf, len);
1951 else if (TYPE_CODE (type) == TYPE_CODE_INT
1952 || TYPE_CODE (type) == TYPE_CODE_CHAR
1953 || TYPE_CODE (type) == TYPE_CODE_BOOL
1954 || TYPE_CODE (type) == TYPE_CODE_PTR
1955 || TYPE_IS_REFERENCE (type)
1956 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1958 /* If the the type is a plain integer, then the access is
1959 straight-forward. Otherwise we have to play around a bit
1961 int len = TYPE_LENGTH (type);
1962 int regno = AARCH64_X0_REGNUM;
1967 /* By using store_unsigned_integer we avoid having to do
1968 anything special for small big-endian values. */
1969 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1970 store_unsigned_integer (valbuf,
1971 (len > X_REGISTER_SIZE
1972 ? X_REGISTER_SIZE : len), byte_order, tmp);
1973 len -= X_REGISTER_SIZE;
1974 valbuf += X_REGISTER_SIZE;
1979 /* For a structure or union the behaviour is as if the value had
1980 been stored to word-aligned memory and then loaded into
1981 registers with 64-bit load instruction(s). */
1982 int len = TYPE_LENGTH (type);
1983 int regno = AARCH64_X0_REGNUM;
1984 bfd_byte buf[X_REGISTER_SIZE];
1988 regs->cooked_read (regno++, buf);
1989 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1990 len -= X_REGISTER_SIZE;
1991 valbuf += X_REGISTER_SIZE;
1997 /* Will a function return an aggregate type in memory or in a
1998 register? Return 0 if an aggregate type can be returned in a
1999 register, 1 if it must be returned in memory. */
2002 aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2004 type = check_typedef (type);
2006 struct type *fundamental_type;
2008 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2011 /* v0-v7 are used to return values and one register is allocated
2012 for one member. However, HFA or HVA has at most four members. */
2016 if (TYPE_LENGTH (type) > 16)
2018 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2019 invisible reference. */
2027 /* Write into appropriate registers a function return value of type
2028 TYPE, given in virtual format. */
2031 aarch64_store_return_value (struct type *type, struct regcache *regs,
2032 const gdb_byte *valbuf)
2034 struct gdbarch *gdbarch = regs->arch ();
2035 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2037 struct type *fundamental_type;
2039 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2042 int len = TYPE_LENGTH (fundamental_type);
2044 for (int i = 0; i < elements; i++)
2046 int regno = AARCH64_V0_REGNUM + i;
2047 /* Enough space for a full vector register. */
2048 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2049 gdb_assert (len <= sizeof (tmpbuf));
2053 debug_printf ("write HFA or HVA return value element %d to %s\n",
2055 gdbarch_register_name (gdbarch, regno));
2058 memcpy (tmpbuf, valbuf,
2059 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2060 regs->cooked_write (regno, tmpbuf);
2064 else if (TYPE_CODE (type) == TYPE_CODE_INT
2065 || TYPE_CODE (type) == TYPE_CODE_CHAR
2066 || TYPE_CODE (type) == TYPE_CODE_BOOL
2067 || TYPE_CODE (type) == TYPE_CODE_PTR
2068 || TYPE_IS_REFERENCE (type)
2069 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2071 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2073 /* Values of one word or less are zero/sign-extended and
2075 bfd_byte tmpbuf[X_REGISTER_SIZE];
2076 LONGEST val = unpack_long (type, valbuf);
2078 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
2079 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
2083 /* Integral values greater than one word are stored in
2084 consecutive registers starting with r0. This will always
2085 be a multiple of the regiser size. */
2086 int len = TYPE_LENGTH (type);
2087 int regno = AARCH64_X0_REGNUM;
2091 regs->cooked_write (regno++, valbuf);
2092 len -= X_REGISTER_SIZE;
2093 valbuf += X_REGISTER_SIZE;
2099 /* For a structure or union the behaviour is as if the value had
2100 been stored to word-aligned memory and then loaded into
2101 registers with 64-bit load instruction(s). */
2102 int len = TYPE_LENGTH (type);
2103 int regno = AARCH64_X0_REGNUM;
2104 bfd_byte tmpbuf[X_REGISTER_SIZE];
2108 memcpy (tmpbuf, valbuf,
2109 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2110 regs->cooked_write (regno++, tmpbuf);
2111 len -= X_REGISTER_SIZE;
2112 valbuf += X_REGISTER_SIZE;
2117 /* Implement the "return_value" gdbarch method. */
2119 static enum return_value_convention
2120 aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2121 struct type *valtype, struct regcache *regcache,
2122 gdb_byte *readbuf, const gdb_byte *writebuf)
2125 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2126 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2127 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2129 if (aarch64_return_in_memory (gdbarch, valtype))
2132 debug_printf ("return value in memory\n");
2133 return RETURN_VALUE_STRUCT_CONVENTION;
2138 aarch64_store_return_value (valtype, regcache, writebuf);
2141 aarch64_extract_return_value (valtype, regcache, readbuf);
2144 debug_printf ("return value in registers\n");
2146 return RETURN_VALUE_REGISTER_CONVENTION;
2149 /* Implement the "get_longjmp_target" gdbarch method. */
2152 aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2155 gdb_byte buf[X_REGISTER_SIZE];
2156 struct gdbarch *gdbarch = get_frame_arch (frame);
2157 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2158 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2160 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2162 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2166 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2170 /* Implement the "gen_return_address" gdbarch method. */
2173 aarch64_gen_return_address (struct gdbarch *gdbarch,
2174 struct agent_expr *ax, struct axs_value *value,
2177 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2178 value->kind = axs_lvalue_register;
2179 value->u.reg = AARCH64_LR_REGNUM;
2183 /* Return the pseudo register name corresponding to register regnum. */
2186 aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2188 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2190 static const char *const q_name[] =
2192 "q0", "q1", "q2", "q3",
2193 "q4", "q5", "q6", "q7",
2194 "q8", "q9", "q10", "q11",
2195 "q12", "q13", "q14", "q15",
2196 "q16", "q17", "q18", "q19",
2197 "q20", "q21", "q22", "q23",
2198 "q24", "q25", "q26", "q27",
2199 "q28", "q29", "q30", "q31",
2202 static const char *const d_name[] =
2204 "d0", "d1", "d2", "d3",
2205 "d4", "d5", "d6", "d7",
2206 "d8", "d9", "d10", "d11",
2207 "d12", "d13", "d14", "d15",
2208 "d16", "d17", "d18", "d19",
2209 "d20", "d21", "d22", "d23",
2210 "d24", "d25", "d26", "d27",
2211 "d28", "d29", "d30", "d31",
2214 static const char *const s_name[] =
2216 "s0", "s1", "s2", "s3",
2217 "s4", "s5", "s6", "s7",
2218 "s8", "s9", "s10", "s11",
2219 "s12", "s13", "s14", "s15",
2220 "s16", "s17", "s18", "s19",
2221 "s20", "s21", "s22", "s23",
2222 "s24", "s25", "s26", "s27",
2223 "s28", "s29", "s30", "s31",
2226 static const char *const h_name[] =
2228 "h0", "h1", "h2", "h3",
2229 "h4", "h5", "h6", "h7",
2230 "h8", "h9", "h10", "h11",
2231 "h12", "h13", "h14", "h15",
2232 "h16", "h17", "h18", "h19",
2233 "h20", "h21", "h22", "h23",
2234 "h24", "h25", "h26", "h27",
2235 "h28", "h29", "h30", "h31",
2238 static const char *const b_name[] =
2240 "b0", "b1", "b2", "b3",
2241 "b4", "b5", "b6", "b7",
2242 "b8", "b9", "b10", "b11",
2243 "b12", "b13", "b14", "b15",
2244 "b16", "b17", "b18", "b19",
2245 "b20", "b21", "b22", "b23",
2246 "b24", "b25", "b26", "b27",
2247 "b28", "b29", "b30", "b31",
2250 regnum -= gdbarch_num_regs (gdbarch);
2252 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2253 return q_name[regnum - AARCH64_Q0_REGNUM];
2255 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2256 return d_name[regnum - AARCH64_D0_REGNUM];
2258 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2259 return s_name[regnum - AARCH64_S0_REGNUM];
2261 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2262 return h_name[regnum - AARCH64_H0_REGNUM];
2264 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2265 return b_name[regnum - AARCH64_B0_REGNUM];
2267 if (tdep->has_sve ())
2269 static const char *const sve_v_name[] =
2271 "v0", "v1", "v2", "v3",
2272 "v4", "v5", "v6", "v7",
2273 "v8", "v9", "v10", "v11",
2274 "v12", "v13", "v14", "v15",
2275 "v16", "v17", "v18", "v19",
2276 "v20", "v21", "v22", "v23",
2277 "v24", "v25", "v26", "v27",
2278 "v28", "v29", "v30", "v31",
2281 if (regnum >= AARCH64_SVE_V0_REGNUM
2282 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2283 return sve_v_name[regnum - AARCH64_SVE_V0_REGNUM];
2286 internal_error (__FILE__, __LINE__,
2287 _("aarch64_pseudo_register_name: bad register number %d"),
2291 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2293 static struct type *
2294 aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2298 regnum -= gdbarch_num_regs (gdbarch);
2300 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2301 return aarch64_vnq_type (gdbarch);
2303 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2304 return aarch64_vnd_type (gdbarch);
2306 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2307 return aarch64_vns_type (gdbarch);
2309 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2310 return aarch64_vnh_type (gdbarch);
2312 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2313 return aarch64_vnb_type (gdbarch);
2315 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2316 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2317 return aarch64_vnv_type (gdbarch);
2319 internal_error (__FILE__, __LINE__,
2320 _("aarch64_pseudo_register_type: bad register number %d"),
2324 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2327 aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2328 struct reggroup *group)
2330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2332 regnum -= gdbarch_num_regs (gdbarch);
2334 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2335 return group == all_reggroup || group == vector_reggroup;
2336 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2337 return (group == all_reggroup || group == vector_reggroup
2338 || group == float_reggroup);
2339 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2340 return (group == all_reggroup || group == vector_reggroup
2341 || group == float_reggroup);
2342 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2343 return group == all_reggroup || group == vector_reggroup;
2344 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2345 return group == all_reggroup || group == vector_reggroup;
2346 else if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2347 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2348 return group == all_reggroup || group == vector_reggroup;
2350 return group == all_reggroup;
2353 /* Helper for aarch64_pseudo_read_value. */
2355 static struct value *
2356 aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2357 readable_regcache *regcache, int regnum_offset,
2358 int regsize, struct value *result_value)
2360 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2362 /* Enough space for a full vector register. */
2363 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2364 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2366 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2367 mark_value_bytes_unavailable (result_value, 0,
2368 TYPE_LENGTH (value_type (result_value)));
2370 memcpy (value_contents_raw (result_value), reg_buf, regsize);
2372 return result_value;
2375 /* Implement the "pseudo_register_read_value" gdbarch method. */
2377 static struct value *
2378 aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
2381 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2382 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
2384 VALUE_LVAL (result_value) = lval_register;
2385 VALUE_REGNUM (result_value) = regnum;
2387 regnum -= gdbarch_num_regs (gdbarch);
2389 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2390 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2391 regnum - AARCH64_Q0_REGNUM,
2392 Q_REGISTER_SIZE, result_value);
2394 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2395 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2396 regnum - AARCH64_D0_REGNUM,
2397 D_REGISTER_SIZE, result_value);
2399 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2400 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2401 regnum - AARCH64_S0_REGNUM,
2402 S_REGISTER_SIZE, result_value);
2404 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2405 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2406 regnum - AARCH64_H0_REGNUM,
2407 H_REGISTER_SIZE, result_value);
2409 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2410 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2411 regnum - AARCH64_B0_REGNUM,
2412 B_REGISTER_SIZE, result_value);
2414 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2415 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2416 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2417 regnum - AARCH64_SVE_V0_REGNUM,
2418 V_REGISTER_SIZE, result_value);
2420 gdb_assert_not_reached ("regnum out of bound");
2423 /* Helper for aarch64_pseudo_write. */
2426 aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2427 int regnum_offset, int regsize, const gdb_byte *buf)
2429 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2431 /* Enough space for a full vector register. */
2432 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2433 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2435 /* Ensure the register buffer is zero, we want gdb writes of the
2436 various 'scalar' pseudo registers to behavior like architectural
2437 writes, register width bytes are written the remainder are set to
2439 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
2441 memcpy (reg_buf, buf, regsize);
2442 regcache->raw_write (v_regnum, reg_buf);
2445 /* Implement the "pseudo_register_write" gdbarch method. */
2448 aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2449 int regnum, const gdb_byte *buf)
2451 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2452 regnum -= gdbarch_num_regs (gdbarch);
2454 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2455 return aarch64_pseudo_write_1 (gdbarch, regcache,
2456 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2459 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2460 return aarch64_pseudo_write_1 (gdbarch, regcache,
2461 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2464 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2465 return aarch64_pseudo_write_1 (gdbarch, regcache,
2466 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2469 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2470 return aarch64_pseudo_write_1 (gdbarch, regcache,
2471 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2474 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2475 return aarch64_pseudo_write_1 (gdbarch, regcache,
2476 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2479 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2480 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2481 return aarch64_pseudo_write_1 (gdbarch, regcache,
2482 regnum - AARCH64_SVE_V0_REGNUM,
2483 V_REGISTER_SIZE, buf);
2485 gdb_assert_not_reached ("regnum out of bound");
2488 /* Callback function for user_reg_add. */
2490 static struct value *
2491 value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2493 const int *reg_p = (const int *) baton;
2495 return value_of_register (*reg_p, frame);
2499 /* Implement the "software_single_step" gdbarch method, needed to
2500 single step through atomic sequences on AArch64. */
2502 static std::vector<CORE_ADDR>
2503 aarch64_software_single_step (struct regcache *regcache)
2505 struct gdbarch *gdbarch = regcache->arch ();
2506 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2507 const int insn_size = 4;
2508 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2509 CORE_ADDR pc = regcache_read_pc (regcache);
2510 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
2512 CORE_ADDR closing_insn = 0;
2513 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2514 byte_order_for_code);
2517 int bc_insn_count = 0; /* Conditional branch instruction count. */
2518 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2521 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2524 /* Look for a Load Exclusive instruction which begins the sequence. */
2525 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
2528 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2531 insn = read_memory_unsigned_integer (loc, insn_size,
2532 byte_order_for_code);
2534 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2536 /* Check if the instruction is a conditional branch. */
2537 if (inst.opcode->iclass == condbranch)
2539 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2541 if (bc_insn_count >= 1)
2544 /* It is, so we'll try to set a breakpoint at the destination. */
2545 breaks[1] = loc + inst.operands[0].imm.value;
2551 /* Look for the Store Exclusive which closes the atomic sequence. */
2552 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
2559 /* We didn't find a closing Store Exclusive instruction, fall back. */
2563 /* Insert breakpoint after the end of the atomic sequence. */
2564 breaks[0] = loc + insn_size;
2566 /* Check for duplicated breakpoints, and also check that the second
2567 breakpoint is not within the atomic sequence. */
2569 && (breaks[1] == breaks[0]
2570 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2571 last_breakpoint = 0;
2573 std::vector<CORE_ADDR> next_pcs;
2575 /* Insert the breakpoint at the end of the sequence, and one at the
2576 destination of the conditional branch, if it exists. */
2577 for (index = 0; index <= last_breakpoint; index++)
2578 next_pcs.push_back (breaks[index]);
2583 struct aarch64_displaced_step_closure : public displaced_step_closure
2585 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2586 is being displaced stepping. */
2589 /* PC adjustment offset after displaced stepping. */
2590 int32_t pc_adjust = 0;
2593 /* Data when visiting instructions for displaced stepping. */
2595 struct aarch64_displaced_step_data
2597 struct aarch64_insn_data base;
2599 /* The address where the instruction will be executed at. */
2601 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2602 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2603 /* Number of instructions in INSN_BUF. */
2604 unsigned insn_count;
2605 /* Registers when doing displaced stepping. */
2606 struct regcache *regs;
2608 aarch64_displaced_step_closure *dsc;
2611 /* Implementation of aarch64_insn_visitor method "b". */
2614 aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2615 struct aarch64_insn_data *data)
2617 struct aarch64_displaced_step_data *dsd
2618 = (struct aarch64_displaced_step_data *) data;
2619 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
2621 if (can_encode_int32 (new_offset, 28))
2623 /* Emit B rather than BL, because executing BL on a new address
2624 will get the wrong address into LR. In order to avoid this,
2625 we emit B, and update LR if the instruction is BL. */
2626 emit_b (dsd->insn_buf, 0, new_offset);
2632 emit_nop (dsd->insn_buf);
2634 dsd->dsc->pc_adjust = offset;
2640 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2641 data->insn_addr + 4);
2645 /* Implementation of aarch64_insn_visitor method "b_cond". */
2648 aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2649 struct aarch64_insn_data *data)
2651 struct aarch64_displaced_step_data *dsd
2652 = (struct aarch64_displaced_step_data *) data;
2654 /* GDB has to fix up PC after displaced step this instruction
2655 differently according to the condition is true or false. Instead
2656 of checking COND against conditional flags, we can use
2657 the following instructions, and GDB can tell how to fix up PC
2658 according to the PC value.
2660 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2666 emit_bcond (dsd->insn_buf, cond, 8);
2668 dsd->dsc->pc_adjust = offset;
2669 dsd->insn_count = 1;
2672 /* Dynamically allocate a new register. If we know the register
2673 statically, we should make it a global as above instead of using this
2676 static struct aarch64_register
2677 aarch64_register (unsigned num, int is64)
2679 return (struct aarch64_register) { num, is64 };
2682 /* Implementation of aarch64_insn_visitor method "cb". */
2685 aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2686 const unsigned rn, int is64,
2687 struct aarch64_insn_data *data)
2689 struct aarch64_displaced_step_data *dsd
2690 = (struct aarch64_displaced_step_data *) data;
2692 /* The offset is out of range for a compare and branch
2693 instruction. We can use the following instructions instead:
2695 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2700 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2701 dsd->insn_count = 1;
2703 dsd->dsc->pc_adjust = offset;
2706 /* Implementation of aarch64_insn_visitor method "tb". */
2709 aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2710 const unsigned rt, unsigned bit,
2711 struct aarch64_insn_data *data)
2713 struct aarch64_displaced_step_data *dsd
2714 = (struct aarch64_displaced_step_data *) data;
2716 /* The offset is out of range for a test bit and branch
2717 instruction We can use the following instructions instead:
2719 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2725 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2726 dsd->insn_count = 1;
2728 dsd->dsc->pc_adjust = offset;
2731 /* Implementation of aarch64_insn_visitor method "adr". */
2734 aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2735 const int is_adrp, struct aarch64_insn_data *data)
2737 struct aarch64_displaced_step_data *dsd
2738 = (struct aarch64_displaced_step_data *) data;
2739 /* We know exactly the address the ADR{P,} instruction will compute.
2740 We can just write it to the destination register. */
2741 CORE_ADDR address = data->insn_addr + offset;
2745 /* Clear the lower 12 bits of the offset to get the 4K page. */
2746 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2750 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2753 dsd->dsc->pc_adjust = 4;
2754 emit_nop (dsd->insn_buf);
2755 dsd->insn_count = 1;
2758 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2761 aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2762 const unsigned rt, const int is64,
2763 struct aarch64_insn_data *data)
2765 struct aarch64_displaced_step_data *dsd
2766 = (struct aarch64_displaced_step_data *) data;
2767 CORE_ADDR address = data->insn_addr + offset;
2768 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2770 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2774 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2775 aarch64_register (rt, 1), zero);
2777 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2778 aarch64_register (rt, 1), zero);
2780 dsd->dsc->pc_adjust = 4;
2783 /* Implementation of aarch64_insn_visitor method "others". */
2786 aarch64_displaced_step_others (const uint32_t insn,
2787 struct aarch64_insn_data *data)
2789 struct aarch64_displaced_step_data *dsd
2790 = (struct aarch64_displaced_step_data *) data;
2792 aarch64_emit_insn (dsd->insn_buf, insn);
2793 dsd->insn_count = 1;
2795 if ((insn & 0xfffffc1f) == 0xd65f0000)
2798 dsd->dsc->pc_adjust = 0;
2801 dsd->dsc->pc_adjust = 4;
2804 static const struct aarch64_insn_visitor visitor =
2806 aarch64_displaced_step_b,
2807 aarch64_displaced_step_b_cond,
2808 aarch64_displaced_step_cb,
2809 aarch64_displaced_step_tb,
2810 aarch64_displaced_step_adr,
2811 aarch64_displaced_step_ldr_literal,
2812 aarch64_displaced_step_others,
2815 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2817 struct displaced_step_closure *
2818 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2819 CORE_ADDR from, CORE_ADDR to,
2820 struct regcache *regs)
2822 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2823 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2824 struct aarch64_displaced_step_data dsd;
2827 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2830 /* Look for a Load Exclusive instruction which begins the sequence. */
2831 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
2833 /* We can't displaced step atomic sequences. */
2837 std::unique_ptr<aarch64_displaced_step_closure> dsc
2838 (new aarch64_displaced_step_closure);
2839 dsd.base.insn_addr = from;
2842 dsd.dsc = dsc.get ();
2844 aarch64_relocate_instruction (insn, &visitor,
2845 (struct aarch64_insn_data *) &dsd);
2846 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2848 if (dsd.insn_count != 0)
2852 /* Instruction can be relocated to scratch pad. Copy
2853 relocated instruction(s) there. */
2854 for (i = 0; i < dsd.insn_count; i++)
2856 if (debug_displaced)
2858 debug_printf ("displaced: writing insn ");
2859 debug_printf ("%.8x", dsd.insn_buf[i]);
2860 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2862 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2863 (ULONGEST) dsd.insn_buf[i]);
2871 return dsc.release ();
2874 /* Implement the "displaced_step_fixup" gdbarch method. */
2877 aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
2878 struct displaced_step_closure *dsc_,
2879 CORE_ADDR from, CORE_ADDR to,
2880 struct regcache *regs)
2882 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
2888 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2891 /* Condition is true. */
2893 else if (pc - to == 4)
2895 /* Condition is false. */
2899 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2902 if (dsc->pc_adjust != 0)
2904 if (debug_displaced)
2906 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2907 paddress (gdbarch, from), dsc->pc_adjust);
2909 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2910 from + dsc->pc_adjust);
2914 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2917 aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2918 struct displaced_step_closure *closure)
2923 /* Get the correct target description for the given VQ value.
2924 If VQ is zero then it is assumed SVE is not supported.
2925 (It is not possible to set VQ to zero on an SVE system). */
2928 aarch64_read_description (uint64_t vq)
2930 if (vq > AARCH64_MAX_SVE_VQ)
2931 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
2932 AARCH64_MAX_SVE_VQ);
2934 struct target_desc *tdesc = tdesc_aarch64_list[vq];
2938 tdesc = aarch64_create_target_description (vq);
2939 tdesc_aarch64_list[vq] = tdesc;
2945 /* Return the VQ used when creating the target description TDESC. */
2948 aarch64_get_tdesc_vq (const struct target_desc *tdesc)
2950 const struct tdesc_feature *feature_sve;
2952 if (!tdesc_has_registers (tdesc))
2955 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
2957 if (feature_sve == nullptr)
2960 uint64_t vl = tdesc_register_bitsize (feature_sve,
2961 aarch64_sve_register_names[0]) / 8;
2962 return sve_vq_from_vl (vl);
2966 /* Initialize the current architecture based on INFO. If possible,
2967 re-use an architecture from ARCHES, which is a list of
2968 architectures already created during this debugging session.
2970 Called e.g. at program startup, when reading a core file, and when
2971 reading a binary file. */
2973 static struct gdbarch *
2974 aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2976 struct gdbarch_tdep *tdep;
2977 struct gdbarch *gdbarch;
2978 struct gdbarch_list *best_arch;
2979 struct tdesc_arch_data *tdesc_data = NULL;
2980 const struct target_desc *tdesc = info.target_desc;
2983 const struct tdesc_feature *feature_core;
2984 const struct tdesc_feature *feature_fpu;
2985 const struct tdesc_feature *feature_sve;
2987 int num_pseudo_regs = 0;
2989 /* Ensure we always have a target description. */
2990 if (!tdesc_has_registers (tdesc))
2991 tdesc = aarch64_read_description (0);
2994 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2995 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2996 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
2998 if (feature_core == NULL)
3001 tdesc_data = tdesc_data_alloc ();
3003 /* Validate the description provides the mandatory core R registers
3004 and allocate their numbers. */
3005 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
3006 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3007 AARCH64_X0_REGNUM + i,
3008 aarch64_r_register_names[i]);
3010 num_regs = AARCH64_X0_REGNUM + i;
3012 /* Add the V registers. */
3013 if (feature_fpu != NULL)
3015 if (feature_sve != NULL)
3016 error (_("Program contains both fpu and SVE features."));
3018 /* Validate the description provides the mandatory V registers
3019 and allocate their numbers. */
3020 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
3021 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3022 AARCH64_V0_REGNUM + i,
3023 aarch64_v_register_names[i]);
3025 num_regs = AARCH64_V0_REGNUM + i;
3028 /* Add the SVE registers. */
3029 if (feature_sve != NULL)
3031 /* Validate the description provides the mandatory SVE registers
3032 and allocate their numbers. */
3033 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3034 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3035 AARCH64_SVE_Z0_REGNUM + i,
3036 aarch64_sve_register_names[i]);
3038 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3039 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3042 if (feature_fpu != NULL || feature_sve != NULL)
3044 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3045 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3046 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3047 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3048 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3053 tdesc_data_cleanup (tdesc_data);
3057 /* AArch64 code is always little-endian. */
3058 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3060 /* If there is already a candidate, use it. */
3061 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3063 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3065 /* Found a match. */
3069 if (best_arch != NULL)
3071 if (tdesc_data != NULL)
3072 tdesc_data_cleanup (tdesc_data);
3073 return best_arch->gdbarch;
3076 tdep = XCNEW (struct gdbarch_tdep);
3077 gdbarch = gdbarch_alloc (&info, tdep);
3079 /* This should be low enough for everything. */
3080 tdep->lowest_pc = 0x20;
3081 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3082 tdep->jb_elt_size = 8;
3083 tdep->vq = aarch64_get_tdesc_vq (tdesc);
3085 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3086 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3088 /* Frame handling. */
3089 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
3090 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
3091 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
3093 /* Advance PC across function entry code. */
3094 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3096 /* The stack grows downward. */
3097 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3099 /* Breakpoint manipulation. */
3100 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3101 aarch64_breakpoint::kind_from_pc);
3102 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3103 aarch64_breakpoint::bp_from_kind);
3104 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3105 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
3107 /* Information about registers, etc. */
3108 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3109 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3110 set_gdbarch_num_regs (gdbarch, num_regs);
3112 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3113 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3114 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3115 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3116 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3117 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3118 aarch64_pseudo_register_reggroup_p);
3121 set_gdbarch_short_bit (gdbarch, 16);
3122 set_gdbarch_int_bit (gdbarch, 32);
3123 set_gdbarch_float_bit (gdbarch, 32);
3124 set_gdbarch_double_bit (gdbarch, 64);
3125 set_gdbarch_long_double_bit (gdbarch, 128);
3126 set_gdbarch_long_bit (gdbarch, 64);
3127 set_gdbarch_long_long_bit (gdbarch, 64);
3128 set_gdbarch_ptr_bit (gdbarch, 64);
3129 set_gdbarch_char_signed (gdbarch, 0);
3130 set_gdbarch_wchar_signed (gdbarch, 0);
3131 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3132 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3133 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3135 /* Internal <-> external register number maps. */
3136 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3138 /* Returning results. */
3139 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3142 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3144 /* Virtual tables. */
3145 set_gdbarch_vbit_in_delta (gdbarch, 1);
3147 /* Hook in the ABI-specific overrides, if they have been registered. */
3148 info.target_desc = tdesc;
3149 info.tdesc_data = tdesc_data;
3150 gdbarch_init_osabi (info, gdbarch);
3152 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3154 /* Add some default predicates. */
3155 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3156 dwarf2_append_unwinders (gdbarch);
3157 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3159 frame_base_set_default (gdbarch, &aarch64_normal_base);
3161 /* Now we have tuned the configuration, set a few final things,
3162 based on what the OS ABI has told us. */
3164 if (tdep->jb_pc >= 0)
3165 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3167 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3169 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3171 /* Add standard register aliases. */
3172 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3173 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3174 value_of_aarch64_user_reg,
3175 &aarch64_register_aliases[i].regnum);
3177 register_aarch64_ravenscar_ops (gdbarch);
3183 aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3185 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3190 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3191 paddress (gdbarch, tdep->lowest_pc));
3197 static void aarch64_process_record_test (void);
3202 _initialize_aarch64_tdep (void)
3204 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3207 /* Debug this file's internals. */
3208 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3209 Set AArch64 debugging."), _("\
3210 Show AArch64 debugging."), _("\
3211 When on, AArch64 specific debugging is enabled."),
3214 &setdebuglist, &showdebuglist);
3217 selftests::register_test ("aarch64-analyze-prologue",
3218 selftests::aarch64_analyze_prologue_test);
3219 selftests::register_test ("aarch64-process-record",
3220 selftests::aarch64_process_record_test);
3221 selftests::record_xml_tdesc ("aarch64.xml",
3222 aarch64_create_target_description (0));
3226 /* AArch64 process record-replay related structures, defines etc. */
3228 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3231 unsigned int reg_len = LENGTH; \
3234 REGS = XNEWVEC (uint32_t, reg_len); \
3235 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3240 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3243 unsigned int mem_len = LENGTH; \
3246 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3247 memcpy(&MEMS->len, &RECORD_BUF[0], \
3248 sizeof(struct aarch64_mem_r) * LENGTH); \
3253 /* AArch64 record/replay structures and enumerations. */
3255 struct aarch64_mem_r
3257 uint64_t len; /* Record length. */
3258 uint64_t addr; /* Memory address. */
3261 enum aarch64_record_result
3263 AARCH64_RECORD_SUCCESS,
3264 AARCH64_RECORD_UNSUPPORTED,
3265 AARCH64_RECORD_UNKNOWN
3268 typedef struct insn_decode_record_t
3270 struct gdbarch *gdbarch;
3271 struct regcache *regcache;
3272 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3273 uint32_t aarch64_insn; /* Insn to be recorded. */
3274 uint32_t mem_rec_count; /* Count of memory records. */
3275 uint32_t reg_rec_count; /* Count of register records. */
3276 uint32_t *aarch64_regs; /* Registers to be recorded. */
3277 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3278 } insn_decode_record;
3280 /* Record handler for data processing - register instructions. */
3283 aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3285 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3286 uint32_t record_buf[4];
3288 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3289 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3290 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3292 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3296 /* Logical (shifted register). */
3297 if (insn_bits24_27 == 0x0a)
3298 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3300 else if (insn_bits24_27 == 0x0b)
3301 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3303 return AARCH64_RECORD_UNKNOWN;
3305 record_buf[0] = reg_rd;
3306 aarch64_insn_r->reg_rec_count = 1;
3308 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3312 if (insn_bits24_27 == 0x0b)
3314 /* Data-processing (3 source). */
3315 record_buf[0] = reg_rd;
3316 aarch64_insn_r->reg_rec_count = 1;
3318 else if (insn_bits24_27 == 0x0a)
3320 if (insn_bits21_23 == 0x00)
3322 /* Add/subtract (with carry). */
3323 record_buf[0] = reg_rd;
3324 aarch64_insn_r->reg_rec_count = 1;
3325 if (bit (aarch64_insn_r->aarch64_insn, 29))
3327 record_buf[1] = AARCH64_CPSR_REGNUM;
3328 aarch64_insn_r->reg_rec_count = 2;
3331 else if (insn_bits21_23 == 0x02)
3333 /* Conditional compare (register) and conditional compare
3334 (immediate) instructions. */
3335 record_buf[0] = AARCH64_CPSR_REGNUM;
3336 aarch64_insn_r->reg_rec_count = 1;
3338 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3340 /* CConditional select. */
3341 /* Data-processing (2 source). */
3342 /* Data-processing (1 source). */
3343 record_buf[0] = reg_rd;
3344 aarch64_insn_r->reg_rec_count = 1;
3347 return AARCH64_RECORD_UNKNOWN;
3351 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3353 return AARCH64_RECORD_SUCCESS;
3356 /* Record handler for data processing - immediate instructions. */
3359 aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3361 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
3362 uint32_t record_buf[4];
3364 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3365 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3366 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3368 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3369 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3370 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3372 record_buf[0] = reg_rd;
3373 aarch64_insn_r->reg_rec_count = 1;
3375 else if (insn_bits24_27 == 0x01)
3377 /* Add/Subtract (immediate). */
3378 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3379 record_buf[0] = reg_rd;
3380 aarch64_insn_r->reg_rec_count = 1;
3382 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3384 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3386 /* Logical (immediate). */
3387 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3388 record_buf[0] = reg_rd;
3389 aarch64_insn_r->reg_rec_count = 1;
3391 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3394 return AARCH64_RECORD_UNKNOWN;
3396 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3398 return AARCH64_RECORD_SUCCESS;
3401 /* Record handler for branch, exception generation and system instructions. */
3404 aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3406 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3407 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3408 uint32_t record_buf[4];
3410 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3411 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3412 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3414 if (insn_bits28_31 == 0x0d)
3416 /* Exception generation instructions. */
3417 if (insn_bits24_27 == 0x04)
3419 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3420 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3421 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
3423 ULONGEST svc_number;
3425 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3427 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3431 return AARCH64_RECORD_UNSUPPORTED;
3433 /* System instructions. */
3434 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3436 uint32_t reg_rt, reg_crn;
3438 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3439 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3441 /* Record rt in case of sysl and mrs instructions. */
3442 if (bit (aarch64_insn_r->aarch64_insn, 21))
3444 record_buf[0] = reg_rt;
3445 aarch64_insn_r->reg_rec_count = 1;
3447 /* Record cpsr for hint and msr(immediate) instructions. */
3448 else if (reg_crn == 0x02 || reg_crn == 0x04)
3450 record_buf[0] = AARCH64_CPSR_REGNUM;
3451 aarch64_insn_r->reg_rec_count = 1;
3454 /* Unconditional branch (register). */
3455 else if((insn_bits24_27 & 0x0e) == 0x06)
3457 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3458 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3459 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3462 return AARCH64_RECORD_UNKNOWN;
3464 /* Unconditional branch (immediate). */
3465 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3467 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3468 if (bit (aarch64_insn_r->aarch64_insn, 31))
3469 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3472 /* Compare & branch (immediate), Test & branch (immediate) and
3473 Conditional branch (immediate). */
3474 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3476 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3478 return AARCH64_RECORD_SUCCESS;
3481 /* Record handler for advanced SIMD load and store instructions. */
3484 aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3487 uint64_t addr_offset = 0;
3488 uint32_t record_buf[24];
3489 uint64_t record_buf_mem[24];
3490 uint32_t reg_rn, reg_rt;
3491 uint32_t reg_index = 0, mem_index = 0;
3492 uint8_t opcode_bits, size_bits;
3494 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3495 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3496 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3497 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3498 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3501 debug_printf ("Process record: Advanced SIMD load/store\n");
3503 /* Load/store single structure. */
3504 if (bit (aarch64_insn_r->aarch64_insn, 24))
3506 uint8_t sindex, scale, selem, esize, replicate = 0;
3507 scale = opcode_bits >> 2;
3508 selem = ((opcode_bits & 0x02) |
3509 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3513 if (size_bits & 0x01)
3514 return AARCH64_RECORD_UNKNOWN;
3517 if ((size_bits >> 1) & 0x01)
3518 return AARCH64_RECORD_UNKNOWN;
3519 if (size_bits & 0x01)
3521 if (!((opcode_bits >> 1) & 0x01))
3524 return AARCH64_RECORD_UNKNOWN;
3528 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3535 return AARCH64_RECORD_UNKNOWN;
3541 for (sindex = 0; sindex < selem; sindex++)
3543 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3544 reg_rt = (reg_rt + 1) % 32;
3548 for (sindex = 0; sindex < selem; sindex++)
3550 if (bit (aarch64_insn_r->aarch64_insn, 22))
3551 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3554 record_buf_mem[mem_index++] = esize / 8;
3555 record_buf_mem[mem_index++] = address + addr_offset;
3557 addr_offset = addr_offset + (esize / 8);
3558 reg_rt = (reg_rt + 1) % 32;
3562 /* Load/store multiple structure. */
3565 uint8_t selem, esize, rpt, elements;
3566 uint8_t eindex, rindex;
3568 esize = 8 << size_bits;
3569 if (bit (aarch64_insn_r->aarch64_insn, 30))
3570 elements = 128 / esize;
3572 elements = 64 / esize;
3574 switch (opcode_bits)
3576 /*LD/ST4 (4 Registers). */
3581 /*LD/ST1 (4 Registers). */
3586 /*LD/ST3 (3 Registers). */
3591 /*LD/ST1 (3 Registers). */
3596 /*LD/ST1 (1 Register). */
3601 /*LD/ST2 (2 Registers). */
3606 /*LD/ST1 (2 Registers). */
3612 return AARCH64_RECORD_UNSUPPORTED;
3615 for (rindex = 0; rindex < rpt; rindex++)
3616 for (eindex = 0; eindex < elements; eindex++)
3618 uint8_t reg_tt, sindex;
3619 reg_tt = (reg_rt + rindex) % 32;
3620 for (sindex = 0; sindex < selem; sindex++)
3622 if (bit (aarch64_insn_r->aarch64_insn, 22))
3623 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3626 record_buf_mem[mem_index++] = esize / 8;
3627 record_buf_mem[mem_index++] = address + addr_offset;
3629 addr_offset = addr_offset + (esize / 8);
3630 reg_tt = (reg_tt + 1) % 32;
3635 if (bit (aarch64_insn_r->aarch64_insn, 23))
3636 record_buf[reg_index++] = reg_rn;
3638 aarch64_insn_r->reg_rec_count = reg_index;
3639 aarch64_insn_r->mem_rec_count = mem_index / 2;
3640 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3642 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3644 return AARCH64_RECORD_SUCCESS;
3647 /* Record handler for load and store instructions. */
3650 aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3652 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3653 uint8_t insn_bit23, insn_bit21;
3654 uint8_t opc, size_bits, ld_flag, vector_flag;
3655 uint32_t reg_rn, reg_rt, reg_rt2;
3656 uint64_t datasize, offset;
3657 uint32_t record_buf[8];
3658 uint64_t record_buf_mem[8];
3661 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3662 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3663 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3664 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3665 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3666 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3667 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3668 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3669 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3670 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3671 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3673 /* Load/store exclusive. */
3674 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3677 debug_printf ("Process record: load/store exclusive\n");
3681 record_buf[0] = reg_rt;
3682 aarch64_insn_r->reg_rec_count = 1;
3685 record_buf[1] = reg_rt2;
3686 aarch64_insn_r->reg_rec_count = 2;
3692 datasize = (8 << size_bits) * 2;
3694 datasize = (8 << size_bits);
3695 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3697 record_buf_mem[0] = datasize / 8;
3698 record_buf_mem[1] = address;
3699 aarch64_insn_r->mem_rec_count = 1;
3702 /* Save register rs. */
3703 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3704 aarch64_insn_r->reg_rec_count = 1;
3708 /* Load register (literal) instructions decoding. */
3709 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3712 debug_printf ("Process record: load register (literal)\n");
3714 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3716 record_buf[0] = reg_rt;
3717 aarch64_insn_r->reg_rec_count = 1;
3719 /* All types of load/store pair instructions decoding. */
3720 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3723 debug_printf ("Process record: load/store pair\n");
3729 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3730 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3734 record_buf[0] = reg_rt;
3735 record_buf[1] = reg_rt2;
3737 aarch64_insn_r->reg_rec_count = 2;
3742 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3744 size_bits = size_bits >> 1;
3745 datasize = 8 << (2 + size_bits);
3746 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3747 offset = offset << (2 + size_bits);
3748 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3750 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3752 if (imm7_off & 0x40)
3753 address = address - offset;
3755 address = address + offset;
3758 record_buf_mem[0] = datasize / 8;
3759 record_buf_mem[1] = address;
3760 record_buf_mem[2] = datasize / 8;
3761 record_buf_mem[3] = address + (datasize / 8);
3762 aarch64_insn_r->mem_rec_count = 2;
3764 if (bit (aarch64_insn_r->aarch64_insn, 23))
3765 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3767 /* Load/store register (unsigned immediate) instructions. */
3768 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3770 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3780 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3782 /* PRFM (immediate) */
3783 return AARCH64_RECORD_SUCCESS;
3785 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3787 /* LDRSW (immediate) */
3801 debug_printf ("Process record: load/store (unsigned immediate):"
3802 " size %x V %d opc %x\n", size_bits, vector_flag,
3808 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3809 datasize = 8 << size_bits;
3810 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3812 offset = offset << size_bits;
3813 address = address + offset;
3815 record_buf_mem[0] = datasize >> 3;
3816 record_buf_mem[1] = address;
3817 aarch64_insn_r->mem_rec_count = 1;
3822 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3824 record_buf[0] = reg_rt;
3825 aarch64_insn_r->reg_rec_count = 1;
3828 /* Load/store register (register offset) instructions. */
3829 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3830 && insn_bits10_11 == 0x02 && insn_bit21)
3833 debug_printf ("Process record: load/store (register offset)\n");
3834 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3841 if (size_bits != 0x03)
3844 return AARCH64_RECORD_UNKNOWN;
3848 ULONGEST reg_rm_val;
3850 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3851 bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
3852 if (bit (aarch64_insn_r->aarch64_insn, 12))
3853 offset = reg_rm_val << size_bits;
3855 offset = reg_rm_val;
3856 datasize = 8 << size_bits;
3857 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3859 address = address + offset;
3860 record_buf_mem[0] = datasize >> 3;
3861 record_buf_mem[1] = address;
3862 aarch64_insn_r->mem_rec_count = 1;
3867 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3869 record_buf[0] = reg_rt;
3870 aarch64_insn_r->reg_rec_count = 1;
3873 /* Load/store register (immediate and unprivileged) instructions. */
3874 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3879 debug_printf ("Process record: load/store "
3880 "(immediate and unprivileged)\n");
3882 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3889 if (size_bits != 0x03)
3892 return AARCH64_RECORD_UNKNOWN;
3897 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3898 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3899 datasize = 8 << size_bits;
3900 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3902 if (insn_bits10_11 != 0x01)
3904 if (imm9_off & 0x0100)
3905 address = address - offset;
3907 address = address + offset;
3909 record_buf_mem[0] = datasize >> 3;
3910 record_buf_mem[1] = address;
3911 aarch64_insn_r->mem_rec_count = 1;
3916 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3918 record_buf[0] = reg_rt;
3919 aarch64_insn_r->reg_rec_count = 1;
3921 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3922 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3924 /* Advanced SIMD load/store instructions. */
3926 return aarch64_record_asimd_load_store (aarch64_insn_r);
3928 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3930 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3932 return AARCH64_RECORD_SUCCESS;
3935 /* Record handler for data processing SIMD and floating point instructions. */
3938 aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3940 uint8_t insn_bit21, opcode, rmode, reg_rd;
3941 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3942 uint8_t insn_bits11_14;
3943 uint32_t record_buf[2];
3945 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3946 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3947 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3948 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3949 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3950 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3951 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3952 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3953 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3956 debug_printf ("Process record: data processing SIMD/FP: ");
3958 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3960 /* Floating point - fixed point conversion instructions. */
3964 debug_printf ("FP - fixed point conversion");
3966 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3967 record_buf[0] = reg_rd;
3969 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3971 /* Floating point - conditional compare instructions. */
3972 else if (insn_bits10_11 == 0x01)
3975 debug_printf ("FP - conditional compare");
3977 record_buf[0] = AARCH64_CPSR_REGNUM;
3979 /* Floating point - data processing (2-source) and
3980 conditional select instructions. */
3981 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3984 debug_printf ("FP - DP (2-source)");
3986 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3988 else if (insn_bits10_11 == 0x00)
3990 /* Floating point - immediate instructions. */
3991 if ((insn_bits12_15 & 0x01) == 0x01
3992 || (insn_bits12_15 & 0x07) == 0x04)
3995 debug_printf ("FP - immediate");
3996 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3998 /* Floating point - compare instructions. */
3999 else if ((insn_bits12_15 & 0x03) == 0x02)
4002 debug_printf ("FP - immediate");
4003 record_buf[0] = AARCH64_CPSR_REGNUM;
4005 /* Floating point - integer conversions instructions. */
4006 else if (insn_bits12_15 == 0x00)
4008 /* Convert float to integer instruction. */
4009 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4012 debug_printf ("float to int conversion");
4014 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4016 /* Convert integer to float instruction. */
4017 else if ((opcode >> 1) == 0x01 && !rmode)
4020 debug_printf ("int to float conversion");
4022 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4024 /* Move float to integer instruction. */
4025 else if ((opcode >> 1) == 0x03)
4028 debug_printf ("move float to int");
4030 if (!(opcode & 0x01))
4031 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4033 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4036 return AARCH64_RECORD_UNKNOWN;
4039 return AARCH64_RECORD_UNKNOWN;
4042 return AARCH64_RECORD_UNKNOWN;
4044 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4047 debug_printf ("SIMD copy");
4049 /* Advanced SIMD copy instructions. */
4050 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4051 && !bit (aarch64_insn_r->aarch64_insn, 15)
4052 && bit (aarch64_insn_r->aarch64_insn, 10))
4054 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4055 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4057 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4060 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4062 /* All remaining floating point or advanced SIMD instructions. */
4066 debug_printf ("all remain");
4068 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4072 debug_printf ("\n");
4074 aarch64_insn_r->reg_rec_count++;
4075 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4076 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4078 return AARCH64_RECORD_SUCCESS;
4081 /* Decodes insns type and invokes its record handler. */
4084 aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4086 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4088 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4089 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4090 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4091 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4093 /* Data processing - immediate instructions. */
4094 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4095 return aarch64_record_data_proc_imm (aarch64_insn_r);
4097 /* Branch, exception generation and system instructions. */
4098 if (ins_bit26 && !ins_bit27 && ins_bit28)
4099 return aarch64_record_branch_except_sys (aarch64_insn_r);
4101 /* Load and store instructions. */
4102 if (!ins_bit25 && ins_bit27)
4103 return aarch64_record_load_store (aarch64_insn_r);
4105 /* Data processing - register instructions. */
4106 if (ins_bit25 && !ins_bit26 && ins_bit27)
4107 return aarch64_record_data_proc_reg (aarch64_insn_r);
4109 /* Data processing - SIMD and floating point instructions. */
4110 if (ins_bit25 && ins_bit26 && ins_bit27)
4111 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4113 return AARCH64_RECORD_UNSUPPORTED;
4116 /* Cleans up local record registers and memory allocations. */
4119 deallocate_reg_mem (insn_decode_record *record)
4121 xfree (record->aarch64_regs);
4122 xfree (record->aarch64_mems);
4126 namespace selftests {
4129 aarch64_process_record_test (void)
4131 struct gdbarch_info info;
4134 gdbarch_info_init (&info);
4135 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4137 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4138 SELF_CHECK (gdbarch != NULL);
4140 insn_decode_record aarch64_record;
4142 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4143 aarch64_record.regcache = NULL;
4144 aarch64_record.this_addr = 0;
4145 aarch64_record.gdbarch = gdbarch;
4147 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4148 aarch64_record.aarch64_insn = 0xf9800020;
4149 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4150 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4151 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4152 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4154 deallocate_reg_mem (&aarch64_record);
4157 } // namespace selftests
4158 #endif /* GDB_SELF_TEST */
4160 /* Parse the current instruction and record the values of the registers and
4161 memory that will be changed in current instruction to record_arch_list
4162 return -1 if something is wrong. */
4165 aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4166 CORE_ADDR insn_addr)
4168 uint32_t rec_no = 0;
4169 uint8_t insn_size = 4;
4171 gdb_byte buf[insn_size];
4172 insn_decode_record aarch64_record;
4174 memset (&buf[0], 0, insn_size);
4175 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4176 target_read_memory (insn_addr, &buf[0], insn_size);
4177 aarch64_record.aarch64_insn
4178 = (uint32_t) extract_unsigned_integer (&buf[0],
4180 gdbarch_byte_order (gdbarch));
4181 aarch64_record.regcache = regcache;
4182 aarch64_record.this_addr = insn_addr;
4183 aarch64_record.gdbarch = gdbarch;
4185 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4186 if (ret == AARCH64_RECORD_UNSUPPORTED)
4188 printf_unfiltered (_("Process record does not support instruction "
4189 "0x%0x at address %s.\n"),
4190 aarch64_record.aarch64_insn,
4191 paddress (gdbarch, insn_addr));
4197 /* Record registers. */
4198 record_full_arch_list_add_reg (aarch64_record.regcache,
4200 /* Always record register CPSR. */
4201 record_full_arch_list_add_reg (aarch64_record.regcache,
4202 AARCH64_CPSR_REGNUM);
4203 if (aarch64_record.aarch64_regs)
4204 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4205 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4206 aarch64_record.aarch64_regs[rec_no]))
4209 /* Record memories. */
4210 if (aarch64_record.aarch64_mems)
4211 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4212 if (record_full_arch_list_add_mem
4213 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4214 aarch64_record.aarch64_mems[rec_no].len))
4217 if (record_full_arch_list_add_end ())
4221 deallocate_reg_mem (&aarch64_record);