1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
38 #include "dwarf2-frame.h"
40 #include "prologue-value.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
47 #include "common/selftest.h"
49 #include "aarch64-tdep.h"
50 #include "aarch64-ravenscar-thread.h"
53 #include "elf/aarch64.h"
55 #include "common/vec.h"
58 #include "record-full.h"
59 #include "arch/aarch64-insn.h"
61 #include "opcode/aarch64.h"
64 #define submask(x) ((1L << ((x) + 1)) - 1)
65 #define bit(obj,st) (((obj) >> (st)) & 1)
66 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
68 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
70 #define HA_MAX_NUM_FLDS 4
72 /* All possible aarch64 target descriptors. */
73 struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
75 /* The standard register names, and all the valid aliases for them. */
78 const char *const name;
80 } aarch64_register_aliases[] =
82 /* 64-bit register names. */
83 {"fp", AARCH64_FP_REGNUM},
84 {"lr", AARCH64_LR_REGNUM},
85 {"sp", AARCH64_SP_REGNUM},
87 /* 32-bit register names. */
88 {"w0", AARCH64_X0_REGNUM + 0},
89 {"w1", AARCH64_X0_REGNUM + 1},
90 {"w2", AARCH64_X0_REGNUM + 2},
91 {"w3", AARCH64_X0_REGNUM + 3},
92 {"w4", AARCH64_X0_REGNUM + 4},
93 {"w5", AARCH64_X0_REGNUM + 5},
94 {"w6", AARCH64_X0_REGNUM + 6},
95 {"w7", AARCH64_X0_REGNUM + 7},
96 {"w8", AARCH64_X0_REGNUM + 8},
97 {"w9", AARCH64_X0_REGNUM + 9},
98 {"w10", AARCH64_X0_REGNUM + 10},
99 {"w11", AARCH64_X0_REGNUM + 11},
100 {"w12", AARCH64_X0_REGNUM + 12},
101 {"w13", AARCH64_X0_REGNUM + 13},
102 {"w14", AARCH64_X0_REGNUM + 14},
103 {"w15", AARCH64_X0_REGNUM + 15},
104 {"w16", AARCH64_X0_REGNUM + 16},
105 {"w17", AARCH64_X0_REGNUM + 17},
106 {"w18", AARCH64_X0_REGNUM + 18},
107 {"w19", AARCH64_X0_REGNUM + 19},
108 {"w20", AARCH64_X0_REGNUM + 20},
109 {"w21", AARCH64_X0_REGNUM + 21},
110 {"w22", AARCH64_X0_REGNUM + 22},
111 {"w23", AARCH64_X0_REGNUM + 23},
112 {"w24", AARCH64_X0_REGNUM + 24},
113 {"w25", AARCH64_X0_REGNUM + 25},
114 {"w26", AARCH64_X0_REGNUM + 26},
115 {"w27", AARCH64_X0_REGNUM + 27},
116 {"w28", AARCH64_X0_REGNUM + 28},
117 {"w29", AARCH64_X0_REGNUM + 29},
118 {"w30", AARCH64_X0_REGNUM + 30},
121 {"ip0", AARCH64_X0_REGNUM + 16},
122 {"ip1", AARCH64_X0_REGNUM + 17}
125 /* The required core 'R' registers. */
126 static const char *const aarch64_r_register_names[] =
128 /* These registers must appear in consecutive RAW register number
129 order and they must begin with AARCH64_X0_REGNUM! */
130 "x0", "x1", "x2", "x3",
131 "x4", "x5", "x6", "x7",
132 "x8", "x9", "x10", "x11",
133 "x12", "x13", "x14", "x15",
134 "x16", "x17", "x18", "x19",
135 "x20", "x21", "x22", "x23",
136 "x24", "x25", "x26", "x27",
137 "x28", "x29", "x30", "sp",
141 /* The FP/SIMD 'V' registers. */
142 static const char *const aarch64_v_register_names[] =
144 /* These registers must appear in consecutive RAW register number
145 order and they must begin with AARCH64_V0_REGNUM! */
146 "v0", "v1", "v2", "v3",
147 "v4", "v5", "v6", "v7",
148 "v8", "v9", "v10", "v11",
149 "v12", "v13", "v14", "v15",
150 "v16", "v17", "v18", "v19",
151 "v20", "v21", "v22", "v23",
152 "v24", "v25", "v26", "v27",
153 "v28", "v29", "v30", "v31",
158 /* The SVE 'Z' and 'P' registers. */
159 static const char *const aarch64_sve_register_names[] =
161 /* These registers must appear in consecutive RAW register number
162 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
163 "z0", "z1", "z2", "z3",
164 "z4", "z5", "z6", "z7",
165 "z8", "z9", "z10", "z11",
166 "z12", "z13", "z14", "z15",
167 "z16", "z17", "z18", "z19",
168 "z20", "z21", "z22", "z23",
169 "z24", "z25", "z26", "z27",
170 "z28", "z29", "z30", "z31",
172 "p0", "p1", "p2", "p3",
173 "p4", "p5", "p6", "p7",
174 "p8", "p9", "p10", "p11",
175 "p12", "p13", "p14", "p15",
179 static const char *const aarch64_pauth_register_names[] =
181 /* Authentication mask for data pointer. */
183 /* Authentication mask for code pointer. */
187 /* AArch64 prologue cache structure. */
188 struct aarch64_prologue_cache
190 /* The program counter at the start of the function. It is used to
191 identify this frame as a prologue frame. */
194 /* The program counter at the time this frame was created; i.e. where
195 this function was called from. It is used to identify this frame as a
199 /* The stack pointer at the time this frame was created; i.e. the
200 caller's stack pointer when this function was called. It is used
201 to identify this frame. */
204 /* Is the target available to read from? */
207 /* The frame base for this frame is just prev_sp - frame size.
208 FRAMESIZE is the distance from the frame pointer to the
209 initial stack pointer. */
212 /* The register used to hold the frame pointer for this frame. */
215 /* Saved register offsets. */
216 struct trad_frame_saved_reg *saved_regs;
220 show_aarch64_debug (struct ui_file *file, int from_tty,
221 struct cmd_list_element *c, const char *value)
223 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
228 /* Abstract instruction reader. */
230 class abstract_instruction_reader
233 /* Read in one instruction. */
234 virtual ULONGEST read (CORE_ADDR memaddr, int len,
235 enum bfd_endian byte_order) = 0;
238 /* Instruction reader from real target. */
240 class instruction_reader : public abstract_instruction_reader
243 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
246 return read_code_unsigned_integer (memaddr, len, byte_order);
252 /* If address signing is enabled, mask off the signature bits from ADDR, using
253 the register values in THIS_FRAME. */
256 aarch64_frame_unmask_address (struct gdbarch_tdep *tdep,
257 struct frame_info *this_frame,
260 if (tdep->has_pauth ()
261 && frame_unwind_register_unsigned (this_frame,
262 tdep->pauth_ra_state_regnum))
264 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
265 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
266 addr = addr & ~cmask;
272 /* Analyze a prologue, looking for a recognizable stack frame
273 and frame pointer. Scan until we encounter a store that could
274 clobber the stack frame unexpectedly, or an unknown instruction. */
277 aarch64_analyze_prologue (struct gdbarch *gdbarch,
278 CORE_ADDR start, CORE_ADDR limit,
279 struct aarch64_prologue_cache *cache,
280 abstract_instruction_reader& reader)
282 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
284 /* Track X registers and D registers in prologue. */
285 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
287 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
288 regs[i] = pv_register (i, 0);
289 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
291 for (; start < limit; start += 4)
296 insn = reader.read (start, 4, byte_order_for_code);
298 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
301 if (inst.opcode->iclass == addsub_imm
302 && (inst.opcode->op == OP_ADD
303 || strcmp ("sub", inst.opcode->name) == 0))
305 unsigned rd = inst.operands[0].reg.regno;
306 unsigned rn = inst.operands[1].reg.regno;
308 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
309 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
310 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
311 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
313 if (inst.opcode->op == OP_ADD)
315 regs[rd] = pv_add_constant (regs[rn],
316 inst.operands[2].imm.value);
320 regs[rd] = pv_add_constant (regs[rn],
321 -inst.operands[2].imm.value);
324 else if (inst.opcode->iclass == pcreladdr
325 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
327 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
328 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
330 regs[inst.operands[0].reg.regno] = pv_unknown ();
332 else if (inst.opcode->iclass == branch_imm)
334 /* Stop analysis on branch. */
337 else if (inst.opcode->iclass == condbranch)
339 /* Stop analysis on branch. */
342 else if (inst.opcode->iclass == branch_reg)
344 /* Stop analysis on branch. */
347 else if (inst.opcode->iclass == compbranch)
349 /* Stop analysis on branch. */
352 else if (inst.opcode->op == OP_MOVZ)
354 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
355 regs[inst.operands[0].reg.regno] = pv_unknown ();
357 else if (inst.opcode->iclass == log_shift
358 && strcmp (inst.opcode->name, "orr") == 0)
360 unsigned rd = inst.operands[0].reg.regno;
361 unsigned rn = inst.operands[1].reg.regno;
362 unsigned rm = inst.operands[2].reg.regno;
364 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
365 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
366 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
368 if (inst.operands[2].shifter.amount == 0
369 && rn == AARCH64_SP_REGNUM)
375 debug_printf ("aarch64: prologue analysis gave up "
376 "addr=%s opcode=0x%x (orr x register)\n",
377 core_addr_to_string_nz (start), insn);
382 else if (inst.opcode->op == OP_STUR)
384 unsigned rt = inst.operands[0].reg.regno;
385 unsigned rn = inst.operands[1].addr.base_regno;
387 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
389 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
390 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
391 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
392 gdb_assert (!inst.operands[1].addr.offset.is_reg);
394 stack.store (pv_add_constant (regs[rn],
395 inst.operands[1].addr.offset.imm),
396 is64 ? 8 : 4, regs[rt]);
398 else if ((inst.opcode->iclass == ldstpair_off
399 || (inst.opcode->iclass == ldstpair_indexed
400 && inst.operands[2].addr.preind))
401 && strcmp ("stp", inst.opcode->name) == 0)
403 /* STP with addressing mode Pre-indexed and Base register. */
406 unsigned rn = inst.operands[2].addr.base_regno;
407 int32_t imm = inst.operands[2].addr.offset.imm;
409 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
410 || inst.operands[0].type == AARCH64_OPND_Ft);
411 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
412 || inst.operands[1].type == AARCH64_OPND_Ft2);
413 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
414 gdb_assert (!inst.operands[2].addr.offset.is_reg);
416 /* If recording this store would invalidate the store area
417 (perhaps because rn is not known) then we should abandon
418 further prologue analysis. */
419 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
422 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
425 rt1 = inst.operands[0].reg.regno;
426 rt2 = inst.operands[1].reg.regno;
427 if (inst.operands[0].type == AARCH64_OPND_Ft)
429 /* Only bottom 64-bit of each V register (D register) need
431 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
432 rt1 += AARCH64_X_REGISTER_COUNT;
433 rt2 += AARCH64_X_REGISTER_COUNT;
436 stack.store (pv_add_constant (regs[rn], imm), 8,
438 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
441 if (inst.operands[2].addr.writeback)
442 regs[rn] = pv_add_constant (regs[rn], imm);
445 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
446 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
447 && (inst.opcode->op == OP_STR_POS
448 || inst.opcode->op == OP_STRF_POS)))
449 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
450 && strcmp ("str", inst.opcode->name) == 0)
452 /* STR (immediate) */
453 unsigned int rt = inst.operands[0].reg.regno;
454 int32_t imm = inst.operands[1].addr.offset.imm;
455 unsigned int rn = inst.operands[1].addr.base_regno;
457 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
458 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
459 || inst.operands[0].type == AARCH64_OPND_Ft);
461 if (inst.operands[0].type == AARCH64_OPND_Ft)
463 /* Only bottom 64-bit of each V register (D register) need
465 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
466 rt += AARCH64_X_REGISTER_COUNT;
469 stack.store (pv_add_constant (regs[rn], imm),
470 is64 ? 8 : 4, regs[rt]);
471 if (inst.operands[1].addr.writeback)
472 regs[rn] = pv_add_constant (regs[rn], imm);
474 else if (inst.opcode->iclass == testbranch)
476 /* Stop analysis on branch. */
479 else if (inst.opcode->iclass == ic_system)
481 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
482 int ra_state_val = 0;
484 if (insn == 0xd503233f /* paciasp. */
485 || insn == 0xd503237f /* pacibsp. */)
487 /* Return addresses are mangled. */
490 else if (insn == 0xd50323bf /* autiasp. */
491 || insn == 0xd50323ff /* autibsp. */)
493 /* Return addresses are not mangled. */
499 debug_printf ("aarch64: prologue analysis gave up addr=%s"
500 " opcode=0x%x (iclass)\n",
501 core_addr_to_string_nz (start), insn);
505 if (tdep->has_pauth () && cache != nullptr)
506 trad_frame_set_value (cache->saved_regs,
507 tdep->pauth_ra_state_regnum,
514 debug_printf ("aarch64: prologue analysis gave up addr=%s"
516 core_addr_to_string_nz (start), insn);
525 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
527 /* Frame pointer is fp. Frame size is constant. */
528 cache->framereg = AARCH64_FP_REGNUM;
529 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
531 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
533 /* Try the stack pointer. */
534 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
535 cache->framereg = AARCH64_SP_REGNUM;
539 /* We're just out of luck. We don't know where the frame is. */
540 cache->framereg = -1;
541 cache->framesize = 0;
544 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
548 if (stack.find_reg (gdbarch, i, &offset))
549 cache->saved_regs[i].addr = offset;
552 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
554 int regnum = gdbarch_num_regs (gdbarch);
557 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
559 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
566 aarch64_analyze_prologue (struct gdbarch *gdbarch,
567 CORE_ADDR start, CORE_ADDR limit,
568 struct aarch64_prologue_cache *cache)
570 instruction_reader reader;
572 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
578 namespace selftests {
580 /* Instruction reader from manually cooked instruction sequences. */
582 class instruction_reader_test : public abstract_instruction_reader
585 template<size_t SIZE>
586 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
587 : m_insns (insns), m_insns_size (SIZE)
590 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
593 SELF_CHECK (len == 4);
594 SELF_CHECK (memaddr % 4 == 0);
595 SELF_CHECK (memaddr / 4 < m_insns_size);
597 return m_insns[memaddr / 4];
601 const uint32_t *m_insns;
606 aarch64_analyze_prologue_test (void)
608 struct gdbarch_info info;
610 gdbarch_info_init (&info);
611 info.bfd_arch_info = bfd_scan_arch ("aarch64");
613 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
614 SELF_CHECK (gdbarch != NULL);
616 struct aarch64_prologue_cache cache;
617 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
619 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
621 /* Test the simple prologue in which frame pointer is used. */
623 static const uint32_t insns[] = {
624 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
625 0x910003fd, /* mov x29, sp */
626 0x97ffffe6, /* bl 0x400580 */
628 instruction_reader_test reader (insns);
630 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
631 SELF_CHECK (end == 4 * 2);
633 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
634 SELF_CHECK (cache.framesize == 272);
636 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
638 if (i == AARCH64_FP_REGNUM)
639 SELF_CHECK (cache.saved_regs[i].addr == -272);
640 else if (i == AARCH64_LR_REGNUM)
641 SELF_CHECK (cache.saved_regs[i].addr == -264);
643 SELF_CHECK (cache.saved_regs[i].addr == -1);
646 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
648 int regnum = gdbarch_num_regs (gdbarch);
650 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
655 /* Test a prologue in which STR is used and frame pointer is not
658 static const uint32_t insns[] = {
659 0xf81d0ff3, /* str x19, [sp, #-48]! */
660 0xb9002fe0, /* str w0, [sp, #44] */
661 0xf90013e1, /* str x1, [sp, #32]*/
662 0xfd000fe0, /* str d0, [sp, #24] */
663 0xaa0203f3, /* mov x19, x2 */
664 0xf94013e0, /* ldr x0, [sp, #32] */
666 instruction_reader_test reader (insns);
668 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
669 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
671 SELF_CHECK (end == 4 * 5);
673 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
674 SELF_CHECK (cache.framesize == 48);
676 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
679 SELF_CHECK (cache.saved_regs[i].addr == -16);
681 SELF_CHECK (cache.saved_regs[i].addr == -48);
683 SELF_CHECK (cache.saved_regs[i].addr == -1);
686 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
688 int regnum = gdbarch_num_regs (gdbarch);
691 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
694 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
699 /* Test a prologue in which there is a return address signing instruction. */
700 if (tdep->has_pauth ())
702 static const uint32_t insns[] = {
703 0xd503233f, /* paciasp */
704 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
705 0x910003fd, /* mov x29, sp */
706 0xf801c3f3, /* str x19, [sp, #28] */
707 0xb9401fa0, /* ldr x19, [x29, #28] */
709 instruction_reader_test reader (insns);
711 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
712 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
715 SELF_CHECK (end == 4 * 4);
716 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
717 SELF_CHECK (cache.framesize == 48);
719 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
722 SELF_CHECK (cache.saved_regs[i].addr == -20);
723 else if (i == AARCH64_FP_REGNUM)
724 SELF_CHECK (cache.saved_regs[i].addr == -48);
725 else if (i == AARCH64_LR_REGNUM)
726 SELF_CHECK (cache.saved_regs[i].addr == -40);
728 SELF_CHECK (cache.saved_regs[i].addr == -1);
731 if (tdep->has_pauth ())
733 SELF_CHECK (trad_frame_value_p (cache.saved_regs,
734 tdep->pauth_ra_state_regnum));
735 SELF_CHECK (cache.saved_regs[tdep->pauth_ra_state_regnum].addr == 1);
739 } // namespace selftests
740 #endif /* GDB_SELF_TEST */
742 /* Implement the "skip_prologue" gdbarch method. */
745 aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
747 CORE_ADDR func_addr, limit_pc;
749 /* See if we can determine the end of the prologue via the symbol
750 table. If so, then return either PC, or the PC after the
751 prologue, whichever is greater. */
752 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
754 CORE_ADDR post_prologue_pc
755 = skip_prologue_using_sal (gdbarch, func_addr);
757 if (post_prologue_pc != 0)
758 return std::max (pc, post_prologue_pc);
761 /* Can't determine prologue from the symbol table, need to examine
764 /* Find an upper limit on the function prologue using the debug
765 information. If the debug information could not be used to
766 provide that bound, then use an arbitrary large number as the
768 limit_pc = skip_prologue_using_sal (gdbarch, pc);
770 limit_pc = pc + 128; /* Magic. */
772 /* Try disassembling prologue. */
773 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
776 /* Scan the function prologue for THIS_FRAME and populate the prologue
780 aarch64_scan_prologue (struct frame_info *this_frame,
781 struct aarch64_prologue_cache *cache)
783 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
784 CORE_ADDR prologue_start;
785 CORE_ADDR prologue_end;
786 CORE_ADDR prev_pc = get_frame_pc (this_frame);
787 struct gdbarch *gdbarch = get_frame_arch (this_frame);
789 cache->prev_pc = prev_pc;
791 /* Assume we do not find a frame. */
792 cache->framereg = -1;
793 cache->framesize = 0;
795 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
798 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
802 /* No line info so use the current PC. */
803 prologue_end = prev_pc;
805 else if (sal.end < prologue_end)
807 /* The next line begins after the function end. */
808 prologue_end = sal.end;
811 prologue_end = std::min (prologue_end, prev_pc);
812 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
818 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
822 cache->framereg = AARCH64_FP_REGNUM;
823 cache->framesize = 16;
824 cache->saved_regs[29].addr = 0;
825 cache->saved_regs[30].addr = 8;
829 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
830 function may throw an exception if the inferior's registers or memory is
834 aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
835 struct aarch64_prologue_cache *cache)
837 CORE_ADDR unwound_fp;
840 aarch64_scan_prologue (this_frame, cache);
842 if (cache->framereg == -1)
845 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
849 cache->prev_sp = unwound_fp + cache->framesize;
851 /* Calculate actual addresses of saved registers using offsets
852 determined by aarch64_analyze_prologue. */
853 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
854 if (trad_frame_addr_p (cache->saved_regs, reg))
855 cache->saved_regs[reg].addr += cache->prev_sp;
857 cache->func = get_frame_func (this_frame);
859 cache->available_p = 1;
862 /* Allocate and fill in *THIS_CACHE with information about the prologue of
863 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
864 Return a pointer to the current aarch64_prologue_cache in
867 static struct aarch64_prologue_cache *
868 aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
870 struct aarch64_prologue_cache *cache;
872 if (*this_cache != NULL)
873 return (struct aarch64_prologue_cache *) *this_cache;
875 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
876 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
881 aarch64_make_prologue_cache_1 (this_frame, cache);
883 catch (const gdb_exception_error &ex)
885 if (ex.error != NOT_AVAILABLE_ERROR)
892 /* Implement the "stop_reason" frame_unwind method. */
894 static enum unwind_stop_reason
895 aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
898 struct aarch64_prologue_cache *cache
899 = aarch64_make_prologue_cache (this_frame, this_cache);
901 if (!cache->available_p)
902 return UNWIND_UNAVAILABLE;
904 /* Halt the backtrace at "_start". */
905 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
906 return UNWIND_OUTERMOST;
908 /* We've hit a wall, stop. */
909 if (cache->prev_sp == 0)
910 return UNWIND_OUTERMOST;
912 return UNWIND_NO_REASON;
915 /* Our frame ID for a normal frame is the current function's starting
916 PC and the caller's SP when we were called. */
919 aarch64_prologue_this_id (struct frame_info *this_frame,
920 void **this_cache, struct frame_id *this_id)
922 struct aarch64_prologue_cache *cache
923 = aarch64_make_prologue_cache (this_frame, this_cache);
925 if (!cache->available_p)
926 *this_id = frame_id_build_unavailable_stack (cache->func);
928 *this_id = frame_id_build (cache->prev_sp, cache->func);
931 /* Implement the "prev_register" frame_unwind method. */
933 static struct value *
934 aarch64_prologue_prev_register (struct frame_info *this_frame,
935 void **this_cache, int prev_regnum)
937 struct aarch64_prologue_cache *cache
938 = aarch64_make_prologue_cache (this_frame, this_cache);
940 /* If we are asked to unwind the PC, then we need to return the LR
941 instead. The prologue may save PC, but it will point into this
942 frame's prologue, not the next frame's resume location. */
943 if (prev_regnum == AARCH64_PC_REGNUM)
946 struct gdbarch *gdbarch = get_frame_arch (this_frame);
947 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
949 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
951 if (tdep->has_pauth ()
952 && trad_frame_value_p (cache->saved_regs,
953 tdep->pauth_ra_state_regnum))
954 lr = aarch64_frame_unmask_address (tdep, this_frame, lr);
956 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
959 /* SP is generally not saved to the stack, but this frame is
960 identified by the next frame's stack pointer at the time of the
961 call. The value was already reconstructed into PREV_SP. */
974 if (prev_regnum == AARCH64_SP_REGNUM)
975 return frame_unwind_got_constant (this_frame, prev_regnum,
978 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
982 /* AArch64 prologue unwinder. */
983 struct frame_unwind aarch64_prologue_unwind =
986 aarch64_prologue_frame_unwind_stop_reason,
987 aarch64_prologue_this_id,
988 aarch64_prologue_prev_register,
990 default_frame_sniffer
993 /* Allocate and fill in *THIS_CACHE with information about the prologue of
994 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
995 Return a pointer to the current aarch64_prologue_cache in
998 static struct aarch64_prologue_cache *
999 aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
1001 struct aarch64_prologue_cache *cache;
1003 if (*this_cache != NULL)
1004 return (struct aarch64_prologue_cache *) *this_cache;
1006 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1007 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1008 *this_cache = cache;
1012 cache->prev_sp = get_frame_register_unsigned (this_frame,
1014 cache->prev_pc = get_frame_pc (this_frame);
1015 cache->available_p = 1;
1017 catch (const gdb_exception_error &ex)
1019 if (ex.error != NOT_AVAILABLE_ERROR)
1026 /* Implement the "stop_reason" frame_unwind method. */
1028 static enum unwind_stop_reason
1029 aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1032 struct aarch64_prologue_cache *cache
1033 = aarch64_make_stub_cache (this_frame, this_cache);
1035 if (!cache->available_p)
1036 return UNWIND_UNAVAILABLE;
1038 return UNWIND_NO_REASON;
1041 /* Our frame ID for a stub frame is the current SP and LR. */
1044 aarch64_stub_this_id (struct frame_info *this_frame,
1045 void **this_cache, struct frame_id *this_id)
1047 struct aarch64_prologue_cache *cache
1048 = aarch64_make_stub_cache (this_frame, this_cache);
1050 if (cache->available_p)
1051 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1053 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
1056 /* Implement the "sniffer" frame_unwind method. */
1059 aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1060 struct frame_info *this_frame,
1061 void **this_prologue_cache)
1063 CORE_ADDR addr_in_block;
1066 addr_in_block = get_frame_address_in_block (this_frame);
1067 if (in_plt_section (addr_in_block)
1068 /* We also use the stub winder if the target memory is unreadable
1069 to avoid having the prologue unwinder trying to read it. */
1070 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1076 /* AArch64 stub unwinder. */
1077 struct frame_unwind aarch64_stub_unwind =
1080 aarch64_stub_frame_unwind_stop_reason,
1081 aarch64_stub_this_id,
1082 aarch64_prologue_prev_register,
1084 aarch64_stub_unwind_sniffer
1087 /* Return the frame base address of *THIS_FRAME. */
1090 aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1092 struct aarch64_prologue_cache *cache
1093 = aarch64_make_prologue_cache (this_frame, this_cache);
1095 return cache->prev_sp - cache->framesize;
1098 /* AArch64 default frame base information. */
1099 struct frame_base aarch64_normal_base =
1101 &aarch64_prologue_unwind,
1102 aarch64_normal_frame_base,
1103 aarch64_normal_frame_base,
1104 aarch64_normal_frame_base
1107 /* Return the value of the REGNUM register in the previous frame of
1110 static struct value *
1111 aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1112 void **this_cache, int regnum)
1114 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1119 case AARCH64_PC_REGNUM:
1120 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1121 lr = aarch64_frame_unmask_address (tdep, this_frame, lr);
1122 return frame_unwind_got_constant (this_frame, regnum, lr);
1125 internal_error (__FILE__, __LINE__,
1126 _("Unexpected register %d"), regnum);
1130 static const unsigned char op_lit0 = DW_OP_lit0;
1131 static const unsigned char op_lit1 = DW_OP_lit1;
1133 /* Implement the "init_reg" dwarf2_frame_ops method. */
1136 aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1137 struct dwarf2_frame_state_reg *reg,
1138 struct frame_info *this_frame)
1140 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1144 case AARCH64_PC_REGNUM:
1145 reg->how = DWARF2_FRAME_REG_FN;
1146 reg->loc.fn = aarch64_dwarf2_prev_register;
1149 case AARCH64_SP_REGNUM:
1150 reg->how = DWARF2_FRAME_REG_CFA;
1154 /* Init pauth registers. */
1155 if (tdep->has_pauth ())
1157 if (regnum == tdep->pauth_ra_state_regnum)
1159 /* Initialize RA_STATE to zero. */
1160 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1161 reg->loc.exp.start = &op_lit0;
1162 reg->loc.exp.len = 1;
1165 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1166 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1168 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1174 /* Implement the execute_dwarf_cfa_vendor_op method. */
1177 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1178 struct dwarf2_frame_state *fs)
1180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1181 struct dwarf2_frame_state_reg *ra_state;
1183 if (tdep->has_pauth () && op == DW_CFA_AARCH64_negate_ra_state)
1185 /* Allocate RA_STATE column if it's not allocated yet. */
1186 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1188 /* Toggle the status of RA_STATE between 0 and 1. */
1189 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1190 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1192 if (ra_state->loc.exp.start == nullptr
1193 || ra_state->loc.exp.start == &op_lit0)
1194 ra_state->loc.exp.start = &op_lit1;
1196 ra_state->loc.exp.start = &op_lit0;
1198 ra_state->loc.exp.len = 1;
1206 /* When arguments must be pushed onto the stack, they go on in reverse
1207 order. The code below implements a FILO (stack) to do this. */
1211 /* Value to pass on stack. It can be NULL if this item is for stack
1213 const gdb_byte *data;
1215 /* Size in bytes of value to pass on stack. */
1219 /* Implement the gdbarch type alignment method, overrides the generic
1220 alignment algorithm for anything that is aarch64 specific. */
1223 aarch64_type_align (gdbarch *gdbarch, struct type *t)
1225 t = check_typedef (t);
1226 if (TYPE_CODE (t) == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
1228 /* Use the natural alignment for vector types (the same for
1229 scalar type), but the maximum alignment is 128-bit. */
1230 if (TYPE_LENGTH (t) > 16)
1233 return TYPE_LENGTH (t);
1236 /* Allow the common code to calculate the alignment. */
1240 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1242 Return the number of register required, or -1 on failure.
1244 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1245 to the element, else fail if the type of this element does not match the
1249 aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1250 struct type **fundamental_type)
1252 if (type == nullptr)
1255 switch (TYPE_CODE (type))
1258 if (TYPE_LENGTH (type) > 16)
1261 if (*fundamental_type == nullptr)
1262 *fundamental_type = type;
1263 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1264 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1269 case TYPE_CODE_COMPLEX:
1271 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1272 if (TYPE_LENGTH (target_type) > 16)
1275 if (*fundamental_type == nullptr)
1276 *fundamental_type = target_type;
1277 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1278 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1284 case TYPE_CODE_ARRAY:
1286 if (TYPE_VECTOR (type))
1288 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1291 if (*fundamental_type == nullptr)
1292 *fundamental_type = type;
1293 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1294 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1301 struct type *target_type = TYPE_TARGET_TYPE (type);
1302 int count = aapcs_is_vfp_call_or_return_candidate_1
1303 (target_type, fundamental_type);
1308 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
1313 case TYPE_CODE_STRUCT:
1314 case TYPE_CODE_UNION:
1318 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1320 /* Ignore any static fields. */
1321 if (field_is_static (&TYPE_FIELD (type, i)))
1324 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1326 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1327 (member, fundamental_type);
1328 if (sub_count == -1)
1333 /* Ensure there is no padding between the fields (allowing for empty
1334 zero length structs) */
1335 int ftype_length = (*fundamental_type == nullptr)
1336 ? 0 : TYPE_LENGTH (*fundamental_type);
1337 if (count * ftype_length != TYPE_LENGTH (type))
1350 /* Return true if an argument, whose type is described by TYPE, can be passed or
1351 returned in simd/fp registers, providing enough parameter passing registers
1352 are available. This is as described in the AAPCS64.
1354 Upon successful return, *COUNT returns the number of needed registers,
1355 *FUNDAMENTAL_TYPE contains the type of those registers.
1357 Candidate as per the AAPCS64 5.4.2.C is either a:
1360 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1361 all the members are floats and has at most 4 members.
1362 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1363 all the members are short vectors and has at most 4 members.
1366 Note that HFAs and HVAs can include nested structures and arrays. */
1369 aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1370 struct type **fundamental_type)
1372 if (type == nullptr)
1375 *fundamental_type = nullptr;
1377 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1380 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1389 /* AArch64 function call information structure. */
1390 struct aarch64_call_info
1392 /* the current argument number. */
1393 unsigned argnum = 0;
1395 /* The next general purpose register number, equivalent to NGRN as
1396 described in the AArch64 Procedure Call Standard. */
1399 /* The next SIMD and floating point register number, equivalent to
1400 NSRN as described in the AArch64 Procedure Call Standard. */
1403 /* The next stacked argument address, equivalent to NSAA as
1404 described in the AArch64 Procedure Call Standard. */
1407 /* Stack item vector. */
1408 std::vector<stack_item_t> si;
1411 /* Pass a value in a sequence of consecutive X registers. The caller
1412 is responsbile for ensuring sufficient registers are available. */
1415 pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1416 struct aarch64_call_info *info, struct type *type,
1419 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1420 int len = TYPE_LENGTH (type);
1421 enum type_code typecode = TYPE_CODE (type);
1422 int regnum = AARCH64_X0_REGNUM + info->ngrn;
1423 const bfd_byte *buf = value_contents (arg);
1429 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1430 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1434 /* Adjust sub-word struct/union args when big-endian. */
1435 if (byte_order == BFD_ENDIAN_BIG
1436 && partial_len < X_REGISTER_SIZE
1437 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1438 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1442 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1443 gdbarch_register_name (gdbarch, regnum),
1444 phex (regval, X_REGISTER_SIZE));
1446 regcache_cooked_write_unsigned (regcache, regnum, regval);
1453 /* Attempt to marshall a value in a V register. Return 1 if
1454 successful, or 0 if insufficient registers are available. This
1455 function, unlike the equivalent pass_in_x() function does not
1456 handle arguments spread across multiple registers. */
1459 pass_in_v (struct gdbarch *gdbarch,
1460 struct regcache *regcache,
1461 struct aarch64_call_info *info,
1462 int len, const bfd_byte *buf)
1466 int regnum = AARCH64_V0_REGNUM + info->nsrn;
1467 /* Enough space for a full vector register. */
1468 gdb_byte reg[register_size (gdbarch, regnum)];
1469 gdb_assert (len <= sizeof (reg));
1474 memset (reg, 0, sizeof (reg));
1475 /* PCS C.1, the argument is allocated to the least significant
1476 bits of V register. */
1477 memcpy (reg, buf, len);
1478 regcache->cooked_write (regnum, reg);
1482 debug_printf ("arg %d in %s\n", info->argnum,
1483 gdbarch_register_name (gdbarch, regnum));
1491 /* Marshall an argument onto the stack. */
1494 pass_on_stack (struct aarch64_call_info *info, struct type *type,
1497 const bfd_byte *buf = value_contents (arg);
1498 int len = TYPE_LENGTH (type);
1504 align = type_align (type);
1506 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1507 Natural alignment of the argument's type. */
1508 align = align_up (align, 8);
1510 /* The AArch64 PCS requires at most doubleword alignment. */
1516 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1522 info->si.push_back (item);
1525 if (info->nsaa & (align - 1))
1527 /* Push stack alignment padding. */
1528 int pad = align - (info->nsaa & (align - 1));
1533 info->si.push_back (item);
1538 /* Marshall an argument into a sequence of one or more consecutive X
1539 registers or, if insufficient X registers are available then onto
1543 pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1544 struct aarch64_call_info *info, struct type *type,
1547 int len = TYPE_LENGTH (type);
1548 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1550 /* PCS C.13 - Pass in registers if we have enough spare */
1551 if (info->ngrn + nregs <= 8)
1553 pass_in_x (gdbarch, regcache, info, type, arg);
1554 info->ngrn += nregs;
1559 pass_on_stack (info, type, arg);
1563 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1564 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1565 registers. A return value of false is an error state as the value will have
1566 been partially passed to the stack. */
1568 pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1569 struct aarch64_call_info *info, struct type *arg_type,
1572 switch (TYPE_CODE (arg_type))
1575 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1576 value_contents (arg));
1579 case TYPE_CODE_COMPLEX:
1581 const bfd_byte *buf = value_contents (arg);
1582 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1584 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1588 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1589 buf + TYPE_LENGTH (target_type));
1592 case TYPE_CODE_ARRAY:
1593 if (TYPE_VECTOR (arg_type))
1594 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1595 value_contents (arg));
1598 case TYPE_CODE_STRUCT:
1599 case TYPE_CODE_UNION:
1600 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1602 /* Don't include static fields. */
1603 if (field_is_static (&TYPE_FIELD (arg_type, i)))
1606 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1607 struct type *field_type = check_typedef (value_type (field));
1609 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1620 /* Implement the "push_dummy_call" gdbarch method. */
1623 aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1624 struct regcache *regcache, CORE_ADDR bp_addr,
1626 struct value **args, CORE_ADDR sp,
1627 function_call_return_method return_method,
1628 CORE_ADDR struct_addr)
1631 struct aarch64_call_info info;
1633 /* We need to know what the type of the called function is in order
1634 to determine the number of named/anonymous arguments for the
1635 actual argument placement, and the return type in order to handle
1636 return value correctly.
1638 The generic code above us views the decision of return in memory
1639 or return in registers as a two stage processes. The language
1640 handler is consulted first and may decide to return in memory (eg
1641 class with copy constructor returned by value), this will cause
1642 the generic code to allocate space AND insert an initial leading
1645 If the language code does not decide to pass in memory then the
1646 target code is consulted.
1648 If the language code decides to pass in memory we want to move
1649 the pointer inserted as the initial argument from the argument
1650 list and into X8, the conventional AArch64 struct return pointer
1653 /* Set the return address. For the AArch64, the return breakpoint
1654 is always at BP_ADDR. */
1655 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1657 /* If we were given an initial argument for the return slot, lose it. */
1658 if (return_method == return_method_hidden_param)
1664 /* The struct_return pointer occupies X8. */
1665 if (return_method != return_method_normal)
1669 debug_printf ("struct return in %s = 0x%s\n",
1670 gdbarch_register_name (gdbarch,
1671 AARCH64_STRUCT_RETURN_REGNUM),
1672 paddress (gdbarch, struct_addr));
1674 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1678 for (argnum = 0; argnum < nargs; argnum++)
1680 struct value *arg = args[argnum];
1681 struct type *arg_type, *fundamental_type;
1684 arg_type = check_typedef (value_type (arg));
1685 len = TYPE_LENGTH (arg_type);
1687 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1688 if there are enough spare registers. */
1689 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1692 if (info.nsrn + elements <= 8)
1694 /* We know that we have sufficient registers available therefore
1695 this will never need to fallback to the stack. */
1696 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1698 gdb_assert_not_reached ("Failed to push args");
1703 pass_on_stack (&info, arg_type, arg);
1708 switch (TYPE_CODE (arg_type))
1711 case TYPE_CODE_BOOL:
1712 case TYPE_CODE_CHAR:
1713 case TYPE_CODE_RANGE:
1714 case TYPE_CODE_ENUM:
1717 /* Promote to 32 bit integer. */
1718 if (TYPE_UNSIGNED (arg_type))
1719 arg_type = builtin_type (gdbarch)->builtin_uint32;
1721 arg_type = builtin_type (gdbarch)->builtin_int32;
1722 arg = value_cast (arg_type, arg);
1724 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1727 case TYPE_CODE_STRUCT:
1728 case TYPE_CODE_ARRAY:
1729 case TYPE_CODE_UNION:
1732 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1733 invisible reference. */
1735 /* Allocate aligned storage. */
1736 sp = align_down (sp - len, 16);
1738 /* Write the real data into the stack. */
1739 write_memory (sp, value_contents (arg), len);
1741 /* Construct the indirection. */
1742 arg_type = lookup_pointer_type (arg_type);
1743 arg = value_from_pointer (arg_type, sp);
1744 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1747 /* PCS C.15 / C.18 multiple values pass. */
1748 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1752 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
1757 /* Make sure stack retains 16 byte alignment. */
1759 sp -= 16 - (info.nsaa & 15);
1761 while (!info.si.empty ())
1763 const stack_item_t &si = info.si.back ();
1766 if (si.data != NULL)
1767 write_memory (sp, si.data, si.len);
1768 info.si.pop_back ();
1771 /* Finally, update the SP register. */
1772 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1777 /* Implement the "frame_align" gdbarch method. */
1780 aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1782 /* Align the stack to sixteen bytes. */
1783 return sp & ~(CORE_ADDR) 15;
1786 /* Return the type for an AdvSISD Q register. */
1788 static struct type *
1789 aarch64_vnq_type (struct gdbarch *gdbarch)
1791 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1793 if (tdep->vnq_type == NULL)
1798 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1801 elem = builtin_type (gdbarch)->builtin_uint128;
1802 append_composite_type_field (t, "u", elem);
1804 elem = builtin_type (gdbarch)->builtin_int128;
1805 append_composite_type_field (t, "s", elem);
1810 return tdep->vnq_type;
1813 /* Return the type for an AdvSISD D register. */
1815 static struct type *
1816 aarch64_vnd_type (struct gdbarch *gdbarch)
1818 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1820 if (tdep->vnd_type == NULL)
1825 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1828 elem = builtin_type (gdbarch)->builtin_double;
1829 append_composite_type_field (t, "f", elem);
1831 elem = builtin_type (gdbarch)->builtin_uint64;
1832 append_composite_type_field (t, "u", elem);
1834 elem = builtin_type (gdbarch)->builtin_int64;
1835 append_composite_type_field (t, "s", elem);
1840 return tdep->vnd_type;
1843 /* Return the type for an AdvSISD S register. */
1845 static struct type *
1846 aarch64_vns_type (struct gdbarch *gdbarch)
1848 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1850 if (tdep->vns_type == NULL)
1855 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1858 elem = builtin_type (gdbarch)->builtin_float;
1859 append_composite_type_field (t, "f", elem);
1861 elem = builtin_type (gdbarch)->builtin_uint32;
1862 append_composite_type_field (t, "u", elem);
1864 elem = builtin_type (gdbarch)->builtin_int32;
1865 append_composite_type_field (t, "s", elem);
1870 return tdep->vns_type;
1873 /* Return the type for an AdvSISD H register. */
1875 static struct type *
1876 aarch64_vnh_type (struct gdbarch *gdbarch)
1878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1880 if (tdep->vnh_type == NULL)
1885 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1888 elem = builtin_type (gdbarch)->builtin_uint16;
1889 append_composite_type_field (t, "u", elem);
1891 elem = builtin_type (gdbarch)->builtin_int16;
1892 append_composite_type_field (t, "s", elem);
1897 return tdep->vnh_type;
1900 /* Return the type for an AdvSISD B register. */
1902 static struct type *
1903 aarch64_vnb_type (struct gdbarch *gdbarch)
1905 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1907 if (tdep->vnb_type == NULL)
1912 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1915 elem = builtin_type (gdbarch)->builtin_uint8;
1916 append_composite_type_field (t, "u", elem);
1918 elem = builtin_type (gdbarch)->builtin_int8;
1919 append_composite_type_field (t, "s", elem);
1924 return tdep->vnb_type;
1927 /* Return the type for an AdvSISD V register. */
1929 static struct type *
1930 aarch64_vnv_type (struct gdbarch *gdbarch)
1932 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1934 if (tdep->vnv_type == NULL)
1936 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1937 slice from the non-pseudo vector registers. However NEON V registers
1938 are always vector registers, and need constructing as such. */
1939 const struct builtin_type *bt = builtin_type (gdbarch);
1941 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1944 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1946 append_composite_type_field (sub, "f",
1947 init_vector_type (bt->builtin_double, 2));
1948 append_composite_type_field (sub, "u",
1949 init_vector_type (bt->builtin_uint64, 2));
1950 append_composite_type_field (sub, "s",
1951 init_vector_type (bt->builtin_int64, 2));
1952 append_composite_type_field (t, "d", sub);
1954 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1956 append_composite_type_field (sub, "f",
1957 init_vector_type (bt->builtin_float, 4));
1958 append_composite_type_field (sub, "u",
1959 init_vector_type (bt->builtin_uint32, 4));
1960 append_composite_type_field (sub, "s",
1961 init_vector_type (bt->builtin_int32, 4));
1962 append_composite_type_field (t, "s", sub);
1964 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1966 append_composite_type_field (sub, "u",
1967 init_vector_type (bt->builtin_uint16, 8));
1968 append_composite_type_field (sub, "s",
1969 init_vector_type (bt->builtin_int16, 8));
1970 append_composite_type_field (t, "h", sub);
1972 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1974 append_composite_type_field (sub, "u",
1975 init_vector_type (bt->builtin_uint8, 16));
1976 append_composite_type_field (sub, "s",
1977 init_vector_type (bt->builtin_int8, 16));
1978 append_composite_type_field (t, "b", sub);
1980 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1982 append_composite_type_field (sub, "u",
1983 init_vector_type (bt->builtin_uint128, 1));
1984 append_composite_type_field (sub, "s",
1985 init_vector_type (bt->builtin_int128, 1));
1986 append_composite_type_field (t, "q", sub);
1991 return tdep->vnv_type;
1994 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1997 aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1999 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2001 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2002 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2004 if (reg == AARCH64_DWARF_SP)
2005 return AARCH64_SP_REGNUM;
2007 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2008 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2010 if (reg == AARCH64_DWARF_SVE_VG)
2011 return AARCH64_SVE_VG_REGNUM;
2013 if (reg == AARCH64_DWARF_SVE_FFR)
2014 return AARCH64_SVE_FFR_REGNUM;
2016 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2017 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2019 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2020 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2022 if (tdep->has_pauth ())
2024 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2025 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2027 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2028 return tdep->pauth_ra_state_regnum;
2034 /* Implement the "print_insn" gdbarch method. */
2037 aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2039 info->symbols = NULL;
2040 return default_print_insn (memaddr, info);
2043 /* AArch64 BRK software debug mode instruction.
2044 Note that AArch64 code is always little-endian.
2045 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2046 constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
2048 typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
2050 /* Extract from an array REGS containing the (raw) register state a
2051 function return value of type TYPE, and copy that, in virtual
2052 format, into VALBUF. */
2055 aarch64_extract_return_value (struct type *type, struct regcache *regs,
2058 struct gdbarch *gdbarch = regs->arch ();
2059 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2061 struct type *fundamental_type;
2063 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2066 int len = TYPE_LENGTH (fundamental_type);
2068 for (int i = 0; i < elements; i++)
2070 int regno = AARCH64_V0_REGNUM + i;
2071 /* Enough space for a full vector register. */
2072 gdb_byte buf[register_size (gdbarch, regno)];
2073 gdb_assert (len <= sizeof (buf));
2077 debug_printf ("read HFA or HVA return value element %d from %s\n",
2079 gdbarch_register_name (gdbarch, regno));
2081 regs->cooked_read (regno, buf);
2083 memcpy (valbuf, buf, len);
2087 else if (TYPE_CODE (type) == TYPE_CODE_INT
2088 || TYPE_CODE (type) == TYPE_CODE_CHAR
2089 || TYPE_CODE (type) == TYPE_CODE_BOOL
2090 || TYPE_CODE (type) == TYPE_CODE_PTR
2091 || TYPE_IS_REFERENCE (type)
2092 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2094 /* If the type is a plain integer, then the access is
2095 straight-forward. Otherwise we have to play around a bit
2097 int len = TYPE_LENGTH (type);
2098 int regno = AARCH64_X0_REGNUM;
2103 /* By using store_unsigned_integer we avoid having to do
2104 anything special for small big-endian values. */
2105 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2106 store_unsigned_integer (valbuf,
2107 (len > X_REGISTER_SIZE
2108 ? X_REGISTER_SIZE : len), byte_order, tmp);
2109 len -= X_REGISTER_SIZE;
2110 valbuf += X_REGISTER_SIZE;
2115 /* For a structure or union the behaviour is as if the value had
2116 been stored to word-aligned memory and then loaded into
2117 registers with 64-bit load instruction(s). */
2118 int len = TYPE_LENGTH (type);
2119 int regno = AARCH64_X0_REGNUM;
2120 bfd_byte buf[X_REGISTER_SIZE];
2124 regs->cooked_read (regno++, buf);
2125 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2126 len -= X_REGISTER_SIZE;
2127 valbuf += X_REGISTER_SIZE;
2133 /* Will a function return an aggregate type in memory or in a
2134 register? Return 0 if an aggregate type can be returned in a
2135 register, 1 if it must be returned in memory. */
2138 aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2140 type = check_typedef (type);
2142 struct type *fundamental_type;
2144 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2147 /* v0-v7 are used to return values and one register is allocated
2148 for one member. However, HFA or HVA has at most four members. */
2152 if (TYPE_LENGTH (type) > 16)
2154 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2155 invisible reference. */
2163 /* Write into appropriate registers a function return value of type
2164 TYPE, given in virtual format. */
2167 aarch64_store_return_value (struct type *type, struct regcache *regs,
2168 const gdb_byte *valbuf)
2170 struct gdbarch *gdbarch = regs->arch ();
2171 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2173 struct type *fundamental_type;
2175 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2178 int len = TYPE_LENGTH (fundamental_type);
2180 for (int i = 0; i < elements; i++)
2182 int regno = AARCH64_V0_REGNUM + i;
2183 /* Enough space for a full vector register. */
2184 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2185 gdb_assert (len <= sizeof (tmpbuf));
2189 debug_printf ("write HFA or HVA return value element %d to %s\n",
2191 gdbarch_register_name (gdbarch, regno));
2194 memcpy (tmpbuf, valbuf,
2195 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2196 regs->cooked_write (regno, tmpbuf);
2200 else if (TYPE_CODE (type) == TYPE_CODE_INT
2201 || TYPE_CODE (type) == TYPE_CODE_CHAR
2202 || TYPE_CODE (type) == TYPE_CODE_BOOL
2203 || TYPE_CODE (type) == TYPE_CODE_PTR
2204 || TYPE_IS_REFERENCE (type)
2205 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2207 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2209 /* Values of one word or less are zero/sign-extended and
2211 bfd_byte tmpbuf[X_REGISTER_SIZE];
2212 LONGEST val = unpack_long (type, valbuf);
2214 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
2215 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
2219 /* Integral values greater than one word are stored in
2220 consecutive registers starting with r0. This will always
2221 be a multiple of the regiser size. */
2222 int len = TYPE_LENGTH (type);
2223 int regno = AARCH64_X0_REGNUM;
2227 regs->cooked_write (regno++, valbuf);
2228 len -= X_REGISTER_SIZE;
2229 valbuf += X_REGISTER_SIZE;
2235 /* For a structure or union the behaviour is as if the value had
2236 been stored to word-aligned memory and then loaded into
2237 registers with 64-bit load instruction(s). */
2238 int len = TYPE_LENGTH (type);
2239 int regno = AARCH64_X0_REGNUM;
2240 bfd_byte tmpbuf[X_REGISTER_SIZE];
2244 memcpy (tmpbuf, valbuf,
2245 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2246 regs->cooked_write (regno++, tmpbuf);
2247 len -= X_REGISTER_SIZE;
2248 valbuf += X_REGISTER_SIZE;
2253 /* Implement the "return_value" gdbarch method. */
2255 static enum return_value_convention
2256 aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2257 struct type *valtype, struct regcache *regcache,
2258 gdb_byte *readbuf, const gdb_byte *writebuf)
2261 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2262 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2263 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2265 if (aarch64_return_in_memory (gdbarch, valtype))
2268 debug_printf ("return value in memory\n");
2269 return RETURN_VALUE_STRUCT_CONVENTION;
2274 aarch64_store_return_value (valtype, regcache, writebuf);
2277 aarch64_extract_return_value (valtype, regcache, readbuf);
2280 debug_printf ("return value in registers\n");
2282 return RETURN_VALUE_REGISTER_CONVENTION;
2285 /* Implement the "get_longjmp_target" gdbarch method. */
2288 aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2291 gdb_byte buf[X_REGISTER_SIZE];
2292 struct gdbarch *gdbarch = get_frame_arch (frame);
2293 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2296 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2298 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2302 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2306 /* Implement the "gen_return_address" gdbarch method. */
2309 aarch64_gen_return_address (struct gdbarch *gdbarch,
2310 struct agent_expr *ax, struct axs_value *value,
2313 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2314 value->kind = axs_lvalue_register;
2315 value->u.reg = AARCH64_LR_REGNUM;
2319 /* Return the pseudo register name corresponding to register regnum. */
2322 aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2324 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2326 static const char *const q_name[] =
2328 "q0", "q1", "q2", "q3",
2329 "q4", "q5", "q6", "q7",
2330 "q8", "q9", "q10", "q11",
2331 "q12", "q13", "q14", "q15",
2332 "q16", "q17", "q18", "q19",
2333 "q20", "q21", "q22", "q23",
2334 "q24", "q25", "q26", "q27",
2335 "q28", "q29", "q30", "q31",
2338 static const char *const d_name[] =
2340 "d0", "d1", "d2", "d3",
2341 "d4", "d5", "d6", "d7",
2342 "d8", "d9", "d10", "d11",
2343 "d12", "d13", "d14", "d15",
2344 "d16", "d17", "d18", "d19",
2345 "d20", "d21", "d22", "d23",
2346 "d24", "d25", "d26", "d27",
2347 "d28", "d29", "d30", "d31",
2350 static const char *const s_name[] =
2352 "s0", "s1", "s2", "s3",
2353 "s4", "s5", "s6", "s7",
2354 "s8", "s9", "s10", "s11",
2355 "s12", "s13", "s14", "s15",
2356 "s16", "s17", "s18", "s19",
2357 "s20", "s21", "s22", "s23",
2358 "s24", "s25", "s26", "s27",
2359 "s28", "s29", "s30", "s31",
2362 static const char *const h_name[] =
2364 "h0", "h1", "h2", "h3",
2365 "h4", "h5", "h6", "h7",
2366 "h8", "h9", "h10", "h11",
2367 "h12", "h13", "h14", "h15",
2368 "h16", "h17", "h18", "h19",
2369 "h20", "h21", "h22", "h23",
2370 "h24", "h25", "h26", "h27",
2371 "h28", "h29", "h30", "h31",
2374 static const char *const b_name[] =
2376 "b0", "b1", "b2", "b3",
2377 "b4", "b5", "b6", "b7",
2378 "b8", "b9", "b10", "b11",
2379 "b12", "b13", "b14", "b15",
2380 "b16", "b17", "b18", "b19",
2381 "b20", "b21", "b22", "b23",
2382 "b24", "b25", "b26", "b27",
2383 "b28", "b29", "b30", "b31",
2386 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
2388 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2389 return q_name[p_regnum - AARCH64_Q0_REGNUM];
2391 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2392 return d_name[p_regnum - AARCH64_D0_REGNUM];
2394 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2395 return s_name[p_regnum - AARCH64_S0_REGNUM];
2397 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2398 return h_name[p_regnum - AARCH64_H0_REGNUM];
2400 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2401 return b_name[p_regnum - AARCH64_B0_REGNUM];
2403 if (tdep->has_sve ())
2405 static const char *const sve_v_name[] =
2407 "v0", "v1", "v2", "v3",
2408 "v4", "v5", "v6", "v7",
2409 "v8", "v9", "v10", "v11",
2410 "v12", "v13", "v14", "v15",
2411 "v16", "v17", "v18", "v19",
2412 "v20", "v21", "v22", "v23",
2413 "v24", "v25", "v26", "v27",
2414 "v28", "v29", "v30", "v31",
2417 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2418 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2419 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
2422 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2423 prevents it from being read by methods such as
2424 mi_cmd_trace_frame_collected. */
2425 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2428 internal_error (__FILE__, __LINE__,
2429 _("aarch64_pseudo_register_name: bad register number %d"),
2433 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2435 static struct type *
2436 aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2438 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2440 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
2442 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2443 return aarch64_vnq_type (gdbarch);
2445 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2446 return aarch64_vnd_type (gdbarch);
2448 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2449 return aarch64_vns_type (gdbarch);
2451 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2452 return aarch64_vnh_type (gdbarch);
2454 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2455 return aarch64_vnb_type (gdbarch);
2457 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2458 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2459 return aarch64_vnv_type (gdbarch);
2461 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2462 return builtin_type (gdbarch)->builtin_uint64;
2464 internal_error (__FILE__, __LINE__,
2465 _("aarch64_pseudo_register_type: bad register number %d"),
2469 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2472 aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2473 struct reggroup *group)
2475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2477 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
2479 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2480 return group == all_reggroup || group == vector_reggroup;
2481 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2482 return (group == all_reggroup || group == vector_reggroup
2483 || group == float_reggroup);
2484 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2485 return (group == all_reggroup || group == vector_reggroup
2486 || group == float_reggroup);
2487 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2488 return group == all_reggroup || group == vector_reggroup;
2489 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2490 return group == all_reggroup || group == vector_reggroup;
2491 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2492 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2493 return group == all_reggroup || group == vector_reggroup;
2494 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2495 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2498 return group == all_reggroup;
2501 /* Helper for aarch64_pseudo_read_value. */
2503 static struct value *
2504 aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2505 readable_regcache *regcache, int regnum_offset,
2506 int regsize, struct value *result_value)
2508 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2510 /* Enough space for a full vector register. */
2511 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2512 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2514 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2515 mark_value_bytes_unavailable (result_value, 0,
2516 TYPE_LENGTH (value_type (result_value)));
2518 memcpy (value_contents_raw (result_value), reg_buf, regsize);
2520 return result_value;
2523 /* Implement the "pseudo_register_read_value" gdbarch method. */
2525 static struct value *
2526 aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
2529 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2530 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
2532 VALUE_LVAL (result_value) = lval_register;
2533 VALUE_REGNUM (result_value) = regnum;
2535 regnum -= gdbarch_num_regs (gdbarch);
2537 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2538 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2539 regnum - AARCH64_Q0_REGNUM,
2540 Q_REGISTER_SIZE, result_value);
2542 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2543 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2544 regnum - AARCH64_D0_REGNUM,
2545 D_REGISTER_SIZE, result_value);
2547 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2548 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2549 regnum - AARCH64_S0_REGNUM,
2550 S_REGISTER_SIZE, result_value);
2552 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2553 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2554 regnum - AARCH64_H0_REGNUM,
2555 H_REGISTER_SIZE, result_value);
2557 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2558 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2559 regnum - AARCH64_B0_REGNUM,
2560 B_REGISTER_SIZE, result_value);
2562 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2563 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2564 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2565 regnum - AARCH64_SVE_V0_REGNUM,
2566 V_REGISTER_SIZE, result_value);
2568 gdb_assert_not_reached ("regnum out of bound");
2571 /* Helper for aarch64_pseudo_write. */
2574 aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2575 int regnum_offset, int regsize, const gdb_byte *buf)
2577 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2579 /* Enough space for a full vector register. */
2580 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2581 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2583 /* Ensure the register buffer is zero, we want gdb writes of the
2584 various 'scalar' pseudo registers to behavior like architectural
2585 writes, register width bytes are written the remainder are set to
2587 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
2589 memcpy (reg_buf, buf, regsize);
2590 regcache->raw_write (v_regnum, reg_buf);
2593 /* Implement the "pseudo_register_write" gdbarch method. */
2596 aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2597 int regnum, const gdb_byte *buf)
2599 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2600 regnum -= gdbarch_num_regs (gdbarch);
2602 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2603 return aarch64_pseudo_write_1 (gdbarch, regcache,
2604 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2607 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2608 return aarch64_pseudo_write_1 (gdbarch, regcache,
2609 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2612 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2613 return aarch64_pseudo_write_1 (gdbarch, regcache,
2614 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2617 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2618 return aarch64_pseudo_write_1 (gdbarch, regcache,
2619 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2622 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2623 return aarch64_pseudo_write_1 (gdbarch, regcache,
2624 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2627 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2628 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2629 return aarch64_pseudo_write_1 (gdbarch, regcache,
2630 regnum - AARCH64_SVE_V0_REGNUM,
2631 V_REGISTER_SIZE, buf);
2633 gdb_assert_not_reached ("regnum out of bound");
2636 /* Callback function for user_reg_add. */
2638 static struct value *
2639 value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2641 const int *reg_p = (const int *) baton;
2643 return value_of_register (*reg_p, frame);
2647 /* Implement the "software_single_step" gdbarch method, needed to
2648 single step through atomic sequences on AArch64. */
2650 static std::vector<CORE_ADDR>
2651 aarch64_software_single_step (struct regcache *regcache)
2653 struct gdbarch *gdbarch = regcache->arch ();
2654 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2655 const int insn_size = 4;
2656 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2657 CORE_ADDR pc = regcache_read_pc (regcache);
2658 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
2660 CORE_ADDR closing_insn = 0;
2661 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2662 byte_order_for_code);
2665 int bc_insn_count = 0; /* Conditional branch instruction count. */
2666 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2669 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2672 /* Look for a Load Exclusive instruction which begins the sequence. */
2673 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
2676 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2679 insn = read_memory_unsigned_integer (loc, insn_size,
2680 byte_order_for_code);
2682 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2684 /* Check if the instruction is a conditional branch. */
2685 if (inst.opcode->iclass == condbranch)
2687 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2689 if (bc_insn_count >= 1)
2692 /* It is, so we'll try to set a breakpoint at the destination. */
2693 breaks[1] = loc + inst.operands[0].imm.value;
2699 /* Look for the Store Exclusive which closes the atomic sequence. */
2700 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
2707 /* We didn't find a closing Store Exclusive instruction, fall back. */
2711 /* Insert breakpoint after the end of the atomic sequence. */
2712 breaks[0] = loc + insn_size;
2714 /* Check for duplicated breakpoints, and also check that the second
2715 breakpoint is not within the atomic sequence. */
2717 && (breaks[1] == breaks[0]
2718 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2719 last_breakpoint = 0;
2721 std::vector<CORE_ADDR> next_pcs;
2723 /* Insert the breakpoint at the end of the sequence, and one at the
2724 destination of the conditional branch, if it exists. */
2725 for (index = 0; index <= last_breakpoint; index++)
2726 next_pcs.push_back (breaks[index]);
2731 struct aarch64_displaced_step_closure : public displaced_step_closure
2733 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2734 is being displaced stepping. */
2737 /* PC adjustment offset after displaced stepping. */
2738 int32_t pc_adjust = 0;
2741 /* Data when visiting instructions for displaced stepping. */
2743 struct aarch64_displaced_step_data
2745 struct aarch64_insn_data base;
2747 /* The address where the instruction will be executed at. */
2749 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2750 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2751 /* Number of instructions in INSN_BUF. */
2752 unsigned insn_count;
2753 /* Registers when doing displaced stepping. */
2754 struct regcache *regs;
2756 aarch64_displaced_step_closure *dsc;
2759 /* Implementation of aarch64_insn_visitor method "b". */
2762 aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2763 struct aarch64_insn_data *data)
2765 struct aarch64_displaced_step_data *dsd
2766 = (struct aarch64_displaced_step_data *) data;
2767 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
2769 if (can_encode_int32 (new_offset, 28))
2771 /* Emit B rather than BL, because executing BL on a new address
2772 will get the wrong address into LR. In order to avoid this,
2773 we emit B, and update LR if the instruction is BL. */
2774 emit_b (dsd->insn_buf, 0, new_offset);
2780 emit_nop (dsd->insn_buf);
2782 dsd->dsc->pc_adjust = offset;
2788 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2789 data->insn_addr + 4);
2793 /* Implementation of aarch64_insn_visitor method "b_cond". */
2796 aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2797 struct aarch64_insn_data *data)
2799 struct aarch64_displaced_step_data *dsd
2800 = (struct aarch64_displaced_step_data *) data;
2802 /* GDB has to fix up PC after displaced step this instruction
2803 differently according to the condition is true or false. Instead
2804 of checking COND against conditional flags, we can use
2805 the following instructions, and GDB can tell how to fix up PC
2806 according to the PC value.
2808 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2814 emit_bcond (dsd->insn_buf, cond, 8);
2816 dsd->dsc->pc_adjust = offset;
2817 dsd->insn_count = 1;
2820 /* Dynamically allocate a new register. If we know the register
2821 statically, we should make it a global as above instead of using this
2824 static struct aarch64_register
2825 aarch64_register (unsigned num, int is64)
2827 return (struct aarch64_register) { num, is64 };
2830 /* Implementation of aarch64_insn_visitor method "cb". */
2833 aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2834 const unsigned rn, int is64,
2835 struct aarch64_insn_data *data)
2837 struct aarch64_displaced_step_data *dsd
2838 = (struct aarch64_displaced_step_data *) data;
2840 /* The offset is out of range for a compare and branch
2841 instruction. We can use the following instructions instead:
2843 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2848 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2849 dsd->insn_count = 1;
2851 dsd->dsc->pc_adjust = offset;
2854 /* Implementation of aarch64_insn_visitor method "tb". */
2857 aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2858 const unsigned rt, unsigned bit,
2859 struct aarch64_insn_data *data)
2861 struct aarch64_displaced_step_data *dsd
2862 = (struct aarch64_displaced_step_data *) data;
2864 /* The offset is out of range for a test bit and branch
2865 instruction We can use the following instructions instead:
2867 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2873 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2874 dsd->insn_count = 1;
2876 dsd->dsc->pc_adjust = offset;
2879 /* Implementation of aarch64_insn_visitor method "adr". */
2882 aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2883 const int is_adrp, struct aarch64_insn_data *data)
2885 struct aarch64_displaced_step_data *dsd
2886 = (struct aarch64_displaced_step_data *) data;
2887 /* We know exactly the address the ADR{P,} instruction will compute.
2888 We can just write it to the destination register. */
2889 CORE_ADDR address = data->insn_addr + offset;
2893 /* Clear the lower 12 bits of the offset to get the 4K page. */
2894 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2898 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2901 dsd->dsc->pc_adjust = 4;
2902 emit_nop (dsd->insn_buf);
2903 dsd->insn_count = 1;
2906 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2909 aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2910 const unsigned rt, const int is64,
2911 struct aarch64_insn_data *data)
2913 struct aarch64_displaced_step_data *dsd
2914 = (struct aarch64_displaced_step_data *) data;
2915 CORE_ADDR address = data->insn_addr + offset;
2916 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2918 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2922 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2923 aarch64_register (rt, 1), zero);
2925 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2926 aarch64_register (rt, 1), zero);
2928 dsd->dsc->pc_adjust = 4;
2931 /* Implementation of aarch64_insn_visitor method "others". */
2934 aarch64_displaced_step_others (const uint32_t insn,
2935 struct aarch64_insn_data *data)
2937 struct aarch64_displaced_step_data *dsd
2938 = (struct aarch64_displaced_step_data *) data;
2940 aarch64_emit_insn (dsd->insn_buf, insn);
2941 dsd->insn_count = 1;
2943 if ((insn & 0xfffffc1f) == 0xd65f0000)
2946 dsd->dsc->pc_adjust = 0;
2949 dsd->dsc->pc_adjust = 4;
2952 static const struct aarch64_insn_visitor visitor =
2954 aarch64_displaced_step_b,
2955 aarch64_displaced_step_b_cond,
2956 aarch64_displaced_step_cb,
2957 aarch64_displaced_step_tb,
2958 aarch64_displaced_step_adr,
2959 aarch64_displaced_step_ldr_literal,
2960 aarch64_displaced_step_others,
2963 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2965 struct displaced_step_closure *
2966 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2967 CORE_ADDR from, CORE_ADDR to,
2968 struct regcache *regs)
2970 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2971 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2972 struct aarch64_displaced_step_data dsd;
2975 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
2978 /* Look for a Load Exclusive instruction which begins the sequence. */
2979 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
2981 /* We can't displaced step atomic sequences. */
2985 std::unique_ptr<aarch64_displaced_step_closure> dsc
2986 (new aarch64_displaced_step_closure);
2987 dsd.base.insn_addr = from;
2990 dsd.dsc = dsc.get ();
2992 aarch64_relocate_instruction (insn, &visitor,
2993 (struct aarch64_insn_data *) &dsd);
2994 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2996 if (dsd.insn_count != 0)
3000 /* Instruction can be relocated to scratch pad. Copy
3001 relocated instruction(s) there. */
3002 for (i = 0; i < dsd.insn_count; i++)
3004 if (debug_displaced)
3006 debug_printf ("displaced: writing insn ");
3007 debug_printf ("%.8x", dsd.insn_buf[i]);
3008 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
3010 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3011 (ULONGEST) dsd.insn_buf[i]);
3019 return dsc.release ();
3022 /* Implement the "displaced_step_fixup" gdbarch method. */
3025 aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
3026 struct displaced_step_closure *dsc_,
3027 CORE_ADDR from, CORE_ADDR to,
3028 struct regcache *regs)
3030 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
3036 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3039 /* Condition is true. */
3041 else if (pc - to == 4)
3043 /* Condition is false. */
3047 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3050 if (dsc->pc_adjust != 0)
3052 if (debug_displaced)
3054 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3055 paddress (gdbarch, from), dsc->pc_adjust);
3057 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3058 from + dsc->pc_adjust);
3062 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3065 aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
3066 struct displaced_step_closure *closure)
3071 /* Get the correct target description for the given VQ value.
3072 If VQ is zero then it is assumed SVE is not supported.
3073 (It is not possible to set VQ to zero on an SVE system). */
3076 aarch64_read_description (uint64_t vq, bool pauth_p)
3078 if (vq > AARCH64_MAX_SVE_VQ)
3079 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
3080 AARCH64_MAX_SVE_VQ);
3082 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
3086 tdesc = aarch64_create_target_description (vq, pauth_p);
3087 tdesc_aarch64_list[vq][pauth_p] = tdesc;
3093 /* Return the VQ used when creating the target description TDESC. */
3096 aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3098 const struct tdesc_feature *feature_sve;
3100 if (!tdesc_has_registers (tdesc))
3103 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3105 if (feature_sve == nullptr)
3108 uint64_t vl = tdesc_register_bitsize (feature_sve,
3109 aarch64_sve_register_names[0]) / 8;
3110 return sve_vq_from_vl (vl);
3113 /* Add all the expected register sets into GDBARCH. */
3116 aarch64_add_reggroups (struct gdbarch *gdbarch)
3118 reggroup_add (gdbarch, general_reggroup);
3119 reggroup_add (gdbarch, float_reggroup);
3120 reggroup_add (gdbarch, system_reggroup);
3121 reggroup_add (gdbarch, vector_reggroup);
3122 reggroup_add (gdbarch, all_reggroup);
3123 reggroup_add (gdbarch, save_reggroup);
3124 reggroup_add (gdbarch, restore_reggroup);
3127 /* Implement the "cannot_store_register" gdbarch method. */
3130 aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3132 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3134 if (!tdep->has_pauth ())
3137 /* Pointer authentication registers are read-only. */
3138 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3139 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3142 /* Initialize the current architecture based on INFO. If possible,
3143 re-use an architecture from ARCHES, which is a list of
3144 architectures already created during this debugging session.
3146 Called e.g. at program startup, when reading a core file, and when
3147 reading a binary file. */
3149 static struct gdbarch *
3150 aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3152 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
3153 const struct tdesc_feature *feature_pauth;
3154 bool valid_p = true;
3155 int i, num_regs = 0, num_pseudo_regs = 0;
3156 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3158 /* Use the vector length passed via the target info. Here -1 is used for no
3159 SVE, and 0 is unset. If unset then use the vector length from the existing
3162 if (info.id == (int *) -1)
3164 else if (info.id != 0)
3165 vq = (uint64_t) info.id;
3167 vq = aarch64_get_tdesc_vq (info.target_desc);
3169 if (vq > AARCH64_MAX_SVE_VQ)
3170 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3171 pulongest (vq), AARCH64_MAX_SVE_VQ);
3173 /* If there is already a candidate, use it. */
3174 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3175 best_arch != nullptr;
3176 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3178 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
3179 if (tdep && tdep->vq == vq)
3180 return best_arch->gdbarch;
3183 /* Ensure we always have a target descriptor, and that it is for the given VQ
3185 const struct target_desc *tdesc = info.target_desc;
3186 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3187 tdesc = aarch64_read_description (vq, false);
3190 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
3191 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3192 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3193 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
3195 if (feature_core == nullptr)
3198 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
3200 /* Validate the description provides the mandatory core R registers
3201 and allocate their numbers. */
3202 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
3203 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3204 AARCH64_X0_REGNUM + i,
3205 aarch64_r_register_names[i]);
3207 num_regs = AARCH64_X0_REGNUM + i;
3209 /* Add the V registers. */
3210 if (feature_fpu != nullptr)
3212 if (feature_sve != nullptr)
3213 error (_("Program contains both fpu and SVE features."));
3215 /* Validate the description provides the mandatory V registers
3216 and allocate their numbers. */
3217 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
3218 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3219 AARCH64_V0_REGNUM + i,
3220 aarch64_v_register_names[i]);
3222 num_regs = AARCH64_V0_REGNUM + i;
3225 /* Add the SVE registers. */
3226 if (feature_sve != nullptr)
3228 /* Validate the description provides the mandatory SVE registers
3229 and allocate their numbers. */
3230 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3231 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3232 AARCH64_SVE_Z0_REGNUM + i,
3233 aarch64_sve_register_names[i]);
3235 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3236 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3239 if (feature_fpu != nullptr || feature_sve != nullptr)
3241 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3242 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3243 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3244 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3245 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3248 /* Add the pauth registers. */
3249 if (feature_pauth != NULL)
3251 first_pauth_regnum = num_regs;
3252 pauth_ra_state_offset = num_pseudo_regs;
3253 /* Validate the descriptor provides the mandatory PAUTH registers and
3254 allocate their numbers. */
3255 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
3256 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
3257 first_pauth_regnum + i,
3258 aarch64_pauth_register_names[i]);
3261 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
3266 tdesc_data_cleanup (tdesc_data);
3270 /* AArch64 code is always little-endian. */
3271 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3273 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3274 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
3276 /* This should be low enough for everything. */
3277 tdep->lowest_pc = 0x20;
3278 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3279 tdep->jb_elt_size = 8;
3281 tdep->pauth_reg_base = first_pauth_regnum;
3282 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3283 : pauth_ra_state_offset + num_regs;
3285 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3286 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3288 /* Advance PC across function entry code. */
3289 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3291 /* The stack grows downward. */
3292 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3294 /* Breakpoint manipulation. */
3295 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3296 aarch64_breakpoint::kind_from_pc);
3297 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3298 aarch64_breakpoint::bp_from_kind);
3299 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3300 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
3302 /* Information about registers, etc. */
3303 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3304 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3305 set_gdbarch_num_regs (gdbarch, num_regs);
3307 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3308 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3309 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3310 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3311 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3312 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3313 aarch64_pseudo_register_reggroup_p);
3314 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
3317 set_gdbarch_short_bit (gdbarch, 16);
3318 set_gdbarch_int_bit (gdbarch, 32);
3319 set_gdbarch_float_bit (gdbarch, 32);
3320 set_gdbarch_double_bit (gdbarch, 64);
3321 set_gdbarch_long_double_bit (gdbarch, 128);
3322 set_gdbarch_long_bit (gdbarch, 64);
3323 set_gdbarch_long_long_bit (gdbarch, 64);
3324 set_gdbarch_ptr_bit (gdbarch, 64);
3325 set_gdbarch_char_signed (gdbarch, 0);
3326 set_gdbarch_wchar_signed (gdbarch, 0);
3327 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3328 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3329 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3330 set_gdbarch_type_align (gdbarch, aarch64_type_align);
3332 /* Internal <-> external register number maps. */
3333 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3335 /* Returning results. */
3336 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3339 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3341 /* Virtual tables. */
3342 set_gdbarch_vbit_in_delta (gdbarch, 1);
3344 /* Register architecture. */
3345 aarch64_add_reggroups (gdbarch);
3347 /* Hook in the ABI-specific overrides, if they have been registered. */
3348 info.target_desc = tdesc;
3349 info.tdesc_data = tdesc_data;
3350 gdbarch_init_osabi (info, gdbarch);
3352 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3353 /* Register DWARF CFA vendor handler. */
3354 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3355 aarch64_execute_dwarf_cfa_vendor_op);
3357 /* Add some default predicates. */
3358 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3359 dwarf2_append_unwinders (gdbarch);
3360 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3362 frame_base_set_default (gdbarch, &aarch64_normal_base);
3364 /* Now we have tuned the configuration, set a few final things,
3365 based on what the OS ABI has told us. */
3367 if (tdep->jb_pc >= 0)
3368 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3370 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3372 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3374 /* Add standard register aliases. */
3375 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3376 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3377 value_of_aarch64_user_reg,
3378 &aarch64_register_aliases[i].regnum);
3380 register_aarch64_ravenscar_ops (gdbarch);
3386 aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3388 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3393 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3394 paddress (gdbarch, tdep->lowest_pc));
3400 static void aarch64_process_record_test (void);
3405 _initialize_aarch64_tdep (void)
3407 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3410 /* Debug this file's internals. */
3411 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3412 Set AArch64 debugging."), _("\
3413 Show AArch64 debugging."), _("\
3414 When on, AArch64 specific debugging is enabled."),
3417 &setdebuglist, &showdebuglist);
3420 selftests::register_test ("aarch64-analyze-prologue",
3421 selftests::aarch64_analyze_prologue_test);
3422 selftests::register_test ("aarch64-process-record",
3423 selftests::aarch64_process_record_test);
3424 selftests::record_xml_tdesc ("aarch64.xml",
3425 aarch64_create_target_description (0, false));
3429 /* AArch64 process record-replay related structures, defines etc. */
3431 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3434 unsigned int reg_len = LENGTH; \
3437 REGS = XNEWVEC (uint32_t, reg_len); \
3438 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3443 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3446 unsigned int mem_len = LENGTH; \
3449 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3450 memcpy(&MEMS->len, &RECORD_BUF[0], \
3451 sizeof(struct aarch64_mem_r) * LENGTH); \
3456 /* AArch64 record/replay structures and enumerations. */
3458 struct aarch64_mem_r
3460 uint64_t len; /* Record length. */
3461 uint64_t addr; /* Memory address. */
3464 enum aarch64_record_result
3466 AARCH64_RECORD_SUCCESS,
3467 AARCH64_RECORD_UNSUPPORTED,
3468 AARCH64_RECORD_UNKNOWN
3471 typedef struct insn_decode_record_t
3473 struct gdbarch *gdbarch;
3474 struct regcache *regcache;
3475 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3476 uint32_t aarch64_insn; /* Insn to be recorded. */
3477 uint32_t mem_rec_count; /* Count of memory records. */
3478 uint32_t reg_rec_count; /* Count of register records. */
3479 uint32_t *aarch64_regs; /* Registers to be recorded. */
3480 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3481 } insn_decode_record;
3483 /* Record handler for data processing - register instructions. */
3486 aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3488 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3489 uint32_t record_buf[4];
3491 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3492 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3493 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3495 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3499 /* Logical (shifted register). */
3500 if (insn_bits24_27 == 0x0a)
3501 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3503 else if (insn_bits24_27 == 0x0b)
3504 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3506 return AARCH64_RECORD_UNKNOWN;
3508 record_buf[0] = reg_rd;
3509 aarch64_insn_r->reg_rec_count = 1;
3511 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3515 if (insn_bits24_27 == 0x0b)
3517 /* Data-processing (3 source). */
3518 record_buf[0] = reg_rd;
3519 aarch64_insn_r->reg_rec_count = 1;
3521 else if (insn_bits24_27 == 0x0a)
3523 if (insn_bits21_23 == 0x00)
3525 /* Add/subtract (with carry). */
3526 record_buf[0] = reg_rd;
3527 aarch64_insn_r->reg_rec_count = 1;
3528 if (bit (aarch64_insn_r->aarch64_insn, 29))
3530 record_buf[1] = AARCH64_CPSR_REGNUM;
3531 aarch64_insn_r->reg_rec_count = 2;
3534 else if (insn_bits21_23 == 0x02)
3536 /* Conditional compare (register) and conditional compare
3537 (immediate) instructions. */
3538 record_buf[0] = AARCH64_CPSR_REGNUM;
3539 aarch64_insn_r->reg_rec_count = 1;
3541 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3543 /* CConditional select. */
3544 /* Data-processing (2 source). */
3545 /* Data-processing (1 source). */
3546 record_buf[0] = reg_rd;
3547 aarch64_insn_r->reg_rec_count = 1;
3550 return AARCH64_RECORD_UNKNOWN;
3554 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3556 return AARCH64_RECORD_SUCCESS;
3559 /* Record handler for data processing - immediate instructions. */
3562 aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3564 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
3565 uint32_t record_buf[4];
3567 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3568 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3569 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3571 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3572 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3573 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3575 record_buf[0] = reg_rd;
3576 aarch64_insn_r->reg_rec_count = 1;
3578 else if (insn_bits24_27 == 0x01)
3580 /* Add/Subtract (immediate). */
3581 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3582 record_buf[0] = reg_rd;
3583 aarch64_insn_r->reg_rec_count = 1;
3585 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3587 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3589 /* Logical (immediate). */
3590 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3591 record_buf[0] = reg_rd;
3592 aarch64_insn_r->reg_rec_count = 1;
3594 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3597 return AARCH64_RECORD_UNKNOWN;
3599 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3601 return AARCH64_RECORD_SUCCESS;
3604 /* Record handler for branch, exception generation and system instructions. */
3607 aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3609 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3610 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3611 uint32_t record_buf[4];
3613 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3614 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3615 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3617 if (insn_bits28_31 == 0x0d)
3619 /* Exception generation instructions. */
3620 if (insn_bits24_27 == 0x04)
3622 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3623 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3624 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
3626 ULONGEST svc_number;
3628 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3630 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3634 return AARCH64_RECORD_UNSUPPORTED;
3636 /* System instructions. */
3637 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3639 uint32_t reg_rt, reg_crn;
3641 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3642 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3644 /* Record rt in case of sysl and mrs instructions. */
3645 if (bit (aarch64_insn_r->aarch64_insn, 21))
3647 record_buf[0] = reg_rt;
3648 aarch64_insn_r->reg_rec_count = 1;
3650 /* Record cpsr for hint and msr(immediate) instructions. */
3651 else if (reg_crn == 0x02 || reg_crn == 0x04)
3653 record_buf[0] = AARCH64_CPSR_REGNUM;
3654 aarch64_insn_r->reg_rec_count = 1;
3657 /* Unconditional branch (register). */
3658 else if((insn_bits24_27 & 0x0e) == 0x06)
3660 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3661 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3662 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3665 return AARCH64_RECORD_UNKNOWN;
3667 /* Unconditional branch (immediate). */
3668 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3670 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3671 if (bit (aarch64_insn_r->aarch64_insn, 31))
3672 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3675 /* Compare & branch (immediate), Test & branch (immediate) and
3676 Conditional branch (immediate). */
3677 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3679 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3681 return AARCH64_RECORD_SUCCESS;
3684 /* Record handler for advanced SIMD load and store instructions. */
3687 aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3690 uint64_t addr_offset = 0;
3691 uint32_t record_buf[24];
3692 uint64_t record_buf_mem[24];
3693 uint32_t reg_rn, reg_rt;
3694 uint32_t reg_index = 0, mem_index = 0;
3695 uint8_t opcode_bits, size_bits;
3697 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3698 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3699 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3700 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3701 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3704 debug_printf ("Process record: Advanced SIMD load/store\n");
3706 /* Load/store single structure. */
3707 if (bit (aarch64_insn_r->aarch64_insn, 24))
3709 uint8_t sindex, scale, selem, esize, replicate = 0;
3710 scale = opcode_bits >> 2;
3711 selem = ((opcode_bits & 0x02) |
3712 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3716 if (size_bits & 0x01)
3717 return AARCH64_RECORD_UNKNOWN;
3720 if ((size_bits >> 1) & 0x01)
3721 return AARCH64_RECORD_UNKNOWN;
3722 if (size_bits & 0x01)
3724 if (!((opcode_bits >> 1) & 0x01))
3727 return AARCH64_RECORD_UNKNOWN;
3731 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3738 return AARCH64_RECORD_UNKNOWN;
3744 for (sindex = 0; sindex < selem; sindex++)
3746 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3747 reg_rt = (reg_rt + 1) % 32;
3751 for (sindex = 0; sindex < selem; sindex++)
3753 if (bit (aarch64_insn_r->aarch64_insn, 22))
3754 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3757 record_buf_mem[mem_index++] = esize / 8;
3758 record_buf_mem[mem_index++] = address + addr_offset;
3760 addr_offset = addr_offset + (esize / 8);
3761 reg_rt = (reg_rt + 1) % 32;
3765 /* Load/store multiple structure. */
3768 uint8_t selem, esize, rpt, elements;
3769 uint8_t eindex, rindex;
3771 esize = 8 << size_bits;
3772 if (bit (aarch64_insn_r->aarch64_insn, 30))
3773 elements = 128 / esize;
3775 elements = 64 / esize;
3777 switch (opcode_bits)
3779 /*LD/ST4 (4 Registers). */
3784 /*LD/ST1 (4 Registers). */
3789 /*LD/ST3 (3 Registers). */
3794 /*LD/ST1 (3 Registers). */
3799 /*LD/ST1 (1 Register). */
3804 /*LD/ST2 (2 Registers). */
3809 /*LD/ST1 (2 Registers). */
3815 return AARCH64_RECORD_UNSUPPORTED;
3818 for (rindex = 0; rindex < rpt; rindex++)
3819 for (eindex = 0; eindex < elements; eindex++)
3821 uint8_t reg_tt, sindex;
3822 reg_tt = (reg_rt + rindex) % 32;
3823 for (sindex = 0; sindex < selem; sindex++)
3825 if (bit (aarch64_insn_r->aarch64_insn, 22))
3826 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3829 record_buf_mem[mem_index++] = esize / 8;
3830 record_buf_mem[mem_index++] = address + addr_offset;
3832 addr_offset = addr_offset + (esize / 8);
3833 reg_tt = (reg_tt + 1) % 32;
3838 if (bit (aarch64_insn_r->aarch64_insn, 23))
3839 record_buf[reg_index++] = reg_rn;
3841 aarch64_insn_r->reg_rec_count = reg_index;
3842 aarch64_insn_r->mem_rec_count = mem_index / 2;
3843 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3845 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3847 return AARCH64_RECORD_SUCCESS;
3850 /* Record handler for load and store instructions. */
3853 aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3855 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3856 uint8_t insn_bit23, insn_bit21;
3857 uint8_t opc, size_bits, ld_flag, vector_flag;
3858 uint32_t reg_rn, reg_rt, reg_rt2;
3859 uint64_t datasize, offset;
3860 uint32_t record_buf[8];
3861 uint64_t record_buf_mem[8];
3864 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3865 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3866 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3867 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3868 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3869 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3870 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3871 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3872 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3873 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3874 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3876 /* Load/store exclusive. */
3877 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3880 debug_printf ("Process record: load/store exclusive\n");
3884 record_buf[0] = reg_rt;
3885 aarch64_insn_r->reg_rec_count = 1;
3888 record_buf[1] = reg_rt2;
3889 aarch64_insn_r->reg_rec_count = 2;
3895 datasize = (8 << size_bits) * 2;
3897 datasize = (8 << size_bits);
3898 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3900 record_buf_mem[0] = datasize / 8;
3901 record_buf_mem[1] = address;
3902 aarch64_insn_r->mem_rec_count = 1;
3905 /* Save register rs. */
3906 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3907 aarch64_insn_r->reg_rec_count = 1;
3911 /* Load register (literal) instructions decoding. */
3912 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3915 debug_printf ("Process record: load register (literal)\n");
3917 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3919 record_buf[0] = reg_rt;
3920 aarch64_insn_r->reg_rec_count = 1;
3922 /* All types of load/store pair instructions decoding. */
3923 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3926 debug_printf ("Process record: load/store pair\n");
3932 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3933 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3937 record_buf[0] = reg_rt;
3938 record_buf[1] = reg_rt2;
3940 aarch64_insn_r->reg_rec_count = 2;
3945 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3947 size_bits = size_bits >> 1;
3948 datasize = 8 << (2 + size_bits);
3949 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3950 offset = offset << (2 + size_bits);
3951 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3953 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3955 if (imm7_off & 0x40)
3956 address = address - offset;
3958 address = address + offset;
3961 record_buf_mem[0] = datasize / 8;
3962 record_buf_mem[1] = address;
3963 record_buf_mem[2] = datasize / 8;
3964 record_buf_mem[3] = address + (datasize / 8);
3965 aarch64_insn_r->mem_rec_count = 2;
3967 if (bit (aarch64_insn_r->aarch64_insn, 23))
3968 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3970 /* Load/store register (unsigned immediate) instructions. */
3971 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3973 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3983 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3985 /* PRFM (immediate) */
3986 return AARCH64_RECORD_SUCCESS;
3988 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3990 /* LDRSW (immediate) */
4004 debug_printf ("Process record: load/store (unsigned immediate):"
4005 " size %x V %d opc %x\n", size_bits, vector_flag,
4011 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4012 datasize = 8 << size_bits;
4013 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4015 offset = offset << size_bits;
4016 address = address + offset;
4018 record_buf_mem[0] = datasize >> 3;
4019 record_buf_mem[1] = address;
4020 aarch64_insn_r->mem_rec_count = 1;
4025 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4027 record_buf[0] = reg_rt;
4028 aarch64_insn_r->reg_rec_count = 1;
4031 /* Load/store register (register offset) instructions. */
4032 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4033 && insn_bits10_11 == 0x02 && insn_bit21)
4036 debug_printf ("Process record: load/store (register offset)\n");
4037 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4044 if (size_bits != 0x03)
4047 return AARCH64_RECORD_UNKNOWN;
4051 ULONGEST reg_rm_val;
4053 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4054 bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
4055 if (bit (aarch64_insn_r->aarch64_insn, 12))
4056 offset = reg_rm_val << size_bits;
4058 offset = reg_rm_val;
4059 datasize = 8 << size_bits;
4060 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4062 address = address + offset;
4063 record_buf_mem[0] = datasize >> 3;
4064 record_buf_mem[1] = address;
4065 aarch64_insn_r->mem_rec_count = 1;
4070 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4072 record_buf[0] = reg_rt;
4073 aarch64_insn_r->reg_rec_count = 1;
4076 /* Load/store register (immediate and unprivileged) instructions. */
4077 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4082 debug_printf ("Process record: load/store "
4083 "(immediate and unprivileged)\n");
4085 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4092 if (size_bits != 0x03)
4095 return AARCH64_RECORD_UNKNOWN;
4100 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4101 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4102 datasize = 8 << size_bits;
4103 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4105 if (insn_bits10_11 != 0x01)
4107 if (imm9_off & 0x0100)
4108 address = address - offset;
4110 address = address + offset;
4112 record_buf_mem[0] = datasize >> 3;
4113 record_buf_mem[1] = address;
4114 aarch64_insn_r->mem_rec_count = 1;
4119 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4121 record_buf[0] = reg_rt;
4122 aarch64_insn_r->reg_rec_count = 1;
4124 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
4125 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4127 /* Advanced SIMD load/store instructions. */
4129 return aarch64_record_asimd_load_store (aarch64_insn_r);
4131 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4133 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4135 return AARCH64_RECORD_SUCCESS;
4138 /* Record handler for data processing SIMD and floating point instructions. */
4141 aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4143 uint8_t insn_bit21, opcode, rmode, reg_rd;
4144 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4145 uint8_t insn_bits11_14;
4146 uint32_t record_buf[2];
4148 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4149 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4150 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4151 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4152 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4153 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4154 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4155 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4156 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4159 debug_printf ("Process record: data processing SIMD/FP: ");
4161 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4163 /* Floating point - fixed point conversion instructions. */
4167 debug_printf ("FP - fixed point conversion");
4169 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4170 record_buf[0] = reg_rd;
4172 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4174 /* Floating point - conditional compare instructions. */
4175 else if (insn_bits10_11 == 0x01)
4178 debug_printf ("FP - conditional compare");
4180 record_buf[0] = AARCH64_CPSR_REGNUM;
4182 /* Floating point - data processing (2-source) and
4183 conditional select instructions. */
4184 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4187 debug_printf ("FP - DP (2-source)");
4189 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4191 else if (insn_bits10_11 == 0x00)
4193 /* Floating point - immediate instructions. */
4194 if ((insn_bits12_15 & 0x01) == 0x01
4195 || (insn_bits12_15 & 0x07) == 0x04)
4198 debug_printf ("FP - immediate");
4199 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4201 /* Floating point - compare instructions. */
4202 else if ((insn_bits12_15 & 0x03) == 0x02)
4205 debug_printf ("FP - immediate");
4206 record_buf[0] = AARCH64_CPSR_REGNUM;
4208 /* Floating point - integer conversions instructions. */
4209 else if (insn_bits12_15 == 0x00)
4211 /* Convert float to integer instruction. */
4212 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4215 debug_printf ("float to int conversion");
4217 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4219 /* Convert integer to float instruction. */
4220 else if ((opcode >> 1) == 0x01 && !rmode)
4223 debug_printf ("int to float conversion");
4225 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4227 /* Move float to integer instruction. */
4228 else if ((opcode >> 1) == 0x03)
4231 debug_printf ("move float to int");
4233 if (!(opcode & 0x01))
4234 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4236 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4239 return AARCH64_RECORD_UNKNOWN;
4242 return AARCH64_RECORD_UNKNOWN;
4245 return AARCH64_RECORD_UNKNOWN;
4247 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4250 debug_printf ("SIMD copy");
4252 /* Advanced SIMD copy instructions. */
4253 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4254 && !bit (aarch64_insn_r->aarch64_insn, 15)
4255 && bit (aarch64_insn_r->aarch64_insn, 10))
4257 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4258 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4260 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4263 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4265 /* All remaining floating point or advanced SIMD instructions. */
4269 debug_printf ("all remain");
4271 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4275 debug_printf ("\n");
4277 aarch64_insn_r->reg_rec_count++;
4278 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4279 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4281 return AARCH64_RECORD_SUCCESS;
4284 /* Decodes insns type and invokes its record handler. */
4287 aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4289 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4291 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4292 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4293 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4294 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4296 /* Data processing - immediate instructions. */
4297 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4298 return aarch64_record_data_proc_imm (aarch64_insn_r);
4300 /* Branch, exception generation and system instructions. */
4301 if (ins_bit26 && !ins_bit27 && ins_bit28)
4302 return aarch64_record_branch_except_sys (aarch64_insn_r);
4304 /* Load and store instructions. */
4305 if (!ins_bit25 && ins_bit27)
4306 return aarch64_record_load_store (aarch64_insn_r);
4308 /* Data processing - register instructions. */
4309 if (ins_bit25 && !ins_bit26 && ins_bit27)
4310 return aarch64_record_data_proc_reg (aarch64_insn_r);
4312 /* Data processing - SIMD and floating point instructions. */
4313 if (ins_bit25 && ins_bit26 && ins_bit27)
4314 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4316 return AARCH64_RECORD_UNSUPPORTED;
4319 /* Cleans up local record registers and memory allocations. */
4322 deallocate_reg_mem (insn_decode_record *record)
4324 xfree (record->aarch64_regs);
4325 xfree (record->aarch64_mems);
4329 namespace selftests {
4332 aarch64_process_record_test (void)
4334 struct gdbarch_info info;
4337 gdbarch_info_init (&info);
4338 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4340 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4341 SELF_CHECK (gdbarch != NULL);
4343 insn_decode_record aarch64_record;
4345 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4346 aarch64_record.regcache = NULL;
4347 aarch64_record.this_addr = 0;
4348 aarch64_record.gdbarch = gdbarch;
4350 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4351 aarch64_record.aarch64_insn = 0xf9800020;
4352 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4353 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4354 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4355 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4357 deallocate_reg_mem (&aarch64_record);
4360 } // namespace selftests
4361 #endif /* GDB_SELF_TEST */
4363 /* Parse the current instruction and record the values of the registers and
4364 memory that will be changed in current instruction to record_arch_list
4365 return -1 if something is wrong. */
4368 aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4369 CORE_ADDR insn_addr)
4371 uint32_t rec_no = 0;
4372 uint8_t insn_size = 4;
4374 gdb_byte buf[insn_size];
4375 insn_decode_record aarch64_record;
4377 memset (&buf[0], 0, insn_size);
4378 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4379 target_read_memory (insn_addr, &buf[0], insn_size);
4380 aarch64_record.aarch64_insn
4381 = (uint32_t) extract_unsigned_integer (&buf[0],
4383 gdbarch_byte_order (gdbarch));
4384 aarch64_record.regcache = regcache;
4385 aarch64_record.this_addr = insn_addr;
4386 aarch64_record.gdbarch = gdbarch;
4388 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4389 if (ret == AARCH64_RECORD_UNSUPPORTED)
4391 printf_unfiltered (_("Process record does not support instruction "
4392 "0x%0x at address %s.\n"),
4393 aarch64_record.aarch64_insn,
4394 paddress (gdbarch, insn_addr));
4400 /* Record registers. */
4401 record_full_arch_list_add_reg (aarch64_record.regcache,
4403 /* Always record register CPSR. */
4404 record_full_arch_list_add_reg (aarch64_record.regcache,
4405 AARCH64_CPSR_REGNUM);
4406 if (aarch64_record.aarch64_regs)
4407 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4408 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4409 aarch64_record.aarch64_regs[rec_no]))
4412 /* Record memories. */
4413 if (aarch64_record.aarch64_mems)
4414 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4415 if (record_full_arch_list_add_mem
4416 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4417 aarch64_record.aarch64_mems[rec_no].len))
4420 if (record_full_arch_list_add_end ())
4424 deallocate_reg_mem (&aarch64_record);