1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2013 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-tdep.h"
31 #include "aarch64-linux-tdep.h"
32 #include "elf/common.h"
34 #include <sys/ptrace.h>
35 #include <sys/utsname.h>
39 #include "features/aarch64.c"
41 /* Defines ps_err_e, struct ps_prochandle. */
42 #include "gdb_proc_service.h"
45 #define TRAP_HWBKPT 0x0004
48 /* On GNU/Linux, threads are implemented as pseudo-processes, in which
49 case we may be tracing more than one process at a time. In that
50 case, inferior_ptid will contain the main process ID and the
51 individual thread (process) ID. get_thread_id () is used to get
52 the thread id if it's available, and the process id otherwise. */
55 get_thread_id (ptid_t ptid)
57 int tid = TIDGET (ptid);
64 /* Macro definitions, data structures, and code for the hardware
65 breakpoint and hardware watchpoint support follow. We use the
66 following abbreviations throughout the code:
72 /* Maximum number of hardware breakpoint and watchpoint registers.
73 Neither of these values may exceed the width of dr_changed_t
76 #define AARCH64_HBP_MAX_NUM 16
77 #define AARCH64_HWP_MAX_NUM 16
79 /* Alignment requirement in bytes for addresses written to
80 hardware breakpoint and watchpoint value registers.
82 A ptrace call attempting to set an address that does not meet the
83 alignment criteria will fail. Limited support has been provided in
84 this port for unaligned watchpoints, such that from a GDB user
85 perspective, an unaligned watchpoint may be requested.
87 This is achieved by minimally enlarging the watched area to meet the
88 alignment requirement, and if necessary, splitting the watchpoint
89 over several hardware watchpoint registers. */
91 #define AARCH64_HBP_ALIGNMENT 4
92 #define AARCH64_HWP_ALIGNMENT 8
94 /* The maximum length of a memory region that can be watched by one
95 hardware watchpoint register. */
97 #define AARCH64_HWP_MAX_LEN_PER_REG 8
99 /* ptrace hardware breakpoint resource info is formatted as follows:
102 +---------------+--------------+---------------+---------------+
103 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
104 +---------------+--------------+---------------+---------------+ */
107 /* Macros to extract fields from the hardware debug information word. */
108 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
109 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
111 /* Macro for the expected version of the ARMv8-A debug architecture. */
112 #define AARCH64_DEBUG_ARCH_V8 0x6
114 /* Number of hardware breakpoints/watchpoints the target supports.
115 They are initialized with values obtained via the ptrace calls
116 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
118 static int aarch64_num_bp_regs;
119 static int aarch64_num_wp_regs;
121 /* Debugging of hardware breakpoint/watchpoint support. */
123 static int debug_hw_points;
125 /* Each bit of a variable of this type is used to indicate whether a
126 hardware breakpoint or watchpoint setting has been changed since
129 Bit N corresponds to the Nth hardware breakpoint or watchpoint
130 setting which is managed in aarch64_debug_reg_state, where N is
131 valid between 0 and the total number of the hardware breakpoint or
132 watchpoint debug registers minus 1.
134 When bit N is 1, the corresponding breakpoint or watchpoint setting
135 has changed, and therefore the corresponding hardware debug
136 register needs to be updated via the ptrace interface.
138 In the per-thread arch-specific data area, we define two such
139 variables for per-thread hardware breakpoint and watchpoint
140 settings respectively.
142 This type is part of the mechanism which helps reduce the number of
143 ptrace calls to the kernel, i.e. avoid asking the kernel to write
144 to the debug registers with unchanged values. */
146 typedef unsigned LONGEST dr_changed_t;
148 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
150 #define DR_MARK_ALL_CHANGED(x, m) \
153 gdb_assert (sizeof ((x)) * 8 >= (m)); \
154 (x) = (((dr_changed_t)1 << (m)) - 1); \
157 #define DR_MARK_N_CHANGED(x, n) \
160 (x) |= ((dr_changed_t)1 << (n)); \
163 #define DR_CLEAR_CHANGED(x) \
169 #define DR_HAS_CHANGED(x) ((x) != 0)
170 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
172 /* Structure for managing the hardware breakpoint/watchpoint resources.
173 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
174 content, and DR_REF_COUNT_* counts the numbers of references to the
175 corresponding bp/wp, by which way the limited hardware resources
176 are not wasted on duplicated bp/wp settings (though so far gdb has
177 done a good job by not sending duplicated bp/wp requests). */
179 struct aarch64_debug_reg_state
181 /* hardware breakpoint */
182 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
183 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
184 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
186 /* hardware watchpoint */
187 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
188 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
189 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
192 /* Clear the reference counts and forget everything we knew about the
196 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
200 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
202 state->dr_addr_bp[i] = 0;
203 state->dr_ctrl_bp[i] = 0;
204 state->dr_ref_count_bp[i] = 0;
207 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
209 state->dr_addr_wp[i] = 0;
210 state->dr_ctrl_wp[i] = 0;
211 state->dr_ref_count_wp[i] = 0;
215 /* Per-inferior data key. */
216 static const struct inferior_data *aarch64_inferior_data;
218 /* Per-inferior data. */
219 struct aarch64_inferior_data
221 /* Copy of AArch64 hardware debug registers for performance reasons. */
222 struct aarch64_debug_reg_state state;
225 /* Per-inferior hook for register_inferior_data_with_cleanup. */
228 aarch64_inferior_data_cleanup (struct inferior *inf, void *arg)
230 struct aarch64_inferior_data *inf_data = arg;
235 /* Get data specific for INFERIOR_PTID LWP. Return special data area
236 for processes being detached. */
238 static struct aarch64_inferior_data *
239 aarch64_inferior_data_get (void)
241 struct inferior *inf = current_inferior ();
242 struct aarch64_inferior_data *inf_data;
244 inf_data = inferior_data (inf, aarch64_inferior_data);
245 if (inf_data == NULL)
247 inf_data = xzalloc (sizeof (*inf_data));
248 set_inferior_data (inf, aarch64_inferior_data, inf_data);
254 /* Get debug registers state for INFERIOR_PTID, see
255 aarch64_inferior_data_get. */
257 static struct aarch64_debug_reg_state *
258 aarch64_get_debug_reg_state (void)
260 return &aarch64_inferior_data_get ()->state;
263 /* Per-thread arch-specific data we want to keep. */
267 /* When bit N is 1, it indicates the Nth hardware breakpoint or
268 watchpoint register pair needs to be updated when the thread is
269 resumed; see aarch64_linux_prepare_to_resume. */
270 dr_changed_t dr_changed_bp;
271 dr_changed_t dr_changed_wp;
274 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
275 registers with data from *STATE. */
278 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
279 int tid, int watchpoint)
283 struct user_hwdebug_state regs;
284 const CORE_ADDR *addr;
285 const unsigned int *ctrl;
287 iov.iov_base = ®s;
288 iov.iov_len = sizeof (regs);
289 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
290 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
291 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
293 for (i = 0; i < count; i++)
295 regs.dbg_regs[i].addr = addr[i];
296 regs.dbg_regs[i].ctrl = ctrl[i];
299 if (ptrace (PTRACE_SETREGSET, tid,
300 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
302 error (_("Unexpected error setting hardware debug registers"));
305 struct aarch64_dr_update_callback_param
311 /* Callback for linux_nat_iterate_watchpoint_lwps. Records the
312 information about the change of one hardware breakpoint/watchpoint
313 setting for the thread LWP.
314 The information is passed in via PTR.
315 N.B. The actual updating of hardware debug registers is not
316 carried out until the moment the thread is resumed. */
319 debug_reg_change_callback (struct lwp_info *lwp, void *ptr)
321 struct aarch64_dr_update_callback_param *param_p
322 = (struct aarch64_dr_update_callback_param *) ptr;
323 int pid = get_thread_id (lwp->ptid);
324 int idx = param_p->idx;
325 int is_watchpoint = param_p->is_watchpoint;
326 struct arch_lwp_info *info = lwp->arch_private;
327 dr_changed_t *dr_changed_ptr;
328 dr_changed_t dr_changed;
331 info = lwp->arch_private = XCNEW (struct arch_lwp_info);
335 fprintf_unfiltered (gdb_stdlog,
336 "debug_reg_change_callback: \n\tOn entry:\n");
337 fprintf_unfiltered (gdb_stdlog,
338 "\tpid%d, dr_changed_bp=0x%s, "
339 "dr_changed_wp=0x%s\n",
340 pid, phex (info->dr_changed_bp, 8),
341 phex (info->dr_changed_wp, 8));
344 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
345 : &info->dr_changed_bp;
346 dr_changed = *dr_changed_ptr;
349 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
350 : aarch64_num_bp_regs)));
352 /* The actual update is done later just before resuming the lwp,
353 we just mark that one register pair needs updating. */
354 DR_MARK_N_CHANGED (dr_changed, idx);
355 *dr_changed_ptr = dr_changed;
357 /* If the lwp isn't stopped, force it to momentarily pause, so
358 we can update its debug registers. */
360 linux_stop_lwp (lwp);
364 fprintf_unfiltered (gdb_stdlog,
365 "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, "
366 "dr_changed_wp=0x%s\n",
367 pid, phex (info->dr_changed_bp, 8),
368 phex (info->dr_changed_wp, 8));
371 /* Continue the iteration. */
375 /* Notify each thread that their IDXth breakpoint/watchpoint register
376 pair needs to be updated. The message will be recorded in each
377 thread's arch-specific data area, the actual updating will be done
378 when the thread is resumed. */
381 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
382 int is_watchpoint, unsigned int idx)
384 struct aarch64_dr_update_callback_param param;
386 param.is_watchpoint = is_watchpoint;
389 linux_nat_iterate_watchpoint_lwps (debug_reg_change_callback,
393 /* Print the values of the cached breakpoint/watchpoint registers. */
396 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
397 const char *func, CORE_ADDR addr,
402 fprintf_unfiltered (gdb_stdlog, "%s", func);
404 fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)",
405 (unsigned long) addr, len,
406 type == hw_write ? "hw-write-watchpoint"
407 : (type == hw_read ? "hw-read-watchpoint"
408 : (type == hw_access ? "hw-access-watchpoint"
409 : (type == hw_execute ? "hw-breakpoint"
411 fprintf_unfiltered (gdb_stdlog, ":\n");
413 fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n");
414 for (i = 0; i < aarch64_num_bp_regs; i++)
415 fprintf_unfiltered (gdb_stdlog,
416 "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
417 i, state->dr_addr_bp[i],
418 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
420 fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n");
421 for (i = 0; i < aarch64_num_wp_regs; i++)
422 fprintf_unfiltered (gdb_stdlog,
423 "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
424 i, state->dr_addr_wp[i],
425 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
428 /* Fill GDB's register array with the general-purpose register values
429 from the current thread. */
432 fetch_gregs_from_thread (struct regcache *regcache)
438 tid = get_thread_id (inferior_ptid);
440 iovec.iov_base = ®s;
441 iovec.iov_len = sizeof (regs);
443 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
445 perror_with_name (_("Unable to fetch general registers."));
447 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
448 regcache_raw_supply (regcache, regno,
449 (char *) ®s[regno - AARCH64_X0_REGNUM]);
452 /* Store to the current thread the valid general-purpose register
453 values in the GDB's register array. */
456 store_gregs_to_thread (const struct regcache *regcache)
462 tid = get_thread_id (inferior_ptid);
464 iovec.iov_base = ®s;
465 iovec.iov_len = sizeof (regs);
467 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
469 perror_with_name (_("Unable to fetch general registers."));
471 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
472 if (REG_VALID == regcache_register_status (regcache, regno))
473 regcache_raw_collect (regcache, regno,
474 (char *) ®s[regno - AARCH64_X0_REGNUM]);
476 ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
478 perror_with_name (_("Unable to store general registers."));
481 /* Fill GDB's register array with the fp/simd register values
482 from the current thread. */
485 fetch_fpregs_from_thread (struct regcache *regcache)
491 tid = get_thread_id (inferior_ptid);
493 iovec.iov_base = ®s;
494 iovec.iov_len = sizeof (regs);
496 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
498 perror_with_name (_("Unable to fetch FP/SIMD registers."));
500 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
501 regcache_raw_supply (regcache, regno,
502 (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
504 regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
505 regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
508 /* Store to the current thread the valid fp/simd register
509 values in the GDB's register array. */
512 store_fpregs_to_thread (const struct regcache *regcache)
518 tid = get_thread_id (inferior_ptid);
520 iovec.iov_base = ®s;
521 iovec.iov_len = sizeof (regs);
523 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
525 perror_with_name (_("Unable to fetch FP/SIMD registers."));
527 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
528 if (REG_VALID == regcache_register_status (regcache, regno))
529 regcache_raw_collect (regcache, regno,
530 (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
532 if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM))
533 regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
534 if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM))
535 regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
537 ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
539 perror_with_name (_("Unable to store FP/SIMD registers."));
542 /* Implement the "to_fetch_register" target_ops method. */
545 aarch64_linux_fetch_inferior_registers (struct target_ops *ops,
546 struct regcache *regcache,
551 fetch_gregs_from_thread (regcache);
552 fetch_fpregs_from_thread (regcache);
554 else if (regno < AARCH64_V0_REGNUM)
555 fetch_gregs_from_thread (regcache);
557 fetch_fpregs_from_thread (regcache);
560 /* Implement the "to_store_register" target_ops method. */
563 aarch64_linux_store_inferior_registers (struct target_ops *ops,
564 struct regcache *regcache,
569 store_gregs_to_thread (regcache);
570 store_fpregs_to_thread (regcache);
572 else if (regno < AARCH64_V0_REGNUM)
573 store_gregs_to_thread (regcache);
575 store_fpregs_to_thread (regcache);
578 /* Fill register REGNO (if it is a general-purpose register) in
579 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
580 do this for all registers. */
583 fill_gregset (const struct regcache *regcache,
584 gdb_gregset_t *gregsetp, int regno)
586 gdb_byte *gregs_buf = (gdb_byte *) gregsetp;
589 for (i = AARCH64_X0_REGNUM; i <= AARCH64_CPSR_REGNUM; i++)
590 if (regno == -1 || regno == i)
591 regcache_raw_collect (regcache, i,
592 gregs_buf + X_REGISTER_SIZE
593 * (i - AARCH64_X0_REGNUM));
596 /* Fill GDB's register array with the general-purpose register values
600 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
602 aarch64_linux_supply_gregset (regcache, (const gdb_byte *) gregsetp);
605 /* Fill register REGNO (if it is a floating-point register) in
606 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
607 do this for all registers. */
610 fill_fpregset (const struct regcache *regcache,
611 gdb_fpregset_t *fpregsetp, int regno)
613 gdb_byte *fpregs_buf = (gdb_byte *) fpregsetp;
616 for (i = AARCH64_V0_REGNUM; i <= AARCH64_V31_REGNUM; i++)
617 if (regno == -1 || regno == i)
618 regcache_raw_collect (regcache, i,
619 fpregs_buf + V_REGISTER_SIZE
620 * (i - AARCH64_V0_REGNUM));
622 if (regno == -1 || regno == AARCH64_FPSR_REGNUM)
623 regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM,
624 fpregs_buf + V_REGISTER_SIZE * 32);
626 if (regno == -1 || regno == AARCH64_FPCR_REGNUM)
627 regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM,
628 fpregs_buf + V_REGISTER_SIZE * 32 + 4);
631 /* Fill GDB's register array with the floating-point register values
635 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
637 aarch64_linux_supply_fpregset (regcache, (const gdb_byte *) fpregsetp);
640 /* Called when resuming a thread.
641 The hardware debug registers are updated when there is any change. */
644 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
646 struct arch_lwp_info *info = lwp->arch_private;
648 /* NULL means this is the main thread still going through the shell,
649 or, no watchpoint has been set yet. In that case, there's
654 if (DR_HAS_CHANGED (info->dr_changed_bp)
655 || DR_HAS_CHANGED (info->dr_changed_wp))
657 int tid = GET_LWP (lwp->ptid);
658 struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state ();
661 fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid);
664 if (DR_HAS_CHANGED (info->dr_changed_wp))
666 aarch64_linux_set_debug_regs (state, tid, 1);
667 DR_CLEAR_CHANGED (info->dr_changed_wp);
671 if (DR_HAS_CHANGED (info->dr_changed_bp))
673 aarch64_linux_set_debug_regs (state, tid, 0);
674 DR_CLEAR_CHANGED (info->dr_changed_bp);
680 aarch64_linux_new_thread (struct lwp_info *lp)
682 struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
684 /* Mark that all the hardware breakpoint/watchpoint register pairs
685 for this thread need to be initialized. */
686 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
687 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
689 lp->arch_private = info;
693 /* Called by libthread_db. Returns a pointer to the thread local
694 storage (or its descriptor). */
697 ps_get_thread_area (const struct ps_prochandle *ph,
698 lwpid_t lwpid, int idx, void **base)
703 iovec.iov_base = ®
704 iovec.iov_len = sizeof (reg);
706 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
709 /* IDX is the bias from the thread pointer to the beginning of the
710 thread descriptor. It has to be subtracted due to implementation
711 quirks in libthread_db. */
712 *base = (void *) (reg - idx);
718 /* Get the hardware debug register capacity information. */
721 aarch64_linux_get_debug_reg_capacity (void)
725 struct user_hwdebug_state dreg_state;
727 tid = get_thread_id (inferior_ptid);
728 iov.iov_base = &dreg_state;
729 iov.iov_len = sizeof (dreg_state);
731 /* Get hardware watchpoint register info. */
732 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
733 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
735 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
736 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
738 warning (_("Unexpected number of hardware watchpoint registers"
739 " reported by ptrace, got %d, expected %d."),
740 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
741 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
746 warning (_("Unable to determine the number of hardware watchpoints"
748 aarch64_num_wp_regs = 0;
751 /* Get hardware breakpoint register info. */
752 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
753 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
755 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
756 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
758 warning (_("Unexpected number of hardware breakpoint registers"
759 " reported by ptrace, got %d, expected %d."),
760 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
761 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
766 warning (_("Unable to determine the number of hardware breakpoints"
768 aarch64_num_bp_regs = 0;
772 static void (*super_post_startup_inferior) (ptid_t ptid);
774 /* Implement the "to_post_startup_inferior" target_ops method. */
777 aarch64_linux_child_post_startup_inferior (ptid_t ptid)
779 struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state ();
781 aarch64_init_debug_reg_state (state);
782 aarch64_linux_get_debug_reg_capacity ();
783 super_post_startup_inferior (ptid);
786 /* Implement the "to_read_description" target_ops method. */
788 static const struct target_desc *
789 aarch64_linux_read_description (struct target_ops *ops)
791 initialize_tdesc_aarch64 ();
792 return tdesc_aarch64;
795 /* Given the (potentially unaligned) watchpoint address in ADDR and
796 length in LEN, return the aligned address and aligned length in
797 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
798 aligned address and length will be valid values to write to the
799 hardware watchpoint value and control registers.
801 The given watchpoint may get truncated if more than one hardware
802 register is needed to cover the watched region. *NEXT_ADDR_P
803 and *NEXT_LEN_P, if non-NULL, will return the address and length
804 of the remaining part of the watchpoint (which can be processed
805 by calling this routine again to generate another aligned address
808 See the comment above the function of the same name in
809 gdbserver/linux-aarch64-low.c for more information. */
812 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
813 int *aligned_len_p, CORE_ADDR *next_addr_p,
818 CORE_ADDR aligned_addr;
819 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
820 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
822 /* As assumed by the algorithm. */
823 gdb_assert (alignment == max_wp_len);
828 /* Address to be put into the hardware watchpoint value register
830 offset = addr & (alignment - 1);
831 aligned_addr = addr - offset;
833 gdb_assert (offset >= 0 && offset < alignment);
834 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
835 gdb_assert (offset + len > 0);
837 if (offset + len >= max_wp_len)
839 /* Need more than one watchpoint registers; truncate it at the
840 alignment boundary. */
841 aligned_len = max_wp_len;
842 len -= (max_wp_len - offset);
843 addr += (max_wp_len - offset);
844 gdb_assert ((addr & (alignment - 1)) == 0);
848 /* Find the smallest valid length that is large enough to
849 accommodate this watchpoint. */
850 static const unsigned char
851 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
852 { 1, 2, 4, 4, 8, 8, 8, 8 };
854 aligned_len = aligned_len_array[offset + len - 1];
860 *aligned_addr_p = aligned_addr;
862 *aligned_len_p = aligned_len;
869 /* Returns the number of hardware watchpoints of type TYPE that we can
870 set. Value is positive if we can set CNT watchpoints, zero if
871 setting watchpoints of type TYPE is not supported, and negative if
872 CNT is more than the maximum number of watchpoints of type TYPE
873 that we can support. TYPE is one of bp_hardware_watchpoint,
874 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
875 CNT is the number of such watchpoints used so far (including this
876 one). OTHERTYPE is non-zero if other types of watchpoints are
879 We always return 1 here because we don't have enough information
880 about possible overlap of addresses that they want to watch. As an
881 extreme example, consider the case where all the watchpoints watch
882 the same address and the same region length: then we can handle a
883 virtually unlimited number of watchpoints, due to debug register
884 sharing implemented via reference counts. */
887 aarch64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
892 /* ptrace expects control registers to be formatted as follows:
895 +--------------------------------+----------+------+------+----+
896 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
897 +--------------------------------+----------+------+------+----+
899 The TYPE field is ignored for breakpoints. */
901 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
902 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
904 /* Utility function that returns the length in bytes of a watchpoint
905 according to the content of a hardware debug control register CTRL.
906 Note that the kernel currently only supports the following Byte
907 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
908 that for a hardware watchpoint, its valid length can only be 1
909 byte, 2 bytes, 4 bytes or 8 bytes. */
911 static inline unsigned int
912 aarch64_watchpoint_length (unsigned int ctrl)
914 switch (DR_CONTROL_LENGTH (ctrl))
929 /* Given the hardware breakpoint or watchpoint type TYPE and its
930 length LEN, return the expected encoding for a hardware
931 breakpoint/watchpoint control register. */
934 aarch64_point_encode_ctrl_reg (int type, int len)
936 unsigned int ctrl, ttype;
954 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
959 ctrl |= ((1 << len) - 1) << 5;
961 ctrl |= (2 << 1) | 1;
966 /* Addresses to be written to the hardware breakpoint and watchpoint
967 value registers need to be aligned; the alignment is 4-byte and
968 8-type respectively. Linux kernel rejects any non-aligned address
969 it receives from the related ptrace call. Furthermore, the kernel
970 currently only supports the following Byte Address Select (BAS)
971 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
972 watchpoint to be accepted by the kernel (via ptrace call), its
973 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
974 Despite these limitations, the unaligned watchpoint is supported in
977 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
980 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
982 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
983 : AARCH64_HBP_ALIGNMENT;
985 if (addr & (alignment - 1))
988 if (len != 8 && len != 4 && len != 2 && len != 1)
994 /* Record the insertion of one breakpoint/watchpoint, as represented
995 by ADDR and CTRL, in the cached debug register state area *STATE. */
998 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
999 int type, CORE_ADDR addr, int len)
1001 int i, idx, num_regs, is_watchpoint;
1002 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
1003 CORE_ADDR *dr_addr_p;
1005 /* Set up state pointers. */
1006 is_watchpoint = (type != hw_execute);
1007 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
1010 num_regs = aarch64_num_wp_regs;
1011 dr_addr_p = state->dr_addr_wp;
1012 dr_ctrl_p = state->dr_ctrl_wp;
1013 dr_ref_count = state->dr_ref_count_wp;
1017 num_regs = aarch64_num_bp_regs;
1018 dr_addr_p = state->dr_addr_bp;
1019 dr_ctrl_p = state->dr_ctrl_bp;
1020 dr_ref_count = state->dr_ref_count_bp;
1023 ctrl = aarch64_point_encode_ctrl_reg (type, len);
1025 /* Find an existing or free register in our cache. */
1027 for (i = 0; i < num_regs; ++i)
1029 if ((dr_ctrl_p[i] & 1) == 0)
1031 gdb_assert (dr_ref_count[i] == 0);
1033 /* no break; continue hunting for an existing one. */
1035 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
1037 gdb_assert (dr_ref_count[i] != 0);
1047 /* Update our cache. */
1048 if ((dr_ctrl_p[idx] & 1) == 0)
1051 dr_addr_p[idx] = addr;
1052 dr_ctrl_p[idx] = ctrl;
1053 dr_ref_count[idx] = 1;
1054 /* Notify the change. */
1055 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
1059 /* existing entry */
1060 dr_ref_count[idx]++;
1066 /* Record the removal of one breakpoint/watchpoint, as represented by
1067 ADDR and CTRL, in the cached debug register state area *STATE. */
1070 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
1071 int type, CORE_ADDR addr, int len)
1073 int i, num_regs, is_watchpoint;
1074 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
1075 CORE_ADDR *dr_addr_p;
1077 /* Set up state pointers. */
1078 is_watchpoint = (type != hw_execute);
1079 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
1082 num_regs = aarch64_num_wp_regs;
1083 dr_addr_p = state->dr_addr_wp;
1084 dr_ctrl_p = state->dr_ctrl_wp;
1085 dr_ref_count = state->dr_ref_count_wp;
1089 num_regs = aarch64_num_bp_regs;
1090 dr_addr_p = state->dr_addr_bp;
1091 dr_ctrl_p = state->dr_ctrl_bp;
1092 dr_ref_count = state->dr_ref_count_bp;
1095 ctrl = aarch64_point_encode_ctrl_reg (type, len);
1097 /* Find the entry that matches the ADDR and CTRL. */
1098 for (i = 0; i < num_regs; ++i)
1099 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
1101 gdb_assert (dr_ref_count[i] != 0);
1109 /* Clear our cache. */
1110 if (--dr_ref_count[i] == 0)
1112 /* Clear the enable bit. */
1115 dr_ctrl_p[i] = ctrl;
1116 /* Notify the change. */
1117 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
1123 /* Implement insertion and removal of a single breakpoint. */
1126 aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert)
1128 struct aarch64_debug_reg_state *state;
1130 /* The hardware breakpoint on AArch64 should always be 4-byte
1132 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
1135 state = aarch64_get_debug_reg_state ();
1138 return aarch64_dr_state_insert_one_point (state, type, addr, len);
1140 return aarch64_dr_state_remove_one_point (state, type, addr, len);
1143 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
1144 Return 0 on success, -1 on failure. */
1147 aarch64_linux_insert_hw_breakpoint (struct gdbarch *gdbarch,
1148 struct bp_target_info *bp_tgt)
1151 CORE_ADDR addr = bp_tgt->placed_address;
1153 const int type = hw_execute;
1155 if (debug_hw_points)
1158 "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1159 (unsigned long) addr, len);
1161 ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */);
1163 if (debug_hw_points > 1)
1164 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1165 "insert_hw_watchpoint", addr, len, type);
1170 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
1171 Return 0 on success, -1 on failure. */
1174 aarch64_linux_remove_hw_breakpoint (struct gdbarch *gdbarch,
1175 struct bp_target_info *bp_tgt)
1178 CORE_ADDR addr = bp_tgt->placed_address;
1180 const int type = hw_execute;
1182 if (debug_hw_points)
1184 (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1185 (unsigned long) addr, len);
1187 ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */);
1189 if (debug_hw_points > 1)
1190 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1191 "remove_hw_watchpoint", addr, len, type);
1196 /* This is essentially the same as aarch64_handle_breakpoint, apart
1197 from that it is an aligned watchpoint to be handled. */
1200 aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len,
1203 struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state ();
1206 return aarch64_dr_state_insert_one_point (state, type, addr, len);
1208 return aarch64_dr_state_remove_one_point (state, type, addr, len);
1211 /* Insert/remove unaligned watchpoint by calling
1212 aarch64_align_watchpoint repeatedly until the whole watched region,
1213 as represented by ADDR and LEN, has been properly aligned and ready
1214 to be written to one or more hardware watchpoint registers.
1215 IS_INSERT indicates whether this is an insertion or a deletion.
1216 Return 0 if succeed. */
1219 aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len,
1222 struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state ();
1226 CORE_ADDR aligned_addr;
1227 int aligned_len, ret;
1229 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
1233 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
1236 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
1239 if (debug_hw_points)
1240 fprintf_unfiltered (gdb_stdlog,
1241 "handle_unaligned_watchpoint: is_insert: %d\n"
1242 " aligned_addr: 0x%08lx, aligned_len: %d\n"
1243 " next_addr: 0x%08lx, next_len: %d\n",
1244 is_insert, aligned_addr, aligned_len, addr, len);
1253 /* Implements insertion and removal of a single watchpoint. */
1256 aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert)
1258 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
1259 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
1261 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
1264 /* Implement the "to_insert_watchpoint" target_ops method.
1266 Insert a watchpoint to watch a memory region which starts at
1267 address ADDR and whose length is LEN bytes. Watch memory accesses
1268 of the type TYPE. Return 0 on success, -1 on failure. */
1271 aarch64_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
1272 struct expression *cond)
1276 if (debug_hw_points)
1277 fprintf_unfiltered (gdb_stdlog,
1278 "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1279 (unsigned long) addr, len);
1281 gdb_assert (type != hw_execute);
1283 ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */);
1285 if (debug_hw_points > 1)
1286 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1287 "insert_watchpoint", addr, len, type);
1292 /* Implement the "to_remove_watchpoint" target_ops method.
1293 Remove a watchpoint that watched the memory region which starts at
1294 address ADDR, whose length is LEN bytes, and for accesses of the
1295 type TYPE. Return 0 on success, -1 on failure. */
1298 aarch64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
1299 struct expression *cond)
1303 if (debug_hw_points)
1304 fprintf_unfiltered (gdb_stdlog,
1305 "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1306 (unsigned long) addr, len);
1308 gdb_assert (type != hw_execute);
1310 ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */);
1312 if (debug_hw_points > 1)
1313 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1314 "remove_watchpoint", addr, len, type);
1319 /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */
1322 aarch64_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1324 CORE_ADDR aligned_addr;
1326 /* Can not set watchpoints for zero or negative lengths. */
1330 /* Must have hardware watchpoint debug register(s). */
1331 if (aarch64_num_wp_regs == 0)
1334 /* We support unaligned watchpoint address and arbitrary length,
1335 as long as the size of the whole watched area after alignment
1336 doesn't exceed size of the total area that all watchpoint debug
1337 registers can watch cooperatively.
1339 This is a very relaxed rule, but unfortunately there are
1340 limitations, e.g. false-positive hits, due to limited support of
1341 hardware debug registers in the kernel. See comment above
1342 aarch64_align_watchpoint for more information. */
1344 aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1);
1345 if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG
1349 /* All tests passed so we are likely to be able to set the watchpoint.
1350 The reason that it is 'likely' rather than 'must' is because
1351 we don't check the current usage of the watchpoint registers, and
1352 there may not be enough registers available for this watchpoint.
1353 Ideally we should check the cached debug register state, however
1354 the checking is costly. */
1358 /* Implement the "to_stopped_data_address" target_ops method. */
1361 aarch64_linux_stopped_data_address (struct target_ops *target,
1366 struct aarch64_debug_reg_state *state;
1368 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
1371 /* This must be a hardware breakpoint. */
1372 if (siginfo.si_signo != SIGTRAP
1373 || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
1376 /* Check if the address matches any watched address. */
1377 state = aarch64_get_debug_reg_state ();
1378 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1380 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1381 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1382 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1384 if (state->dr_ref_count_wp[i]
1385 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1386 && addr_trap >= addr_watch
1387 && addr_trap < addr_watch + len)
1389 *addr_p = addr_trap;
1397 /* Implement the "to_stopped_by_watchpoint" target_ops method. */
1400 aarch64_linux_stopped_by_watchpoint (void)
1404 return aarch64_linux_stopped_data_address (¤t_target, &addr);
1407 /* Implement the "to_watchpoint_addr_within_range" target_ops method. */
1410 aarch64_linux_watchpoint_addr_within_range (struct target_ops *target,
1412 CORE_ADDR start, int length)
1414 return start <= addr && start + length - 1 >= addr;
1417 /* Define AArch64 maintenance commands. */
1420 add_show_debug_regs_command (void)
1422 /* A maintenance command to enable printing the internal DRi mirror
1424 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
1425 &debug_hw_points, _("\
1426 Set whether to show variables that mirror the AArch64 debug registers."), _("\
1427 Show whether to show variables that mirror the AArch64 debug registers."), _("\
1428 Use \"on\" to enable, \"off\" to disable.\n\
1429 If enabled, the debug registers values are shown when GDB inserts\n\
1430 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1431 triggers a breakpoint or watchpoint."),
1434 &maintenance_set_cmdlist,
1435 &maintenance_show_cmdlist);
1438 /* -Wmissing-prototypes. */
1439 void _initialize_aarch64_linux_nat (void);
1442 _initialize_aarch64_linux_nat (void)
1444 struct target_ops *t;
1446 /* Fill in the generic GNU/Linux methods. */
1447 t = linux_target ();
1449 add_show_debug_regs_command ();
1451 /* Add our register access methods. */
1452 t->to_fetch_registers = aarch64_linux_fetch_inferior_registers;
1453 t->to_store_registers = aarch64_linux_store_inferior_registers;
1455 t->to_read_description = aarch64_linux_read_description;
1457 t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint;
1458 t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint;
1459 t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint;
1460 t->to_region_ok_for_hw_watchpoint =
1461 aarch64_linux_region_ok_for_hw_watchpoint;
1462 t->to_insert_watchpoint = aarch64_linux_insert_watchpoint;
1463 t->to_remove_watchpoint = aarch64_linux_remove_watchpoint;
1464 t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint;
1465 t->to_stopped_data_address = aarch64_linux_stopped_data_address;
1466 t->to_watchpoint_addr_within_range =
1467 aarch64_linux_watchpoint_addr_within_range;
1468 if (aarch64_inferior_data == NULL)
1469 aarch64_inferior_data
1470 = register_inferior_data_with_cleanup (NULL,
1471 aarch64_inferior_data_cleanup);
1473 /* Override the GNU/Linux inferior startup hook. */
1474 super_post_startup_inferior = t->to_post_startup_inferior;
1475 t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior;
1477 /* Register the target. */
1478 linux_nat_add_target (t);
1479 linux_nat_set_new_thread (t, aarch64_linux_new_thread);
1480 linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume);