1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2013 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-tdep.h"
31 #include "aarch64-linux-tdep.h"
32 #include "elf/common.h"
34 #include <sys/ptrace.h>
35 #include <sys/utsname.h>
39 #include "features/aarch64.c"
41 /* Defines ps_err_e, struct ps_prochandle. */
42 #include "gdb_proc_service.h"
45 #define TRAP_HWBKPT 0x0004
48 /* On GNU/Linux, threads are implemented as pseudo-processes, in which
49 case we may be tracing more than one process at a time. In that
50 case, inferior_ptid will contain the main process ID and the
51 individual thread (process) ID. get_thread_id () is used to get
52 the thread id if it's available, and the process id otherwise. */
55 get_thread_id (ptid_t ptid)
57 int tid = TIDGET (ptid);
64 /* Macro definitions, data structures, and code for the hardware
65 breakpoint and hardware watchpoint support follow. We use the
66 following abbreviations throughout the code:
72 /* Maximum number of hardware breakpoint and watchpoint registers.
73 Neither of these values may exceed the width of dr_changed_t
76 #define AARCH64_HBP_MAX_NUM 16
77 #define AARCH64_HWP_MAX_NUM 16
79 /* Alignment requirement in bytes for addresses written to
80 hardware breakpoint and watchpoint value registers.
82 A ptrace call attempting to set an address that does not meet the
83 alignment criteria will fail. Limited support has been provided in
84 this port for unaligned watchpoints, such that from a GDB user
85 perspective, an unaligned watchpoint may be requested.
87 This is achieved by minimally enlarging the watched area to meet the
88 alignment requirement, and if necessary, splitting the watchpoint
89 over several hardware watchpoint registers. */
91 #define AARCH64_HBP_ALIGNMENT 4
92 #define AARCH64_HWP_ALIGNMENT 8
94 /* The maximum length of a memory region that can be watched by one
95 hardware watchpoint register. */
97 #define AARCH64_HWP_MAX_LEN_PER_REG 8
99 /* ptrace hardware breakpoint resource info is formatted as follows:
102 +---------------+--------------+---------------+---------------+
103 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
104 +---------------+--------------+---------------+---------------+ */
107 /* Macros to extract fields from the hardware debug information word. */
108 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
109 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
111 /* Macro for the expected version of the ARMv8-A debug architecture. */
112 #define AARCH64_DEBUG_ARCH_V8 0x6
114 /* Number of hardware breakpoints/watchpoints the target supports.
115 They are initialized with values obtained via the ptrace calls
116 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
118 static int aarch64_num_bp_regs;
119 static int aarch64_num_wp_regs;
121 /* Debugging of hardware breakpoint/watchpoint support. */
123 static int debug_hw_points;
125 /* Each bit of a variable of this type is used to indicate whether a
126 hardware breakpoint or watchpoint setting has been changed since
129 Bit N corresponds to the Nth hardware breakpoint or watchpoint
130 setting which is managed in aarch64_debug_reg_state, where N is
131 valid between 0 and the total number of the hardware breakpoint or
132 watchpoint debug registers minus 1.
134 When bit N is 1, the corresponding breakpoint or watchpoint setting
135 has changed, and therefore the corresponding hardware debug
136 register needs to be updated via the ptrace interface.
138 In the per-thread arch-specific data area, we define two such
139 variables for per-thread hardware breakpoint and watchpoint
140 settings respectively.
142 This type is part of the mechanism which helps reduce the number of
143 ptrace calls to the kernel, i.e. avoid asking the kernel to write
144 to the debug registers with unchanged values. */
146 typedef unsigned LONGEST dr_changed_t;
148 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
150 #define DR_MARK_ALL_CHANGED(x, m) \
153 gdb_assert (sizeof ((x)) * 8 >= (m)); \
154 (x) = (((dr_changed_t)1 << (m)) - 1); \
157 #define DR_MARK_N_CHANGED(x, n) \
160 (x) |= ((dr_changed_t)1 << (n)); \
163 #define DR_CLEAR_CHANGED(x) \
169 #define DR_HAS_CHANGED(x) ((x) != 0)
170 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
172 /* Structure for managing the hardware breakpoint/watchpoint resources.
173 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
174 content, and DR_REF_COUNT_* counts the numbers of references to the
175 corresponding bp/wp, by which way the limited hardware resources
176 are not wasted on duplicated bp/wp settings (though so far gdb has
177 done a good job by not sending duplicated bp/wp requests). */
179 struct aarch64_debug_reg_state
181 /* hardware breakpoint */
182 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
183 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
184 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
186 /* hardware watchpoint */
187 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
188 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
189 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
192 /* Per-process data. We don't bind this to a per-inferior registry
193 because of targets like x86 GNU/Linux that need to keep track of
194 processes that aren't bound to any inferior (e.g., fork children,
197 struct aarch64_process_info
200 struct aarch64_process_info *next;
202 /* The process identifier. */
205 /* Copy of aarch64 hardware debug registers. */
206 struct aarch64_debug_reg_state state;
209 static struct aarch64_process_info *aarch64_process_list = NULL;
211 /* Find process data for process PID. */
213 static struct aarch64_process_info *
214 aarch64_find_process_pid (pid_t pid)
216 struct aarch64_process_info *proc;
218 for (proc = aarch64_process_list; proc; proc = proc->next)
219 if (proc->pid == pid)
225 /* Add process data for process PID. Returns newly allocated info
228 static struct aarch64_process_info *
229 aarch64_add_process (pid_t pid)
231 struct aarch64_process_info *proc;
233 proc = xcalloc (1, sizeof (*proc));
236 proc->next = aarch64_process_list;
237 aarch64_process_list = proc;
242 /* Get data specific info for process PID, creating it if necessary.
243 Never returns NULL. */
245 static struct aarch64_process_info *
246 aarch64_process_info_get (pid_t pid)
248 struct aarch64_process_info *proc;
250 proc = aarch64_find_process_pid (pid);
252 proc = aarch64_add_process (pid);
257 /* Called whenever GDB is no longer debugging process PID. It deletes
258 data structures that keep track of debug register state. */
261 aarch64_forget_process (pid_t pid)
263 struct aarch64_process_info *proc, **proc_link;
265 proc = aarch64_process_list;
266 proc_link = &aarch64_process_list;
270 if (proc->pid == pid)
272 *proc_link = proc->next;
278 proc_link = &proc->next;
283 /* Get debug registers state for process PID. */
285 static struct aarch64_debug_reg_state *
286 aarch64_get_debug_reg_state (pid_t pid)
288 return &aarch64_process_info_get (pid)->state;
291 /* Per-thread arch-specific data we want to keep. */
295 /* When bit N is 1, it indicates the Nth hardware breakpoint or
296 watchpoint register pair needs to be updated when the thread is
297 resumed; see aarch64_linux_prepare_to_resume. */
298 dr_changed_t dr_changed_bp;
299 dr_changed_t dr_changed_wp;
302 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
303 registers with data from *STATE. */
306 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
307 int tid, int watchpoint)
311 struct user_hwdebug_state regs;
312 const CORE_ADDR *addr;
313 const unsigned int *ctrl;
315 memset (®s, 0, sizeof (regs));
316 iov.iov_base = ®s;
317 iov.iov_len = sizeof (regs);
318 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
319 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
320 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
322 for (i = 0; i < count; i++)
324 regs.dbg_regs[i].addr = addr[i];
325 regs.dbg_regs[i].ctrl = ctrl[i];
328 if (ptrace (PTRACE_SETREGSET, tid,
329 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
331 error (_("Unexpected error setting hardware debug registers"));
334 struct aarch64_dr_update_callback_param
340 /* Callback for iterate_over_lwps. Records the
341 information about the change of one hardware breakpoint/watchpoint
342 setting for the thread LWP.
343 The information is passed in via PTR.
344 N.B. The actual updating of hardware debug registers is not
345 carried out until the moment the thread is resumed. */
348 debug_reg_change_callback (struct lwp_info *lwp, void *ptr)
350 struct aarch64_dr_update_callback_param *param_p
351 = (struct aarch64_dr_update_callback_param *) ptr;
352 int pid = get_thread_id (lwp->ptid);
353 int idx = param_p->idx;
354 int is_watchpoint = param_p->is_watchpoint;
355 struct arch_lwp_info *info = lwp->arch_private;
356 dr_changed_t *dr_changed_ptr;
357 dr_changed_t dr_changed;
360 info = lwp->arch_private = XCNEW (struct arch_lwp_info);
364 fprintf_unfiltered (gdb_stdlog,
365 "debug_reg_change_callback: \n\tOn entry:\n");
366 fprintf_unfiltered (gdb_stdlog,
367 "\tpid%d, dr_changed_bp=0x%s, "
368 "dr_changed_wp=0x%s\n",
369 pid, phex (info->dr_changed_bp, 8),
370 phex (info->dr_changed_wp, 8));
373 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
374 : &info->dr_changed_bp;
375 dr_changed = *dr_changed_ptr;
378 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
379 : aarch64_num_bp_regs)));
381 /* The actual update is done later just before resuming the lwp,
382 we just mark that one register pair needs updating. */
383 DR_MARK_N_CHANGED (dr_changed, idx);
384 *dr_changed_ptr = dr_changed;
386 /* If the lwp isn't stopped, force it to momentarily pause, so
387 we can update its debug registers. */
389 linux_stop_lwp (lwp);
393 fprintf_unfiltered (gdb_stdlog,
394 "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, "
395 "dr_changed_wp=0x%s\n",
396 pid, phex (info->dr_changed_bp, 8),
397 phex (info->dr_changed_wp, 8));
400 /* Continue the iteration. */
404 /* Notify each thread that their IDXth breakpoint/watchpoint register
405 pair needs to be updated. The message will be recorded in each
406 thread's arch-specific data area, the actual updating will be done
407 when the thread is resumed. */
410 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
411 int is_watchpoint, unsigned int idx)
413 struct aarch64_dr_update_callback_param param;
414 ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid));
416 param.is_watchpoint = is_watchpoint;
419 iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) ¶m);
422 /* Print the values of the cached breakpoint/watchpoint registers. */
425 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
426 const char *func, CORE_ADDR addr,
431 fprintf_unfiltered (gdb_stdlog, "%s", func);
433 fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)",
434 (unsigned long) addr, len,
435 type == hw_write ? "hw-write-watchpoint"
436 : (type == hw_read ? "hw-read-watchpoint"
437 : (type == hw_access ? "hw-access-watchpoint"
438 : (type == hw_execute ? "hw-breakpoint"
440 fprintf_unfiltered (gdb_stdlog, ":\n");
442 fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n");
443 for (i = 0; i < aarch64_num_bp_regs; i++)
444 fprintf_unfiltered (gdb_stdlog,
445 "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
446 i, state->dr_addr_bp[i],
447 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
449 fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n");
450 for (i = 0; i < aarch64_num_wp_regs; i++)
451 fprintf_unfiltered (gdb_stdlog,
452 "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
453 i, state->dr_addr_wp[i],
454 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
457 /* Fill GDB's register array with the general-purpose register values
458 from the current thread. */
461 fetch_gregs_from_thread (struct regcache *regcache)
467 tid = get_thread_id (inferior_ptid);
469 iovec.iov_base = ®s;
470 iovec.iov_len = sizeof (regs);
472 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
474 perror_with_name (_("Unable to fetch general registers."));
476 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
477 regcache_raw_supply (regcache, regno,
478 (char *) ®s[regno - AARCH64_X0_REGNUM]);
481 /* Store to the current thread the valid general-purpose register
482 values in the GDB's register array. */
485 store_gregs_to_thread (const struct regcache *regcache)
491 tid = get_thread_id (inferior_ptid);
493 iovec.iov_base = ®s;
494 iovec.iov_len = sizeof (regs);
496 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
498 perror_with_name (_("Unable to fetch general registers."));
500 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
501 if (REG_VALID == regcache_register_status (regcache, regno))
502 regcache_raw_collect (regcache, regno,
503 (char *) ®s[regno - AARCH64_X0_REGNUM]);
505 ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
507 perror_with_name (_("Unable to store general registers."));
510 /* Fill GDB's register array with the fp/simd register values
511 from the current thread. */
514 fetch_fpregs_from_thread (struct regcache *regcache)
520 tid = get_thread_id (inferior_ptid);
522 iovec.iov_base = ®s;
523 iovec.iov_len = sizeof (regs);
525 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
527 perror_with_name (_("Unable to fetch FP/SIMD registers."));
529 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
530 regcache_raw_supply (regcache, regno,
531 (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
533 regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
534 regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
537 /* Store to the current thread the valid fp/simd register
538 values in the GDB's register array. */
541 store_fpregs_to_thread (const struct regcache *regcache)
547 tid = get_thread_id (inferior_ptid);
549 iovec.iov_base = ®s;
550 iovec.iov_len = sizeof (regs);
552 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
554 perror_with_name (_("Unable to fetch FP/SIMD registers."));
556 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
557 if (REG_VALID == regcache_register_status (regcache, regno))
558 regcache_raw_collect (regcache, regno,
559 (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
561 if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM))
562 regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
563 if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM))
564 regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
566 ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
568 perror_with_name (_("Unable to store FP/SIMD registers."));
571 /* Implement the "to_fetch_register" target_ops method. */
574 aarch64_linux_fetch_inferior_registers (struct target_ops *ops,
575 struct regcache *regcache,
580 fetch_gregs_from_thread (regcache);
581 fetch_fpregs_from_thread (regcache);
583 else if (regno < AARCH64_V0_REGNUM)
584 fetch_gregs_from_thread (regcache);
586 fetch_fpregs_from_thread (regcache);
589 /* Implement the "to_store_register" target_ops method. */
592 aarch64_linux_store_inferior_registers (struct target_ops *ops,
593 struct regcache *regcache,
598 store_gregs_to_thread (regcache);
599 store_fpregs_to_thread (regcache);
601 else if (regno < AARCH64_V0_REGNUM)
602 store_gregs_to_thread (regcache);
604 store_fpregs_to_thread (regcache);
607 /* Fill register REGNO (if it is a general-purpose register) in
608 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
609 do this for all registers. */
612 fill_gregset (const struct regcache *regcache,
613 gdb_gregset_t *gregsetp, int regno)
615 gdb_byte *gregs_buf = (gdb_byte *) gregsetp;
618 for (i = AARCH64_X0_REGNUM; i <= AARCH64_CPSR_REGNUM; i++)
619 if (regno == -1 || regno == i)
620 regcache_raw_collect (regcache, i,
621 gregs_buf + X_REGISTER_SIZE
622 * (i - AARCH64_X0_REGNUM));
625 /* Fill GDB's register array with the general-purpose register values
629 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
631 aarch64_linux_supply_gregset (regcache, (const gdb_byte *) gregsetp);
634 /* Fill register REGNO (if it is a floating-point register) in
635 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
636 do this for all registers. */
639 fill_fpregset (const struct regcache *regcache,
640 gdb_fpregset_t *fpregsetp, int regno)
642 gdb_byte *fpregs_buf = (gdb_byte *) fpregsetp;
645 for (i = AARCH64_V0_REGNUM; i <= AARCH64_V31_REGNUM; i++)
646 if (regno == -1 || regno == i)
647 regcache_raw_collect (regcache, i,
648 fpregs_buf + V_REGISTER_SIZE
649 * (i - AARCH64_V0_REGNUM));
651 if (regno == -1 || regno == AARCH64_FPSR_REGNUM)
652 regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM,
653 fpregs_buf + V_REGISTER_SIZE * 32);
655 if (regno == -1 || regno == AARCH64_FPCR_REGNUM)
656 regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM,
657 fpregs_buf + V_REGISTER_SIZE * 32 + 4);
660 /* Fill GDB's register array with the floating-point register values
664 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
666 aarch64_linux_supply_fpregset (regcache, (const gdb_byte *) fpregsetp);
669 /* Called when resuming a thread.
670 The hardware debug registers are updated when there is any change. */
673 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
675 struct arch_lwp_info *info = lwp->arch_private;
677 /* NULL means this is the main thread still going through the shell,
678 or, no watchpoint has been set yet. In that case, there's
683 if (DR_HAS_CHANGED (info->dr_changed_bp)
684 || DR_HAS_CHANGED (info->dr_changed_wp))
686 int tid = GET_LWP (lwp->ptid);
687 struct aarch64_debug_reg_state *state
688 = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid));
691 fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid);
694 if (DR_HAS_CHANGED (info->dr_changed_wp))
696 aarch64_linux_set_debug_regs (state, tid, 1);
697 DR_CLEAR_CHANGED (info->dr_changed_wp);
701 if (DR_HAS_CHANGED (info->dr_changed_bp))
703 aarch64_linux_set_debug_regs (state, tid, 0);
704 DR_CLEAR_CHANGED (info->dr_changed_bp);
710 aarch64_linux_new_thread (struct lwp_info *lp)
712 struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
714 /* Mark that all the hardware breakpoint/watchpoint register pairs
715 for this thread need to be initialized. */
716 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
717 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
719 lp->arch_private = info;
722 /* linux_nat_new_fork hook. */
725 aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid)
728 struct aarch64_debug_reg_state *parent_state;
729 struct aarch64_debug_reg_state *child_state;
731 /* NULL means no watchpoint has ever been set in the parent. In
732 that case, there's nothing to do. */
733 if (parent->arch_private == NULL)
736 /* GDB core assumes the child inherits the watchpoints/hw
737 breakpoints of the parent, and will remove them all from the
738 forked off process. Copy the debug registers mirrors into the
739 new process so that all breakpoints and watchpoints can be
742 parent_pid = ptid_get_pid (parent->ptid);
743 parent_state = aarch64_get_debug_reg_state (parent_pid);
744 child_state = aarch64_get_debug_reg_state (child_pid);
745 *child_state = *parent_state;
749 /* Called by libthread_db. Returns a pointer to the thread local
750 storage (or its descriptor). */
753 ps_get_thread_area (const struct ps_prochandle *ph,
754 lwpid_t lwpid, int idx, void **base)
759 iovec.iov_base = ®
760 iovec.iov_len = sizeof (reg);
762 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
765 /* IDX is the bias from the thread pointer to the beginning of the
766 thread descriptor. It has to be subtracted due to implementation
767 quirks in libthread_db. */
768 *base = (void *) (reg - idx);
774 /* Get the hardware debug register capacity information. */
777 aarch64_linux_get_debug_reg_capacity (void)
781 struct user_hwdebug_state dreg_state;
783 tid = get_thread_id (inferior_ptid);
784 iov.iov_base = &dreg_state;
785 iov.iov_len = sizeof (dreg_state);
787 /* Get hardware watchpoint register info. */
788 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
789 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
791 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
792 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
794 warning (_("Unexpected number of hardware watchpoint registers"
795 " reported by ptrace, got %d, expected %d."),
796 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
797 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
802 warning (_("Unable to determine the number of hardware watchpoints"
804 aarch64_num_wp_regs = 0;
807 /* Get hardware breakpoint register info. */
808 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
809 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
811 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
812 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
814 warning (_("Unexpected number of hardware breakpoint registers"
815 " reported by ptrace, got %d, expected %d."),
816 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
817 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
822 warning (_("Unable to determine the number of hardware breakpoints"
824 aarch64_num_bp_regs = 0;
828 static void (*super_post_startup_inferior) (ptid_t ptid);
830 /* Implement the "to_post_startup_inferior" target_ops method. */
833 aarch64_linux_child_post_startup_inferior (ptid_t ptid)
835 aarch64_forget_process (ptid_get_pid (ptid));
836 aarch64_linux_get_debug_reg_capacity ();
837 super_post_startup_inferior (ptid);
840 /* Implement the "to_read_description" target_ops method. */
842 static const struct target_desc *
843 aarch64_linux_read_description (struct target_ops *ops)
845 initialize_tdesc_aarch64 ();
846 return tdesc_aarch64;
849 /* Given the (potentially unaligned) watchpoint address in ADDR and
850 length in LEN, return the aligned address and aligned length in
851 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
852 aligned address and length will be valid values to write to the
853 hardware watchpoint value and control registers.
855 The given watchpoint may get truncated if more than one hardware
856 register is needed to cover the watched region. *NEXT_ADDR_P
857 and *NEXT_LEN_P, if non-NULL, will return the address and length
858 of the remaining part of the watchpoint (which can be processed
859 by calling this routine again to generate another aligned address
862 See the comment above the function of the same name in
863 gdbserver/linux-aarch64-low.c for more information. */
866 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
867 int *aligned_len_p, CORE_ADDR *next_addr_p,
872 CORE_ADDR aligned_addr;
873 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
874 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
876 /* As assumed by the algorithm. */
877 gdb_assert (alignment == max_wp_len);
882 /* Address to be put into the hardware watchpoint value register
884 offset = addr & (alignment - 1);
885 aligned_addr = addr - offset;
887 gdb_assert (offset >= 0 && offset < alignment);
888 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
889 gdb_assert (offset + len > 0);
891 if (offset + len >= max_wp_len)
893 /* Need more than one watchpoint registers; truncate it at the
894 alignment boundary. */
895 aligned_len = max_wp_len;
896 len -= (max_wp_len - offset);
897 addr += (max_wp_len - offset);
898 gdb_assert ((addr & (alignment - 1)) == 0);
902 /* Find the smallest valid length that is large enough to
903 accommodate this watchpoint. */
904 static const unsigned char
905 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
906 { 1, 2, 4, 4, 8, 8, 8, 8 };
908 aligned_len = aligned_len_array[offset + len - 1];
914 *aligned_addr_p = aligned_addr;
916 *aligned_len_p = aligned_len;
923 /* Returns the number of hardware watchpoints of type TYPE that we can
924 set. Value is positive if we can set CNT watchpoints, zero if
925 setting watchpoints of type TYPE is not supported, and negative if
926 CNT is more than the maximum number of watchpoints of type TYPE
927 that we can support. TYPE is one of bp_hardware_watchpoint,
928 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
929 CNT is the number of such watchpoints used so far (including this
930 one). OTHERTYPE is non-zero if other types of watchpoints are
933 We always return 1 here because we don't have enough information
934 about possible overlap of addresses that they want to watch. As an
935 extreme example, consider the case where all the watchpoints watch
936 the same address and the same region length: then we can handle a
937 virtually unlimited number of watchpoints, due to debug register
938 sharing implemented via reference counts. */
941 aarch64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
946 /* ptrace expects control registers to be formatted as follows:
949 +--------------------------------+----------+------+------+----+
950 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
951 +--------------------------------+----------+------+------+----+
953 The TYPE field is ignored for breakpoints. */
955 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
956 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
958 /* Utility function that returns the length in bytes of a watchpoint
959 according to the content of a hardware debug control register CTRL.
960 Note that the kernel currently only supports the following Byte
961 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
962 that for a hardware watchpoint, its valid length can only be 1
963 byte, 2 bytes, 4 bytes or 8 bytes. */
965 static inline unsigned int
966 aarch64_watchpoint_length (unsigned int ctrl)
968 switch (DR_CONTROL_LENGTH (ctrl))
983 /* Given the hardware breakpoint or watchpoint type TYPE and its
984 length LEN, return the expected encoding for a hardware
985 breakpoint/watchpoint control register. */
988 aarch64_point_encode_ctrl_reg (int type, int len)
990 unsigned int ctrl, ttype;
1008 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
1012 /* length bitmask */
1013 ctrl |= ((1 << len) - 1) << 5;
1014 /* enabled at el0 */
1015 ctrl |= (2 << 1) | 1;
1020 /* Addresses to be written to the hardware breakpoint and watchpoint
1021 value registers need to be aligned; the alignment is 4-byte and
1022 8-type respectively. Linux kernel rejects any non-aligned address
1023 it receives from the related ptrace call. Furthermore, the kernel
1024 currently only supports the following Byte Address Select (BAS)
1025 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
1026 watchpoint to be accepted by the kernel (via ptrace call), its
1027 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
1028 Despite these limitations, the unaligned watchpoint is supported in
1031 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
1034 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
1036 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
1037 : AARCH64_HBP_ALIGNMENT;
1039 if (addr & (alignment - 1))
1042 if (len != 8 && len != 4 && len != 2 && len != 1)
1048 /* Record the insertion of one breakpoint/watchpoint, as represented
1049 by ADDR and CTRL, in the cached debug register state area *STATE. */
1052 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
1053 int type, CORE_ADDR addr, int len)
1055 int i, idx, num_regs, is_watchpoint;
1056 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
1057 CORE_ADDR *dr_addr_p;
1059 /* Set up state pointers. */
1060 is_watchpoint = (type != hw_execute);
1061 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
1064 num_regs = aarch64_num_wp_regs;
1065 dr_addr_p = state->dr_addr_wp;
1066 dr_ctrl_p = state->dr_ctrl_wp;
1067 dr_ref_count = state->dr_ref_count_wp;
1071 num_regs = aarch64_num_bp_regs;
1072 dr_addr_p = state->dr_addr_bp;
1073 dr_ctrl_p = state->dr_ctrl_bp;
1074 dr_ref_count = state->dr_ref_count_bp;
1077 ctrl = aarch64_point_encode_ctrl_reg (type, len);
1079 /* Find an existing or free register in our cache. */
1081 for (i = 0; i < num_regs; ++i)
1083 if ((dr_ctrl_p[i] & 1) == 0)
1085 gdb_assert (dr_ref_count[i] == 0);
1087 /* no break; continue hunting for an existing one. */
1089 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
1091 gdb_assert (dr_ref_count[i] != 0);
1101 /* Update our cache. */
1102 if ((dr_ctrl_p[idx] & 1) == 0)
1105 dr_addr_p[idx] = addr;
1106 dr_ctrl_p[idx] = ctrl;
1107 dr_ref_count[idx] = 1;
1108 /* Notify the change. */
1109 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
1113 /* existing entry */
1114 dr_ref_count[idx]++;
1120 /* Record the removal of one breakpoint/watchpoint, as represented by
1121 ADDR and CTRL, in the cached debug register state area *STATE. */
1124 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
1125 int type, CORE_ADDR addr, int len)
1127 int i, num_regs, is_watchpoint;
1128 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
1129 CORE_ADDR *dr_addr_p;
1131 /* Set up state pointers. */
1132 is_watchpoint = (type != hw_execute);
1133 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
1136 num_regs = aarch64_num_wp_regs;
1137 dr_addr_p = state->dr_addr_wp;
1138 dr_ctrl_p = state->dr_ctrl_wp;
1139 dr_ref_count = state->dr_ref_count_wp;
1143 num_regs = aarch64_num_bp_regs;
1144 dr_addr_p = state->dr_addr_bp;
1145 dr_ctrl_p = state->dr_ctrl_bp;
1146 dr_ref_count = state->dr_ref_count_bp;
1149 ctrl = aarch64_point_encode_ctrl_reg (type, len);
1151 /* Find the entry that matches the ADDR and CTRL. */
1152 for (i = 0; i < num_regs; ++i)
1153 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
1155 gdb_assert (dr_ref_count[i] != 0);
1163 /* Clear our cache. */
1164 if (--dr_ref_count[i] == 0)
1166 /* Clear the enable bit. */
1169 dr_ctrl_p[i] = ctrl;
1170 /* Notify the change. */
1171 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
1177 /* Implement insertion and removal of a single breakpoint. */
1180 aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert)
1182 struct aarch64_debug_reg_state *state;
1184 /* The hardware breakpoint on AArch64 should always be 4-byte
1186 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
1189 state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1192 return aarch64_dr_state_insert_one_point (state, type, addr, len);
1194 return aarch64_dr_state_remove_one_point (state, type, addr, len);
1197 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
1198 Return 0 on success, -1 on failure. */
1201 aarch64_linux_insert_hw_breakpoint (struct gdbarch *gdbarch,
1202 struct bp_target_info *bp_tgt)
1205 CORE_ADDR addr = bp_tgt->placed_address;
1207 const int type = hw_execute;
1209 if (debug_hw_points)
1212 "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1213 (unsigned long) addr, len);
1215 ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */);
1217 if (debug_hw_points > 1)
1219 struct aarch64_debug_reg_state *state
1220 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1222 aarch64_show_debug_reg_state (state,
1223 "insert_hw_watchpoint", addr, len, type);
1229 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
1230 Return 0 on success, -1 on failure. */
1233 aarch64_linux_remove_hw_breakpoint (struct gdbarch *gdbarch,
1234 struct bp_target_info *bp_tgt)
1237 CORE_ADDR addr = bp_tgt->placed_address;
1239 const int type = hw_execute;
1241 if (debug_hw_points)
1243 (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1244 (unsigned long) addr, len);
1246 ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */);
1248 if (debug_hw_points > 1)
1250 struct aarch64_debug_reg_state *state
1251 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1253 aarch64_show_debug_reg_state (state,
1254 "remove_hw_watchpoint", addr, len, type);
1260 /* This is essentially the same as aarch64_handle_breakpoint, apart
1261 from that it is an aligned watchpoint to be handled. */
1264 aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len,
1267 struct aarch64_debug_reg_state *state
1268 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1271 return aarch64_dr_state_insert_one_point (state, type, addr, len);
1273 return aarch64_dr_state_remove_one_point (state, type, addr, len);
1276 /* Insert/remove unaligned watchpoint by calling
1277 aarch64_align_watchpoint repeatedly until the whole watched region,
1278 as represented by ADDR and LEN, has been properly aligned and ready
1279 to be written to one or more hardware watchpoint registers.
1280 IS_INSERT indicates whether this is an insertion or a deletion.
1281 Return 0 if succeed. */
1284 aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len,
1287 struct aarch64_debug_reg_state *state
1288 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1292 CORE_ADDR aligned_addr;
1293 int aligned_len, ret;
1295 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
1299 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
1302 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
1305 if (debug_hw_points)
1306 fprintf_unfiltered (gdb_stdlog,
1307 "handle_unaligned_watchpoint: is_insert: %d\n"
1308 " aligned_addr: 0x%08lx, aligned_len: %d\n"
1309 " next_addr: 0x%08lx, next_len: %d\n",
1310 is_insert, aligned_addr, aligned_len, addr, len);
1319 /* Implements insertion and removal of a single watchpoint. */
1322 aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert)
1324 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
1325 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
1327 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
1330 /* Implement the "to_insert_watchpoint" target_ops method.
1332 Insert a watchpoint to watch a memory region which starts at
1333 address ADDR and whose length is LEN bytes. Watch memory accesses
1334 of the type TYPE. Return 0 on success, -1 on failure. */
1337 aarch64_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
1338 struct expression *cond)
1342 if (debug_hw_points)
1343 fprintf_unfiltered (gdb_stdlog,
1344 "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1345 (unsigned long) addr, len);
1347 gdb_assert (type != hw_execute);
1349 ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */);
1351 if (debug_hw_points > 1)
1353 struct aarch64_debug_reg_state *state
1354 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1356 aarch64_show_debug_reg_state (state,
1357 "insert_watchpoint", addr, len, type);
1363 /* Implement the "to_remove_watchpoint" target_ops method.
1364 Remove a watchpoint that watched the memory region which starts at
1365 address ADDR, whose length is LEN bytes, and for accesses of the
1366 type TYPE. Return 0 on success, -1 on failure. */
1369 aarch64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
1370 struct expression *cond)
1374 if (debug_hw_points)
1375 fprintf_unfiltered (gdb_stdlog,
1376 "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1377 (unsigned long) addr, len);
1379 gdb_assert (type != hw_execute);
1381 ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */);
1383 if (debug_hw_points > 1)
1385 struct aarch64_debug_reg_state *state
1386 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1388 aarch64_show_debug_reg_state (state,
1389 "remove_watchpoint", addr, len, type);
1395 /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */
1398 aarch64_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1400 CORE_ADDR aligned_addr;
1402 /* Can not set watchpoints for zero or negative lengths. */
1406 /* Must have hardware watchpoint debug register(s). */
1407 if (aarch64_num_wp_regs == 0)
1410 /* We support unaligned watchpoint address and arbitrary length,
1411 as long as the size of the whole watched area after alignment
1412 doesn't exceed size of the total area that all watchpoint debug
1413 registers can watch cooperatively.
1415 This is a very relaxed rule, but unfortunately there are
1416 limitations, e.g. false-positive hits, due to limited support of
1417 hardware debug registers in the kernel. See comment above
1418 aarch64_align_watchpoint for more information. */
1420 aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1);
1421 if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG
1425 /* All tests passed so we are likely to be able to set the watchpoint.
1426 The reason that it is 'likely' rather than 'must' is because
1427 we don't check the current usage of the watchpoint registers, and
1428 there may not be enough registers available for this watchpoint.
1429 Ideally we should check the cached debug register state, however
1430 the checking is costly. */
1434 /* Implement the "to_stopped_data_address" target_ops method. */
1437 aarch64_linux_stopped_data_address (struct target_ops *target,
1442 struct aarch64_debug_reg_state *state;
1444 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
1447 /* This must be a hardware breakpoint. */
1448 if (siginfo.si_signo != SIGTRAP
1449 || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
1452 /* Check if the address matches any watched address. */
1453 state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1454 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1456 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1457 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1458 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1460 if (state->dr_ref_count_wp[i]
1461 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1462 && addr_trap >= addr_watch
1463 && addr_trap < addr_watch + len)
1465 *addr_p = addr_trap;
1473 /* Implement the "to_stopped_by_watchpoint" target_ops method. */
1476 aarch64_linux_stopped_by_watchpoint (void)
1480 return aarch64_linux_stopped_data_address (¤t_target, &addr);
1483 /* Implement the "to_watchpoint_addr_within_range" target_ops method. */
1486 aarch64_linux_watchpoint_addr_within_range (struct target_ops *target,
1488 CORE_ADDR start, int length)
1490 return start <= addr && start + length - 1 >= addr;
1493 /* Define AArch64 maintenance commands. */
1496 add_show_debug_regs_command (void)
1498 /* A maintenance command to enable printing the internal DRi mirror
1500 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
1501 &debug_hw_points, _("\
1502 Set whether to show variables that mirror the AArch64 debug registers."), _("\
1503 Show whether to show variables that mirror the AArch64 debug registers."), _("\
1504 Use \"on\" to enable, \"off\" to disable.\n\
1505 If enabled, the debug registers values are shown when GDB inserts\n\
1506 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1507 triggers a breakpoint or watchpoint."),
1510 &maintenance_set_cmdlist,
1511 &maintenance_show_cmdlist);
1514 /* -Wmissing-prototypes. */
1515 void _initialize_aarch64_linux_nat (void);
1518 _initialize_aarch64_linux_nat (void)
1520 struct target_ops *t;
1522 /* Fill in the generic GNU/Linux methods. */
1523 t = linux_target ();
1525 add_show_debug_regs_command ();
1527 /* Add our register access methods. */
1528 t->to_fetch_registers = aarch64_linux_fetch_inferior_registers;
1529 t->to_store_registers = aarch64_linux_store_inferior_registers;
1531 t->to_read_description = aarch64_linux_read_description;
1533 t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint;
1534 t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint;
1535 t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint;
1536 t->to_region_ok_for_hw_watchpoint =
1537 aarch64_linux_region_ok_for_hw_watchpoint;
1538 t->to_insert_watchpoint = aarch64_linux_insert_watchpoint;
1539 t->to_remove_watchpoint = aarch64_linux_remove_watchpoint;
1540 t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint;
1541 t->to_stopped_data_address = aarch64_linux_stopped_data_address;
1542 t->to_watchpoint_addr_within_range =
1543 aarch64_linux_watchpoint_addr_within_range;
1545 /* Override the GNU/Linux inferior startup hook. */
1546 super_post_startup_inferior = t->to_post_startup_inferior;
1547 t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior;
1549 /* Register the target. */
1550 linux_nat_add_target (t);
1551 linux_nat_set_new_thread (t, aarch64_linux_new_thread);
1552 linux_nat_set_new_fork (t, aarch64_linux_new_fork);
1553 linux_nat_set_forget_process (t, aarch64_forget_process);
1554 linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume);